diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl index c4ae7a31d..e259361f4 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl @@ -80,6 +80,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params TDMA_BER_ENABLE "0" + # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {25.78125} diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl index bc964128c..ed9756684 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl @@ -80,6 +80,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params TDMA_BER_ENABLE "0" + # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {10.3125} diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl index ed9e41f1c..70e7321be 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl @@ -80,6 +80,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params TDMA_BER_ENABLE "1" + # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {25.78125} diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v index e6113d7ed..8f65cdfb0 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v @@ -52,6 +52,9 @@ module fpga # parameter GIT_HASH = 32'hdce357bf, parameter RELEASE_INFO = 32'h00000000, + // Board configuration + parameter TDMA_BER_ENABLE = 0, + // Structural configuration parameter IF_COUNT = 2, parameter PORTS_PER_IF = 1, @@ -1364,6 +1367,9 @@ fpga_core #( .GIT_HASH(GIT_HASH), .RELEASE_INFO(RELEASE_INFO), + // Board configuration + .TDMA_BER_ENABLE(TDMA_BER_ENABLE), + // Structural configuration .IF_COUNT(IF_COUNT), .PORTS_PER_IF(PORTS_PER_IF), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v index c9bbec2fd..80cca4600 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v @@ -52,6 +52,9 @@ module fpga_core # parameter GIT_HASH = 32'hdce357bf, parameter RELEASE_INFO = 32'h00000000, + // Board configuration + parameter TDMA_BER_ENABLE = 0, + // Structural configuration parameter IF_COUNT = 2, parameter PORTS_PER_IF = 1, @@ -854,53 +857,80 @@ always @(posedge ptp_clk) begin pps_led_reg <= pps_led_counter_reg > 0; end -// BER tester -tdma_ber #( - .COUNT(8), - .INDEX_WIDTH(6), - .SLICE_WIDTH(5), - .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_ADDR_WIDTH(8+6+$clog2(8)), - .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .SCHEDULE_START_S(0), - .SCHEDULE_START_NS(0), - .SCHEDULE_PERIOD_S(0), - .SCHEDULE_PERIOD_NS(1000000), - .TIMESLOT_PERIOD_S(0), - .TIMESLOT_PERIOD_NS(100000), - .ACTIVE_PERIOD_S(0), - .ACTIVE_PERIOD_NS(90000) -) -tdma_ber_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - .phy_tx_clk({qsfp_1_tx_clk_3, qsfp_1_tx_clk_2, qsfp_1_tx_clk_1, qsfp_1_tx_clk_0, qsfp_0_tx_clk_3, qsfp_0_tx_clk_2, qsfp_0_tx_clk_1, qsfp_0_tx_clk_0}), - .phy_rx_clk({qsfp_1_rx_clk_3, qsfp_1_rx_clk_2, qsfp_1_rx_clk_1, qsfp_1_rx_clk_0, qsfp_0_rx_clk_3, qsfp_0_rx_clk_2, qsfp_0_rx_clk_1, qsfp_0_rx_clk_0}), - .phy_rx_error_count({qsfp_1_rx_error_count_3, qsfp_1_rx_error_count_2, qsfp_1_rx_error_count_1, qsfp_1_rx_error_count_0, qsfp_0_rx_error_count_3, qsfp_0_rx_error_count_2, qsfp_0_rx_error_count_1, qsfp_0_rx_error_count_0}), - .phy_tx_prbs31_enable({qsfp_1_tx_prbs31_enable_3, qsfp_1_tx_prbs31_enable_2, qsfp_1_tx_prbs31_enable_1, qsfp_1_tx_prbs31_enable_0, qsfp_0_tx_prbs31_enable_3, qsfp_0_tx_prbs31_enable_2, qsfp_0_tx_prbs31_enable_1, qsfp_0_tx_prbs31_enable_0}), - .phy_rx_prbs31_enable({qsfp_1_rx_prbs31_enable_3, qsfp_1_rx_prbs31_enable_2, qsfp_1_rx_prbs31_enable_1, qsfp_1_rx_prbs31_enable_0, qsfp_0_rx_prbs31_enable_3, qsfp_0_rx_prbs31_enable_2, qsfp_0_rx_prbs31_enable_1, qsfp_0_rx_prbs31_enable_0}), - .s_axil_awaddr(axil_csr_awaddr), - .s_axil_awprot(axil_csr_awprot), - .s_axil_awvalid(axil_csr_awvalid), - .s_axil_awready(axil_csr_awready), - .s_axil_wdata(axil_csr_wdata), - .s_axil_wstrb(axil_csr_wstrb), - .s_axil_wvalid(axil_csr_wvalid), - .s_axil_wready(axil_csr_wready), - .s_axil_bresp(axil_csr_bresp), - .s_axil_bvalid(axil_csr_bvalid), - .s_axil_bready(axil_csr_bready), - .s_axil_araddr(axil_csr_araddr), - .s_axil_arprot(axil_csr_arprot), - .s_axil_arvalid(axil_csr_arvalid), - .s_axil_arready(axil_csr_arready), - .s_axil_rdata(axil_csr_rdata), - .s_axil_rresp(axil_csr_rresp), - .s_axil_rvalid(axil_csr_rvalid), - .s_axil_rready(axil_csr_rready), - .ptp_ts_96(ptp_sync_ts_96), - .ptp_ts_step(ptp_sync_ts_step) -); +generate + +if (TDMA_BER_ENABLE) begin + + // BER tester + tdma_ber #( + .COUNT(8), + .INDEX_WIDTH(6), + .SLICE_WIDTH(5), + .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .AXIL_ADDR_WIDTH(8+6+$clog2(8)), + .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .SCHEDULE_START_S(0), + .SCHEDULE_START_NS(0), + .SCHEDULE_PERIOD_S(0), + .SCHEDULE_PERIOD_NS(1000000), + .TIMESLOT_PERIOD_S(0), + .TIMESLOT_PERIOD_NS(100000), + .ACTIVE_PERIOD_S(0), + .ACTIVE_PERIOD_NS(90000) + ) + tdma_ber_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + .phy_tx_clk({qsfp_1_tx_clk_3, qsfp_1_tx_clk_2, qsfp_1_tx_clk_1, qsfp_1_tx_clk_0, qsfp_0_tx_clk_3, qsfp_0_tx_clk_2, qsfp_0_tx_clk_1, qsfp_0_tx_clk_0}), + .phy_rx_clk({qsfp_1_rx_clk_3, qsfp_1_rx_clk_2, qsfp_1_rx_clk_1, qsfp_1_rx_clk_0, qsfp_0_rx_clk_3, qsfp_0_rx_clk_2, qsfp_0_rx_clk_1, qsfp_0_rx_clk_0}), + .phy_rx_error_count({qsfp_1_rx_error_count_3, qsfp_1_rx_error_count_2, qsfp_1_rx_error_count_1, qsfp_1_rx_error_count_0, qsfp_0_rx_error_count_3, qsfp_0_rx_error_count_2, qsfp_0_rx_error_count_1, qsfp_0_rx_error_count_0}), + .phy_tx_prbs31_enable({qsfp_1_tx_prbs31_enable_3, qsfp_1_tx_prbs31_enable_2, qsfp_1_tx_prbs31_enable_1, qsfp_1_tx_prbs31_enable_0, qsfp_0_tx_prbs31_enable_3, qsfp_0_tx_prbs31_enable_2, qsfp_0_tx_prbs31_enable_1, qsfp_0_tx_prbs31_enable_0}), + .phy_rx_prbs31_enable({qsfp_1_rx_prbs31_enable_3, qsfp_1_rx_prbs31_enable_2, qsfp_1_rx_prbs31_enable_1, qsfp_1_rx_prbs31_enable_0, qsfp_0_rx_prbs31_enable_3, qsfp_0_rx_prbs31_enable_2, qsfp_0_rx_prbs31_enable_1, qsfp_0_rx_prbs31_enable_0}), + .s_axil_awaddr(axil_csr_awaddr), + .s_axil_awprot(axil_csr_awprot), + .s_axil_awvalid(axil_csr_awvalid), + .s_axil_awready(axil_csr_awready), + .s_axil_wdata(axil_csr_wdata), + .s_axil_wstrb(axil_csr_wstrb), + .s_axil_wvalid(axil_csr_wvalid), + .s_axil_wready(axil_csr_wready), + .s_axil_bresp(axil_csr_bresp), + .s_axil_bvalid(axil_csr_bvalid), + .s_axil_bready(axil_csr_bready), + .s_axil_araddr(axil_csr_araddr), + .s_axil_arprot(axil_csr_arprot), + .s_axil_arvalid(axil_csr_arvalid), + .s_axil_arready(axil_csr_arready), + .s_axil_rdata(axil_csr_rdata), + .s_axil_rresp(axil_csr_rresp), + .s_axil_rvalid(axil_csr_rvalid), + .s_axil_rready(axil_csr_rready), + .ptp_ts_96(ptp_sync_ts_96), + .ptp_ts_step(ptp_sync_ts_step) + ); + +end else begin + + assign qsfp_0_tx_prbs31_enable_0 = 1'b0; + assign qsfp_0_rx_prbs31_enable_0 = 1'b0; + assign qsfp_0_tx_prbs31_enable_1 = 1'b0; + assign qsfp_0_rx_prbs31_enable_1 = 1'b0; + assign qsfp_0_tx_prbs31_enable_2 = 1'b0; + assign qsfp_0_rx_prbs31_enable_2 = 1'b0; + assign qsfp_0_tx_prbs31_enable_3 = 1'b0; + assign qsfp_0_rx_prbs31_enable_3 = 1'b0; + assign qsfp_1_tx_prbs31_enable_0 = 1'b0; + assign qsfp_1_rx_prbs31_enable_0 = 1'b0; + assign qsfp_1_tx_prbs31_enable_1 = 1'b0; + assign qsfp_1_rx_prbs31_enable_1 = 1'b0; + assign qsfp_1_tx_prbs31_enable_2 = 1'b0; + assign qsfp_1_rx_prbs31_enable_2 = 1'b0; + assign qsfp_1_tx_prbs31_enable_3 = 1'b0; + assign qsfp_1_rx_prbs31_enable_3 = 1'b0; + +end + +endgenerate assign user_led_g[0] = 1'b1; assign user_led_g[1] = !pps_led_reg; @@ -1180,7 +1210,7 @@ mqnic_core_pcie_us #( .AXIL_CTRL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), .AXIL_IF_CTRL_ADDR_WIDTH(AXIL_IF_CTRL_ADDR_WIDTH), .AXIL_CSR_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .AXIL_CSR_PASSTHROUGH_ENABLE(1), + .AXIL_CSR_PASSTHROUGH_ENABLE(TDMA_BER_ENABLE), .RB_NEXT_PTR(RB_BASE_ADDR), // AXI lite interface configuration (application control) diff --git a/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl index 16a4eea6c..c1297a6dc 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl @@ -80,6 +80,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params TDMA_BER_ENABLE "0" + # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {25.78125} diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl index dcc7505cd..ad91b3473 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl @@ -80,6 +80,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params TDMA_BER_ENABLE "0" + # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {10.3125} diff --git a/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v index 28013bb20..e0fdb0f26 100644 --- a/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v @@ -52,6 +52,9 @@ module fpga # parameter GIT_HASH = 32'hdce357bf, parameter RELEASE_INFO = 32'h00000000, + // Board configuration + parameter TDMA_BER_ENABLE = 0, + // Structural configuration parameter IF_COUNT = 2, parameter PORTS_PER_IF = 1, @@ -1497,6 +1500,9 @@ fpga_core #( .GIT_HASH(GIT_HASH), .RELEASE_INFO(RELEASE_INFO), + // Board configuration + .TDMA_BER_ENABLE(TDMA_BER_ENABLE), + // Structural configuration .IF_COUNT(IF_COUNT), .PORTS_PER_IF(PORTS_PER_IF), diff --git a/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v index 749408d41..0bfd3383a 100644 --- a/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v @@ -52,6 +52,9 @@ module fpga_core # parameter GIT_HASH = 32'hdce357bf, parameter RELEASE_INFO = 32'h00000000, + // Board configuration + parameter TDMA_BER_ENABLE = 0, + // Structural configuration parameter IF_COUNT = 2, parameter PORTS_PER_IF = 1, @@ -865,54 +868,81 @@ always @(posedge ptp_clk) begin pps_led_reg <= pps_led_counter_reg > 0; end -// BER tester -tdma_ber #( - .COUNT(8), - .INDEX_WIDTH(6), - .SLICE_WIDTH(5), - .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_ADDR_WIDTH(8+6+$clog2(8)), - .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .SCHEDULE_START_S(0), - .SCHEDULE_START_NS(0), - .SCHEDULE_PERIOD_S(0), - .SCHEDULE_PERIOD_NS(1000000), - .TIMESLOT_PERIOD_S(0), - .TIMESLOT_PERIOD_NS(100000), - .ACTIVE_PERIOD_S(0), - .ACTIVE_PERIOD_NS(90000), - .PHY_PIPELINE(2) -) -tdma_ber_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - .phy_tx_clk({qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1, qsfp0_tx_clk_4, qsfp0_tx_clk_3, qsfp0_tx_clk_2, qsfp0_tx_clk_1}), - .phy_rx_clk({qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}), - .phy_rx_error_count({qsfp1_rx_error_count_4, qsfp1_rx_error_count_3, qsfp1_rx_error_count_2, qsfp1_rx_error_count_1, qsfp0_rx_error_count_4, qsfp0_rx_error_count_3, qsfp0_rx_error_count_2, qsfp0_rx_error_count_1}), - .phy_tx_prbs31_enable({qsfp1_tx_prbs31_enable_4, qsfp1_tx_prbs31_enable_3, qsfp1_tx_prbs31_enable_2, qsfp1_tx_prbs31_enable_1, qsfp0_tx_prbs31_enable_4, qsfp0_tx_prbs31_enable_3, qsfp0_tx_prbs31_enable_2, qsfp0_tx_prbs31_enable_1}), - .phy_rx_prbs31_enable({qsfp1_rx_prbs31_enable_4, qsfp1_rx_prbs31_enable_3, qsfp1_rx_prbs31_enable_2, qsfp1_rx_prbs31_enable_1, qsfp0_rx_prbs31_enable_4, qsfp0_rx_prbs31_enable_3, qsfp0_rx_prbs31_enable_2, qsfp0_rx_prbs31_enable_1}), - .s_axil_awaddr(axil_csr_awaddr), - .s_axil_awprot(axil_csr_awprot), - .s_axil_awvalid(axil_csr_awvalid), - .s_axil_awready(axil_csr_awready), - .s_axil_wdata(axil_csr_wdata), - .s_axil_wstrb(axil_csr_wstrb), - .s_axil_wvalid(axil_csr_wvalid), - .s_axil_wready(axil_csr_wready), - .s_axil_bresp(axil_csr_bresp), - .s_axil_bvalid(axil_csr_bvalid), - .s_axil_bready(axil_csr_bready), - .s_axil_araddr(axil_csr_araddr), - .s_axil_arprot(axil_csr_arprot), - .s_axil_arvalid(axil_csr_arvalid), - .s_axil_arready(axil_csr_arready), - .s_axil_rdata(axil_csr_rdata), - .s_axil_rresp(axil_csr_rresp), - .s_axil_rvalid(axil_csr_rvalid), - .s_axil_rready(axil_csr_rready), - .ptp_ts_96(ptp_sync_ts_96), - .ptp_ts_step(ptp_sync_ts_step) -); +generate + +if (TDMA_BER_ENABLE) begin + + // BER tester + tdma_ber #( + .COUNT(8), + .INDEX_WIDTH(6), + .SLICE_WIDTH(5), + .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .AXIL_ADDR_WIDTH(8+6+$clog2(8)), + .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .SCHEDULE_START_S(0), + .SCHEDULE_START_NS(0), + .SCHEDULE_PERIOD_S(0), + .SCHEDULE_PERIOD_NS(1000000), + .TIMESLOT_PERIOD_S(0), + .TIMESLOT_PERIOD_NS(100000), + .ACTIVE_PERIOD_S(0), + .ACTIVE_PERIOD_NS(90000), + .PHY_PIPELINE(2) + ) + tdma_ber_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + .phy_tx_clk({qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1, qsfp0_tx_clk_4, qsfp0_tx_clk_3, qsfp0_tx_clk_2, qsfp0_tx_clk_1}), + .phy_rx_clk({qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}), + .phy_rx_error_count({qsfp1_rx_error_count_4, qsfp1_rx_error_count_3, qsfp1_rx_error_count_2, qsfp1_rx_error_count_1, qsfp0_rx_error_count_4, qsfp0_rx_error_count_3, qsfp0_rx_error_count_2, qsfp0_rx_error_count_1}), + .phy_tx_prbs31_enable({qsfp1_tx_prbs31_enable_4, qsfp1_tx_prbs31_enable_3, qsfp1_tx_prbs31_enable_2, qsfp1_tx_prbs31_enable_1, qsfp0_tx_prbs31_enable_4, qsfp0_tx_prbs31_enable_3, qsfp0_tx_prbs31_enable_2, qsfp0_tx_prbs31_enable_1}), + .phy_rx_prbs31_enable({qsfp1_rx_prbs31_enable_4, qsfp1_rx_prbs31_enable_3, qsfp1_rx_prbs31_enable_2, qsfp1_rx_prbs31_enable_1, qsfp0_rx_prbs31_enable_4, qsfp0_rx_prbs31_enable_3, qsfp0_rx_prbs31_enable_2, qsfp0_rx_prbs31_enable_1}), + .s_axil_awaddr(axil_csr_awaddr), + .s_axil_awprot(axil_csr_awprot), + .s_axil_awvalid(axil_csr_awvalid), + .s_axil_awready(axil_csr_awready), + .s_axil_wdata(axil_csr_wdata), + .s_axil_wstrb(axil_csr_wstrb), + .s_axil_wvalid(axil_csr_wvalid), + .s_axil_wready(axil_csr_wready), + .s_axil_bresp(axil_csr_bresp), + .s_axil_bvalid(axil_csr_bvalid), + .s_axil_bready(axil_csr_bready), + .s_axil_araddr(axil_csr_araddr), + .s_axil_arprot(axil_csr_arprot), + .s_axil_arvalid(axil_csr_arvalid), + .s_axil_arready(axil_csr_arready), + .s_axil_rdata(axil_csr_rdata), + .s_axil_rresp(axil_csr_rresp), + .s_axil_rvalid(axil_csr_rvalid), + .s_axil_rready(axil_csr_rready), + .ptp_ts_96(ptp_sync_ts_96), + .ptp_ts_step(ptp_sync_ts_step) + ); + +end else begin + + assign qsfp0_tx_prbs31_enable_1 = 1'b0; + assign qsfp0_rx_prbs31_enable_1 = 1'b0; + assign qsfp0_tx_prbs31_enable_2 = 1'b0; + assign qsfp0_rx_prbs31_enable_2 = 1'b0; + assign qsfp0_tx_prbs31_enable_3 = 1'b0; + assign qsfp0_rx_prbs31_enable_3 = 1'b0; + assign qsfp0_tx_prbs31_enable_4 = 1'b0; + assign qsfp0_rx_prbs31_enable_4 = 1'b0; + assign qsfp1_tx_prbs31_enable_1 = 1'b0; + assign qsfp1_rx_prbs31_enable_1 = 1'b0; + assign qsfp1_tx_prbs31_enable_2 = 1'b0; + assign qsfp1_rx_prbs31_enable_2 = 1'b0; + assign qsfp1_tx_prbs31_enable_3 = 1'b0; + assign qsfp1_rx_prbs31_enable_3 = 1'b0; + assign qsfp1_tx_prbs31_enable_4 = 1'b0; + assign qsfp1_rx_prbs31_enable_4 = 1'b0; + +end + +endgenerate assign led[0] = pps_led_reg; assign led[2:1] = 0; @@ -1189,7 +1219,7 @@ mqnic_core_pcie_us #( .AXIL_CTRL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), .AXIL_IF_CTRL_ADDR_WIDTH(AXIL_IF_CTRL_ADDR_WIDTH), .AXIL_CSR_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .AXIL_CSR_PASSTHROUGH_ENABLE(1), + .AXIL_CSR_PASSTHROUGH_ENABLE(TDMA_BER_ENABLE), .RB_NEXT_PTR(RB_BASE_ADDR), // AXI lite interface configuration (application control) diff --git a/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl index 742e2c25b..49a00077d 100644 --- a/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl @@ -80,6 +80,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params TDMA_BER_ENABLE "0" + # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {25.78125} diff --git a/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl index 6cf28a357..8865e6027 100644 --- a/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl @@ -80,6 +80,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params TDMA_BER_ENABLE "0" + # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {10.3125} diff --git a/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v index f95aeaa76..af3e565a9 100644 --- a/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v @@ -52,6 +52,9 @@ module fpga # parameter GIT_HASH = 32'hdce357bf, parameter RELEASE_INFO = 32'h00000000, + // Board configuration + parameter TDMA_BER_ENABLE = 0, + // Structural configuration parameter IF_COUNT = 2, parameter PORTS_PER_IF = 1, @@ -1497,6 +1500,9 @@ fpga_core #( .GIT_HASH(GIT_HASH), .RELEASE_INFO(RELEASE_INFO), + // Board configuration + .TDMA_BER_ENABLE(TDMA_BER_ENABLE), + // Structural configuration .IF_COUNT(IF_COUNT), .PORTS_PER_IF(PORTS_PER_IF), diff --git a/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v index da37b00bf..ae8699bfb 100644 --- a/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v @@ -52,6 +52,9 @@ module fpga_core # parameter GIT_HASH = 32'hdce357bf, parameter RELEASE_INFO = 32'h00000000, + // Board configuration + parameter TDMA_BER_ENABLE = 0, + // Structural configuration parameter IF_COUNT = 2, parameter PORTS_PER_IF = 1, @@ -865,54 +868,81 @@ always @(posedge ptp_clk) begin pps_led_reg <= pps_led_counter_reg > 0; end -// BER tester -tdma_ber #( - .COUNT(8), - .INDEX_WIDTH(6), - .SLICE_WIDTH(5), - .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_ADDR_WIDTH(8+6+$clog2(8)), - .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .SCHEDULE_START_S(0), - .SCHEDULE_START_NS(0), - .SCHEDULE_PERIOD_S(0), - .SCHEDULE_PERIOD_NS(1000000), - .TIMESLOT_PERIOD_S(0), - .TIMESLOT_PERIOD_NS(100000), - .ACTIVE_PERIOD_S(0), - .ACTIVE_PERIOD_NS(90000), - .PHY_PIPELINE(2) -) -tdma_ber_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - .phy_tx_clk({qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1, qsfp0_tx_clk_4, qsfp0_tx_clk_3, qsfp0_tx_clk_2, qsfp0_tx_clk_1}), - .phy_rx_clk({qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}), - .phy_rx_error_count({qsfp1_rx_error_count_4, qsfp1_rx_error_count_3, qsfp1_rx_error_count_2, qsfp1_rx_error_count_1, qsfp0_rx_error_count_4, qsfp0_rx_error_count_3, qsfp0_rx_error_count_2, qsfp0_rx_error_count_1}), - .phy_tx_prbs31_enable({qsfp1_tx_prbs31_enable_4, qsfp1_tx_prbs31_enable_3, qsfp1_tx_prbs31_enable_2, qsfp1_tx_prbs31_enable_1, qsfp0_tx_prbs31_enable_4, qsfp0_tx_prbs31_enable_3, qsfp0_tx_prbs31_enable_2, qsfp0_tx_prbs31_enable_1}), - .phy_rx_prbs31_enable({qsfp1_rx_prbs31_enable_4, qsfp1_rx_prbs31_enable_3, qsfp1_rx_prbs31_enable_2, qsfp1_rx_prbs31_enable_1, qsfp0_rx_prbs31_enable_4, qsfp0_rx_prbs31_enable_3, qsfp0_rx_prbs31_enable_2, qsfp0_rx_prbs31_enable_1}), - .s_axil_awaddr(axil_csr_awaddr), - .s_axil_awprot(axil_csr_awprot), - .s_axil_awvalid(axil_csr_awvalid), - .s_axil_awready(axil_csr_awready), - .s_axil_wdata(axil_csr_wdata), - .s_axil_wstrb(axil_csr_wstrb), - .s_axil_wvalid(axil_csr_wvalid), - .s_axil_wready(axil_csr_wready), - .s_axil_bresp(axil_csr_bresp), - .s_axil_bvalid(axil_csr_bvalid), - .s_axil_bready(axil_csr_bready), - .s_axil_araddr(axil_csr_araddr), - .s_axil_arprot(axil_csr_arprot), - .s_axil_arvalid(axil_csr_arvalid), - .s_axil_arready(axil_csr_arready), - .s_axil_rdata(axil_csr_rdata), - .s_axil_rresp(axil_csr_rresp), - .s_axil_rvalid(axil_csr_rvalid), - .s_axil_rready(axil_csr_rready), - .ptp_ts_96(ptp_sync_ts_96), - .ptp_ts_step(ptp_sync_ts_step) -); +generate + +if (TDMA_BER_ENABLE) begin + + // BER tester + tdma_ber #( + .COUNT(8), + .INDEX_WIDTH(6), + .SLICE_WIDTH(5), + .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .AXIL_ADDR_WIDTH(8+6+$clog2(8)), + .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .SCHEDULE_START_S(0), + .SCHEDULE_START_NS(0), + .SCHEDULE_PERIOD_S(0), + .SCHEDULE_PERIOD_NS(1000000), + .TIMESLOT_PERIOD_S(0), + .TIMESLOT_PERIOD_NS(100000), + .ACTIVE_PERIOD_S(0), + .ACTIVE_PERIOD_NS(90000), + .PHY_PIPELINE(2) + ) + tdma_ber_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + .phy_tx_clk({qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1, qsfp0_tx_clk_4, qsfp0_tx_clk_3, qsfp0_tx_clk_2, qsfp0_tx_clk_1}), + .phy_rx_clk({qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}), + .phy_rx_error_count({qsfp1_rx_error_count_4, qsfp1_rx_error_count_3, qsfp1_rx_error_count_2, qsfp1_rx_error_count_1, qsfp0_rx_error_count_4, qsfp0_rx_error_count_3, qsfp0_rx_error_count_2, qsfp0_rx_error_count_1}), + .phy_tx_prbs31_enable({qsfp1_tx_prbs31_enable_4, qsfp1_tx_prbs31_enable_3, qsfp1_tx_prbs31_enable_2, qsfp1_tx_prbs31_enable_1, qsfp0_tx_prbs31_enable_4, qsfp0_tx_prbs31_enable_3, qsfp0_tx_prbs31_enable_2, qsfp0_tx_prbs31_enable_1}), + .phy_rx_prbs31_enable({qsfp1_rx_prbs31_enable_4, qsfp1_rx_prbs31_enable_3, qsfp1_rx_prbs31_enable_2, qsfp1_rx_prbs31_enable_1, qsfp0_rx_prbs31_enable_4, qsfp0_rx_prbs31_enable_3, qsfp0_rx_prbs31_enable_2, qsfp0_rx_prbs31_enable_1}), + .s_axil_awaddr(axil_csr_awaddr), + .s_axil_awprot(axil_csr_awprot), + .s_axil_awvalid(axil_csr_awvalid), + .s_axil_awready(axil_csr_awready), + .s_axil_wdata(axil_csr_wdata), + .s_axil_wstrb(axil_csr_wstrb), + .s_axil_wvalid(axil_csr_wvalid), + .s_axil_wready(axil_csr_wready), + .s_axil_bresp(axil_csr_bresp), + .s_axil_bvalid(axil_csr_bvalid), + .s_axil_bready(axil_csr_bready), + .s_axil_araddr(axil_csr_araddr), + .s_axil_arprot(axil_csr_arprot), + .s_axil_arvalid(axil_csr_arvalid), + .s_axil_arready(axil_csr_arready), + .s_axil_rdata(axil_csr_rdata), + .s_axil_rresp(axil_csr_rresp), + .s_axil_rvalid(axil_csr_rvalid), + .s_axil_rready(axil_csr_rready), + .ptp_ts_96(ptp_sync_ts_96), + .ptp_ts_step(ptp_sync_ts_step) + ); + +end else begin + + assign qsfp0_tx_prbs31_enable_1 = 1'b0; + assign qsfp0_rx_prbs31_enable_1 = 1'b0; + assign qsfp0_tx_prbs31_enable_2 = 1'b0; + assign qsfp0_rx_prbs31_enable_2 = 1'b0; + assign qsfp0_tx_prbs31_enable_3 = 1'b0; + assign qsfp0_rx_prbs31_enable_3 = 1'b0; + assign qsfp0_tx_prbs31_enable_4 = 1'b0; + assign qsfp0_rx_prbs31_enable_4 = 1'b0; + assign qsfp1_tx_prbs31_enable_1 = 1'b0; + assign qsfp1_rx_prbs31_enable_1 = 1'b0; + assign qsfp1_tx_prbs31_enable_2 = 1'b0; + assign qsfp1_rx_prbs31_enable_2 = 1'b0; + assign qsfp1_tx_prbs31_enable_3 = 1'b0; + assign qsfp1_rx_prbs31_enable_3 = 1'b0; + assign qsfp1_tx_prbs31_enable_4 = 1'b0; + assign qsfp1_rx_prbs31_enable_4 = 1'b0; + +end + +endgenerate assign led[0] = pps_led_reg; assign led[2:1] = 0; @@ -1189,7 +1219,7 @@ mqnic_core_pcie_us #( .AXIL_CTRL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), .AXIL_IF_CTRL_ADDR_WIDTH(AXIL_IF_CTRL_ADDR_WIDTH), .AXIL_CSR_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .AXIL_CSR_PASSTHROUGH_ENABLE(1), + .AXIL_CSR_PASSTHROUGH_ENABLE(TDMA_BER_ENABLE), .RB_NEXT_PTR(RB_BASE_ADDR), // AXI lite interface configuration (application control) diff --git a/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl index 1a851dd85..2a306a340 100644 --- a/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl @@ -80,6 +80,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params TDMA_BER_ENABLE "0" + # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {25.78125} diff --git a/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl index 028ab1d60..fc5a70ea7 100644 --- a/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl @@ -80,6 +80,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params TDMA_BER_ENABLE "0" + # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {10.3125} diff --git a/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v index 2b77befdb..52379c9c4 100644 --- a/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v @@ -52,6 +52,9 @@ module fpga # parameter GIT_HASH = 32'hdce357bf, parameter RELEASE_INFO = 32'h00000000, + // Board configuration + parameter TDMA_BER_ENABLE = 0, + // Structural configuration parameter IF_COUNT = 2, parameter PORTS_PER_IF = 1, @@ -1400,6 +1403,9 @@ fpga_core #( .GIT_HASH(GIT_HASH), .RELEASE_INFO(RELEASE_INFO), + // Board configuration + .TDMA_BER_ENABLE(TDMA_BER_ENABLE), + // Structural configuration .IF_COUNT(IF_COUNT), .PORTS_PER_IF(PORTS_PER_IF), diff --git a/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v index 279ce1b43..97bb5922a 100644 --- a/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v @@ -52,6 +52,9 @@ module fpga_core # parameter GIT_HASH = 32'hdce357bf, parameter RELEASE_INFO = 32'h00000000, + // Board configuration + parameter TDMA_BER_ENABLE = 0, + // Structural configuration parameter IF_COUNT = 2, parameter PORTS_PER_IF = 1, @@ -744,54 +747,81 @@ qsfp1_rb_drp_inst ( .drp_rdy(qsfp1_drp_rdy) ); -// BER tester -tdma_ber #( - .COUNT(8), - .INDEX_WIDTH(6), - .SLICE_WIDTH(5), - .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_ADDR_WIDTH(8+6+$clog2(8)), - .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .SCHEDULE_START_S(0), - .SCHEDULE_START_NS(0), - .SCHEDULE_PERIOD_S(0), - .SCHEDULE_PERIOD_NS(1000000), - .TIMESLOT_PERIOD_S(0), - .TIMESLOT_PERIOD_NS(100000), - .ACTIVE_PERIOD_S(0), - .ACTIVE_PERIOD_NS(90000), - .PHY_PIPELINE(2) -) -tdma_ber_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - .phy_tx_clk({qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1, qsfp0_tx_clk_4, qsfp0_tx_clk_3, qsfp0_tx_clk_2, qsfp0_tx_clk_1}), - .phy_rx_clk({qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}), - .phy_rx_error_count({qsfp1_rx_error_count_4, qsfp1_rx_error_count_3, qsfp1_rx_error_count_2, qsfp1_rx_error_count_1, qsfp0_rx_error_count_4, qsfp0_rx_error_count_3, qsfp0_rx_error_count_2, qsfp0_rx_error_count_1}), - .phy_tx_prbs31_enable({qsfp1_tx_prbs31_enable_4, qsfp1_tx_prbs31_enable_3, qsfp1_tx_prbs31_enable_2, qsfp1_tx_prbs31_enable_1, qsfp0_tx_prbs31_enable_4, qsfp0_tx_prbs31_enable_3, qsfp0_tx_prbs31_enable_2, qsfp0_tx_prbs31_enable_1}), - .phy_rx_prbs31_enable({qsfp1_rx_prbs31_enable_4, qsfp1_rx_prbs31_enable_3, qsfp1_rx_prbs31_enable_2, qsfp1_rx_prbs31_enable_1, qsfp0_rx_prbs31_enable_4, qsfp0_rx_prbs31_enable_3, qsfp0_rx_prbs31_enable_2, qsfp0_rx_prbs31_enable_1}), - .s_axil_awaddr(axil_csr_awaddr), - .s_axil_awprot(axil_csr_awprot), - .s_axil_awvalid(axil_csr_awvalid), - .s_axil_awready(axil_csr_awready), - .s_axil_wdata(axil_csr_wdata), - .s_axil_wstrb(axil_csr_wstrb), - .s_axil_wvalid(axil_csr_wvalid), - .s_axil_wready(axil_csr_wready), - .s_axil_bresp(axil_csr_bresp), - .s_axil_bvalid(axil_csr_bvalid), - .s_axil_bready(axil_csr_bready), - .s_axil_araddr(axil_csr_araddr), - .s_axil_arprot(axil_csr_arprot), - .s_axil_arvalid(axil_csr_arvalid), - .s_axil_arready(axil_csr_arready), - .s_axil_rdata(axil_csr_rdata), - .s_axil_rresp(axil_csr_rresp), - .s_axil_rvalid(axil_csr_rvalid), - .s_axil_rready(axil_csr_rready), - .ptp_ts_96(ptp_sync_ts_96), - .ptp_ts_step(ptp_sync_ts_step) -); +generate + +if (TDMA_BER_ENABLE) begin + + // BER tester + tdma_ber #( + .COUNT(8), + .INDEX_WIDTH(6), + .SLICE_WIDTH(5), + .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .AXIL_ADDR_WIDTH(8+6+$clog2(8)), + .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .SCHEDULE_START_S(0), + .SCHEDULE_START_NS(0), + .SCHEDULE_PERIOD_S(0), + .SCHEDULE_PERIOD_NS(1000000), + .TIMESLOT_PERIOD_S(0), + .TIMESLOT_PERIOD_NS(100000), + .ACTIVE_PERIOD_S(0), + .ACTIVE_PERIOD_NS(90000), + .PHY_PIPELINE(2) + ) + tdma_ber_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + .phy_tx_clk({qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1, qsfp0_tx_clk_4, qsfp0_tx_clk_3, qsfp0_tx_clk_2, qsfp0_tx_clk_1}), + .phy_rx_clk({qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}), + .phy_rx_error_count({qsfp1_rx_error_count_4, qsfp1_rx_error_count_3, qsfp1_rx_error_count_2, qsfp1_rx_error_count_1, qsfp0_rx_error_count_4, qsfp0_rx_error_count_3, qsfp0_rx_error_count_2, qsfp0_rx_error_count_1}), + .phy_tx_prbs31_enable({qsfp1_tx_prbs31_enable_4, qsfp1_tx_prbs31_enable_3, qsfp1_tx_prbs31_enable_2, qsfp1_tx_prbs31_enable_1, qsfp0_tx_prbs31_enable_4, qsfp0_tx_prbs31_enable_3, qsfp0_tx_prbs31_enable_2, qsfp0_tx_prbs31_enable_1}), + .phy_rx_prbs31_enable({qsfp1_rx_prbs31_enable_4, qsfp1_rx_prbs31_enable_3, qsfp1_rx_prbs31_enable_2, qsfp1_rx_prbs31_enable_1, qsfp0_rx_prbs31_enable_4, qsfp0_rx_prbs31_enable_3, qsfp0_rx_prbs31_enable_2, qsfp0_rx_prbs31_enable_1}), + .s_axil_awaddr(axil_csr_awaddr), + .s_axil_awprot(axil_csr_awprot), + .s_axil_awvalid(axil_csr_awvalid), + .s_axil_awready(axil_csr_awready), + .s_axil_wdata(axil_csr_wdata), + .s_axil_wstrb(axil_csr_wstrb), + .s_axil_wvalid(axil_csr_wvalid), + .s_axil_wready(axil_csr_wready), + .s_axil_bresp(axil_csr_bresp), + .s_axil_bvalid(axil_csr_bvalid), + .s_axil_bready(axil_csr_bready), + .s_axil_araddr(axil_csr_araddr), + .s_axil_arprot(axil_csr_arprot), + .s_axil_arvalid(axil_csr_arvalid), + .s_axil_arready(axil_csr_arready), + .s_axil_rdata(axil_csr_rdata), + .s_axil_rresp(axil_csr_rresp), + .s_axil_rvalid(axil_csr_rvalid), + .s_axil_rready(axil_csr_rready), + .ptp_ts_96(ptp_sync_ts_96), + .ptp_ts_step(ptp_sync_ts_step) + ); + +end else begin + + assign qsfp0_tx_prbs31_enable_1 = 1'b0; + assign qsfp0_rx_prbs31_enable_1 = 1'b0; + assign qsfp0_tx_prbs31_enable_2 = 1'b0; + assign qsfp0_rx_prbs31_enable_2 = 1'b0; + assign qsfp0_tx_prbs31_enable_3 = 1'b0; + assign qsfp0_rx_prbs31_enable_3 = 1'b0; + assign qsfp0_tx_prbs31_enable_4 = 1'b0; + assign qsfp0_rx_prbs31_enable_4 = 1'b0; + assign qsfp1_tx_prbs31_enable_1 = 1'b0; + assign qsfp1_rx_prbs31_enable_1 = 1'b0; + assign qsfp1_tx_prbs31_enable_2 = 1'b0; + assign qsfp1_rx_prbs31_enable_2 = 1'b0; + assign qsfp1_tx_prbs31_enable_3 = 1'b0; + assign qsfp1_rx_prbs31_enable_3 = 1'b0; + assign qsfp1_tx_prbs31_enable_4 = 1'b0; + assign qsfp1_rx_prbs31_enable_4 = 1'b0; + +end + +endgenerate wire [PORT_COUNT-1:0] eth_tx_clk; wire [PORT_COUNT-1:0] eth_tx_rst; @@ -1065,7 +1095,7 @@ mqnic_core_pcie_us #( .AXIL_CTRL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), .AXIL_IF_CTRL_ADDR_WIDTH(AXIL_IF_CTRL_ADDR_WIDTH), .AXIL_CSR_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .AXIL_CSR_PASSTHROUGH_ENABLE(1), + .AXIL_CSR_PASSTHROUGH_ENABLE(TDMA_BER_ENABLE), .RB_NEXT_PTR(RB_BASE_ADDR), // AXI lite interface configuration (application control) diff --git a/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl index a28e74902..82a7400e3 100644 --- a/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl @@ -80,6 +80,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params TDMA_BER_ENABLE "0" + # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {25.78125} diff --git a/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl index a5407e9cb..2a4dcb9b2 100644 --- a/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl @@ -80,6 +80,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params TDMA_BER_ENABLE "0" + # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {10.3125} diff --git a/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v index dd581d3a8..2ab49c4ec 100644 --- a/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v @@ -52,6 +52,9 @@ module fpga # parameter GIT_HASH = 32'hdce357bf, parameter RELEASE_INFO = 32'h00000000, + // Board configuration + parameter TDMA_BER_ENABLE = 0, + // Structural configuration parameter IF_COUNT = 1, parameter PORTS_PER_IF = 1, @@ -1162,6 +1165,9 @@ fpga_core #( .GIT_HASH(GIT_HASH), .RELEASE_INFO(RELEASE_INFO), + // Board configuration + .TDMA_BER_ENABLE(TDMA_BER_ENABLE), + // Structural configuration .IF_COUNT(IF_COUNT), .PORTS_PER_IF(PORTS_PER_IF), diff --git a/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v index 30e261081..3313fb549 100644 --- a/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v @@ -52,6 +52,9 @@ module fpga_core # parameter GIT_HASH = 32'hdce357bf, parameter RELEASE_INFO = 32'h00000000, + // Board configuration + parameter TDMA_BER_ENABLE = 0, + // Structural configuration parameter IF_COUNT = 1, parameter PORTS_PER_IF = 1, @@ -657,54 +660,73 @@ always @(posedge ptp_clk) begin pps_led_reg <= pps_led_counter_reg > 0; end -// BER tester -tdma_ber #( - .COUNT(4), - .INDEX_WIDTH(6), - .SLICE_WIDTH(5), - .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_ADDR_WIDTH(8+6+$clog2(4)), - .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .SCHEDULE_START_S(0), - .SCHEDULE_START_NS(0), - .SCHEDULE_PERIOD_S(0), - .SCHEDULE_PERIOD_NS(1000000), - .TIMESLOT_PERIOD_S(0), - .TIMESLOT_PERIOD_NS(100000), - .ACTIVE_PERIOD_S(0), - .ACTIVE_PERIOD_NS(90000), - .PHY_PIPELINE(2) -) -tdma_ber_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - .phy_tx_clk({qsfp_tx_clk_4, qsfp_tx_clk_3, qsfp_tx_clk_2, qsfp_tx_clk_1}), - .phy_rx_clk({qsfp_rx_clk_4, qsfp_rx_clk_3, qsfp_rx_clk_2, qsfp_rx_clk_1}), - .phy_rx_error_count({qsfp_rx_error_count_4, qsfp_rx_error_count_3, qsfp_rx_error_count_2, qsfp_rx_error_count_1}), - .phy_tx_prbs31_enable({qsfp_tx_prbs31_enable_4, qsfp_tx_prbs31_enable_3, qsfp_tx_prbs31_enable_2, qsfp_tx_prbs31_enable_1}), - .phy_rx_prbs31_enable({qsfp_rx_prbs31_enable_4, qsfp_rx_prbs31_enable_3, qsfp_rx_prbs31_enable_2, qsfp_rx_prbs31_enable_1}), - .s_axil_awaddr(axil_csr_awaddr), - .s_axil_awprot(axil_csr_awprot), - .s_axil_awvalid(axil_csr_awvalid), - .s_axil_awready(axil_csr_awready), - .s_axil_wdata(axil_csr_wdata), - .s_axil_wstrb(axil_csr_wstrb), - .s_axil_wvalid(axil_csr_wvalid), - .s_axil_wready(axil_csr_wready), - .s_axil_bresp(axil_csr_bresp), - .s_axil_bvalid(axil_csr_bvalid), - .s_axil_bready(axil_csr_bready), - .s_axil_araddr(axil_csr_araddr), - .s_axil_arprot(axil_csr_arprot), - .s_axil_arvalid(axil_csr_arvalid), - .s_axil_arready(axil_csr_arready), - .s_axil_rdata(axil_csr_rdata), - .s_axil_rresp(axil_csr_rresp), - .s_axil_rvalid(axil_csr_rvalid), - .s_axil_rready(axil_csr_rready), - .ptp_ts_96(ptp_sync_ts_96), - .ptp_ts_step(ptp_sync_ts_step) -); +generate + +if (TDMA_BER_ENABLE) begin + + // BER tester + tdma_ber #( + .COUNT(4), + .INDEX_WIDTH(6), + .SLICE_WIDTH(5), + .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .AXIL_ADDR_WIDTH(8+6+$clog2(4)), + .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .SCHEDULE_START_S(0), + .SCHEDULE_START_NS(0), + .SCHEDULE_PERIOD_S(0), + .SCHEDULE_PERIOD_NS(1000000), + .TIMESLOT_PERIOD_S(0), + .TIMESLOT_PERIOD_NS(100000), + .ACTIVE_PERIOD_S(0), + .ACTIVE_PERIOD_NS(90000), + .PHY_PIPELINE(2) + ) + tdma_ber_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + .phy_tx_clk({qsfp_tx_clk_4, qsfp_tx_clk_3, qsfp_tx_clk_2, qsfp_tx_clk_1}), + .phy_rx_clk({qsfp_rx_clk_4, qsfp_rx_clk_3, qsfp_rx_clk_2, qsfp_rx_clk_1}), + .phy_rx_error_count({qsfp_rx_error_count_4, qsfp_rx_error_count_3, qsfp_rx_error_count_2, qsfp_rx_error_count_1}), + .phy_tx_prbs31_enable({qsfp_tx_prbs31_enable_4, qsfp_tx_prbs31_enable_3, qsfp_tx_prbs31_enable_2, qsfp_tx_prbs31_enable_1}), + .phy_rx_prbs31_enable({qsfp_rx_prbs31_enable_4, qsfp_rx_prbs31_enable_3, qsfp_rx_prbs31_enable_2, qsfp_rx_prbs31_enable_1}), + .s_axil_awaddr(axil_csr_awaddr), + .s_axil_awprot(axil_csr_awprot), + .s_axil_awvalid(axil_csr_awvalid), + .s_axil_awready(axil_csr_awready), + .s_axil_wdata(axil_csr_wdata), + .s_axil_wstrb(axil_csr_wstrb), + .s_axil_wvalid(axil_csr_wvalid), + .s_axil_wready(axil_csr_wready), + .s_axil_bresp(axil_csr_bresp), + .s_axil_bvalid(axil_csr_bvalid), + .s_axil_bready(axil_csr_bready), + .s_axil_araddr(axil_csr_araddr), + .s_axil_arprot(axil_csr_arprot), + .s_axil_arvalid(axil_csr_arvalid), + .s_axil_arready(axil_csr_arready), + .s_axil_rdata(axil_csr_rdata), + .s_axil_rresp(axil_csr_rresp), + .s_axil_rvalid(axil_csr_rvalid), + .s_axil_rready(axil_csr_rready), + .ptp_ts_96(ptp_sync_ts_96), + .ptp_ts_step(ptp_sync_ts_step) + ); + +end else begin + + assign qsfp_tx_prbs31_enable_1 = 1'b0; + assign qsfp_rx_prbs31_enable_1 = 1'b0; + assign qsfp_tx_prbs31_enable_2 = 1'b0; + assign qsfp_rx_prbs31_enable_2 = 1'b0; + assign qsfp_tx_prbs31_enable_3 = 1'b0; + assign qsfp_rx_prbs31_enable_3 = 1'b0; + assign qsfp_tx_prbs31_enable_4 = 1'b0; + assign qsfp_rx_prbs31_enable_4 = 1'b0; + +end + +endgenerate assign qsfp_led_act = pps_led_reg; assign qsfp_led_stat_g = 1'b0; @@ -982,7 +1004,7 @@ mqnic_core_pcie_us #( .AXIL_CTRL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), .AXIL_IF_CTRL_ADDR_WIDTH(AXIL_IF_CTRL_ADDR_WIDTH), .AXIL_CSR_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .AXIL_CSR_PASSTHROUGH_ENABLE(1), + .AXIL_CSR_PASSTHROUGH_ENABLE(TDMA_BER_ENABLE), .RB_NEXT_PTR(RB_BASE_ADDR), // AXI lite interface configuration (application control) diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl index 625426f87..734f14ae6 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl @@ -80,6 +80,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params TDMA_BER_ENABLE "0" + # Structural configuration dict set params IF_COUNT "2" dict set params PORTS_PER_IF "1" diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl index dff15a7e0..bd665542c 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl @@ -80,6 +80,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params TDMA_BER_ENABLE "0" + # Structural configuration dict set params IF_COUNT "2" dict set params PORTS_PER_IF "1" diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v index 6f3c74773..a5ba9efb6 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v @@ -52,6 +52,9 @@ module fpga # parameter GIT_HASH = 32'hdce357bf, parameter RELEASE_INFO = 32'h00000000, + // Board configuration + parameter TDMA_BER_ENABLE = 0, + // Structural configuration parameter IF_COUNT = 1, parameter PORTS_PER_IF = 1, @@ -1356,6 +1359,9 @@ fpga_core #( .GIT_HASH(GIT_HASH), .RELEASE_INFO(RELEASE_INFO), + // Board configuration + .TDMA_BER_ENABLE(TDMA_BER_ENABLE), + // Structural configuration .IF_COUNT(IF_COUNT), .PORTS_PER_IF(PORTS_PER_IF), diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v index 331d4a55b..9b3f9b34e 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v @@ -52,6 +52,9 @@ module fpga_core # parameter GIT_HASH = 32'hdce357bf, parameter RELEASE_INFO = 32'h00000000, + // Board configuration + parameter TDMA_BER_ENABLE = 0, + // Structural configuration parameter IF_COUNT = 1, parameter PORTS_PER_IF = 1, @@ -882,54 +885,81 @@ always @(posedge ptp_clk) begin pps_led_reg <= pps_led_counter_reg > 0; end -// BER tester -tdma_ber #( - .COUNT(8), - .INDEX_WIDTH(6), - .SLICE_WIDTH(5), - .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_ADDR_WIDTH(8+6+$clog2(8)), - .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .SCHEDULE_START_S(0), - .SCHEDULE_START_NS(0), - .SCHEDULE_PERIOD_S(0), - .SCHEDULE_PERIOD_NS(1000000), - .TIMESLOT_PERIOD_S(0), - .TIMESLOT_PERIOD_NS(100000), - .ACTIVE_PERIOD_S(0), - .ACTIVE_PERIOD_NS(90000), - .PHY_PIPELINE(2) -) -tdma_ber_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - .phy_tx_clk({qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1, qsfp0_tx_clk_4, qsfp0_tx_clk_3, qsfp0_tx_clk_2, qsfp0_tx_clk_1}), - .phy_rx_clk({qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}), - .phy_rx_error_count({qsfp1_rx_error_count_4, qsfp1_rx_error_count_3, qsfp1_rx_error_count_2, qsfp1_rx_error_count_1, qsfp0_rx_error_count_4, qsfp0_rx_error_count_3, qsfp0_rx_error_count_2, qsfp0_rx_error_count_1}), - .phy_tx_prbs31_enable({qsfp1_tx_prbs31_enable_4, qsfp1_tx_prbs31_enable_3, qsfp1_tx_prbs31_enable_2, qsfp1_tx_prbs31_enable_1, qsfp0_tx_prbs31_enable_4, qsfp0_tx_prbs31_enable_3, qsfp0_tx_prbs31_enable_2, qsfp0_tx_prbs31_enable_1}), - .phy_rx_prbs31_enable({qsfp1_rx_prbs31_enable_4, qsfp1_rx_prbs31_enable_3, qsfp1_rx_prbs31_enable_2, qsfp1_rx_prbs31_enable_1, qsfp0_rx_prbs31_enable_4, qsfp0_rx_prbs31_enable_3, qsfp0_rx_prbs31_enable_2, qsfp0_rx_prbs31_enable_1}), - .s_axil_awaddr(axil_csr_awaddr), - .s_axil_awprot(axil_csr_awprot), - .s_axil_awvalid(axil_csr_awvalid), - .s_axil_awready(axil_csr_awready), - .s_axil_wdata(axil_csr_wdata), - .s_axil_wstrb(axil_csr_wstrb), - .s_axil_wvalid(axil_csr_wvalid), - .s_axil_wready(axil_csr_wready), - .s_axil_bresp(axil_csr_bresp), - .s_axil_bvalid(axil_csr_bvalid), - .s_axil_bready(axil_csr_bready), - .s_axil_araddr(axil_csr_araddr), - .s_axil_arprot(axil_csr_arprot), - .s_axil_arvalid(axil_csr_arvalid), - .s_axil_arready(axil_csr_arready), - .s_axil_rdata(axil_csr_rdata), - .s_axil_rresp(axil_csr_rresp), - .s_axil_rvalid(axil_csr_rvalid), - .s_axil_rready(axil_csr_rready), - .ptp_ts_96(ptp_sync_ts_96), - .ptp_ts_step(ptp_sync_ts_step) -); +generate + +if (TDMA_BER_ENABLE) begin + + // BER tester + tdma_ber #( + .COUNT(8), + .INDEX_WIDTH(6), + .SLICE_WIDTH(5), + .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .AXIL_ADDR_WIDTH(8+6+$clog2(8)), + .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .SCHEDULE_START_S(0), + .SCHEDULE_START_NS(0), + .SCHEDULE_PERIOD_S(0), + .SCHEDULE_PERIOD_NS(1000000), + .TIMESLOT_PERIOD_S(0), + .TIMESLOT_PERIOD_NS(100000), + .ACTIVE_PERIOD_S(0), + .ACTIVE_PERIOD_NS(90000), + .PHY_PIPELINE(2) + ) + tdma_ber_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + .phy_tx_clk({qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1, qsfp0_tx_clk_4, qsfp0_tx_clk_3, qsfp0_tx_clk_2, qsfp0_tx_clk_1}), + .phy_rx_clk({qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}), + .phy_rx_error_count({qsfp1_rx_error_count_4, qsfp1_rx_error_count_3, qsfp1_rx_error_count_2, qsfp1_rx_error_count_1, qsfp0_rx_error_count_4, qsfp0_rx_error_count_3, qsfp0_rx_error_count_2, qsfp0_rx_error_count_1}), + .phy_tx_prbs31_enable({qsfp1_tx_prbs31_enable_4, qsfp1_tx_prbs31_enable_3, qsfp1_tx_prbs31_enable_2, qsfp1_tx_prbs31_enable_1, qsfp0_tx_prbs31_enable_4, qsfp0_tx_prbs31_enable_3, qsfp0_tx_prbs31_enable_2, qsfp0_tx_prbs31_enable_1}), + .phy_rx_prbs31_enable({qsfp1_rx_prbs31_enable_4, qsfp1_rx_prbs31_enable_3, qsfp1_rx_prbs31_enable_2, qsfp1_rx_prbs31_enable_1, qsfp0_rx_prbs31_enable_4, qsfp0_rx_prbs31_enable_3, qsfp0_rx_prbs31_enable_2, qsfp0_rx_prbs31_enable_1}), + .s_axil_awaddr(axil_csr_awaddr), + .s_axil_awprot(axil_csr_awprot), + .s_axil_awvalid(axil_csr_awvalid), + .s_axil_awready(axil_csr_awready), + .s_axil_wdata(axil_csr_wdata), + .s_axil_wstrb(axil_csr_wstrb), + .s_axil_wvalid(axil_csr_wvalid), + .s_axil_wready(axil_csr_wready), + .s_axil_bresp(axil_csr_bresp), + .s_axil_bvalid(axil_csr_bvalid), + .s_axil_bready(axil_csr_bready), + .s_axil_araddr(axil_csr_araddr), + .s_axil_arprot(axil_csr_arprot), + .s_axil_arvalid(axil_csr_arvalid), + .s_axil_arready(axil_csr_arready), + .s_axil_rdata(axil_csr_rdata), + .s_axil_rresp(axil_csr_rresp), + .s_axil_rvalid(axil_csr_rvalid), + .s_axil_rready(axil_csr_rready), + .ptp_ts_96(ptp_sync_ts_96), + .ptp_ts_step(ptp_sync_ts_step) + ); + +end else begin + + assign qsfp0_tx_prbs31_enable_1 = 1'b0; + assign qsfp0_rx_prbs31_enable_1 = 1'b0; + assign qsfp0_tx_prbs31_enable_2 = 1'b0; + assign qsfp0_rx_prbs31_enable_2 = 1'b0; + assign qsfp0_tx_prbs31_enable_3 = 1'b0; + assign qsfp0_rx_prbs31_enable_3 = 1'b0; + assign qsfp0_tx_prbs31_enable_4 = 1'b0; + assign qsfp0_rx_prbs31_enable_4 = 1'b0; + assign qsfp1_tx_prbs31_enable_1 = 1'b0; + assign qsfp1_rx_prbs31_enable_1 = 1'b0; + assign qsfp1_tx_prbs31_enable_2 = 1'b0; + assign qsfp1_rx_prbs31_enable_2 = 1'b0; + assign qsfp1_tx_prbs31_enable_3 = 1'b0; + assign qsfp1_rx_prbs31_enable_3 = 1'b0; + assign qsfp1_tx_prbs31_enable_4 = 1'b0; + assign qsfp1_rx_prbs31_enable_4 = 1'b0; + +end + +endgenerate assign user_led[6:0] = 0; assign user_led[7] = pps_led_reg; @@ -1211,7 +1241,7 @@ mqnic_core_pcie_us #( .AXIL_CTRL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), .AXIL_IF_CTRL_ADDR_WIDTH(AXIL_IF_CTRL_ADDR_WIDTH), .AXIL_CSR_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .AXIL_CSR_PASSTHROUGH_ENABLE(1), + .AXIL_CSR_PASSTHROUGH_ENABLE(TDMA_BER_ENABLE), .RB_NEXT_PTR(RB_BASE_ADDR), // AXI lite interface configuration (application control) diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl index b9c6be3d1..768275250 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl @@ -80,6 +80,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params TDMA_BER_ENABLE "0" + # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {25.78125} diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl index b845dc760..172bc098f 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl @@ -80,6 +80,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params TDMA_BER_ENABLE "0" + # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {10.3125} diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v index 915ffe4b5..363f42061 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v @@ -52,6 +52,9 @@ module fpga # parameter GIT_HASH = 32'hdce357bf, parameter RELEASE_INFO = 32'h00000000, + // Board configuration + parameter TDMA_BER_ENABLE = 0, + // Structural configuration parameter IF_COUNT = 2, parameter PORTS_PER_IF = 1, @@ -1292,6 +1295,9 @@ fpga_core #( .GIT_HASH(GIT_HASH), .RELEASE_INFO(RELEASE_INFO), + // Board configuration + .TDMA_BER_ENABLE(TDMA_BER_ENABLE), + // Structural configuration .IF_COUNT(IF_COUNT), .PORTS_PER_IF(PORTS_PER_IF), diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v index 0b3662b3a..16894491b 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v @@ -52,6 +52,9 @@ module fpga_core # parameter GIT_HASH = 32'hdce357bf, parameter RELEASE_INFO = 32'h00000000, + // Board configuration + parameter TDMA_BER_ENABLE = 0, + // Structural configuration parameter IF_COUNT = 2, parameter PORTS_PER_IF = 1, @@ -913,53 +916,80 @@ always @(posedge ptp_clk) begin pps_led_reg <= pps_led_counter_reg > 0; end -// BER tester -tdma_ber #( - .COUNT(8), - .INDEX_WIDTH(6), - .SLICE_WIDTH(5), - .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_ADDR_WIDTH(8+6+$clog2(8)), - .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .SCHEDULE_START_S(0), - .SCHEDULE_START_NS(0), - .SCHEDULE_PERIOD_S(0), - .SCHEDULE_PERIOD_NS(1000000), - .TIMESLOT_PERIOD_S(0), - .TIMESLOT_PERIOD_NS(100000), - .ACTIVE_PERIOD_S(0), - .ACTIVE_PERIOD_NS(90000) -) -tdma_ber_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - .phy_tx_clk({qsfp_1_tx_clk_3, qsfp_1_tx_clk_2, qsfp_1_tx_clk_1, qsfp_1_tx_clk_0, qsfp_0_tx_clk_3, qsfp_0_tx_clk_2, qsfp_0_tx_clk_1, qsfp_0_tx_clk_0}), - .phy_rx_clk({qsfp_1_rx_clk_3, qsfp_1_rx_clk_2, qsfp_1_rx_clk_1, qsfp_1_rx_clk_0, qsfp_0_rx_clk_3, qsfp_0_rx_clk_2, qsfp_0_rx_clk_1, qsfp_0_rx_clk_0}), - .phy_rx_error_count({qsfp_1_rx_error_count_3, qsfp_1_rx_error_count_2, qsfp_1_rx_error_count_1, qsfp_1_rx_error_count_0, qsfp_0_rx_error_count_3, qsfp_0_rx_error_count_2, qsfp_0_rx_error_count_1, qsfp_0_rx_error_count_0}), - .phy_tx_prbs31_enable({qsfp_1_tx_prbs31_enable_3, qsfp_1_tx_prbs31_enable_2, qsfp_1_tx_prbs31_enable_1, qsfp_1_tx_prbs31_enable_0, qsfp_0_tx_prbs31_enable_3, qsfp_0_tx_prbs31_enable_2, qsfp_0_tx_prbs31_enable_1, qsfp_0_tx_prbs31_enable_0}), - .phy_rx_prbs31_enable({qsfp_1_rx_prbs31_enable_3, qsfp_1_rx_prbs31_enable_2, qsfp_1_rx_prbs31_enable_1, qsfp_1_rx_prbs31_enable_0, qsfp_0_rx_prbs31_enable_3, qsfp_0_rx_prbs31_enable_2, qsfp_0_rx_prbs31_enable_1, qsfp_0_rx_prbs31_enable_0}), - .s_axil_awaddr(axil_csr_awaddr), - .s_axil_awprot(axil_csr_awprot), - .s_axil_awvalid(axil_csr_awvalid), - .s_axil_awready(axil_csr_awready), - .s_axil_wdata(axil_csr_wdata), - .s_axil_wstrb(axil_csr_wstrb), - .s_axil_wvalid(axil_csr_wvalid), - .s_axil_wready(axil_csr_wready), - .s_axil_bresp(axil_csr_bresp), - .s_axil_bvalid(axil_csr_bvalid), - .s_axil_bready(axil_csr_bready), - .s_axil_araddr(axil_csr_araddr), - .s_axil_arprot(axil_csr_arprot), - .s_axil_arvalid(axil_csr_arvalid), - .s_axil_arready(axil_csr_arready), - .s_axil_rdata(axil_csr_rdata), - .s_axil_rresp(axil_csr_rresp), - .s_axil_rvalid(axil_csr_rvalid), - .s_axil_rready(axil_csr_rready), - .ptp_ts_96(ptp_sync_ts_96), - .ptp_ts_step(ptp_sync_ts_step) -); +generate + +if (TDMA_BER_ENABLE) begin + + // BER tester + tdma_ber #( + .COUNT(8), + .INDEX_WIDTH(6), + .SLICE_WIDTH(5), + .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .AXIL_ADDR_WIDTH(8+6+$clog2(8)), + .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .SCHEDULE_START_S(0), + .SCHEDULE_START_NS(0), + .SCHEDULE_PERIOD_S(0), + .SCHEDULE_PERIOD_NS(1000000), + .TIMESLOT_PERIOD_S(0), + .TIMESLOT_PERIOD_NS(100000), + .ACTIVE_PERIOD_S(0), + .ACTIVE_PERIOD_NS(90000) + ) + tdma_ber_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + .phy_tx_clk({qsfp_1_tx_clk_3, qsfp_1_tx_clk_2, qsfp_1_tx_clk_1, qsfp_1_tx_clk_0, qsfp_0_tx_clk_3, qsfp_0_tx_clk_2, qsfp_0_tx_clk_1, qsfp_0_tx_clk_0}), + .phy_rx_clk({qsfp_1_rx_clk_3, qsfp_1_rx_clk_2, qsfp_1_rx_clk_1, qsfp_1_rx_clk_0, qsfp_0_rx_clk_3, qsfp_0_rx_clk_2, qsfp_0_rx_clk_1, qsfp_0_rx_clk_0}), + .phy_rx_error_count({qsfp_1_rx_error_count_3, qsfp_1_rx_error_count_2, qsfp_1_rx_error_count_1, qsfp_1_rx_error_count_0, qsfp_0_rx_error_count_3, qsfp_0_rx_error_count_2, qsfp_0_rx_error_count_1, qsfp_0_rx_error_count_0}), + .phy_tx_prbs31_enable({qsfp_1_tx_prbs31_enable_3, qsfp_1_tx_prbs31_enable_2, qsfp_1_tx_prbs31_enable_1, qsfp_1_tx_prbs31_enable_0, qsfp_0_tx_prbs31_enable_3, qsfp_0_tx_prbs31_enable_2, qsfp_0_tx_prbs31_enable_1, qsfp_0_tx_prbs31_enable_0}), + .phy_rx_prbs31_enable({qsfp_1_rx_prbs31_enable_3, qsfp_1_rx_prbs31_enable_2, qsfp_1_rx_prbs31_enable_1, qsfp_1_rx_prbs31_enable_0, qsfp_0_rx_prbs31_enable_3, qsfp_0_rx_prbs31_enable_2, qsfp_0_rx_prbs31_enable_1, qsfp_0_rx_prbs31_enable_0}), + .s_axil_awaddr(axil_csr_awaddr), + .s_axil_awprot(axil_csr_awprot), + .s_axil_awvalid(axil_csr_awvalid), + .s_axil_awready(axil_csr_awready), + .s_axil_wdata(axil_csr_wdata), + .s_axil_wstrb(axil_csr_wstrb), + .s_axil_wvalid(axil_csr_wvalid), + .s_axil_wready(axil_csr_wready), + .s_axil_bresp(axil_csr_bresp), + .s_axil_bvalid(axil_csr_bvalid), + .s_axil_bready(axil_csr_bready), + .s_axil_araddr(axil_csr_araddr), + .s_axil_arprot(axil_csr_arprot), + .s_axil_arvalid(axil_csr_arvalid), + .s_axil_arready(axil_csr_arready), + .s_axil_rdata(axil_csr_rdata), + .s_axil_rresp(axil_csr_rresp), + .s_axil_rvalid(axil_csr_rvalid), + .s_axil_rready(axil_csr_rready), + .ptp_ts_96(ptp_sync_ts_96), + .ptp_ts_step(ptp_sync_ts_step) + ); + +end else begin + + assign qsfp_0_tx_prbs31_enable_0 = 1'b0; + assign qsfp_0_rx_prbs31_enable_0 = 1'b0; + assign qsfp_0_tx_prbs31_enable_1 = 1'b0; + assign qsfp_0_rx_prbs31_enable_1 = 1'b0; + assign qsfp_0_tx_prbs31_enable_2 = 1'b0; + assign qsfp_0_rx_prbs31_enable_2 = 1'b0; + assign qsfp_0_tx_prbs31_enable_3 = 1'b0; + assign qsfp_0_rx_prbs31_enable_3 = 1'b0; + assign qsfp_1_tx_prbs31_enable_0 = 1'b0; + assign qsfp_1_rx_prbs31_enable_0 = 1'b0; + assign qsfp_1_tx_prbs31_enable_1 = 1'b0; + assign qsfp_1_rx_prbs31_enable_1 = 1'b0; + assign qsfp_1_tx_prbs31_enable_2 = 1'b0; + assign qsfp_1_rx_prbs31_enable_2 = 1'b0; + assign qsfp_1_tx_prbs31_enable_3 = 1'b0; + assign qsfp_1_rx_prbs31_enable_3 = 1'b0; + +end + +endgenerate assign sma_out = ptp_perout_pulse; assign sma_out_en = 1'b0; @@ -1244,7 +1274,7 @@ mqnic_core_pcie_us #( .AXIL_CTRL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), .AXIL_IF_CTRL_ADDR_WIDTH(AXIL_IF_CTRL_ADDR_WIDTH), .AXIL_CSR_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .AXIL_CSR_PASSTHROUGH_ENABLE(1), + .AXIL_CSR_PASSTHROUGH_ENABLE(TDMA_BER_ENABLE), .RB_NEXT_PTR(RB_BASE_ADDR), // AXI lite interface configuration (application control) diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/config.tcl b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/config.tcl index 3a71582df..6b0f228c5 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/config.tcl @@ -80,6 +80,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params TDMA_BER_ENABLE "0" + # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {25.78125} diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/config.tcl index d00c61ffa..015e3d66d 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/config.tcl @@ -80,6 +80,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params TDMA_BER_ENABLE "0" + # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {10.3125} diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v index 8a5822a51..f952be220 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v @@ -52,6 +52,9 @@ module fpga # parameter GIT_HASH = 32'hdce357bf, parameter RELEASE_INFO = 32'h00000000, + // Board configuration + parameter TDMA_BER_ENABLE = 0, + // Structural configuration parameter IF_COUNT = 2, parameter PORTS_PER_IF = 1, @@ -1061,6 +1064,9 @@ fpga_core #( .GIT_HASH(GIT_HASH), .RELEASE_INFO(RELEASE_INFO), + // Board configuration + .TDMA_BER_ENABLE(TDMA_BER_ENABLE), + // Structural configuration .IF_COUNT(IF_COUNT), .PORTS_PER_IF(PORTS_PER_IF), diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v index 878dc32aa..b7fa2c860 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v @@ -52,6 +52,9 @@ module fpga_core # parameter GIT_HASH = 32'hdce357bf, parameter RELEASE_INFO = 32'h00000000, + // Board configuration + parameter TDMA_BER_ENABLE = 0, + // Structural configuration parameter IF_COUNT = 2, parameter PORTS_PER_IF = 1, @@ -745,53 +748,68 @@ always @(posedge ptp_clk) begin pps_led_reg <= pps_led_counter_reg > 0; end -// BER tester -tdma_ber #( - .COUNT(2), - .INDEX_WIDTH(6), - .SLICE_WIDTH(5), - .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_ADDR_WIDTH(8+6+$clog2(2)), - .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .SCHEDULE_START_S(0), - .SCHEDULE_START_NS(0), - .SCHEDULE_PERIOD_S(0), - .SCHEDULE_PERIOD_NS(1000000), - .TIMESLOT_PERIOD_S(0), - .TIMESLOT_PERIOD_NS(100000), - .ACTIVE_PERIOD_S(0), - .ACTIVE_PERIOD_NS(90000) -) -tdma_ber_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - .phy_tx_clk({sfp_2_tx_clk, sfp_1_tx_clk}), - .phy_rx_clk({sfp_2_rx_clk, sfp_1_rx_clk}), - .phy_rx_error_count({sfp_2_rx_error_count, sfp_1_rx_error_count}), - .phy_tx_prbs31_enable({sfp_2_tx_prbs31_enable, sfp_1_tx_prbs31_enable}), - .phy_rx_prbs31_enable({sfp_2_rx_prbs31_enable, sfp_1_rx_prbs31_enable}), - .s_axil_awaddr(axil_csr_awaddr), - .s_axil_awprot(axil_csr_awprot), - .s_axil_awvalid(axil_csr_awvalid), - .s_axil_awready(axil_csr_awready), - .s_axil_wdata(axil_csr_wdata), - .s_axil_wstrb(axil_csr_wstrb), - .s_axil_wvalid(axil_csr_wvalid), - .s_axil_wready(axil_csr_wready), - .s_axil_bresp(axil_csr_bresp), - .s_axil_bvalid(axil_csr_bvalid), - .s_axil_bready(axil_csr_bready), - .s_axil_araddr(axil_csr_araddr), - .s_axil_arprot(axil_csr_arprot), - .s_axil_arvalid(axil_csr_arvalid), - .s_axil_arready(axil_csr_arready), - .s_axil_rdata(axil_csr_rdata), - .s_axil_rresp(axil_csr_rresp), - .s_axil_rvalid(axil_csr_rvalid), - .s_axil_rready(axil_csr_rready), - .ptp_ts_96(ptp_sync_ts_96), - .ptp_ts_step(ptp_sync_ts_step) -); +generate + +if (TDMA_BER_ENABLE) begin + + // BER tester + tdma_ber #( + .COUNT(2), + .INDEX_WIDTH(6), + .SLICE_WIDTH(5), + .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .AXIL_ADDR_WIDTH(8+6+$clog2(2)), + .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .SCHEDULE_START_S(0), + .SCHEDULE_START_NS(0), + .SCHEDULE_PERIOD_S(0), + .SCHEDULE_PERIOD_NS(1000000), + .TIMESLOT_PERIOD_S(0), + .TIMESLOT_PERIOD_NS(100000), + .ACTIVE_PERIOD_S(0), + .ACTIVE_PERIOD_NS(90000) + ) + tdma_ber_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + .phy_tx_clk({sfp_2_tx_clk, sfp_1_tx_clk}), + .phy_rx_clk({sfp_2_rx_clk, sfp_1_rx_clk}), + .phy_rx_error_count({sfp_2_rx_error_count, sfp_1_rx_error_count}), + .phy_tx_prbs31_enable({sfp_2_tx_prbs31_enable, sfp_1_tx_prbs31_enable}), + .phy_rx_prbs31_enable({sfp_2_rx_prbs31_enable, sfp_1_rx_prbs31_enable}), + .s_axil_awaddr(axil_csr_awaddr), + .s_axil_awprot(axil_csr_awprot), + .s_axil_awvalid(axil_csr_awvalid), + .s_axil_awready(axil_csr_awready), + .s_axil_wdata(axil_csr_wdata), + .s_axil_wstrb(axil_csr_wstrb), + .s_axil_wvalid(axil_csr_wvalid), + .s_axil_wready(axil_csr_wready), + .s_axil_bresp(axil_csr_bresp), + .s_axil_bvalid(axil_csr_bvalid), + .s_axil_bready(axil_csr_bready), + .s_axil_araddr(axil_csr_araddr), + .s_axil_arprot(axil_csr_arprot), + .s_axil_arvalid(axil_csr_arvalid), + .s_axil_arready(axil_csr_arready), + .s_axil_rdata(axil_csr_rdata), + .s_axil_rresp(axil_csr_rresp), + .s_axil_rvalid(axil_csr_rvalid), + .s_axil_rready(axil_csr_rready), + .ptp_ts_96(ptp_sync_ts_96), + .ptp_ts_step(ptp_sync_ts_step) + ); + +end else begin + + assign sfp_1_tx_prbs31_enable = 1'b0; + assign sfp_1_rx_prbs31_enable = 1'b0; + assign sfp_2_tx_prbs31_enable = 1'b0; + assign sfp_2_rx_prbs31_enable = 1'b0; + +end + +endgenerate assign sma_out = ptp_perout_pulse; assign sma_out_en = 1'b0; @@ -1074,7 +1092,7 @@ mqnic_core_pcie_us #( .AXIL_CTRL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), .AXIL_IF_CTRL_ADDR_WIDTH(AXIL_IF_CTRL_ADDR_WIDTH), .AXIL_CSR_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .AXIL_CSR_PASSTHROUGH_ENABLE(1), + .AXIL_CSR_PASSTHROUGH_ENABLE(TDMA_BER_ENABLE), .RB_NEXT_PTR(RB_BASE_ADDR), // AXI lite interface configuration (application control) diff --git a/fpga/mqnic/VCU108/fpga_10g/fpga/config.tcl b/fpga/mqnic/VCU108/fpga_10g/fpga/config.tcl index fddc00ceb..2edd97ad2 100644 --- a/fpga/mqnic/VCU108/fpga_10g/fpga/config.tcl +++ b/fpga/mqnic/VCU108/fpga_10g/fpga/config.tcl @@ -80,6 +80,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params TDMA_BER_ENABLE "0" + # Structural configuration dict set params IF_COUNT "1" dict set params PORTS_PER_IF "1" diff --git a/fpga/mqnic/VCU108/fpga_10g/rtl/fpga.v b/fpga/mqnic/VCU108/fpga_10g/rtl/fpga.v index 0f54c21c7..49bb1e6a0 100644 --- a/fpga/mqnic/VCU108/fpga_10g/rtl/fpga.v +++ b/fpga/mqnic/VCU108/fpga_10g/rtl/fpga.v @@ -52,6 +52,9 @@ module fpga # parameter GIT_HASH = 32'hdce357bf, parameter RELEASE_INFO = 32'h00000000, + // Board configuration + parameter TDMA_BER_ENABLE = 0, + // Structural configuration parameter IF_COUNT = 1, parameter PORTS_PER_IF = 1, @@ -1128,6 +1131,9 @@ fpga_core #( .GIT_HASH(GIT_HASH), .RELEASE_INFO(RELEASE_INFO), + // Board configuration + .TDMA_BER_ENABLE(TDMA_BER_ENABLE), + // Structural configuration .IF_COUNT(IF_COUNT), .PORTS_PER_IF(PORTS_PER_IF), diff --git a/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v index 8aa66e38b..39fec99f7 100644 --- a/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v @@ -52,6 +52,9 @@ module fpga_core # parameter GIT_HASH = 32'hdce357bf, parameter RELEASE_INFO = 32'h00000000, + // Board configuration + parameter TDMA_BER_ENABLE = 0, + // Structural configuration parameter IF_COUNT = 1, parameter PORTS_PER_IF = 1, @@ -697,53 +700,72 @@ always @(posedge ptp_clk) begin pps_led_reg <= pps_led_counter_reg > 0; end -// BER tester -tdma_ber #( - .COUNT(4), - .INDEX_WIDTH(6), - .SLICE_WIDTH(5), - .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_ADDR_WIDTH(8+6+$clog2(4)), - .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .SCHEDULE_START_S(0), - .SCHEDULE_START_NS(0), - .SCHEDULE_PERIOD_S(0), - .SCHEDULE_PERIOD_NS(1000000), - .TIMESLOT_PERIOD_S(0), - .TIMESLOT_PERIOD_NS(100000), - .ACTIVE_PERIOD_S(0), - .ACTIVE_PERIOD_NS(90000) -) -tdma_ber_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - .phy_tx_clk({qsfp_tx_clk_4, qsfp_tx_clk_3, qsfp_tx_clk_2, qsfp_tx_clk_1}), - .phy_rx_clk({qsfp_rx_clk_4, qsfp_rx_clk_3, qsfp_rx_clk_2, qsfp_rx_clk_1}), - .phy_rx_error_count({qsfp_rx_error_count_4, qsfp_rx_error_count_3, qsfp_rx_error_count_2, qsfp_rx_error_count_1}), - .phy_tx_prbs31_enable({qsfp_tx_prbs31_enable_4, qsfp_tx_prbs31_enable_3, qsfp_tx_prbs31_enable_2, qsfp_tx_prbs31_enable_1}), - .phy_rx_prbs31_enable({qsfp_rx_prbs31_enable_4, qsfp_rx_prbs31_enable_3, qsfp_rx_prbs31_enable_2, qsfp_rx_prbs31_enable_1}), - .s_axil_awaddr(axil_csr_awaddr), - .s_axil_awprot(axil_csr_awprot), - .s_axil_awvalid(axil_csr_awvalid), - .s_axil_awready(axil_csr_awready), - .s_axil_wdata(axil_csr_wdata), - .s_axil_wstrb(axil_csr_wstrb), - .s_axil_wvalid(axil_csr_wvalid), - .s_axil_wready(axil_csr_wready), - .s_axil_bresp(axil_csr_bresp), - .s_axil_bvalid(axil_csr_bvalid), - .s_axil_bready(axil_csr_bready), - .s_axil_araddr(axil_csr_araddr), - .s_axil_arprot(axil_csr_arprot), - .s_axil_arvalid(axil_csr_arvalid), - .s_axil_arready(axil_csr_arready), - .s_axil_rdata(axil_csr_rdata), - .s_axil_rresp(axil_csr_rresp), - .s_axil_rvalid(axil_csr_rvalid), - .s_axil_rready(axil_csr_rready), - .ptp_ts_96(ptp_sync_ts_96), - .ptp_ts_step(ptp_sync_ts_step) -); +generate + +if (TDMA_BER_ENABLE) begin + + // BER tester + tdma_ber #( + .COUNT(4), + .INDEX_WIDTH(6), + .SLICE_WIDTH(5), + .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .AXIL_ADDR_WIDTH(8+6+$clog2(4)), + .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .SCHEDULE_START_S(0), + .SCHEDULE_START_NS(0), + .SCHEDULE_PERIOD_S(0), + .SCHEDULE_PERIOD_NS(1000000), + .TIMESLOT_PERIOD_S(0), + .TIMESLOT_PERIOD_NS(100000), + .ACTIVE_PERIOD_S(0), + .ACTIVE_PERIOD_NS(90000) + ) + tdma_ber_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + .phy_tx_clk({qsfp_tx_clk_4, qsfp_tx_clk_3, qsfp_tx_clk_2, qsfp_tx_clk_1}), + .phy_rx_clk({qsfp_rx_clk_4, qsfp_rx_clk_3, qsfp_rx_clk_2, qsfp_rx_clk_1}), + .phy_rx_error_count({qsfp_rx_error_count_4, qsfp_rx_error_count_3, qsfp_rx_error_count_2, qsfp_rx_error_count_1}), + .phy_tx_prbs31_enable({qsfp_tx_prbs31_enable_4, qsfp_tx_prbs31_enable_3, qsfp_tx_prbs31_enable_2, qsfp_tx_prbs31_enable_1}), + .phy_rx_prbs31_enable({qsfp_rx_prbs31_enable_4, qsfp_rx_prbs31_enable_3, qsfp_rx_prbs31_enable_2, qsfp_rx_prbs31_enable_1}), + .s_axil_awaddr(axil_csr_awaddr), + .s_axil_awprot(axil_csr_awprot), + .s_axil_awvalid(axil_csr_awvalid), + .s_axil_awready(axil_csr_awready), + .s_axil_wdata(axil_csr_wdata), + .s_axil_wstrb(axil_csr_wstrb), + .s_axil_wvalid(axil_csr_wvalid), + .s_axil_wready(axil_csr_wready), + .s_axil_bresp(axil_csr_bresp), + .s_axil_bvalid(axil_csr_bvalid), + .s_axil_bready(axil_csr_bready), + .s_axil_araddr(axil_csr_araddr), + .s_axil_arprot(axil_csr_arprot), + .s_axil_arvalid(axil_csr_arvalid), + .s_axil_arready(axil_csr_arready), + .s_axil_rdata(axil_csr_rdata), + .s_axil_rresp(axil_csr_rresp), + .s_axil_rvalid(axil_csr_rvalid), + .s_axil_rready(axil_csr_rready), + .ptp_ts_96(ptp_sync_ts_96), + .ptp_ts_step(ptp_sync_ts_step) + ); + +end else begin + + assign qsfp_tx_prbs31_enable_1 = 1'b0; + assign qsfp_rx_prbs31_enable_1 = 1'b0; + assign qsfp_tx_prbs31_enable_2 = 1'b0; + assign qsfp_rx_prbs31_enable_2 = 1'b0; + assign qsfp_tx_prbs31_enable_3 = 1'b0; + assign qsfp_rx_prbs31_enable_3 = 1'b0; + assign qsfp_tx_prbs31_enable_4 = 1'b0; + assign qsfp_rx_prbs31_enable_4 = 1'b0; + +end + +endgenerate assign pmod0[0] = ptp_perout_pulse; assign pmod0[7:1] = 0; @@ -1025,7 +1047,7 @@ mqnic_core_pcie_us #( .AXIL_CTRL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), .AXIL_IF_CTRL_ADDR_WIDTH(AXIL_IF_CTRL_ADDR_WIDTH), .AXIL_CSR_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .AXIL_CSR_PASSTHROUGH_ENABLE(1), + .AXIL_CSR_PASSTHROUGH_ENABLE(TDMA_BER_ENABLE), .RB_NEXT_PTR(RB_BASE_ADDR), // AXI lite interface configuration (application control) diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl b/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl index 746bcd822..70f3bbfa7 100644 --- a/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl @@ -80,6 +80,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params TDMA_BER_ENABLE "0" + # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {25.78125} diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl index c46710509..babe8a0f4 100644 --- a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl @@ -80,6 +80,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params TDMA_BER_ENABLE "0" + # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {10.3125} diff --git a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v index 8134c5ce2..7221b4fa6 100644 --- a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v @@ -52,6 +52,9 @@ module fpga # parameter GIT_HASH = 32'hdce357bf, parameter RELEASE_INFO = 32'h00000000, + // Board configuration + parameter TDMA_BER_ENABLE = 0, + // Structural configuration parameter IF_COUNT = 2, parameter PORTS_PER_IF = 1, @@ -1350,6 +1353,9 @@ fpga_core #( .GIT_HASH(GIT_HASH), .RELEASE_INFO(RELEASE_INFO), + // Board configuration + .TDMA_BER_ENABLE(TDMA_BER_ENABLE), + // Structural configuration .IF_COUNT(IF_COUNT), .PORTS_PER_IF(PORTS_PER_IF), diff --git a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v index d2ab0bb2d..d4a9581aa 100644 --- a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v @@ -52,6 +52,9 @@ module fpga_core # parameter GIT_HASH = 32'hdce357bf, parameter RELEASE_INFO = 32'h00000000, + // Board configuration + parameter TDMA_BER_ENABLE = 0, + // Structural configuration parameter IF_COUNT = 2, parameter PORTS_PER_IF = 1, @@ -828,54 +831,81 @@ always @(posedge ptp_clk) begin pps_led_reg <= pps_led_counter_reg > 0; end -// BER tester -tdma_ber #( - .COUNT(8), - .INDEX_WIDTH(6), - .SLICE_WIDTH(5), - .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_ADDR_WIDTH(8+6+$clog2(8)), - .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .SCHEDULE_START_S(0), - .SCHEDULE_START_NS(0), - .SCHEDULE_PERIOD_S(0), - .SCHEDULE_PERIOD_NS(1000000), - .TIMESLOT_PERIOD_S(0), - .TIMESLOT_PERIOD_NS(100000), - .ACTIVE_PERIOD_S(0), - .ACTIVE_PERIOD_NS(90000), - .PHY_PIPELINE(2) -) -tdma_ber_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - .phy_tx_clk({qsfp2_tx_clk_4, qsfp2_tx_clk_3, qsfp2_tx_clk_2, qsfp2_tx_clk_1, qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1}), - .phy_rx_clk({qsfp2_rx_clk_4, qsfp2_rx_clk_3, qsfp2_rx_clk_2, qsfp2_rx_clk_1, qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1}), - .phy_rx_error_count({qsfp2_rx_error_count_4, qsfp2_rx_error_count_3, qsfp2_rx_error_count_2, qsfp2_rx_error_count_1, qsfp1_rx_error_count_4, qsfp1_rx_error_count_3, qsfp1_rx_error_count_2, qsfp1_rx_error_count_1}), - .phy_tx_prbs31_enable({qsfp2_tx_prbs31_enable_4, qsfp2_tx_prbs31_enable_3, qsfp2_tx_prbs31_enable_2, qsfp2_tx_prbs31_enable_1, qsfp1_tx_prbs31_enable_4, qsfp1_tx_prbs31_enable_3, qsfp1_tx_prbs31_enable_2, qsfp1_tx_prbs31_enable_1}), - .phy_rx_prbs31_enable({qsfp2_rx_prbs31_enable_4, qsfp2_rx_prbs31_enable_3, qsfp2_rx_prbs31_enable_2, qsfp2_rx_prbs31_enable_1, qsfp1_rx_prbs31_enable_4, qsfp1_rx_prbs31_enable_3, qsfp1_rx_prbs31_enable_2, qsfp1_rx_prbs31_enable_1}), - .s_axil_awaddr(axil_csr_awaddr), - .s_axil_awprot(axil_csr_awprot), - .s_axil_awvalid(axil_csr_awvalid), - .s_axil_awready(axil_csr_awready), - .s_axil_wdata(axil_csr_wdata), - .s_axil_wstrb(axil_csr_wstrb), - .s_axil_wvalid(axil_csr_wvalid), - .s_axil_wready(axil_csr_wready), - .s_axil_bresp(axil_csr_bresp), - .s_axil_bvalid(axil_csr_bvalid), - .s_axil_bready(axil_csr_bready), - .s_axil_araddr(axil_csr_araddr), - .s_axil_arprot(axil_csr_arprot), - .s_axil_arvalid(axil_csr_arvalid), - .s_axil_arready(axil_csr_arready), - .s_axil_rdata(axil_csr_rdata), - .s_axil_rresp(axil_csr_rresp), - .s_axil_rvalid(axil_csr_rvalid), - .s_axil_rready(axil_csr_rready), - .ptp_ts_96(ptp_sync_ts_96), - .ptp_ts_step(ptp_sync_ts_step) -); +generate + +if (TDMA_BER_ENABLE) begin + + // BER tester + tdma_ber #( + .COUNT(8), + .INDEX_WIDTH(6), + .SLICE_WIDTH(5), + .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .AXIL_ADDR_WIDTH(8+6+$clog2(8)), + .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .SCHEDULE_START_S(0), + .SCHEDULE_START_NS(0), + .SCHEDULE_PERIOD_S(0), + .SCHEDULE_PERIOD_NS(1000000), + .TIMESLOT_PERIOD_S(0), + .TIMESLOT_PERIOD_NS(100000), + .ACTIVE_PERIOD_S(0), + .ACTIVE_PERIOD_NS(90000), + .PHY_PIPELINE(2) + ) + tdma_ber_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + .phy_tx_clk({qsfp2_tx_clk_4, qsfp2_tx_clk_3, qsfp2_tx_clk_2, qsfp2_tx_clk_1, qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1}), + .phy_rx_clk({qsfp2_rx_clk_4, qsfp2_rx_clk_3, qsfp2_rx_clk_2, qsfp2_rx_clk_1, qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1}), + .phy_rx_error_count({qsfp2_rx_error_count_4, qsfp2_rx_error_count_3, qsfp2_rx_error_count_2, qsfp2_rx_error_count_1, qsfp1_rx_error_count_4, qsfp1_rx_error_count_3, qsfp1_rx_error_count_2, qsfp1_rx_error_count_1}), + .phy_tx_prbs31_enable({qsfp2_tx_prbs31_enable_4, qsfp2_tx_prbs31_enable_3, qsfp2_tx_prbs31_enable_2, qsfp2_tx_prbs31_enable_1, qsfp1_tx_prbs31_enable_4, qsfp1_tx_prbs31_enable_3, qsfp1_tx_prbs31_enable_2, qsfp1_tx_prbs31_enable_1}), + .phy_rx_prbs31_enable({qsfp2_rx_prbs31_enable_4, qsfp2_rx_prbs31_enable_3, qsfp2_rx_prbs31_enable_2, qsfp2_rx_prbs31_enable_1, qsfp1_rx_prbs31_enable_4, qsfp1_rx_prbs31_enable_3, qsfp1_rx_prbs31_enable_2, qsfp1_rx_prbs31_enable_1}), + .s_axil_awaddr(axil_csr_awaddr), + .s_axil_awprot(axil_csr_awprot), + .s_axil_awvalid(axil_csr_awvalid), + .s_axil_awready(axil_csr_awready), + .s_axil_wdata(axil_csr_wdata), + .s_axil_wstrb(axil_csr_wstrb), + .s_axil_wvalid(axil_csr_wvalid), + .s_axil_wready(axil_csr_wready), + .s_axil_bresp(axil_csr_bresp), + .s_axil_bvalid(axil_csr_bvalid), + .s_axil_bready(axil_csr_bready), + .s_axil_araddr(axil_csr_araddr), + .s_axil_arprot(axil_csr_arprot), + .s_axil_arvalid(axil_csr_arvalid), + .s_axil_arready(axil_csr_arready), + .s_axil_rdata(axil_csr_rdata), + .s_axil_rresp(axil_csr_rresp), + .s_axil_rvalid(axil_csr_rvalid), + .s_axil_rready(axil_csr_rready), + .ptp_ts_96(ptp_sync_ts_96), + .ptp_ts_step(ptp_sync_ts_step) + ); + +end else begin + + assign qsfp1_tx_prbs31_enable_1 = 1'b0; + assign qsfp1_rx_prbs31_enable_1 = 1'b0; + assign qsfp1_tx_prbs31_enable_2 = 1'b0; + assign qsfp1_rx_prbs31_enable_2 = 1'b0; + assign qsfp1_tx_prbs31_enable_3 = 1'b0; + assign qsfp1_rx_prbs31_enable_3 = 1'b0; + assign qsfp1_tx_prbs31_enable_4 = 1'b0; + assign qsfp1_rx_prbs31_enable_4 = 1'b0; + assign qsfp2_tx_prbs31_enable_1 = 1'b0; + assign qsfp2_rx_prbs31_enable_1 = 1'b0; + assign qsfp2_tx_prbs31_enable_2 = 1'b0; + assign qsfp2_rx_prbs31_enable_2 = 1'b0; + assign qsfp2_tx_prbs31_enable_3 = 1'b0; + assign qsfp2_rx_prbs31_enable_3 = 1'b0; + assign qsfp2_tx_prbs31_enable_4 = 1'b0; + assign qsfp2_rx_prbs31_enable_4 = 1'b0; + +end + +endgenerate assign pmod0[0] = ptp_perout_pulse; assign pmod0[7:1] = 0; @@ -1157,7 +1187,7 @@ mqnic_core_pcie_us #( .AXIL_CTRL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), .AXIL_IF_CTRL_ADDR_WIDTH(AXIL_IF_CTRL_ADDR_WIDTH), .AXIL_CSR_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .AXIL_CSR_PASSTHROUGH_ENABLE(1), + .AXIL_CSR_PASSTHROUGH_ENABLE(TDMA_BER_ENABLE), .RB_NEXT_PTR(RB_BASE_ADDR), // AXI lite interface configuration (application control) diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl b/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl index 434d25c93..73dde0612 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl @@ -80,6 +80,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params TDMA_BER_ENABLE "0" + # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {25.78125} diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl index fd664cbc2..f9ee78a68 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl @@ -80,6 +80,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params TDMA_BER_ENABLE "0" + # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {10.3125} diff --git a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v index d219add17..922400c81 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v @@ -52,6 +52,9 @@ module fpga # parameter GIT_HASH = 32'hdce357bf, parameter RELEASE_INFO = 32'h00000000, + // Board configuration + parameter TDMA_BER_ENABLE = 0, + // Structural configuration parameter IF_COUNT = 2, parameter PORTS_PER_IF = 1, @@ -1342,6 +1345,9 @@ fpga_core #( .GIT_HASH(GIT_HASH), .RELEASE_INFO(RELEASE_INFO), + // Board configuration + .TDMA_BER_ENABLE(TDMA_BER_ENABLE), + // Structural configuration .IF_COUNT(IF_COUNT), .PORTS_PER_IF(PORTS_PER_IF), diff --git a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v index 52edc7b0f..4fe4c3c3e 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v @@ -52,6 +52,9 @@ module fpga_core # parameter GIT_HASH = 32'hdce357bf, parameter RELEASE_INFO = 32'h00000000, + // Board configuration + parameter TDMA_BER_ENABLE = 0, + // Structural configuration parameter IF_COUNT = 2, parameter PORTS_PER_IF = 1, @@ -788,54 +791,81 @@ always @(posedge ptp_clk) begin pps_led_reg <= pps_led_counter_reg > 0; end -// BER tester -tdma_ber #( - .COUNT(8), - .INDEX_WIDTH(6), - .SLICE_WIDTH(5), - .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_ADDR_WIDTH(8+6+$clog2(8)), - .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .SCHEDULE_START_S(0), - .SCHEDULE_START_NS(0), - .SCHEDULE_PERIOD_S(0), - .SCHEDULE_PERIOD_NS(1000000), - .TIMESLOT_PERIOD_S(0), - .TIMESLOT_PERIOD_NS(100000), - .ACTIVE_PERIOD_S(0), - .ACTIVE_PERIOD_NS(90000), - .PHY_PIPELINE(2) -) -tdma_ber_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - .phy_tx_clk({qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1, qsfp0_tx_clk_4, qsfp0_tx_clk_3, qsfp0_tx_clk_2, qsfp0_tx_clk_1}), - .phy_rx_clk({qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}), - .phy_rx_error_count({qsfp1_rx_error_count_4, qsfp1_rx_error_count_3, qsfp1_rx_error_count_2, qsfp1_rx_error_count_1, qsfp0_rx_error_count_4, qsfp0_rx_error_count_3, qsfp0_rx_error_count_2, qsfp0_rx_error_count_1}), - .phy_tx_prbs31_enable({qsfp1_tx_prbs31_enable_4, qsfp1_tx_prbs31_enable_3, qsfp1_tx_prbs31_enable_2, qsfp1_tx_prbs31_enable_1, qsfp0_tx_prbs31_enable_4, qsfp0_tx_prbs31_enable_3, qsfp0_tx_prbs31_enable_2, qsfp0_tx_prbs31_enable_1}), - .phy_rx_prbs31_enable({qsfp1_rx_prbs31_enable_4, qsfp1_rx_prbs31_enable_3, qsfp1_rx_prbs31_enable_2, qsfp1_rx_prbs31_enable_1, qsfp0_rx_prbs31_enable_4, qsfp0_rx_prbs31_enable_3, qsfp0_rx_prbs31_enable_2, qsfp0_rx_prbs31_enable_1}), - .s_axil_awaddr(axil_csr_awaddr), - .s_axil_awprot(axil_csr_awprot), - .s_axil_awvalid(axil_csr_awvalid), - .s_axil_awready(axil_csr_awready), - .s_axil_wdata(axil_csr_wdata), - .s_axil_wstrb(axil_csr_wstrb), - .s_axil_wvalid(axil_csr_wvalid), - .s_axil_wready(axil_csr_wready), - .s_axil_bresp(axil_csr_bresp), - .s_axil_bvalid(axil_csr_bvalid), - .s_axil_bready(axil_csr_bready), - .s_axil_araddr(axil_csr_araddr), - .s_axil_arprot(axil_csr_arprot), - .s_axil_arvalid(axil_csr_arvalid), - .s_axil_arready(axil_csr_arready), - .s_axil_rdata(axil_csr_rdata), - .s_axil_rresp(axil_csr_rresp), - .s_axil_rvalid(axil_csr_rvalid), - .s_axil_rready(axil_csr_rready), - .ptp_ts_96(ptp_sync_ts_96), - .ptp_ts_step(ptp_sync_ts_step) -); +generate + +if (TDMA_BER_ENABLE) begin + + // BER tester + tdma_ber #( + .COUNT(8), + .INDEX_WIDTH(6), + .SLICE_WIDTH(5), + .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .AXIL_ADDR_WIDTH(8+6+$clog2(8)), + .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .SCHEDULE_START_S(0), + .SCHEDULE_START_NS(0), + .SCHEDULE_PERIOD_S(0), + .SCHEDULE_PERIOD_NS(1000000), + .TIMESLOT_PERIOD_S(0), + .TIMESLOT_PERIOD_NS(100000), + .ACTIVE_PERIOD_S(0), + .ACTIVE_PERIOD_NS(90000), + .PHY_PIPELINE(2) + ) + tdma_ber_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + .phy_tx_clk({qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1, qsfp0_tx_clk_4, qsfp0_tx_clk_3, qsfp0_tx_clk_2, qsfp0_tx_clk_1}), + .phy_rx_clk({qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}), + .phy_rx_error_count({qsfp1_rx_error_count_4, qsfp1_rx_error_count_3, qsfp1_rx_error_count_2, qsfp1_rx_error_count_1, qsfp0_rx_error_count_4, qsfp0_rx_error_count_3, qsfp0_rx_error_count_2, qsfp0_rx_error_count_1}), + .phy_tx_prbs31_enable({qsfp1_tx_prbs31_enable_4, qsfp1_tx_prbs31_enable_3, qsfp1_tx_prbs31_enable_2, qsfp1_tx_prbs31_enable_1, qsfp0_tx_prbs31_enable_4, qsfp0_tx_prbs31_enable_3, qsfp0_tx_prbs31_enable_2, qsfp0_tx_prbs31_enable_1}), + .phy_rx_prbs31_enable({qsfp1_rx_prbs31_enable_4, qsfp1_rx_prbs31_enable_3, qsfp1_rx_prbs31_enable_2, qsfp1_rx_prbs31_enable_1, qsfp0_rx_prbs31_enable_4, qsfp0_rx_prbs31_enable_3, qsfp0_rx_prbs31_enable_2, qsfp0_rx_prbs31_enable_1}), + .s_axil_awaddr(axil_csr_awaddr), + .s_axil_awprot(axil_csr_awprot), + .s_axil_awvalid(axil_csr_awvalid), + .s_axil_awready(axil_csr_awready), + .s_axil_wdata(axil_csr_wdata), + .s_axil_wstrb(axil_csr_wstrb), + .s_axil_wvalid(axil_csr_wvalid), + .s_axil_wready(axil_csr_wready), + .s_axil_bresp(axil_csr_bresp), + .s_axil_bvalid(axil_csr_bvalid), + .s_axil_bready(axil_csr_bready), + .s_axil_araddr(axil_csr_araddr), + .s_axil_arprot(axil_csr_arprot), + .s_axil_arvalid(axil_csr_arvalid), + .s_axil_arready(axil_csr_arready), + .s_axil_rdata(axil_csr_rdata), + .s_axil_rresp(axil_csr_rresp), + .s_axil_rvalid(axil_csr_rvalid), + .s_axil_rready(axil_csr_rready), + .ptp_ts_96(ptp_sync_ts_96), + .ptp_ts_step(ptp_sync_ts_step) + ); + +end else begin + + assign qsfp0_tx_prbs31_enable_1 = 1'b0; + assign qsfp0_rx_prbs31_enable_1 = 1'b0; + assign qsfp0_tx_prbs31_enable_2 = 1'b0; + assign qsfp0_rx_prbs31_enable_2 = 1'b0; + assign qsfp0_tx_prbs31_enable_3 = 1'b0; + assign qsfp0_rx_prbs31_enable_3 = 1'b0; + assign qsfp0_tx_prbs31_enable_4 = 1'b0; + assign qsfp0_rx_prbs31_enable_4 = 1'b0; + assign qsfp1_tx_prbs31_enable_1 = 1'b0; + assign qsfp1_rx_prbs31_enable_1 = 1'b0; + assign qsfp1_tx_prbs31_enable_2 = 1'b0; + assign qsfp1_rx_prbs31_enable_2 = 1'b0; + assign qsfp1_tx_prbs31_enable_3 = 1'b0; + assign qsfp1_rx_prbs31_enable_3 = 1'b0; + assign qsfp1_tx_prbs31_enable_4 = 1'b0; + assign qsfp1_rx_prbs31_enable_4 = 1'b0; + +end + +endgenerate assign led[0] = pps_led_reg; assign led[2:1] = 0; @@ -1112,7 +1142,7 @@ mqnic_core_pcie_us #( .AXIL_CTRL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), .AXIL_IF_CTRL_ADDR_WIDTH(AXIL_IF_CTRL_ADDR_WIDTH), .AXIL_CSR_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .AXIL_CSR_PASSTHROUGH_ENABLE(1), + .AXIL_CSR_PASSTHROUGH_ENABLE(TDMA_BER_ENABLE), .RB_NEXT_PTR(RB_BASE_ADDR), // AXI lite interface configuration (application control) diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl b/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl index f5de34dc9..56048cc36 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl @@ -80,6 +80,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params TDMA_BER_ENABLE "0" + # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {25.78125} diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl index 8314ef1bf..6e321b4ad 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl @@ -80,6 +80,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params TDMA_BER_ENABLE "0" + # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {10.3125} diff --git a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v index 7daa0d289..fb1e39514 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v @@ -52,6 +52,9 @@ module fpga # parameter GIT_HASH = 32'hdce357bf, parameter RELEASE_INFO = 32'h00000000, + // Board configuration + parameter TDMA_BER_ENABLE = 0, + // Structural configuration parameter IF_COUNT = 2, parameter PORTS_PER_IF = 1, @@ -1877,6 +1880,9 @@ fpga_core #( .GIT_HASH(GIT_HASH), .RELEASE_INFO(RELEASE_INFO), + // Board configuration + .TDMA_BER_ENABLE(TDMA_BER_ENABLE), + // Structural configuration .IF_COUNT(IF_COUNT), .PORTS_PER_IF(PORTS_PER_IF), diff --git a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v index 0624358f4..19a55f3ad 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v @@ -52,6 +52,9 @@ module fpga_core # parameter GIT_HASH = 32'hdce357bf, parameter RELEASE_INFO = 32'h00000000, + // Board configuration + parameter TDMA_BER_ENABLE = 0, + // Structural configuration parameter IF_COUNT = 2, parameter PORTS_PER_IF = 1, @@ -1191,54 +1194,97 @@ always @(posedge ptp_clk) begin pps_led_reg <= pps_led_counter_reg > 0; end -// BER tester -tdma_ber #( - .COUNT(16), - .INDEX_WIDTH(6), - .SLICE_WIDTH(5), - .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_ADDR_WIDTH(8+6+$clog2(16)), - .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .SCHEDULE_START_S(0), - .SCHEDULE_START_NS(0), - .SCHEDULE_PERIOD_S(0), - .SCHEDULE_PERIOD_NS(1000000), - .TIMESLOT_PERIOD_S(0), - .TIMESLOT_PERIOD_NS(100000), - .ACTIVE_PERIOD_S(0), - .ACTIVE_PERIOD_NS(90000), - .PHY_PIPELINE(2) -) -tdma_ber_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - .phy_tx_clk({qsfp3_tx_clk_4, qsfp3_tx_clk_3, qsfp3_tx_clk_2, qsfp3_tx_clk_1, qsfp2_tx_clk_4, qsfp2_tx_clk_3, qsfp2_tx_clk_2, qsfp2_tx_clk_1, qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1, qsfp0_tx_clk_4, qsfp0_tx_clk_3, qsfp0_tx_clk_2, qsfp0_tx_clk_1}), - .phy_rx_clk({qsfp3_rx_clk_4, qsfp3_rx_clk_3, qsfp3_rx_clk_2, qsfp3_rx_clk_1, qsfp2_rx_clk_4, qsfp2_rx_clk_3, qsfp2_rx_clk_2, qsfp2_rx_clk_1, qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}), - .phy_rx_error_count({qsfp3_rx_error_count_4, qsfp3_rx_error_count_3, qsfp3_rx_error_count_2, qsfp3_rx_error_count_1, qsfp2_rx_error_count_4, qsfp2_rx_error_count_3, qsfp2_rx_error_count_2, qsfp2_rx_error_count_1, qsfp1_rx_error_count_4, qsfp1_rx_error_count_3, qsfp1_rx_error_count_2, qsfp1_rx_error_count_1, qsfp0_rx_error_count_4, qsfp0_rx_error_count_3, qsfp0_rx_error_count_2, qsfp0_rx_error_count_1}), - .phy_tx_prbs31_enable({qsfp3_tx_prbs31_enable_4, qsfp3_tx_prbs31_enable_3, qsfp3_tx_prbs31_enable_2, qsfp3_tx_prbs31_enable_1, qsfp2_tx_prbs31_enable_4, qsfp2_tx_prbs31_enable_3, qsfp2_tx_prbs31_enable_2, qsfp2_tx_prbs31_enable_1, qsfp1_tx_prbs31_enable_4, qsfp1_tx_prbs31_enable_3, qsfp1_tx_prbs31_enable_2, qsfp1_tx_prbs31_enable_1, qsfp0_tx_prbs31_enable_4, qsfp0_tx_prbs31_enable_3, qsfp0_tx_prbs31_enable_2, qsfp0_tx_prbs31_enable_1}), - .phy_rx_prbs31_enable({qsfp3_rx_prbs31_enable_4, qsfp3_rx_prbs31_enable_3, qsfp3_rx_prbs31_enable_2, qsfp3_rx_prbs31_enable_1, qsfp2_rx_prbs31_enable_4, qsfp2_rx_prbs31_enable_3, qsfp2_rx_prbs31_enable_2, qsfp2_rx_prbs31_enable_1, qsfp1_rx_prbs31_enable_4, qsfp1_rx_prbs31_enable_3, qsfp1_rx_prbs31_enable_2, qsfp1_rx_prbs31_enable_1, qsfp0_rx_prbs31_enable_4, qsfp0_rx_prbs31_enable_3, qsfp0_rx_prbs31_enable_2, qsfp0_rx_prbs31_enable_1}), - .s_axil_awaddr(axil_csr_awaddr), - .s_axil_awprot(axil_csr_awprot), - .s_axil_awvalid(axil_csr_awvalid), - .s_axil_awready(axil_csr_awready), - .s_axil_wdata(axil_csr_wdata), - .s_axil_wstrb(axil_csr_wstrb), - .s_axil_wvalid(axil_csr_wvalid), - .s_axil_wready(axil_csr_wready), - .s_axil_bresp(axil_csr_bresp), - .s_axil_bvalid(axil_csr_bvalid), - .s_axil_bready(axil_csr_bready), - .s_axil_araddr(axil_csr_araddr), - .s_axil_arprot(axil_csr_arprot), - .s_axil_arvalid(axil_csr_arvalid), - .s_axil_arready(axil_csr_arready), - .s_axil_rdata(axil_csr_rdata), - .s_axil_rresp(axil_csr_rresp), - .s_axil_rvalid(axil_csr_rvalid), - .s_axil_rready(axil_csr_rready), - .ptp_ts_96(ptp_sync_ts_96), - .ptp_ts_step(ptp_sync_ts_step) -); +generate + +if (TDMA_BER_ENABLE) begin + + // BER tester + tdma_ber #( + .COUNT(16), + .INDEX_WIDTH(6), + .SLICE_WIDTH(5), + .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .AXIL_ADDR_WIDTH(8+6+$clog2(16)), + .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .SCHEDULE_START_S(0), + .SCHEDULE_START_NS(0), + .SCHEDULE_PERIOD_S(0), + .SCHEDULE_PERIOD_NS(1000000), + .TIMESLOT_PERIOD_S(0), + .TIMESLOT_PERIOD_NS(100000), + .ACTIVE_PERIOD_S(0), + .ACTIVE_PERIOD_NS(90000), + .PHY_PIPELINE(2) + ) + tdma_ber_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + .phy_tx_clk({qsfp3_tx_clk_4, qsfp3_tx_clk_3, qsfp3_tx_clk_2, qsfp3_tx_clk_1, qsfp2_tx_clk_4, qsfp2_tx_clk_3, qsfp2_tx_clk_2, qsfp2_tx_clk_1, qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1, qsfp0_tx_clk_4, qsfp0_tx_clk_3, qsfp0_tx_clk_2, qsfp0_tx_clk_1}), + .phy_rx_clk({qsfp3_rx_clk_4, qsfp3_rx_clk_3, qsfp3_rx_clk_2, qsfp3_rx_clk_1, qsfp2_rx_clk_4, qsfp2_rx_clk_3, qsfp2_rx_clk_2, qsfp2_rx_clk_1, qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}), + .phy_rx_error_count({qsfp3_rx_error_count_4, qsfp3_rx_error_count_3, qsfp3_rx_error_count_2, qsfp3_rx_error_count_1, qsfp2_rx_error_count_4, qsfp2_rx_error_count_3, qsfp2_rx_error_count_2, qsfp2_rx_error_count_1, qsfp1_rx_error_count_4, qsfp1_rx_error_count_3, qsfp1_rx_error_count_2, qsfp1_rx_error_count_1, qsfp0_rx_error_count_4, qsfp0_rx_error_count_3, qsfp0_rx_error_count_2, qsfp0_rx_error_count_1}), + .phy_tx_prbs31_enable({qsfp3_tx_prbs31_enable_4, qsfp3_tx_prbs31_enable_3, qsfp3_tx_prbs31_enable_2, qsfp3_tx_prbs31_enable_1, qsfp2_tx_prbs31_enable_4, qsfp2_tx_prbs31_enable_3, qsfp2_tx_prbs31_enable_2, qsfp2_tx_prbs31_enable_1, qsfp1_tx_prbs31_enable_4, qsfp1_tx_prbs31_enable_3, qsfp1_tx_prbs31_enable_2, qsfp1_tx_prbs31_enable_1, qsfp0_tx_prbs31_enable_4, qsfp0_tx_prbs31_enable_3, qsfp0_tx_prbs31_enable_2, qsfp0_tx_prbs31_enable_1}), + .phy_rx_prbs31_enable({qsfp3_rx_prbs31_enable_4, qsfp3_rx_prbs31_enable_3, qsfp3_rx_prbs31_enable_2, qsfp3_rx_prbs31_enable_1, qsfp2_rx_prbs31_enable_4, qsfp2_rx_prbs31_enable_3, qsfp2_rx_prbs31_enable_2, qsfp2_rx_prbs31_enable_1, qsfp1_rx_prbs31_enable_4, qsfp1_rx_prbs31_enable_3, qsfp1_rx_prbs31_enable_2, qsfp1_rx_prbs31_enable_1, qsfp0_rx_prbs31_enable_4, qsfp0_rx_prbs31_enable_3, qsfp0_rx_prbs31_enable_2, qsfp0_rx_prbs31_enable_1}), + .s_axil_awaddr(axil_csr_awaddr), + .s_axil_awprot(axil_csr_awprot), + .s_axil_awvalid(axil_csr_awvalid), + .s_axil_awready(axil_csr_awready), + .s_axil_wdata(axil_csr_wdata), + .s_axil_wstrb(axil_csr_wstrb), + .s_axil_wvalid(axil_csr_wvalid), + .s_axil_wready(axil_csr_wready), + .s_axil_bresp(axil_csr_bresp), + .s_axil_bvalid(axil_csr_bvalid), + .s_axil_bready(axil_csr_bready), + .s_axil_araddr(axil_csr_araddr), + .s_axil_arprot(axil_csr_arprot), + .s_axil_arvalid(axil_csr_arvalid), + .s_axil_arready(axil_csr_arready), + .s_axil_rdata(axil_csr_rdata), + .s_axil_rresp(axil_csr_rresp), + .s_axil_rvalid(axil_csr_rvalid), + .s_axil_rready(axil_csr_rready), + .ptp_ts_96(ptp_sync_ts_96), + .ptp_ts_step(ptp_sync_ts_step) + ); + +end else begin + + assign qsfp0_tx_prbs31_enable_1 = 1'b0; + assign qsfp0_rx_prbs31_enable_1 = 1'b0; + assign qsfp0_tx_prbs31_enable_2 = 1'b0; + assign qsfp0_rx_prbs31_enable_2 = 1'b0; + assign qsfp0_tx_prbs31_enable_3 = 1'b0; + assign qsfp0_rx_prbs31_enable_3 = 1'b0; + assign qsfp0_tx_prbs31_enable_4 = 1'b0; + assign qsfp0_rx_prbs31_enable_4 = 1'b0; + assign qsfp1_tx_prbs31_enable_1 = 1'b0; + assign qsfp1_rx_prbs31_enable_1 = 1'b0; + assign qsfp1_tx_prbs31_enable_2 = 1'b0; + assign qsfp1_rx_prbs31_enable_2 = 1'b0; + assign qsfp1_tx_prbs31_enable_3 = 1'b0; + assign qsfp1_rx_prbs31_enable_3 = 1'b0; + assign qsfp1_tx_prbs31_enable_4 = 1'b0; + assign qsfp1_rx_prbs31_enable_4 = 1'b0; + assign qsfp2_tx_prbs31_enable_1 = 1'b0; + assign qsfp2_rx_prbs31_enable_1 = 1'b0; + assign qsfp2_tx_prbs31_enable_2 = 1'b0; + assign qsfp2_rx_prbs31_enable_2 = 1'b0; + assign qsfp2_tx_prbs31_enable_3 = 1'b0; + assign qsfp2_rx_prbs31_enable_3 = 1'b0; + assign qsfp2_tx_prbs31_enable_4 = 1'b0; + assign qsfp2_rx_prbs31_enable_4 = 1'b0; + assign qsfp3_tx_prbs31_enable_1 = 1'b0; + assign qsfp3_rx_prbs31_enable_1 = 1'b0; + assign qsfp3_tx_prbs31_enable_2 = 1'b0; + assign qsfp3_rx_prbs31_enable_2 = 1'b0; + assign qsfp3_tx_prbs31_enable_3 = 1'b0; + assign qsfp3_rx_prbs31_enable_3 = 1'b0; + assign qsfp3_tx_prbs31_enable_4 = 1'b0; + assign qsfp3_rx_prbs31_enable_4 = 1'b0; + +end + +endgenerate assign led[2:0] = 3'b111; assign led[3] = !pps_led_reg; @@ -1515,7 +1561,7 @@ mqnic_core_pcie_us #( .AXIL_CTRL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), .AXIL_IF_CTRL_ADDR_WIDTH(AXIL_IF_CTRL_ADDR_WIDTH), .AXIL_CSR_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .AXIL_CSR_PASSTHROUGH_ENABLE(1), + .AXIL_CSR_PASSTHROUGH_ENABLE(TDMA_BER_ENABLE), .RB_NEXT_PTR(RB_BASE_ADDR), // AXI lite interface configuration (application control) diff --git a/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl b/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl index 46c3a74b8..2832b4392 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl +++ b/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl @@ -80,6 +80,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params TDMA_BER_ENABLE "0" + # Structural configuration dict set params IF_COUNT "2" dict set params PORTS_PER_IF "1" diff --git a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v index 7fddee7b4..13eea8909 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v +++ b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v @@ -52,6 +52,9 @@ module fpga # parameter GIT_HASH = 32'hdce357bf, parameter RELEASE_INFO = 32'h00000000, + // Board configuration + parameter TDMA_BER_ENABLE = 0, + // Structural configuration parameter IF_COUNT = 2, parameter PORTS_PER_IF = 1, @@ -841,6 +844,9 @@ fpga_core #( .GIT_HASH(GIT_HASH), .RELEASE_INFO(RELEASE_INFO), + // Board configuration + .TDMA_BER_ENABLE(TDMA_BER_ENABLE), + // Structural configuration .IF_COUNT(IF_COUNT), .PORTS_PER_IF(PORTS_PER_IF), diff --git a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v index d1cbd5ad0..d7f10ca35 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v +++ b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v @@ -52,6 +52,9 @@ module fpga_core # parameter GIT_HASH = 32'hdce357bf, parameter RELEASE_INFO = 32'h00000000, + // Board configuration + parameter TDMA_BER_ENABLE = 0, + // Structural configuration parameter IF_COUNT = 2, parameter PORTS_PER_IF = 1, @@ -561,53 +564,68 @@ always @(posedge ptp_clk) begin pps_led_reg <= pps_led_counter_reg > 0; end -// BER tester -tdma_ber #( - .COUNT(2), - .INDEX_WIDTH(6), - .SLICE_WIDTH(5), - .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_ADDR_WIDTH(8+6+$clog2(2)), - .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .SCHEDULE_START_S(0), - .SCHEDULE_START_NS(0), - .SCHEDULE_PERIOD_S(0), - .SCHEDULE_PERIOD_NS(1000000), - .TIMESLOT_PERIOD_S(0), - .TIMESLOT_PERIOD_NS(100000), - .ACTIVE_PERIOD_S(0), - .ACTIVE_PERIOD_NS(90000) -) -tdma_ber_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - .phy_tx_clk({sfp1_tx_clk, sfp0_tx_clk}), - .phy_rx_clk({sfp1_rx_clk, sfp0_rx_clk}), - .phy_rx_error_count({sfp1_rx_error_count, sfp0_rx_error_count}), - .phy_tx_prbs31_enable({sfp1_tx_prbs31_enable, sfp0_tx_prbs31_enable}), - .phy_rx_prbs31_enable({sfp1_rx_prbs31_enable, sfp0_rx_prbs31_enable}), - .s_axil_awaddr(axil_csr_awaddr), - .s_axil_awprot(axil_csr_awprot), - .s_axil_awvalid(axil_csr_awvalid), - .s_axil_awready(axil_csr_awready), - .s_axil_wdata(axil_csr_wdata), - .s_axil_wstrb(axil_csr_wstrb), - .s_axil_wvalid(axil_csr_wvalid), - .s_axil_wready(axil_csr_wready), - .s_axil_bresp(axil_csr_bresp), - .s_axil_bvalid(axil_csr_bvalid), - .s_axil_bready(axil_csr_bready), - .s_axil_araddr(axil_csr_araddr), - .s_axil_arprot(axil_csr_arprot), - .s_axil_arvalid(axil_csr_arvalid), - .s_axil_arready(axil_csr_arready), - .s_axil_rdata(axil_csr_rdata), - .s_axil_rresp(axil_csr_rresp), - .s_axil_rvalid(axil_csr_rvalid), - .s_axil_rready(axil_csr_rready), - .ptp_ts_96(ptp_sync_ts_96), - .ptp_ts_step(ptp_sync_ts_step) -); +generate + +if (TDMA_BER_ENABLE) begin + + // BER tester + tdma_ber #( + .COUNT(2), + .INDEX_WIDTH(6), + .SLICE_WIDTH(5), + .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .AXIL_ADDR_WIDTH(8+6+$clog2(2)), + .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .SCHEDULE_START_S(0), + .SCHEDULE_START_NS(0), + .SCHEDULE_PERIOD_S(0), + .SCHEDULE_PERIOD_NS(1000000), + .TIMESLOT_PERIOD_S(0), + .TIMESLOT_PERIOD_NS(100000), + .ACTIVE_PERIOD_S(0), + .ACTIVE_PERIOD_NS(90000) + ) + tdma_ber_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + .phy_tx_clk({sfp1_tx_clk, sfp0_tx_clk}), + .phy_rx_clk({sfp1_rx_clk, sfp0_rx_clk}), + .phy_rx_error_count({sfp1_rx_error_count, sfp0_rx_error_count}), + .phy_tx_prbs31_enable({sfp1_tx_prbs31_enable, sfp0_tx_prbs31_enable}), + .phy_rx_prbs31_enable({sfp1_rx_prbs31_enable, sfp0_rx_prbs31_enable}), + .s_axil_awaddr(axil_csr_awaddr), + .s_axil_awprot(axil_csr_awprot), + .s_axil_awvalid(axil_csr_awvalid), + .s_axil_awready(axil_csr_awready), + .s_axil_wdata(axil_csr_wdata), + .s_axil_wstrb(axil_csr_wstrb), + .s_axil_wvalid(axil_csr_wvalid), + .s_axil_wready(axil_csr_wready), + .s_axil_bresp(axil_csr_bresp), + .s_axil_bvalid(axil_csr_bvalid), + .s_axil_bready(axil_csr_bready), + .s_axil_araddr(axil_csr_araddr), + .s_axil_arprot(axil_csr_arprot), + .s_axil_arvalid(axil_csr_arvalid), + .s_axil_arready(axil_csr_arready), + .s_axil_rdata(axil_csr_rdata), + .s_axil_rresp(axil_csr_rresp), + .s_axil_rvalid(axil_csr_rvalid), + .s_axil_rready(axil_csr_rready), + .ptp_ts_96(ptp_sync_ts_96), + .ptp_ts_step(ptp_sync_ts_step) + ); + +end else begin + + assign sfp0_tx_prbs31_enable = 1'b0; + assign sfp0_rx_prbs31_enable = 1'b0; + assign sfp1_tx_prbs31_enable = 1'b0; + assign sfp1_rx_prbs31_enable = 1'b0; + +end + +endgenerate assign led[0] = pps_led_reg; assign led[7:1] = 0; @@ -884,7 +902,7 @@ mqnic_core_pcie_us #( .AXIL_CTRL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), .AXIL_IF_CTRL_ADDR_WIDTH(AXIL_IF_CTRL_ADDR_WIDTH), .AXIL_CSR_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .AXIL_CSR_PASSTHROUGH_ENABLE(1), + .AXIL_CSR_PASSTHROUGH_ENABLE(TDMA_BER_ENABLE), .RB_NEXT_PTR(RB_BASE_ADDR), // AXI lite interface configuration (application control) diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl index f52fa3830..b63033c89 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl @@ -72,6 +72,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params TDMA_BER_ENABLE "0" + # Structural configuration dict set params IF_COUNT "2" dict set params PORTS_PER_IF "1" diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v index 40d85c37d..728e95e2e 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v @@ -52,6 +52,9 @@ module fpga # parameter GIT_HASH = 32'hdce357bf, parameter RELEASE_INFO = 32'h00000000, + // Board configuration + parameter TDMA_BER_ENABLE = 0, + // Structural configuration parameter IF_COUNT = 2, parameter PORTS_PER_IF = 1, @@ -701,6 +704,9 @@ fpga_core #( .GIT_HASH(GIT_HASH), .RELEASE_INFO(RELEASE_INFO), + // Board configuration + .TDMA_BER_ENABLE(TDMA_BER_ENABLE), + // Structural configuration .IF_COUNT(IF_COUNT), .PORTS_PER_IF(PORTS_PER_IF), diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v index 9aa0b01f8..06e0859c7 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v @@ -52,6 +52,9 @@ module fpga_core # parameter GIT_HASH = 32'hdce357bf, parameter RELEASE_INFO = 32'h00000000, + // Board configuration + parameter TDMA_BER_ENABLE = 0, + // Structural configuration parameter IF_COUNT = 2, parameter PORTS_PER_IF = 1, @@ -520,53 +523,68 @@ always @(posedge ptp_clk) begin pps_led_reg <= pps_led_counter_reg > 0; end -// BER tester -tdma_ber #( - .COUNT(2), - .INDEX_WIDTH(6), - .SLICE_WIDTH(5), - .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_ADDR_WIDTH(8+6+$clog2(2)), - .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .SCHEDULE_START_S(0), - .SCHEDULE_START_NS(0), - .SCHEDULE_PERIOD_S(0), - .SCHEDULE_PERIOD_NS(1000000), - .TIMESLOT_PERIOD_S(0), - .TIMESLOT_PERIOD_NS(100000), - .ACTIVE_PERIOD_S(0), - .ACTIVE_PERIOD_NS(90000) -) -tdma_ber_inst ( - .clk(clk_300mhz), - .rst(rst_300mhz), - .phy_tx_clk({sfp1_tx_clk, sfp0_tx_clk}), - .phy_rx_clk({sfp1_rx_clk, sfp0_rx_clk}), - .phy_rx_error_count({sfp1_rx_error_count, sfp0_rx_error_count}), - .phy_tx_prbs31_enable({sfp1_tx_prbs31_enable, sfp0_tx_prbs31_enable}), - .phy_rx_prbs31_enable({sfp1_rx_prbs31_enable, sfp0_rx_prbs31_enable}), - .s_axil_awaddr(axil_csr_awaddr), - .s_axil_awprot(axil_csr_awprot), - .s_axil_awvalid(axil_csr_awvalid), - .s_axil_awready(axil_csr_awready), - .s_axil_wdata(axil_csr_wdata), - .s_axil_wstrb(axil_csr_wstrb), - .s_axil_wvalid(axil_csr_wvalid), - .s_axil_wready(axil_csr_wready), - .s_axil_bresp(axil_csr_bresp), - .s_axil_bvalid(axil_csr_bvalid), - .s_axil_bready(axil_csr_bready), - .s_axil_araddr(axil_csr_araddr), - .s_axil_arprot(axil_csr_arprot), - .s_axil_arvalid(axil_csr_arvalid), - .s_axil_arready(axil_csr_arready), - .s_axil_rdata(axil_csr_rdata), - .s_axil_rresp(axil_csr_rresp), - .s_axil_rvalid(axil_csr_rvalid), - .s_axil_rready(axil_csr_rready), - .ptp_ts_96(ptp_sync_ts_96), - .ptp_ts_step(ptp_sync_ts_step) -); +generate + +if (TDMA_BER_ENABLE) begin + + // BER tester + tdma_ber #( + .COUNT(2), + .INDEX_WIDTH(6), + .SLICE_WIDTH(5), + .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .AXIL_ADDR_WIDTH(8+6+$clog2(2)), + .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .SCHEDULE_START_S(0), + .SCHEDULE_START_NS(0), + .SCHEDULE_PERIOD_S(0), + .SCHEDULE_PERIOD_NS(1000000), + .TIMESLOT_PERIOD_S(0), + .TIMESLOT_PERIOD_NS(100000), + .ACTIVE_PERIOD_S(0), + .ACTIVE_PERIOD_NS(90000) + ) + tdma_ber_inst ( + .clk(clk_300mhz), + .rst(rst_300mhz), + .phy_tx_clk({sfp1_tx_clk, sfp0_tx_clk}), + .phy_rx_clk({sfp1_rx_clk, sfp0_rx_clk}), + .phy_rx_error_count({sfp1_rx_error_count, sfp0_rx_error_count}), + .phy_tx_prbs31_enable({sfp1_tx_prbs31_enable, sfp0_tx_prbs31_enable}), + .phy_rx_prbs31_enable({sfp1_rx_prbs31_enable, sfp0_rx_prbs31_enable}), + .s_axil_awaddr(axil_csr_awaddr), + .s_axil_awprot(axil_csr_awprot), + .s_axil_awvalid(axil_csr_awvalid), + .s_axil_awready(axil_csr_awready), + .s_axil_wdata(axil_csr_wdata), + .s_axil_wstrb(axil_csr_wstrb), + .s_axil_wvalid(axil_csr_wvalid), + .s_axil_wready(axil_csr_wready), + .s_axil_bresp(axil_csr_bresp), + .s_axil_bvalid(axil_csr_bvalid), + .s_axil_bready(axil_csr_bready), + .s_axil_araddr(axil_csr_araddr), + .s_axil_arprot(axil_csr_arprot), + .s_axil_arvalid(axil_csr_arvalid), + .s_axil_arready(axil_csr_arready), + .s_axil_rdata(axil_csr_rdata), + .s_axil_rresp(axil_csr_rresp), + .s_axil_rvalid(axil_csr_rvalid), + .s_axil_rready(axil_csr_rready), + .ptp_ts_96(ptp_sync_ts_96), + .ptp_ts_step(ptp_sync_ts_step) + ); + +end else begin + + assign sfp0_tx_prbs31_enable = 1'b0; + assign sfp0_rx_prbs31_enable = 1'b0; + assign sfp1_tx_prbs31_enable = 1'b0; + assign sfp1_rx_prbs31_enable = 1'b0; + +end + +endgenerate assign led[0] = pps_led_reg; assign led[7:1] = 0; @@ -833,7 +851,7 @@ mqnic_core_axi #( .AXIL_CTRL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), .AXIL_IF_CTRL_ADDR_WIDTH(AXIL_IF_CTRL_ADDR_WIDTH), .AXIL_CSR_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .AXIL_CSR_PASSTHROUGH_ENABLE(1), + .AXIL_CSR_PASSTHROUGH_ENABLE(TDMA_BER_ENABLE), .RB_NEXT_PTR(RB_BASE_ADDR), // AXI lite interface configuration (application control) diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl b/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl index 18863ddc4..66243517b 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl @@ -80,6 +80,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params TDMA_BER_ENABLE "0" + # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {25.78125} diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl index 87ab5440a..8c688fac6 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl @@ -80,6 +80,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params TDMA_BER_ENABLE "0" + # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {10.3125} diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl index 02ac80998..a3c0cdbb4 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl @@ -80,6 +80,9 @@ dict set params BUILD_DATE "32'd${build_date}" dict set params GIT_HASH "32'h${git_hash}" dict set params RELEASE_INFO [format "32'h%08x" $release_info] +# Board configuration +dict set params TDMA_BER_ENABLE "1" + # Transceiver configuration set eth_xcvr_freerun_freq {125} set eth_xcvr_line_rate {25.78125} diff --git a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v index 3eb18c1d0..070339c05 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v @@ -52,6 +52,9 @@ module fpga # parameter GIT_HASH = 32'hdce357bf, parameter RELEASE_INFO = 32'h00000000, + // Board configuration + parameter TDMA_BER_ENABLE = 0, + // Structural configuration parameter IF_COUNT = 2, parameter PORTS_PER_IF = 1, @@ -1390,6 +1393,9 @@ fpga_core #( .GIT_HASH(GIT_HASH), .RELEASE_INFO(RELEASE_INFO), + // Board configuration + .TDMA_BER_ENABLE(TDMA_BER_ENABLE), + // Structural configuration .IF_COUNT(IF_COUNT), .PORTS_PER_IF(PORTS_PER_IF), diff --git a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v index 477d87a0e..a71bebeaa 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v @@ -52,6 +52,9 @@ module fpga_core # parameter GIT_HASH = 32'hdce357bf, parameter RELEASE_INFO = 32'h00000000, + // Board configuration + parameter TDMA_BER_ENABLE = 0, + // Structural configuration parameter IF_COUNT = 2, parameter PORTS_PER_IF = 1, @@ -886,53 +889,80 @@ always @(posedge ptp_clk) begin pps_led_reg <= pps_led_counter_reg > 0; end -// BER tester -tdma_ber #( - .COUNT(8), - .INDEX_WIDTH(6), - .SLICE_WIDTH(5), - .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), - .AXIL_ADDR_WIDTH(8+6+$clog2(8)), - .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), - .SCHEDULE_START_S(0), - .SCHEDULE_START_NS(0), - .SCHEDULE_PERIOD_S(0), - .SCHEDULE_PERIOD_NS(1000000), - .TIMESLOT_PERIOD_S(0), - .TIMESLOT_PERIOD_NS(100000), - .ACTIVE_PERIOD_S(0), - .ACTIVE_PERIOD_NS(90000) -) -tdma_ber_inst ( - .clk(clk_250mhz), - .rst(rst_250mhz), - .phy_tx_clk({qsfp_1_tx_clk_3, qsfp_1_tx_clk_2, qsfp_1_tx_clk_1, qsfp_1_tx_clk_0, qsfp_0_tx_clk_3, qsfp_0_tx_clk_2, qsfp_0_tx_clk_1, qsfp_0_tx_clk_0}), - .phy_rx_clk({qsfp_1_rx_clk_3, qsfp_1_rx_clk_2, qsfp_1_rx_clk_1, qsfp_1_rx_clk_0, qsfp_0_rx_clk_3, qsfp_0_rx_clk_2, qsfp_0_rx_clk_1, qsfp_0_rx_clk_0}), - .phy_rx_error_count({qsfp_1_rx_error_count_3, qsfp_1_rx_error_count_2, qsfp_1_rx_error_count_1, qsfp_1_rx_error_count_0, qsfp_0_rx_error_count_3, qsfp_0_rx_error_count_2, qsfp_0_rx_error_count_1, qsfp_0_rx_error_count_0}), - .phy_tx_prbs31_enable({qsfp_1_tx_prbs31_enable_3, qsfp_1_tx_prbs31_enable_2, qsfp_1_tx_prbs31_enable_1, qsfp_1_tx_prbs31_enable_0, qsfp_0_tx_prbs31_enable_3, qsfp_0_tx_prbs31_enable_2, qsfp_0_tx_prbs31_enable_1, qsfp_0_tx_prbs31_enable_0}), - .phy_rx_prbs31_enable({qsfp_1_rx_prbs31_enable_3, qsfp_1_rx_prbs31_enable_2, qsfp_1_rx_prbs31_enable_1, qsfp_1_rx_prbs31_enable_0, qsfp_0_rx_prbs31_enable_3, qsfp_0_rx_prbs31_enable_2, qsfp_0_rx_prbs31_enable_1, qsfp_0_rx_prbs31_enable_0}), - .s_axil_awaddr(axil_csr_awaddr), - .s_axil_awprot(axil_csr_awprot), - .s_axil_awvalid(axil_csr_awvalid), - .s_axil_awready(axil_csr_awready), - .s_axil_wdata(axil_csr_wdata), - .s_axil_wstrb(axil_csr_wstrb), - .s_axil_wvalid(axil_csr_wvalid), - .s_axil_wready(axil_csr_wready), - .s_axil_bresp(axil_csr_bresp), - .s_axil_bvalid(axil_csr_bvalid), - .s_axil_bready(axil_csr_bready), - .s_axil_araddr(axil_csr_araddr), - .s_axil_arprot(axil_csr_arprot), - .s_axil_arvalid(axil_csr_arvalid), - .s_axil_arready(axil_csr_arready), - .s_axil_rdata(axil_csr_rdata), - .s_axil_rresp(axil_csr_rresp), - .s_axil_rvalid(axil_csr_rvalid), - .s_axil_rready(axil_csr_rready), - .ptp_ts_96(ptp_sync_ts_96), - .ptp_ts_step(ptp_sync_ts_step) -); +generate + +if (TDMA_BER_ENABLE) begin + + // BER tester + tdma_ber #( + .COUNT(8), + .INDEX_WIDTH(6), + .SLICE_WIDTH(5), + .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .AXIL_ADDR_WIDTH(8+6+$clog2(8)), + .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .SCHEDULE_START_S(0), + .SCHEDULE_START_NS(0), + .SCHEDULE_PERIOD_S(0), + .SCHEDULE_PERIOD_NS(1000000), + .TIMESLOT_PERIOD_S(0), + .TIMESLOT_PERIOD_NS(100000), + .ACTIVE_PERIOD_S(0), + .ACTIVE_PERIOD_NS(90000) + ) + tdma_ber_inst ( + .clk(clk_250mhz), + .rst(rst_250mhz), + .phy_tx_clk({qsfp_1_tx_clk_3, qsfp_1_tx_clk_2, qsfp_1_tx_clk_1, qsfp_1_tx_clk_0, qsfp_0_tx_clk_3, qsfp_0_tx_clk_2, qsfp_0_tx_clk_1, qsfp_0_tx_clk_0}), + .phy_rx_clk({qsfp_1_rx_clk_3, qsfp_1_rx_clk_2, qsfp_1_rx_clk_1, qsfp_1_rx_clk_0, qsfp_0_rx_clk_3, qsfp_0_rx_clk_2, qsfp_0_rx_clk_1, qsfp_0_rx_clk_0}), + .phy_rx_error_count({qsfp_1_rx_error_count_3, qsfp_1_rx_error_count_2, qsfp_1_rx_error_count_1, qsfp_1_rx_error_count_0, qsfp_0_rx_error_count_3, qsfp_0_rx_error_count_2, qsfp_0_rx_error_count_1, qsfp_0_rx_error_count_0}), + .phy_tx_prbs31_enable({qsfp_1_tx_prbs31_enable_3, qsfp_1_tx_prbs31_enable_2, qsfp_1_tx_prbs31_enable_1, qsfp_1_tx_prbs31_enable_0, qsfp_0_tx_prbs31_enable_3, qsfp_0_tx_prbs31_enable_2, qsfp_0_tx_prbs31_enable_1, qsfp_0_tx_prbs31_enable_0}), + .phy_rx_prbs31_enable({qsfp_1_rx_prbs31_enable_3, qsfp_1_rx_prbs31_enable_2, qsfp_1_rx_prbs31_enable_1, qsfp_1_rx_prbs31_enable_0, qsfp_0_rx_prbs31_enable_3, qsfp_0_rx_prbs31_enable_2, qsfp_0_rx_prbs31_enable_1, qsfp_0_rx_prbs31_enable_0}), + .s_axil_awaddr(axil_csr_awaddr), + .s_axil_awprot(axil_csr_awprot), + .s_axil_awvalid(axil_csr_awvalid), + .s_axil_awready(axil_csr_awready), + .s_axil_wdata(axil_csr_wdata), + .s_axil_wstrb(axil_csr_wstrb), + .s_axil_wvalid(axil_csr_wvalid), + .s_axil_wready(axil_csr_wready), + .s_axil_bresp(axil_csr_bresp), + .s_axil_bvalid(axil_csr_bvalid), + .s_axil_bready(axil_csr_bready), + .s_axil_araddr(axil_csr_araddr), + .s_axil_arprot(axil_csr_arprot), + .s_axil_arvalid(axil_csr_arvalid), + .s_axil_arready(axil_csr_arready), + .s_axil_rdata(axil_csr_rdata), + .s_axil_rresp(axil_csr_rresp), + .s_axil_rvalid(axil_csr_rvalid), + .s_axil_rready(axil_csr_rready), + .ptp_ts_96(ptp_sync_ts_96), + .ptp_ts_step(ptp_sync_ts_step) + ); + +end else begin + + assign qsfp_0_tx_prbs31_enable_0 = 1'b0; + assign qsfp_0_rx_prbs31_enable_0 = 1'b0; + assign qsfp_0_tx_prbs31_enable_1 = 1'b0; + assign qsfp_0_rx_prbs31_enable_1 = 1'b0; + assign qsfp_0_tx_prbs31_enable_2 = 1'b0; + assign qsfp_0_rx_prbs31_enable_2 = 1'b0; + assign qsfp_0_tx_prbs31_enable_3 = 1'b0; + assign qsfp_0_rx_prbs31_enable_3 = 1'b0; + assign qsfp_1_tx_prbs31_enable_0 = 1'b0; + assign qsfp_1_rx_prbs31_enable_0 = 1'b0; + assign qsfp_1_tx_prbs31_enable_1 = 1'b0; + assign qsfp_1_rx_prbs31_enable_1 = 1'b0; + assign qsfp_1_tx_prbs31_enable_2 = 1'b0; + assign qsfp_1_rx_prbs31_enable_2 = 1'b0; + assign qsfp_1_tx_prbs31_enable_3 = 1'b0; + assign qsfp_1_rx_prbs31_enable_3 = 1'b0; + +end + +endgenerate assign led_red = 8'd0; assign led_green = 8'd0; @@ -1213,7 +1243,7 @@ mqnic_core_pcie_us #( .AXIL_CTRL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), .AXIL_IF_CTRL_ADDR_WIDTH(AXIL_IF_CTRL_ADDR_WIDTH), .AXIL_CSR_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), - .AXIL_CSR_PASSTHROUGH_ENABLE(1), + .AXIL_CSR_PASSTHROUGH_ENABLE(TDMA_BER_ENABLE), .RB_NEXT_PTR(RB_BASE_ADDR), // AXI lite interface configuration (application control)