diff --git a/fpga/lib/pcie/README.md b/fpga/lib/pcie/README.md index e62d83d65..24d7e3dd3 100644 --- a/fpga/lib/pcie/README.md +++ b/fpga/lib/pcie/README.md @@ -72,9 +72,11 @@ dual port RAMs, enabling mixing different client interface types and widths and even supporting clients running in different clock domains without datapath FIFOs. -The dma_if_pcie_us module connects the PCIe interface to the segmented memory -interface. Currently, it does not support TLP straddling, but it should be -possible to support this with the segmented interface. +![DMA system block diagram](dma_block.svg) + +The dma_if_pcie_us module connects the Xilinx Ultrascale PCIe interface to the +segmented memory interface. Currently, it does not support TLP straddling, +but it should be possible to support this with the segmented interface. The dma_psdpram module is a dual clock, parallel simple dual port RAM module with a segmented interface. The depth is independently adjustable from the diff --git a/fpga/lib/pcie/dma_block.svg b/fpga/lib/pcie/dma_block.svg new file mode 100644 index 000000000..399d13de8 --- /dev/null +++ b/fpga/lib/pcie/dma_block.svg @@ -0,0 +1,297 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Segmented + + + + + + + + DMA IF + + + + + + Control/status + + + + + + + + + + + + + + + PSDP RAM + + + + + + + + Control + + + + + + + + DMA Client + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + PSDP RAM + + + + + + + + Control + + + + + + + + DMA Client + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/fpga/lib/pcie/example/ADM_PCIE_9V3/fpga_axi_x8/common/vivado.mk b/fpga/lib/pcie/example/ADM_PCIE_9V3/fpga_axi_x8/common/vivado.mk index 964ed04eb..b84025221 100644 --- a/fpga/lib/pcie/example/ADM_PCIE_9V3/fpga_axi_x8/common/vivado.mk +++ b/fpga/lib/pcie/example/ADM_PCIE_9V3/fpga_axi_x8/common/vivado.mk @@ -40,6 +40,7 @@ CONFIG ?= config.mk SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) +IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) ifdef XDC_FILES XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) @@ -59,7 +60,7 @@ all: fpga fpga: $(FPGA_TOP).bit tmpclean: - -rm -rf *.log *.jou *.cache *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf *.log *.jou *.cache *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl clean: tmpclean @@ -82,6 +83,7 @@ distclean: clean for x in $(SYN_FILES_REL); do echo "add_files -fileset sources_1 $$x" >> create_project.tcl; done for x in $(XDC_FILES_REL); do echo "add_files -fileset constrs_1 $$x" >> create_project.tcl; done for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> create_project.tcl; done + for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> create_project.tcl; done echo "exit" >> create_project.tcl vivado -nojournal -nolog -mode batch -source create_project.tcl diff --git a/fpga/lib/pcie/example/ADM_PCIE_9V3/fpga_axi_x8/fpga/Makefile b/fpga/lib/pcie/example/ADM_PCIE_9V3/fpga_axi_x8/fpga/Makefile index 469aecb08..b7de4367c 100644 --- a/fpga/lib/pcie/example/ADM_PCIE_9V3/fpga_axi_x8/fpga/Makefile +++ b/fpga/lib/pcie/example/ADM_PCIE_9V3/fpga_axi_x8/fpga/Makefile @@ -32,7 +32,7 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v XDC_FILES = fpga.xdc # IP -XCI_FILES = ip/pcie4_uscale_plus_0.xci +IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl include ../common/vivado.mk diff --git a/fpga/lib/pcie/example/ADM_PCIE_9V3/fpga_axi_x8/ip/pcie4_uscale_plus_0.tcl b/fpga/lib/pcie/example/ADM_PCIE_9V3/fpga_axi_x8/ip/pcie4_uscale_plus_0.tcl new file mode 100644 index 000000000..504586ec9 --- /dev/null +++ b/fpga/lib/pcie/example/ADM_PCIE_9V3/fpga_axi_x8/ip/pcie4_uscale_plus_0.tcl @@ -0,0 +1,28 @@ + +create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pcie4_uscale_plus_0 + +set_property -dict [list \ + CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ + CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \ + CONFIG.AXISTEN_IF_RC_STRADDLE {false} \ + CONFIG.axisten_if_enable_client_tag {true} \ + CONFIG.axisten_if_width {256_bit} \ + CONFIG.axisten_freq {250} \ + CONFIG.PF0_CLASS_CODE {020000} \ + CONFIG.PF0_DEVICE_ID {0001} \ + CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \ + CONFIG.PF0_SUBSYSTEM_ID {0001} \ + CONFIG.PF0_SUBSYSTEM_VENDOR_ID {1234} \ + CONFIG.PF0_Use_Class_Code_Lookup_Assistant {true} \ + CONFIG.pf0_class_code_sub {00} \ + CONFIG.pf0_base_class_menu {Network_controller} \ + CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \ + CONFIG.pf0_bar0_scale {Megabytes} \ + CONFIG.pf0_bar0_size {16} \ + CONFIG.pf0_bar1_enabled {true} \ + CONFIG.pf0_bar1_type {Memory} \ + CONFIG.pf0_bar1_scale {Megabytes} \ + CONFIG.pf0_bar1_size {16} \ + CONFIG.vendor_id {1234} \ + CONFIG.en_msi_per_vec_masking {true} \ +] [get_ips pcie4_uscale_plus_0] diff --git a/fpga/lib/pcie/example/ADM_PCIE_9V3/fpga_axi_x8/ip/pcie4_uscale_plus_0.xci b/fpga/lib/pcie/example/ADM_PCIE_9V3/fpga_axi_x8/ip/pcie4_uscale_plus_0.xci deleted file mode 100644 index 65a453ede..000000000 --- a/fpga/lib/pcie/example/ADM_PCIE_9V3/fpga_axi_x8/ip/pcie4_uscale_plus_0.xci +++ /dev/null @@ -1,1284 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - pcie4_uscale_plus_0 - - - - - - 0 - 0.000 - - - - 0 - 0.000 - - - - 100000000 - 0 - 0.000 - - - - 100000000 - 0 - 0.000 - - 0 - 0.000 - - 100000000 - 1 - 1 - 1 - 0 - 0 - undef - 0.000 - 32 - 0 - 0 - 88 - - 100000000 - 1 - 1 - 1 - 0 - 0 - undef - 0.000 - 32 - 0 - 0 - 75 - 0 - ACTIVE_LOW - 0 - - 100000000 - 1 - 1 - 1 - 0 - 0 - undef - 0.000 - 32 - 0 - 0 - 33 - - 100000000 - 1 - 1 - 1 - 0 - 0 - undef - 0.000 - 32 - 0 - 0 - 62 - 0x000 - FALSE - FALSE - 0 - 33 - 88 - 256 - 75 - 62 - 0x0 - 0x0 - TRUE - FALSE - 0x00000 - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - 0x0 - FALSE - 0x0 - FALSE - FALSE - FALSE - TRUE - TRUE - TRUE - TRUE - TRUE - TRUE - TRUE - FALSE - TRUE - 2 - TRUE - FALSE - FALSE - FALSE - 0 - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - 1 - TRUE - 2 - 1 - 0 - ADD-IN_CARD - 0 - FALSE - FALSE - FALSE - 0x000 - NONE - 0x00000000 - FALSE - TRUE - 32 - None - TRUE - FALSE - FALSE - NONE - FALSE - TRUE - FALSE - 0x1C0 - 0x1C0 - 0x00 - 0x011 - 0x4 - 0x011 - 0x4 - 0x000 - 0x0 - 0x000 - 0x0 - 0x000 - 0x0 - 0x000 - 0x0 - 0x40 - 0x020000 - 0x0001 - FALSE - FALSE - FALSE - FALSE - TRUE - FALSE - 0x3 - 0x1C0 - 0x000 - FALSE - 0x0 - 0 - TRUE - 0x70 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 5 - 0x70 - TRUE - 0x48 - FALSE - FALSE - FALSE - FALSE - 0x0 - 0x7 - 0x7 - 0x7 - 0x7 - 0x7 - 0xffffffffffff - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x1 - 0x00 - 0x000 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x0000 - 0x000 - 0x0000 - 0x1 - 0x0000 - 0x0000 - 0x00000553 - 0x0000 - 0x0001 - 0x1234 - TRUE - FALSE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - FALSE - 0x000 - 0x1234 - 0x000 - 0x000 - 0x00 - 0x011 - 0x4 - 0x011 - 0x4 - 0x000 - 0x0 - 0x000 - 0x0 - 0x000 - 0x0 - 0x000 - 0x0 - 0x40 - 0x058000 - 0x9011 - 0x3 - 0x000 - 0x000 - FALSE - 0x0 - 0x70 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x70 - TRUE - 0x70 - 0x0 - 0x7 - 0x7 - 0x7 - 0x7 - 0x7 - 0xffffffffffff - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x1 - 0x00 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x0000 - 0x000 - 0x0000 - 0x1 - 0x0000 - 0x0001 - 0x00000553 - 0x0000 - 0x0007 - 0x000 - 0x0 - 0x000 - 0x000 - 0x00 - 0x011 - 0x4 - 0x011 - 0x4 - 0x000 - 0x0 - 0x000 - 0x0 - 0x000 - 0x0 - 0x000 - 0x0 - 0x40 - 0x058000 - 0x9438 - 0x3 - 0x000 - 0x000 - FALSE - 0x0 - 0x70 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x70 - TRUE - 0x70 - 0x0 - 0x7 - 0x7 - 0x7 - 0x7 - 0x7 - 0xffffffffffff - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x1 - 0x00 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x0000 - 0x000 - 0x0000 - 0x1 - 0x0000 - 0x0002 - 0x00000553 - 0x0000 - 0x0007 - 0x000 - 0x0 - 0x000 - 0x000 - 0x00 - 0x011 - 0x4 - 0x011 - 0x4 - 0x000 - 0x0 - 0x000 - 0x0 - 0x000 - 0x0 - 0x000 - 0x0 - 0x40 - 0x058000 - 0x9638 - 0x3 - 0x000 - 0x000 - FALSE - 0x0 - 0x70 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x70 - TRUE - 0x70 - 0x0 - 0x7 - 0x7 - 0x7 - 0x7 - 0x7 - 0xffffffffffff - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x1 - 0x00 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x0000 - 0x000 - 0x0000 - 0x1 - 0x0000 - 0x0003 - 0x00000553 - 0x0000 - 0x0007 - 0x000 - 0x0 - 4 - 0 - FALSE - 2 - TRUE - FALSE - 4 - 8 - TRUE - FALSE - 0x000 - FALSE - TRUE - GTY_Quad_227 - 1 - 0x00000000 - 0x0 - FALSE - 0 - FALSE - FALSE - 0x2 - 0x000 - 0x00 - 0x004 - 0x20 - 0x3E0 - 0x20 - FALSE - 0 - FALSE - X8G3 - FALSE - TRUE - FALSE - 0x70 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - FALSE - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 6 - Beta - 0 - false - true - true - true - true - true - DWORD_Aligned - false - false - false - true - false - false - DWORD_Aligned - pcie4_uscale_plus_0 - 15 - None - Custom - false - 020000 - 0001 - false - false - false - false - false - NONE - true - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 32_vectors - false - false - false - false - 00 - 0 - 0 - 0000 - 00000553 - 0000 - 0001 - 1234 - true - 058000 - 9011 - NONE - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - 00 - 0 - 1 - 0 - 0001 - 00000553 - 0000 - 0007 - 1234 - false - 058000 - 9438 - NONE - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - 00 - 0 - 1 - 0 - 0002 - 00000553 - 0000 - 0007 - 1234 - false - 058000 - 9638 - NONE - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - 00 - 0 - 1 - 0 - 0003 - 00000553 - 0000 - 0007 - 1234 - false - 4 - true - 8.0_GT/s - X8 - 100_MHz - 0 - 0 - false - false - 1 - Custom - 1 - 1 - 00000000 - 00000000 - 0 - 00000000 - 00000000 - 0 - 00000000 - 00000000 - 0 - 00000000 - 00000000 - 0 - false - DWORD_Aligned - No_ASPM - 0 - 250 - true - 00000 - false - false - 256_bit - false - true - true - true - true - true - true - true - false - true - true - 500 - true - false - false - PCI_Express_Endpoint_device - false - false - false - false - false - false - false - true - false - false - true - false - false - false - false - false - False - false - 0000 - false - false - false - false - false - false - false - false - false - false - false - true - 100_MHz - true - false - false - false - false - false - false - true - false - false - false - false - false - Internal - 2 - 1 - Add-in_Card - false - false - false - None - 00000000 - Basic - HARD - true - X1Y0 - false - true - Extreme - true - false - false - true - 0 - false - Megabytes - 16 - Memory - false - true - 7 - false - Megabytes - 16 - Memory - false - false - 7 - false - Kilobytes - 128 - N/A - false - false - 7 - false - Kilobytes - 128 - N/A - false - false - 7 - false - Kilobytes - 128 - N/A - false - 7 - false - Kilobytes - 128 - N/A - Network_controller - 02 - 00 - 00 - 1024_bytes - false - false - Kilobytes - 2 - true - false - 0xffffffffffff - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 1 - false - true - false - Kilobytes - 2 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - 1 - Ethernet_controller - false - false - false - true - 0 - false - Megabytes - 16 - Memory - false - true - 7 - false - Megabytes - 16 - Memory - false - false - 7 - false - Kilobytes - 128 - N/A - false - false - 7 - false - Kilobytes - 128 - N/A - false - false - 7 - false - Kilobytes - 128 - N/A - false - 7 - false - Kilobytes - 128 - N/A - Memory_controller - 05 - 00 - 80 - false - Kilobytes - 2 - false - false - 0xffffffffffff - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 1 - false - true - false - Kilobytes - 2 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - Other_memory_controller - 1234 - false - true - 0 - false - Megabytes - 16 - Memory - false - true - 7 - false - Megabytes - 16 - Memory - false - false - 7 - false - Kilobytes - 128 - N/A - false - false - 7 - false - Kilobytes - 128 - N/A - false - false - 7 - false - Kilobytes - 128 - N/A - false - 7 - false - Kilobytes - 128 - N/A - Memory_controller - 05 - 00 - 80 - false - Kilobytes - 2 - false - false - 0xffffffffffff - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 1 - false - true - false - Kilobytes - 2 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - Other_memory_controller - 1234 - false - true - 0 - false - Megabytes - 16 - Memory - false - true - 7 - false - Megabytes - 16 - Memory - false - false - 7 - false - Kilobytes - 128 - N/A - false - false - 7 - false - Kilobytes - 128 - N/A - false - false - 7 - false - Kilobytes - 128 - N/A - false - 7 - false - Kilobytes - 128 - N/A - Memory_controller - 05 - 00 - 80 - false - Kilobytes - 2 - false - false - 0xffffffffffff - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 1 - false - true - false - Kilobytes - 2 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - Other_memory_controller - 1234 - false - QPLL1 - false - true - GTY_Quad_227 - false - false - ACTIVE_LOW - false - 15 - 15 - X8G3 - false - true - Enabled - 64bit_Enabled - true - false - 1234 - false - None - virtexuplus - - - xcvu3p - ffvc1517 - VERILOG - - MIXED - -2 - - I - TRUE - TRUE - IP_Flow - 5 - TRUE - . - - . - 2019.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/lib/pcie/example/ExaNIC_X10/fpga_axi/common/vivado.mk b/fpga/lib/pcie/example/ExaNIC_X10/fpga_axi/common/vivado.mk index 964ed04eb..b84025221 100644 --- a/fpga/lib/pcie/example/ExaNIC_X10/fpga_axi/common/vivado.mk +++ b/fpga/lib/pcie/example/ExaNIC_X10/fpga_axi/common/vivado.mk @@ -40,6 +40,7 @@ CONFIG ?= config.mk SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) +IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) ifdef XDC_FILES XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) @@ -59,7 +60,7 @@ all: fpga fpga: $(FPGA_TOP).bit tmpclean: - -rm -rf *.log *.jou *.cache *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf *.log *.jou *.cache *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl clean: tmpclean @@ -82,6 +83,7 @@ distclean: clean for x in $(SYN_FILES_REL); do echo "add_files -fileset sources_1 $$x" >> create_project.tcl; done for x in $(XDC_FILES_REL); do echo "add_files -fileset constrs_1 $$x" >> create_project.tcl; done for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> create_project.tcl; done + for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> create_project.tcl; done echo "exit" >> create_project.tcl vivado -nojournal -nolog -mode batch -source create_project.tcl diff --git a/fpga/lib/pcie/example/ExaNIC_X10/fpga_axi/fpga/Makefile b/fpga/lib/pcie/example/ExaNIC_X10/fpga_axi/fpga/Makefile index 84476e646..c7b6ef167 100644 --- a/fpga/lib/pcie/example/ExaNIC_X10/fpga_axi/fpga/Makefile +++ b/fpga/lib/pcie/example/ExaNIC_X10/fpga_axi/fpga/Makefile @@ -32,7 +32,7 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v XDC_FILES = fpga.xdc # IP -XCI_FILES = ip/pcie3_ultrascale_0.xci +IP_TCL_FILES = ip/pcie3_ultrascale_0.tcl include ../common/vivado.mk diff --git a/fpga/lib/pcie/example/ExaNIC_X10/fpga_axi/ip/pcie3_ultrascale_0.tcl b/fpga/lib/pcie/example/ExaNIC_X10/fpga_axi/ip/pcie3_ultrascale_0.tcl new file mode 100644 index 000000000..ef3e4146d --- /dev/null +++ b/fpga/lib/pcie/example/ExaNIC_X10/fpga_axi/ip/pcie3_ultrascale_0.tcl @@ -0,0 +1,32 @@ + +create_ip -name pcie3_ultrascale -vendor xilinx.com -library ip -module_name pcie3_ultrascale_0 + +set_property -dict [list \ + CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ + CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \ + CONFIG.AXISTEN_IF_RC_STRADDLE {false} \ + CONFIG.axisten_if_width {256_bit} \ + CONFIG.extended_tag_field {true} \ + CONFIG.axisten_freq {250} \ + CONFIG.PF0_CLASS_CODE {020000} \ + CONFIG.PF0_DEVICE_ID {0001} \ + CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \ + CONFIG.PF0_SUBSYSTEM_ID {0001} \ + CONFIG.PF0_SUBSYSTEM_VENDOR_ID {1234} \ + CONFIG.PF0_Use_Class_Code_Lookup_Assistant {true} \ + CONFIG.pf0_base_class_menu {Network_controller} \ + CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \ + CONFIG.pf0_class_code_base {02} \ + CONFIG.pf0_class_code_sub {00} \ + CONFIG.pf0_bar0_scale {Megabytes} \ + CONFIG.pf0_bar0_size {16} \ + CONFIG.pf0_bar1_enabled {true} \ + CONFIG.pf0_bar1_type {Memory} \ + CONFIG.pf0_bar1_scale {Megabytes} \ + CONFIG.pf0_bar1_size {16} \ + CONFIG.PF0_INTERRUPT_PIN {NONE} \ + CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_0} \ + CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_0} \ + CONFIG.vendor_id {1234} \ + CONFIG.en_msi_per_vec_masking {true} \ +] [get_ips pcie3_ultrascale_0] diff --git a/fpga/lib/pcie/example/ExaNIC_X10/fpga_axi/ip/pcie3_ultrascale_0.xci b/fpga/lib/pcie/example/ExaNIC_X10/fpga_axi/ip/pcie3_ultrascale_0.xci deleted file mode 100644 index 0e872a83f..000000000 --- a/fpga/lib/pcie/example/ExaNIC_X10/fpga_axi/ip/pcie3_ultrascale_0.xci +++ /dev/null @@ -1,899 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - pcie3_ultrascale_0 - - - - - - 100000000 - 0 - 0.000 - - - - 100000000 - 0 - 0.000 - - 0 - 0.000 - - 100000000 - 1 - 1 - 1 - 0 - 0 - undef - 0.000 - 32 - 0 - 0 - 85 - - 100000000 - 1 - 1 - 1 - 0 - 0 - undef - 0.000 - 32 - 0 - 0 - 75 - 0 - ACTIVE_LOW - 0 - - 100000000 - 1 - 1 - 1 - 0 - 0 - undef - 0.000 - 32 - 0 - 0 - 33 - - 100000000 - 1 - 1 - 1 - 0 - 0 - undef - 0.000 - 32 - 0 - 0 - 60 - 0x000 - FALSE - FALSE - FALSE - FALSE - FALSE - TRUE - 0x00000 - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - TRUE - TRUE - TRUE - TRUE - TRUE - TRUE - 16KB - 2 - 256 - FALSE - TRUE - 0 - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - 0 - 1 - 0 - Add-in_Card - 0x000 - NONE - 0x00000000 - FALSE - TRUE - FALSE - FALSE - FALSE - NONE - 3 - 2.0 - TRUE - FALSE - FALSE - 0x300 - 0x000 - 0x00 - 0x11 - 0x4 - 0x11 - 0x4 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x80 - 0x020000 - 0x0001 - FALSE - FALSE - FALSE - FALSE - 0x0 - FALSE - TRUE - FALSE - 0x2 - 0x300 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x300 - 0x00 - FALSE - 0x1 - 0 - TRUE - 0x300 - 0x00 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 5 - 0xC0 - 0x274 - 0x90 - FALSE - FALSE - FALSE - FALSE - FALSE - 0x300 - 0x00000 - 0x00000 - 0x00000 - 0x00 - 0x000 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x0000 - 0x300 - 0x0000 - 0x0 - 0x0000 - 0x0000 - 0x00000553 - 0x0000 - 0x0001 - 0x1234 - TRUE - FALSE - FALSE - 0x300 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0x1234 - FALSE - FALSE - 0x000 - 0x000 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x80 - 0x058000 - 0x8011 - 0x2 - 0x000 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x000 - 0x00 - FALSE - 0x0 - 0x00 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - 0x000 - 0x00 - FALSE - 0x000 - 0x00000 - 0x00000 - 0x00000 - 0x00 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x0000 - 0x000 - 0x0000 - 0x0 - 0x0000 - 0x0001 - 0x00000553 - 0x0000 - 0x0007 - TRUE - FALSE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 4 - FALSE - 2 - FALSE - 4 - 8 - TRUE - FALSE - TRUE - 0 - 0 - GTH_Quad_225 - 1 - 0x00000000 - FALSE - 0 - 0x000 - 0x00 - 0x028 - 0x20 - 0x198 - 0x20 - FALSE - FALSE - 0x0 - FALSE - TRUE - 3 - 0x000 - 0x80 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - FALSE - 1 - 0 - 0 - 0 - 0 - 0 - 0 - Production - 0 - true - false - pcie3_ultrascale_0 - 15 - false - false - 020000 - 0001 - false - false - false - 00_Not_Supported - false - false - INTA - true - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 32_vectors - false - false - false - false - 00 - 0 - N/A - 0000 - 00000553 - 0000 - 0001 - 1234 - false - false - false - 058000 - 8011 - NONE - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - 00 - 0 - 0 - N/A - 0001 - 00000553 - 0000 - 0007 - false - 4 - 8.0_GT/s - X8 - 100_MHz - Default - 0 - 0 - false - false - 1 - false - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - false - DWORD_Aligned - No_ASPM - 250 - true - 2FFFF - false - false - 256_bit - false - None - true - true - true - true - true - true - 500 - true - PCI_Express_Endpoint_device - false - false - false - false - true - false - false - false - false - false - false - false - false - False - false - false - false - false - false - false - true - 100_MHz - true - false - false - false - false - false - Internal - 1 - Add-in_Card - None - 00000000 - Basic - false - X0Y0 - true - Extreme - false - true - false - false - true - false - Megabytes - 16 - Memory - false - true - false - Megabytes - 16 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - Network_controller - 02 - 00 - 00 - 512_bytes - false - false - false - Kilobytes - 2 - false - true - false - false - false - false - true - false - Kilobytes - 2 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - 0 - Ethernet_controller - false - false - true - false - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - Memory_controller - 05 - 00 - 80 - 512_bytes - false - false - false - Kilobytes - 2 - true - false - false - false - false - true - false - Kilobytes - 2 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - Other_memory_controller - false - false - QPLL1 - None - true - GTH_Quad_225 - false - ACTIVE_LOW - None - true - true - 1234 - None - kintexu - - - xcku035 - fbva676 - VERILOG - - MIXED - -2 - - E - TRUE - TRUE - IP_Flow - 5 - TRUE - . - - . - 2019.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/lib/pcie/example/ExaNIC_X25/fpga_axi/common/vivado.mk b/fpga/lib/pcie/example/ExaNIC_X25/fpga_axi/common/vivado.mk index 964ed04eb..b84025221 100644 --- a/fpga/lib/pcie/example/ExaNIC_X25/fpga_axi/common/vivado.mk +++ b/fpga/lib/pcie/example/ExaNIC_X25/fpga_axi/common/vivado.mk @@ -40,6 +40,7 @@ CONFIG ?= config.mk SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) +IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) ifdef XDC_FILES XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) @@ -59,7 +60,7 @@ all: fpga fpga: $(FPGA_TOP).bit tmpclean: - -rm -rf *.log *.jou *.cache *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf *.log *.jou *.cache *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl clean: tmpclean @@ -82,6 +83,7 @@ distclean: clean for x in $(SYN_FILES_REL); do echo "add_files -fileset sources_1 $$x" >> create_project.tcl; done for x in $(XDC_FILES_REL); do echo "add_files -fileset constrs_1 $$x" >> create_project.tcl; done for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> create_project.tcl; done + for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> create_project.tcl; done echo "exit" >> create_project.tcl vivado -nojournal -nolog -mode batch -source create_project.tcl diff --git a/fpga/lib/pcie/example/ExaNIC_X25/fpga_axi/fpga/Makefile b/fpga/lib/pcie/example/ExaNIC_X25/fpga_axi/fpga/Makefile index 14ada5091..007439126 100644 --- a/fpga/lib/pcie/example/ExaNIC_X25/fpga_axi/fpga/Makefile +++ b/fpga/lib/pcie/example/ExaNIC_X25/fpga_axi/fpga/Makefile @@ -32,7 +32,7 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v XDC_FILES = fpga.xdc # IP -XCI_FILES = ip/pcie4_uscale_plus_0.xci +IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl include ../common/vivado.mk diff --git a/fpga/lib/pcie/example/ExaNIC_X25/fpga_axi/ip/pcie4_uscale_plus_0.tcl b/fpga/lib/pcie/example/ExaNIC_X25/fpga_axi/ip/pcie4_uscale_plus_0.tcl new file mode 100644 index 000000000..0ae73b335 --- /dev/null +++ b/fpga/lib/pcie/example/ExaNIC_X25/fpga_axi/ip/pcie4_uscale_plus_0.tcl @@ -0,0 +1,33 @@ + +create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pcie4_uscale_plus_0 + +set_property -dict [list \ + CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ + CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \ + CONFIG.AXISTEN_IF_RC_STRADDLE {false} \ + CONFIG.axisten_if_enable_client_tag {true} \ + CONFIG.axisten_if_width {256_bit} \ + CONFIG.extended_tag_field {true} \ + CONFIG.axisten_freq {250} \ + CONFIG.PF0_CLASS_CODE {020000} \ + CONFIG.PF0_DEVICE_ID {0001} \ + CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \ + CONFIG.PF0_SUBSYSTEM_ID {0001} \ + CONFIG.PF0_SUBSYSTEM_VENDOR_ID {1234} \ + CONFIG.PF0_Use_Class_Code_Lookup_Assistant {true} \ + CONFIG.pf0_class_code_base {02} \ + CONFIG.pf0_class_code_sub {00} \ + CONFIG.pf0_base_class_menu {Network_controller} \ + CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \ + CONFIG.pf0_bar0_scale {Megabytes} \ + CONFIG.pf0_bar0_size {16} \ + CONFIG.pf0_bar1_enabled {true} \ + CONFIG.pf0_bar1_type {Memory} \ + CONFIG.pf0_bar1_scale {Megabytes} \ + CONFIG.pf0_bar1_size {16} \ + CONFIG.vendor_id {1234} \ + CONFIG.en_msi_per_vec_masking {true} \ + CONFIG.mode_selection {Advanced} \ + CONFIG.en_gt_selection {true} \ + CONFIG.MASTER_GT {GTYE4_CHANNEL_X0Y7} \ +] [get_ips pcie4_uscale_plus_0] diff --git a/fpga/lib/pcie/example/ExaNIC_X25/fpga_axi/ip/pcie4_uscale_plus_0.xci b/fpga/lib/pcie/example/ExaNIC_X25/fpga_axi/ip/pcie4_uscale_plus_0.xci deleted file mode 100644 index 54cafe420..000000000 --- a/fpga/lib/pcie/example/ExaNIC_X25/fpga_axi/ip/pcie4_uscale_plus_0.xci +++ /dev/null @@ -1,1294 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - pcie4_uscale_plus_0 - - - - - - 0 - 0.000 - - - - 0 - 0.000 - - - - 100000000 - 0 - 0.000 - - - - 100000000 - 0 - 0.000 - - 0 - 0.000 - - 100000000 - 1 - 1 - 1 - 0 - 0 - undef - 0.000 - 32 - 0 - 0 - 88 - - 100000000 - 1 - 1 - 1 - 0 - 0 - undef - 0.000 - 32 - 0 - 0 - 75 - 0 - ACTIVE_LOW - 0 - - 100000000 - 1 - 1 - 1 - 0 - 0 - undef - 0.000 - 32 - 0 - 0 - 33 - - 100000000 - 1 - 1 - 1 - 0 - 0 - undef - 0.000 - 32 - 0 - 0 - 62 - 0x000 - FALSE - FALSE - 0 - 33 - 88 - 256 - 75 - 62 - 0x0 - 0x0 - TRUE - FALSE - 0x00000 - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - 0x0 - FALSE - 0x0 - FALSE - FALSE - FALSE - TRUE - TRUE - TRUE - TRUE - TRUE - TRUE - TRUE - FALSE - TRUE - 2 - TRUE - FALSE - FALSE - FALSE - 0 - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - TRUE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - 0 - TRUE - 2 - 1 - 0 - ADD-IN_CARD - 0 - FALSE - FALSE - FALSE - 0x000 - NONE - 0x00000000 - FALSE - TRUE - 32 - None - TRUE - FALSE - FALSE - NONE - FALSE - TRUE - FALSE - 0x1C0 - 0x1C0 - 0x04 - 0x011 - 0x4 - 0x011 - 0x4 - 0x000 - 0x0 - 0x000 - 0x0 - 0x000 - 0x0 - 0x000 - 0x0 - 0x40 - 0x020000 - 0x0001 - FALSE - FALSE - FALSE - FALSE - TRUE - FALSE - 0x3 - 0x1C0 - 0x000 - FALSE - 0x0 - 0 - TRUE - 0x70 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 5 - 0x70 - TRUE - 0x48 - FALSE - FALSE - FALSE - FALSE - 000 - 0x7 - 0x7 - 0x7 - 0x7 - 0x7 - 0xffffffffffff - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 001 - 0x00 - 0x000 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x0000 - 0x000 - 0x0000 - 0x1 - 0x0000 - 0x0000 - 0x00000553 - 0x0000 - 0x0001 - 0x1234 - TRUE - FALSE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - FALSE - 0x000 - 0x1234 - 0x000 - 0x000 - 0x04 - 0x011 - 0x4 - 0x011 - 0x4 - 0x000 - 0x0 - 0x000 - 0x0 - 0x000 - 0x0 - 0x000 - 0x0 - 0x40 - 0x058000 - 0x9011 - 0x3 - 0x000 - 0x000 - FALSE - 0x0 - 0x70 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x70 - TRUE - 0x70 - 000 - 0x7 - 0x7 - 0x7 - 0x7 - 0x7 - 0xffffffffffff - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 001 - 0x00 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x0000 - 0x000 - 0x0000 - 0x1 - 0x0000 - 0x0001 - 0x00000553 - 0x0000 - 0x0007 - 0x000 - 0x0 - 0x000 - 0x000 - 0x04 - 0x011 - 0x4 - 0x011 - 0x4 - 0x000 - 0x0 - 0x000 - 0x0 - 0x000 - 0x0 - 0x000 - 0x0 - 0x40 - 0x058000 - 0x9438 - 0x3 - 0x000 - 0x000 - FALSE - 0x0 - 0x70 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x70 - TRUE - 0x70 - 000 - 0x7 - 0x7 - 0x7 - 0x7 - 0x7 - 0xffffffffffff - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 001 - 0x00 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x0000 - 0x000 - 0x0000 - 0x1 - 0x0000 - 0x0002 - 0x00000553 - 0x0000 - 0x0007 - 0x000 - 0x0 - 0x000 - 0x000 - 0x04 - 0x011 - 0x4 - 0x011 - 0x4 - 0x000 - 0x0 - 0x000 - 0x0 - 0x000 - 0x0 - 0x000 - 0x0 - 0x40 - 0x058000 - 0x9638 - 0x3 - 0x000 - 0x000 - FALSE - 0x0 - 0x70 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x70 - TRUE - 0x70 - 000 - 0x7 - 0x7 - 0x7 - 0x7 - 0x7 - 0xffffffffffff - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 001 - 0x00 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x0000 - 0x000 - 0x0000 - 0x1 - 0x0000 - 0x0003 - 0x00000553 - 0x0000 - 0x0007 - 0x000 - 0x0 - 4 - 0 - FALSE - 2 - TRUE - FALSE - 4 - 8 - TRUE - FALSE - 0x000 - FALSE - TRUE - GTY_Quad_225 - 1 - 0x00000000 - 0000 - FALSE - 0 - FALSE - FALSE - 0x2 - 0x000 - 0x00 - 0x004 - 0x20 - 0x3E0 - 0x20 - FALSE - 0 - FALSE - X8G3 - FALSE - TRUE - FALSE - 0x70 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - FALSE - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - Beta - 0 - false - true - true - true - true - true - DWORD_Aligned - false - false - false - true - false - false - DWORD_Aligned - pcie4_uscale_plus_0 - 15 - None - Custom - false - 020000 - 0001 - false - false - false - false - false - NONE - true - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 32_vectors - false - false - false - false - 00 - 0 - 0 - 0000 - 00000553 - 0000 - 0001 - 1234 - true - 058000 - 9011 - NONE - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - 00 - 0 - 1 - 0 - 0001 - 00000553 - 0000 - 0007 - 1234 - false - 058000 - 9438 - NONE - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - 00 - 0 - 1 - 0 - 0002 - 00000553 - 0000 - 0007 - 1234 - false - 058000 - 9638 - NONE - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - 00 - 0 - 1 - 0 - 0003 - 00000553 - 0000 - 0007 - 1234 - false - 4 - true - 8.0_GT/s - X8 - 100_MHz - 0 - 0 - false - false - 1 - Custom - 1 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - false - DWORD_Aligned - No_ASPM - 0 - 250 - true - 00000 - false - false - 256_bit - false - true - true - true - true - true - true - true - false - true - true - 500 - true - false - false - PCI_Express_Endpoint_device - false - false - false - false - false - false - false - true - true - false - true - false - false - false - false - false - False - false - 0000 - false - false - false - false - false - false - false - false - false - false - false - true - 100_MHz - true - true - false - false - false - false - false - false - false - false - false - false - false - Internal - 2 - 1 - Add-in_Card - false - false - false - None - 00000000 - Advanced - HARD - true - X0Y0 - false - true - Extreme - true - false - false - true - 0 - false - Megabytes - 16 - Memory - false - true - 7 - false - Megabytes - 16 - Memory - false - false - 7 - false - Kilobytes - 128 - N/A - false - false - 7 - false - Kilobytes - 128 - N/A - false - false - 7 - false - Kilobytes - 128 - N/A - false - 7 - false - Kilobytes - 128 - N/A - Network_controller - 02 - 00 - 00 - 1024_bytes - false - false - Kilobytes - 2 - true - false - 0xffffffffffff - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 1 - false - true - false - Kilobytes - 2 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - 1 - Ethernet_controller - false - false - false - true - 0 - false - Megabytes - 16 - Memory - false - true - 7 - false - Megabytes - 16 - Memory - false - false - 7 - false - Kilobytes - 128 - N/A - false - false - 7 - false - Kilobytes - 128 - N/A - false - false - 7 - false - Kilobytes - 128 - N/A - false - 7 - false - Kilobytes - 128 - N/A - Memory_controller - 05 - 00 - 80 - false - Kilobytes - 2 - false - false - 0xffffffffffff - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 1 - false - true - false - Kilobytes - 2 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - Other_memory_controller - 1234 - false - true - 0 - false - Megabytes - 16 - Memory - false - true - 7 - false - Megabytes - 16 - Memory - false - false - 7 - false - Kilobytes - 128 - N/A - false - false - 7 - false - Kilobytes - 128 - N/A - false - false - 7 - false - Kilobytes - 128 - N/A - false - 7 - false - Kilobytes - 128 - N/A - Memory_controller - 05 - 00 - 80 - false - Kilobytes - 2 - false - false - 0xffffffffffff - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 1 - false - true - false - Kilobytes - 2 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - Other_memory_controller - 1234 - false - true - 0 - false - Megabytes - 16 - Memory - false - true - 7 - false - Megabytes - 16 - Memory - false - false - 7 - false - Kilobytes - 128 - N/A - false - false - 7 - false - Kilobytes - 128 - N/A - false - false - 7 - false - Kilobytes - 128 - N/A - false - 7 - false - Kilobytes - 128 - N/A - Memory_controller - 05 - 00 - 80 - false - Kilobytes - 2 - false - false - 0xffffffffffff - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 1 - false - true - false - Kilobytes - 2 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - Other_memory_controller - 1234 - false - QPLL1 - false - true - GTY_Quad_225 - false - false - ACTIVE_LOW - false - 15 - 15 - X8G3 - false - true - Enabled - 64bit_Enabled - true - false - 1234 - false - None - kintexuplus - - - xcku3p - ffvb676 - VERILOG - - MIXED - -2 - - E - TRUE - TRUE - IP_Flow - 5 - TRUE - . - - . - 2019.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/lib/pcie/example/VCU108/fpga_axi/common/vivado.mk b/fpga/lib/pcie/example/VCU108/fpga_axi/common/vivado.mk index 964ed04eb..b84025221 100644 --- a/fpga/lib/pcie/example/VCU108/fpga_axi/common/vivado.mk +++ b/fpga/lib/pcie/example/VCU108/fpga_axi/common/vivado.mk @@ -40,6 +40,7 @@ CONFIG ?= config.mk SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) +IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) ifdef XDC_FILES XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) @@ -59,7 +60,7 @@ all: fpga fpga: $(FPGA_TOP).bit tmpclean: - -rm -rf *.log *.jou *.cache *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf *.log *.jou *.cache *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl clean: tmpclean @@ -82,6 +83,7 @@ distclean: clean for x in $(SYN_FILES_REL); do echo "add_files -fileset sources_1 $$x" >> create_project.tcl; done for x in $(XDC_FILES_REL); do echo "add_files -fileset constrs_1 $$x" >> create_project.tcl; done for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> create_project.tcl; done + for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> create_project.tcl; done echo "exit" >> create_project.tcl vivado -nojournal -nolog -mode batch -source create_project.tcl diff --git a/fpga/lib/pcie/example/VCU108/fpga_axi/fpga/Makefile b/fpga/lib/pcie/example/VCU108/fpga_axi/fpga/Makefile index 9b2688ac2..c653c112a 100644 --- a/fpga/lib/pcie/example/VCU108/fpga_axi/fpga/Makefile +++ b/fpga/lib/pcie/example/VCU108/fpga_axi/fpga/Makefile @@ -32,7 +32,7 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v XDC_FILES = fpga.xdc # IP -XCI_FILES = ip/pcie3_ultrascale_0.xci +IP_TCL_FILES = ip/pcie3_ultrascale_0.tcl include ../common/vivado.mk diff --git a/fpga/lib/pcie/example/VCU108/fpga_axi/ip/pcie3_ultrascale_0.tcl b/fpga/lib/pcie/example/VCU108/fpga_axi/ip/pcie3_ultrascale_0.tcl new file mode 100644 index 000000000..ef3e4146d --- /dev/null +++ b/fpga/lib/pcie/example/VCU108/fpga_axi/ip/pcie3_ultrascale_0.tcl @@ -0,0 +1,32 @@ + +create_ip -name pcie3_ultrascale -vendor xilinx.com -library ip -module_name pcie3_ultrascale_0 + +set_property -dict [list \ + CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ + CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \ + CONFIG.AXISTEN_IF_RC_STRADDLE {false} \ + CONFIG.axisten_if_width {256_bit} \ + CONFIG.extended_tag_field {true} \ + CONFIG.axisten_freq {250} \ + CONFIG.PF0_CLASS_CODE {020000} \ + CONFIG.PF0_DEVICE_ID {0001} \ + CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \ + CONFIG.PF0_SUBSYSTEM_ID {0001} \ + CONFIG.PF0_SUBSYSTEM_VENDOR_ID {1234} \ + CONFIG.PF0_Use_Class_Code_Lookup_Assistant {true} \ + CONFIG.pf0_base_class_menu {Network_controller} \ + CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \ + CONFIG.pf0_class_code_base {02} \ + CONFIG.pf0_class_code_sub {00} \ + CONFIG.pf0_bar0_scale {Megabytes} \ + CONFIG.pf0_bar0_size {16} \ + CONFIG.pf0_bar1_enabled {true} \ + CONFIG.pf0_bar1_type {Memory} \ + CONFIG.pf0_bar1_scale {Megabytes} \ + CONFIG.pf0_bar1_size {16} \ + CONFIG.PF0_INTERRUPT_PIN {NONE} \ + CONFIG.PF0_MSIX_CAP_TABLE_BIR {BAR_0} \ + CONFIG.PF0_MSIX_CAP_PBA_BIR {BAR_0} \ + CONFIG.vendor_id {1234} \ + CONFIG.en_msi_per_vec_masking {true} \ +] [get_ips pcie3_ultrascale_0] diff --git a/fpga/lib/pcie/example/VCU108/fpga_axi/ip/pcie3_ultrascale_0.xci b/fpga/lib/pcie/example/VCU108/fpga_axi/ip/pcie3_ultrascale_0.xci deleted file mode 100644 index 181c69748..000000000 --- a/fpga/lib/pcie/example/VCU108/fpga_axi/ip/pcie3_ultrascale_0.xci +++ /dev/null @@ -1,890 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - pcie3_ultrascale_0 - - - - - - 100000000 - 0 - 0.000 - - - - 100000000 - 0 - 0.000 - - 0 - 0.000 - - 100000000 - 1 - 1 - 1 - 0 - 0 - undef - 0.000 - 32 - 0 - 0 - 85 - - 100000000 - 1 - 1 - 1 - 0 - 0 - undef - 0.000 - 32 - 0 - 0 - 75 - 0 - ACTIVE_LOW - 0 - - 100000000 - 1 - 1 - 1 - 0 - 0 - undef - 0.000 - 32 - 0 - 0 - 33 - - 100000000 - 1 - 1 - 1 - 0 - 0 - undef - 0.000 - 32 - 0 - 0 - 60 - 0x000 - FALSE - FALSE - FALSE - FALSE - FALSE - TRUE - 0x00000 - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - TRUE - TRUE - TRUE - TRUE - TRUE - TRUE - 16KB - 2 - 256 - FALSE - TRUE - 0 - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - 0 - 1 - 0 - Add-in_Card - 0x000 - NONE - 0x00000000 - FALSE - TRUE - TRUE - FALSE - FALSE - NONE - 3 - 2.0 - TRUE - FALSE - FALSE - 0x300 - 0x000 - 0x00 - 0x11 - 0x4 - 0x11 - 0x4 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x80 - 0x020000 - 0x0001 - FALSE - FALSE - FALSE - FALSE - 0x0 - FALSE - TRUE - FALSE - 0x2 - 0x300 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x300 - 0x00 - FALSE - 0x1 - 0 - TRUE - 0x300 - 0x00 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 5 - 0xC0 - 0x274 - 0x90 - FALSE - FALSE - FALSE - FALSE - FALSE - 0x300 - 0x00000 - 0x00000 - 0x00000 - 0x00 - 0x000 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x0000 - 0x300 - 0x0000 - 0x0 - 0x0000 - 0x0000 - 0x00000553 - 0x0000 - 0x0001 - 0x1234 - TRUE - FALSE - FALSE - 0x300 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0x1234 - FALSE - FALSE - 0x000 - 0x000 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x80 - 0x058000 - 0x8011 - 0x2 - 0x000 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x00 - 0x000 - 0x00 - FALSE - 0x0 - 0x00 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - 0x000 - 0x00 - FALSE - 0x000 - 0x00000 - 0x00000 - 0x00000 - 0x00 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x0000 - 0x000 - 0x0000 - 0x0 - 0x0000 - 0x0001 - 0x00000553 - 0x0000 - 0x0007 - TRUE - FALSE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 4 - FALSE - 2 - FALSE - 4 - 8 - TRUE - FALSE - TRUE - 0 - 0 - GTH_Quad_225 - 1 - 0x00000000 - FALSE - 0 - 0x000 - 0x00 - 0x028 - 0x20 - 0x198 - 0x20 - FALSE - FALSE - 0x0 - FALSE - TRUE - 3 - 0x000 - 0x80 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00 - TRUE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - FALSE - 1 - 0 - 0 - 0 - 0 - 0 - 0 - Production - 0 - true - false - pcie3_ultrascale_0 - 15 - false - false - 020000 - 0001 - false - false - false - 00_Not_Supported - false - false - INTA - true - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 32_vectors - false - false - false - false - 00 - 0 - N/A - 0000 - 00000553 - 0000 - 0001 - 1234 - true - false - false - 058000 - 8011 - NONE - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - 00 - 0 - 0 - N/A - 0001 - 00000553 - 0000 - 0007 - false - 4 - 8.0_GT/s - X8 - 100_MHz - Default - 0 - 0 - false - false - 1 - false - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - false - DWORD_Aligned - No_ASPM - 250 - true - 2FFFF - false - false - 256_bit - false - None - true - true - true - true - true - true - 500 - true - PCI_Express_Endpoint_device - false - false - false - false - true - false - false - false - false - false - false - false - false - False - false - false - false - false - false - false - true - 100_MHz - true - false - false - false - false - false - Internal - 1 - Add-in_Card - None - 00000000 - Basic - true - X0Y0 - true - Extreme - false - true - false - false - true - false - Megabytes - 16 - Memory - false - true - false - Megabytes - 16 - Memory - false - false - false - Megabytes - 4 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - Network_controller - 02 - 00 - 00 - 512_bytes - false - false - false - Kilobytes - 2 - false - true - false - false - false - false - true - false - Kilobytes - 2 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - 0 - Ethernet_controller - false - false - true - false - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - Memory_controller - 05 - 00 - 80 - 512_bytes - false - false - false - Kilobytes - 2 - true - false - false - false - false - true - false - Kilobytes - 2 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - Other_memory_controller - false - false - QPLL1 - None - true - GTH_Quad_225 - false - ACTIVE_LOW - None - true - true - 1234 - None - virtexu - - - xcvu095 - ffva2104 - VERILOG - - MIXED - -2 - - E - TRUE - TRUE - IP_Flow - 5 - TRUE - . - - . - 2019.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/lib/pcie/example/VCU118/fpga_axi_x8/common/vivado.mk b/fpga/lib/pcie/example/VCU118/fpga_axi_x8/common/vivado.mk index 964ed04eb..b84025221 100644 --- a/fpga/lib/pcie/example/VCU118/fpga_axi_x8/common/vivado.mk +++ b/fpga/lib/pcie/example/VCU118/fpga_axi_x8/common/vivado.mk @@ -40,6 +40,7 @@ CONFIG ?= config.mk SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) +IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) ifdef XDC_FILES XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) @@ -59,7 +60,7 @@ all: fpga fpga: $(FPGA_TOP).bit tmpclean: - -rm -rf *.log *.jou *.cache *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf *.log *.jou *.cache *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl clean: tmpclean @@ -82,6 +83,7 @@ distclean: clean for x in $(SYN_FILES_REL); do echo "add_files -fileset sources_1 $$x" >> create_project.tcl; done for x in $(XDC_FILES_REL); do echo "add_files -fileset constrs_1 $$x" >> create_project.tcl; done for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> create_project.tcl; done + for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> create_project.tcl; done echo "exit" >> create_project.tcl vivado -nojournal -nolog -mode batch -source create_project.tcl diff --git a/fpga/lib/pcie/example/VCU118/fpga_axi_x8/fpga/Makefile b/fpga/lib/pcie/example/VCU118/fpga_axi_x8/fpga/Makefile index 22557e6c1..002312617 100644 --- a/fpga/lib/pcie/example/VCU118/fpga_axi_x8/fpga/Makefile +++ b/fpga/lib/pcie/example/VCU118/fpga_axi_x8/fpga/Makefile @@ -32,7 +32,7 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v XDC_FILES = fpga.xdc # IP -XCI_FILES = ip/pcie4_uscale_plus_0.xci +IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl include ../common/vivado.mk diff --git a/fpga/lib/pcie/example/VCU118/fpga_axi_x8/ip/pcie4_uscale_plus_0.tcl b/fpga/lib/pcie/example/VCU118/fpga_axi_x8/ip/pcie4_uscale_plus_0.tcl new file mode 100644 index 000000000..504586ec9 --- /dev/null +++ b/fpga/lib/pcie/example/VCU118/fpga_axi_x8/ip/pcie4_uscale_plus_0.tcl @@ -0,0 +1,28 @@ + +create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pcie4_uscale_plus_0 + +set_property -dict [list \ + CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ + CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \ + CONFIG.AXISTEN_IF_RC_STRADDLE {false} \ + CONFIG.axisten_if_enable_client_tag {true} \ + CONFIG.axisten_if_width {256_bit} \ + CONFIG.axisten_freq {250} \ + CONFIG.PF0_CLASS_CODE {020000} \ + CONFIG.PF0_DEVICE_ID {0001} \ + CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \ + CONFIG.PF0_SUBSYSTEM_ID {0001} \ + CONFIG.PF0_SUBSYSTEM_VENDOR_ID {1234} \ + CONFIG.PF0_Use_Class_Code_Lookup_Assistant {true} \ + CONFIG.pf0_class_code_sub {00} \ + CONFIG.pf0_base_class_menu {Network_controller} \ + CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \ + CONFIG.pf0_bar0_scale {Megabytes} \ + CONFIG.pf0_bar0_size {16} \ + CONFIG.pf0_bar1_enabled {true} \ + CONFIG.pf0_bar1_type {Memory} \ + CONFIG.pf0_bar1_scale {Megabytes} \ + CONFIG.pf0_bar1_size {16} \ + CONFIG.vendor_id {1234} \ + CONFIG.en_msi_per_vec_masking {true} \ +] [get_ips pcie4_uscale_plus_0] diff --git a/fpga/lib/pcie/example/VCU118/fpga_axi_x8/ip/pcie4_uscale_plus_0.xci b/fpga/lib/pcie/example/VCU118/fpga_axi_x8/ip/pcie4_uscale_plus_0.xci deleted file mode 100644 index db958ecff..000000000 --- a/fpga/lib/pcie/example/VCU118/fpga_axi_x8/ip/pcie4_uscale_plus_0.xci +++ /dev/null @@ -1,1285 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - pcie4_uscale_plus_0 - - - - - - 0 - 0.000 - - - - 0 - 0.000 - - - - 100000000 - 0 - 0.000 - - - - 100000000 - 0 - 0.000 - - 0 - 0.000 - - 100000000 - 1 - 1 - 1 - 0 - 0 - undef - 0.000 - 32 - 0 - 0 - 88 - - 100000000 - 1 - 1 - 1 - 0 - 0 - undef - 0.000 - 32 - 0 - 0 - 75 - 0 - ACTIVE_LOW - 0 - - 100000000 - 1 - 1 - 1 - 0 - 0 - undef - 0.000 - 32 - 0 - 0 - 33 - - 100000000 - 1 - 1 - 1 - 0 - 0 - undef - 0.000 - 32 - 0 - 0 - 62 - 0x000 - FALSE - FALSE - 0 - 33 - 88 - 256 - 75 - 62 - 0x0 - 0x0 - TRUE - FALSE - 0x00000 - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - 0x0 - FALSE - 0x0 - FALSE - FALSE - FALSE - TRUE - TRUE - TRUE - TRUE - TRUE - TRUE - TRUE - FALSE - TRUE - 2 - TRUE - FALSE - FALSE - FALSE - 0 - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - 1 - TRUE - 2 - 1 - 0 - ADD-IN_CARD - 0 - FALSE - FALSE - FALSE - 0x000 - NONE - 0x00000000 - FALSE - TRUE - 32 - None - TRUE - FALSE - FALSE - NONE - FALSE - TRUE - FALSE - 0x1C0 - 0x1C0 - 0x00 - 0x011 - 0x4 - 0x011 - 0x4 - 0x000 - 0x0 - 0x000 - 0x0 - 0x000 - 0x0 - 0x000 - 0x0 - 0x40 - 0x020000 - 0x0001 - FALSE - FALSE - FALSE - FALSE - TRUE - FALSE - 0x3 - 0x1C0 - 0x000 - FALSE - 0x0 - 0 - TRUE - 0x70 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 5 - 0x70 - TRUE - 0x48 - FALSE - FALSE - FALSE - FALSE - 0x0 - 0x7 - 0x7 - 0x7 - 0x7 - 0x7 - 0xffffffffffff - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x1 - 0x00 - 0x000 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x0000 - 0x000 - 0x0000 - 0x1 - 0x0000 - 0x0000 - 0x00000553 - 0x0000 - 0x0001 - 0x1234 - TRUE - FALSE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - FALSE - 0x000 - 0x1234 - 0x000 - 0x000 - 0x00 - 0x011 - 0x4 - 0x011 - 0x4 - 0x000 - 0x0 - 0x000 - 0x0 - 0x000 - 0x0 - 0x000 - 0x0 - 0x40 - 0x058000 - 0x9011 - 0x3 - 0x000 - 0x000 - FALSE - 0x0 - 0x70 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x70 - TRUE - 0x70 - 0x0 - 0x7 - 0x7 - 0x7 - 0x7 - 0x7 - 0xffffffffffff - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x1 - 0x00 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x0000 - 0x000 - 0x0000 - 0x1 - 0x0000 - 0x0001 - 0x00000553 - 0x0000 - 0x0007 - 0x000 - 0x0 - 0x000 - 0x000 - 0x00 - 0x011 - 0x4 - 0x011 - 0x4 - 0x000 - 0x0 - 0x000 - 0x0 - 0x000 - 0x0 - 0x000 - 0x0 - 0x40 - 0x058000 - 0x9438 - 0x3 - 0x000 - 0x000 - FALSE - 0x0 - 0x70 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x70 - TRUE - 0x70 - 0x0 - 0x7 - 0x7 - 0x7 - 0x7 - 0x7 - 0xffffffffffff - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x1 - 0x00 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x0000 - 0x000 - 0x0000 - 0x1 - 0x0000 - 0x0002 - 0x00000553 - 0x0000 - 0x0007 - 0x000 - 0x0 - 0x000 - 0x000 - 0x00 - 0x011 - 0x4 - 0x011 - 0x4 - 0x000 - 0x0 - 0x000 - 0x0 - 0x000 - 0x0 - 0x000 - 0x0 - 0x40 - 0x058000 - 0x9638 - 0x3 - 0x000 - 0x000 - FALSE - 0x0 - 0x70 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x70 - TRUE - 0x70 - 0x0 - 0x7 - 0x7 - 0x7 - 0x7 - 0x7 - 0xffffffffffff - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x1 - 0x00 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x0000 - 0x000 - 0x0000 - 0x1 - 0x0000 - 0x0003 - 0x00000553 - 0x0000 - 0x0007 - 0x000 - 0x0 - 4 - 0 - FALSE - 2 - TRUE - FALSE - 4 - 8 - TRUE - FALSE - 0x000 - FALSE - TRUE - GTY_Quad_227 - 1 - 0x00000000 - 0x0 - FALSE - 0 - FALSE - FALSE - 0x2 - 0x000 - 0x00 - 0x004 - 0x20 - 0x3E0 - 0x20 - FALSE - 0 - FALSE - X8G3 - FALSE - TRUE - FALSE - 0x70 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - FALSE - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 8 - Beta - 0 - false - true - true - true - true - true - DWORD_Aligned - false - false - false - true - false - false - DWORD_Aligned - pcie4_uscale_plus_0 - 15 - None - Custom - false - 020000 - 0001 - false - false - false - false - false - NONE - true - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 32_vectors - false - false - false - false - 00 - 0 - 0 - 0000 - 00000553 - 0000 - 0001 - 1234 - true - 058000 - 9011 - NONE - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - 00 - 0 - 1 - 0 - 0001 - 00000553 - 0000 - 0007 - 1234 - false - 058000 - 9438 - NONE - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - 00 - 0 - 1 - 0 - 0002 - 00000553 - 0000 - 0007 - 1234 - false - 058000 - 9638 - NONE - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - 00 - 0 - 1 - 0 - 0003 - 00000553 - 0000 - 0007 - 1234 - false - 4 - true - 8.0_GT/s - X8 - 100_MHz - 0 - 0 - false - false - 1 - Custom - 1 - 1 - 00000000 - 00000000 - 0 - 00000000 - 00000000 - 0 - 00000000 - 00000000 - 0 - 00000000 - 00000000 - 0 - false - DWORD_Aligned - No_ASPM - 0 - 250 - true - 00000 - false - false - 256_bit - false - true - true - true - true - true - true - true - false - true - true - 500 - true - false - false - PCI_Express_Endpoint_device - false - false - false - false - false - false - false - true - false - false - true - false - false - false - false - false - False - false - 0000 - false - false - false - false - false - false - false - false - false - false - false - true - 100_MHz - true - false - false - false - false - false - false - false - false - true - false - false - false - Internal - 2 - 1 - Add-in_Card - false - false - false - None - 00000000 - Basic - HARD - true - X1Y2 - false - true - Extreme - true - false - false - true - 0 - false - Megabytes - 16 - Memory - false - true - 7 - false - Megabytes - 16 - Memory - false - false - 7 - false - Kilobytes - 128 - N/A - false - false - 7 - false - Kilobytes - 128 - N/A - false - false - 7 - false - Kilobytes - 128 - N/A - false - 7 - false - Kilobytes - 128 - N/A - Network_controller - 02 - 00 - 00 - 1024_bytes - false - false - Kilobytes - 2 - true - false - 0xffffffffffff - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 1 - false - true - false - Kilobytes - 2 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - 1 - Ethernet_controller - false - false - false - true - 0 - false - Megabytes - 16 - Memory - false - true - 7 - false - Megabytes - 16 - Memory - false - false - 7 - false - Kilobytes - 128 - N/A - false - false - 7 - false - Kilobytes - 128 - N/A - false - false - 7 - false - Kilobytes - 128 - N/A - false - 7 - false - Kilobytes - 128 - N/A - Memory_controller - 05 - 00 - 80 - false - Kilobytes - 2 - false - false - 0xffffffffffff - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 1 - false - true - false - Kilobytes - 2 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - Other_memory_controller - 1234 - false - true - 0 - false - Megabytes - 16 - Memory - false - true - 7 - false - Megabytes - 16 - Memory - false - false - 7 - false - Kilobytes - 128 - N/A - false - false - 7 - false - Kilobytes - 128 - N/A - false - false - 7 - false - Kilobytes - 128 - N/A - false - 7 - false - Kilobytes - 128 - N/A - Memory_controller - 05 - 00 - 80 - false - Kilobytes - 2 - false - false - 0xffffffffffff - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 1 - false - true - false - Kilobytes - 2 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - Other_memory_controller - 1234 - false - true - 0 - false - Megabytes - 16 - Memory - false - true - 7 - false - Megabytes - 16 - Memory - false - false - 7 - false - Kilobytes - 128 - N/A - false - false - 7 - false - Kilobytes - 128 - N/A - false - false - 7 - false - Kilobytes - 128 - N/A - false - 7 - false - Kilobytes - 128 - N/A - Memory_controller - 05 - 00 - 80 - false - Kilobytes - 2 - false - false - 0xffffffffffff - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 1 - false - true - false - Kilobytes - 2 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - Other_memory_controller - 1234 - false - QPLL1 - false - true - GTY_Quad_227 - false - false - ACTIVE_LOW - false - 15 - 15 - X8G3 - false - true - Enabled - 64bit_Enabled - true - false - 1234 - false - None - virtexuplus - - - xcvu9p - flga2104 - VERILOG - - MIXED - -2L - - E - TRUE - TRUE - IP_Flow - 5 - TRUE - . - - . - 2019.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/lib/pcie/example/VCU1525/fpga_axi/common/vivado.mk b/fpga/lib/pcie/example/VCU1525/fpga_axi/common/vivado.mk index 964ed04eb..b84025221 100644 --- a/fpga/lib/pcie/example/VCU1525/fpga_axi/common/vivado.mk +++ b/fpga/lib/pcie/example/VCU1525/fpga_axi/common/vivado.mk @@ -40,6 +40,7 @@ CONFIG ?= config.mk SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES)) INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES)) XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES)) +IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES)) ifdef XDC_FILES XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES)) @@ -59,7 +60,7 @@ all: fpga fpga: $(FPGA_TOP).bit tmpclean: - -rm -rf *.log *.jou *.cache *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v + -rm -rf *.log *.jou *.cache *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v -rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl clean: tmpclean @@ -82,6 +83,7 @@ distclean: clean for x in $(SYN_FILES_REL); do echo "add_files -fileset sources_1 $$x" >> create_project.tcl; done for x in $(XDC_FILES_REL); do echo "add_files -fileset constrs_1 $$x" >> create_project.tcl; done for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> create_project.tcl; done + for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> create_project.tcl; done echo "exit" >> create_project.tcl vivado -nojournal -nolog -mode batch -source create_project.tcl diff --git a/fpga/lib/pcie/example/VCU1525/fpga_axi/fpga/Makefile b/fpga/lib/pcie/example/VCU1525/fpga_axi/fpga/Makefile index 4fd15df67..9c516b5f8 100644 --- a/fpga/lib/pcie/example/VCU1525/fpga_axi/fpga/Makefile +++ b/fpga/lib/pcie/example/VCU1525/fpga_axi/fpga/Makefile @@ -32,7 +32,7 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v XDC_FILES = fpga.xdc # IP -XCI_FILES = ip/pcie4_uscale_plus_0.xci +IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl include ../common/vivado.mk diff --git a/fpga/lib/pcie/example/VCU1525/fpga_axi/ip/pcie4_uscale_plus_0.tcl b/fpga/lib/pcie/example/VCU1525/fpga_axi/ip/pcie4_uscale_plus_0.tcl new file mode 100644 index 000000000..55d3ca6e8 --- /dev/null +++ b/fpga/lib/pcie/example/VCU1525/fpga_axi/ip/pcie4_uscale_plus_0.tcl @@ -0,0 +1,28 @@ + +create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pcie4_uscale_plus_0 + +set_property -dict [list \ + CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ + CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \ + CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \ + CONFIG.axisten_if_enable_client_tag {true} \ + CONFIG.axisten_if_width {512_bit} \ + CONFIG.axisten_freq {250} \ + CONFIG.PF0_CLASS_CODE {020000} \ + CONFIG.PF0_DEVICE_ID {0001} \ + CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \ + CONFIG.PF0_SUBSYSTEM_ID {0001} \ + CONFIG.PF0_SUBSYSTEM_VENDOR_ID {1234} \ + CONFIG.PF0_Use_Class_Code_Lookup_Assistant {true} \ + CONFIG.pf0_class_code_sub {00} \ + CONFIG.pf0_base_class_menu {Network_controller} \ + CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \ + CONFIG.pf0_bar0_scale {Megabytes} \ + CONFIG.pf0_bar0_size {16} \ + CONFIG.pf0_bar1_enabled {true} \ + CONFIG.pf0_bar1_type {Memory} \ + CONFIG.pf0_bar1_scale {Megabytes} \ + CONFIG.pf0_bar1_size {16} \ + CONFIG.vendor_id {1234} \ + CONFIG.en_msi_per_vec_masking {true} \ +] [get_ips pcie4_uscale_plus_0] diff --git a/fpga/lib/pcie/example/VCU1525/fpga_axi/ip/pcie4_uscale_plus_0.xci b/fpga/lib/pcie/example/VCU1525/fpga_axi/ip/pcie4_uscale_plus_0.xci deleted file mode 100644 index 773cecce3..000000000 --- a/fpga/lib/pcie/example/VCU1525/fpga_axi/ip/pcie4_uscale_plus_0.xci +++ /dev/null @@ -1,1303 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - pcie4_uscale_plus_0 - - - - - - 0 - 0.000 - - - - 0 - 0.000 - - - - 100000000 - 0 - 0.000 - - - - 100000000 - 0 - 0.000 - - 0 - 0.000 - - 100000000 - 1 - 1 - 1 - 0 - 0 - undef - 0.000 - 64 - 0 - 0 - 183 - - 100000000 - 1 - 1 - 1 - 0 - 0 - undef - 0.000 - 64 - 0 - 0 - 161 - 0 - ACTIVE_LOW - 0 - - 100000000 - 1 - 1 - 1 - 0 - 0 - undef - 0.000 - 64 - 0 - 0 - 81 - - 100000000 - 1 - 1 - 1 - 0 - 0 - undef - 0.000 - 64 - 0 - 0 - 137 - 0x000 - FALSE - FALSE - 0 - 81 - 183 - 512 - 161 - 137 - 0x0 - 0x0 - TRUE - FALSE - 0x00000 - FALSE - FALSE - FALSE - TRUE - FALSE - FALSE - FALSE - 0x0 - FALSE - 0x0 - FALSE - FALSE - FALSE - TRUE - TRUE - TRUE - TRUE - TRUE - TRUE - TRUE - FALSE - TRUE - 3 - TRUE - FALSE - FALSE - FALSE - 0 - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - FALSE - 1 - TRUE - 2 - 1 - 0 - ADD-IN_CARD - 0 - FALSE - FALSE - FALSE - 0x000 - NONE - 0x00000000 - FALSE - TRUE - 32 - None - TRUE - FALSE - FALSE - NONE - FALSE - TRUE - FALSE - 0x1C0 - 0x1C0 - 0x00 - 0x011 - 0x4 - 0x011 - 0x4 - 0x000 - 0x0 - 0x000 - 0x0 - 0x000 - 0x0 - 0x000 - 0x0 - 0x40 - 0x020000 - 0x0001 - FALSE - FALSE - FALSE - FALSE - TRUE - FALSE - 0x3 - 0x1C0 - 0x000 - FALSE - 0x0 - 0 - TRUE - 0x70 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 5 - 0x70 - TRUE - 0x48 - FALSE - FALSE - FALSE - FALSE - 0x0 - 0x7 - 0x7 - 0x7 - 0x7 - 0x7 - 0xffffffffffff - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x1 - 0x00 - 0x000 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x0000 - 0x000 - 0x0000 - 0x1 - 0x0000 - 0x0000 - 0x00000553 - 0x0000 - 0x0001 - 0x1234 - TRUE - FALSE - FALSE - 0x000 - 0x0 - 0x0 - 0x000 - 0x1 - FALSE - 0x000 - 0x1234 - 0x000 - 0x000 - 0x00 - 0x011 - 0x4 - 0x011 - 0x4 - 0x000 - 0x0 - 0x000 - 0x0 - 0x000 - 0x0 - 0x000 - 0x0 - 0x40 - 0x058000 - 0x9011 - 0x3 - 0x000 - 0x000 - FALSE - 0x0 - 0x70 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x70 - TRUE - 0x70 - 0x0 - 0x7 - 0x7 - 0x7 - 0x7 - 0x7 - 0xffffffffffff - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x1 - 0x00 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x0000 - 0x000 - 0x0000 - 0x1 - 0x0000 - 0x0001 - 0x00000553 - 0x0000 - 0x0007 - 0x000 - 0x0 - 0x000 - 0x000 - 0x00 - 0x011 - 0x4 - 0x011 - 0x4 - 0x000 - 0x0 - 0x000 - 0x0 - 0x000 - 0x0 - 0x000 - 0x0 - 0x40 - 0x058000 - 0x943F - 0x3 - 0x000 - 0x000 - FALSE - 0x0 - 0x70 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x70 - TRUE - 0x70 - 0x0 - 0x7 - 0x7 - 0x7 - 0x7 - 0x7 - 0xffffffffffff - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x1 - 0x00 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x0000 - 0x000 - 0x0000 - 0x1 - 0x0000 - 0x0002 - 0x00000553 - 0x0000 - 0x0007 - 0x000 - 0x0 - 0x000 - 0x000 - 0x00 - 0x011 - 0x4 - 0x011 - 0x4 - 0x000 - 0x0 - 0x000 - 0x0 - 0x000 - 0x0 - 0x000 - 0x0 - 0x40 - 0x058000 - 0x963F - 0x3 - 0x000 - 0x000 - FALSE - 0x0 - 0x70 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x70 - TRUE - 0x70 - 0x0 - 0x7 - 0x7 - 0x7 - 0x7 - 0x7 - 0xffffffffffff - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x1 - 0x00 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x00 - 0x0 - 0x0000 - 0x000 - 0x0000 - 0x1 - 0x0000 - 0x0003 - 0x00000553 - 0x0000 - 0x0007 - 0x000 - 0x0 - 4 - 0 - FALSE - 2 - TRUE - FALSE - 4 - 16 - TRUE - FALSE - 0x000 - FALSE - TRUE - GTY_Quad_227 - 1 - 0x00000000 - 0x0 - FALSE - 0 - FALSE - FALSE - 0x2 - 0x000 - 0x00 - 0x004 - 0x20 - 0x3E0 - 0x20 - FALSE - 0 - FALSE - X8G3 - FALSE - TRUE - FALSE - 0x70 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - 0 - 0x00000000 - 0 - 0x00000000 - 0x000 - FALSE - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 0 - 0 - 0 - 8 - Beta - 0 - false - false - true - true - true - true - DWORD_Aligned - false - false - true - true - false - false - DWORD_Aligned - pcie4_uscale_plus_0 - 15 - None - Custom - false - 020000 - 0001 - false - false - false - false - false - NONE - true - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 32_vectors - false - false - false - false - 00 - 0 - 0 - 0000 - 00000553 - 0000 - 0001 - 1234 - true - 058000 - 9011 - NONE - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - 00 - 0 - 1 - 0 - 0001 - 00000553 - 0000 - 0007 - 1234 - false - 058000 - 943F - NONE - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - 00 - 0 - 1 - 0 - 0002 - 00000553 - 0000 - 0007 - 1234 - false - 058000 - 963F - NONE - BAR_0 - 00000000 - BAR_0 - 00000000 - 000 - 1_vector - 00 - 0 - 1 - 0 - 0003 - 00000553 - 0000 - 0007 - 1234 - false - 4 - true - 8.0_GT/s - X16 - 100_MHz - 0 - 0 - false - false - 1 - Custom - 1 - 1 - 00000000 - 00000000 - 0 - 00000000 - 00000000 - 0 - 00000000 - 00000000 - 0 - 00000000 - 00000000 - 0 - false - DWORD_Aligned - No_ASPM - 0 - 250 - true - 00000 - false - false - 512_bit - false - true - true - true - true - true - true - true - false - true - true - 500 - true - false - false - PCI_Express_Endpoint_device - false - false - false - false - false - false - false - true - false - false - true - false - false - false - false - false - False - false - 0000 - false - false - false - false - false - false - false - false - false - false - false - true - 100_MHz - true - false - false - false - false - false - false - false - false - true - false - false - false - Internal - 2 - 1 - Add-in_Card - false - false - false - None - 00000000 - Basic - HARD - true - X1Y2 - false - true - Extreme - true - false - false - true - 0 - false - Megabytes - 16 - Memory - false - true - 7 - false - Megabytes - 16 - Memory - false - false - 7 - false - Kilobytes - 128 - N/A - false - false - 7 - false - Kilobytes - 128 - N/A - false - false - 7 - false - Kilobytes - 128 - N/A - false - 7 - false - Kilobytes - 128 - N/A - Network_controller - 02 - 00 - 00 - 1024_bytes - false - false - Kilobytes - 2 - true - false - 0xffffffffffff - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 1 - false - true - false - Kilobytes - 2 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - 1 - Ethernet_controller - false - false - false - true - 0 - false - Megabytes - 16 - Memory - false - true - 7 - false - Megabytes - 16 - Memory - false - false - 7 - false - Kilobytes - 128 - N/A - false - false - 7 - false - Kilobytes - 128 - N/A - false - false - 7 - false - Kilobytes - 128 - N/A - false - 7 - false - Kilobytes - 128 - N/A - Memory_controller - 05 - 00 - 80 - false - Kilobytes - 2 - false - false - 0xffffffffffff - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 1 - false - true - false - Kilobytes - 2 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - Other_memory_controller - 1234 - false - true - 0 - false - Megabytes - 16 - Memory - false - true - 7 - false - Megabytes - 16 - Memory - false - false - 7 - false - Kilobytes - 128 - N/A - false - false - 7 - false - Kilobytes - 128 - N/A - false - false - 7 - false - Kilobytes - 128 - N/A - false - 7 - false - Kilobytes - 128 - N/A - Memory_controller - 05 - 00 - 80 - false - Kilobytes - 2 - false - false - 0xffffffffffff - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 1 - false - true - false - Kilobytes - 2 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - Other_memory_controller - 1234 - false - true - 0 - false - Megabytes - 16 - Memory - false - true - 7 - false - Megabytes - 16 - Memory - false - false - 7 - false - Kilobytes - 128 - N/A - false - false - 7 - false - Kilobytes - 128 - N/A - false - false - 7 - false - Kilobytes - 128 - N/A - false - 7 - false - Kilobytes - 128 - N/A - Memory_controller - 05 - 00 - 80 - false - Kilobytes - 2 - false - false - 0xffffffffffff - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 0x000000000000 - 1 - false - true - false - Kilobytes - 2 - Memory - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - false - Kilobytes - 2 - N/A - false - false - Kilobytes - 2 - N/A - Other_memory_controller - 1234 - false - QPLL1 - false - true - GTY_Quad_227 - false - false - ACTIVE_LOW - false - 15 - 15 - X8G3 - false - true - Enabled - 64bit_Enabled - true - false - 1234 - false - None - virtexuplus - - - xcvu9p - fsgd2104 - VERILOG - - MIXED - -2L - - E - TRUE - TRUE - IP_Flow - 5 - TRUE - . - - . - 2019.1 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/fpga/lib/pcie/tb/axi.py b/fpga/lib/pcie/tb/axi.py index a4a7ddbf9..f7a216c79 100644 --- a/fpga/lib/pcie/tb/axi.py +++ b/fpga/lib/pcie/tb/axi.py @@ -73,6 +73,15 @@ AWCACHE_WRITE_BACK_READ_ALLOC = 0b0111 AWCACHE_WRITE_BACK_WRITE_ALLOC = 0b1111 AWCACHE_WRITE_BACK_READ_AND_WRIE_ALLOC = 0b1111 +PROT_PRIVILEGED = 0b001 +PROT_NONSECURE = 0b010 +PROT_INSTRUCTION = 0b100 + +RESP_OKAY = 0b00 +RESP_EXOKAY = 0b01 +RESP_SLVERR = 0b10 +RESP_DECERR = 0b11 + class AXIMaster(object): def __init__(self): self.write_command_queue = [] @@ -101,19 +110,21 @@ class AXIMaster(object): self.int_read_addr_sync = Signal(False) self.int_read_resp_command_queue = [] self.int_read_resp_command_sync = Signal(False) - self.int_read_resp_queue = [] + self.int_read_resp_queue_list = {} self.int_read_resp_sync = Signal(False) self.in_flight_operations = 0 + self.max_burst_len = 256 + self.has_logic = False self.clk = None - def init_read(self, address, length, burst=0b01, size=None, lock=0b0, cache=0b0000, prot=0b010, qos=0b0000, region=0b0000, user=None): + def init_read(self, address, length, burst=0b01, size=None, lock=0b0, cache=0b0011, prot=0b010, qos=0b0000, region=0b0000, user=None): self.read_command_queue.append((address, length, burst, size, lock, cache, prot, qos, region, user)) self.read_command_sync.next = not self.read_command_sync - def init_write(self, address, data, burst=0b01, size=None, lock=0b0, cache=0b0000, prot=0b010, qos=0b0000, region=0b0000, user=None): + def init_write(self, address, data, burst=0b01, size=None, lock=0b0, cache=0b0011, prot=0b010, qos=0b0000, region=0b0000, user=None): self.write_command_queue.append((address, data, burst, size, lock, cache, prot, qos, region, user)) self.write_command_sync.next = not self.write_command_sync @@ -179,33 +190,38 @@ class AXIMaster(object): m_axi_ruser=None, m_axi_rvalid=Signal(bool(False)), m_axi_rready=Signal(bool(False)), + pause=False, + awpause=False, + wpause=False, + bpause=False, + arpause=False, + rpause=False, name=None ): - + if self.has_logic: raise Exception("Logic already instantiated!") if m_axi_wdata is not None: - assert m_axi_awid is not None - assert m_axi_bid is not None - assert len(m_axi_awid) == len(m_axi_bid) + if m_axi_awid is not None: + assert m_axi_bid is not None + assert len(m_axi_awid) == len(m_axi_bid) assert m_axi_awaddr is not None assert len(m_axi_wdata) % 8 == 0 assert len(m_axi_wdata) / 8 == len(m_axi_wstrb) w = len(m_axi_wdata) if m_axi_rdata is not None: - assert m_axi_arid is not None - assert m_axi_rid is not None - assert len(m_axi_arid) == len(m_axi_rid) + if m_axi_arid is not None: + assert m_axi_rid is not None + assert len(m_axi_arid) == len(m_axi_rid) assert m_axi_araddr is not None assert len(m_axi_rdata) % 8 == 0 w = len(m_axi_rdata) if m_axi_wdata is not None: - assert len(m_axi_wdata) == len(m_axi_rdata) - assert len(m_axi_awid) == len(m_axi_arid) assert len(m_axi_awaddr) == len(m_axi_araddr) + assert len(m_axi_wdata) == len(m_axi_rdata) bw = int(w/8) @@ -214,12 +230,28 @@ class AXIMaster(object): self.has_logic = True self.clk = clk + m_axi_bvalid_int = Signal(bool(False)) + m_axi_bready_int = Signal(bool(False)) + m_axi_rvalid_int = Signal(bool(False)) + m_axi_rready_int = Signal(bool(False)) + + @always_comb + def pause_logic(): + m_axi_bvalid_int.next = m_axi_bvalid and not (pause or bpause) + m_axi_bready.next = m_axi_bready_int and not (pause or bpause) + m_axi_rvalid_int.next = m_axi_rvalid and not (pause or rpause) + m_axi_rready.next = m_axi_rready_int and not (pause or rpause) + @instance def write_logic(): while True: if not self.write_command_queue: yield self.write_command_sync + if m_axi_awaddr is None: + print("Error: attempted write on read-only interface") + raise StopSimulation + addr, data, burst, size, lock, cache, prot, qos, region, user = self.write_command_queue.pop(0) self.in_flight_operations += 1 @@ -269,12 +301,17 @@ class AXIMaster(object): if n >= burst_length: transfer_count += 1 n = 0 - burst_length = min(cycles-k, 256) # max len - burst_length = min(burst_length, 0x1000-(cur_addr&0xfff)) # 4k align + burst_length = min(cycles-k, min(max(self.max_burst_len, 1), 256)) # max len + burst_length = int((min(burst_length*num_bytes, 0x1000-(cur_addr&0xfff))+num_bytes-1)/num_bytes) # 4k align awid = self.cur_write_id - self.cur_write_id = (self.cur_write_id + 1) % 2**len(m_axi_awid) + if m_axi_awid is not None: + self.cur_write_id = (self.cur_write_id + 1) % 2**len(m_axi_awid) + else: + self.cur_write_id = 0 self.int_write_addr_queue.append((cur_addr, awid, burst_length-1, size, burst, lock, cache, prot, qos, region, user)) self.int_write_addr_sync.next = not self.int_write_addr_sync + if name is not None: + print("[%s] Write burst awid: 0x%x awaddr: 0x%08x awlen: %d awsize: %d" % (name, awid, cur_addr, burst_length-1, size)) n += 1 self.int_write_data_queue.append((val, strb, n >= burst_length)) self.int_write_data_sync.next = not self.int_write_data_sync @@ -299,7 +336,7 @@ class AXIMaster(object): while not self.int_write_resp_queue: yield clk.posedge - cycle_resp = self.int_write_resp_queue.pop(0) + cycle_id, cycle_resp, cycle_user = self.int_write_resp_queue.pop(0) if cycle_resp != 0: resp = cycle_resp @@ -315,7 +352,8 @@ class AXIMaster(object): yield clk.posedge addr, awid, length, size, burst, lock, cache, prot, qos, region, user = self.int_write_addr_queue.pop(0) - m_axi_awaddr.next = addr + if m_axi_awaddr is not None: + m_axi_awaddr.next = addr m_axi_awid.next = awid m_axi_awlen.next = length m_axi_awsize.next = size @@ -327,11 +365,12 @@ class AXIMaster(object): m_axi_awregion.next = region if m_axi_awuser is not None: m_axi_awuser.next = user - m_axi_awvalid.next = True + m_axi_awvalid.next = not (pause or awpause) yield clk.posedge - while m_axi_awvalid and not m_axi_awready: + while not m_axi_awvalid or not m_axi_awready: + m_axi_awvalid.next = m_axi_awvalid or not (pause or awpause) yield clk.posedge m_axi_awvalid.next = False @@ -343,11 +382,12 @@ class AXIMaster(object): yield clk.posedge m_axi_wdata.next, m_axi_wstrb.next, m_axi_wlast.next = self.int_write_data_queue.pop(0) - m_axi_wvalid.next = True + m_axi_wvalid.next = not (pause or wpause) yield clk.posedge - while m_axi_wvalid and not m_axi_wready: + while not m_axi_wvalid or not m_axi_wready: + m_axi_wvalid.next = m_axi_wvalid or not (pause or wpause) yield clk.posedge m_axi_wvalid.next = False @@ -355,12 +395,21 @@ class AXIMaster(object): @instance def write_resp_interface_logic(): while True: - m_axi_bready.next = True + m_axi_bready_int.next = True yield clk.posedge - if m_axi_bready & m_axi_bvalid: - self.int_write_resp_queue.append(int(m_axi_bresp)) + if m_axi_bready and m_axi_bvalid_int: + if m_axi_bid is not None: + bid = int(m_axi_bid) + else: + bid = 0 + bresp = int(m_axi_bresp) + if m_axi_buser is not None: + buser = int(m_axi_buser) + else: + buser = 0 + self.int_write_resp_queue.append((bid, bresp, buser)) self.int_write_resp_sync.next = not self.int_write_resp_sync @instance @@ -369,6 +418,10 @@ class AXIMaster(object): if not self.read_command_queue: yield self.read_command_sync + if m_axi_araddr is None: + print("Error: attempted read on write-only interface") + raise StopSimulation + addr, length, burst, size, lock, cache, prot, qos, region, user = self.read_command_queue.pop(0) self.in_flight_operations += 1 @@ -385,7 +438,9 @@ class AXIMaster(object): cycles = int((length + num_bytes-1 + (addr % num_bytes)) / num_bytes) - self.int_read_resp_command_queue.append((addr, length, size, cycles, prot)) + burst_list = [] + + self.int_read_resp_command_queue.append((addr, length, size, cycles, prot, burst_list)) self.int_read_resp_command_sync.next = not self.int_read_resp_command_sync cur_addr = aligned_addr @@ -398,22 +453,30 @@ class AXIMaster(object): n += 1 if n >= burst_length: n = 0 - burst_length = min(cycles-k, 256) # max len - burst_length = min(burst_length, 0x1000-((aligned_addr+k*num_bytes)&0xfff))# 4k align + burst_length = min(cycles-k, min(max(self.max_burst_len, 1), 256)) # max len + burst_length = int((min(burst_length*num_bytes, 0x1000-(cur_addr&0xfff))+num_bytes-1)/num_bytes) # 4k align arid = self.cur_read_id - self.cur_read_id = (self.cur_read_id + 1) % 2**len(m_axi_arid) + if m_axi_arid is not None: + self.cur_read_id = (self.cur_read_id + 1) % 2**len(m_axi_arid) + else: + self.cur_read_id = 0 + burst_list.append((arid, burst_length)) self.int_read_addr_queue.append((cur_addr, arid, burst_length-1, size, burst, lock, cache, prot, qos, region, user)) self.int_read_addr_sync.next = not self.int_read_addr_sync + if name is not None: + print("[%s] Read burst arid: 0x%x araddr: 0x%08x arlen: %d arsize: %d" % (name, arid, cur_addr, burst_length-1, size)) cur_addr += num_bytes + burst_list.append(None) + @instance def read_resp_logic(): while True: if not self.int_read_resp_command_queue: yield self.int_read_resp_command_sync - addr, length, size, cycles, prot = self.int_read_resp_command_queue.pop(0) + addr, length, size, cycles, prot, burst_list = self.int_read_resp_command_queue.pop(0) num_bytes = 2**size assert 0 <= size <= int(math.log(bw, 2)) @@ -429,29 +492,46 @@ class AXIMaster(object): resp = 0 - for k in range(cycles): - if not self.int_read_resp_queue: - yield self.int_read_resp_sync + first = True - cycle_data, cycle_resp, cycle_last = self.int_read_resp_queue.pop(0) + while True: + while not burst_list: + yield clk.posedge - if cycle_resp != 0: - resp = cycle_resp + cur_burst = burst_list.pop(0) - start = cycle_offset - stop = cycle_offset+num_bytes + if cur_burst is None: + break - if k == 0: - start = start_offset - if k == cycles-1: - stop = end_offset + rid = cur_burst[0] + burst_length = cur_burst[1] - assert cycle_last == (k == cycles - 1) + for k in range(burst_length): + self.int_read_resp_queue_list.setdefault(rid, []) + while not self.int_read_resp_queue_list[rid]: + yield self.int_read_resp_sync - for j in range(start, stop): - data += bytearray([(cycle_data >> j*8) & 0xff]) + cycle_id, cycle_data, cycle_resp, cycle_last, cycle_user = self.int_read_resp_queue_list[rid].pop(0) - cycle_offset = (cycle_offset + num_bytes) % bw + if cycle_resp != 0: + resp = cycle_resp + + start = cycle_offset + stop = cycle_offset+num_bytes + + if first: + start = start_offset + + assert cycle_last == (k == burst_length - 1) + + for j in range(start, stop): + data += bytearray([(cycle_data >> j*8) & 0xff]) + + cycle_offset = (cycle_offset + num_bytes) % bw + + first = False + + data = data[:length] if name is not None: print("[%s] Read data addr: 0x%08x prot: 0x%x data: %s" % (name, addr, prot, " ".join(("{:02x}".format(c) for c in bytearray(data))))) @@ -468,7 +548,8 @@ class AXIMaster(object): addr, arid, length, size, burst, lock, cache, prot, qos, region, user = self.int_read_addr_queue.pop(0) m_axi_araddr.next = addr - m_axi_arid.next = arid + if m_axi_arid is not None: + m_axi_arid.next = arid m_axi_arlen.next = length m_axi_arsize.next = size m_axi_arburst.next = burst @@ -479,11 +560,12 @@ class AXIMaster(object): m_axi_arregion.next = region if m_axi_aruser is not None: m_axi_aruser.next = user - m_axi_arvalid.next = True + m_axi_arvalid.next = not (pause or arpause) yield clk.posedge - while m_axi_arvalid and not m_axi_arready: + while not m_axi_arvalid or not m_axi_arready: + m_axi_arvalid.next = m_axi_arvalid or not (pause or arpause) yield clk.posedge m_axi_arvalid.next = False @@ -491,12 +573,24 @@ class AXIMaster(object): @instance def read_resp_interface_logic(): while True: - m_axi_rready.next = True + m_axi_rready_int.next = True yield clk.posedge - if m_axi_rready & m_axi_rvalid: - self.int_read_resp_queue.append((int(m_axi_rdata), int(m_axi_rresp), int(m_axi_rlast))) + if m_axi_rready and m_axi_rvalid_int: + if m_axi_rid is not None: + rid = int(m_axi_rid) + else: + rid = 0 + rdata = int(m_axi_rdata) + rresp = int(m_axi_rresp) + rlast = int(m_axi_rlast) + if m_axi_buser is not None: + ruser = int(m_axi_ruser) + else: + ruser = 0 + self.int_read_resp_queue_list.setdefault(rid, []) + self.int_read_resp_queue_list[rid].append((rid, rdata, rresp, rlast, ruser)) self.int_read_resp_sync.next = not self.int_read_resp_sync return instances() @@ -525,7 +619,7 @@ class AXIRam(object): def write_mem(self, address, data): self.mem.seek(address % self.size) - self.mem.write(data) + self.mem.write(bytes(data)) def create_port(self, clk, @@ -564,35 +658,56 @@ class AXIRam(object): s_axi_rlast=Signal(bool(True)), s_axi_rvalid=Signal(bool(False)), s_axi_rready=Signal(bool(False)), + pause=False, + awpause=False, + wpause=False, + bpause=False, + arpause=False, + rpause=False, name=None ): if s_axi_wdata is not None: - assert s_axi_awid is not None - assert s_axi_bid is not None - assert len(s_axi_awid) == len(s_axi_bid) + if s_axi_awid is not None: + assert s_axi_bid is not None + assert len(s_axi_awid) == len(s_axi_bid) assert s_axi_awaddr is not None assert len(s_axi_wdata) % 8 == 0 assert len(s_axi_wdata) / 8 == len(s_axi_wstrb) w = len(s_axi_wdata) if s_axi_rdata is not None: - assert s_axi_arid is not None - assert s_axi_rid is not None - assert len(s_axi_arid) == len(s_axi_rid) + if s_axi_arid is not None: + assert s_axi_rid is not None + assert len(s_axi_arid) == len(s_axi_rid) assert s_axi_araddr is not None assert len(s_axi_rdata) % 8 == 0 w = len(s_axi_rdata) if s_axi_wdata is not None: - assert len(s_axi_wdata) == len(s_axi_rdata) - assert len(s_axi_awid) == len(s_axi_arid) assert len(s_axi_awaddr) == len(s_axi_araddr) + assert len(s_axi_wdata) == len(s_axi_rdata) bw = int(w/8) assert bw in (1, 2, 4, 8, 16, 32, 64, 128) + s_axi_awvalid_int = Signal(bool(False)) + s_axi_awready_int = Signal(bool(False)) + s_axi_wvalid_int = Signal(bool(False)) + s_axi_wready_int = Signal(bool(False)) + s_axi_arvalid_int = Signal(bool(False)) + s_axi_arready_int = Signal(bool(False)) + + @always_comb + def pause_logic(): + s_axi_awvalid_int.next = s_axi_awvalid and not (pause or awpause) + s_axi_awready.next = s_axi_awready_int and not (pause or awpause) + s_axi_wvalid_int.next = s_axi_wvalid and not (pause or wpause) + s_axi_wready.next = s_axi_wready_int and not (pause or wpause) + s_axi_arvalid_int.next = s_axi_arvalid and not (pause or arpause) + s_axi_arready.next = s_axi_arready_int and not (pause or arpause) + @instance def write_logic(): while True: @@ -601,6 +716,9 @@ class AXIRam(object): addr, awid, length, size, burst, lock, cache, prot = self.int_write_addr_queue.pop(0) + if name is not None: + print("[%s] Write burst awid: 0x%x awaddr: 0x%08x awlen: %d awsize: %d" % (name, awid, addr, length, size)) + num_bytes = 2**size assert 0 < num_bytes <= bw @@ -622,25 +740,28 @@ class AXIRam(object): for n in range(length): cur_word_addr = int(cur_addr/bw)*bw - self.mem.seek(cur_word_addr % self.size) - if not self.int_write_data_queue: yield self.int_write_data_sync wdata, strb, last = self.int_write_data_queue.pop(0) + self.mem.seek(cur_word_addr % self.size) + data = bytearray() for i in range(bw): data.extend(bytearray([wdata & 0xff])) wdata >>= 8 for i in range(bw): if strb & (1 << i): - self.mem.write(data[i:i+1]) + self.mem.write(bytes(data[i:i+1])) else: self.mem.seek(1, 1) if n == length-1: self.int_write_resp_queue.append((awid, 0b00)) self.int_write_resp_sync.next = not self.int_write_resp_sync + if last != (n == length-1): + print("Error: bad last assert") + raise StopSimulation assert last == (n == length-1) if name is not None: print("[%s] Write word id: %d addr: 0x%08x prot: 0x%x wstrb: 0x%02x data: %s" % (name, awid, cur_addr, prot, s_axi_wstrb, " ".join(("{:02x}".format(c) for c in bytearray(data))))) @@ -655,13 +776,16 @@ class AXIRam(object): @instance def write_addr_interface_logic(): while True: - s_axi_awready.next = True + s_axi_awready_int.next = True yield clk.posedge - if s_axi_awready & s_axi_awvalid: + if s_axi_awready and s_axi_awvalid_int: addr = int(s_axi_awaddr) - awid = int(s_axi_awid) + if s_axi_awid is not None: + awid = int(s_axi_awid) + else: + awid = 0 length = int(s_axi_awlen) size = int(s_axi_awsize) burst = int(s_axi_awburst) @@ -674,11 +798,11 @@ class AXIRam(object): @instance def write_data_interface_logic(): while True: - s_axi_wready.next = True + s_axi_wready_int.next = True yield clk.posedge - if s_axi_wready & s_axi_wvalid: + if s_axi_wready and s_axi_wvalid_int: data = int(s_axi_wdata) strb = int(s_axi_wstrb) last = bool(s_axi_wlast) @@ -691,12 +815,16 @@ class AXIRam(object): while not self.int_write_resp_queue: yield clk.posedge - s_axi_bid.next, s_axi_bresp.next = self.int_write_resp_queue.pop(0) - s_axi_bvalid.next = True + bid, bresp = self.int_write_resp_queue.pop(0) + if s_axi_bid is not None: + s_axi_bid.next = bid + s_axi_bresp.next = bresp + s_axi_bvalid.next = not (pause or bpause) yield clk.posedge - while s_axi_bvalid and not s_axi_bready: + while not s_axi_bvalid or not s_axi_bready: + s_axi_bvalid.next = s_axi_bvalid or not (pause or bpause) yield clk.posedge s_axi_bvalid.next = False @@ -709,6 +837,9 @@ class AXIRam(object): addr, arid, length, size, burst, lock, cache, prot = self.int_read_addr_queue.pop(0) + if name is not None: + print("[%s] Read burst arid: 0x%x araddr: 0x%08x arlen: %d arsize: %d" % (name, arid, addr, length, size)) + num_bytes = 2**size assert 0 < num_bytes <= bw @@ -752,13 +883,16 @@ class AXIRam(object): @instance def read_addr_interface_logic(): while True: - s_axi_arready.next = True + s_axi_arready_int.next = True yield clk.posedge - if s_axi_arready & s_axi_arvalid: + if s_axi_arready and s_axi_arvalid_int: addr = int(s_axi_araddr) - arid = int(s_axi_arid) + if s_axi_arid is not None: + arid = int(s_axi_arid) + else: + arid = 0 length = int(s_axi_arlen) size = int(s_axi_arsize) burst = int(s_axi_arburst) @@ -774,12 +908,18 @@ class AXIRam(object): while not self.int_read_resp_queue: yield clk.posedge - s_axi_rid.next, s_axi_rdata.next, s_axi_rresp.next, s_axi_rlast.next = self.int_read_resp_queue.pop(0) - s_axi_rvalid.next = True + rid, rdata, rresp, rlast = self.int_read_resp_queue.pop(0) + if s_axi_rid is not None: + s_axi_rid.next = rid + s_axi_rdata.next = rdata + s_axi_rresp.next = rresp + s_axi_rlast.next = rlast + s_axi_rvalid.next = not (pause or rpause) yield clk.posedge - while s_axi_rvalid and not s_axi_rready: + while not s_axi_rvalid or not s_axi_rready: + s_axi_rvalid.next = s_axi_rvalid or not (pause or rpause) yield clk.posedge s_axi_rvalid.next = False