diff --git a/fpga/mqnic/AU200/fpga_100g/fpga.xdc b/fpga/mqnic/AU200/fpga_100g/fpga.xdc index 2fdbd7003..bb86ee770 100644 --- a/fpga/mqnic/AU200/fpga_100g/fpga.xdc +++ b/fpga/mqnic/AU200/fpga_100g/fpga.xdc @@ -11,7 +11,6 @@ set_property BITSTREAM.CONFIG.CONFIGRATE 63.8 [current_design] set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] -set_property BITSTREAM.CONFIG.SPI_OPCODE 8'h6B [current_design] set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] # System clocks diff --git a/fpga/mqnic/AU200/fpga_10g/fpga.xdc b/fpga/mqnic/AU200/fpga_10g/fpga.xdc index 3615daada..8558e3731 100644 --- a/fpga/mqnic/AU200/fpga_10g/fpga.xdc +++ b/fpga/mqnic/AU200/fpga_10g/fpga.xdc @@ -11,7 +11,6 @@ set_property BITSTREAM.CONFIG.CONFIGRATE 63.8 [current_design] set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] -set_property BITSTREAM.CONFIG.SPI_OPCODE 8'h6B [current_design] set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] # System clocks diff --git a/fpga/mqnic/AU250/fpga_100g/fpga.xdc b/fpga/mqnic/AU250/fpga_100g/fpga.xdc index 658a4614a..55199086f 100644 --- a/fpga/mqnic/AU250/fpga_100g/fpga.xdc +++ b/fpga/mqnic/AU250/fpga_100g/fpga.xdc @@ -11,7 +11,6 @@ set_property BITSTREAM.CONFIG.CONFIGRATE 63.8 [current_design] set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] -set_property BITSTREAM.CONFIG.SPI_OPCODE 8'h6B [current_design] set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] # System clocks diff --git a/fpga/mqnic/AU250/fpga_10g/fpga.xdc b/fpga/mqnic/AU250/fpga_10g/fpga.xdc index 42ded87f0..fc1f527c1 100644 --- a/fpga/mqnic/AU250/fpga_10g/fpga.xdc +++ b/fpga/mqnic/AU250/fpga_10g/fpga.xdc @@ -11,7 +11,6 @@ set_property BITSTREAM.CONFIG.CONFIGRATE 63.8 [current_design] set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design] set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] -set_property BITSTREAM.CONFIG.SPI_OPCODE 8'h6B [current_design] set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] # System clocks