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MAC optimizations
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14d8819cd3
commit
5e12f97518
@ -126,7 +126,7 @@ lfsr #(
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.STYLE("AUTO")
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)
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eth_crc_8 (
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.data_in(last_cycle ? xgmii_rxd_d1[39:32] : xgmii_rxd_d0[7:0]),
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.data_in(xgmii_rxd_d0[7:0]),
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.state_in(last_cycle ? crc_state3 : crc_state),
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.data_out(),
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.state_out(crc_next0)
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@ -142,7 +142,7 @@ lfsr #(
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.STYLE("AUTO")
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)
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eth_crc_16 (
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.data_in(last_cycle ? xgmii_rxd_d1[47:32] : xgmii_rxd_d0[15:0]),
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.data_in(xgmii_rxd_d0[15:0]),
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.state_in(last_cycle ? crc_state3 : crc_state),
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.data_out(),
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.state_out(crc_next1)
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@ -158,7 +158,7 @@ lfsr #(
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.STYLE("AUTO")
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)
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eth_crc_24 (
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.data_in(last_cycle ? xgmii_rxd_d1[55:32] : xgmii_rxd_d0[23:0]),
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.data_in(xgmii_rxd_d0[23:0]),
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.state_in(last_cycle ? crc_state3 : crc_state),
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.data_out(),
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.state_out(crc_next2)
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@ -174,7 +174,7 @@ lfsr #(
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.STYLE("AUTO")
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)
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eth_crc_32 (
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.data_in(last_cycle ? xgmii_rxd_d1[63:32] : xgmii_rxd_d0[31:0]),
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.data_in(xgmii_rxd_d0[31:0]),
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.state_in(last_cycle ? crc_state3 : crc_state),
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.data_out(),
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.state_out(crc_next3)
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@ -423,8 +423,8 @@ always @(posedge clk) begin
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xgmii_rxc_d0 <= xgmii_rxc;
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end else if (xgmii_rxc[4] && xgmii_rxd[39:32] == 8'hfb) begin
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lanes_swapped <= 1'b1;
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xgmii_rxd_d0 <= 64'h0707070707070707;
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xgmii_rxc_d0 <= 8'b11111111;
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xgmii_rxd_d0 <= {xgmii_rxd[31:0], swap_rxd};
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xgmii_rxc_d0 <= {xgmii_rxc[3:0], swap_rxc};
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end else if (lanes_swapped) begin
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xgmii_rxd_d0 <= {xgmii_rxd[31:0], swap_rxd};
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xgmii_rxc_d0 <= {xgmii_rxc[3:0], swap_rxc};
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@ -433,6 +433,11 @@ always @(posedge clk) begin
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xgmii_rxc_d0 <= xgmii_rxc;
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end
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if (state_next == STATE_LAST) begin
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xgmii_rxd_d0[31:0] <= xgmii_rxd_d0[63:32];
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xgmii_rxc_d0[3:0] <= xgmii_rxc_d0[7:4];
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end
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xgmii_rxd_d1 <= xgmii_rxd_d0;
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xgmii_rxc_d1 <= xgmii_rxc_d0;
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@ -99,6 +99,8 @@ reg [7:0] fcs_output_txc_1;
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reg [7:0] ifg_offset;
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reg extra_cycle;
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reg [15:0] frame_ptr_reg = 16'd0, frame_ptr_next;
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reg [7:0] ifg_count_reg = 8'd0, ifg_count_next;
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@ -301,6 +303,7 @@ always @* begin
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fcs_output_txc_0 = 8'b11100000;
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fcs_output_txc_1 = 8'b11111111;
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ifg_offset = 8'd3;
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extra_cycle = 1'b0;
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end
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8'bzzzzz011: begin
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fcs_output_txd_0 = {16'h07fd, ~crc_next1[31:0], input_tdata_reg[15:0]};
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@ -308,6 +311,7 @@ always @* begin
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fcs_output_txc_0 = 8'b11000000;
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fcs_output_txc_1 = 8'b11111111;
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ifg_offset = 8'd2;
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extra_cycle = 1'b0;
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end
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8'bzzzz0111: begin
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fcs_output_txd_0 = {8'hfd, ~crc_next2[31:0], input_tdata_reg[23:0]};
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@ -315,6 +319,7 @@ always @* begin
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fcs_output_txc_0 = 8'b10000000;
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fcs_output_txc_1 = 8'b11111111;
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ifg_offset = 8'd1;
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extra_cycle = 1'b0;
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end
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8'bzzz01111: begin
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fcs_output_txd_0 = {~crc_next3[31:0], input_tdata_reg[31:0]};
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@ -322,6 +327,7 @@ always @* begin
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fcs_output_txc_0 = 8'b00000000;
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fcs_output_txc_1 = 8'b11111111;
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ifg_offset = 8'd8;
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extra_cycle = 1'b1;
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end
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8'bzz011111: begin
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fcs_output_txd_0 = {~crc_next4[23:0], input_tdata_reg[39:0]};
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@ -329,6 +335,7 @@ always @* begin
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fcs_output_txc_0 = 8'b00000000;
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fcs_output_txc_1 = 8'b11111110;
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ifg_offset = 8'd7;
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extra_cycle = 1'b1;
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end
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8'bz0111111: begin
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fcs_output_txd_0 = {~crc_next5[15:0], input_tdata_reg[47:0]};
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@ -336,6 +343,7 @@ always @* begin
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fcs_output_txc_0 = 8'b00000000;
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fcs_output_txc_1 = 8'b11111100;
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ifg_offset = 8'd6;
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extra_cycle = 1'b1;
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end
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8'b01111111: begin
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fcs_output_txd_0 = {~crc_next6[7:0], input_tdata_reg[55:0]};
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@ -343,6 +351,7 @@ always @* begin
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fcs_output_txc_0 = 8'b00000000;
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fcs_output_txc_1 = 8'b11111000;
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ifg_offset = 8'd5;
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extra_cycle = 1'b1;
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end
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8'b11111111: begin
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fcs_output_txd_0 = input_tdata_reg;
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@ -350,6 +359,7 @@ always @* begin
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fcs_output_txc_0 = 8'b00000000;
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fcs_output_txc_1 = 8'b11110000;
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ifg_offset = 8'd4;
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extra_cycle = 1'b1;
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end
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default: begin
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fcs_output_txd_0 = 64'd0;
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@ -357,6 +367,7 @@ always @* begin
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fcs_output_txc_0 = 8'd0;
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fcs_output_txc_1 = 8'd0;
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ifg_offset = 8'd0;
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extra_cycle = 1'b1;
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end
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endcase
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end
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@ -500,7 +511,7 @@ always @* begin
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frame_ptr_next = 16'd0;
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ifg_count_next = (ifg_delay > 8'd12 ? ifg_delay : 8'd12) - ifg_offset + (lanes_swapped ? 8'd4 : 8'd0) + deficit_idle_count_reg;
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if (fcs_output_txc_1 != 8'hff || fcs_output_txc_0 == 8'd0) begin
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if (extra_cycle) begin
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state_next = STATE_FCS_2;
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end else begin
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state_next = STATE_IFG;
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@ -652,8 +663,8 @@ always @(posedge clk) begin
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end else begin
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if (swap_lanes) begin
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lanes_swapped <= 1'b1;
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xgmii_txd_reg <= {xgmii_txd_next[31:0], 32'h07070707};
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xgmii_txc_reg <= {xgmii_txc_next[3:0], 4'b1111};
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xgmii_txd_reg <= {xgmii_txd_next[31:0], swap_txd};
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xgmii_txc_reg <= {xgmii_txc_next[3:0], swap_txc};
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end else begin
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xgmii_txd_reg <= xgmii_txd_next;
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xgmii_txc_reg <= xgmii_txc_next;
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