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Rework PHY bitslip timing

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This commit is contained in:
Alex Forencich 2021-05-05 00:35:43 -07:00
parent c021d01c26
commit 5e1329a992
17 changed files with 78 additions and 46 deletions
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6
rtl/eth_mac_phy_10g.v
View File

@ -52,7 +52,8 @@ module eth_mac_phy_10g #
parameter PRBS31_ENABLE = 0,
parameter TX_SERDES_PIPELINE = 0,
parameter RX_SERDES_PIPELINE = 0,
parameter SLIP_COUNT_WIDTH = 3,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 8,
parameter COUNT_125US = 125000/6.4
)
(
@ -132,7 +133,8 @@ eth_mac_phy_10g_rx #(
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.SERDES_PIPELINE(RX_SERDES_PIPELINE),
.SLIP_COUNT_WIDTH(SLIP_COUNT_WIDTH),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
eth_mac_phy_10g_rx_inst (

6
rtl/eth_mac_phy_10g_fifo.v
View File

@ -44,7 +44,8 @@ module eth_mac_phy_10g_fifo #
parameter PRBS31_ENABLE = 0,
parameter TX_SERDES_PIPELINE = 0,
parameter RX_SERDES_PIPELINE = 0,
parameter SLIP_COUNT_WIDTH = 3,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 8,
parameter COUNT_125US = 125000/6.4,
parameter TX_FIFO_DEPTH = 4096,
parameter TX_FIFO_PIPELINE_OUTPUT = 2,
@ -560,7 +561,8 @@ eth_mac_phy_10g #(
.PRBS31_ENABLE(PRBS31_ENABLE),
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
.SLIP_COUNT_WIDTH(SLIP_COUNT_WIDTH),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
eth_mac_phy_10g_inst (

6
rtl/eth_mac_phy_10g_rx.v
View File

@ -43,7 +43,8 @@ module eth_mac_phy_10g_rx #
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter SERDES_PIPELINE = 0,
parameter SLIP_COUNT_WIDTH = 3,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 8,
parameter COUNT_125US = 125000/6.4
)
(
@ -116,7 +117,8 @@ eth_phy_10g_rx_if #(
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.SERDES_PIPELINE(SERDES_PIPELINE),
.SLIP_COUNT_WIDTH(SLIP_COUNT_WIDTH),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
eth_phy_10g_rx_if_inst (

6
rtl/eth_phy_10g.v
View File

@ -39,7 +39,8 @@ module eth_phy_10g #
parameter PRBS31_ENABLE = 0,
parameter TX_SERDES_PIPELINE = 0,
parameter RX_SERDES_PIPELINE = 0,
parameter SLIP_COUNT_WIDTH = 3,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 8,
parameter COUNT_125US = 125000/6.4
)
(
@ -88,7 +89,8 @@ eth_phy_10g_rx #(
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.SERDES_PIPELINE(RX_SERDES_PIPELINE),
.SLIP_COUNT_WIDTH(SLIP_COUNT_WIDTH),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
eth_phy_10g_rx_inst (

6
rtl/eth_phy_10g_rx.v
View File

@ -38,7 +38,8 @@ module eth_phy_10g_rx #
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter SERDES_PIPELINE = 0,
parameter SLIP_COUNT_WIDTH = 3,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 8,
parameter COUNT_125US = 125000/6.4
)
(
@ -100,7 +101,8 @@ eth_phy_10g_rx_if #(
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.SERDES_PIPELINE(SERDES_PIPELINE),
.SLIP_COUNT_WIDTH(SLIP_COUNT_WIDTH),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
eth_phy_10g_rx_if_inst (

39
rtl/eth_phy_10g_rx_frame_sync.v
View File

@ -32,7 +32,8 @@ THE SOFTWARE.
module eth_phy_10g_rx_frame_sync #
(
parameter HDR_WIDTH = 2,
parameter SLIP_COUNT_WIDTH = 3
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 8
)
(
input wire clk,
@ -50,6 +51,9 @@ module eth_phy_10g_rx_frame_sync #
output wire rx_block_lock
);
parameter BITSLIP_MAX_CYCLES = BITSLIP_HIGH_CYCLES > BITSLIP_LOW_CYCLES ? BITSLIP_HIGH_CYCLES : BITSLIP_LOW_CYCLES;
parameter BITSLIP_COUNT_WIDTH = $clog2(BITSLIP_MAX_CYCLES);
// bus width assertions
initial begin
if (HDR_WIDTH != 2) begin
@ -64,7 +68,7 @@ localparam [1:0]
reg [5:0] sh_count_reg = 6'd0, sh_count_next;
reg [3:0] sh_invalid_count_reg = 4'd0, sh_invalid_count_next;
reg [SLIP_COUNT_WIDTH-1:0] slip_count_reg = 0, slip_count_next;
reg [BITSLIP_COUNT_WIDTH-1:0] bitslip_count_reg = 0, bitslip_count_next;
reg serdes_rx_bitslip_reg = 1'b0, serdes_rx_bitslip_next;
@ -76,14 +80,17 @@ assign rx_block_lock = rx_block_lock_reg;
always @* begin
sh_count_next = sh_count_reg;
sh_invalid_count_next = sh_invalid_count_reg;
slip_count_next = slip_count_reg;
bitslip_count_next = bitslip_count_reg;
serdes_rx_bitslip_next = 1'b0;
serdes_rx_bitslip_next = serdes_rx_bitslip_reg;
rx_block_lock_next = rx_block_lock_reg;
if (slip_count_reg) begin
slip_count_next = slip_count_reg-1;
if (bitslip_count_reg) begin
bitslip_count_next = bitslip_count_reg-1;
end else if (serdes_rx_bitslip_reg) begin
serdes_rx_bitslip_next = 1'b0;
bitslip_count_next = BITSLIP_LOW_CYCLES > 0 ? BITSLIP_LOW_CYCLES-1 : 0;
end else if (serdes_rx_hdr == SYNC_CTRL || serdes_rx_hdr == SYNC_DATA) begin
// valid header
sh_count_next = sh_count_reg + 1;
@ -104,8 +111,10 @@ always @* begin
sh_count_next = 0;
sh_invalid_count_next = 0;
rx_block_lock_next = 1'b0;
// slip one bit
serdes_rx_bitslip_next = 1'b1;
slip_count_next = {SLIP_COUNT_WIDTH{1'b1}};
bitslip_count_next = BITSLIP_HIGH_CYCLES > 0 ? BITSLIP_HIGH_CYCLES-1 : 0;
end else if (&sh_count_reg) begin
// valid count overflow, reset
sh_count_next = 0;
@ -115,19 +124,19 @@ always @* begin
end
always @(posedge clk) begin
sh_count_reg <= sh_count_next;
sh_invalid_count_reg <= sh_invalid_count_next;
bitslip_count_reg <= bitslip_count_next;
serdes_rx_bitslip_reg <= serdes_rx_bitslip_next;
rx_block_lock_reg <= rx_block_lock_next;
if (rst) begin
sh_count_reg <= 6'd0;
sh_invalid_count_reg <= 4'd0;
slip_count_reg <= 0;
bitslip_count_reg <= 0;
serdes_rx_bitslip_reg <= 1'b0;
rx_block_lock_reg <= 1'b0;
end else begin
sh_count_reg <= sh_count_next;
sh_invalid_count_reg <= sh_invalid_count_next;
slip_count_reg <= slip_count_next;
rx_block_lock_reg <= rx_block_lock_next;
end
serdes_rx_bitslip_reg <= serdes_rx_bitslip_next;
end
endmodule

6
rtl/eth_phy_10g_rx_if.v
View File

@ -37,7 +37,8 @@ module eth_phy_10g_rx_if #
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter SERDES_PIPELINE = 0,
parameter SLIP_COUNT_WIDTH = 3,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 8,
parameter COUNT_125US = 125000/6.4
)
(
@ -218,7 +219,8 @@ assign serdes_rx_bitslip = serdes_rx_bitslip_int && !(PRBS31_ENABLE && rx_prbs31
eth_phy_10g_rx_frame_sync #(
.HDR_WIDTH(HDR_WIDTH),
.SLIP_COUNT_WIDTH(SLIP_COUNT_WIDTH)
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES)
)
eth_phy_10g_rx_frame_sync_inst (
.clk(clk),

3
tb/test_eth_mac_phy_10g.py
View File

@ -76,7 +76,8 @@ def bench():
PRBS31_ENABLE = 1
TX_SERDES_PIPELINE = 2
RX_SERDES_PIPELINE = 2
SLIP_COUNT_WIDTH = 3
BITSLIP_HIGH_CYCLES = 1
BITSLIP_LOW_CYCLES = 8
COUNT_125US = 125000/6.4
# Inputs

6
tb/test_eth_mac_phy_10g.v
View File

@ -53,7 +53,8 @@ parameter SCRAMBLER_DISABLE = 0;
parameter PRBS31_ENABLE = 1;
parameter TX_SERDES_PIPELINE = 2;
parameter RX_SERDES_PIPELINE = 2;
parameter SLIP_COUNT_WIDTH = 3;
parameter BITSLIP_HIGH_CYCLES = 1;
parameter BITSLIP_LOW_CYCLES = 8;
parameter COUNT_125US = 125000/6.4;
// Inputs
@ -175,7 +176,8 @@ eth_mac_phy_10g #(
.PRBS31_ENABLE(PRBS31_ENABLE),
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
.SLIP_COUNT_WIDTH(SLIP_COUNT_WIDTH),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
UUT (

3
tb/test_eth_mac_phy_10g_fifo.py
View File

@ -71,7 +71,8 @@ def bench():
PRBS31_ENABLE = 1
TX_SERDES_PIPELINE = 2
RX_SERDES_PIPELINE = 2
SLIP_COUNT_WIDTH = 3
BITSLIP_HIGH_CYCLES = 1
BITSLIP_LOW_CYCLES = 8
COUNT_125US = 125000/6.4
TX_FIFO_DEPTH = 4096
TX_FIFO_PIPELINE_OUTPUT = 2

6
tb/test_eth_mac_phy_10g_fifo.v
View File

@ -45,7 +45,8 @@ parameter SCRAMBLER_DISABLE = 0;
parameter PRBS31_ENABLE = 1;
parameter TX_SERDES_PIPELINE = 2;
parameter RX_SERDES_PIPELINE = 2;
parameter SLIP_COUNT_WIDTH = 3;
parameter BITSLIP_HIGH_CYCLES = 1;
parameter BITSLIP_LOW_CYCLES = 8;
parameter COUNT_125US = 125000/6.4;
parameter TX_FIFO_DEPTH = 4096;
parameter TX_FIFO_PIPELINE_OUTPUT = 2;
@ -171,7 +172,8 @@ eth_mac_phy_10g_fifo #(
.PRBS31_ENABLE(PRBS31_ENABLE),
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
.SLIP_COUNT_WIDTH(SLIP_COUNT_WIDTH),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.TX_FIFO_PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT),

3
tb/test_eth_mac_phy_10g_fifo_ptp.py
View File

@ -76,7 +76,8 @@ def bench():
PRBS31_ENABLE = 1
TX_SERDES_PIPELINE = 2
RX_SERDES_PIPELINE = 2
SLIP_COUNT_WIDTH = 3
BITSLIP_HIGH_CYCLES = 1
BITSLIP_LOW_CYCLES = 8
COUNT_125US = 125000/6.4
TX_FIFO_DEPTH = 4096
TX_FIFO_PIPELINE_OUTPUT = 2

10
tb/test_eth_mac_phy_10g_fifo_ptp.v
View File

@ -45,7 +45,8 @@ parameter SCRAMBLER_DISABLE = 0;
parameter PRBS31_ENABLE = 1;
parameter TX_SERDES_PIPELINE = 2;
parameter RX_SERDES_PIPELINE = 2;
parameter SLIP_COUNT_WIDTH = 3;
parameter BITSLIP_HIGH_CYCLES = 1;
parameter BITSLIP_LOW_CYCLES = 8;
parameter COUNT_125US = 125000/6.4;
parameter TX_FIFO_DEPTH = 4096;
parameter TX_FIFO_PIPELINE_OUTPUT = 2;
@ -57,8 +58,6 @@ parameter RX_FIFO_PIPELINE_OUTPUT = 2;
parameter RX_FRAME_FIFO = 1;
parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO;
parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO;
parameter LOGIC_PTP_PERIOD_NS = 4'h6;
parameter LOGIC_PTP_PERIOD_FNS = 16'h6666;
parameter PTP_PERIOD_NS = 4'h6;
parameter PTP_PERIOD_FNS = 16'h6666;
parameter PTP_USE_SAMPLE_CLOCK = 0;
@ -207,7 +206,8 @@ eth_mac_phy_10g_fifo #(
.PRBS31_ENABLE(PRBS31_ENABLE),
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
.SLIP_COUNT_WIDTH(SLIP_COUNT_WIDTH),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.TX_FIFO_PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT),
@ -219,8 +219,6 @@ eth_mac_phy_10g_fifo #(
.RX_FRAME_FIFO(RX_FRAME_FIFO),
.RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
.RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL),
.LOGIC_PTP_PERIOD_NS(LOGIC_PTP_PERIOD_NS),
.LOGIC_PTP_PERIOD_FNS(LOGIC_PTP_PERIOD_FNS),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),

3
tb/test_eth_phy_10g_64.py
View File

@ -63,7 +63,8 @@ def bench():
PRBS31_ENABLE = 1
TX_SERDES_PIPELINE = 2
RX_SERDES_PIPELINE = 2
SLIP_COUNT_WIDTH = 3
BITSLIP_HIGH_CYCLES = 1
BITSLIP_LOW_CYCLES = 8
COUNT_125US = 1250/6.4
# Inputs

6
tb/test_eth_phy_10g_64.v
View File

@ -40,7 +40,8 @@ parameter SCRAMBLER_DISABLE = 0;
parameter PRBS31_ENABLE = 1;
parameter TX_SERDES_PIPELINE = 2;
parameter RX_SERDES_PIPELINE = 2;
parameter SLIP_COUNT_WIDTH = 3;
parameter BITSLIP_HIGH_CYCLES = 1;
parameter BITSLIP_LOW_CYCLES = 8;
parameter COUNT_125US = 125000/6.4;
// Inputs
@ -113,7 +114,8 @@ eth_phy_10g #(
.PRBS31_ENABLE(PRBS31_ENABLE),
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
.SLIP_COUNT_WIDTH(SLIP_COUNT_WIDTH),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
UUT (

3
tb/test_eth_phy_10g_rx_64.py
View File

@ -69,7 +69,8 @@ def bench():
SCRAMBLER_DISABLE = 0
PRBS31_ENABLE = 1
SERDES_PIPELINE = 2
SLIP_COUNT_WIDTH = 3
BITSLIP_HIGH_CYCLES = 1
BITSLIP_LOW_CYCLES = 8
COUNT_125US = 1250/6.4
# Inputs

6
tb/test_eth_phy_10g_rx_64.v
View File

@ -39,7 +39,8 @@ parameter BIT_REVERSE = 0;
parameter SCRAMBLER_DISABLE = 0;
parameter PRBS31_ENABLE = 1;
parameter SERDES_PIPELINE = 2;
parameter SLIP_COUNT_WIDTH = 3;
parameter BITSLIP_HIGH_CYCLES = 1;
parameter BITSLIP_LOW_CYCLES = 8;
parameter COUNT_125US = 1250/6.4;
// Inputs
@ -93,7 +94,8 @@ eth_phy_10g_rx #(
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.SERDES_PIPELINE(SERDES_PIPELINE),
.SLIP_COUNT_WIDTH(SLIP_COUNT_WIDTH),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
UUT (