From 5e528e005713946e3eb95e8c9b2ca6db525bf6fe Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Tue, 1 Nov 2022 23:56:11 -0700 Subject: [PATCH] Update FIFO PIPELINE_OUTPUT to RAM_PIPELINE Signed-off-by: Alex Forencich --- rtl/eth_mac_10g_fifo.v | 8 ++++---- rtl/eth_mac_1g_fifo.v | 4 ++++ rtl/eth_mac_1g_gmii_fifo.v | 8 ++++---- rtl/eth_mac_1g_rgmii_fifo.v | 8 ++++---- rtl/eth_mac_mii_fifo.v | 8 ++++---- rtl/eth_mac_phy_10g_fifo.v | 8 ++++---- tb/eth_mac_10g_fifo/Makefile | 12 ++++++------ tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py | 4 ++-- tb/eth_mac_phy_10g_fifo/Makefile | 12 ++++++------ tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py | 4 ++-- 10 files changed, 40 insertions(+), 36 deletions(-) diff --git a/rtl/eth_mac_10g_fifo.v b/rtl/eth_mac_10g_fifo.v index 2be5811c9..f98fff1ac 100644 --- a/rtl/eth_mac_10g_fifo.v +++ b/rtl/eth_mac_10g_fifo.v @@ -42,13 +42,13 @@ module eth_mac_10g_fifo # parameter ENABLE_DIC = 1, parameter MIN_FRAME_LENGTH = 64, parameter TX_FIFO_DEPTH = 4096, - parameter TX_FIFO_PIPELINE_OUTPUT = 2, + parameter TX_FIFO_RAM_PIPELINE = 1, parameter TX_FRAME_FIFO = 1, parameter TX_DROP_OVERSIZE_FRAME = TX_FRAME_FIFO, parameter TX_DROP_BAD_FRAME = TX_DROP_OVERSIZE_FRAME, parameter TX_DROP_WHEN_FULL = 0, parameter RX_FIFO_DEPTH = 4096, - parameter RX_FIFO_PIPELINE_OUTPUT = 2, + parameter RX_FIFO_RAM_PIPELINE = 1, parameter RX_FRAME_FIFO = 1, parameter RX_DROP_OVERSIZE_FRAME = RX_FRAME_FIFO, parameter RX_DROP_BAD_FRAME = RX_DROP_OVERSIZE_FRAME, @@ -395,7 +395,7 @@ axis_async_fifo_adapter #( .DEST_ENABLE(0), .USER_ENABLE(1), .USER_WIDTH(TX_USER_WIDTH), - .PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT), + .RAM_PIPELINE(TX_FIFO_RAM_PIPELINE), .FRAME_FIFO(TX_FRAME_FIFO), .USER_BAD_FRAME_VALUE(1'b1), .USER_BAD_FRAME_MASK(1'b1), @@ -447,7 +447,7 @@ axis_async_fifo_adapter #( .DEST_ENABLE(0), .USER_ENABLE(1), .USER_WIDTH(RX_USER_WIDTH), - .PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT), + .RAM_PIPELINE(RX_FIFO_RAM_PIPELINE), .FRAME_FIFO(RX_FRAME_FIFO), .USER_BAD_FRAME_VALUE(1'b1), .USER_BAD_FRAME_MASK(1'b1), diff --git a/rtl/eth_mac_1g_fifo.v b/rtl/eth_mac_1g_fifo.v index c16a86cb5..fc6bf7e0e 100644 --- a/rtl/eth_mac_1g_fifo.v +++ b/rtl/eth_mac_1g_fifo.v @@ -39,11 +39,13 @@ module eth_mac_1g_fifo # parameter ENABLE_PADDING = 1, parameter MIN_FRAME_LENGTH = 64, parameter TX_FIFO_DEPTH = 4096, + parameter TX_FIFO_RAM_PIPELINE = 1, parameter TX_FRAME_FIFO = 1, parameter TX_DROP_OVERSIZE_FRAME = TX_FRAME_FIFO, parameter TX_DROP_BAD_FRAME = TX_DROP_OVERSIZE_FRAME, parameter TX_DROP_WHEN_FULL = 0, parameter RX_FIFO_DEPTH = 4096, + parameter RX_FIFO_RAM_PIPELINE = 1, parameter RX_FRAME_FIFO = 1, parameter RX_DROP_OVERSIZE_FRAME = RX_FRAME_FIFO, parameter RX_DROP_BAD_FRAME = RX_DROP_OVERSIZE_FRAME, @@ -231,6 +233,7 @@ axis_async_fifo_adapter #( .DEST_ENABLE(0), .USER_ENABLE(1), .USER_WIDTH(1), + .RAM_PIPELINE(TX_FIFO_RAM_PIPELINE), .FRAME_FIFO(TX_FRAME_FIFO), .USER_BAD_FRAME_VALUE(1'b1), .USER_BAD_FRAME_MASK(1'b1), @@ -281,6 +284,7 @@ axis_async_fifo_adapter #( .DEST_ENABLE(0), .USER_ENABLE(1), .USER_WIDTH(1), + .RAM_PIPELINE(RX_FIFO_RAM_PIPELINE), .FRAME_FIFO(RX_FRAME_FIFO), .USER_BAD_FRAME_VALUE(1'b1), .USER_BAD_FRAME_MASK(1'b1), diff --git a/rtl/eth_mac_1g_gmii_fifo.v b/rtl/eth_mac_1g_gmii_fifo.v index d85774787..2c6763047 100644 --- a/rtl/eth_mac_1g_gmii_fifo.v +++ b/rtl/eth_mac_1g_gmii_fifo.v @@ -50,13 +50,13 @@ module eth_mac_1g_gmii_fifo # parameter ENABLE_PADDING = 1, parameter MIN_FRAME_LENGTH = 64, parameter TX_FIFO_DEPTH = 4096, - parameter TX_FIFO_PIPELINE_OUTPUT = 2, + parameter TX_FIFO_RAM_PIPELINE = 1, parameter TX_FRAME_FIFO = 1, parameter TX_DROP_OVERSIZE_FRAME = TX_FRAME_FIFO, parameter TX_DROP_BAD_FRAME = TX_DROP_OVERSIZE_FRAME, parameter TX_DROP_WHEN_FULL = 0, parameter RX_FIFO_DEPTH = 4096, - parameter RX_FIFO_PIPELINE_OUTPUT = 2, + parameter RX_FIFO_RAM_PIPELINE = 1, parameter RX_FRAME_FIFO = 1, parameter RX_DROP_OVERSIZE_FRAME = RX_FRAME_FIFO, parameter RX_DROP_BAD_FRAME = RX_DROP_OVERSIZE_FRAME, @@ -260,7 +260,7 @@ axis_async_fifo_adapter #( .DEST_ENABLE(0), .USER_ENABLE(1), .USER_WIDTH(1), - .PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT), + .RAM_PIPELINE(TX_FIFO_RAM_PIPELINE), .FRAME_FIFO(TX_FRAME_FIFO), .USER_BAD_FRAME_VALUE(1'b1), .USER_BAD_FRAME_MASK(1'b1), @@ -311,7 +311,7 @@ axis_async_fifo_adapter #( .DEST_ENABLE(0), .USER_ENABLE(1), .USER_WIDTH(1), - .PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT), + .RAM_PIPELINE(RX_FIFO_RAM_PIPELINE), .FRAME_FIFO(RX_FRAME_FIFO), .USER_BAD_FRAME_VALUE(1'b1), .USER_BAD_FRAME_MASK(1'b1), diff --git a/rtl/eth_mac_1g_rgmii_fifo.v b/rtl/eth_mac_1g_rgmii_fifo.v index 6855a9949..bf97dc594 100644 --- a/rtl/eth_mac_1g_rgmii_fifo.v +++ b/rtl/eth_mac_1g_rgmii_fifo.v @@ -51,13 +51,13 @@ module eth_mac_1g_rgmii_fifo # parameter ENABLE_PADDING = 1, parameter MIN_FRAME_LENGTH = 64, parameter TX_FIFO_DEPTH = 4096, - parameter TX_FIFO_PIPELINE_OUTPUT = 2, + parameter TX_FIFO_RAM_PIPELINE = 1, parameter TX_FRAME_FIFO = 1, parameter TX_DROP_OVERSIZE_FRAME = TX_FRAME_FIFO, parameter TX_DROP_BAD_FRAME = TX_DROP_OVERSIZE_FRAME, parameter TX_DROP_WHEN_FULL = 0, parameter RX_FIFO_DEPTH = 4096, - parameter RX_FIFO_PIPELINE_OUTPUT = 2, + parameter RX_FIFO_RAM_PIPELINE = 1, parameter RX_FRAME_FIFO = 1, parameter RX_DROP_OVERSIZE_FRAME = RX_FRAME_FIFO, parameter RX_DROP_BAD_FRAME = RX_DROP_OVERSIZE_FRAME, @@ -258,7 +258,7 @@ axis_async_fifo_adapter #( .DEST_ENABLE(0), .USER_ENABLE(1), .USER_WIDTH(1), - .PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT), + .RAM_PIPELINE(TX_FIFO_RAM_PIPELINE), .FRAME_FIFO(TX_FRAME_FIFO), .USER_BAD_FRAME_VALUE(1'b1), .USER_BAD_FRAME_MASK(1'b1), @@ -309,7 +309,7 @@ axis_async_fifo_adapter #( .DEST_ENABLE(0), .USER_ENABLE(1), .USER_WIDTH(1), - .PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT), + .RAM_PIPELINE(RX_FIFO_RAM_PIPELINE), .FRAME_FIFO(RX_FRAME_FIFO), .USER_BAD_FRAME_VALUE(1'b1), .USER_BAD_FRAME_MASK(1'b1), diff --git a/rtl/eth_mac_mii_fifo.v b/rtl/eth_mac_mii_fifo.v index 1d70c7dee..9384ac149 100644 --- a/rtl/eth_mac_mii_fifo.v +++ b/rtl/eth_mac_mii_fifo.v @@ -46,13 +46,13 @@ module eth_mac_mii_fifo # parameter ENABLE_PADDING = 1, parameter MIN_FRAME_LENGTH = 64, parameter TX_FIFO_DEPTH = 4096, - parameter TX_FIFO_PIPELINE_OUTPUT = 2, + parameter TX_FIFO_RAM_PIPELINE = 1, parameter TX_FRAME_FIFO = 1, parameter TX_DROP_OVERSIZE_FRAME = TX_FRAME_FIFO, parameter TX_DROP_BAD_FRAME = TX_DROP_OVERSIZE_FRAME, parameter TX_DROP_WHEN_FULL = 0, parameter RX_FIFO_DEPTH = 4096, - parameter RX_FIFO_PIPELINE_OUTPUT = 2, + parameter RX_FIFO_RAM_PIPELINE = 1, parameter RX_FRAME_FIFO = 1, parameter RX_DROP_OVERSIZE_FRAME = RX_FRAME_FIFO, parameter RX_DROP_BAD_FRAME = RX_DROP_OVERSIZE_FRAME, @@ -237,7 +237,7 @@ axis_async_fifo_adapter #( .DEST_ENABLE(0), .USER_ENABLE(1), .USER_WIDTH(1), - .PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT), + .RAM_PIPELINE(TX_FIFO_RAM_PIPELINE), .FRAME_FIFO(TX_FRAME_FIFO), .USER_BAD_FRAME_VALUE(1'b1), .USER_BAD_FRAME_MASK(1'b1), @@ -288,7 +288,7 @@ axis_async_fifo_adapter #( .DEST_ENABLE(0), .USER_ENABLE(1), .USER_WIDTH(1), - .PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT), + .RAM_PIPELINE(RX_FIFO_RAM_PIPELINE), .FRAME_FIFO(RX_FRAME_FIFO), .USER_BAD_FRAME_VALUE(1'b1), .USER_BAD_FRAME_MASK(1'b1), diff --git a/rtl/eth_mac_phy_10g_fifo.v b/rtl/eth_mac_phy_10g_fifo.v index 85137f249..6b142e0e6 100644 --- a/rtl/eth_mac_phy_10g_fifo.v +++ b/rtl/eth_mac_phy_10g_fifo.v @@ -50,13 +50,13 @@ module eth_mac_phy_10g_fifo # parameter BITSLIP_LOW_CYCLES = 8, parameter COUNT_125US = 125000/6.4, parameter TX_FIFO_DEPTH = 4096, - parameter TX_FIFO_PIPELINE_OUTPUT = 2, + parameter TX_FIFO_RAM_PIPELINE = 1, parameter TX_FRAME_FIFO = 1, parameter TX_DROP_OVERSIZE_FRAME = TX_FRAME_FIFO, parameter TX_DROP_BAD_FRAME = TX_DROP_OVERSIZE_FRAME, parameter TX_DROP_WHEN_FULL = 0, parameter RX_FIFO_DEPTH = 4096, - parameter RX_FIFO_PIPELINE_OUTPUT = 2, + parameter RX_FIFO_RAM_PIPELINE = 1, parameter RX_FRAME_FIFO = 1, parameter RX_DROP_OVERSIZE_FRAME = RX_FRAME_FIFO, parameter RX_DROP_BAD_FRAME = RX_DROP_OVERSIZE_FRAME, @@ -439,7 +439,7 @@ axis_async_fifo_adapter #( .DEST_ENABLE(0), .USER_ENABLE(1), .USER_WIDTH(TX_USER_WIDTH), - .PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT), + .RAM_PIPELINE(TX_FIFO_RAM_PIPELINE), .FRAME_FIFO(TX_FRAME_FIFO), .USER_BAD_FRAME_VALUE(1'b1), .USER_BAD_FRAME_MASK(1'b1), @@ -491,7 +491,7 @@ axis_async_fifo_adapter #( .DEST_ENABLE(0), .USER_ENABLE(1), .USER_WIDTH(RX_USER_WIDTH), - .PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT), + .RAM_PIPELINE(RX_FIFO_RAM_PIPELINE), .FRAME_FIFO(RX_FRAME_FIFO), .USER_BAD_FRAME_VALUE(1'b1), .USER_BAD_FRAME_MASK(1'b1), diff --git a/tb/eth_mac_10g_fifo/Makefile b/tb/eth_mac_10g_fifo/Makefile index 52f4f3fd2..493f8c194 100644 --- a/tb/eth_mac_10g_fifo/Makefile +++ b/tb/eth_mac_10g_fifo/Makefile @@ -51,13 +51,13 @@ export PARAM_ENABLE_PADDING ?= 1 export PARAM_ENABLE_DIC ?= 1 export PARAM_MIN_FRAME_LENGTH ?= 64 export PARAM_TX_FIFO_DEPTH ?= 16384 -export PARAM_TX_FIFO_PIPELINE_OUTPUT ?= 2 +export PARAM_TX_FIFO_RAM_PIPELINE ?= 1 export PARAM_TX_FRAME_FIFO ?= 1 export PARAM_TX_DROP_OVERSIZE_FRAME ?= $(PARAM_TX_FRAME_FIFO) export PARAM_TX_DROP_BAD_FRAME ?= $(PARAM_TX_DROP_OVERSIZE_FRAME) export PARAM_TX_DROP_WHEN_FULL ?= 0 export PARAM_RX_FIFO_DEPTH ?= 16384 -export PARAM_RX_FIFO_PIPELINE_OUTPUT ?= 2 +export PARAM_RX_FIFO_RAM_PIPELINE ?= 1 export PARAM_RX_FRAME_FIFO ?= 1 export PARAM_RX_DROP_OVERSIZE_FRAME ?= $(PARAM_RX_FRAME_FIFO) export PARAM_RX_DROP_BAD_FRAME ?= $(PARAM_RX_DROP_OVERSIZE_FRAME) @@ -86,13 +86,13 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).ENABLE_DIC=$(PARAM_ENABLE_DIC) COMPILE_ARGS += -P $(TOPLEVEL).MIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) - COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_PIPELINE_OUTPUT=$(PARAM_TX_FIFO_PIPELINE_OUTPUT) + COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_RAM_PIPELINE=$(PARAM_TX_FIFO_RAM_PIPELINE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FRAME_FIFO=$(PARAM_TX_FRAME_FIFO) COMPILE_ARGS += -P $(TOPLEVEL).TX_DROP_OVERSIZE_FRAME=$(PARAM_TX_DROP_OVERSIZE_FRAME) COMPILE_ARGS += -P $(TOPLEVEL).TX_DROP_BAD_FRAME=$(PARAM_TX_DROP_BAD_FRAME) COMPILE_ARGS += -P $(TOPLEVEL).TX_DROP_WHEN_FULL=$(PARAM_TX_DROP_WHEN_FULL) COMPILE_ARGS += -P $(TOPLEVEL).RX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH) - COMPILE_ARGS += -P $(TOPLEVEL).RX_FIFO_PIPELINE_OUTPUT=$(PARAM_RX_FIFO_PIPELINE_OUTPUT) + COMPILE_ARGS += -P $(TOPLEVEL).RX_FIFO_RAM_PIPELINE=$(PARAM_RX_FIFO_RAM_PIPELINE) COMPILE_ARGS += -P $(TOPLEVEL).RX_FRAME_FIFO=$(PARAM_RX_FRAME_FIFO) COMPILE_ARGS += -P $(TOPLEVEL).RX_DROP_OVERSIZE_FRAME=$(PARAM_RX_DROP_OVERSIZE_FRAME) COMPILE_ARGS += -P $(TOPLEVEL).RX_DROP_BAD_FRAME=$(PARAM_RX_DROP_BAD_FRAME) @@ -125,13 +125,13 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GENABLE_DIC=$(PARAM_ENABLE_DIC) COMPILE_ARGS += -GMIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) - COMPILE_ARGS += -GTX_FIFO_PIPELINE_OUTPUT=$(PARAM_TX_FIFO_PIPELINE_OUTPUT) + COMPILE_ARGS += -GTX_FIFO_RAM_PIPELINE=$(PARAM_TX_FIFO_RAM_PIPELINE) COMPILE_ARGS += -GTX_FRAME_FIFO=$(PARAM_TX_FRAME_FIFO) COMPILE_ARGS += -GTX_DROP_OVERSIZE_FRAME=$(PARAM_TX_DROP_OVERSIZE_FRAME) COMPILE_ARGS += -GTX_DROP_BAD_FRAME=$(PARAM_TX_DROP_BAD_FRAME) COMPILE_ARGS += -GTX_DROP_WHEN_FULL=$(PARAM_TX_DROP_WHEN_FULL) COMPILE_ARGS += -GRX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH) - COMPILE_ARGS += -GRX_FIFO_PIPELINE_OUTPUT=$(PARAM_RX_FIFO_PIPELINE_OUTPUT) + COMPILE_ARGS += -GRX_FIFO_RAM_PIPELINE=$(PARAM_RX_FIFO_RAM_PIPELINE) COMPILE_ARGS += -GRX_FRAME_FIFO=$(PARAM_RX_FRAME_FIFO) COMPILE_ARGS += -GRX_DROP_OVERSIZE_FRAME=$(PARAM_RX_DROP_OVERSIZE_FRAME) COMPILE_ARGS += -GRX_DROP_BAD_FRAME=$(PARAM_RX_DROP_BAD_FRAME) diff --git a/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py b/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py index 10ddb6f5d..36338f5a2 100644 --- a/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py +++ b/tb/eth_mac_10g_fifo/test_eth_mac_10g_fifo.py @@ -322,13 +322,13 @@ def test_eth_mac_10g_fifo(request, data_width, enable_dic): parameters['ENABLE_DIC'] = enable_dic parameters['MIN_FRAME_LENGTH'] = 64 parameters['TX_FIFO_DEPTH'] = 16384 - parameters['TX_FIFO_PIPELINE_OUTPUT'] = 2 + parameters['TX_FIFO_RAM_PIPELINE'] = 1 parameters['TX_FRAME_FIFO'] = 1 parameters['TX_DROP_OVERSIZE_FRAME'] = parameters['TX_FRAME_FIFO'] parameters['TX_DROP_BAD_FRAME'] = parameters['TX_DROP_OVERSIZE_FRAME'] parameters['TX_DROP_WHEN_FULL'] = 0 parameters['RX_FIFO_DEPTH'] = 16384 - parameters['RX_FIFO_PIPELINE_OUTPUT'] = 2 + parameters['RX_FIFO_RAM_PIPELINE'] = 1 parameters['RX_FRAME_FIFO'] = 1 parameters['RX_DROP_OVERSIZE_FRAME'] = parameters['RX_FRAME_FIFO'] parameters['RX_DROP_BAD_FRAME'] = parameters['RX_DROP_OVERSIZE_FRAME'] diff --git a/tb/eth_mac_phy_10g_fifo/Makefile b/tb/eth_mac_phy_10g_fifo/Makefile index 2865a2a99..c99e99b62 100644 --- a/tb/eth_mac_phy_10g_fifo/Makefile +++ b/tb/eth_mac_phy_10g_fifo/Makefile @@ -56,13 +56,13 @@ export PARAM_ENABLE_PADDING ?= 1 export PARAM_ENABLE_DIC ?= 1 export PARAM_MIN_FRAME_LENGTH ?= 64 export PARAM_TX_FIFO_DEPTH ?= 16384 -export PARAM_TX_FIFO_PIPELINE_OUTPUT ?= 2 +export PARAM_TX_FIFO_RAM_PIPELINE ?= 1 export PARAM_TX_FRAME_FIFO ?= 1 export PARAM_TX_DROP_OVERSIZE_FRAME ?= $(PARAM_TX_FRAME_FIFO) export PARAM_TX_DROP_BAD_FRAME ?= $(PARAM_TX_DROP_OVERSIZE_FRAME) export PARAM_TX_DROP_WHEN_FULL ?= 0 export PARAM_RX_FIFO_DEPTH ?= 16384 -export PARAM_RX_FIFO_PIPELINE_OUTPUT ?= 2 +export PARAM_RX_FIFO_RAM_PIPELINE ?= 1 export PARAM_RX_FRAME_FIFO ?= 1 export PARAM_RX_DROP_OVERSIZE_FRAME ?= $(PARAM_RX_FRAME_FIFO) export PARAM_RX_DROP_BAD_FRAME ?= $(PARAM_RX_DROP_OVERSIZE_FRAME) @@ -99,13 +99,13 @@ ifeq ($(SIM), icarus) COMPILE_ARGS += -P $(TOPLEVEL).ENABLE_DIC=$(PARAM_ENABLE_DIC) COMPILE_ARGS += -P $(TOPLEVEL).MIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH) COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) - COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_PIPELINE_OUTPUT=$(PARAM_TX_FIFO_PIPELINE_OUTPUT) + COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_RAM_PIPELINE=$(PARAM_TX_FIFO_RAM_PIPELINE) COMPILE_ARGS += -P $(TOPLEVEL).TX_FRAME_FIFO=$(PARAM_TX_FRAME_FIFO) COMPILE_ARGS += -P $(TOPLEVEL).TX_DROP_OVERSIZE_FRAME=$(PARAM_TX_DROP_OVERSIZE_FRAME) COMPILE_ARGS += -P $(TOPLEVEL).TX_DROP_BAD_FRAME=$(PARAM_TX_DROP_BAD_FRAME) COMPILE_ARGS += -P $(TOPLEVEL).TX_DROP_WHEN_FULL=$(PARAM_TX_DROP_WHEN_FULL) COMPILE_ARGS += -P $(TOPLEVEL).RX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH) - COMPILE_ARGS += -P $(TOPLEVEL).RX_FIFO_PIPELINE_OUTPUT=$(PARAM_RX_FIFO_PIPELINE_OUTPUT) + COMPILE_ARGS += -P $(TOPLEVEL).RX_FIFO_RAM_PIPELINE=$(PARAM_RX_FIFO_RAM_PIPELINE) COMPILE_ARGS += -P $(TOPLEVEL).RX_FRAME_FIFO=$(PARAM_RX_FRAME_FIFO) COMPILE_ARGS += -P $(TOPLEVEL).RX_DROP_OVERSIZE_FRAME=$(PARAM_RX_DROP_OVERSIZE_FRAME) COMPILE_ARGS += -P $(TOPLEVEL).RX_DROP_BAD_FRAME=$(PARAM_RX_DROP_BAD_FRAME) @@ -146,13 +146,13 @@ else ifeq ($(SIM), verilator) COMPILE_ARGS += -GENABLE_DIC=$(PARAM_ENABLE_DIC) COMPILE_ARGS += -GMIN_FRAME_LENGTH=$(PARAM_MIN_FRAME_LENGTH) COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH) - COMPILE_ARGS += -GTX_FIFO_PIPELINE_OUTPUT=$(PARAM_TX_FIFO_PIPELINE_OUTPUT) + COMPILE_ARGS += -GTX_FIFO_RAM_PIPELINE=$(PARAM_TX_FIFO_RAM_PIPELINE) COMPILE_ARGS += -GTX_FRAME_FIFO=$(PARAM_TX_FRAME_FIFO) COMPILE_ARGS += -GTX_DROP_OVERSIZE_FRAME=$(PARAM_TX_DROP_OVERSIZE_FRAME) COMPILE_ARGS += -GTX_DROP_BAD_FRAME=$(PARAM_TX_DROP_BAD_FRAME) COMPILE_ARGS += -GTX_DROP_WHEN_FULL=$(PARAM_TX_DROP_WHEN_FULL) COMPILE_ARGS += -GRX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH) - COMPILE_ARGS += -GRX_FIFO_PIPELINE_OUTPUT=$(PARAM_RX_FIFO_PIPELINE_OUTPUT) + COMPILE_ARGS += -GRX_FIFO_RAM_PIPELINE=$(PARAM_RX_FIFO_RAM_PIPELINE) COMPILE_ARGS += -GRX_FRAME_FIFO=$(PARAM_RX_FRAME_FIFO) COMPILE_ARGS += -GRX_DROP_OVERSIZE_FRAME=$(PARAM_RX_DROP_OVERSIZE_FRAME) COMPILE_ARGS += -GRX_DROP_BAD_FRAME=$(PARAM_RX_DROP_BAD_FRAME) diff --git a/tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py b/tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py index aa5c9b7c6..1c553227f 100644 --- a/tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py +++ b/tb/eth_mac_phy_10g_fifo/test_eth_mac_phy_10g_fifo.py @@ -389,13 +389,13 @@ def test_eth_mac_phy_10g_fifo(request, data_width, enable_dic): parameters['ENABLE_DIC'] = enable_dic parameters['MIN_FRAME_LENGTH'] = 64 parameters['TX_FIFO_DEPTH'] = 16384 - parameters['TX_FIFO_PIPELINE_OUTPUT'] = 2 + parameters['TX_FIFO_RAM_PIPELINE'] = 1 parameters['TX_FRAME_FIFO'] = 1 parameters['TX_DROP_OVERSIZE_FRAME'] = parameters['TX_FRAME_FIFO'] parameters['TX_DROP_BAD_FRAME'] = parameters['TX_DROP_OVERSIZE_FRAME'] parameters['TX_DROP_WHEN_FULL'] = 0 parameters['RX_FIFO_DEPTH'] = 16384 - parameters['RX_FIFO_PIPELINE_OUTPUT'] = 2 + parameters['RX_FIFO_RAM_PIPELINE'] = 1 parameters['RX_FRAME_FIFO'] = 1 parameters['RX_DROP_OVERSIZE_FRAME'] = parameters['RX_FRAME_FIFO'] parameters['RX_DROP_BAD_FRAME'] = parameters['RX_DROP_OVERSIZE_FRAME']