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fpga/mqnic: Add MIGs and HBM controllers for most boards
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
parent
941288e926
commit
5e52a52f5e
@ -49,9 +49,9 @@ This section details PCIe form-factor targets, which interface with a separate h
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Nexus K35-S Gen 3 x8 2x SFP+ \- \-
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Nexus K3P-S Gen 3 x8 2x SFP28 4 GB DDR4 (1G x32) \-
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Nexus K3P-Q Gen 3 x8 2x QSFP28 8 GB DDR4 (1G x72) \-
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fb2CG\@KU15P Gen 3 x16 2x QSFP28 16 GB DDR4 2400 (4x 512M x72) \-
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fb2CG\@KU15P Gen 3 x16 2x QSFP28 16 GB DDR4 2666 (4x 512M x72) \-
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NetFPGA SUME Gen 3 x8 4x SFP+ 8 GB DDR3 1866 (2x 512M x64) \-
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250-SoC Gen 3 x16 2x QSFP28 4 GB DDR4 2400 (512M x72) \-
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250-SoC Gen 3 x16 2x QSFP28 4 GB DDR4 2666 (512M x72) \-
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XUP-P3R Gen 3 x16 4x QSFP28 4x DDR4 2400 DIMM (4x x72) \-
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DK-DEV-1SMX-H-A Gen 3 x16 2x QSFP28 8 GB DDR4 2666 (2x 512M x72) 8 GB
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DK-DEV-1SMC-H-A Gen 3 x16 2x QSFP28 8 GB DDR4 2666 (2x 512M x72) 16 GB
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@ -62,7 +62,7 @@ This section details PCIe form-factor targets, which interface with a separate h
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Alveo U250 Gen 3 x16 2x QSFP28 64 GB DDR4 2400 (4x 2G x72) \-
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Alveo U280 Gen 3 x16 2x QSFP28 32 GB DDR4 2400 (2x 2G x72) 8 GB
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VCU108 Gen 3 x8 1x QSFP28 4 GB DDR4 2400 (2x 256M x80) \-
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VCU118 Gen 3 x16 2x QSFP28 4 GB DDR4 2400 (2x 256M x80) \-
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VCU118 Gen 3 x16 2x QSFP28 4 GB DDR4 2666 (2x 256M x80) \-
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VCU1525 Gen 3 x16 2x QSFP28 64 GB DDR4 2400 (4x 2G x72) \-
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ZCU106 Gen 3 x4 2x SFP+ 2 GB DDR4 2400 (256M x64) \-
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======================= ========= ========== =============================== =====
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@ -186,7 +186,7 @@ This section details SoC targets, which interface with CPU cores on the same dev
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================= ========= ========== =============================== =====
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Board PCIe IF Network IF DDR HBM
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================= ========= ========== =============================== =====
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ZCU102 \- 4x SFP+ 2 GB DDR4 2400 (256M x64) \-
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ZCU102 \- 4x SFP+ 512 MB DDR4 2400 (256M x16) \-
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ZCU106 Gen 3 x4 2x SFP+ 2 GB DDR4 2400 (256M x64) \-
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================= ========= ========== =============================== =====
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@ -7,6 +7,7 @@ This design targets the BittWare 250-SoC FPGA board.
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* FPGA: xczu19eg-ffvd1760-2-e
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* MAC: Xilinx 100G CMAC
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* PHY: 100G CAUI-4 CMAC and internal GTY transceivers
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* RAM: 4 GB DDR4 2666 (512M x72)
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## How to build
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@ -6,8 +6,8 @@ set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
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# System clocks
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# 200 MHz (DDR 0)
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set_property -dict {LOC J19 IOSTANDARD DIFF_SSTL12} [get_ports clk_200mhz_p]
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set_property -dict {LOC J18 IOSTANDARD DIFF_SSTL12} [get_ports clk_200mhz_n]
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set_property -dict {LOC J19 IOSTANDARD DIFF_SSTL12 ODT RTT_48} [get_ports clk_200mhz_p]
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set_property -dict {LOC J18 IOSTANDARD DIFF_SSTL12 ODT RTT_48} [get_ports clk_200mhz_n]
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create_clock -period 5 -name clk_200mhz [get_ports clk_200mhz_p]
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# LEDs
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@ -183,3 +183,133 @@ create_clock -period 10 -name pcie_mgt_refclk_0 [get_ports pcie_refclk_0_p]
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set_false_path -from [get_ports {pcie_reset_n}]
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set_input_delay 0 [get_ports {pcie_reset_n}]
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# DDR4
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# 5x MT40A512M16HA-075E
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set_property -dict {LOC N16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[0]}]
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set_property -dict {LOC H17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[1]}]
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set_property -dict {LOC R18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[2]}]
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set_property -dict {LOC G18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[3]}]
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set_property -dict {LOC H16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[4]}]
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set_property -dict {LOC M19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[5]}]
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set_property -dict {LOC N19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[6]}]
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set_property -dict {LOC N20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[7]}]
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set_property -dict {LOC P19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[8]}]
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set_property -dict {LOC N17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[9]}]
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set_property -dict {LOC G16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[10]}]
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set_property -dict {LOC R20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[11]}]
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set_property -dict {LOC G19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[12]}]
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set_property -dict {LOC P20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[13]}]
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set_property -dict {LOC K18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[14]}]
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set_property -dict {LOC M16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[15]}]
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set_property -dict {LOC J17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[16]}]
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set_property -dict {LOC L20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_ba[0]}]
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set_property -dict {LOC L19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_ba[1]}]
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set_property -dict {LOC L18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_bg[0]}]
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set_property -dict {LOC K17 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_ck_t}]
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set_property -dict {LOC K16 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_ck_c}]
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set_property -dict {LOC L16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_cke}]
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set_property -dict {LOC F19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_cs_n}]
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set_property -dict {LOC F16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_act_n}]
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set_property -dict {LOC E17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_odt}]
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set_property -dict {LOC G17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_reset_n}]
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set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[0]}]
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set_property -dict {LOC H22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[1]}]
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set_property -dict {LOC J22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[2]}]
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set_property -dict {LOC J23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[3]}]
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set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[4]}]
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set_property -dict {LOC K23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[5]}]
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set_property -dict {LOC H24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[6]}]
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set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[7]}]
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set_property -dict {LOC R22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[8]}]
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set_property -dict {LOC M22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[9]}]
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set_property -dict {LOC P23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[10]}]
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set_property -dict {LOC N24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[11]}]
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set_property -dict {LOC R23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[12]}]
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set_property -dict {LOC M23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[13]}]
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set_property -dict {LOC P22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[14]}]
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set_property -dict {LOC M24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[15]}]
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set_property -dict {LOC F20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[16]}]
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set_property -dict {LOC E23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[17]}]
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set_property -dict {LOC E22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[18]}]
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set_property -dict {LOC G24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[19]}]
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set_property -dict {LOC F21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[20]}]
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set_property -dict {LOC G23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[21]}]
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set_property -dict {LOC G21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[22]}]
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set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[23]}]
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set_property -dict {LOC C16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[24]}]
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set_property -dict {LOC C19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[25]}]
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set_property -dict {LOC A16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[26]}]
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set_property -dict {LOC A18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[27]}]
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set_property -dict {LOC B16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[28]}]
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set_property -dict {LOC B19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[29]}]
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set_property -dict {LOC C17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[30]}]
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set_property -dict {LOC A19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[31]}]
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set_property -dict {LOC A21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[32]}]
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set_property -dict {LOC D20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[33]}]
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set_property -dict {LOC A20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[34]}]
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set_property -dict {LOC C21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[35]}]
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set_property -dict {LOC A23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[36]}]
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set_property -dict {LOC C22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[37]}]
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set_property -dict {LOC B22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[38]}]
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set_property -dict {LOC B23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[39]}]
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set_property -dict {LOC B24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[40]}]
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set_property -dict {LOC B28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[41]}]
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set_property -dict {LOC A24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[42]}]
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set_property -dict {LOC A26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[43]}]
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set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[44]}]
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set_property -dict {LOC C27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[45]}]
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set_property -dict {LOC A25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[46]}]
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set_property -dict {LOC B26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[47]}]
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set_property -dict {LOC D28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[48]}]
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set_property -dict {LOC G27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[49]}]
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set_property -dict {LOC E26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[50]}]
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set_property -dict {LOC F26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[51]}]
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set_property -dict {LOC D27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[52]}]
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set_property -dict {LOC F28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[53]}]
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set_property -dict {LOC E25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[54]}]
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set_property -dict {LOC F25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[55]}]
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set_property -dict {LOC J25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[56]}]
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set_property -dict {LOC K28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[57]}]
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set_property -dict {LOC H27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[58]}]
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set_property -dict {LOC K26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[59]}]
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set_property -dict {LOC H26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[60]}]
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set_property -dict {LOC K27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[61]}]
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set_property -dict {LOC G28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[62]}]
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set_property -dict {LOC K25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[63]}]
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set_property -dict {LOC M27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[64]}]
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set_property -dict {LOC R26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[65]}]
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set_property -dict {LOC M28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[66]}]
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set_property -dict {LOC P26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[67]}]
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set_property -dict {LOC N26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[68]}]
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set_property -dict {LOC P28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[69]}]
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set_property -dict {LOC N27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[70]}]
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set_property -dict {LOC P27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[71]}]
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set_property -dict {LOC K20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[0]}]
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set_property -dict {LOC J20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[0]}]
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set_property -dict {LOC N21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[1]}]
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set_property -dict {LOC N22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[1]}]
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set_property -dict {LOC F23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[2]}]
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set_property -dict {LOC F24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[2]}]
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set_property -dict {LOC B18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[3]}]
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set_property -dict {LOC B17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[3]}]
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set_property -dict {LOC C20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[4]}]
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set_property -dict {LOC B21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[4]}]
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set_property -dict {LOC B27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[5]}]
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set_property -dict {LOC A28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[5]}]
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set_property -dict {LOC E27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[6]}]
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set_property -dict {LOC E28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[6]}]
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set_property -dict {LOC J27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[7]}]
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set_property -dict {LOC J28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[7]}]
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set_property -dict {LOC P25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[8]}]
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set_property -dict {LOC N25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[8]}]
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set_property -dict {LOC M21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[0]}]
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set_property -dict {LOC R24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[1]}]
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set_property -dict {LOC H20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[2]}]
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set_property -dict {LOC D18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[3]}]
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set_property -dict {LOC D22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[4]}]
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set_property -dict {LOC C25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[5]}]
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set_property -dict {LOC H25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[6]}]
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set_property -dict {LOC L25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[7]}]
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set_property -dict {LOC R27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[8]}]
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@ -117,6 +117,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
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IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
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IP_TCL_FILES += ip/cmac_usplus_0.tcl
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IP_TCL_FILES += ip/cmac_usplus_1.tcl
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IP_TCL_FILES += ip/ddr4_0.tcl
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# Configuration
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CONFIG_TCL_FILES = ./config.tcl
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@ -136,6 +136,12 @@ dict set params MAX_TX_SIZE "9214"
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dict set params MAX_RX_SIZE "9214"
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dict set params TX_RAM_SIZE "131072"
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dict set params RX_RAM_SIZE "131072"
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# RAM configuration
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dict set params DDR_CH "1"
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dict set params DDR_ENABLE "1"
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dict set params AXI_DDR_ID_WIDTH "8"
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dict set params AXI_DDR_MAX_BURST_LEN "256"
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# Application block configuration
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dict set params APP_ID "32'h00000000"
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@ -187,6 +193,19 @@ dict set params STAT_PCIE_ENABLE "1"
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dict set params STAT_INC_WIDTH "24"
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dict set params STAT_ID_WIDTH "12"
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# DDR4 MIG settings
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if {[dict get $params DDR_ENABLE]} {
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set ddr4 [get_ips ddr4_0]
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# set AXI ID width
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set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
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# extract AXI configuration
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dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4]
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dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4]
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dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1]
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}
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# PCIe IP core settings
|
||||
set pcie [get_ips pcie4_uscale_plus_0]
|
||||
|
||||
|
||||
20
fpga/mqnic/250_SoC/fpga_100g/ip/ddr4_0.tcl
Normal file
20
fpga/mqnic/250_SoC/fpga_100g/ip/ddr4_0.tcl
Normal file
@ -0,0 +1,20 @@
|
||||
|
||||
create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0
|
||||
|
||||
set_property -dict [list \
|
||||
CONFIG.System_Clock {No_Buffer} \
|
||||
CONFIG.C0.DDR4_AxiSelection {true} \
|
||||
CONFIG.C0.DDR4_AxiDataWidth {512} \
|
||||
CONFIG.C0.DDR4_AxiIDWidth {8} \
|
||||
CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \
|
||||
CONFIG.C0.DDR4_TimePeriod {750} \
|
||||
CONFIG.C0.DDR4_InputClockPeriod {5000} \
|
||||
CONFIG.C0.DDR4_MemoryType {Components} \
|
||||
CONFIG.C0.DDR4_MemoryPart {MT40A512M16HA-075E} \
|
||||
CONFIG.C0.DDR4_DataWidth {72} \
|
||||
CONFIG.C0.DDR4_DataMask {NO_DM_NO_DBI} \
|
||||
CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \
|
||||
CONFIG.C0.DDR4_CasLatency {18} \
|
||||
CONFIG.C0.DDR4_CasWriteLatency {14} \
|
||||
CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV}
|
||||
] [get_ips ddr4_0]
|
||||
@ -109,6 +109,15 @@ module fpga #
|
||||
parameter TX_RAM_SIZE = 131072,
|
||||
parameter RX_RAM_SIZE = 131072,
|
||||
|
||||
// RAM configuration
|
||||
parameter DDR_CH = 1,
|
||||
parameter DDR_ENABLE = 1,
|
||||
parameter AXI_DDR_DATA_WIDTH = 512,
|
||||
parameter AXI_DDR_ADDR_WIDTH = 32,
|
||||
parameter AXI_DDR_ID_WIDTH = 8,
|
||||
parameter AXI_DDR_MAX_BURST_LEN = 256,
|
||||
parameter AXI_DDR_NARROW_BURST = 0,
|
||||
|
||||
// Application block configuration
|
||||
parameter APP_ID = 32'h00000000,
|
||||
parameter APP_ENABLE = 0,
|
||||
@ -255,7 +264,25 @@ module fpga #
|
||||
output wire qsfp1_resetl,
|
||||
input wire qsfp1_modprsl,
|
||||
input wire qsfp1_intl,
|
||||
output wire qsfp1_lpmode
|
||||
output wire qsfp1_lpmode,
|
||||
|
||||
/*
|
||||
* DDR4
|
||||
*/
|
||||
output wire [16:0] ddr4_adr,
|
||||
output wire [1:0] ddr4_ba,
|
||||
output wire [0:0] ddr4_bg,
|
||||
output wire [0:0] ddr4_ck_t,
|
||||
output wire [0:0] ddr4_ck_c,
|
||||
output wire [0:0] ddr4_cke,
|
||||
output wire [0:0] ddr4_cs_n,
|
||||
output wire ddr4_act_n,
|
||||
output wire [0:0] ddr4_odt,
|
||||
output wire ddr4_reset_n,
|
||||
inout wire [71:0] ddr4_dq,
|
||||
inout wire [8:0] ddr4_dqs_t,
|
||||
inout wire [8:0] ddr4_dqs_c,
|
||||
inout wire [8:0] ddr4_dm_dbi_n
|
||||
);
|
||||
|
||||
// PTP configuration
|
||||
@ -268,6 +295,9 @@ parameter PTP_SEPARATE_RX_CLOCK = 1;
|
||||
// Interface configuration
|
||||
parameter TX_TAG_WIDTH = 16;
|
||||
|
||||
// RAM configuration
|
||||
parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8);
|
||||
|
||||
// Ethernet interface configuration
|
||||
parameter AXIS_ETH_DATA_WIDTH = 512;
|
||||
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8;
|
||||
@ -1553,6 +1583,182 @@ assign led[1] = qsfp1_rx_status;
|
||||
assign led[2] = led_int[2];
|
||||
assign led[3] = led_int[3];
|
||||
|
||||
// DDR4
|
||||
wire [DDR_CH-1:0] ddr_clk;
|
||||
wire [DDR_CH-1:0] ddr_rst;
|
||||
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid;
|
||||
wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr;
|
||||
wire [DDR_CH*8-1:0] m_axi_ddr_awlen;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_awsize;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_awburst;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_awlock;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_awcache;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_awprot;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_awqos;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_awvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_awready;
|
||||
wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata;
|
||||
wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_wlast;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_wvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_wready;
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_bresp;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_bvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_bready;
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid;
|
||||
wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr;
|
||||
wire [DDR_CH*8-1:0] m_axi_ddr_arlen;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_arsize;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_arburst;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_arlock;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_arcache;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_arprot;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_arqos;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_arvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_arready;
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid;
|
||||
wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_rresp;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_rlast;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_rvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_rready;
|
||||
|
||||
wire [DDR_CH-1:0] ddr_status;
|
||||
|
||||
generate
|
||||
|
||||
if (DDR_ENABLE && DDR_CH > 0) begin
|
||||
|
||||
ddr4_0 ddr4_inst (
|
||||
.c0_sys_clk_i(clk_200mhz_ibufg),
|
||||
.sys_rst(pcie_user_reset),
|
||||
|
||||
.c0_init_calib_complete(ddr_status[0 +: 1]),
|
||||
.c0_ddr4_interrupt(),
|
||||
.dbg_clk(),
|
||||
.dbg_bus(),
|
||||
|
||||
.c0_ddr4_adr(ddr4_adr),
|
||||
.c0_ddr4_ba(ddr4_ba),
|
||||
.c0_ddr4_cke(ddr4_cke),
|
||||
.c0_ddr4_cs_n(ddr4_cs_n),
|
||||
.c0_ddr4_dq(ddr4_dq),
|
||||
.c0_ddr4_dqs_t(ddr4_dqs_t),
|
||||
.c0_ddr4_dqs_c(ddr4_dqs_c),
|
||||
.c0_ddr4_dm_dbi_n(ddr4_dm_dbi_n),
|
||||
.c0_ddr4_odt(ddr4_odt),
|
||||
.c0_ddr4_bg(ddr4_bg),
|
||||
.c0_ddr4_reset_n(ddr4_reset_n),
|
||||
.c0_ddr4_act_n(ddr4_act_n),
|
||||
.c0_ddr4_ck_t(ddr4_ck_t),
|
||||
.c0_ddr4_ck_c(ddr4_ck_c),
|
||||
|
||||
.c0_ddr4_ui_clk(ddr_clk[0 +: 1]),
|
||||
.c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]),
|
||||
|
||||
.c0_ddr4_aresetn(!ddr_rst[0 +: 1]),
|
||||
|
||||
.c0_ddr4_s_axi_ctrl_awvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_awready(),
|
||||
.c0_ddr4_s_axi_ctrl_awaddr(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_wvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_wready(),
|
||||
.c0_ddr4_s_axi_ctrl_wdata(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_bvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_bready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_bresp(),
|
||||
.c0_ddr4_s_axi_ctrl_arvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_arready(),
|
||||
.c0_ddr4_s_axi_ctrl_araddr(31'd0),
|
||||
.c0_ddr4_s_axi_ctrl_rvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_rready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_rdata(),
|
||||
.c0_ddr4_s_axi_ctrl_rresp(),
|
||||
|
||||
.c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]),
|
||||
.c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]),
|
||||
.c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]),
|
||||
.c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]),
|
||||
.c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]),
|
||||
.c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]),
|
||||
.c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]),
|
||||
.c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH])
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign ddr4_adr = {17{1'bz}};
|
||||
assign ddr4_ba = {2{1'bz}};
|
||||
assign ddr4_bg = {1{1'bz}};
|
||||
assign ddr4_cke = 1'bz;
|
||||
assign ddr4_cs_n = 1'bz;
|
||||
assign ddr4_act_n = 1'bz;
|
||||
assign ddr4_odt = 1'bz;
|
||||
assign ddr4_reset_n = 1'b0;
|
||||
assign ddr4_dq = {72{1'bz}};
|
||||
assign ddr4_dqs_t = {9{1'bz}};
|
||||
assign ddr4_dqs_c = {9{1'bz}};
|
||||
assign ddr4_dm_dbi_n = {9{1'bz}};
|
||||
|
||||
OBUFTDS ddr4_ck_obuftds_inst (
|
||||
.I(1'b0),
|
||||
.T(1'b1),
|
||||
.O(ddr4_ck_t),
|
||||
.OB(ddr4_ck_c)
|
||||
);
|
||||
|
||||
assign ddr_clk = 0;
|
||||
assign ddr_rst = 0;
|
||||
|
||||
assign m_axi_ddr_awready = 0;
|
||||
assign m_axi_ddr_wready = 0;
|
||||
assign m_axi_ddr_bid = 0;
|
||||
assign m_axi_ddr_bresp = 0;
|
||||
assign m_axi_ddr_bvalid = 0;
|
||||
assign m_axi_ddr_arready = 0;
|
||||
assign m_axi_ddr_rid = 0;
|
||||
assign m_axi_ddr_rdata = 0;
|
||||
assign m_axi_ddr_rresp = 0;
|
||||
assign m_axi_ddr_rlast = 0;
|
||||
assign m_axi_ddr_rvalid = 0;
|
||||
|
||||
assign ddr_status = 0;
|
||||
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
fpga_core #(
|
||||
// FW and board IDs
|
||||
.FPGA_ID(FPGA_ID),
|
||||
@ -1627,6 +1833,16 @@ fpga_core #(
|
||||
.TX_RAM_SIZE(TX_RAM_SIZE),
|
||||
.RX_RAM_SIZE(RX_RAM_SIZE),
|
||||
|
||||
// RAM configuration
|
||||
.DDR_CH(DDR_CH),
|
||||
.DDR_ENABLE(DDR_ENABLE),
|
||||
.AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH),
|
||||
.AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH),
|
||||
.AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH),
|
||||
.AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH),
|
||||
.AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN),
|
||||
.AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST),
|
||||
|
||||
// Application block configuration
|
||||
.APP_ID(APP_ID),
|
||||
.APP_ENABLE(APP_ENABLE),
|
||||
@ -1871,7 +2087,53 @@ core_inst (
|
||||
.qsfp1_modprsl(qsfp1_modprsl_int),
|
||||
.qsfp1_resetl(qsfp1_resetl),
|
||||
.qsfp1_intl(qsfp1_intl_int),
|
||||
.qsfp1_lpmode(qsfp1_lpmode)
|
||||
.qsfp1_lpmode(qsfp1_lpmode),
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
.ddr_clk(ddr_clk),
|
||||
.ddr_rst(ddr_rst),
|
||||
|
||||
.m_axi_ddr_awid(m_axi_ddr_awid),
|
||||
.m_axi_ddr_awaddr(m_axi_ddr_awaddr),
|
||||
.m_axi_ddr_awlen(m_axi_ddr_awlen),
|
||||
.m_axi_ddr_awsize(m_axi_ddr_awsize),
|
||||
.m_axi_ddr_awburst(m_axi_ddr_awburst),
|
||||
.m_axi_ddr_awlock(m_axi_ddr_awlock),
|
||||
.m_axi_ddr_awcache(m_axi_ddr_awcache),
|
||||
.m_axi_ddr_awprot(m_axi_ddr_awprot),
|
||||
.m_axi_ddr_awqos(m_axi_ddr_awqos),
|
||||
.m_axi_ddr_awvalid(m_axi_ddr_awvalid),
|
||||
.m_axi_ddr_awready(m_axi_ddr_awready),
|
||||
.m_axi_ddr_wdata(m_axi_ddr_wdata),
|
||||
.m_axi_ddr_wstrb(m_axi_ddr_wstrb),
|
||||
.m_axi_ddr_wlast(m_axi_ddr_wlast),
|
||||
.m_axi_ddr_wvalid(m_axi_ddr_wvalid),
|
||||
.m_axi_ddr_wready(m_axi_ddr_wready),
|
||||
.m_axi_ddr_bid(m_axi_ddr_bid),
|
||||
.m_axi_ddr_bresp(m_axi_ddr_bresp),
|
||||
.m_axi_ddr_bvalid(m_axi_ddr_bvalid),
|
||||
.m_axi_ddr_bready(m_axi_ddr_bready),
|
||||
.m_axi_ddr_arid(m_axi_ddr_arid),
|
||||
.m_axi_ddr_araddr(m_axi_ddr_araddr),
|
||||
.m_axi_ddr_arlen(m_axi_ddr_arlen),
|
||||
.m_axi_ddr_arsize(m_axi_ddr_arsize),
|
||||
.m_axi_ddr_arburst(m_axi_ddr_arburst),
|
||||
.m_axi_ddr_arlock(m_axi_ddr_arlock),
|
||||
.m_axi_ddr_arcache(m_axi_ddr_arcache),
|
||||
.m_axi_ddr_arprot(m_axi_ddr_arprot),
|
||||
.m_axi_ddr_arqos(m_axi_ddr_arqos),
|
||||
.m_axi_ddr_arvalid(m_axi_ddr_arvalid),
|
||||
.m_axi_ddr_arready(m_axi_ddr_arready),
|
||||
.m_axi_ddr_rid(m_axi_ddr_rid),
|
||||
.m_axi_ddr_rdata(m_axi_ddr_rdata),
|
||||
.m_axi_ddr_rresp(m_axi_ddr_rresp),
|
||||
.m_axi_ddr_rlast(m_axi_ddr_rlast),
|
||||
.m_axi_ddr_rvalid(m_axi_ddr_rvalid),
|
||||
.m_axi_ddr_rready(m_axi_ddr_rready),
|
||||
|
||||
.ddr_status(ddr_status)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
@ -115,6 +115,16 @@ module fpga_core #
|
||||
parameter TX_RAM_SIZE = 131072,
|
||||
parameter RX_RAM_SIZE = 131072,
|
||||
|
||||
// RAM configuration
|
||||
parameter DDR_CH = 1,
|
||||
parameter DDR_ENABLE = 1,
|
||||
parameter AXI_DDR_DATA_WIDTH = 512,
|
||||
parameter AXI_DDR_ADDR_WIDTH = 32,
|
||||
parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8),
|
||||
parameter AXI_DDR_ID_WIDTH = 8,
|
||||
parameter AXI_DDR_MAX_BURST_LEN = 256,
|
||||
parameter AXI_DDR_NARROW_BURST = 0,
|
||||
|
||||
// Application block configuration
|
||||
parameter APP_ID = 32'h00000000,
|
||||
parameter APP_ENABLE = 0,
|
||||
@ -373,7 +383,53 @@ module fpga_core #
|
||||
output wire qsfp1_resetl,
|
||||
input wire qsfp1_modprsl,
|
||||
input wire qsfp1_intl,
|
||||
output wire qsfp1_lpmode
|
||||
output wire qsfp1_lpmode,
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
input wire [DDR_CH-1:0] ddr_clk,
|
||||
input wire [DDR_CH-1:0] ddr_rst,
|
||||
|
||||
output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid,
|
||||
output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr,
|
||||
output wire [DDR_CH*8-1:0] m_axi_ddr_awlen,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_awsize,
|
||||
output wire [DDR_CH*2-1:0] m_axi_ddr_awburst,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_awlock,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_awcache,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_awprot,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_awqos,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_awvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_awready,
|
||||
output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata,
|
||||
output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_wlast,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_wvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_wready,
|
||||
input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid,
|
||||
input wire [DDR_CH*2-1:0] m_axi_ddr_bresp,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_bvalid,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_bready,
|
||||
output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid,
|
||||
output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr,
|
||||
output wire [DDR_CH*8-1:0] m_axi_ddr_arlen,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_arsize,
|
||||
output wire [DDR_CH*2-1:0] m_axi_ddr_arburst,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_arlock,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_arcache,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_arprot,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_arqos,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_arvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_arready,
|
||||
input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid,
|
||||
input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata,
|
||||
input wire [DDR_CH*2-1:0] m_axi_ddr_rresp,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_rlast,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_rvalid,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_rready,
|
||||
|
||||
input wire [DDR_CH-1:0] ddr_status
|
||||
);
|
||||
|
||||
parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF;
|
||||
@ -826,6 +882,25 @@ mqnic_core_pcie_us #(
|
||||
.TX_RAM_SIZE(TX_RAM_SIZE),
|
||||
.RX_RAM_SIZE(RX_RAM_SIZE),
|
||||
|
||||
// RAM configuration
|
||||
.DDR_CH(DDR_CH),
|
||||
.DDR_ENABLE(DDR_ENABLE),
|
||||
.DDR_GROUP_SIZE(1),
|
||||
.AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH),
|
||||
.AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH),
|
||||
.AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH),
|
||||
.AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH),
|
||||
.AXI_DDR_AWUSER_ENABLE(0),
|
||||
.AXI_DDR_WUSER_ENABLE(0),
|
||||
.AXI_DDR_BUSER_ENABLE(0),
|
||||
.AXI_DDR_ARUSER_ENABLE(0),
|
||||
.AXI_DDR_RUSER_ENABLE(0),
|
||||
.AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN),
|
||||
.AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST),
|
||||
.AXI_DDR_FIXED_BURST(0),
|
||||
.AXI_DDR_WRAP_BURST(1),
|
||||
.HBM_ENABLE(0),
|
||||
|
||||
// Application block configuration
|
||||
.APP_ID(APP_ID),
|
||||
.APP_ENABLE(APP_ENABLE),
|
||||
@ -1103,6 +1178,108 @@ core_inst (
|
||||
|
||||
.eth_rx_status(eth_rx_status),
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
.ddr_clk(ddr_clk),
|
||||
.ddr_rst(ddr_rst),
|
||||
|
||||
.m_axi_ddr_awid(m_axi_ddr_awid),
|
||||
.m_axi_ddr_awaddr(m_axi_ddr_awaddr),
|
||||
.m_axi_ddr_awlen(m_axi_ddr_awlen),
|
||||
.m_axi_ddr_awsize(m_axi_ddr_awsize),
|
||||
.m_axi_ddr_awburst(m_axi_ddr_awburst),
|
||||
.m_axi_ddr_awlock(m_axi_ddr_awlock),
|
||||
.m_axi_ddr_awcache(m_axi_ddr_awcache),
|
||||
.m_axi_ddr_awprot(m_axi_ddr_awprot),
|
||||
.m_axi_ddr_awqos(m_axi_ddr_awqos),
|
||||
.m_axi_ddr_awuser(),
|
||||
.m_axi_ddr_awvalid(m_axi_ddr_awvalid),
|
||||
.m_axi_ddr_awready(m_axi_ddr_awready),
|
||||
.m_axi_ddr_wdata(m_axi_ddr_wdata),
|
||||
.m_axi_ddr_wstrb(m_axi_ddr_wstrb),
|
||||
.m_axi_ddr_wlast(m_axi_ddr_wlast),
|
||||
.m_axi_ddr_wuser(),
|
||||
.m_axi_ddr_wvalid(m_axi_ddr_wvalid),
|
||||
.m_axi_ddr_wready(m_axi_ddr_wready),
|
||||
.m_axi_ddr_bid(m_axi_ddr_bid),
|
||||
.m_axi_ddr_bresp(m_axi_ddr_bresp),
|
||||
.m_axi_ddr_buser(0),
|
||||
.m_axi_ddr_bvalid(m_axi_ddr_bvalid),
|
||||
.m_axi_ddr_bready(m_axi_ddr_bready),
|
||||
.m_axi_ddr_arid(m_axi_ddr_arid),
|
||||
.m_axi_ddr_araddr(m_axi_ddr_araddr),
|
||||
.m_axi_ddr_arlen(m_axi_ddr_arlen),
|
||||
.m_axi_ddr_arsize(m_axi_ddr_arsize),
|
||||
.m_axi_ddr_arburst(m_axi_ddr_arburst),
|
||||
.m_axi_ddr_arlock(m_axi_ddr_arlock),
|
||||
.m_axi_ddr_arcache(m_axi_ddr_arcache),
|
||||
.m_axi_ddr_arprot(m_axi_ddr_arprot),
|
||||
.m_axi_ddr_arqos(m_axi_ddr_arqos),
|
||||
.m_axi_ddr_aruser(),
|
||||
.m_axi_ddr_arvalid(m_axi_ddr_arvalid),
|
||||
.m_axi_ddr_arready(m_axi_ddr_arready),
|
||||
.m_axi_ddr_rid(m_axi_ddr_rid),
|
||||
.m_axi_ddr_rdata(m_axi_ddr_rdata),
|
||||
.m_axi_ddr_rresp(m_axi_ddr_rresp),
|
||||
.m_axi_ddr_rlast(m_axi_ddr_rlast),
|
||||
.m_axi_ddr_ruser(0),
|
||||
.m_axi_ddr_rvalid(m_axi_ddr_rvalid),
|
||||
.m_axi_ddr_rready(m_axi_ddr_rready),
|
||||
|
||||
.ddr_status(ddr_status),
|
||||
|
||||
/*
|
||||
* HBM
|
||||
*/
|
||||
.hbm_clk(0),
|
||||
.hbm_rst(0),
|
||||
|
||||
.m_axi_hbm_awid(),
|
||||
.m_axi_hbm_awaddr(),
|
||||
.m_axi_hbm_awlen(),
|
||||
.m_axi_hbm_awsize(),
|
||||
.m_axi_hbm_awburst(),
|
||||
.m_axi_hbm_awlock(),
|
||||
.m_axi_hbm_awcache(),
|
||||
.m_axi_hbm_awprot(),
|
||||
.m_axi_hbm_awqos(),
|
||||
.m_axi_hbm_awuser(),
|
||||
.m_axi_hbm_awvalid(),
|
||||
.m_axi_hbm_awready(0),
|
||||
.m_axi_hbm_wdata(),
|
||||
.m_axi_hbm_wstrb(),
|
||||
.m_axi_hbm_wlast(),
|
||||
.m_axi_hbm_wuser(),
|
||||
.m_axi_hbm_wvalid(),
|
||||
.m_axi_hbm_wready(0),
|
||||
.m_axi_hbm_bid(0),
|
||||
.m_axi_hbm_bresp(0),
|
||||
.m_axi_hbm_buser(0),
|
||||
.m_axi_hbm_bvalid(0),
|
||||
.m_axi_hbm_bready(),
|
||||
.m_axi_hbm_arid(),
|
||||
.m_axi_hbm_araddr(),
|
||||
.m_axi_hbm_arlen(),
|
||||
.m_axi_hbm_arsize(),
|
||||
.m_axi_hbm_arburst(),
|
||||
.m_axi_hbm_arlock(),
|
||||
.m_axi_hbm_arcache(),
|
||||
.m_axi_hbm_arprot(),
|
||||
.m_axi_hbm_arqos(),
|
||||
.m_axi_hbm_aruser(),
|
||||
.m_axi_hbm_arvalid(),
|
||||
.m_axi_hbm_arready(0),
|
||||
.m_axi_hbm_rid(0),
|
||||
.m_axi_hbm_rdata(0),
|
||||
.m_axi_hbm_rresp(0),
|
||||
.m_axi_hbm_rlast(0),
|
||||
.m_axi_hbm_ruser(0),
|
||||
.m_axi_hbm_rvalid(0),
|
||||
.m_axi_hbm_rready(),
|
||||
|
||||
.hbm_status(0),
|
||||
|
||||
/*
|
||||
* Statistics input
|
||||
*/
|
||||
|
||||
@ -6,6 +6,7 @@ This design targets the BittWare 250-SoC FPGA board.
|
||||
|
||||
* FPGA: xczu19eg-ffvd1760-2-e
|
||||
* PHY: 10G BASE-R PHY IP core and internal GTY transceiver
|
||||
* RAM: 4 GB DDR4 2666 (512M x72)
|
||||
|
||||
## How to build
|
||||
|
||||
|
||||
@ -6,8 +6,8 @@ set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
|
||||
|
||||
# System clocks
|
||||
# 200 MHz (DDR 0)
|
||||
set_property -dict {LOC J19 IOSTANDARD DIFF_SSTL12} [get_ports clk_200mhz_p]
|
||||
set_property -dict {LOC J18 IOSTANDARD DIFF_SSTL12} [get_ports clk_200mhz_n]
|
||||
set_property -dict {LOC J19 IOSTANDARD DIFF_SSTL12 ODT RTT_48} [get_ports clk_200mhz_p]
|
||||
set_property -dict {LOC J18 IOSTANDARD DIFF_SSTL12 ODT RTT_48} [get_ports clk_200mhz_n]
|
||||
create_clock -period 5 -name clk_200mhz [get_ports clk_200mhz_p]
|
||||
|
||||
# LEDs
|
||||
@ -183,3 +183,133 @@ create_clock -period 10 -name pcie_mgt_refclk_0 [get_ports pcie_refclk_0_p]
|
||||
|
||||
set_false_path -from [get_ports {pcie_reset_n}]
|
||||
set_input_delay 0 [get_ports {pcie_reset_n}]
|
||||
|
||||
# DDR4
|
||||
# 5x MT40A512M16HA-075E
|
||||
set_property -dict {LOC N16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[0]}]
|
||||
set_property -dict {LOC H17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[1]}]
|
||||
set_property -dict {LOC R18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[2]}]
|
||||
set_property -dict {LOC G18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[3]}]
|
||||
set_property -dict {LOC H16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[4]}]
|
||||
set_property -dict {LOC M19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[5]}]
|
||||
set_property -dict {LOC N19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[6]}]
|
||||
set_property -dict {LOC N20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[7]}]
|
||||
set_property -dict {LOC P19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[8]}]
|
||||
set_property -dict {LOC N17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[9]}]
|
||||
set_property -dict {LOC G16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[10]}]
|
||||
set_property -dict {LOC R20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[11]}]
|
||||
set_property -dict {LOC G19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[12]}]
|
||||
set_property -dict {LOC P20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[13]}]
|
||||
set_property -dict {LOC K18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[14]}]
|
||||
set_property -dict {LOC M16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[15]}]
|
||||
set_property -dict {LOC J17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[16]}]
|
||||
set_property -dict {LOC L20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_ba[0]}]
|
||||
set_property -dict {LOC L19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_ba[1]}]
|
||||
set_property -dict {LOC L18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_bg[0]}]
|
||||
set_property -dict {LOC K17 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_ck_t}]
|
||||
set_property -dict {LOC K16 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_ck_c}]
|
||||
set_property -dict {LOC L16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_cke}]
|
||||
set_property -dict {LOC F19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_cs_n}]
|
||||
set_property -dict {LOC F16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_act_n}]
|
||||
set_property -dict {LOC E17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_odt}]
|
||||
set_property -dict {LOC G17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_reset_n}]
|
||||
|
||||
set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[0]}]
|
||||
set_property -dict {LOC H22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[1]}]
|
||||
set_property -dict {LOC J22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[2]}]
|
||||
set_property -dict {LOC J23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[3]}]
|
||||
set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[4]}]
|
||||
set_property -dict {LOC K23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[5]}]
|
||||
set_property -dict {LOC H24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[6]}]
|
||||
set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[7]}]
|
||||
set_property -dict {LOC R22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[8]}]
|
||||
set_property -dict {LOC M22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[9]}]
|
||||
set_property -dict {LOC P23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[10]}]
|
||||
set_property -dict {LOC N24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[11]}]
|
||||
set_property -dict {LOC R23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[12]}]
|
||||
set_property -dict {LOC M23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[13]}]
|
||||
set_property -dict {LOC P22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[14]}]
|
||||
set_property -dict {LOC M24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[15]}]
|
||||
set_property -dict {LOC F20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[16]}]
|
||||
set_property -dict {LOC E23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[17]}]
|
||||
set_property -dict {LOC E22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[18]}]
|
||||
set_property -dict {LOC G24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[19]}]
|
||||
set_property -dict {LOC F21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[20]}]
|
||||
set_property -dict {LOC G23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[21]}]
|
||||
set_property -dict {LOC G21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[22]}]
|
||||
set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[23]}]
|
||||
set_property -dict {LOC C16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[24]}]
|
||||
set_property -dict {LOC C19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[25]}]
|
||||
set_property -dict {LOC A16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[26]}]
|
||||
set_property -dict {LOC A18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[27]}]
|
||||
set_property -dict {LOC B16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[28]}]
|
||||
set_property -dict {LOC B19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[29]}]
|
||||
set_property -dict {LOC C17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[30]}]
|
||||
set_property -dict {LOC A19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[31]}]
|
||||
set_property -dict {LOC A21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[32]}]
|
||||
set_property -dict {LOC D20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[33]}]
|
||||
set_property -dict {LOC A20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[34]}]
|
||||
set_property -dict {LOC C21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[35]}]
|
||||
set_property -dict {LOC A23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[36]}]
|
||||
set_property -dict {LOC C22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[37]}]
|
||||
set_property -dict {LOC B22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[38]}]
|
||||
set_property -dict {LOC B23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[39]}]
|
||||
set_property -dict {LOC B24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[40]}]
|
||||
set_property -dict {LOC B28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[41]}]
|
||||
set_property -dict {LOC A24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[42]}]
|
||||
set_property -dict {LOC A26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[43]}]
|
||||
set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[44]}]
|
||||
set_property -dict {LOC C27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[45]}]
|
||||
set_property -dict {LOC A25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[46]}]
|
||||
set_property -dict {LOC B26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[47]}]
|
||||
set_property -dict {LOC D28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[48]}]
|
||||
set_property -dict {LOC G27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[49]}]
|
||||
set_property -dict {LOC E26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[50]}]
|
||||
set_property -dict {LOC F26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[51]}]
|
||||
set_property -dict {LOC D27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[52]}]
|
||||
set_property -dict {LOC F28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[53]}]
|
||||
set_property -dict {LOC E25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[54]}]
|
||||
set_property -dict {LOC F25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[55]}]
|
||||
set_property -dict {LOC J25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[56]}]
|
||||
set_property -dict {LOC K28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[57]}]
|
||||
set_property -dict {LOC H27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[58]}]
|
||||
set_property -dict {LOC K26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[59]}]
|
||||
set_property -dict {LOC H26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[60]}]
|
||||
set_property -dict {LOC K27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[61]}]
|
||||
set_property -dict {LOC G28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[62]}]
|
||||
set_property -dict {LOC K25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[63]}]
|
||||
set_property -dict {LOC M27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[64]}]
|
||||
set_property -dict {LOC R26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[65]}]
|
||||
set_property -dict {LOC M28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[66]}]
|
||||
set_property -dict {LOC P26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[67]}]
|
||||
set_property -dict {LOC N26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[68]}]
|
||||
set_property -dict {LOC P28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[69]}]
|
||||
set_property -dict {LOC N27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[70]}]
|
||||
set_property -dict {LOC P27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[71]}]
|
||||
set_property -dict {LOC K20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[0]}]
|
||||
set_property -dict {LOC J20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[0]}]
|
||||
set_property -dict {LOC N21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[1]}]
|
||||
set_property -dict {LOC N22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[1]}]
|
||||
set_property -dict {LOC F23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[2]}]
|
||||
set_property -dict {LOC F24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[2]}]
|
||||
set_property -dict {LOC B18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[3]}]
|
||||
set_property -dict {LOC B17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[3]}]
|
||||
set_property -dict {LOC C20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[4]}]
|
||||
set_property -dict {LOC B21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[4]}]
|
||||
set_property -dict {LOC B27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[5]}]
|
||||
set_property -dict {LOC A28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[5]}]
|
||||
set_property -dict {LOC E27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[6]}]
|
||||
set_property -dict {LOC E28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[6]}]
|
||||
set_property -dict {LOC J27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[7]}]
|
||||
set_property -dict {LOC J28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[7]}]
|
||||
set_property -dict {LOC P25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[8]}]
|
||||
set_property -dict {LOC N25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[8]}]
|
||||
set_property -dict {LOC M21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[0]}]
|
||||
set_property -dict {LOC R24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[1]}]
|
||||
set_property -dict {LOC H20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[2]}]
|
||||
set_property -dict {LOC D18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[3]}]
|
||||
set_property -dict {LOC D22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[4]}]
|
||||
set_property -dict {LOC C25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[5]}]
|
||||
set_property -dict {LOC H25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[6]}]
|
||||
set_property -dict {LOC L25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[7]}]
|
||||
set_property -dict {LOC R27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[8]}]
|
||||
|
||||
@ -137,6 +137,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
|
||||
# IP
|
||||
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
|
||||
IP_TCL_FILES += ip/eth_xcvr_gty.tcl
|
||||
IP_TCL_FILES += ip/ddr4_0.tcl
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
@ -148,6 +148,12 @@ dict set params MAX_TX_SIZE "9214"
|
||||
dict set params MAX_RX_SIZE "9214"
|
||||
dict set params TX_RAM_SIZE "32768"
|
||||
dict set params RX_RAM_SIZE "131072"
|
||||
|
||||
# RAM configuration
|
||||
dict set params DDR_CH "1"
|
||||
dict set params DDR_ENABLE "1"
|
||||
dict set params AXI_DDR_ID_WIDTH "8"
|
||||
dict set params AXI_DDR_MAX_BURST_LEN "256"
|
||||
|
||||
# Application block configuration
|
||||
dict set params APP_ID "32'h00000000"
|
||||
@ -200,6 +206,19 @@ dict set params STAT_PCIE_ENABLE "1"
|
||||
dict set params STAT_INC_WIDTH "24"
|
||||
dict set params STAT_ID_WIDTH "12"
|
||||
|
||||
# DDR4 MIG settings
|
||||
if {[dict get $params DDR_ENABLE]} {
|
||||
set ddr4 [get_ips ddr4_0]
|
||||
|
||||
# set AXI ID width
|
||||
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
|
||||
|
||||
# extract AXI configuration
|
||||
dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4]
|
||||
dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4]
|
||||
dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1]
|
||||
}
|
||||
|
||||
# PCIe IP core settings
|
||||
set pcie [get_ips pcie4_uscale_plus_0]
|
||||
|
||||
|
||||
@ -137,6 +137,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
|
||||
# IP
|
||||
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
|
||||
IP_TCL_FILES += ip/eth_xcvr_gty.tcl
|
||||
IP_TCL_FILES += ip/ddr4_0.tcl
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
@ -148,6 +148,12 @@ dict set params MAX_TX_SIZE "9214"
|
||||
dict set params MAX_RX_SIZE "9214"
|
||||
dict set params TX_RAM_SIZE "32768"
|
||||
dict set params RX_RAM_SIZE "32768"
|
||||
|
||||
# RAM configuration
|
||||
dict set params DDR_CH "1"
|
||||
dict set params DDR_ENABLE "1"
|
||||
dict set params AXI_DDR_ID_WIDTH "8"
|
||||
dict set params AXI_DDR_MAX_BURST_LEN "256"
|
||||
|
||||
# Application block configuration
|
||||
dict set params APP_ID "32'h00000000"
|
||||
@ -200,6 +206,19 @@ dict set params STAT_PCIE_ENABLE "1"
|
||||
dict set params STAT_INC_WIDTH "24"
|
||||
dict set params STAT_ID_WIDTH "12"
|
||||
|
||||
# DDR4 MIG settings
|
||||
if {[dict get $params DDR_ENABLE]} {
|
||||
set ddr4 [get_ips ddr4_0]
|
||||
|
||||
# set AXI ID width
|
||||
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
|
||||
|
||||
# extract AXI configuration
|
||||
dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4]
|
||||
dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4]
|
||||
dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1]
|
||||
}
|
||||
|
||||
# PCIe IP core settings
|
||||
set pcie [get_ips pcie4_uscale_plus_0]
|
||||
|
||||
|
||||
20
fpga/mqnic/250_SoC/fpga_25g/ip/ddr4_0.tcl
Normal file
20
fpga/mqnic/250_SoC/fpga_25g/ip/ddr4_0.tcl
Normal file
@ -0,0 +1,20 @@
|
||||
|
||||
create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0
|
||||
|
||||
set_property -dict [list \
|
||||
CONFIG.System_Clock {No_Buffer} \
|
||||
CONFIG.C0.DDR4_AxiSelection {true} \
|
||||
CONFIG.C0.DDR4_AxiDataWidth {512} \
|
||||
CONFIG.C0.DDR4_AxiIDWidth {8} \
|
||||
CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \
|
||||
CONFIG.C0.DDR4_TimePeriod {750} \
|
||||
CONFIG.C0.DDR4_InputClockPeriod {5000} \
|
||||
CONFIG.C0.DDR4_MemoryType {Components} \
|
||||
CONFIG.C0.DDR4_MemoryPart {MT40A512M16HA-075E} \
|
||||
CONFIG.C0.DDR4_DataWidth {72} \
|
||||
CONFIG.C0.DDR4_DataMask {NO_DM_NO_DBI} \
|
||||
CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \
|
||||
CONFIG.C0.DDR4_CasLatency {18} \
|
||||
CONFIG.C0.DDR4_CasWriteLatency {14} \
|
||||
CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV}
|
||||
] [get_ips ddr4_0]
|
||||
@ -112,6 +112,15 @@ module fpga #
|
||||
parameter TX_RAM_SIZE = 32768,
|
||||
parameter RX_RAM_SIZE = 32768,
|
||||
|
||||
// RAM configuration
|
||||
parameter DDR_CH = 1,
|
||||
parameter DDR_ENABLE = 1,
|
||||
parameter AXI_DDR_DATA_WIDTH = 512,
|
||||
parameter AXI_DDR_ADDR_WIDTH = 32,
|
||||
parameter AXI_DDR_ID_WIDTH = 8,
|
||||
parameter AXI_DDR_MAX_BURST_LEN = 256,
|
||||
parameter AXI_DDR_NARROW_BURST = 0,
|
||||
|
||||
// Application block configuration
|
||||
parameter APP_ID = 32'h00000000,
|
||||
parameter APP_ENABLE = 0,
|
||||
@ -259,7 +268,25 @@ module fpga #
|
||||
output wire qsfp1_resetl,
|
||||
input wire qsfp1_modprsl,
|
||||
input wire qsfp1_intl,
|
||||
output wire qsfp1_lpmode
|
||||
output wire qsfp1_lpmode,
|
||||
|
||||
/*
|
||||
* DDR4
|
||||
*/
|
||||
output wire [16:0] ddr4_adr,
|
||||
output wire [1:0] ddr4_ba,
|
||||
output wire [0:0] ddr4_bg,
|
||||
output wire [0:0] ddr4_ck_t,
|
||||
output wire [0:0] ddr4_ck_c,
|
||||
output wire [0:0] ddr4_cke,
|
||||
output wire [0:0] ddr4_cs_n,
|
||||
output wire ddr4_act_n,
|
||||
output wire [0:0] ddr4_odt,
|
||||
output wire ddr4_reset_n,
|
||||
inout wire [71:0] ddr4_dq,
|
||||
inout wire [8:0] ddr4_dqs_t,
|
||||
inout wire [8:0] ddr4_dqs_c,
|
||||
inout wire [8:0] ddr4_dm_dbi_n
|
||||
);
|
||||
|
||||
// PTP configuration
|
||||
@ -273,6 +300,9 @@ parameter IF_PTP_PERIOD_FNS = 16'h6666;
|
||||
// Interface configuration
|
||||
parameter TX_TAG_WIDTH = 16;
|
||||
|
||||
// RAM configuration
|
||||
parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8);
|
||||
|
||||
// Ethernet interface configuration
|
||||
parameter XGMII_DATA_WIDTH = 64;
|
||||
parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8;
|
||||
@ -1150,6 +1180,182 @@ assign ptp_clk = qsfp0_mgt_refclk_bufg;
|
||||
assign ptp_rst = qsfp0_rst;
|
||||
assign ptp_sample_clk = clk_125mhz_int;
|
||||
|
||||
// DDR4
|
||||
wire [DDR_CH-1:0] ddr_clk;
|
||||
wire [DDR_CH-1:0] ddr_rst;
|
||||
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid;
|
||||
wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr;
|
||||
wire [DDR_CH*8-1:0] m_axi_ddr_awlen;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_awsize;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_awburst;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_awlock;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_awcache;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_awprot;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_awqos;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_awvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_awready;
|
||||
wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata;
|
||||
wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_wlast;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_wvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_wready;
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_bresp;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_bvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_bready;
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid;
|
||||
wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr;
|
||||
wire [DDR_CH*8-1:0] m_axi_ddr_arlen;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_arsize;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_arburst;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_arlock;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_arcache;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_arprot;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_arqos;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_arvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_arready;
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid;
|
||||
wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_rresp;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_rlast;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_rvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_rready;
|
||||
|
||||
wire [DDR_CH-1:0] ddr_status;
|
||||
|
||||
generate
|
||||
|
||||
if (DDR_ENABLE && DDR_CH > 0) begin
|
||||
|
||||
ddr4_0 ddr4_inst (
|
||||
.c0_sys_clk_i(clk_200mhz_ibufg),
|
||||
.sys_rst(pcie_user_reset),
|
||||
|
||||
.c0_init_calib_complete(ddr_status[0 +: 1]),
|
||||
.c0_ddr4_interrupt(),
|
||||
.dbg_clk(),
|
||||
.dbg_bus(),
|
||||
|
||||
.c0_ddr4_adr(ddr4_adr),
|
||||
.c0_ddr4_ba(ddr4_ba),
|
||||
.c0_ddr4_cke(ddr4_cke),
|
||||
.c0_ddr4_cs_n(ddr4_cs_n),
|
||||
.c0_ddr4_dq(ddr4_dq),
|
||||
.c0_ddr4_dqs_t(ddr4_dqs_t),
|
||||
.c0_ddr4_dqs_c(ddr4_dqs_c),
|
||||
.c0_ddr4_dm_dbi_n(ddr4_dm_dbi_n),
|
||||
.c0_ddr4_odt(ddr4_odt),
|
||||
.c0_ddr4_bg(ddr4_bg),
|
||||
.c0_ddr4_reset_n(ddr4_reset_n),
|
||||
.c0_ddr4_act_n(ddr4_act_n),
|
||||
.c0_ddr4_ck_t(ddr4_ck_t),
|
||||
.c0_ddr4_ck_c(ddr4_ck_c),
|
||||
|
||||
.c0_ddr4_ui_clk(ddr_clk[0 +: 1]),
|
||||
.c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]),
|
||||
|
||||
.c0_ddr4_aresetn(!ddr_rst[0 +: 1]),
|
||||
|
||||
.c0_ddr4_s_axi_ctrl_awvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_awready(),
|
||||
.c0_ddr4_s_axi_ctrl_awaddr(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_wvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_wready(),
|
||||
.c0_ddr4_s_axi_ctrl_wdata(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_bvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_bready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_bresp(),
|
||||
.c0_ddr4_s_axi_ctrl_arvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_arready(),
|
||||
.c0_ddr4_s_axi_ctrl_araddr(31'd0),
|
||||
.c0_ddr4_s_axi_ctrl_rvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_rready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_rdata(),
|
||||
.c0_ddr4_s_axi_ctrl_rresp(),
|
||||
|
||||
.c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]),
|
||||
.c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]),
|
||||
.c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]),
|
||||
.c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]),
|
||||
.c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]),
|
||||
.c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]),
|
||||
.c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]),
|
||||
.c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH])
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign ddr4_adr = {17{1'bz}};
|
||||
assign ddr4_ba = {2{1'bz}};
|
||||
assign ddr4_bg = {1{1'bz}};
|
||||
assign ddr4_cke = 1'bz;
|
||||
assign ddr4_cs_n = 1'bz;
|
||||
assign ddr4_act_n = 1'bz;
|
||||
assign ddr4_odt = 1'bz;
|
||||
assign ddr4_reset_n = 1'b0;
|
||||
assign ddr4_dq = {72{1'bz}};
|
||||
assign ddr4_dqs_t = {9{1'bz}};
|
||||
assign ddr4_dqs_c = {9{1'bz}};
|
||||
assign ddr4_dm_dbi_n = {9{1'bz}};
|
||||
|
||||
OBUFTDS ddr4_ck_obuftds_inst (
|
||||
.I(1'b0),
|
||||
.T(1'b1),
|
||||
.O(ddr4_ck_t),
|
||||
.OB(ddr4_ck_c)
|
||||
);
|
||||
|
||||
assign ddr_clk = 0;
|
||||
assign ddr_rst = 0;
|
||||
|
||||
assign m_axi_ddr_awready = 0;
|
||||
assign m_axi_ddr_wready = 0;
|
||||
assign m_axi_ddr_bid = 0;
|
||||
assign m_axi_ddr_bresp = 0;
|
||||
assign m_axi_ddr_bvalid = 0;
|
||||
assign m_axi_ddr_arready = 0;
|
||||
assign m_axi_ddr_rid = 0;
|
||||
assign m_axi_ddr_rdata = 0;
|
||||
assign m_axi_ddr_rresp = 0;
|
||||
assign m_axi_ddr_rlast = 0;
|
||||
assign m_axi_ddr_rvalid = 0;
|
||||
|
||||
assign ddr_status = 0;
|
||||
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
fpga_core #(
|
||||
// FW and board IDs
|
||||
.FPGA_ID(FPGA_ID),
|
||||
@ -1226,6 +1432,16 @@ fpga_core #(
|
||||
.TX_RAM_SIZE(TX_RAM_SIZE),
|
||||
.RX_RAM_SIZE(RX_RAM_SIZE),
|
||||
|
||||
// RAM configuration
|
||||
.DDR_CH(DDR_CH),
|
||||
.DDR_ENABLE(DDR_ENABLE),
|
||||
.AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH),
|
||||
.AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH),
|
||||
.AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH),
|
||||
.AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH),
|
||||
.AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN),
|
||||
.AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST),
|
||||
|
||||
// Application block configuration
|
||||
.APP_ID(APP_ID),
|
||||
.APP_ENABLE(APP_ENABLE),
|
||||
@ -1540,7 +1756,53 @@ core_inst (
|
||||
.qsfp1_modprsl(qsfp1_modprsl_int),
|
||||
.qsfp1_resetl(qsfp1_resetl),
|
||||
.qsfp1_intl(qsfp1_intl_int),
|
||||
.qsfp1_lpmode(qsfp1_lpmode)
|
||||
.qsfp1_lpmode(qsfp1_lpmode),
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
.ddr_clk(ddr_clk),
|
||||
.ddr_rst(ddr_rst),
|
||||
|
||||
.m_axi_ddr_awid(m_axi_ddr_awid),
|
||||
.m_axi_ddr_awaddr(m_axi_ddr_awaddr),
|
||||
.m_axi_ddr_awlen(m_axi_ddr_awlen),
|
||||
.m_axi_ddr_awsize(m_axi_ddr_awsize),
|
||||
.m_axi_ddr_awburst(m_axi_ddr_awburst),
|
||||
.m_axi_ddr_awlock(m_axi_ddr_awlock),
|
||||
.m_axi_ddr_awcache(m_axi_ddr_awcache),
|
||||
.m_axi_ddr_awprot(m_axi_ddr_awprot),
|
||||
.m_axi_ddr_awqos(m_axi_ddr_awqos),
|
||||
.m_axi_ddr_awvalid(m_axi_ddr_awvalid),
|
||||
.m_axi_ddr_awready(m_axi_ddr_awready),
|
||||
.m_axi_ddr_wdata(m_axi_ddr_wdata),
|
||||
.m_axi_ddr_wstrb(m_axi_ddr_wstrb),
|
||||
.m_axi_ddr_wlast(m_axi_ddr_wlast),
|
||||
.m_axi_ddr_wvalid(m_axi_ddr_wvalid),
|
||||
.m_axi_ddr_wready(m_axi_ddr_wready),
|
||||
.m_axi_ddr_bid(m_axi_ddr_bid),
|
||||
.m_axi_ddr_bresp(m_axi_ddr_bresp),
|
||||
.m_axi_ddr_bvalid(m_axi_ddr_bvalid),
|
||||
.m_axi_ddr_bready(m_axi_ddr_bready),
|
||||
.m_axi_ddr_arid(m_axi_ddr_arid),
|
||||
.m_axi_ddr_araddr(m_axi_ddr_araddr),
|
||||
.m_axi_ddr_arlen(m_axi_ddr_arlen),
|
||||
.m_axi_ddr_arsize(m_axi_ddr_arsize),
|
||||
.m_axi_ddr_arburst(m_axi_ddr_arburst),
|
||||
.m_axi_ddr_arlock(m_axi_ddr_arlock),
|
||||
.m_axi_ddr_arcache(m_axi_ddr_arcache),
|
||||
.m_axi_ddr_arprot(m_axi_ddr_arprot),
|
||||
.m_axi_ddr_arqos(m_axi_ddr_arqos),
|
||||
.m_axi_ddr_arvalid(m_axi_ddr_arvalid),
|
||||
.m_axi_ddr_arready(m_axi_ddr_arready),
|
||||
.m_axi_ddr_rid(m_axi_ddr_rid),
|
||||
.m_axi_ddr_rdata(m_axi_ddr_rdata),
|
||||
.m_axi_ddr_rresp(m_axi_ddr_rresp),
|
||||
.m_axi_ddr_rlast(m_axi_ddr_rlast),
|
||||
.m_axi_ddr_rvalid(m_axi_ddr_rvalid),
|
||||
.m_axi_ddr_rready(m_axi_ddr_rready),
|
||||
|
||||
.ddr_status(ddr_status)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
@ -122,6 +122,16 @@ module fpga_core #
|
||||
parameter TX_RAM_SIZE = 32768,
|
||||
parameter RX_RAM_SIZE = 32768,
|
||||
|
||||
// RAM configuration
|
||||
parameter DDR_CH = 1,
|
||||
parameter DDR_ENABLE = 1,
|
||||
parameter AXI_DDR_DATA_WIDTH = 512,
|
||||
parameter AXI_DDR_ADDR_WIDTH = 32,
|
||||
parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8),
|
||||
parameter AXI_DDR_ID_WIDTH = 8,
|
||||
parameter AXI_DDR_MAX_BURST_LEN = 256,
|
||||
parameter AXI_DDR_NARROW_BURST = 0,
|
||||
|
||||
// Application block configuration
|
||||
parameter APP_ID = 32'h00000000,
|
||||
parameter APP_ENABLE = 0,
|
||||
@ -438,7 +448,53 @@ module fpga_core #
|
||||
output wire qsfp1_resetl,
|
||||
input wire qsfp1_modprsl,
|
||||
input wire qsfp1_intl,
|
||||
output wire qsfp1_lpmode
|
||||
output wire qsfp1_lpmode,
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
input wire [DDR_CH-1:0] ddr_clk,
|
||||
input wire [DDR_CH-1:0] ddr_rst,
|
||||
|
||||
output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid,
|
||||
output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr,
|
||||
output wire [DDR_CH*8-1:0] m_axi_ddr_awlen,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_awsize,
|
||||
output wire [DDR_CH*2-1:0] m_axi_ddr_awburst,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_awlock,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_awcache,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_awprot,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_awqos,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_awvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_awready,
|
||||
output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata,
|
||||
output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_wlast,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_wvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_wready,
|
||||
input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid,
|
||||
input wire [DDR_CH*2-1:0] m_axi_ddr_bresp,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_bvalid,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_bready,
|
||||
output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid,
|
||||
output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr,
|
||||
output wire [DDR_CH*8-1:0] m_axi_ddr_arlen,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_arsize,
|
||||
output wire [DDR_CH*2-1:0] m_axi_ddr_arburst,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_arlock,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_arcache,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_arprot,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_arqos,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_arvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_arready,
|
||||
input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid,
|
||||
input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata,
|
||||
input wire [DDR_CH*2-1:0] m_axi_ddr_rresp,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_rlast,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_rvalid,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_rready,
|
||||
|
||||
input wire [DDR_CH-1:0] ddr_status
|
||||
);
|
||||
|
||||
parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF;
|
||||
@ -1093,6 +1149,25 @@ mqnic_core_pcie_us #(
|
||||
.TX_RAM_SIZE(TX_RAM_SIZE),
|
||||
.RX_RAM_SIZE(RX_RAM_SIZE),
|
||||
|
||||
// RAM configuration
|
||||
.DDR_CH(DDR_CH),
|
||||
.DDR_ENABLE(DDR_ENABLE),
|
||||
.DDR_GROUP_SIZE(1),
|
||||
.AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH),
|
||||
.AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH),
|
||||
.AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH),
|
||||
.AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH),
|
||||
.AXI_DDR_AWUSER_ENABLE(0),
|
||||
.AXI_DDR_WUSER_ENABLE(0),
|
||||
.AXI_DDR_BUSER_ENABLE(0),
|
||||
.AXI_DDR_ARUSER_ENABLE(0),
|
||||
.AXI_DDR_RUSER_ENABLE(0),
|
||||
.AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN),
|
||||
.AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST),
|
||||
.AXI_DDR_FIXED_BURST(0),
|
||||
.AXI_DDR_WRAP_BURST(1),
|
||||
.HBM_ENABLE(0),
|
||||
|
||||
// Application block configuration
|
||||
.APP_ID(APP_ID),
|
||||
.APP_ENABLE(APP_ENABLE),
|
||||
@ -1370,6 +1445,108 @@ core_inst (
|
||||
|
||||
.eth_rx_status(eth_rx_status),
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
.ddr_clk(ddr_clk),
|
||||
.ddr_rst(ddr_rst),
|
||||
|
||||
.m_axi_ddr_awid(m_axi_ddr_awid),
|
||||
.m_axi_ddr_awaddr(m_axi_ddr_awaddr),
|
||||
.m_axi_ddr_awlen(m_axi_ddr_awlen),
|
||||
.m_axi_ddr_awsize(m_axi_ddr_awsize),
|
||||
.m_axi_ddr_awburst(m_axi_ddr_awburst),
|
||||
.m_axi_ddr_awlock(m_axi_ddr_awlock),
|
||||
.m_axi_ddr_awcache(m_axi_ddr_awcache),
|
||||
.m_axi_ddr_awprot(m_axi_ddr_awprot),
|
||||
.m_axi_ddr_awqos(m_axi_ddr_awqos),
|
||||
.m_axi_ddr_awuser(),
|
||||
.m_axi_ddr_awvalid(m_axi_ddr_awvalid),
|
||||
.m_axi_ddr_awready(m_axi_ddr_awready),
|
||||
.m_axi_ddr_wdata(m_axi_ddr_wdata),
|
||||
.m_axi_ddr_wstrb(m_axi_ddr_wstrb),
|
||||
.m_axi_ddr_wlast(m_axi_ddr_wlast),
|
||||
.m_axi_ddr_wuser(),
|
||||
.m_axi_ddr_wvalid(m_axi_ddr_wvalid),
|
||||
.m_axi_ddr_wready(m_axi_ddr_wready),
|
||||
.m_axi_ddr_bid(m_axi_ddr_bid),
|
||||
.m_axi_ddr_bresp(m_axi_ddr_bresp),
|
||||
.m_axi_ddr_buser(0),
|
||||
.m_axi_ddr_bvalid(m_axi_ddr_bvalid),
|
||||
.m_axi_ddr_bready(m_axi_ddr_bready),
|
||||
.m_axi_ddr_arid(m_axi_ddr_arid),
|
||||
.m_axi_ddr_araddr(m_axi_ddr_araddr),
|
||||
.m_axi_ddr_arlen(m_axi_ddr_arlen),
|
||||
.m_axi_ddr_arsize(m_axi_ddr_arsize),
|
||||
.m_axi_ddr_arburst(m_axi_ddr_arburst),
|
||||
.m_axi_ddr_arlock(m_axi_ddr_arlock),
|
||||
.m_axi_ddr_arcache(m_axi_ddr_arcache),
|
||||
.m_axi_ddr_arprot(m_axi_ddr_arprot),
|
||||
.m_axi_ddr_arqos(m_axi_ddr_arqos),
|
||||
.m_axi_ddr_aruser(),
|
||||
.m_axi_ddr_arvalid(m_axi_ddr_arvalid),
|
||||
.m_axi_ddr_arready(m_axi_ddr_arready),
|
||||
.m_axi_ddr_rid(m_axi_ddr_rid),
|
||||
.m_axi_ddr_rdata(m_axi_ddr_rdata),
|
||||
.m_axi_ddr_rresp(m_axi_ddr_rresp),
|
||||
.m_axi_ddr_rlast(m_axi_ddr_rlast),
|
||||
.m_axi_ddr_ruser(0),
|
||||
.m_axi_ddr_rvalid(m_axi_ddr_rvalid),
|
||||
.m_axi_ddr_rready(m_axi_ddr_rready),
|
||||
|
||||
.ddr_status(ddr_status),
|
||||
|
||||
/*
|
||||
* HBM
|
||||
*/
|
||||
.hbm_clk(0),
|
||||
.hbm_rst(0),
|
||||
|
||||
.m_axi_hbm_awid(),
|
||||
.m_axi_hbm_awaddr(),
|
||||
.m_axi_hbm_awlen(),
|
||||
.m_axi_hbm_awsize(),
|
||||
.m_axi_hbm_awburst(),
|
||||
.m_axi_hbm_awlock(),
|
||||
.m_axi_hbm_awcache(),
|
||||
.m_axi_hbm_awprot(),
|
||||
.m_axi_hbm_awqos(),
|
||||
.m_axi_hbm_awuser(),
|
||||
.m_axi_hbm_awvalid(),
|
||||
.m_axi_hbm_awready(0),
|
||||
.m_axi_hbm_wdata(),
|
||||
.m_axi_hbm_wstrb(),
|
||||
.m_axi_hbm_wlast(),
|
||||
.m_axi_hbm_wuser(),
|
||||
.m_axi_hbm_wvalid(),
|
||||
.m_axi_hbm_wready(0),
|
||||
.m_axi_hbm_bid(0),
|
||||
.m_axi_hbm_bresp(0),
|
||||
.m_axi_hbm_buser(0),
|
||||
.m_axi_hbm_bvalid(0),
|
||||
.m_axi_hbm_bready(),
|
||||
.m_axi_hbm_arid(),
|
||||
.m_axi_hbm_araddr(),
|
||||
.m_axi_hbm_arlen(),
|
||||
.m_axi_hbm_arsize(),
|
||||
.m_axi_hbm_arburst(),
|
||||
.m_axi_hbm_arlock(),
|
||||
.m_axi_hbm_arcache(),
|
||||
.m_axi_hbm_arprot(),
|
||||
.m_axi_hbm_arqos(),
|
||||
.m_axi_hbm_aruser(),
|
||||
.m_axi_hbm_arvalid(),
|
||||
.m_axi_hbm_arready(0),
|
||||
.m_axi_hbm_rid(0),
|
||||
.m_axi_hbm_rdata(0),
|
||||
.m_axi_hbm_rresp(0),
|
||||
.m_axi_hbm_rlast(0),
|
||||
.m_axi_hbm_ruser(0),
|
||||
.m_axi_hbm_rvalid(0),
|
||||
.m_axi_hbm_rready(),
|
||||
|
||||
.hbm_status(0),
|
||||
|
||||
/*
|
||||
* Statistics input
|
||||
*/
|
||||
|
||||
@ -7,6 +7,7 @@ This design targets the Alpha Data ADM-PCIE-9V3 FPGA board.
|
||||
* FPGA: xcvu3p-ffvc1517-2-i
|
||||
* MAC: Xilinx 100G CMAC
|
||||
* PHY: 100G CAUI-4 CMAC and internal GTY transceivers
|
||||
* RAM: 16 GB DDR4 2400 (2x 1G x72)
|
||||
|
||||
## How to build
|
||||
|
||||
|
||||
@ -17,6 +17,16 @@ set_property -dict {LOC AP26 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports
|
||||
set_property -dict {LOC AP27 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports clk_300mhz_n]
|
||||
create_clock -period 3.333 -name clk_300mhz [get_ports clk_300mhz_p]
|
||||
|
||||
# 300 MHz memory clock (C0)
|
||||
set_property -dict {LOC G31 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports mem_clk_300mhz_0_p]
|
||||
set_property -dict {LOC G32 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports mem_clk_300mhz_0_n]
|
||||
# create_clock -period 3.333 -name mem_clk_300mhz_0 [get_ports mem_clk_300mhz_0_p]
|
||||
|
||||
# 300 MHz memory clock (C1)
|
||||
set_property -dict {LOC AN25 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports mem_clk_300mhz_1_p]
|
||||
set_property -dict {LOC AN26 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports mem_clk_300mhz_1_n]
|
||||
# create_clock -period 3.333 -name mem_clk_300mhz_1 [get_ports mem_clk_300mhz_1_p]
|
||||
|
||||
# LEDs
|
||||
set_property -dict {LOC AT27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {user_led_g[0]}]
|
||||
set_property -dict {LOC AU27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {user_led_g[1]}]
|
||||
@ -193,6 +203,282 @@ create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_1_p]
|
||||
set_false_path -from [get_ports {perst_0}]
|
||||
set_input_delay 0 [get_ports {perst_0}]
|
||||
|
||||
# DDR4 C0
|
||||
# 5x K4A8G085WB-RC
|
||||
set_property -dict {LOC F9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}]
|
||||
set_property -dict {LOC G9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}]
|
||||
set_property -dict {LOC G11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}]
|
||||
set_property -dict {LOC D11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}]
|
||||
set_property -dict {LOC E12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}]
|
||||
set_property -dict {LOC G10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}]
|
||||
set_property -dict {LOC F10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}]
|
||||
set_property -dict {LOC J9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}]
|
||||
set_property -dict {LOC J8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}]
|
||||
set_property -dict {LOC F12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}]
|
||||
set_property -dict {LOC D9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}]
|
||||
set_property -dict {LOC H11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}]
|
||||
set_property -dict {LOC E8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}]
|
||||
set_property -dict {LOC J11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}]
|
||||
set_property -dict {LOC C9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}]
|
||||
set_property -dict {LOC B11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}]
|
||||
set_property -dict {LOC K12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}]
|
||||
# set_property -dict {LOC H9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[17]}]
|
||||
set_property -dict {LOC F8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}]
|
||||
set_property -dict {LOC H8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}]
|
||||
set_property -dict {LOC D10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}]
|
||||
set_property -dict {LOC E11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}]
|
||||
# set_property -dict {LOC B10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_c[0]}]
|
||||
# set_property -dict {LOC C11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_c[1]}]
|
||||
# set_property -dict {LOC A9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_c[2]}]
|
||||
set_property -dict {LOC H12 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t}]
|
||||
set_property -dict {LOC G12 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c}]
|
||||
set_property -dict {LOC B9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke}]
|
||||
set_property -dict {LOC E10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n}]
|
||||
set_property -dict {LOC C12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}]
|
||||
set_property -dict {LOC A10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt}]
|
||||
set_property -dict {LOC G7 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}]
|
||||
set_property -dict {LOC F7 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_reset_n}]
|
||||
set_property -dict {LOC H7 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_alert_n}]
|
||||
set_property -dict {LOC J10 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_ten}]
|
||||
|
||||
set_property -dict {LOC L10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}]
|
||||
set_property -dict {LOC L9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}]
|
||||
set_property -dict {LOC N9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}]
|
||||
set_property -dict {LOC M9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}]
|
||||
set_property -dict {LOC M10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}]
|
||||
set_property -dict {LOC K11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}]
|
||||
set_property -dict {LOC M11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}]
|
||||
set_property -dict {LOC K10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}]
|
||||
set_property -dict {LOC L17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}]
|
||||
set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}]
|
||||
set_property -dict {LOC M15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}]
|
||||
set_property -dict {LOC M17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}]
|
||||
set_property -dict {LOC M14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}]
|
||||
set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}]
|
||||
set_property -dict {LOC N16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}]
|
||||
set_property -dict {LOC N17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}]
|
||||
set_property -dict {LOC F15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}]
|
||||
set_property -dict {LOC E16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}]
|
||||
set_property -dict {LOC F14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}]
|
||||
set_property -dict {LOC E17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}]
|
||||
set_property -dict {LOC G16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}]
|
||||
set_property -dict {LOC F17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}]
|
||||
set_property -dict {LOC E15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}]
|
||||
set_property -dict {LOC G17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}]
|
||||
set_property -dict {LOC A17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}]
|
||||
set_property -dict {LOC C16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}]
|
||||
set_property -dict {LOC B16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}]
|
||||
set_property -dict {LOC A14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}]
|
||||
set_property -dict {LOC B17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}]
|
||||
set_property -dict {LOC B14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}]
|
||||
set_property -dict {LOC D16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}]
|
||||
set_property -dict {LOC D15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}]
|
||||
set_property -dict {LOC F18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}]
|
||||
set_property -dict {LOC F20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}]
|
||||
set_property -dict {LOC F19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}]
|
||||
set_property -dict {LOC D21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}]
|
||||
set_property -dict {LOC E18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}]
|
||||
set_property -dict {LOC G19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}]
|
||||
set_property -dict {LOC E21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}]
|
||||
set_property -dict {LOC G20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}]
|
||||
set_property -dict {LOC D18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}]
|
||||
set_property -dict {LOC B22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}]
|
||||
set_property -dict {LOC A19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}]
|
||||
set_property -dict {LOC A18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}]
|
||||
set_property -dict {LOC C19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}]
|
||||
set_property -dict {LOC B19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}]
|
||||
set_property -dict {LOC A22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}]
|
||||
set_property -dict {LOC C18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}]
|
||||
set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}]
|
||||
set_property -dict {LOC J20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}]
|
||||
set_property -dict {LOC H19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}]
|
||||
set_property -dict {LOC J19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}]
|
||||
set_property -dict {LOC H18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}]
|
||||
set_property -dict {LOC J18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}]
|
||||
set_property -dict {LOC G21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}]
|
||||
set_property -dict {LOC K18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}]
|
||||
set_property -dict {LOC L20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}]
|
||||
set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}]
|
||||
set_property -dict {LOC N19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}]
|
||||
set_property -dict {LOC M21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}]
|
||||
set_property -dict {LOC M19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}]
|
||||
set_property -dict {LOC M22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}]
|
||||
set_property -dict {LOC L19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}]
|
||||
set_property -dict {LOC M20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}]
|
||||
set_property -dict {LOC H16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}]
|
||||
set_property -dict {LOC K15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}]
|
||||
set_property -dict {LOC J16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}]
|
||||
set_property -dict {LOC J14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}]
|
||||
set_property -dict {LOC K13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}]
|
||||
set_property -dict {LOC L13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}]
|
||||
set_property -dict {LOC H14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}]
|
||||
set_property -dict {LOC J15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}]
|
||||
set_property -dict {LOC M12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}]
|
||||
set_property -dict {LOC L12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}]
|
||||
set_property -dict {LOC L15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}]
|
||||
set_property -dict {LOC L14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}]
|
||||
set_property -dict {LOC F13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}]
|
||||
set_property -dict {LOC E13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}]
|
||||
set_property -dict {LOC B15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}]
|
||||
set_property -dict {LOC A15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}]
|
||||
set_property -dict {LOC F22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}]
|
||||
set_property -dict {LOC E22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}]
|
||||
set_property -dict {LOC C21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}]
|
||||
set_property -dict {LOC B21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}]
|
||||
set_property -dict {LOC K21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}]
|
||||
set_property -dict {LOC K20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}]
|
||||
set_property -dict {LOC L22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}]
|
||||
set_property -dict {LOC K22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}]
|
||||
set_property -dict {LOC K17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}]
|
||||
set_property -dict {LOC K16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}]
|
||||
set_property -dict {LOC N12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[0]}]
|
||||
set_property -dict {LOC P14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[1]}]
|
||||
set_property -dict {LOC G15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[2]}]
|
||||
set_property -dict {LOC D14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[3]}]
|
||||
set_property -dict {LOC E20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[4]}]
|
||||
set_property -dict {LOC B20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[5]}]
|
||||
set_property -dict {LOC H22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[6]}]
|
||||
set_property -dict {LOC N22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[7]}]
|
||||
set_property -dict {LOC J13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[8]}]
|
||||
|
||||
# DDR4 C1
|
||||
# 5x K4A8G085WB-RC
|
||||
set_property -dict {LOC AN9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}]
|
||||
set_property -dict {LOC AM9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}]
|
||||
set_property -dict {LOC AP11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}]
|
||||
set_property -dict {LOC AU9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}]
|
||||
set_property -dict {LOC AT10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}]
|
||||
set_property -dict {LOC AL12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}]
|
||||
set_property -dict {LOC AM12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}]
|
||||
set_property -dict {LOC AM10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}]
|
||||
set_property -dict {LOC AL11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}]
|
||||
set_property -dict {LOC AP7 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}]
|
||||
set_property -dict {LOC AR8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}]
|
||||
set_property -dict {LOC AL10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}]
|
||||
set_property -dict {LOC AP8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}]
|
||||
set_property -dict {LOC AK11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}]
|
||||
set_property -dict {LOC AP9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}]
|
||||
set_property -dict {LOC AV10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}]
|
||||
set_property -dict {LOC AT11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}]
|
||||
# set_property -dict {LOC AL8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[17]}]
|
||||
set_property -dict {LOC AN11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}]
|
||||
set_property -dict {LOC AR9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}]
|
||||
set_property -dict {LOC AP12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}]
|
||||
set_property -dict {LOC AN10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}]
|
||||
# set_property -dict {LOC AW13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_c[0]}]
|
||||
# set_property -dict {LOC AU10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_c[1]}]
|
||||
# set_property -dict {LOC AW11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_c[2]}]
|
||||
set_property -dict {LOC AM7 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t}]
|
||||
set_property -dict {LOC AN7 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c}]
|
||||
set_property -dict {LOC AU12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke}]
|
||||
set_property -dict {LOC AT12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n}]
|
||||
set_property -dict {LOC AV9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}]
|
||||
set_property -dict {LOC AR11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt}]
|
||||
set_property -dict {LOC AM8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}]
|
||||
set_property -dict {LOC AN12 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}]
|
||||
set_property -dict {LOC AR10 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_alert_n}]
|
||||
set_property -dict {LOC AV11 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_ten}]
|
||||
|
||||
set_property -dict {LOC AK9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}]
|
||||
set_property -dict {LOC AK10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}]
|
||||
set_property -dict {LOC AH10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}]
|
||||
set_property -dict {LOC AJ11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}]
|
||||
set_property -dict {LOC AJ9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}]
|
||||
set_property -dict {LOC AH12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}]
|
||||
set_property -dict {LOC AG10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}]
|
||||
set_property -dict {LOC AJ12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}]
|
||||
set_property -dict {LOC AM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}]
|
||||
set_property -dict {LOC AN14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}]
|
||||
set_property -dict {LOC AL13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}]
|
||||
set_property -dict {LOC AM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}]
|
||||
set_property -dict {LOC AL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}]
|
||||
set_property -dict {LOC AM17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}]
|
||||
set_property -dict {LOC AL17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}]
|
||||
set_property -dict {LOC AM13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}]
|
||||
set_property -dict {LOC AR15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}]
|
||||
set_property -dict {LOC AP14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}]
|
||||
set_property -dict {LOC AT15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}]
|
||||
set_property -dict {LOC AR14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}]
|
||||
set_property -dict {LOC AP17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}]
|
||||
set_property -dict {LOC AN16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}]
|
||||
set_property -dict {LOC AN17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}]
|
||||
set_property -dict {LOC AN15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}]
|
||||
set_property -dict {LOC AU15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}]
|
||||
set_property -dict {LOC AT17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}]
|
||||
set_property -dict {LOC AV15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}]
|
||||
set_property -dict {LOC AT16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}]
|
||||
set_property -dict {LOC AV14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}]
|
||||
set_property -dict {LOC AW17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}]
|
||||
set_property -dict {LOC AW14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}]
|
||||
set_property -dict {LOC AW18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}]
|
||||
set_property -dict {LOC AP19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}]
|
||||
set_property -dict {LOC AT20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}]
|
||||
set_property -dict {LOC AN21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}]
|
||||
set_property -dict {LOC AR19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}]
|
||||
set_property -dict {LOC AN20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}]
|
||||
set_property -dict {LOC AR18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}]
|
||||
set_property -dict {LOC AR20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}]
|
||||
set_property -dict {LOC AP18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}]
|
||||
set_property -dict {LOC AW19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}]
|
||||
set_property -dict {LOC AU22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}]
|
||||
set_property -dict {LOC AV19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}]
|
||||
set_property -dict {LOC AW22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}]
|
||||
set_property -dict {LOC AU18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}]
|
||||
set_property -dict {LOC AT22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}]
|
||||
set_property -dict {LOC AW21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}]
|
||||
set_property -dict {LOC AU19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}]
|
||||
set_property -dict {LOC AH19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}]
|
||||
set_property -dict {LOC AJ22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}]
|
||||
set_property -dict {LOC AF21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}]
|
||||
set_property -dict {LOC AH22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}]
|
||||
set_property -dict {LOC AF20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}]
|
||||
set_property -dict {LOC AJ19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}]
|
||||
set_property -dict {LOC AH21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}]
|
||||
set_property -dict {LOC AJ21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}]
|
||||
set_property -dict {LOC AM19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}]
|
||||
set_property -dict {LOC AK20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}]
|
||||
set_property -dict {LOC AM22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}]
|
||||
set_property -dict {LOC AL22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}]
|
||||
set_property -dict {LOC AM20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}]
|
||||
set_property -dict {LOC AK19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}]
|
||||
set_property -dict {LOC AN19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}]
|
||||
set_property -dict {LOC AL20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}]
|
||||
set_property -dict {LOC AF15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}]
|
||||
set_property -dict {LOC AJ17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}]
|
||||
set_property -dict {LOC AH17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}]
|
||||
set_property -dict {LOC AJ14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}]
|
||||
set_property -dict {LOC AG15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}]
|
||||
set_property -dict {LOC AJ13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}]
|
||||
set_property -dict {LOC AG17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}]
|
||||
set_property -dict {LOC AJ16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}]
|
||||
set_property -dict {LOC AG9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}]
|
||||
set_property -dict {LOC AH9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}]
|
||||
set_property -dict {LOC AK16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}]
|
||||
set_property -dict {LOC AL16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}]
|
||||
set_property -dict {LOC AR13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}]
|
||||
set_property -dict {LOC AT13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}]
|
||||
set_property -dict {LOC AU17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}]
|
||||
set_property -dict {LOC AV17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}]
|
||||
set_property -dict {LOC AN22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}]
|
||||
set_property -dict {LOC AP22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}]
|
||||
set_property -dict {LOC AV22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}]
|
||||
set_property -dict {LOC AV21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}]
|
||||
set_property -dict {LOC AG20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}]
|
||||
set_property -dict {LOC AH20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}]
|
||||
set_property -dict {LOC AK21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}]
|
||||
set_property -dict {LOC AL21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}]
|
||||
set_property -dict {LOC AH16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}]
|
||||
set_property -dict {LOC AH15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}]
|
||||
set_property -dict {LOC AG12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[0]}]
|
||||
set_property -dict {LOC AK15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[1]}]
|
||||
set_property -dict {LOC AP16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[2]}]
|
||||
set_property -dict {LOC AV16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[3]}]
|
||||
set_property -dict {LOC AP21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[4]}]
|
||||
set_property -dict {LOC AU20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[5]}]
|
||||
set_property -dict {LOC AG19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[6]}]
|
||||
set_property -dict {LOC AL18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[7]}]
|
||||
set_property -dict {LOC AG14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[8]}]
|
||||
|
||||
# QSPI flash
|
||||
set_property -dict {LOC AF30 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[0]}]
|
||||
set_property -dict {LOC AG30 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[1]}]
|
||||
|
||||
@ -119,6 +119,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
|
||||
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
|
||||
IP_TCL_FILES += ip/cmac_usplus_0.tcl
|
||||
IP_TCL_FILES += ip/cmac_usplus_1.tcl
|
||||
IP_TCL_FILES += ip/ddr4_0.tcl
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
@ -136,6 +136,12 @@ dict set params MAX_TX_SIZE "9214"
|
||||
dict set params MAX_RX_SIZE "9214"
|
||||
dict set params TX_RAM_SIZE "131072"
|
||||
dict set params RX_RAM_SIZE "131072"
|
||||
|
||||
# RAM configuration
|
||||
dict set params DDR_CH "2"
|
||||
dict set params DDR_ENABLE "1"
|
||||
dict set params AXI_DDR_ID_WIDTH "8"
|
||||
dict set params AXI_DDR_MAX_BURST_LEN "256"
|
||||
|
||||
# Application block configuration
|
||||
dict set params APP_ID "32'h00000000"
|
||||
@ -187,6 +193,19 @@ dict set params STAT_PCIE_ENABLE "1"
|
||||
dict set params STAT_INC_WIDTH "24"
|
||||
dict set params STAT_ID_WIDTH "12"
|
||||
|
||||
# DDR4 MIG settings
|
||||
if {[dict get $params DDR_ENABLE]} {
|
||||
set ddr4 [get_ips ddr4_0]
|
||||
|
||||
# set AXI ID width
|
||||
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
|
||||
|
||||
# extract AXI configuration
|
||||
dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4]
|
||||
dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4]
|
||||
dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1]
|
||||
}
|
||||
|
||||
# PCIe IP core settings
|
||||
set pcie [get_ips pcie4_uscale_plus_0]
|
||||
|
||||
|
||||
@ -121,6 +121,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
|
||||
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
|
||||
IP_TCL_FILES += ip/cmac_usplus_0.tcl
|
||||
IP_TCL_FILES += ip/cmac_usplus_1.tcl
|
||||
IP_TCL_FILES += ip/ddr4_0.tcl
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
@ -136,6 +136,12 @@ dict set params MAX_TX_SIZE "9214"
|
||||
dict set params MAX_RX_SIZE "9214"
|
||||
dict set params TX_RAM_SIZE "131072"
|
||||
dict set params RX_RAM_SIZE "131072"
|
||||
|
||||
# RAM configuration
|
||||
dict set params DDR_CH "2"
|
||||
dict set params DDR_ENABLE "1"
|
||||
dict set params AXI_DDR_ID_WIDTH "8"
|
||||
dict set params AXI_DDR_MAX_BURST_LEN "256"
|
||||
|
||||
# Application block configuration
|
||||
dict set params APP_ID "32'h00000000"
|
||||
@ -187,6 +193,19 @@ dict set params STAT_PCIE_ENABLE "1"
|
||||
dict set params STAT_INC_WIDTH "24"
|
||||
dict set params STAT_ID_WIDTH "12"
|
||||
|
||||
# DDR4 MIG settings
|
||||
if {[dict get $params DDR_ENABLE]} {
|
||||
set ddr4 [get_ips ddr4_0]
|
||||
|
||||
# set AXI ID width
|
||||
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
|
||||
|
||||
# extract AXI configuration
|
||||
dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4]
|
||||
dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4]
|
||||
dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1]
|
||||
}
|
||||
|
||||
# PCIe IP core settings
|
||||
set pcie [get_ips pcie4_uscale_plus_0]
|
||||
|
||||
|
||||
@ -0,0 +1,5 @@
|
||||
Part type,Part name,Rank,StackHeight,CA Mirror,Data mask,Address width,Row width,Column width,Bank width,Bank group width,CS width,CKE width,ODT width,CK width,Memory speed grade,Memory density,Component density,Memory device width,Memory component width,Data bits per strobe,IO Voltages,Data widths,Min period,Max period,tCKE,tFAW,tFAW_dlr,tMRD,tRAS,tRCD,tREFI,tRFC,tRFC_dlr,tRP,tRRD_S,tRRD_L,tRRD_dlr,tRTP,tWR,tWTR_S,tWTR_L,tXPR,tZQCS,tZQINIT,tCCD_3ds,cas latency,cas write latency,burst length,RTT (nominal) - ODT
|
||||
Components,CUSTOM_MT40A1G8PM-083E,1,1,0,1,17,16,10,2,2,1,1,1,1,083E,8Gb,8Gb,8,8,8,1.2V,"72",833,1600,5000 ps,21000 ps,0,8 tck,32000 ps,13320 ps,7800000 ps,350000 ps,0,13320 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,"17","12",8,RZQ/6
|
||||
Components,CUSTOM_DBI_RD_MT40A1G8PM-083E,1,1,0,1,17,16,10,2,2,1,1,1,1,083E,8Gb,8Gb,8,8,8,1.2V,"72",833,1600,5000 ps,21000 ps,0,8 tck,32000 ps,13320 ps,7800000 ps,350000 ps,0,13320 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,"20","12",8,RZQ/6
|
||||
Components,CUSTOM_K4A8G085WB-RC,1,1,0,1,17,16,10,2,2,1,1,1,1,083,8Gb,8Gb,8,8,8,1.2V,"72",833,1600,5000 ps,21000 ps,0,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,0,14160 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,"17","12",8,RZQ/6
|
||||
Components,CUSTOM_DBI_RD_K4A8G085WB-RC,1,1,0,1,17,16,10,2,2,1,1,1,1,083,8Gb,8Gb,8,8,8,1.2V,"72",833,1600,5000 ps,21000 ps,0,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,0,14160 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,"20","12",8,RZQ/6
|
||||
|
23
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/ip/ddr4_0.tcl
Normal file
23
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/ip/ddr4_0.tcl
Normal file
@ -0,0 +1,23 @@
|
||||
|
||||
create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0
|
||||
|
||||
set path [file dirname [file normalize [info script]]]
|
||||
|
||||
set_property -dict [list \
|
||||
CONFIG.C0.DDR4_AxiSelection {true} \
|
||||
CONFIG.C0.DDR4_AxiDataWidth {512} \
|
||||
CONFIG.C0.DDR4_AxiIDWidth {8} \
|
||||
CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \
|
||||
CONFIG.C0.DDR4_TimePeriod {833} \
|
||||
CONFIG.C0.DDR4_InputClockPeriod {3332} \
|
||||
CONFIG.C0.DDR4_CustomParts "$path/custom_parts_2400.csv" \
|
||||
CONFIG.C0.DDR4_isCustom {true} \
|
||||
CONFIG.C0.DDR4_MemoryType {Components} \
|
||||
CONFIG.C0.DDR4_MemoryPart {CUSTOM_K4A8G085WB-RC} \
|
||||
CONFIG.C0.DDR4_DataWidth {72} \
|
||||
CONFIG.C0.DDR4_DataMask {NO_DM_NO_DBI} \
|
||||
CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \
|
||||
CONFIG.C0.DDR4_CasLatency {17} \
|
||||
CONFIG.C0.DDR4_CasWriteLatency {12} \
|
||||
CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV}
|
||||
] [get_ips ddr4_0]
|
||||
@ -109,6 +109,15 @@ module fpga #
|
||||
parameter TX_RAM_SIZE = 131072,
|
||||
parameter RX_RAM_SIZE = 131072,
|
||||
|
||||
// RAM configuration
|
||||
parameter DDR_CH = 2,
|
||||
parameter DDR_ENABLE = 1,
|
||||
parameter AXI_DDR_DATA_WIDTH = 512,
|
||||
parameter AXI_DDR_ADDR_WIDTH = 33,
|
||||
parameter AXI_DDR_ID_WIDTH = 8,
|
||||
parameter AXI_DDR_MAX_BURST_LEN = 256,
|
||||
parameter AXI_DDR_NARROW_BURST = 0,
|
||||
|
||||
// Application block configuration
|
||||
parameter APP_ID = 32'h00000000,
|
||||
parameter APP_ENABLE = 0,
|
||||
@ -178,6 +187,10 @@ module fpga #
|
||||
*/
|
||||
input wire clk_300mhz_p,
|
||||
input wire clk_300mhz_n,
|
||||
input wire mem_clk_300mhz_0_p,
|
||||
input wire mem_clk_300mhz_0_n,
|
||||
input wire mem_clk_300mhz_1_p,
|
||||
input wire mem_clk_300mhz_1_n,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
@ -253,6 +266,45 @@ module fpga #
|
||||
inout wire eeprom_i2c_sda,
|
||||
output wire eeprom_wp,
|
||||
|
||||
/*
|
||||
* DDR4
|
||||
*/
|
||||
output wire [16:0] ddr4_c0_adr,
|
||||
output wire [1:0] ddr4_c0_ba,
|
||||
output wire [1:0] ddr4_c0_bg,
|
||||
output wire ddr4_c0_ck_t,
|
||||
output wire ddr4_c0_ck_c,
|
||||
output wire ddr4_c0_cke,
|
||||
output wire ddr4_c0_cs_n,
|
||||
output wire ddr4_c0_act_n,
|
||||
output wire ddr4_c0_odt,
|
||||
output wire ddr4_c0_par,
|
||||
input wire ddr4_c0_alert_n,
|
||||
output wire ddr4_c0_reset_n,
|
||||
output wire ddr4_c0_ten,
|
||||
inout wire [71:0] ddr4_c0_dq,
|
||||
inout wire [8:0] ddr4_c0_dqs_t,
|
||||
inout wire [8:0] ddr4_c0_dqs_c,
|
||||
inout wire [8:0] ddr4_c0_dm_dbi_n,
|
||||
|
||||
output wire [16:0] ddr4_c1_adr,
|
||||
output wire [1:0] ddr4_c1_ba,
|
||||
output wire [1:0] ddr4_c1_bg,
|
||||
output wire ddr4_c1_ck_t,
|
||||
output wire ddr4_c1_ck_c,
|
||||
output wire ddr4_c1_cke,
|
||||
output wire ddr4_c1_cs_n,
|
||||
output wire ddr4_c1_act_n,
|
||||
output wire ddr4_c1_odt,
|
||||
output wire ddr4_c1_par,
|
||||
input wire ddr4_c1_alert_n,
|
||||
output wire ddr4_c1_reset_n,
|
||||
output wire ddr4_c1_ten,
|
||||
inout wire [71:0] ddr4_c1_dq,
|
||||
inout wire [8:0] ddr4_c1_dqs_t,
|
||||
inout wire [8:0] ddr4_c1_dqs_c,
|
||||
inout wire [8:0] ddr4_c1_dm_dbi_n,
|
||||
|
||||
/*
|
||||
* QSPI
|
||||
*/
|
||||
@ -270,6 +322,8 @@ parameter PTP_SEPARATE_RX_CLOCK = 1;
|
||||
// Interface configuration
|
||||
parameter TX_TAG_WIDTH = 16;
|
||||
|
||||
// RAM configuration
|
||||
parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8);
|
||||
|
||||
// Ethernet interface configuration
|
||||
parameter AXIS_ETH_DATA_WIDTH = 512;
|
||||
@ -1757,6 +1811,301 @@ sync_reset_ptp_rst_inst (
|
||||
assign front_led[0] = qsfp_0_rx_status;
|
||||
assign front_led[1] = qsfp_1_rx_status;
|
||||
|
||||
// DDR4
|
||||
wire [DDR_CH-1:0] ddr_clk;
|
||||
wire [DDR_CH-1:0] ddr_rst;
|
||||
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid;
|
||||
wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr;
|
||||
wire [DDR_CH*8-1:0] m_axi_ddr_awlen;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_awsize;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_awburst;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_awlock;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_awcache;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_awprot;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_awqos;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_awvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_awready;
|
||||
wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata;
|
||||
wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_wlast;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_wvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_wready;
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_bresp;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_bvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_bready;
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid;
|
||||
wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr;
|
||||
wire [DDR_CH*8-1:0] m_axi_ddr_arlen;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_arsize;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_arburst;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_arlock;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_arcache;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_arprot;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_arqos;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_arvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_arready;
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid;
|
||||
wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_rresp;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_rlast;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_rvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_rready;
|
||||
|
||||
wire [DDR_CH-1:0] ddr_status;
|
||||
|
||||
generate
|
||||
|
||||
if (DDR_ENABLE && DDR_CH > 0) begin
|
||||
|
||||
ddr4_0 ddr4_c0_inst (
|
||||
.c0_sys_clk_p(mem_clk_300mhz_0_p),
|
||||
.c0_sys_clk_n(mem_clk_300mhz_0_n),
|
||||
.sys_rst(pcie_user_reset),
|
||||
|
||||
.c0_init_calib_complete(ddr_status[0 +: 1]),
|
||||
.c0_ddr4_interrupt(),
|
||||
.dbg_clk(),
|
||||
.dbg_bus(),
|
||||
|
||||
.c0_ddr4_adr(ddr4_c0_adr),
|
||||
.c0_ddr4_ba(ddr4_c0_ba),
|
||||
.c0_ddr4_cke(ddr4_c0_cke),
|
||||
.c0_ddr4_cs_n(ddr4_c0_cs_n),
|
||||
.c0_ddr4_dq(ddr4_c0_dq),
|
||||
.c0_ddr4_dqs_t(ddr4_c0_dqs_t),
|
||||
.c0_ddr4_dqs_c(ddr4_c0_dqs_c),
|
||||
.c0_ddr4_dm_dbi_n(ddr4_c0_dm_dbi_n),
|
||||
.c0_ddr4_odt(ddr4_c0_odt),
|
||||
.c0_ddr4_bg(ddr4_c0_bg),
|
||||
.c0_ddr4_reset_n(ddr4_c0_reset_n),
|
||||
.c0_ddr4_act_n(ddr4_c0_act_n),
|
||||
.c0_ddr4_ck_t(ddr4_c0_ck_t),
|
||||
.c0_ddr4_ck_c(ddr4_c0_ck_c),
|
||||
|
||||
.c0_ddr4_ui_clk(ddr_clk[0 +: 1]),
|
||||
.c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]),
|
||||
|
||||
.c0_ddr4_aresetn(!ddr_rst[0 +: 1]),
|
||||
|
||||
.c0_ddr4_s_axi_ctrl_awvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_awready(),
|
||||
.c0_ddr4_s_axi_ctrl_awaddr(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_wvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_wready(),
|
||||
.c0_ddr4_s_axi_ctrl_wdata(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_bvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_bready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_bresp(),
|
||||
.c0_ddr4_s_axi_ctrl_arvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_arready(),
|
||||
.c0_ddr4_s_axi_ctrl_araddr(31'd0),
|
||||
.c0_ddr4_s_axi_ctrl_rvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_rready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_rdata(),
|
||||
.c0_ddr4_s_axi_ctrl_rresp(),
|
||||
|
||||
.c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]),
|
||||
.c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]),
|
||||
.c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]),
|
||||
.c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]),
|
||||
.c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]),
|
||||
.c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]),
|
||||
.c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]),
|
||||
.c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH])
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign ddr4_c0_adr = {17{1'bz}};
|
||||
assign ddr4_c0_ba = {2{1'bz}};
|
||||
assign ddr4_c0_bg = {2{1'bz}};
|
||||
assign ddr4_c0_cke = 1'bz;
|
||||
assign ddr4_c0_cs_n = 1'bz;
|
||||
assign ddr4_c0_act_n = 1'bz;
|
||||
assign ddr4_c0_odt = 1'bz;
|
||||
assign ddr4_c0_reset_n = 1'b0;
|
||||
assign ddr4_c0_dq = {80{1'bz}};
|
||||
assign ddr4_c0_dqs_t = {10{1'bz}};
|
||||
assign ddr4_c0_dqs_c = {10{1'bz}};
|
||||
assign ddr4_c0_dm_dbi_n = {10{1'bz}};
|
||||
|
||||
OBUFTDS ddr4_c0_ck_obuftds_inst (
|
||||
.I(1'b0),
|
||||
.T(1'b1),
|
||||
.O(ddr4_c0_ck_t),
|
||||
.OB(ddr4_c0_ck_c)
|
||||
);
|
||||
|
||||
assign ddr_clk = 0;
|
||||
assign ddr_rst = 0;
|
||||
|
||||
assign m_axi_ddr_awready = 0;
|
||||
assign m_axi_ddr_wready = 0;
|
||||
assign m_axi_ddr_bid = 0;
|
||||
assign m_axi_ddr_bresp = 0;
|
||||
assign m_axi_ddr_bvalid = 0;
|
||||
assign m_axi_ddr_arready = 0;
|
||||
assign m_axi_ddr_rid = 0;
|
||||
assign m_axi_ddr_rdata = 0;
|
||||
assign m_axi_ddr_rresp = 0;
|
||||
assign m_axi_ddr_rlast = 0;
|
||||
assign m_axi_ddr_rvalid = 0;
|
||||
|
||||
assign ddr_status = 0;
|
||||
|
||||
end
|
||||
|
||||
assign ddr4_c0_par = 1'b0;
|
||||
assign ddr4_c0_ten = 1'b0;
|
||||
|
||||
if (DDR_ENABLE && DDR_CH > 1) begin
|
||||
|
||||
ddr4_0 ddr4_c1_inst (
|
||||
.c0_sys_clk_p(mem_clk_300mhz_1_p),
|
||||
.c0_sys_clk_n(mem_clk_300mhz_1_n),
|
||||
.sys_rst(pcie_user_reset),
|
||||
|
||||
.c0_init_calib_complete(ddr_status[1 +: 1]),
|
||||
.c0_ddr4_interrupt(),
|
||||
.dbg_clk(),
|
||||
.dbg_bus(),
|
||||
|
||||
.c0_ddr4_adr(ddr4_c1_adr),
|
||||
.c0_ddr4_ba(ddr4_c1_ba),
|
||||
.c0_ddr4_cke(ddr4_c1_cke),
|
||||
.c0_ddr4_cs_n(ddr4_c1_cs_n),
|
||||
.c0_ddr4_dq(ddr4_c1_dq),
|
||||
.c0_ddr4_dqs_t(ddr4_c1_dqs_t),
|
||||
.c0_ddr4_dqs_c(ddr4_c1_dqs_c),
|
||||
.c0_ddr4_dm_dbi_n(ddr4_c1_dm_dbi_n),
|
||||
.c0_ddr4_odt(ddr4_c1_odt),
|
||||
.c0_ddr4_bg(ddr4_c1_bg),
|
||||
.c0_ddr4_reset_n(ddr4_c1_reset_n),
|
||||
.c0_ddr4_act_n(ddr4_c1_act_n),
|
||||
.c0_ddr4_ck_t(ddr4_c1_ck_t),
|
||||
.c0_ddr4_ck_c(ddr4_c1_ck_c),
|
||||
|
||||
.c0_ddr4_ui_clk(ddr_clk[1 +: 1]),
|
||||
.c0_ddr4_ui_clk_sync_rst(ddr_rst[1 +: 1]),
|
||||
|
||||
.c0_ddr4_aresetn(!ddr_rst[1 +: 1]),
|
||||
|
||||
.c0_ddr4_s_axi_ctrl_awvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_awready(),
|
||||
.c0_ddr4_s_axi_ctrl_awaddr(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_wvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_wready(),
|
||||
.c0_ddr4_s_axi_ctrl_wdata(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_bvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_bready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_bresp(),
|
||||
.c0_ddr4_s_axi_ctrl_arvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_arready(),
|
||||
.c0_ddr4_s_axi_ctrl_araddr(31'd0),
|
||||
.c0_ddr4_s_axi_ctrl_rvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_rready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_rdata(),
|
||||
.c0_ddr4_s_axi_ctrl_rresp(),
|
||||
|
||||
.c0_ddr4_s_axi_awid(m_axi_ddr_awid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[1*8 +: 8]),
|
||||
.c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[1*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[1*2 +: 2]),
|
||||
.c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[1 +: 1]),
|
||||
.c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[1*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[1*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[1*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_awready(m_axi_ddr_awready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]),
|
||||
.c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[1*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]),
|
||||
.c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[1 +: 1]),
|
||||
.c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_wready(m_axi_ddr_wready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_bready(m_axi_ddr_bready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_bid(m_axi_ddr_bid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[1*2 +: 2]),
|
||||
.c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_arid(m_axi_ddr_arid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[1*8 +: 8]),
|
||||
.c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[1*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[1*2 +: 2]),
|
||||
.c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[1 +: 1]),
|
||||
.c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[1*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[1*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[1*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_arready(m_axi_ddr_arready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_rready(m_axi_ddr_rready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[1 +: 1]),
|
||||
.c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[1*2 +: 2]),
|
||||
.c0_ddr4_s_axi_rid(m_axi_ddr_rid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH])
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign ddr4_c1_adr = {17{1'bz}};
|
||||
assign ddr4_c1_ba = {2{1'bz}};
|
||||
assign ddr4_c1_bg = {2{1'bz}};
|
||||
assign ddr4_c1_cke = 1'bz;
|
||||
assign ddr4_c1_cs_n = 1'bz;
|
||||
assign ddr4_c1_act_n = 1'bz;
|
||||
assign ddr4_c1_odt = 1'bz;
|
||||
assign ddr4_c1_reset_n = 1'b0;
|
||||
assign ddr4_c1_dq = {80{1'bz}};
|
||||
assign ddr4_c1_dqs_t = {10{1'bz}};
|
||||
assign ddr4_c1_dqs_c = {10{1'bz}};
|
||||
assign ddr4_c1_dm_dbi_n = {10{1'bz}};
|
||||
|
||||
OBUFTDS ddr4_c1_ck_obuftds_inst (
|
||||
.I(1'b0),
|
||||
.T(1'b1),
|
||||
.O(ddr4_c1_ck_t),
|
||||
.OB(ddr4_c1_ck_c)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
assign ddr4_c1_par = 1'b0;
|
||||
assign ddr4_c1_ten = 1'b0;
|
||||
|
||||
endgenerate
|
||||
|
||||
fpga_core #(
|
||||
// FW and board IDs
|
||||
.FPGA_ID(FPGA_ID),
|
||||
@ -1831,6 +2180,16 @@ fpga_core #(
|
||||
.TX_RAM_SIZE(TX_RAM_SIZE),
|
||||
.RX_RAM_SIZE(RX_RAM_SIZE),
|
||||
|
||||
// RAM configuration
|
||||
.DDR_CH(DDR_CH),
|
||||
.DDR_ENABLE(DDR_ENABLE),
|
||||
.AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH),
|
||||
.AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH),
|
||||
.AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH),
|
||||
.AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH),
|
||||
.AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN),
|
||||
.AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST),
|
||||
|
||||
// Application block configuration
|
||||
.APP_ID(APP_ID),
|
||||
.APP_ENABLE(APP_ENABLE),
|
||||
@ -2070,6 +2429,50 @@ core_inst (
|
||||
.eeprom_i2c_sda_t(eeprom_i2c_sda_t),
|
||||
.eeprom_wp(eeprom_wp),
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
.ddr_clk(ddr_clk),
|
||||
.ddr_rst(ddr_rst),
|
||||
|
||||
.m_axi_ddr_awid(m_axi_ddr_awid),
|
||||
.m_axi_ddr_awaddr(m_axi_ddr_awaddr),
|
||||
.m_axi_ddr_awlen(m_axi_ddr_awlen),
|
||||
.m_axi_ddr_awsize(m_axi_ddr_awsize),
|
||||
.m_axi_ddr_awburst(m_axi_ddr_awburst),
|
||||
.m_axi_ddr_awlock(m_axi_ddr_awlock),
|
||||
.m_axi_ddr_awcache(m_axi_ddr_awcache),
|
||||
.m_axi_ddr_awprot(m_axi_ddr_awprot),
|
||||
.m_axi_ddr_awqos(m_axi_ddr_awqos),
|
||||
.m_axi_ddr_awvalid(m_axi_ddr_awvalid),
|
||||
.m_axi_ddr_awready(m_axi_ddr_awready),
|
||||
.m_axi_ddr_wdata(m_axi_ddr_wdata),
|
||||
.m_axi_ddr_wstrb(m_axi_ddr_wstrb),
|
||||
.m_axi_ddr_wlast(m_axi_ddr_wlast),
|
||||
.m_axi_ddr_wvalid(m_axi_ddr_wvalid),
|
||||
.m_axi_ddr_wready(m_axi_ddr_wready),
|
||||
.m_axi_ddr_bid(m_axi_ddr_bid),
|
||||
.m_axi_ddr_bresp(m_axi_ddr_bresp),
|
||||
.m_axi_ddr_bvalid(m_axi_ddr_bvalid),
|
||||
.m_axi_ddr_bready(m_axi_ddr_bready),
|
||||
.m_axi_ddr_arid(m_axi_ddr_arid),
|
||||
.m_axi_ddr_araddr(m_axi_ddr_araddr),
|
||||
.m_axi_ddr_arlen(m_axi_ddr_arlen),
|
||||
.m_axi_ddr_arsize(m_axi_ddr_arsize),
|
||||
.m_axi_ddr_arburst(m_axi_ddr_arburst),
|
||||
.m_axi_ddr_arlock(m_axi_ddr_arlock),
|
||||
.m_axi_ddr_arcache(m_axi_ddr_arcache),
|
||||
.m_axi_ddr_arprot(m_axi_ddr_arprot),
|
||||
.m_axi_ddr_arqos(m_axi_ddr_arqos),
|
||||
.m_axi_ddr_arvalid(m_axi_ddr_arvalid),
|
||||
.m_axi_ddr_arready(m_axi_ddr_arready),
|
||||
.m_axi_ddr_rid(m_axi_ddr_rid),
|
||||
.m_axi_ddr_rdata(m_axi_ddr_rdata),
|
||||
.m_axi_ddr_rresp(m_axi_ddr_rresp),
|
||||
.m_axi_ddr_rlast(m_axi_ddr_rlast),
|
||||
.m_axi_ddr_rvalid(m_axi_ddr_rvalid),
|
||||
.m_axi_ddr_rready(m_axi_ddr_rready),
|
||||
|
||||
/*
|
||||
* QSPI flash
|
||||
*/
|
||||
|
||||
@ -115,6 +115,16 @@ module fpga_core #
|
||||
parameter TX_RAM_SIZE = 131072,
|
||||
parameter RX_RAM_SIZE = 131072,
|
||||
|
||||
// RAM configuration
|
||||
parameter DDR_CH = 2,
|
||||
parameter DDR_ENABLE = 1,
|
||||
parameter AXI_DDR_DATA_WIDTH = 512,
|
||||
parameter AXI_DDR_ADDR_WIDTH = 33,
|
||||
parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8),
|
||||
parameter AXI_DDR_ID_WIDTH = 8,
|
||||
parameter AXI_DDR_MAX_BURST_LEN = 256,
|
||||
parameter AXI_DDR_NARROW_BURST = 0,
|
||||
|
||||
// Application block configuration
|
||||
parameter APP_ID = 32'h00000000,
|
||||
parameter APP_ENABLE = 0,
|
||||
@ -368,6 +378,52 @@ module fpga_core #
|
||||
output wire eeprom_i2c_sda_t,
|
||||
output wire eeprom_wp,
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
input wire [DDR_CH-1:0] ddr_clk,
|
||||
input wire [DDR_CH-1:0] ddr_rst,
|
||||
|
||||
output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid,
|
||||
output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr,
|
||||
output wire [DDR_CH*8-1:0] m_axi_ddr_awlen,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_awsize,
|
||||
output wire [DDR_CH*2-1:0] m_axi_ddr_awburst,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_awlock,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_awcache,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_awprot,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_awqos,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_awvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_awready,
|
||||
output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata,
|
||||
output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_wlast,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_wvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_wready,
|
||||
input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid,
|
||||
input wire [DDR_CH*2-1:0] m_axi_ddr_bresp,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_bvalid,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_bready,
|
||||
output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid,
|
||||
output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr,
|
||||
output wire [DDR_CH*8-1:0] m_axi_ddr_arlen,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_arsize,
|
||||
output wire [DDR_CH*2-1:0] m_axi_ddr_arburst,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_arlock,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_arcache,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_arprot,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_arqos,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_arvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_arready,
|
||||
input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid,
|
||||
input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata,
|
||||
input wire [DDR_CH*2-1:0] m_axi_ddr_rresp,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_rlast,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_rvalid,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_rready,
|
||||
|
||||
input wire [DDR_CH-1:0] ddr_status,
|
||||
|
||||
/*
|
||||
* QSPI flash
|
||||
*/
|
||||
@ -895,6 +951,25 @@ mqnic_core_pcie_us #(
|
||||
.TX_RAM_SIZE(TX_RAM_SIZE),
|
||||
.RX_RAM_SIZE(RX_RAM_SIZE),
|
||||
|
||||
// RAM configuration
|
||||
.DDR_CH(DDR_CH),
|
||||
.DDR_ENABLE(DDR_ENABLE),
|
||||
.DDR_GROUP_SIZE(1),
|
||||
.AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH),
|
||||
.AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH),
|
||||
.AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH),
|
||||
.AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH),
|
||||
.AXI_DDR_AWUSER_ENABLE(0),
|
||||
.AXI_DDR_WUSER_ENABLE(0),
|
||||
.AXI_DDR_BUSER_ENABLE(0),
|
||||
.AXI_DDR_ARUSER_ENABLE(0),
|
||||
.AXI_DDR_RUSER_ENABLE(0),
|
||||
.AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN),
|
||||
.AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST),
|
||||
.AXI_DDR_FIXED_BURST(0),
|
||||
.AXI_DDR_WRAP_BURST(1),
|
||||
.HBM_ENABLE(0),
|
||||
|
||||
// Application block configuration
|
||||
.APP_ID(APP_ID),
|
||||
.APP_ENABLE(APP_ENABLE),
|
||||
@ -1172,6 +1247,108 @@ core_inst (
|
||||
|
||||
.eth_rx_status(eth_rx_status),
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
.ddr_clk(ddr_clk),
|
||||
.ddr_rst(ddr_rst),
|
||||
|
||||
.m_axi_ddr_awid(m_axi_ddr_awid),
|
||||
.m_axi_ddr_awaddr(m_axi_ddr_awaddr),
|
||||
.m_axi_ddr_awlen(m_axi_ddr_awlen),
|
||||
.m_axi_ddr_awsize(m_axi_ddr_awsize),
|
||||
.m_axi_ddr_awburst(m_axi_ddr_awburst),
|
||||
.m_axi_ddr_awlock(m_axi_ddr_awlock),
|
||||
.m_axi_ddr_awcache(m_axi_ddr_awcache),
|
||||
.m_axi_ddr_awprot(m_axi_ddr_awprot),
|
||||
.m_axi_ddr_awqos(m_axi_ddr_awqos),
|
||||
.m_axi_ddr_awuser(),
|
||||
.m_axi_ddr_awvalid(m_axi_ddr_awvalid),
|
||||
.m_axi_ddr_awready(m_axi_ddr_awready),
|
||||
.m_axi_ddr_wdata(m_axi_ddr_wdata),
|
||||
.m_axi_ddr_wstrb(m_axi_ddr_wstrb),
|
||||
.m_axi_ddr_wlast(m_axi_ddr_wlast),
|
||||
.m_axi_ddr_wuser(),
|
||||
.m_axi_ddr_wvalid(m_axi_ddr_wvalid),
|
||||
.m_axi_ddr_wready(m_axi_ddr_wready),
|
||||
.m_axi_ddr_bid(m_axi_ddr_bid),
|
||||
.m_axi_ddr_bresp(m_axi_ddr_bresp),
|
||||
.m_axi_ddr_buser(0),
|
||||
.m_axi_ddr_bvalid(m_axi_ddr_bvalid),
|
||||
.m_axi_ddr_bready(m_axi_ddr_bready),
|
||||
.m_axi_ddr_arid(m_axi_ddr_arid),
|
||||
.m_axi_ddr_araddr(m_axi_ddr_araddr),
|
||||
.m_axi_ddr_arlen(m_axi_ddr_arlen),
|
||||
.m_axi_ddr_arsize(m_axi_ddr_arsize),
|
||||
.m_axi_ddr_arburst(m_axi_ddr_arburst),
|
||||
.m_axi_ddr_arlock(m_axi_ddr_arlock),
|
||||
.m_axi_ddr_arcache(m_axi_ddr_arcache),
|
||||
.m_axi_ddr_arprot(m_axi_ddr_arprot),
|
||||
.m_axi_ddr_arqos(m_axi_ddr_arqos),
|
||||
.m_axi_ddr_aruser(),
|
||||
.m_axi_ddr_arvalid(m_axi_ddr_arvalid),
|
||||
.m_axi_ddr_arready(m_axi_ddr_arready),
|
||||
.m_axi_ddr_rid(m_axi_ddr_rid),
|
||||
.m_axi_ddr_rdata(m_axi_ddr_rdata),
|
||||
.m_axi_ddr_rresp(m_axi_ddr_rresp),
|
||||
.m_axi_ddr_rlast(m_axi_ddr_rlast),
|
||||
.m_axi_ddr_ruser(0),
|
||||
.m_axi_ddr_rvalid(m_axi_ddr_rvalid),
|
||||
.m_axi_ddr_rready(m_axi_ddr_rready),
|
||||
|
||||
.ddr_status(ddr_status),
|
||||
|
||||
/*
|
||||
* HBM
|
||||
*/
|
||||
.hbm_clk(0),
|
||||
.hbm_rst(0),
|
||||
|
||||
.m_axi_hbm_awid(),
|
||||
.m_axi_hbm_awaddr(),
|
||||
.m_axi_hbm_awlen(),
|
||||
.m_axi_hbm_awsize(),
|
||||
.m_axi_hbm_awburst(),
|
||||
.m_axi_hbm_awlock(),
|
||||
.m_axi_hbm_awcache(),
|
||||
.m_axi_hbm_awprot(),
|
||||
.m_axi_hbm_awqos(),
|
||||
.m_axi_hbm_awuser(),
|
||||
.m_axi_hbm_awvalid(),
|
||||
.m_axi_hbm_awready(0),
|
||||
.m_axi_hbm_wdata(),
|
||||
.m_axi_hbm_wstrb(),
|
||||
.m_axi_hbm_wlast(),
|
||||
.m_axi_hbm_wuser(),
|
||||
.m_axi_hbm_wvalid(),
|
||||
.m_axi_hbm_wready(0),
|
||||
.m_axi_hbm_bid(0),
|
||||
.m_axi_hbm_bresp(0),
|
||||
.m_axi_hbm_buser(0),
|
||||
.m_axi_hbm_bvalid(0),
|
||||
.m_axi_hbm_bready(),
|
||||
.m_axi_hbm_arid(),
|
||||
.m_axi_hbm_araddr(),
|
||||
.m_axi_hbm_arlen(),
|
||||
.m_axi_hbm_arsize(),
|
||||
.m_axi_hbm_arburst(),
|
||||
.m_axi_hbm_arlock(),
|
||||
.m_axi_hbm_arcache(),
|
||||
.m_axi_hbm_arprot(),
|
||||
.m_axi_hbm_arqos(),
|
||||
.m_axi_hbm_aruser(),
|
||||
.m_axi_hbm_arvalid(),
|
||||
.m_axi_hbm_arready(0),
|
||||
.m_axi_hbm_rid(0),
|
||||
.m_axi_hbm_rdata(0),
|
||||
.m_axi_hbm_rresp(0),
|
||||
.m_axi_hbm_rlast(0),
|
||||
.m_axi_hbm_ruser(0),
|
||||
.m_axi_hbm_rvalid(0),
|
||||
.m_axi_hbm_rready(),
|
||||
|
||||
.hbm_status(0),
|
||||
|
||||
/*
|
||||
* Statistics input
|
||||
*/
|
||||
|
||||
@ -4,8 +4,9 @@
|
||||
|
||||
This design targets the Alpha Data ADM-PCIE-9V3 FPGA board.
|
||||
|
||||
FPGA: xcvu3p-ffvc1517-2-i
|
||||
PHY: 25G BASE-R PHY IP core and internal GTY transceiver
|
||||
* FPGA: xcvu3p-ffvc1517-2-i
|
||||
* PHY: 25G BASE-R PHY IP core and internal GTY transceiver
|
||||
* RAM: 16 GB DDR4 2400 (2x 1G x72)
|
||||
|
||||
## How to build
|
||||
|
||||
|
||||
@ -17,6 +17,16 @@ set_property -dict {LOC AP26 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports
|
||||
set_property -dict {LOC AP27 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports clk_300mhz_n]
|
||||
create_clock -period 3.333 -name clk_300mhz [get_ports clk_300mhz_p]
|
||||
|
||||
# 300 MHz memory clock (C0)
|
||||
set_property -dict {LOC G31 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports mem_clk_300mhz_0_p]
|
||||
set_property -dict {LOC G32 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports mem_clk_300mhz_0_n]
|
||||
# create_clock -period 3.333 -name mem_clk_300mhz_0 [get_ports mem_clk_300mhz_0_p]
|
||||
|
||||
# 300 MHz memory clock (C1)
|
||||
set_property -dict {LOC AN25 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports mem_clk_300mhz_1_p]
|
||||
set_property -dict {LOC AN26 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports mem_clk_300mhz_1_n]
|
||||
# create_clock -period 3.333 -name mem_clk_300mhz_1 [get_ports mem_clk_300mhz_1_p]
|
||||
|
||||
# LEDs
|
||||
set_property -dict {LOC AT27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {user_led_g[0]}]
|
||||
set_property -dict {LOC AU27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {user_led_g[1]}]
|
||||
@ -193,6 +203,282 @@ create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_1_p]
|
||||
set_false_path -from [get_ports {perst_0}]
|
||||
set_input_delay 0 [get_ports {perst_0}]
|
||||
|
||||
# DDR4 C0
|
||||
# 5x K4A8G085WB-RC
|
||||
set_property -dict {LOC F9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}]
|
||||
set_property -dict {LOC G9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}]
|
||||
set_property -dict {LOC G11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}]
|
||||
set_property -dict {LOC D11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}]
|
||||
set_property -dict {LOC E12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}]
|
||||
set_property -dict {LOC G10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}]
|
||||
set_property -dict {LOC F10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}]
|
||||
set_property -dict {LOC J9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}]
|
||||
set_property -dict {LOC J8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}]
|
||||
set_property -dict {LOC F12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}]
|
||||
set_property -dict {LOC D9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}]
|
||||
set_property -dict {LOC H11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}]
|
||||
set_property -dict {LOC E8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}]
|
||||
set_property -dict {LOC J11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}]
|
||||
set_property -dict {LOC C9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}]
|
||||
set_property -dict {LOC B11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}]
|
||||
set_property -dict {LOC K12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}]
|
||||
# set_property -dict {LOC H9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[17]}]
|
||||
set_property -dict {LOC F8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}]
|
||||
set_property -dict {LOC H8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}]
|
||||
set_property -dict {LOC D10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}]
|
||||
set_property -dict {LOC E11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}]
|
||||
# set_property -dict {LOC B10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_c[0]}]
|
||||
# set_property -dict {LOC C11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_c[1]}]
|
||||
# set_property -dict {LOC A9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_c[2]}]
|
||||
set_property -dict {LOC H12 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t}]
|
||||
set_property -dict {LOC G12 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c}]
|
||||
set_property -dict {LOC B9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke}]
|
||||
set_property -dict {LOC E10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n}]
|
||||
set_property -dict {LOC C12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}]
|
||||
set_property -dict {LOC A10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt}]
|
||||
set_property -dict {LOC G7 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}]
|
||||
set_property -dict {LOC F7 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_reset_n}]
|
||||
set_property -dict {LOC H7 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_alert_n}]
|
||||
set_property -dict {LOC J10 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_ten}]
|
||||
|
||||
set_property -dict {LOC L10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}]
|
||||
set_property -dict {LOC L9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}]
|
||||
set_property -dict {LOC N9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}]
|
||||
set_property -dict {LOC M9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}]
|
||||
set_property -dict {LOC M10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}]
|
||||
set_property -dict {LOC K11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}]
|
||||
set_property -dict {LOC M11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}]
|
||||
set_property -dict {LOC K10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}]
|
||||
set_property -dict {LOC L17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}]
|
||||
set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}]
|
||||
set_property -dict {LOC M15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}]
|
||||
set_property -dict {LOC M17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}]
|
||||
set_property -dict {LOC M14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}]
|
||||
set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}]
|
||||
set_property -dict {LOC N16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}]
|
||||
set_property -dict {LOC N17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}]
|
||||
set_property -dict {LOC F15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}]
|
||||
set_property -dict {LOC E16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}]
|
||||
set_property -dict {LOC F14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}]
|
||||
set_property -dict {LOC E17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}]
|
||||
set_property -dict {LOC G16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}]
|
||||
set_property -dict {LOC F17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}]
|
||||
set_property -dict {LOC E15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}]
|
||||
set_property -dict {LOC G17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}]
|
||||
set_property -dict {LOC A17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}]
|
||||
set_property -dict {LOC C16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}]
|
||||
set_property -dict {LOC B16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}]
|
||||
set_property -dict {LOC A14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}]
|
||||
set_property -dict {LOC B17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}]
|
||||
set_property -dict {LOC B14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}]
|
||||
set_property -dict {LOC D16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}]
|
||||
set_property -dict {LOC D15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}]
|
||||
set_property -dict {LOC F18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}]
|
||||
set_property -dict {LOC F20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}]
|
||||
set_property -dict {LOC F19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}]
|
||||
set_property -dict {LOC D21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}]
|
||||
set_property -dict {LOC E18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}]
|
||||
set_property -dict {LOC G19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}]
|
||||
set_property -dict {LOC E21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}]
|
||||
set_property -dict {LOC G20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}]
|
||||
set_property -dict {LOC D18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}]
|
||||
set_property -dict {LOC B22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}]
|
||||
set_property -dict {LOC A19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}]
|
||||
set_property -dict {LOC A18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}]
|
||||
set_property -dict {LOC C19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}]
|
||||
set_property -dict {LOC B19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}]
|
||||
set_property -dict {LOC A22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}]
|
||||
set_property -dict {LOC C18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}]
|
||||
set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}]
|
||||
set_property -dict {LOC J20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}]
|
||||
set_property -dict {LOC H19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}]
|
||||
set_property -dict {LOC J19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}]
|
||||
set_property -dict {LOC H18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}]
|
||||
set_property -dict {LOC J18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}]
|
||||
set_property -dict {LOC G21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}]
|
||||
set_property -dict {LOC K18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}]
|
||||
set_property -dict {LOC L20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}]
|
||||
set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}]
|
||||
set_property -dict {LOC N19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}]
|
||||
set_property -dict {LOC M21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}]
|
||||
set_property -dict {LOC M19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}]
|
||||
set_property -dict {LOC M22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}]
|
||||
set_property -dict {LOC L19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}]
|
||||
set_property -dict {LOC M20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}]
|
||||
set_property -dict {LOC H16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}]
|
||||
set_property -dict {LOC K15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}]
|
||||
set_property -dict {LOC J16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}]
|
||||
set_property -dict {LOC J14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}]
|
||||
set_property -dict {LOC K13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}]
|
||||
set_property -dict {LOC L13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}]
|
||||
set_property -dict {LOC H14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}]
|
||||
set_property -dict {LOC J15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}]
|
||||
set_property -dict {LOC M12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}]
|
||||
set_property -dict {LOC L12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}]
|
||||
set_property -dict {LOC L15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}]
|
||||
set_property -dict {LOC L14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}]
|
||||
set_property -dict {LOC F13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}]
|
||||
set_property -dict {LOC E13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}]
|
||||
set_property -dict {LOC B15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}]
|
||||
set_property -dict {LOC A15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}]
|
||||
set_property -dict {LOC F22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}]
|
||||
set_property -dict {LOC E22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}]
|
||||
set_property -dict {LOC C21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}]
|
||||
set_property -dict {LOC B21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}]
|
||||
set_property -dict {LOC K21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}]
|
||||
set_property -dict {LOC K20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}]
|
||||
set_property -dict {LOC L22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}]
|
||||
set_property -dict {LOC K22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}]
|
||||
set_property -dict {LOC K17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}]
|
||||
set_property -dict {LOC K16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}]
|
||||
set_property -dict {LOC N12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[0]}]
|
||||
set_property -dict {LOC P14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[1]}]
|
||||
set_property -dict {LOC G15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[2]}]
|
||||
set_property -dict {LOC D14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[3]}]
|
||||
set_property -dict {LOC E20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[4]}]
|
||||
set_property -dict {LOC B20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[5]}]
|
||||
set_property -dict {LOC H22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[6]}]
|
||||
set_property -dict {LOC N22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[7]}]
|
||||
set_property -dict {LOC J13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[8]}]
|
||||
|
||||
# DDR4 C1
|
||||
# 5x K4A8G085WB-RC
|
||||
set_property -dict {LOC AN9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}]
|
||||
set_property -dict {LOC AM9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}]
|
||||
set_property -dict {LOC AP11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}]
|
||||
set_property -dict {LOC AU9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}]
|
||||
set_property -dict {LOC AT10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}]
|
||||
set_property -dict {LOC AL12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}]
|
||||
set_property -dict {LOC AM12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}]
|
||||
set_property -dict {LOC AM10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}]
|
||||
set_property -dict {LOC AL11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}]
|
||||
set_property -dict {LOC AP7 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}]
|
||||
set_property -dict {LOC AR8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}]
|
||||
set_property -dict {LOC AL10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}]
|
||||
set_property -dict {LOC AP8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}]
|
||||
set_property -dict {LOC AK11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}]
|
||||
set_property -dict {LOC AP9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}]
|
||||
set_property -dict {LOC AV10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}]
|
||||
set_property -dict {LOC AT11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}]
|
||||
# set_property -dict {LOC AL8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[17]}]
|
||||
set_property -dict {LOC AN11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}]
|
||||
set_property -dict {LOC AR9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}]
|
||||
set_property -dict {LOC AP12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}]
|
||||
set_property -dict {LOC AN10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}]
|
||||
# set_property -dict {LOC AW13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_c[0]}]
|
||||
# set_property -dict {LOC AU10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_c[1]}]
|
||||
# set_property -dict {LOC AW11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_c[2]}]
|
||||
set_property -dict {LOC AM7 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t}]
|
||||
set_property -dict {LOC AN7 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c}]
|
||||
set_property -dict {LOC AU12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke}]
|
||||
set_property -dict {LOC AT12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n}]
|
||||
set_property -dict {LOC AV9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}]
|
||||
set_property -dict {LOC AR11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt}]
|
||||
set_property -dict {LOC AM8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}]
|
||||
set_property -dict {LOC AN12 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}]
|
||||
set_property -dict {LOC AR10 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_alert_n}]
|
||||
set_property -dict {LOC AV11 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_ten}]
|
||||
|
||||
set_property -dict {LOC AK9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}]
|
||||
set_property -dict {LOC AK10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}]
|
||||
set_property -dict {LOC AH10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}]
|
||||
set_property -dict {LOC AJ11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}]
|
||||
set_property -dict {LOC AJ9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}]
|
||||
set_property -dict {LOC AH12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}]
|
||||
set_property -dict {LOC AG10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}]
|
||||
set_property -dict {LOC AJ12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}]
|
||||
set_property -dict {LOC AM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}]
|
||||
set_property -dict {LOC AN14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}]
|
||||
set_property -dict {LOC AL13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}]
|
||||
set_property -dict {LOC AM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}]
|
||||
set_property -dict {LOC AL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}]
|
||||
set_property -dict {LOC AM17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}]
|
||||
set_property -dict {LOC AL17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}]
|
||||
set_property -dict {LOC AM13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}]
|
||||
set_property -dict {LOC AR15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}]
|
||||
set_property -dict {LOC AP14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}]
|
||||
set_property -dict {LOC AT15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}]
|
||||
set_property -dict {LOC AR14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}]
|
||||
set_property -dict {LOC AP17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}]
|
||||
set_property -dict {LOC AN16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}]
|
||||
set_property -dict {LOC AN17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}]
|
||||
set_property -dict {LOC AN15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}]
|
||||
set_property -dict {LOC AU15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}]
|
||||
set_property -dict {LOC AT17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}]
|
||||
set_property -dict {LOC AV15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}]
|
||||
set_property -dict {LOC AT16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}]
|
||||
set_property -dict {LOC AV14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}]
|
||||
set_property -dict {LOC AW17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}]
|
||||
set_property -dict {LOC AW14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}]
|
||||
set_property -dict {LOC AW18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}]
|
||||
set_property -dict {LOC AP19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}]
|
||||
set_property -dict {LOC AT20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}]
|
||||
set_property -dict {LOC AN21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}]
|
||||
set_property -dict {LOC AR19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}]
|
||||
set_property -dict {LOC AN20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}]
|
||||
set_property -dict {LOC AR18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}]
|
||||
set_property -dict {LOC AR20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}]
|
||||
set_property -dict {LOC AP18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}]
|
||||
set_property -dict {LOC AW19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}]
|
||||
set_property -dict {LOC AU22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}]
|
||||
set_property -dict {LOC AV19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}]
|
||||
set_property -dict {LOC AW22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}]
|
||||
set_property -dict {LOC AU18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}]
|
||||
set_property -dict {LOC AT22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}]
|
||||
set_property -dict {LOC AW21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}]
|
||||
set_property -dict {LOC AU19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}]
|
||||
set_property -dict {LOC AH19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}]
|
||||
set_property -dict {LOC AJ22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}]
|
||||
set_property -dict {LOC AF21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}]
|
||||
set_property -dict {LOC AH22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}]
|
||||
set_property -dict {LOC AF20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}]
|
||||
set_property -dict {LOC AJ19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}]
|
||||
set_property -dict {LOC AH21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}]
|
||||
set_property -dict {LOC AJ21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}]
|
||||
set_property -dict {LOC AM19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}]
|
||||
set_property -dict {LOC AK20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}]
|
||||
set_property -dict {LOC AM22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}]
|
||||
set_property -dict {LOC AL22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}]
|
||||
set_property -dict {LOC AM20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}]
|
||||
set_property -dict {LOC AK19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}]
|
||||
set_property -dict {LOC AN19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}]
|
||||
set_property -dict {LOC AL20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}]
|
||||
set_property -dict {LOC AF15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}]
|
||||
set_property -dict {LOC AJ17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}]
|
||||
set_property -dict {LOC AH17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}]
|
||||
set_property -dict {LOC AJ14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}]
|
||||
set_property -dict {LOC AG15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}]
|
||||
set_property -dict {LOC AJ13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}]
|
||||
set_property -dict {LOC AG17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}]
|
||||
set_property -dict {LOC AJ16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}]
|
||||
set_property -dict {LOC AG9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}]
|
||||
set_property -dict {LOC AH9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}]
|
||||
set_property -dict {LOC AK16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}]
|
||||
set_property -dict {LOC AL16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}]
|
||||
set_property -dict {LOC AR13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}]
|
||||
set_property -dict {LOC AT13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}]
|
||||
set_property -dict {LOC AU17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}]
|
||||
set_property -dict {LOC AV17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}]
|
||||
set_property -dict {LOC AN22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}]
|
||||
set_property -dict {LOC AP22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}]
|
||||
set_property -dict {LOC AV22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}]
|
||||
set_property -dict {LOC AV21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}]
|
||||
set_property -dict {LOC AG20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}]
|
||||
set_property -dict {LOC AH20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}]
|
||||
set_property -dict {LOC AK21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}]
|
||||
set_property -dict {LOC AL21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}]
|
||||
set_property -dict {LOC AH16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}]
|
||||
set_property -dict {LOC AH15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}]
|
||||
set_property -dict {LOC AG12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[0]}]
|
||||
set_property -dict {LOC AK15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[1]}]
|
||||
set_property -dict {LOC AP16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[2]}]
|
||||
set_property -dict {LOC AV16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[3]}]
|
||||
set_property -dict {LOC AP21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[4]}]
|
||||
set_property -dict {LOC AU20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[5]}]
|
||||
set_property -dict {LOC AG19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[6]}]
|
||||
set_property -dict {LOC AL18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[7]}]
|
||||
set_property -dict {LOC AG14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[8]}]
|
||||
|
||||
# QSPI flash
|
||||
set_property -dict {LOC AF30 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[0]}]
|
||||
set_property -dict {LOC AG30 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[1]}]
|
||||
|
||||
@ -139,6 +139,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
|
||||
# IP
|
||||
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
|
||||
IP_TCL_FILES += ip/eth_xcvr_gty.tcl
|
||||
IP_TCL_FILES += ip/ddr4_0.tcl
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
@ -148,6 +148,12 @@ dict set params MAX_TX_SIZE "9214"
|
||||
dict set params MAX_RX_SIZE "9214"
|
||||
dict set params TX_RAM_SIZE "32768"
|
||||
dict set params RX_RAM_SIZE "131072"
|
||||
|
||||
# RAM configuration
|
||||
dict set params DDR_CH "2"
|
||||
dict set params DDR_ENABLE "1"
|
||||
dict set params AXI_DDR_ID_WIDTH "8"
|
||||
dict set params AXI_DDR_MAX_BURST_LEN "256"
|
||||
|
||||
# Application block configuration
|
||||
dict set params APP_ID "32'h00000000"
|
||||
@ -200,6 +206,19 @@ dict set params STAT_PCIE_ENABLE "1"
|
||||
dict set params STAT_INC_WIDTH "24"
|
||||
dict set params STAT_ID_WIDTH "12"
|
||||
|
||||
# DDR4 MIG settings
|
||||
if {[dict get $params DDR_ENABLE]} {
|
||||
set ddr4 [get_ips ddr4_0]
|
||||
|
||||
# set AXI ID width
|
||||
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
|
||||
|
||||
# extract AXI configuration
|
||||
dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4]
|
||||
dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4]
|
||||
dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1]
|
||||
}
|
||||
|
||||
# PCIe IP core settings
|
||||
set pcie [get_ips pcie4_uscale_plus_0]
|
||||
|
||||
|
||||
@ -139,6 +139,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
|
||||
# IP
|
||||
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
|
||||
IP_TCL_FILES += ip/eth_xcvr_gty.tcl
|
||||
IP_TCL_FILES += ip/ddr4_0.tcl
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
@ -148,6 +148,12 @@ dict set params MAX_TX_SIZE "9214"
|
||||
dict set params MAX_RX_SIZE "9214"
|
||||
dict set params TX_RAM_SIZE "32768"
|
||||
dict set params RX_RAM_SIZE "32768"
|
||||
|
||||
# RAM configuration
|
||||
dict set params DDR_CH "2"
|
||||
dict set params DDR_ENABLE "1"
|
||||
dict set params AXI_DDR_ID_WIDTH "8"
|
||||
dict set params AXI_DDR_MAX_BURST_LEN "256"
|
||||
|
||||
# Application block configuration
|
||||
dict set params APP_ID "32'h00000000"
|
||||
@ -200,6 +206,19 @@ dict set params STAT_PCIE_ENABLE "1"
|
||||
dict set params STAT_INC_WIDTH "24"
|
||||
dict set params STAT_ID_WIDTH "12"
|
||||
|
||||
# DDR4 MIG settings
|
||||
if {[dict get $params DDR_ENABLE]} {
|
||||
set ddr4 [get_ips ddr4_0]
|
||||
|
||||
# set AXI ID width
|
||||
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
|
||||
|
||||
# extract AXI configuration
|
||||
dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4]
|
||||
dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4]
|
||||
dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1]
|
||||
}
|
||||
|
||||
# PCIe IP core settings
|
||||
set pcie [get_ips pcie4_uscale_plus_0]
|
||||
|
||||
|
||||
@ -140,6 +140,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
|
||||
# IP
|
||||
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
|
||||
IP_TCL_FILES += ip/eth_xcvr_gty.tcl
|
||||
IP_TCL_FILES += ip/ddr4_0.tcl
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
@ -148,6 +148,12 @@ dict set params MAX_TX_SIZE "9214"
|
||||
dict set params MAX_RX_SIZE "9214"
|
||||
dict set params TX_RAM_SIZE "32768"
|
||||
dict set params RX_RAM_SIZE "131072"
|
||||
|
||||
# RAM configuration
|
||||
dict set params DDR_CH "2"
|
||||
dict set params DDR_ENABLE "1"
|
||||
dict set params AXI_DDR_ID_WIDTH "8"
|
||||
dict set params AXI_DDR_MAX_BURST_LEN "256"
|
||||
|
||||
# Application block configuration
|
||||
dict set params APP_ID "32'h00000000"
|
||||
@ -200,6 +206,19 @@ dict set params STAT_PCIE_ENABLE "1"
|
||||
dict set params STAT_INC_WIDTH "24"
|
||||
dict set params STAT_ID_WIDTH "12"
|
||||
|
||||
# DDR4 MIG settings
|
||||
if {[dict get $params DDR_ENABLE]} {
|
||||
set ddr4 [get_ips ddr4_0]
|
||||
|
||||
# set AXI ID width
|
||||
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
|
||||
|
||||
# extract AXI configuration
|
||||
dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4]
|
||||
dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4]
|
||||
dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1]
|
||||
}
|
||||
|
||||
# PCIe IP core settings
|
||||
set pcie [get_ips pcie4_uscale_plus_0]
|
||||
|
||||
|
||||
@ -0,0 +1,5 @@
|
||||
Part type,Part name,Rank,StackHeight,CA Mirror,Data mask,Address width,Row width,Column width,Bank width,Bank group width,CS width,CKE width,ODT width,CK width,Memory speed grade,Memory density,Component density,Memory device width,Memory component width,Data bits per strobe,IO Voltages,Data widths,Min period,Max period,tCKE,tFAW,tFAW_dlr,tMRD,tRAS,tRCD,tREFI,tRFC,tRFC_dlr,tRP,tRRD_S,tRRD_L,tRRD_dlr,tRTP,tWR,tWTR_S,tWTR_L,tXPR,tZQCS,tZQINIT,tCCD_3ds,cas latency,cas write latency,burst length,RTT (nominal) - ODT
|
||||
Components,CUSTOM_MT40A1G8PM-083E,1,1,0,1,17,16,10,2,2,1,1,1,1,083E,8Gb,8Gb,8,8,8,1.2V,"72",833,1600,5000 ps,21000 ps,0,8 tck,32000 ps,13320 ps,7800000 ps,350000 ps,0,13320 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,"17","12",8,RZQ/6
|
||||
Components,CUSTOM_DBI_RD_MT40A1G8PM-083E,1,1,0,1,17,16,10,2,2,1,1,1,1,083E,8Gb,8Gb,8,8,8,1.2V,"72",833,1600,5000 ps,21000 ps,0,8 tck,32000 ps,13320 ps,7800000 ps,350000 ps,0,13320 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,"20","12",8,RZQ/6
|
||||
Components,CUSTOM_K4A8G085WB-RC,1,1,0,1,17,16,10,2,2,1,1,1,1,083,8Gb,8Gb,8,8,8,1.2V,"72",833,1600,5000 ps,21000 ps,0,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,0,14160 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,"17","12",8,RZQ/6
|
||||
Components,CUSTOM_DBI_RD_K4A8G085WB-RC,1,1,0,1,17,16,10,2,2,1,1,1,1,083,8Gb,8Gb,8,8,8,1.2V,"72",833,1600,5000 ps,21000 ps,0,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,0,14160 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,"20","12",8,RZQ/6
|
||||
|
23
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/ip/ddr4_0.tcl
Normal file
23
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/ip/ddr4_0.tcl
Normal file
@ -0,0 +1,23 @@
|
||||
|
||||
create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0
|
||||
|
||||
set path [file dirname [file normalize [info script]]]
|
||||
|
||||
set_property -dict [list \
|
||||
CONFIG.C0.DDR4_AxiSelection {true} \
|
||||
CONFIG.C0.DDR4_AxiDataWidth {512} \
|
||||
CONFIG.C0.DDR4_AxiIDWidth {8} \
|
||||
CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \
|
||||
CONFIG.C0.DDR4_TimePeriod {833} \
|
||||
CONFIG.C0.DDR4_InputClockPeriod {3332} \
|
||||
CONFIG.C0.DDR4_CustomParts "$path/custom_parts_2400.csv" \
|
||||
CONFIG.C0.DDR4_isCustom {true} \
|
||||
CONFIG.C0.DDR4_MemoryType {Components} \
|
||||
CONFIG.C0.DDR4_MemoryPart {CUSTOM_K4A8G085WB-RC} \
|
||||
CONFIG.C0.DDR4_DataWidth {72} \
|
||||
CONFIG.C0.DDR4_DataMask {NO_DM_NO_DBI} \
|
||||
CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \
|
||||
CONFIG.C0.DDR4_CasLatency {17} \
|
||||
CONFIG.C0.DDR4_CasWriteLatency {12} \
|
||||
CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV}
|
||||
] [get_ips ddr4_0]
|
||||
@ -112,6 +112,15 @@ module fpga #
|
||||
parameter TX_RAM_SIZE = 32768,
|
||||
parameter RX_RAM_SIZE = 32768,
|
||||
|
||||
// RAM configuration
|
||||
parameter DDR_CH = 2,
|
||||
parameter DDR_ENABLE = 1,
|
||||
parameter AXI_DDR_DATA_WIDTH = 512,
|
||||
parameter AXI_DDR_ADDR_WIDTH = 33,
|
||||
parameter AXI_DDR_ID_WIDTH = 8,
|
||||
parameter AXI_DDR_MAX_BURST_LEN = 256,
|
||||
parameter AXI_DDR_NARROW_BURST = 0,
|
||||
|
||||
// Application block configuration
|
||||
parameter APP_ID = 32'h00000000,
|
||||
parameter APP_ENABLE = 0,
|
||||
@ -182,6 +191,10 @@ module fpga #
|
||||
*/
|
||||
input wire clk_300mhz_p,
|
||||
input wire clk_300mhz_n,
|
||||
input wire mem_clk_300mhz_0_p,
|
||||
input wire mem_clk_300mhz_0_n,
|
||||
input wire mem_clk_300mhz_1_p,
|
||||
input wire mem_clk_300mhz_1_n,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
@ -257,6 +270,45 @@ module fpga #
|
||||
inout wire eeprom_i2c_sda,
|
||||
output wire eeprom_wp,
|
||||
|
||||
/*
|
||||
* DDR4
|
||||
*/
|
||||
output wire [16:0] ddr4_c0_adr,
|
||||
output wire [1:0] ddr4_c0_ba,
|
||||
output wire [1:0] ddr4_c0_bg,
|
||||
output wire ddr4_c0_ck_t,
|
||||
output wire ddr4_c0_ck_c,
|
||||
output wire ddr4_c0_cke,
|
||||
output wire ddr4_c0_cs_n,
|
||||
output wire ddr4_c0_act_n,
|
||||
output wire ddr4_c0_odt,
|
||||
output wire ddr4_c0_par,
|
||||
input wire ddr4_c0_alert_n,
|
||||
output wire ddr4_c0_reset_n,
|
||||
output wire ddr4_c0_ten,
|
||||
inout wire [71:0] ddr4_c0_dq,
|
||||
inout wire [8:0] ddr4_c0_dqs_t,
|
||||
inout wire [8:0] ddr4_c0_dqs_c,
|
||||
inout wire [8:0] ddr4_c0_dm_dbi_n,
|
||||
|
||||
output wire [16:0] ddr4_c1_adr,
|
||||
output wire [1:0] ddr4_c1_ba,
|
||||
output wire [1:0] ddr4_c1_bg,
|
||||
output wire ddr4_c1_ck_t,
|
||||
output wire ddr4_c1_ck_c,
|
||||
output wire ddr4_c1_cke,
|
||||
output wire ddr4_c1_cs_n,
|
||||
output wire ddr4_c1_act_n,
|
||||
output wire ddr4_c1_odt,
|
||||
output wire ddr4_c1_par,
|
||||
input wire ddr4_c1_alert_n,
|
||||
output wire ddr4_c1_reset_n,
|
||||
output wire ddr4_c1_ten,
|
||||
inout wire [71:0] ddr4_c1_dq,
|
||||
inout wire [8:0] ddr4_c1_dqs_t,
|
||||
inout wire [8:0] ddr4_c1_dqs_c,
|
||||
inout wire [8:0] ddr4_c1_dm_dbi_n,
|
||||
|
||||
/*
|
||||
* QSPI
|
||||
*/
|
||||
@ -275,6 +327,9 @@ parameter IF_PTP_PERIOD_FNS = 16'h8F5C;
|
||||
// Interface configuration
|
||||
parameter TX_TAG_WIDTH = 16;
|
||||
|
||||
// RAM configuration
|
||||
parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8);
|
||||
|
||||
// Ethernet interface configuration
|
||||
parameter XGMII_DATA_WIDTH = 64;
|
||||
parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8;
|
||||
@ -1357,6 +1412,301 @@ assign ptp_clk = qsfp_0_mgt_refclk_bufg;
|
||||
assign ptp_rst = qsfp_0_rst;
|
||||
assign ptp_sample_clk = clk_125mhz_int;
|
||||
|
||||
// DDR4
|
||||
wire [DDR_CH-1:0] ddr_clk;
|
||||
wire [DDR_CH-1:0] ddr_rst;
|
||||
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid;
|
||||
wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr;
|
||||
wire [DDR_CH*8-1:0] m_axi_ddr_awlen;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_awsize;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_awburst;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_awlock;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_awcache;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_awprot;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_awqos;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_awvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_awready;
|
||||
wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata;
|
||||
wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_wlast;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_wvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_wready;
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_bresp;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_bvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_bready;
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid;
|
||||
wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr;
|
||||
wire [DDR_CH*8-1:0] m_axi_ddr_arlen;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_arsize;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_arburst;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_arlock;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_arcache;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_arprot;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_arqos;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_arvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_arready;
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid;
|
||||
wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_rresp;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_rlast;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_rvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_rready;
|
||||
|
||||
wire [DDR_CH-1:0] ddr_status;
|
||||
|
||||
generate
|
||||
|
||||
if (DDR_ENABLE && DDR_CH > 0) begin
|
||||
|
||||
ddr4_0 ddr4_c0_inst (
|
||||
.c0_sys_clk_p(mem_clk_300mhz_0_p),
|
||||
.c0_sys_clk_n(mem_clk_300mhz_0_n),
|
||||
.sys_rst(pcie_user_reset),
|
||||
|
||||
.c0_init_calib_complete(ddr_status[0 +: 1]),
|
||||
.c0_ddr4_interrupt(),
|
||||
.dbg_clk(),
|
||||
.dbg_bus(),
|
||||
|
||||
.c0_ddr4_adr(ddr4_c0_adr),
|
||||
.c0_ddr4_ba(ddr4_c0_ba),
|
||||
.c0_ddr4_cke(ddr4_c0_cke),
|
||||
.c0_ddr4_cs_n(ddr4_c0_cs_n),
|
||||
.c0_ddr4_dq(ddr4_c0_dq),
|
||||
.c0_ddr4_dqs_t(ddr4_c0_dqs_t),
|
||||
.c0_ddr4_dqs_c(ddr4_c0_dqs_c),
|
||||
.c0_ddr4_dm_dbi_n(ddr4_c0_dm_dbi_n),
|
||||
.c0_ddr4_odt(ddr4_c0_odt),
|
||||
.c0_ddr4_bg(ddr4_c0_bg),
|
||||
.c0_ddr4_reset_n(ddr4_c0_reset_n),
|
||||
.c0_ddr4_act_n(ddr4_c0_act_n),
|
||||
.c0_ddr4_ck_t(ddr4_c0_ck_t),
|
||||
.c0_ddr4_ck_c(ddr4_c0_ck_c),
|
||||
|
||||
.c0_ddr4_ui_clk(ddr_clk[0 +: 1]),
|
||||
.c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]),
|
||||
|
||||
.c0_ddr4_aresetn(!ddr_rst[0 +: 1]),
|
||||
|
||||
.c0_ddr4_s_axi_ctrl_awvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_awready(),
|
||||
.c0_ddr4_s_axi_ctrl_awaddr(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_wvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_wready(),
|
||||
.c0_ddr4_s_axi_ctrl_wdata(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_bvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_bready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_bresp(),
|
||||
.c0_ddr4_s_axi_ctrl_arvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_arready(),
|
||||
.c0_ddr4_s_axi_ctrl_araddr(31'd0),
|
||||
.c0_ddr4_s_axi_ctrl_rvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_rready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_rdata(),
|
||||
.c0_ddr4_s_axi_ctrl_rresp(),
|
||||
|
||||
.c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]),
|
||||
.c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]),
|
||||
.c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]),
|
||||
.c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]),
|
||||
.c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]),
|
||||
.c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]),
|
||||
.c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]),
|
||||
.c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH])
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign ddr4_c0_adr = {17{1'bz}};
|
||||
assign ddr4_c0_ba = {2{1'bz}};
|
||||
assign ddr4_c0_bg = {2{1'bz}};
|
||||
assign ddr4_c0_cke = 1'bz;
|
||||
assign ddr4_c0_cs_n = 1'bz;
|
||||
assign ddr4_c0_act_n = 1'bz;
|
||||
assign ddr4_c0_odt = 1'bz;
|
||||
assign ddr4_c0_reset_n = 1'b0;
|
||||
assign ddr4_c0_dq = {80{1'bz}};
|
||||
assign ddr4_c0_dqs_t = {10{1'bz}};
|
||||
assign ddr4_c0_dqs_c = {10{1'bz}};
|
||||
assign ddr4_c0_dm_dbi_n = {10{1'bz}};
|
||||
|
||||
OBUFTDS ddr4_c0_ck_obuftds_inst (
|
||||
.I(1'b0),
|
||||
.T(1'b1),
|
||||
.O(ddr4_c0_ck_t),
|
||||
.OB(ddr4_c0_ck_c)
|
||||
);
|
||||
|
||||
assign ddr_clk = 0;
|
||||
assign ddr_rst = 0;
|
||||
|
||||
assign m_axi_ddr_awready = 0;
|
||||
assign m_axi_ddr_wready = 0;
|
||||
assign m_axi_ddr_bid = 0;
|
||||
assign m_axi_ddr_bresp = 0;
|
||||
assign m_axi_ddr_bvalid = 0;
|
||||
assign m_axi_ddr_arready = 0;
|
||||
assign m_axi_ddr_rid = 0;
|
||||
assign m_axi_ddr_rdata = 0;
|
||||
assign m_axi_ddr_rresp = 0;
|
||||
assign m_axi_ddr_rlast = 0;
|
||||
assign m_axi_ddr_rvalid = 0;
|
||||
|
||||
assign ddr_status = 0;
|
||||
|
||||
end
|
||||
|
||||
assign ddr4_c0_par = 1'b0;
|
||||
assign ddr4_c0_ten = 1'b0;
|
||||
|
||||
if (DDR_ENABLE && DDR_CH > 1) begin
|
||||
|
||||
ddr4_0 ddr4_c1_inst (
|
||||
.c0_sys_clk_p(mem_clk_300mhz_1_p),
|
||||
.c0_sys_clk_n(mem_clk_300mhz_1_n),
|
||||
.sys_rst(pcie_user_reset),
|
||||
|
||||
.c0_init_calib_complete(ddr_status[1 +: 1]),
|
||||
.c0_ddr4_interrupt(),
|
||||
.dbg_clk(),
|
||||
.dbg_bus(),
|
||||
|
||||
.c0_ddr4_adr(ddr4_c1_adr),
|
||||
.c0_ddr4_ba(ddr4_c1_ba),
|
||||
.c0_ddr4_cke(ddr4_c1_cke),
|
||||
.c0_ddr4_cs_n(ddr4_c1_cs_n),
|
||||
.c0_ddr4_dq(ddr4_c1_dq),
|
||||
.c0_ddr4_dqs_t(ddr4_c1_dqs_t),
|
||||
.c0_ddr4_dqs_c(ddr4_c1_dqs_c),
|
||||
.c0_ddr4_dm_dbi_n(ddr4_c1_dm_dbi_n),
|
||||
.c0_ddr4_odt(ddr4_c1_odt),
|
||||
.c0_ddr4_bg(ddr4_c1_bg),
|
||||
.c0_ddr4_reset_n(ddr4_c1_reset_n),
|
||||
.c0_ddr4_act_n(ddr4_c1_act_n),
|
||||
.c0_ddr4_ck_t(ddr4_c1_ck_t),
|
||||
.c0_ddr4_ck_c(ddr4_c1_ck_c),
|
||||
|
||||
.c0_ddr4_ui_clk(ddr_clk[1 +: 1]),
|
||||
.c0_ddr4_ui_clk_sync_rst(ddr_rst[1 +: 1]),
|
||||
|
||||
.c0_ddr4_aresetn(!ddr_rst[1 +: 1]),
|
||||
|
||||
.c0_ddr4_s_axi_ctrl_awvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_awready(),
|
||||
.c0_ddr4_s_axi_ctrl_awaddr(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_wvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_wready(),
|
||||
.c0_ddr4_s_axi_ctrl_wdata(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_bvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_bready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_bresp(),
|
||||
.c0_ddr4_s_axi_ctrl_arvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_arready(),
|
||||
.c0_ddr4_s_axi_ctrl_araddr(31'd0),
|
||||
.c0_ddr4_s_axi_ctrl_rvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_rready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_rdata(),
|
||||
.c0_ddr4_s_axi_ctrl_rresp(),
|
||||
|
||||
.c0_ddr4_s_axi_awid(m_axi_ddr_awid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[1*8 +: 8]),
|
||||
.c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[1*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[1*2 +: 2]),
|
||||
.c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[1 +: 1]),
|
||||
.c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[1*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[1*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[1*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_awready(m_axi_ddr_awready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]),
|
||||
.c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[1*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]),
|
||||
.c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[1 +: 1]),
|
||||
.c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_wready(m_axi_ddr_wready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_bready(m_axi_ddr_bready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_bid(m_axi_ddr_bid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[1*2 +: 2]),
|
||||
.c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_arid(m_axi_ddr_arid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[1*8 +: 8]),
|
||||
.c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[1*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[1*2 +: 2]),
|
||||
.c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[1 +: 1]),
|
||||
.c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[1*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[1*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[1*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_arready(m_axi_ddr_arready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_rready(m_axi_ddr_rready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[1 +: 1]),
|
||||
.c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[1*2 +: 2]),
|
||||
.c0_ddr4_s_axi_rid(m_axi_ddr_rid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH])
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign ddr4_c1_adr = {17{1'bz}};
|
||||
assign ddr4_c1_ba = {2{1'bz}};
|
||||
assign ddr4_c1_bg = {2{1'bz}};
|
||||
assign ddr4_c1_cke = 1'bz;
|
||||
assign ddr4_c1_cs_n = 1'bz;
|
||||
assign ddr4_c1_act_n = 1'bz;
|
||||
assign ddr4_c1_odt = 1'bz;
|
||||
assign ddr4_c1_reset_n = 1'b0;
|
||||
assign ddr4_c1_dq = {80{1'bz}};
|
||||
assign ddr4_c1_dqs_t = {10{1'bz}};
|
||||
assign ddr4_c1_dqs_c = {10{1'bz}};
|
||||
assign ddr4_c1_dm_dbi_n = {10{1'bz}};
|
||||
|
||||
OBUFTDS ddr4_c1_ck_obuftds_inst (
|
||||
.I(1'b0),
|
||||
.T(1'b1),
|
||||
.O(ddr4_c1_ck_t),
|
||||
.OB(ddr4_c1_ck_c)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
assign ddr4_c1_par = 1'b0;
|
||||
assign ddr4_c1_ten = 1'b0;
|
||||
|
||||
endgenerate
|
||||
|
||||
fpga_core #(
|
||||
// FW and board IDs
|
||||
.FPGA_ID(FPGA_ID),
|
||||
@ -1433,6 +1783,16 @@ fpga_core #(
|
||||
.TX_RAM_SIZE(TX_RAM_SIZE),
|
||||
.RX_RAM_SIZE(RX_RAM_SIZE),
|
||||
|
||||
// RAM configuration
|
||||
.DDR_CH(DDR_CH),
|
||||
.DDR_ENABLE(DDR_ENABLE),
|
||||
.AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH),
|
||||
.AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH),
|
||||
.AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH),
|
||||
.AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH),
|
||||
.AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN),
|
||||
.AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST),
|
||||
|
||||
// Application block configuration
|
||||
.APP_ID(APP_ID),
|
||||
.APP_ENABLE(APP_ENABLE),
|
||||
@ -1742,6 +2102,50 @@ core_inst (
|
||||
.eeprom_i2c_sda_t(eeprom_i2c_sda_t),
|
||||
.eeprom_wp(eeprom_wp),
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
.ddr_clk(ddr_clk),
|
||||
.ddr_rst(ddr_rst),
|
||||
|
||||
.m_axi_ddr_awid(m_axi_ddr_awid),
|
||||
.m_axi_ddr_awaddr(m_axi_ddr_awaddr),
|
||||
.m_axi_ddr_awlen(m_axi_ddr_awlen),
|
||||
.m_axi_ddr_awsize(m_axi_ddr_awsize),
|
||||
.m_axi_ddr_awburst(m_axi_ddr_awburst),
|
||||
.m_axi_ddr_awlock(m_axi_ddr_awlock),
|
||||
.m_axi_ddr_awcache(m_axi_ddr_awcache),
|
||||
.m_axi_ddr_awprot(m_axi_ddr_awprot),
|
||||
.m_axi_ddr_awqos(m_axi_ddr_awqos),
|
||||
.m_axi_ddr_awvalid(m_axi_ddr_awvalid),
|
||||
.m_axi_ddr_awready(m_axi_ddr_awready),
|
||||
.m_axi_ddr_wdata(m_axi_ddr_wdata),
|
||||
.m_axi_ddr_wstrb(m_axi_ddr_wstrb),
|
||||
.m_axi_ddr_wlast(m_axi_ddr_wlast),
|
||||
.m_axi_ddr_wvalid(m_axi_ddr_wvalid),
|
||||
.m_axi_ddr_wready(m_axi_ddr_wready),
|
||||
.m_axi_ddr_bid(m_axi_ddr_bid),
|
||||
.m_axi_ddr_bresp(m_axi_ddr_bresp),
|
||||
.m_axi_ddr_bvalid(m_axi_ddr_bvalid),
|
||||
.m_axi_ddr_bready(m_axi_ddr_bready),
|
||||
.m_axi_ddr_arid(m_axi_ddr_arid),
|
||||
.m_axi_ddr_araddr(m_axi_ddr_araddr),
|
||||
.m_axi_ddr_arlen(m_axi_ddr_arlen),
|
||||
.m_axi_ddr_arsize(m_axi_ddr_arsize),
|
||||
.m_axi_ddr_arburst(m_axi_ddr_arburst),
|
||||
.m_axi_ddr_arlock(m_axi_ddr_arlock),
|
||||
.m_axi_ddr_arcache(m_axi_ddr_arcache),
|
||||
.m_axi_ddr_arprot(m_axi_ddr_arprot),
|
||||
.m_axi_ddr_arqos(m_axi_ddr_arqos),
|
||||
.m_axi_ddr_arvalid(m_axi_ddr_arvalid),
|
||||
.m_axi_ddr_arready(m_axi_ddr_arready),
|
||||
.m_axi_ddr_rid(m_axi_ddr_rid),
|
||||
.m_axi_ddr_rdata(m_axi_ddr_rdata),
|
||||
.m_axi_ddr_rresp(m_axi_ddr_rresp),
|
||||
.m_axi_ddr_rlast(m_axi_ddr_rlast),
|
||||
.m_axi_ddr_rvalid(m_axi_ddr_rvalid),
|
||||
.m_axi_ddr_rready(m_axi_ddr_rready),
|
||||
|
||||
/*
|
||||
* QSPI flash
|
||||
*/
|
||||
|
||||
@ -122,6 +122,16 @@ module fpga_core #
|
||||
parameter TX_RAM_SIZE = 32768,
|
||||
parameter RX_RAM_SIZE = 32768,
|
||||
|
||||
// RAM configuration
|
||||
parameter DDR_CH = 2,
|
||||
parameter DDR_ENABLE = 1,
|
||||
parameter AXI_DDR_DATA_WIDTH = 512,
|
||||
parameter AXI_DDR_ADDR_WIDTH = 33,
|
||||
parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8),
|
||||
parameter AXI_DDR_ID_WIDTH = 8,
|
||||
parameter AXI_DDR_MAX_BURST_LEN = 256,
|
||||
parameter AXI_DDR_NARROW_BURST = 0,
|
||||
|
||||
// Application block configuration
|
||||
parameter APP_ID = 32'h00000000,
|
||||
parameter APP_ENABLE = 0,
|
||||
@ -433,6 +443,52 @@ module fpga_core #
|
||||
output wire eeprom_i2c_sda_t,
|
||||
output wire eeprom_wp,
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
input wire [DDR_CH-1:0] ddr_clk,
|
||||
input wire [DDR_CH-1:0] ddr_rst,
|
||||
|
||||
output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid,
|
||||
output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr,
|
||||
output wire [DDR_CH*8-1:0] m_axi_ddr_awlen,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_awsize,
|
||||
output wire [DDR_CH*2-1:0] m_axi_ddr_awburst,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_awlock,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_awcache,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_awprot,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_awqos,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_awvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_awready,
|
||||
output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata,
|
||||
output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_wlast,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_wvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_wready,
|
||||
input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid,
|
||||
input wire [DDR_CH*2-1:0] m_axi_ddr_bresp,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_bvalid,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_bready,
|
||||
output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid,
|
||||
output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr,
|
||||
output wire [DDR_CH*8-1:0] m_axi_ddr_arlen,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_arsize,
|
||||
output wire [DDR_CH*2-1:0] m_axi_ddr_arburst,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_arlock,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_arcache,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_arprot,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_arqos,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_arvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_arready,
|
||||
input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid,
|
||||
input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata,
|
||||
input wire [DDR_CH*2-1:0] m_axi_ddr_rresp,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_rlast,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_rvalid,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_rready,
|
||||
|
||||
input wire [DDR_CH-1:0] ddr_status,
|
||||
|
||||
/*
|
||||
* QSPI flash
|
||||
*/
|
||||
@ -1161,6 +1217,25 @@ mqnic_core_pcie_us #(
|
||||
.TX_RAM_SIZE(TX_RAM_SIZE),
|
||||
.RX_RAM_SIZE(RX_RAM_SIZE),
|
||||
|
||||
// RAM configuration
|
||||
.DDR_CH(DDR_CH),
|
||||
.DDR_ENABLE(DDR_ENABLE),
|
||||
.DDR_GROUP_SIZE(1),
|
||||
.AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH),
|
||||
.AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH),
|
||||
.AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH),
|
||||
.AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH),
|
||||
.AXI_DDR_AWUSER_ENABLE(0),
|
||||
.AXI_DDR_WUSER_ENABLE(0),
|
||||
.AXI_DDR_BUSER_ENABLE(0),
|
||||
.AXI_DDR_ARUSER_ENABLE(0),
|
||||
.AXI_DDR_RUSER_ENABLE(0),
|
||||
.AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN),
|
||||
.AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST),
|
||||
.AXI_DDR_FIXED_BURST(0),
|
||||
.AXI_DDR_WRAP_BURST(1),
|
||||
.HBM_ENABLE(0),
|
||||
|
||||
// Application block configuration
|
||||
.APP_ID(APP_ID),
|
||||
.APP_ENABLE(APP_ENABLE),
|
||||
@ -1438,6 +1513,108 @@ core_inst (
|
||||
|
||||
.eth_rx_status(eth_rx_status),
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
.ddr_clk(ddr_clk),
|
||||
.ddr_rst(ddr_rst),
|
||||
|
||||
.m_axi_ddr_awid(m_axi_ddr_awid),
|
||||
.m_axi_ddr_awaddr(m_axi_ddr_awaddr),
|
||||
.m_axi_ddr_awlen(m_axi_ddr_awlen),
|
||||
.m_axi_ddr_awsize(m_axi_ddr_awsize),
|
||||
.m_axi_ddr_awburst(m_axi_ddr_awburst),
|
||||
.m_axi_ddr_awlock(m_axi_ddr_awlock),
|
||||
.m_axi_ddr_awcache(m_axi_ddr_awcache),
|
||||
.m_axi_ddr_awprot(m_axi_ddr_awprot),
|
||||
.m_axi_ddr_awqos(m_axi_ddr_awqos),
|
||||
.m_axi_ddr_awuser(),
|
||||
.m_axi_ddr_awvalid(m_axi_ddr_awvalid),
|
||||
.m_axi_ddr_awready(m_axi_ddr_awready),
|
||||
.m_axi_ddr_wdata(m_axi_ddr_wdata),
|
||||
.m_axi_ddr_wstrb(m_axi_ddr_wstrb),
|
||||
.m_axi_ddr_wlast(m_axi_ddr_wlast),
|
||||
.m_axi_ddr_wuser(),
|
||||
.m_axi_ddr_wvalid(m_axi_ddr_wvalid),
|
||||
.m_axi_ddr_wready(m_axi_ddr_wready),
|
||||
.m_axi_ddr_bid(m_axi_ddr_bid),
|
||||
.m_axi_ddr_bresp(m_axi_ddr_bresp),
|
||||
.m_axi_ddr_buser(0),
|
||||
.m_axi_ddr_bvalid(m_axi_ddr_bvalid),
|
||||
.m_axi_ddr_bready(m_axi_ddr_bready),
|
||||
.m_axi_ddr_arid(m_axi_ddr_arid),
|
||||
.m_axi_ddr_araddr(m_axi_ddr_araddr),
|
||||
.m_axi_ddr_arlen(m_axi_ddr_arlen),
|
||||
.m_axi_ddr_arsize(m_axi_ddr_arsize),
|
||||
.m_axi_ddr_arburst(m_axi_ddr_arburst),
|
||||
.m_axi_ddr_arlock(m_axi_ddr_arlock),
|
||||
.m_axi_ddr_arcache(m_axi_ddr_arcache),
|
||||
.m_axi_ddr_arprot(m_axi_ddr_arprot),
|
||||
.m_axi_ddr_arqos(m_axi_ddr_arqos),
|
||||
.m_axi_ddr_aruser(),
|
||||
.m_axi_ddr_arvalid(m_axi_ddr_arvalid),
|
||||
.m_axi_ddr_arready(m_axi_ddr_arready),
|
||||
.m_axi_ddr_rid(m_axi_ddr_rid),
|
||||
.m_axi_ddr_rdata(m_axi_ddr_rdata),
|
||||
.m_axi_ddr_rresp(m_axi_ddr_rresp),
|
||||
.m_axi_ddr_rlast(m_axi_ddr_rlast),
|
||||
.m_axi_ddr_ruser(0),
|
||||
.m_axi_ddr_rvalid(m_axi_ddr_rvalid),
|
||||
.m_axi_ddr_rready(m_axi_ddr_rready),
|
||||
|
||||
.ddr_status(ddr_status),
|
||||
|
||||
/*
|
||||
* HBM
|
||||
*/
|
||||
.hbm_clk(0),
|
||||
.hbm_rst(0),
|
||||
|
||||
.m_axi_hbm_awid(),
|
||||
.m_axi_hbm_awaddr(),
|
||||
.m_axi_hbm_awlen(),
|
||||
.m_axi_hbm_awsize(),
|
||||
.m_axi_hbm_awburst(),
|
||||
.m_axi_hbm_awlock(),
|
||||
.m_axi_hbm_awcache(),
|
||||
.m_axi_hbm_awprot(),
|
||||
.m_axi_hbm_awqos(),
|
||||
.m_axi_hbm_awuser(),
|
||||
.m_axi_hbm_awvalid(),
|
||||
.m_axi_hbm_awready(0),
|
||||
.m_axi_hbm_wdata(),
|
||||
.m_axi_hbm_wstrb(),
|
||||
.m_axi_hbm_wlast(),
|
||||
.m_axi_hbm_wuser(),
|
||||
.m_axi_hbm_wvalid(),
|
||||
.m_axi_hbm_wready(0),
|
||||
.m_axi_hbm_bid(0),
|
||||
.m_axi_hbm_bresp(0),
|
||||
.m_axi_hbm_buser(0),
|
||||
.m_axi_hbm_bvalid(0),
|
||||
.m_axi_hbm_bready(),
|
||||
.m_axi_hbm_arid(),
|
||||
.m_axi_hbm_araddr(),
|
||||
.m_axi_hbm_arlen(),
|
||||
.m_axi_hbm_arsize(),
|
||||
.m_axi_hbm_arburst(),
|
||||
.m_axi_hbm_arlock(),
|
||||
.m_axi_hbm_arcache(),
|
||||
.m_axi_hbm_arprot(),
|
||||
.m_axi_hbm_arqos(),
|
||||
.m_axi_hbm_aruser(),
|
||||
.m_axi_hbm_arvalid(),
|
||||
.m_axi_hbm_arready(0),
|
||||
.m_axi_hbm_rid(0),
|
||||
.m_axi_hbm_rdata(0),
|
||||
.m_axi_hbm_rresp(0),
|
||||
.m_axi_hbm_rlast(0),
|
||||
.m_axi_hbm_ruser(0),
|
||||
.m_axi_hbm_rvalid(0),
|
||||
.m_axi_hbm_rready(),
|
||||
|
||||
.hbm_status(0),
|
||||
|
||||
/*
|
||||
* Statistics input
|
||||
*/
|
||||
|
||||
@ -7,6 +7,7 @@ This design targets the Xilinx Alveo U200 FPGA board.
|
||||
* FPGA: xcu200-fsgd2104-2-e
|
||||
* MAC: Xilinx 100G CMAC
|
||||
* PHY: 100G CAUI-4 CMAC and internal GTY transceivers
|
||||
* RAM: 64 GB DDR4 2400 (4x 2G x72 DIMM)
|
||||
|
||||
## How to build
|
||||
|
||||
|
||||
@ -17,23 +17,23 @@ set_operating_conditions -design_power_budget 160
|
||||
|
||||
# System clocks
|
||||
# 300 MHz (DDR 0)
|
||||
#set_property -dict {LOC AY37 IOSTANDARD LVDS} [get_ports clk_300mhz_0_p]
|
||||
#set_property -dict {LOC AY38 IOSTANDARD LVDS} [get_ports clk_300mhz_0_n]
|
||||
set_property -dict {LOC AY37 IOSTANDARD LVDS} [get_ports clk_300mhz_0_p]
|
||||
set_property -dict {LOC AY38 IOSTANDARD LVDS} [get_ports clk_300mhz_0_n]
|
||||
#create_clock -period 3.333 -name clk_300mhz_0 [get_ports clk_300mhz_0_p]
|
||||
|
||||
# 300 MHz (DDR 1)
|
||||
#set_property -dict {LOC AW20 IOSTANDARD LVDS} [get_ports clk_300mhz_1_p]
|
||||
#set_property -dict {LOC AW19 IOSTANDARD LVDS} [get_ports clk_300mhz_1_n]
|
||||
set_property -dict {LOC AW20 IOSTANDARD LVDS} [get_ports clk_300mhz_1_p]
|
||||
set_property -dict {LOC AW19 IOSTANDARD LVDS} [get_ports clk_300mhz_1_n]
|
||||
#create_clock -period 3.333 -name clk_300mhz_1 [get_ports clk_300mhz_1_p]
|
||||
|
||||
# 300 MHz (DDR 2)
|
||||
#set_property -dict {LOC F32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_p]
|
||||
#set_property -dict {LOC E32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_n]
|
||||
set_property -dict {LOC F32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_p]
|
||||
set_property -dict {LOC E32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_n]
|
||||
#create_clock -period 3.333 -name clk_300mhz_2 [get_ports clk_300mhz_2_p]
|
||||
|
||||
# 300 MHz (DDR 3)
|
||||
#set_property -dict {LOC J16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_p]
|
||||
#set_property -dict {LOC H16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_n]
|
||||
set_property -dict {LOC J16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_p]
|
||||
set_property -dict {LOC H16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_n]
|
||||
#create_clock -period 3.333 -name clk_300mhz_3 [get_ports clk_300mhz_3_p]
|
||||
|
||||
# SI570 user clock
|
||||
@ -257,3 +257,591 @@ create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_p]
|
||||
|
||||
set_false_path -from [get_ports {pcie_reset_n}]
|
||||
set_input_delay 0 [get_ports {pcie_reset_n}]
|
||||
|
||||
# DDR4 C0
|
||||
set_property -dict {LOC AT36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}]
|
||||
set_property -dict {LOC AV36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}]
|
||||
set_property -dict {LOC AV37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}]
|
||||
set_property -dict {LOC AW35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}]
|
||||
set_property -dict {LOC AW36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}]
|
||||
set_property -dict {LOC AY36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}]
|
||||
set_property -dict {LOC AY35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}]
|
||||
set_property -dict {LOC BA40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}]
|
||||
set_property -dict {LOC BA37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}]
|
||||
set_property -dict {LOC BB37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}]
|
||||
set_property -dict {LOC AR35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}]
|
||||
set_property -dict {LOC BA39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}]
|
||||
set_property -dict {LOC BB40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}]
|
||||
set_property -dict {LOC AN36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}]
|
||||
set_property -dict {LOC AP35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}]
|
||||
set_property -dict {LOC AP36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}]
|
||||
set_property -dict {LOC AR36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}]
|
||||
set_property -dict {LOC AT35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}]
|
||||
set_property -dict {LOC AT34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}]
|
||||
set_property -dict {LOC BC37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}]
|
||||
set_property -dict {LOC BC39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}]
|
||||
set_property -dict {LOC AV38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t[0]}]
|
||||
set_property -dict {LOC AW38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c[0]}]
|
||||
#set_property -dict {LOC AU34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t[1]}]
|
||||
#set_property -dict {LOC AU35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c[1]}]
|
||||
set_property -dict {LOC BC38 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[0]}]
|
||||
#set_property -dict {LOC BC40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[1]}]
|
||||
set_property -dict {LOC AR33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[0]}]
|
||||
#set_property -dict {LOC AP33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[1]}]
|
||||
#set_property -dict {LOC AN33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[2]}]
|
||||
#set_property -dict {LOC AM34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[3]}]
|
||||
set_property -dict {LOC BB39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}]
|
||||
set_property -dict {LOC AP34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[0]}]
|
||||
#set_property -dict {LOC AN34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[1]}]
|
||||
set_property -dict {LOC AU36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}]
|
||||
set_property -dict {LOC AU31 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_reset_n}]
|
||||
|
||||
set_property -dict {LOC AW28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}]
|
||||
set_property -dict {LOC AW29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}]
|
||||
set_property -dict {LOC BA28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}]
|
||||
set_property -dict {LOC BA27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}]
|
||||
set_property -dict {LOC BB29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}]
|
||||
set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}]
|
||||
set_property -dict {LOC BC27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}]
|
||||
set_property -dict {LOC BB27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}]
|
||||
set_property -dict {LOC BE28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}]
|
||||
set_property -dict {LOC BF28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}]
|
||||
set_property -dict {LOC BE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}]
|
||||
set_property -dict {LOC BD30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}]
|
||||
set_property -dict {LOC BF27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}]
|
||||
set_property -dict {LOC BE27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}]
|
||||
set_property -dict {LOC BF30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}]
|
||||
set_property -dict {LOC BF29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}]
|
||||
set_property -dict {LOC BB31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}]
|
||||
set_property -dict {LOC BB32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}]
|
||||
set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}]
|
||||
set_property -dict {LOC AY33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}]
|
||||
set_property -dict {LOC BC32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}]
|
||||
set_property -dict {LOC BC33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}]
|
||||
set_property -dict {LOC BB34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}]
|
||||
set_property -dict {LOC BC34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}]
|
||||
set_property -dict {LOC AV31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}]
|
||||
set_property -dict {LOC AV32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}]
|
||||
set_property -dict {LOC AV34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}]
|
||||
set_property -dict {LOC AW34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}]
|
||||
set_property -dict {LOC AW31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}]
|
||||
set_property -dict {LOC AY31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}]
|
||||
set_property -dict {LOC BA35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}]
|
||||
set_property -dict {LOC BA34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}]
|
||||
set_property -dict {LOC AL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}]
|
||||
set_property -dict {LOC AM30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}]
|
||||
set_property -dict {LOC AU32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}]
|
||||
set_property -dict {LOC AT32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}]
|
||||
set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}]
|
||||
set_property -dict {LOC AN32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}]
|
||||
set_property -dict {LOC AR32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}]
|
||||
set_property -dict {LOC AR31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}]
|
||||
set_property -dict {LOC AP29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}]
|
||||
set_property -dict {LOC AP28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}]
|
||||
set_property -dict {LOC AN27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}]
|
||||
set_property -dict {LOC AM27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}]
|
||||
set_property -dict {LOC AN29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}]
|
||||
set_property -dict {LOC AM29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}]
|
||||
set_property -dict {LOC AR27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}]
|
||||
set_property -dict {LOC AR28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}]
|
||||
set_property -dict {LOC AT28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}]
|
||||
set_property -dict {LOC AV27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}]
|
||||
set_property -dict {LOC AU27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}]
|
||||
set_property -dict {LOC AT27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}]
|
||||
set_property -dict {LOC AV29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}]
|
||||
set_property -dict {LOC AY30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}]
|
||||
set_property -dict {LOC AW30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}]
|
||||
set_property -dict {LOC AV28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}]
|
||||
set_property -dict {LOC BD34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}]
|
||||
set_property -dict {LOC BD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}]
|
||||
set_property -dict {LOC BE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}]
|
||||
set_property -dict {LOC BD35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}]
|
||||
set_property -dict {LOC BF32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}]
|
||||
set_property -dict {LOC BF33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}]
|
||||
set_property -dict {LOC BF34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}]
|
||||
set_property -dict {LOC BF35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}]
|
||||
set_property -dict {LOC BD40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}]
|
||||
set_property -dict {LOC BD39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}]
|
||||
set_property -dict {LOC BF43 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}]
|
||||
set_property -dict {LOC BF42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}]
|
||||
set_property -dict {LOC BF37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}]
|
||||
set_property -dict {LOC BE37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}]
|
||||
set_property -dict {LOC BE40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}]
|
||||
set_property -dict {LOC BF41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}]
|
||||
set_property -dict {LOC BA30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}]
|
||||
set_property -dict {LOC BB30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}]
|
||||
set_property -dict {LOC BB26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}]
|
||||
set_property -dict {LOC BC26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}]
|
||||
set_property -dict {LOC BD28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}]
|
||||
set_property -dict {LOC BD29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}]
|
||||
set_property -dict {LOC BD26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}]
|
||||
set_property -dict {LOC BE26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}]
|
||||
set_property -dict {LOC BB35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}]
|
||||
set_property -dict {LOC BB36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}]
|
||||
set_property -dict {LOC BC31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}]
|
||||
set_property -dict {LOC BD31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}]
|
||||
set_property -dict {LOC AV33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}]
|
||||
set_property -dict {LOC AW33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}]
|
||||
set_property -dict {LOC BA32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}]
|
||||
set_property -dict {LOC BA33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}]
|
||||
set_property -dict {LOC AM31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}]
|
||||
set_property -dict {LOC AM32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}]
|
||||
set_property -dict {LOC AP30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[9]}]
|
||||
set_property -dict {LOC AP31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[9]}]
|
||||
set_property -dict {LOC AL28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[10]}]
|
||||
set_property -dict {LOC AL29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[10]}]
|
||||
set_property -dict {LOC AR30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[11]}]
|
||||
set_property -dict {LOC AT30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[11]}]
|
||||
set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[12]}]
|
||||
set_property -dict {LOC AU30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[12]}]
|
||||
set_property -dict {LOC AY27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[13]}]
|
||||
set_property -dict {LOC AY28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[13]}]
|
||||
set_property -dict {LOC BE35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[14]}]
|
||||
set_property -dict {LOC BE36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[14]}]
|
||||
set_property -dict {LOC BE31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[15]}]
|
||||
set_property -dict {LOC BE32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[15]}]
|
||||
set_property -dict {LOC BE38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[16]}]
|
||||
set_property -dict {LOC BF38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[16]}]
|
||||
set_property -dict {LOC BF39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[17]}]
|
||||
set_property -dict {LOC BF40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[17]}]
|
||||
|
||||
# DDR4 C1
|
||||
set_property -dict {LOC AN24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}]
|
||||
set_property -dict {LOC AT24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}]
|
||||
set_property -dict {LOC AW24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}]
|
||||
set_property -dict {LOC AN26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}]
|
||||
set_property -dict {LOC AY22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}]
|
||||
set_property -dict {LOC AY23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}]
|
||||
set_property -dict {LOC AV24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}]
|
||||
set_property -dict {LOC BA22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}]
|
||||
set_property -dict {LOC AY25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}]
|
||||
set_property -dict {LOC BA23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}]
|
||||
set_property -dict {LOC AM26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}]
|
||||
set_property -dict {LOC BA25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}]
|
||||
set_property -dict {LOC BB22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}]
|
||||
set_property -dict {LOC AL24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}]
|
||||
set_property -dict {LOC AL25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}]
|
||||
set_property -dict {LOC AM25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}]
|
||||
set_property -dict {LOC AN23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}]
|
||||
set_property -dict {LOC AU24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}]
|
||||
set_property -dict {LOC AP26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}]
|
||||
set_property -dict {LOC BC22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}]
|
||||
set_property -dict {LOC AW26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}]
|
||||
set_property -dict {LOC AT25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t[0]}]
|
||||
set_property -dict {LOC AU25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c[0]}]
|
||||
#set_property -dict {LOC AU26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t[1]}]
|
||||
#set_property -dict {LOC AV26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c[1]}]
|
||||
set_property -dict {LOC BB25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[0]}]
|
||||
#set_property -dict {LOC BB24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[1]}]
|
||||
set_property -dict {LOC AV23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[0]}]
|
||||
#set_property -dict {LOC AP25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[1]}]
|
||||
#set_property -dict {LOC AR23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[2]}]
|
||||
#set_property -dict {LOC AP23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[3]}]
|
||||
set_property -dict {LOC AW25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}]
|
||||
set_property -dict {LOC AW23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[0]}]
|
||||
#set_property -dict {LOC AP24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[1]}]
|
||||
set_property -dict {LOC AT23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}]
|
||||
set_property -dict {LOC AR17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}]
|
||||
|
||||
set_property -dict {LOC BD9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}]
|
||||
set_property -dict {LOC BD7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}]
|
||||
set_property -dict {LOC BC7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}]
|
||||
set_property -dict {LOC BD8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}]
|
||||
set_property -dict {LOC BD10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}]
|
||||
set_property -dict {LOC BE10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}]
|
||||
set_property -dict {LOC BE7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}]
|
||||
set_property -dict {LOC BF7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}]
|
||||
set_property -dict {LOC AU13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}]
|
||||
set_property -dict {LOC AV13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}]
|
||||
set_property -dict {LOC AW13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}]
|
||||
set_property -dict {LOC AW14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}]
|
||||
set_property -dict {LOC AU14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}]
|
||||
set_property -dict {LOC AY11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}]
|
||||
set_property -dict {LOC AV14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}]
|
||||
set_property -dict {LOC BA11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}]
|
||||
set_property -dict {LOC BA12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}]
|
||||
set_property -dict {LOC BB12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}]
|
||||
set_property -dict {LOC BA13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}]
|
||||
set_property -dict {LOC BA14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}]
|
||||
set_property -dict {LOC BC9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}]
|
||||
set_property -dict {LOC BB9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}]
|
||||
set_property -dict {LOC BA7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}]
|
||||
set_property -dict {LOC BA8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}]
|
||||
set_property -dict {LOC AN13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}]
|
||||
set_property -dict {LOC AR13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}]
|
||||
set_property -dict {LOC AM13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}]
|
||||
set_property -dict {LOC AP13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}]
|
||||
set_property -dict {LOC AM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}]
|
||||
set_property -dict {LOC AR15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}]
|
||||
set_property -dict {LOC AL14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}]
|
||||
set_property -dict {LOC AT15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}]
|
||||
set_property -dict {LOC BE13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}]
|
||||
set_property -dict {LOC BD14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}]
|
||||
set_property -dict {LOC BF12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}]
|
||||
set_property -dict {LOC BD13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}]
|
||||
set_property -dict {LOC BD15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}]
|
||||
set_property -dict {LOC BD16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}]
|
||||
set_property -dict {LOC BF14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}]
|
||||
set_property -dict {LOC BF13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}]
|
||||
set_property -dict {LOC AY17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}]
|
||||
set_property -dict {LOC BA17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}]
|
||||
set_property -dict {LOC AY18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}]
|
||||
set_property -dict {LOC BA18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}]
|
||||
set_property -dict {LOC BA15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}]
|
||||
set_property -dict {LOC BB15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}]
|
||||
set_property -dict {LOC BC11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}]
|
||||
set_property -dict {LOC BD11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}]
|
||||
set_property -dict {LOC AV16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}]
|
||||
set_property -dict {LOC AV17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}]
|
||||
set_property -dict {LOC AU16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}]
|
||||
set_property -dict {LOC AU17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}]
|
||||
set_property -dict {LOC BB17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}]
|
||||
set_property -dict {LOC BB16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}]
|
||||
set_property -dict {LOC AT18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}]
|
||||
set_property -dict {LOC AT17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}]
|
||||
set_property -dict {LOC AM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}]
|
||||
set_property -dict {LOC AL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}]
|
||||
set_property -dict {LOC AN17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}]
|
||||
set_property -dict {LOC AN16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}]
|
||||
set_property -dict {LOC AR18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}]
|
||||
set_property -dict {LOC AP18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}]
|
||||
set_property -dict {LOC AL17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}]
|
||||
set_property -dict {LOC AL16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}]
|
||||
set_property -dict {LOC BF25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}]
|
||||
set_property -dict {LOC BF24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}]
|
||||
set_property -dict {LOC BD25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}]
|
||||
set_property -dict {LOC BE25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}]
|
||||
set_property -dict {LOC BD23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}]
|
||||
set_property -dict {LOC BC23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}]
|
||||
set_property -dict {LOC BF23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}]
|
||||
set_property -dict {LOC BE23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}]
|
||||
set_property -dict {LOC BF10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}]
|
||||
set_property -dict {LOC BF9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}]
|
||||
set_property -dict {LOC BE8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}]
|
||||
set_property -dict {LOC BF8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}]
|
||||
set_property -dict {LOC AW15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}]
|
||||
set_property -dict {LOC AY15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}]
|
||||
set_property -dict {LOC AY13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}]
|
||||
set_property -dict {LOC AY12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}]
|
||||
set_property -dict {LOC BB11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}]
|
||||
set_property -dict {LOC BB10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}]
|
||||
set_property -dict {LOC BA10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}]
|
||||
set_property -dict {LOC BA9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}]
|
||||
set_property -dict {LOC AT14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}]
|
||||
set_property -dict {LOC AT13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}]
|
||||
set_property -dict {LOC AN14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}]
|
||||
set_property -dict {LOC AP14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}]
|
||||
set_property -dict {LOC BE12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}]
|
||||
set_property -dict {LOC BE11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}]
|
||||
set_property -dict {LOC BE15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}]
|
||||
set_property -dict {LOC BF15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}]
|
||||
set_property -dict {LOC BC13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[10]}]
|
||||
set_property -dict {LOC BC12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[10]}]
|
||||
set_property -dict {LOC BB14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[11]}]
|
||||
set_property -dict {LOC BC14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[11]}]
|
||||
set_property -dict {LOC AV18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[12]}]
|
||||
set_property -dict {LOC AW18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[12]}]
|
||||
set_property -dict {LOC AW16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[13]}]
|
||||
set_property -dict {LOC AY16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[13]}]
|
||||
set_property -dict {LOC AP16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[14]}]
|
||||
set_property -dict {LOC AR16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[14]}]
|
||||
set_property -dict {LOC AM17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[15]}]
|
||||
set_property -dict {LOC AM16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[15]}]
|
||||
set_property -dict {LOC BC24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[16]}]
|
||||
set_property -dict {LOC BD24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[16]}]
|
||||
set_property -dict {LOC BE22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[17]}]
|
||||
set_property -dict {LOC BF22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[17]}]
|
||||
|
||||
# DDR4 C2
|
||||
set_property -dict {LOC L29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[0]}]
|
||||
set_property -dict {LOC A33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[1]}]
|
||||
set_property -dict {LOC C33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[2]}]
|
||||
set_property -dict {LOC J29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[3]}]
|
||||
set_property -dict {LOC H31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[4]}]
|
||||
set_property -dict {LOC G31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[5]}]
|
||||
set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[6]}]
|
||||
set_property -dict {LOC B32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[7]}]
|
||||
set_property -dict {LOC A32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[8]}]
|
||||
set_property -dict {LOC D31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[9]}]
|
||||
set_property -dict {LOC A34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[10]}]
|
||||
set_property -dict {LOC E31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[11]}]
|
||||
set_property -dict {LOC M30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[12]}]
|
||||
set_property -dict {LOC F33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[13]}]
|
||||
set_property -dict {LOC A35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[14]}]
|
||||
set_property -dict {LOC G32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[15]}]
|
||||
set_property -dict {LOC K30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[16]}]
|
||||
set_property -dict {LOC D33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[0]}]
|
||||
set_property -dict {LOC B36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[1]}]
|
||||
set_property -dict {LOC C31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[0]}]
|
||||
set_property -dict {LOC J30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[1]}]
|
||||
set_property -dict {LOC C34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t[0]}]
|
||||
set_property -dict {LOC B34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c[0]}]
|
||||
#set_property -dict {LOC D34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t[1]}]
|
||||
#set_property -dict {LOC D35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c[1]}]
|
||||
set_property -dict {LOC G30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[0]}]
|
||||
#set_property -dict {LOC E30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[1]}]
|
||||
set_property -dict {LOC B35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[0]}]
|
||||
#set_property -dict {LOC J31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[1]}]
|
||||
#set_property -dict {LOC L30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[2]}]
|
||||
#set_property -dict {LOC K31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[3]}]
|
||||
set_property -dict {LOC B31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_act_n}]
|
||||
set_property -dict {LOC E33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[0]}]
|
||||
#set_property -dict {LOC F34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[1]}]
|
||||
set_property -dict {LOC M29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_par}]
|
||||
set_property -dict {LOC D36 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_reset_n}]
|
||||
|
||||
set_property -dict {LOC R25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[0]}]
|
||||
set_property -dict {LOC P25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[1]}]
|
||||
set_property -dict {LOC M25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[2]}]
|
||||
set_property -dict {LOC L25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[3]}]
|
||||
set_property -dict {LOC P26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[4]}]
|
||||
set_property -dict {LOC R26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[5]}]
|
||||
set_property -dict {LOC N27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[6]}]
|
||||
set_property -dict {LOC N28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[7]}]
|
||||
set_property -dict {LOC J28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[8]}]
|
||||
set_property -dict {LOC H29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[9]}]
|
||||
set_property -dict {LOC H28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[10]}]
|
||||
set_property -dict {LOC G29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[11]}]
|
||||
set_property -dict {LOC K25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[12]}]
|
||||
set_property -dict {LOC L27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[13]}]
|
||||
set_property -dict {LOC K26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[14]}]
|
||||
set_property -dict {LOC K27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[15]}]
|
||||
set_property -dict {LOC F27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[16]}]
|
||||
set_property -dict {LOC E27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[17]}]
|
||||
set_property -dict {LOC E28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[18]}]
|
||||
set_property -dict {LOC D28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[19]}]
|
||||
set_property -dict {LOC G27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[20]}]
|
||||
set_property -dict {LOC G26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[21]}]
|
||||
set_property -dict {LOC F28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[22]}]
|
||||
set_property -dict {LOC F29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[23]}]
|
||||
set_property -dict {LOC D26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[24]}]
|
||||
set_property -dict {LOC C26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[25]}]
|
||||
set_property -dict {LOC B27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[26]}]
|
||||
set_property -dict {LOC B26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[27]}]
|
||||
set_property -dict {LOC A29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[28]}]
|
||||
set_property -dict {LOC A30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[29]}]
|
||||
set_property -dict {LOC C27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[30]}]
|
||||
set_property -dict {LOC C28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[31]}]
|
||||
set_property -dict {LOC F35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[32]}]
|
||||
set_property -dict {LOC E38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[33]}]
|
||||
set_property -dict {LOC D38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[34]}]
|
||||
set_property -dict {LOC E35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[35]}]
|
||||
set_property -dict {LOC E36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[36]}]
|
||||
set_property -dict {LOC E37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[37]}]
|
||||
set_property -dict {LOC F38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[38]}]
|
||||
set_property -dict {LOC G38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[39]}]
|
||||
set_property -dict {LOC P30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[40]}]
|
||||
set_property -dict {LOC R30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[41]}]
|
||||
set_property -dict {LOC P29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[42]}]
|
||||
set_property -dict {LOC N29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[43]}]
|
||||
set_property -dict {LOC L32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[44]}]
|
||||
set_property -dict {LOC M32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[45]}]
|
||||
set_property -dict {LOC P31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[46]}]
|
||||
set_property -dict {LOC N32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[47]}]
|
||||
set_property -dict {LOC J35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[48]}]
|
||||
set_property -dict {LOC K35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[49]}]
|
||||
set_property -dict {LOC L33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[50]}]
|
||||
set_property -dict {LOC K33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[51]}]
|
||||
set_property -dict {LOC J34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[52]}]
|
||||
set_property -dict {LOC J33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[53]}]
|
||||
set_property -dict {LOC N34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[54]}]
|
||||
set_property -dict {LOC P34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[55]}]
|
||||
set_property -dict {LOC H36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[56]}]
|
||||
set_property -dict {LOC G36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[57]}]
|
||||
set_property -dict {LOC H37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[58]}]
|
||||
set_property -dict {LOC J36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[59]}]
|
||||
set_property -dict {LOC K37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[60]}]
|
||||
set_property -dict {LOC K38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[61]}]
|
||||
set_property -dict {LOC G35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[62]}]
|
||||
set_property -dict {LOC G34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[63]}]
|
||||
set_property -dict {LOC C36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[64]}]
|
||||
set_property -dict {LOC B37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[65]}]
|
||||
set_property -dict {LOC A37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[66]}]
|
||||
set_property -dict {LOC A38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[67]}]
|
||||
set_property -dict {LOC C39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[68]}]
|
||||
set_property -dict {LOC D39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[69]}]
|
||||
set_property -dict {LOC A40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[70]}]
|
||||
set_property -dict {LOC B40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[71]}]
|
||||
set_property -dict {LOC N26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[0]}]
|
||||
set_property -dict {LOC M26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[0]}]
|
||||
set_property -dict {LOC R28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[1]}]
|
||||
set_property -dict {LOC P28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[1]}]
|
||||
set_property -dict {LOC J25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[2]}]
|
||||
set_property -dict {LOC J26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[2]}]
|
||||
set_property -dict {LOC M27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[3]}]
|
||||
set_property -dict {LOC L28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[3]}]
|
||||
set_property -dict {LOC D29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[4]}]
|
||||
set_property -dict {LOC D30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[4]}]
|
||||
set_property -dict {LOC H26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[5]}]
|
||||
set_property -dict {LOC H27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[5]}]
|
||||
set_property -dict {LOC A27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[6]}]
|
||||
set_property -dict {LOC A28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[6]}]
|
||||
set_property -dict {LOC C29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[7]}]
|
||||
set_property -dict {LOC B29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[7]}]
|
||||
set_property -dict {LOC E39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[8]}]
|
||||
set_property -dict {LOC E40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[8]}]
|
||||
set_property -dict {LOC G37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[9]}]
|
||||
set_property -dict {LOC F37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[9]}]
|
||||
set_property -dict {LOC N31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[10]}]
|
||||
set_property -dict {LOC M31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[10]}]
|
||||
set_property -dict {LOC T30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[11]}]
|
||||
set_property -dict {LOC R31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[11]}]
|
||||
set_property -dict {LOC L35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[12]}]
|
||||
set_property -dict {LOC L36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[12]}]
|
||||
set_property -dict {LOC M34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[13]}]
|
||||
set_property -dict {LOC L34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[13]}]
|
||||
set_property -dict {LOC J38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[14]}]
|
||||
set_property -dict {LOC H38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[14]}]
|
||||
set_property -dict {LOC H33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[15]}]
|
||||
set_property -dict {LOC H34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[15]}]
|
||||
set_property -dict {LOC B39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[16]}]
|
||||
set_property -dict {LOC A39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[16]}]
|
||||
set_property -dict {LOC C37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[17]}]
|
||||
set_property -dict {LOC C38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[17]}]
|
||||
|
||||
# DDR4 C3
|
||||
set_property -dict {LOC K15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[0]}]
|
||||
set_property -dict {LOC B15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[1]}]
|
||||
set_property -dict {LOC F14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[2]}]
|
||||
set_property -dict {LOC A15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[3]}]
|
||||
set_property -dict {LOC C14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[4]}]
|
||||
set_property -dict {LOC A14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[5]}]
|
||||
set_property -dict {LOC B14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[6]}]
|
||||
set_property -dict {LOC E13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[7]}]
|
||||
set_property -dict {LOC F13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[8]}]
|
||||
set_property -dict {LOC A13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[9]}]
|
||||
set_property -dict {LOC D14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[10]}]
|
||||
set_property -dict {LOC C13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[11]}]
|
||||
set_property -dict {LOC B13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[12]}]
|
||||
set_property -dict {LOC K16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[13]}]
|
||||
set_property -dict {LOC D15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[14]}]
|
||||
set_property -dict {LOC E15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[15]}]
|
||||
set_property -dict {LOC F15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[16]}]
|
||||
set_property -dict {LOC J15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[0]}]
|
||||
set_property -dict {LOC H14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[1]}]
|
||||
set_property -dict {LOC D13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[0]}]
|
||||
set_property -dict {LOC J13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[1]}]
|
||||
set_property -dict {LOC L14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t[0]}]
|
||||
set_property -dict {LOC L13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c[0]}]
|
||||
#set_property -dict {LOC G14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t[1]}]
|
||||
#set_property -dict {LOC G13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c[1]}]
|
||||
set_property -dict {LOC K13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[0]}]
|
||||
#set_property -dict {LOC L15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[1]}]
|
||||
set_property -dict {LOC B16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[0]}]
|
||||
#set_property -dict {LOC D16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[1]}]
|
||||
#set_property -dict {LOC M14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[2]}]
|
||||
#set_property -dict {LOC M13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[3]}]
|
||||
set_property -dict {LOC H13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_act_n}]
|
||||
set_property -dict {LOC C16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[0]}]
|
||||
#set_property -dict {LOC E16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[1]}]
|
||||
set_property -dict {LOC J14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_par}]
|
||||
set_property -dict {LOC D21 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c3_reset_n}]
|
||||
|
||||
set_property -dict {LOC P24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[0]}]
|
||||
set_property -dict {LOC N24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[1]}]
|
||||
set_property -dict {LOC T24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[2]}]
|
||||
set_property -dict {LOC R23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[3]}]
|
||||
set_property -dict {LOC N23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[4]}]
|
||||
set_property -dict {LOC P21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[5]}]
|
||||
set_property -dict {LOC P23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[6]}]
|
||||
set_property -dict {LOC R21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[7]}]
|
||||
set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[8]}]
|
||||
set_property -dict {LOC J23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[9]}]
|
||||
set_property -dict {LOC H24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[10]}]
|
||||
set_property -dict {LOC G24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[11]}]
|
||||
set_property -dict {LOC L24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[12]}]
|
||||
set_property -dict {LOC L23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[13]}]
|
||||
set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[14]}]
|
||||
set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[15]}]
|
||||
set_property -dict {LOC G20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[16]}]
|
||||
set_property -dict {LOC H17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[17]}]
|
||||
set_property -dict {LOC F19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[18]}]
|
||||
set_property -dict {LOC G17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[19]}]
|
||||
set_property -dict {LOC J20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[20]}]
|
||||
set_property -dict {LOC L19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[21]}]
|
||||
set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[22]}]
|
||||
set_property -dict {LOC J19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[23]}]
|
||||
set_property -dict {LOC M19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[24]}]
|
||||
set_property -dict {LOC M20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[25]}]
|
||||
set_property -dict {LOC R18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[26]}]
|
||||
set_property -dict {LOC R17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[27]}]
|
||||
set_property -dict {LOC R20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[28]}]
|
||||
set_property -dict {LOC T20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[29]}]
|
||||
set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[30]}]
|
||||
set_property -dict {LOC N19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[31]}]
|
||||
set_property -dict {LOC A23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[32]}]
|
||||
set_property -dict {LOC A22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[33]}]
|
||||
set_property -dict {LOC B24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[34]}]
|
||||
set_property -dict {LOC B25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[35]}]
|
||||
set_property -dict {LOC B22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[36]}]
|
||||
set_property -dict {LOC C22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[37]}]
|
||||
set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[38]}]
|
||||
set_property -dict {LOC C23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[39]}]
|
||||
set_property -dict {LOC C19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[40]}]
|
||||
set_property -dict {LOC C18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[41]}]
|
||||
set_property -dict {LOC C21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[42]}]
|
||||
set_property -dict {LOC B21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[43]}]
|
||||
set_property -dict {LOC A18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[44]}]
|
||||
set_property -dict {LOC A17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[45]}]
|
||||
set_property -dict {LOC A20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[46]}]
|
||||
set_property -dict {LOC B20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[47]}]
|
||||
set_property -dict {LOC E17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[48]}]
|
||||
set_property -dict {LOC F20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[49]}]
|
||||
set_property -dict {LOC E18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[50]}]
|
||||
set_property -dict {LOC E20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[51]}]
|
||||
set_property -dict {LOC D19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[52]}]
|
||||
set_property -dict {LOC D20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[53]}]
|
||||
set_property -dict {LOC H18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[54]}]
|
||||
set_property -dict {LOC J18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[55]}]
|
||||
set_property -dict {LOC F22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[56]}]
|
||||
set_property -dict {LOC E22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[57]}]
|
||||
set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[58]}]
|
||||
set_property -dict {LOC G21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[59]}]
|
||||
set_property -dict {LOC F24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[60]}]
|
||||
set_property -dict {LOC E25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[61]}]
|
||||
set_property -dict {LOC F25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[62]}]
|
||||
set_property -dict {LOC G25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[63]}]
|
||||
set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[64]}]
|
||||
set_property -dict {LOC N16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[65]}]
|
||||
set_property -dict {LOC N13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[66]}]
|
||||
set_property -dict {LOC N14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[67]}]
|
||||
set_property -dict {LOC T15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[68]}]
|
||||
set_property -dict {LOC R15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[69]}]
|
||||
set_property -dict {LOC P13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[70]}]
|
||||
set_property -dict {LOC P14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[71]}]
|
||||
set_property -dict {LOC T22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[0]}]
|
||||
set_property -dict {LOC R22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[0]}]
|
||||
set_property -dict {LOC N22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[1]}]
|
||||
set_property -dict {LOC N21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[1]}]
|
||||
set_property -dict {LOC J21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[2]}]
|
||||
set_property -dict {LOC H21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[2]}]
|
||||
set_property -dict {LOC M22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[3]}]
|
||||
set_property -dict {LOC L22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[3]}]
|
||||
set_property -dict {LOC L20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[4]}]
|
||||
set_property -dict {LOC K20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[4]}]
|
||||
set_property -dict {LOC K18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[5]}]
|
||||
set_property -dict {LOC K17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[5]}]
|
||||
set_property -dict {LOC P19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[6]}]
|
||||
set_property -dict {LOC P18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[6]}]
|
||||
set_property -dict {LOC N17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[7]}]
|
||||
set_property -dict {LOC M17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[7]}]
|
||||
set_property -dict {LOC A25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[8]}]
|
||||
set_property -dict {LOC A24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[8]}]
|
||||
set_property -dict {LOC D24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[9]}]
|
||||
set_property -dict {LOC D23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[9]}]
|
||||
set_property -dict {LOC C17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[10]}]
|
||||
set_property -dict {LOC B17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[10]}]
|
||||
set_property -dict {LOC B19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[11]}]
|
||||
set_property -dict {LOC A19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[11]}]
|
||||
set_property -dict {LOC F18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[12]}]
|
||||
set_property -dict {LOC F17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[12]}]
|
||||
set_property -dict {LOC H19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[13]}]
|
||||
set_property -dict {LOC G19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[13]}]
|
||||
set_property -dict {LOC F23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[14]}]
|
||||
set_property -dict {LOC E23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[14]}]
|
||||
set_property -dict {LOC H23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[15]}]
|
||||
set_property -dict {LOC H22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[15]}]
|
||||
set_property -dict {LOC R16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[16]}]
|
||||
set_property -dict {LOC P15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[16]}]
|
||||
set_property -dict {LOC T13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[17]}]
|
||||
set_property -dict {LOC R13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[17]}]
|
||||
|
||||
@ -125,6 +125,7 @@ IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
|
||||
IP_TCL_FILES += ip/cmac_usplus_0.tcl
|
||||
IP_TCL_FILES += ip/cmac_usplus_1.tcl
|
||||
IP_TCL_FILES += ip/cms.tcl
|
||||
IP_TCL_FILES += ip/ddr4_0.tcl
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
@ -136,6 +136,12 @@ dict set params MAX_TX_SIZE "9214"
|
||||
dict set params MAX_RX_SIZE "9214"
|
||||
dict set params TX_RAM_SIZE "131072"
|
||||
dict set params RX_RAM_SIZE "131072"
|
||||
|
||||
# RAM configuration
|
||||
dict set params DDR_CH "4"
|
||||
dict set params DDR_ENABLE "1"
|
||||
dict set params AXI_DDR_ID_WIDTH "8"
|
||||
dict set params AXI_DDR_MAX_BURST_LEN "256"
|
||||
|
||||
# Application block configuration
|
||||
dict set params APP_ID "32'h00000000"
|
||||
@ -187,6 +193,19 @@ dict set params STAT_PCIE_ENABLE "1"
|
||||
dict set params STAT_INC_WIDTH "24"
|
||||
dict set params STAT_ID_WIDTH "12"
|
||||
|
||||
# DDR4 MIG settings
|
||||
if {[dict get $params DDR_ENABLE]} {
|
||||
set ddr4 [get_ips ddr4_0]
|
||||
|
||||
# set AXI ID width
|
||||
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
|
||||
|
||||
# extract AXI configuration
|
||||
dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4]
|
||||
dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4]
|
||||
dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1]
|
||||
}
|
||||
|
||||
# PCIe IP core settings
|
||||
set pcie [get_ips pcie4_uscale_plus_0]
|
||||
|
||||
|
||||
17
fpga/mqnic/AU200/fpga_100g/ip/ddr4_0.tcl
Normal file
17
fpga/mqnic/AU200/fpga_100g/ip/ddr4_0.tcl
Normal file
@ -0,0 +1,17 @@
|
||||
|
||||
create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0
|
||||
|
||||
set_property -dict [list \
|
||||
CONFIG.C0.DDR4_AxiSelection {true} \
|
||||
CONFIG.C0.DDR4_AxiDataWidth {512} \
|
||||
CONFIG.C0.DDR4_AxiIDWidth {8} \
|
||||
CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \
|
||||
CONFIG.C0.DDR4_TimePeriod {833} \
|
||||
CONFIG.C0.DDR4_InputClockPeriod {3332} \
|
||||
CONFIG.C0.DDR4_MemoryType {RDIMMs} \
|
||||
CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PZ-2G3} \
|
||||
CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \
|
||||
CONFIG.C0.DDR4_CasLatency {17} \
|
||||
CONFIG.C0.DDR4_CasWriteLatency {12} \
|
||||
CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV}
|
||||
] [get_ips ddr4_0]
|
||||
@ -109,6 +109,15 @@ module fpga #
|
||||
parameter TX_RAM_SIZE = 131072,
|
||||
parameter RX_RAM_SIZE = 131072,
|
||||
|
||||
// RAM configuration
|
||||
parameter DDR_CH = 4,
|
||||
parameter DDR_ENABLE = 1,
|
||||
parameter AXI_DDR_DATA_WIDTH = 512,
|
||||
parameter AXI_DDR_ADDR_WIDTH = 34,
|
||||
parameter AXI_DDR_ID_WIDTH = 8,
|
||||
parameter AXI_DDR_MAX_BURST_LEN = 256,
|
||||
parameter AXI_DDR_NARROW_BURST = 0,
|
||||
|
||||
// Application block configuration
|
||||
parameter APP_ID = 32'h00000000,
|
||||
parameter APP_ENABLE = 0,
|
||||
@ -173,6 +182,18 @@ module fpga #
|
||||
parameter STAT_ID_WIDTH = 12
|
||||
)
|
||||
(
|
||||
/*
|
||||
* Clock and reset
|
||||
*/
|
||||
input wire clk_300mhz_0_p,
|
||||
input wire clk_300mhz_0_n,
|
||||
input wire clk_300mhz_1_p,
|
||||
input wire clk_300mhz_1_n,
|
||||
input wire clk_300mhz_2_p,
|
||||
input wire clk_300mhz_2_n,
|
||||
input wire clk_300mhz_3_p,
|
||||
input wire clk_300mhz_3_n,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
@ -256,7 +277,70 @@ module fpga #
|
||||
input wire qsfp1_intl,
|
||||
output wire qsfp1_lpmode,
|
||||
output wire qsfp1_refclk_reset,
|
||||
output wire [1:0] qsfp1_fs
|
||||
output wire [1:0] qsfp1_fs,
|
||||
|
||||
/*
|
||||
* DDR4
|
||||
*/
|
||||
output wire [16:0] ddr4_c0_adr,
|
||||
output wire [1:0] ddr4_c0_ba,
|
||||
output wire [1:0] ddr4_c0_bg,
|
||||
output wire [0:0] ddr4_c0_ck_t,
|
||||
output wire [0:0] ddr4_c0_ck_c,
|
||||
output wire [0:0] ddr4_c0_cke,
|
||||
output wire [0:0] ddr4_c0_cs_n,
|
||||
output wire ddr4_c0_act_n,
|
||||
output wire [0:0] ddr4_c0_odt,
|
||||
output wire ddr4_c0_par,
|
||||
output wire ddr4_c0_reset_n,
|
||||
inout wire [71:0] ddr4_c0_dq,
|
||||
inout wire [17:0] ddr4_c0_dqs_t,
|
||||
inout wire [17:0] ddr4_c0_dqs_c,
|
||||
|
||||
output wire [16:0] ddr4_c1_adr,
|
||||
output wire [1:0] ddr4_c1_ba,
|
||||
output wire [1:0] ddr4_c1_bg,
|
||||
output wire [0:0] ddr4_c1_ck_t,
|
||||
output wire [0:0] ddr4_c1_ck_c,
|
||||
output wire [0:0] ddr4_c1_cke,
|
||||
output wire [0:0] ddr4_c1_cs_n,
|
||||
output wire ddr4_c1_act_n,
|
||||
output wire [0:0] ddr4_c1_odt,
|
||||
output wire ddr4_c1_par,
|
||||
output wire ddr4_c1_reset_n,
|
||||
inout wire [71:0] ddr4_c1_dq,
|
||||
inout wire [17:0] ddr4_c1_dqs_t,
|
||||
inout wire [17:0] ddr4_c1_dqs_c,
|
||||
|
||||
output wire [16:0] ddr4_c2_adr,
|
||||
output wire [1:0] ddr4_c2_ba,
|
||||
output wire [1:0] ddr4_c2_bg,
|
||||
output wire [0:0] ddr4_c2_ck_t,
|
||||
output wire [0:0] ddr4_c2_ck_c,
|
||||
output wire [0:0] ddr4_c2_cke,
|
||||
output wire [0:0] ddr4_c2_cs_n,
|
||||
output wire ddr4_c2_act_n,
|
||||
output wire [0:0] ddr4_c2_odt,
|
||||
output wire ddr4_c2_par,
|
||||
output wire ddr4_c2_reset_n,
|
||||
inout wire [71:0] ddr4_c2_dq,
|
||||
inout wire [17:0] ddr4_c2_dqs_t,
|
||||
inout wire [17:0] ddr4_c2_dqs_c,
|
||||
|
||||
output wire [16:0] ddr4_c3_adr,
|
||||
output wire [1:0] ddr4_c3_ba,
|
||||
output wire [1:0] ddr4_c3_bg,
|
||||
output wire [0:0] ddr4_c3_ck_t,
|
||||
output wire [0:0] ddr4_c3_ck_c,
|
||||
output wire [0:0] ddr4_c3_cke,
|
||||
output wire [0:0] ddr4_c3_cs_n,
|
||||
output wire ddr4_c3_act_n,
|
||||
output wire [0:0] ddr4_c3_odt,
|
||||
output wire ddr4_c3_par,
|
||||
output wire ddr4_c3_reset_n,
|
||||
inout wire [71:0] ddr4_c3_dq,
|
||||
inout wire [17:0] ddr4_c3_dqs_t,
|
||||
inout wire [17:0] ddr4_c3_dqs_c
|
||||
);
|
||||
|
||||
// PTP configuration
|
||||
@ -269,6 +353,9 @@ parameter PTP_SEPARATE_RX_CLOCK = 1;
|
||||
// Interface configuration
|
||||
parameter TX_TAG_WIDTH = 16;
|
||||
|
||||
// RAM configuration
|
||||
parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8);
|
||||
|
||||
// Ethernet interface configuration
|
||||
parameter AXIS_ETH_DATA_WIDTH = 512;
|
||||
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8;
|
||||
@ -1889,6 +1976,519 @@ assign led[0] = led_int[0]; // red
|
||||
assign led[1] = qsfp1_rx_status; // yellow
|
||||
assign led[2] = qsfp0_rx_status; // green
|
||||
|
||||
// DDR4
|
||||
wire [DDR_CH-1:0] ddr_clk;
|
||||
wire [DDR_CH-1:0] ddr_rst;
|
||||
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid;
|
||||
wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr;
|
||||
wire [DDR_CH*8-1:0] m_axi_ddr_awlen;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_awsize;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_awburst;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_awlock;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_awcache;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_awprot;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_awqos;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_awvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_awready;
|
||||
wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata;
|
||||
wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_wlast;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_wvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_wready;
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_bresp;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_bvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_bready;
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid;
|
||||
wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr;
|
||||
wire [DDR_CH*8-1:0] m_axi_ddr_arlen;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_arsize;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_arburst;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_arlock;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_arcache;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_arprot;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_arqos;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_arvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_arready;
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid;
|
||||
wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_rresp;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_rlast;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_rvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_rready;
|
||||
|
||||
wire [DDR_CH-1:0] ddr_status;
|
||||
|
||||
generate
|
||||
|
||||
if (DDR_ENABLE && DDR_CH > 0) begin
|
||||
|
||||
ddr4_0 ddr4_c0_inst (
|
||||
.c0_sys_clk_p(clk_300mhz_0_p),
|
||||
.c0_sys_clk_n(clk_300mhz_0_n),
|
||||
.sys_rst(pcie_user_reset),
|
||||
|
||||
.c0_init_calib_complete(ddr_status[0 +: 1]),
|
||||
.c0_ddr4_interrupt(),
|
||||
.dbg_clk(),
|
||||
.dbg_bus(),
|
||||
|
||||
.c0_ddr4_adr(ddr4_c0_adr),
|
||||
.c0_ddr4_ba(ddr4_c0_ba),
|
||||
.c0_ddr4_cke(ddr4_c0_cke),
|
||||
.c0_ddr4_cs_n(ddr4_c0_cs_n),
|
||||
.c0_ddr4_dq(ddr4_c0_dq),
|
||||
.c0_ddr4_dqs_t(ddr4_c0_dqs_t),
|
||||
.c0_ddr4_dqs_c(ddr4_c0_dqs_c),
|
||||
.c0_ddr4_odt(ddr4_c0_odt),
|
||||
.c0_ddr4_parity(ddr4_c0_par),
|
||||
.c0_ddr4_bg(ddr4_c0_bg),
|
||||
.c0_ddr4_reset_n(ddr4_c0_reset_n),
|
||||
.c0_ddr4_act_n(ddr4_c0_act_n),
|
||||
.c0_ddr4_ck_t(ddr4_c0_ck_t),
|
||||
.c0_ddr4_ck_c(ddr4_c0_ck_c),
|
||||
|
||||
.c0_ddr4_ui_clk(ddr_clk[0 +: 1]),
|
||||
.c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]),
|
||||
|
||||
.c0_ddr4_aresetn(!ddr_rst[0 +: 1]),
|
||||
|
||||
.c0_ddr4_s_axi_ctrl_awvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_awready(),
|
||||
.c0_ddr4_s_axi_ctrl_awaddr(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_wvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_wready(),
|
||||
.c0_ddr4_s_axi_ctrl_wdata(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_bvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_bready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_bresp(),
|
||||
.c0_ddr4_s_axi_ctrl_arvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_arready(),
|
||||
.c0_ddr4_s_axi_ctrl_araddr(31'd0),
|
||||
.c0_ddr4_s_axi_ctrl_rvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_rready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_rdata(),
|
||||
.c0_ddr4_s_axi_ctrl_rresp(),
|
||||
|
||||
.c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]),
|
||||
.c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]),
|
||||
.c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]),
|
||||
.c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]),
|
||||
.c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]),
|
||||
.c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]),
|
||||
.c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]),
|
||||
.c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH])
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign ddr4_c0_adr = {17{1'bz}};
|
||||
assign ddr4_c0_ba = {2{1'bz}};
|
||||
assign ddr4_c0_bg = {2{1'bz}};
|
||||
assign ddr4_c0_cke = 1'bz;
|
||||
assign ddr4_c0_cs_n = 1'bz;
|
||||
assign ddr4_c0_act_n = 1'bz;
|
||||
assign ddr4_c0_odt = 1'bz;
|
||||
assign ddr4_c0_par = 1'bz;
|
||||
assign ddr4_c0_reset_n = 1'b0;
|
||||
assign ddr4_c0_dq = {72{1'bz}};
|
||||
assign ddr4_c0_dqs_t = {18{1'bz}};
|
||||
assign ddr4_c0_dqs_c = {18{1'bz}};
|
||||
|
||||
OBUFTDS ddr4_c0_ck_obuftds_inst (
|
||||
.I(1'b0),
|
||||
.T(1'b1),
|
||||
.O(ddr4_c0_ck_t),
|
||||
.OB(ddr4_c0_ck_c)
|
||||
);
|
||||
|
||||
assign ddr_clk = 0;
|
||||
assign ddr_rst = 0;
|
||||
|
||||
assign m_axi_ddr_awready = 0;
|
||||
assign m_axi_ddr_wready = 0;
|
||||
assign m_axi_ddr_bid = 0;
|
||||
assign m_axi_ddr_bresp = 0;
|
||||
assign m_axi_ddr_bvalid = 0;
|
||||
assign m_axi_ddr_arready = 0;
|
||||
assign m_axi_ddr_rid = 0;
|
||||
assign m_axi_ddr_rdata = 0;
|
||||
assign m_axi_ddr_rresp = 0;
|
||||
assign m_axi_ddr_rlast = 0;
|
||||
assign m_axi_ddr_rvalid = 0;
|
||||
|
||||
assign ddr_status = 0;
|
||||
|
||||
end
|
||||
|
||||
if (DDR_ENABLE && DDR_CH > 1) begin
|
||||
|
||||
ddr4_0 ddr4_c1_inst (
|
||||
.c0_sys_clk_p(clk_300mhz_1_p),
|
||||
.c0_sys_clk_n(clk_300mhz_1_n),
|
||||
.sys_rst(pcie_user_reset),
|
||||
|
||||
.c0_init_calib_complete(ddr_status[1 +: 1]),
|
||||
.c0_ddr4_interrupt(),
|
||||
.dbg_clk(),
|
||||
.dbg_bus(),
|
||||
|
||||
.c0_ddr4_adr(ddr4_c1_adr),
|
||||
.c0_ddr4_ba(ddr4_c1_ba),
|
||||
.c0_ddr4_cke(ddr4_c1_cke),
|
||||
.c0_ddr4_cs_n(ddr4_c1_cs_n),
|
||||
.c0_ddr4_dq(ddr4_c1_dq),
|
||||
.c0_ddr4_dqs_t(ddr4_c1_dqs_t),
|
||||
.c0_ddr4_dqs_c(ddr4_c1_dqs_c),
|
||||
.c0_ddr4_odt(ddr4_c1_odt),
|
||||
.c0_ddr4_parity(ddr4_c1_par),
|
||||
.c0_ddr4_bg(ddr4_c1_bg),
|
||||
.c0_ddr4_reset_n(ddr4_c1_reset_n),
|
||||
.c0_ddr4_act_n(ddr4_c1_act_n),
|
||||
.c0_ddr4_ck_t(ddr4_c1_ck_t),
|
||||
.c0_ddr4_ck_c(ddr4_c1_ck_c),
|
||||
|
||||
.c0_ddr4_ui_clk(ddr_clk[1 +: 1]),
|
||||
.c0_ddr4_ui_clk_sync_rst(ddr_rst[1 +: 1]),
|
||||
|
||||
.c0_ddr4_aresetn(!ddr_rst[1 +: 1]),
|
||||
|
||||
.c0_ddr4_s_axi_ctrl_awvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_awready(),
|
||||
.c0_ddr4_s_axi_ctrl_awaddr(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_wvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_wready(),
|
||||
.c0_ddr4_s_axi_ctrl_wdata(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_bvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_bready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_bresp(),
|
||||
.c0_ddr4_s_axi_ctrl_arvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_arready(),
|
||||
.c0_ddr4_s_axi_ctrl_araddr(31'd0),
|
||||
.c0_ddr4_s_axi_ctrl_rvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_rready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_rdata(),
|
||||
.c0_ddr4_s_axi_ctrl_rresp(),
|
||||
|
||||
.c0_ddr4_s_axi_awid(m_axi_ddr_awid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[1*8 +: 8]),
|
||||
.c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[1*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[1*2 +: 2]),
|
||||
.c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[1 +: 1]),
|
||||
.c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[1*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[1*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[1*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_awready(m_axi_ddr_awready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]),
|
||||
.c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[1*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]),
|
||||
.c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[1 +: 1]),
|
||||
.c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_wready(m_axi_ddr_wready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_bready(m_axi_ddr_bready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_bid(m_axi_ddr_bid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[1*2 +: 2]),
|
||||
.c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_arid(m_axi_ddr_arid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[1*8 +: 8]),
|
||||
.c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[1*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[1*2 +: 2]),
|
||||
.c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[1 +: 1]),
|
||||
.c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[1*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[1*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[1*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_arready(m_axi_ddr_arready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_rready(m_axi_ddr_rready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[1 +: 1]),
|
||||
.c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[1*2 +: 2]),
|
||||
.c0_ddr4_s_axi_rid(m_axi_ddr_rid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH])
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign ddr4_c1_adr = {17{1'bz}};
|
||||
assign ddr4_c1_ba = {2{1'bz}};
|
||||
assign ddr4_c1_bg = {2{1'bz}};
|
||||
assign ddr4_c1_cke = 1'bz;
|
||||
assign ddr4_c1_cs_n = 1'bz;
|
||||
assign ddr4_c1_act_n = 1'bz;
|
||||
assign ddr4_c1_odt = 1'bz;
|
||||
assign ddr4_c1_par = 1'bz;
|
||||
assign ddr4_c1_reset_n = 1'b0;
|
||||
assign ddr4_c1_dq = {72{1'bz}};
|
||||
assign ddr4_c1_dqs_t = {18{1'bz}};
|
||||
assign ddr4_c1_dqs_c = {18{1'bz}};
|
||||
|
||||
OBUFTDS ddr4_c1_ck_obuftds_inst (
|
||||
.I(1'b0),
|
||||
.T(1'b1),
|
||||
.O(ddr4_c1_ck_t),
|
||||
.OB(ddr4_c1_ck_c)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
if (DDR_ENABLE && DDR_CH > 2) begin
|
||||
|
||||
ddr4_0 ddr4_c2_inst (
|
||||
.c0_sys_clk_p(clk_300mhz_2_p),
|
||||
.c0_sys_clk_n(clk_300mhz_2_n),
|
||||
.sys_rst(pcie_user_reset),
|
||||
|
||||
.c0_init_calib_complete(ddr_status[2 +: 1]),
|
||||
.c0_ddr4_interrupt(),
|
||||
.dbg_clk(),
|
||||
.dbg_bus(),
|
||||
|
||||
.c0_ddr4_adr(ddr4_c2_adr),
|
||||
.c0_ddr4_ba(ddr4_c2_ba),
|
||||
.c0_ddr4_cke(ddr4_c2_cke),
|
||||
.c0_ddr4_cs_n(ddr4_c2_cs_n),
|
||||
.c0_ddr4_dq(ddr4_c2_dq),
|
||||
.c0_ddr4_dqs_t(ddr4_c2_dqs_t),
|
||||
.c0_ddr4_dqs_c(ddr4_c2_dqs_c),
|
||||
.c0_ddr4_odt(ddr4_c2_odt),
|
||||
.c0_ddr4_parity(ddr4_c2_par),
|
||||
.c0_ddr4_bg(ddr4_c2_bg),
|
||||
.c0_ddr4_reset_n(ddr4_c2_reset_n),
|
||||
.c0_ddr4_act_n(ddr4_c2_act_n),
|
||||
.c0_ddr4_ck_t(ddr4_c2_ck_t),
|
||||
.c0_ddr4_ck_c(ddr4_c2_ck_c),
|
||||
|
||||
.c0_ddr4_ui_clk(ddr_clk[2 +: 1]),
|
||||
.c0_ddr4_ui_clk_sync_rst(ddr_rst[2 +: 1]),
|
||||
|
||||
.c0_ddr4_aresetn(!ddr_rst[2 +: 1]),
|
||||
|
||||
.c0_ddr4_s_axi_ctrl_awvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_awready(),
|
||||
.c0_ddr4_s_axi_ctrl_awaddr(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_wvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_wready(),
|
||||
.c0_ddr4_s_axi_ctrl_wdata(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_bvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_bready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_bresp(),
|
||||
.c0_ddr4_s_axi_ctrl_arvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_arready(),
|
||||
.c0_ddr4_s_axi_ctrl_araddr(31'd0),
|
||||
.c0_ddr4_s_axi_ctrl_rvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_rready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_rdata(),
|
||||
.c0_ddr4_s_axi_ctrl_rresp(),
|
||||
|
||||
.c0_ddr4_s_axi_awid(m_axi_ddr_awid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[2*8 +: 8]),
|
||||
.c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[2*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[2*2 +: 2]),
|
||||
.c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[2 +: 1]),
|
||||
.c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[2*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[2*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[2*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[2 +: 1]),
|
||||
.c0_ddr4_s_axi_awready(m_axi_ddr_awready[2 +: 1]),
|
||||
.c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]),
|
||||
.c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[2*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]),
|
||||
.c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[2 +: 1]),
|
||||
.c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[2 +: 1]),
|
||||
.c0_ddr4_s_axi_wready(m_axi_ddr_wready[2 +: 1]),
|
||||
.c0_ddr4_s_axi_bready(m_axi_ddr_bready[2 +: 1]),
|
||||
.c0_ddr4_s_axi_bid(m_axi_ddr_bid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[2*2 +: 2]),
|
||||
.c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[2 +: 1]),
|
||||
.c0_ddr4_s_axi_arid(m_axi_ddr_arid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[2*8 +: 8]),
|
||||
.c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[2*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[2*2 +: 2]),
|
||||
.c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[2 +: 1]),
|
||||
.c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[2*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[2*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[2*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[2 +: 1]),
|
||||
.c0_ddr4_s_axi_arready(m_axi_ddr_arready[2 +: 1]),
|
||||
.c0_ddr4_s_axi_rready(m_axi_ddr_rready[2 +: 1]),
|
||||
.c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[2 +: 1]),
|
||||
.c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[2 +: 1]),
|
||||
.c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[2*2 +: 2]),
|
||||
.c0_ddr4_s_axi_rid(m_axi_ddr_rid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH])
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign ddr4_c2_adr = {17{1'bz}};
|
||||
assign ddr4_c2_ba = {2{1'bz}};
|
||||
assign ddr4_c2_bg = {2{1'bz}};
|
||||
assign ddr4_c2_cke = 1'bz;
|
||||
assign ddr4_c2_cs_n = 1'bz;
|
||||
assign ddr4_c2_act_n = 1'bz;
|
||||
assign ddr4_c2_odt = 1'bz;
|
||||
assign ddr4_c2_par = 1'bz;
|
||||
assign ddr4_c2_reset_n = 1'b0;
|
||||
assign ddr4_c2_dq = {72{1'bz}};
|
||||
assign ddr4_c2_dqs_t = {18{1'bz}};
|
||||
assign ddr4_c2_dqs_c = {18{1'bz}};
|
||||
|
||||
OBUFTDS ddr4_c2_ck_obuftds_inst (
|
||||
.I(1'b0),
|
||||
.T(1'b1),
|
||||
.O(ddr4_c2_ck_t),
|
||||
.OB(ddr4_c2_ck_c)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
if (DDR_ENABLE && DDR_CH > 3) begin
|
||||
|
||||
ddr4_0 ddr4_c3_inst (
|
||||
.c0_sys_clk_p(clk_300mhz_3_p),
|
||||
.c0_sys_clk_n(clk_300mhz_3_n),
|
||||
.sys_rst(pcie_user_reset),
|
||||
|
||||
.c0_init_calib_complete(ddr_status[3 +: 1]),
|
||||
.c0_ddr4_interrupt(),
|
||||
.dbg_clk(),
|
||||
.dbg_bus(),
|
||||
|
||||
.c0_ddr4_adr(ddr4_c3_adr),
|
||||
.c0_ddr4_ba(ddr4_c3_ba),
|
||||
.c0_ddr4_cke(ddr4_c3_cke),
|
||||
.c0_ddr4_cs_n(ddr4_c3_cs_n),
|
||||
.c0_ddr4_dq(ddr4_c3_dq),
|
||||
.c0_ddr4_dqs_t(ddr4_c3_dqs_t),
|
||||
.c0_ddr4_dqs_c(ddr4_c3_dqs_c),
|
||||
.c0_ddr4_odt(ddr4_c3_odt),
|
||||
.c0_ddr4_parity(ddr4_c3_par),
|
||||
.c0_ddr4_bg(ddr4_c3_bg),
|
||||
.c0_ddr4_reset_n(ddr4_c3_reset_n),
|
||||
.c0_ddr4_act_n(ddr4_c3_act_n),
|
||||
.c0_ddr4_ck_t(ddr4_c3_ck_t),
|
||||
.c0_ddr4_ck_c(ddr4_c3_ck_c),
|
||||
|
||||
.c0_ddr4_ui_clk(ddr_clk[3 +: 1]),
|
||||
.c0_ddr4_ui_clk_sync_rst(ddr_rst[3 +: 1]),
|
||||
|
||||
.c0_ddr4_aresetn(!ddr_rst[3 +: 1]),
|
||||
|
||||
.c0_ddr4_s_axi_ctrl_awvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_awready(),
|
||||
.c0_ddr4_s_axi_ctrl_awaddr(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_wvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_wready(),
|
||||
.c0_ddr4_s_axi_ctrl_wdata(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_bvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_bready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_bresp(),
|
||||
.c0_ddr4_s_axi_ctrl_arvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_arready(),
|
||||
.c0_ddr4_s_axi_ctrl_araddr(31'd0),
|
||||
.c0_ddr4_s_axi_ctrl_rvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_rready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_rdata(),
|
||||
.c0_ddr4_s_axi_ctrl_rresp(),
|
||||
|
||||
.c0_ddr4_s_axi_awid(m_axi_ddr_awid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[3*8 +: 8]),
|
||||
.c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[3*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[3*2 +: 2]),
|
||||
.c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[3 +: 1]),
|
||||
.c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[3*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[3*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[3*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[3 +: 1]),
|
||||
.c0_ddr4_s_axi_awready(m_axi_ddr_awready[3 +: 1]),
|
||||
.c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]),
|
||||
.c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[3*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]),
|
||||
.c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[3 +: 1]),
|
||||
.c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[3 +: 1]),
|
||||
.c0_ddr4_s_axi_wready(m_axi_ddr_wready[3 +: 1]),
|
||||
.c0_ddr4_s_axi_bready(m_axi_ddr_bready[3 +: 1]),
|
||||
.c0_ddr4_s_axi_bid(m_axi_ddr_bid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[3*2 +: 2]),
|
||||
.c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[3 +: 1]),
|
||||
.c0_ddr4_s_axi_arid(m_axi_ddr_arid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[3*8 +: 8]),
|
||||
.c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[3*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[3*2 +: 2]),
|
||||
.c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[3 +: 1]),
|
||||
.c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[3*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[3*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[3*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[3 +: 1]),
|
||||
.c0_ddr4_s_axi_arready(m_axi_ddr_arready[3 +: 1]),
|
||||
.c0_ddr4_s_axi_rready(m_axi_ddr_rready[3 +: 1]),
|
||||
.c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[3 +: 1]),
|
||||
.c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[3 +: 1]),
|
||||
.c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[3*2 +: 2]),
|
||||
.c0_ddr4_s_axi_rid(m_axi_ddr_rid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH])
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign ddr4_c3_adr = {17{1'bz}};
|
||||
assign ddr4_c3_ba = {2{1'bz}};
|
||||
assign ddr4_c3_bg = {2{1'bz}};
|
||||
assign ddr4_c3_cke = 1'bz;
|
||||
assign ddr4_c3_cs_n = 1'bz;
|
||||
assign ddr4_c3_act_n = 1'bz;
|
||||
assign ddr4_c3_odt = 1'bz;
|
||||
assign ddr4_c3_par = 1'bz;
|
||||
assign ddr4_c3_reset_n = 1'b0;
|
||||
assign ddr4_c3_dq = {72{1'bz}};
|
||||
assign ddr4_c3_dqs_t = {18{1'bz}};
|
||||
assign ddr4_c3_dqs_c = {18{1'bz}};
|
||||
|
||||
OBUFTDS ddr4_c3_ck_obuftds_inst (
|
||||
.I(1'b0),
|
||||
.T(1'b1),
|
||||
.O(ddr4_c3_ck_t),
|
||||
.OB(ddr4_c3_ck_c)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
fpga_core #(
|
||||
// FW and board IDs
|
||||
.FPGA_ID(FPGA_ID),
|
||||
@ -1963,6 +2563,16 @@ fpga_core #(
|
||||
.TX_RAM_SIZE(TX_RAM_SIZE),
|
||||
.RX_RAM_SIZE(RX_RAM_SIZE),
|
||||
|
||||
// RAM configuration
|
||||
.DDR_CH(DDR_CH),
|
||||
.DDR_ENABLE(DDR_ENABLE),
|
||||
.AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH),
|
||||
.AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH),
|
||||
.AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH),
|
||||
.AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH),
|
||||
.AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN),
|
||||
.AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST),
|
||||
|
||||
// Application block configuration
|
||||
.APP_ID(APP_ID),
|
||||
.APP_ENABLE(APP_ENABLE),
|
||||
@ -2200,6 +2810,52 @@ core_inst (
|
||||
.qsfp1_intl(qsfp1_intl_int),
|
||||
.qsfp1_lpmode(qsfp1_lpmode),
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
.ddr_clk(ddr_clk),
|
||||
.ddr_rst(ddr_rst),
|
||||
|
||||
.m_axi_ddr_awid(m_axi_ddr_awid),
|
||||
.m_axi_ddr_awaddr(m_axi_ddr_awaddr),
|
||||
.m_axi_ddr_awlen(m_axi_ddr_awlen),
|
||||
.m_axi_ddr_awsize(m_axi_ddr_awsize),
|
||||
.m_axi_ddr_awburst(m_axi_ddr_awburst),
|
||||
.m_axi_ddr_awlock(m_axi_ddr_awlock),
|
||||
.m_axi_ddr_awcache(m_axi_ddr_awcache),
|
||||
.m_axi_ddr_awprot(m_axi_ddr_awprot),
|
||||
.m_axi_ddr_awqos(m_axi_ddr_awqos),
|
||||
.m_axi_ddr_awvalid(m_axi_ddr_awvalid),
|
||||
.m_axi_ddr_awready(m_axi_ddr_awready),
|
||||
.m_axi_ddr_wdata(m_axi_ddr_wdata),
|
||||
.m_axi_ddr_wstrb(m_axi_ddr_wstrb),
|
||||
.m_axi_ddr_wlast(m_axi_ddr_wlast),
|
||||
.m_axi_ddr_wvalid(m_axi_ddr_wvalid),
|
||||
.m_axi_ddr_wready(m_axi_ddr_wready),
|
||||
.m_axi_ddr_bid(m_axi_ddr_bid),
|
||||
.m_axi_ddr_bresp(m_axi_ddr_bresp),
|
||||
.m_axi_ddr_bvalid(m_axi_ddr_bvalid),
|
||||
.m_axi_ddr_bready(m_axi_ddr_bready),
|
||||
.m_axi_ddr_arid(m_axi_ddr_arid),
|
||||
.m_axi_ddr_araddr(m_axi_ddr_araddr),
|
||||
.m_axi_ddr_arlen(m_axi_ddr_arlen),
|
||||
.m_axi_ddr_arsize(m_axi_ddr_arsize),
|
||||
.m_axi_ddr_arburst(m_axi_ddr_arburst),
|
||||
.m_axi_ddr_arlock(m_axi_ddr_arlock),
|
||||
.m_axi_ddr_arcache(m_axi_ddr_arcache),
|
||||
.m_axi_ddr_arprot(m_axi_ddr_arprot),
|
||||
.m_axi_ddr_arqos(m_axi_ddr_arqos),
|
||||
.m_axi_ddr_arvalid(m_axi_ddr_arvalid),
|
||||
.m_axi_ddr_arready(m_axi_ddr_arready),
|
||||
.m_axi_ddr_rid(m_axi_ddr_rid),
|
||||
.m_axi_ddr_rdata(m_axi_ddr_rdata),
|
||||
.m_axi_ddr_rresp(m_axi_ddr_rresp),
|
||||
.m_axi_ddr_rlast(m_axi_ddr_rlast),
|
||||
.m_axi_ddr_rvalid(m_axi_ddr_rvalid),
|
||||
.m_axi_ddr_rready(m_axi_ddr_rready),
|
||||
|
||||
.ddr_status(ddr_status),
|
||||
|
||||
/*
|
||||
* QSPI flash
|
||||
*/
|
||||
|
||||
@ -115,6 +115,16 @@ module fpga_core #
|
||||
parameter TX_RAM_SIZE = 131072,
|
||||
parameter RX_RAM_SIZE = 131072,
|
||||
|
||||
// RAM configuration
|
||||
parameter DDR_CH = 4,
|
||||
parameter DDR_ENABLE = 1,
|
||||
parameter AXI_DDR_DATA_WIDTH = 512,
|
||||
parameter AXI_DDR_ADDR_WIDTH = 34,
|
||||
parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8),
|
||||
parameter AXI_DDR_ID_WIDTH = 8,
|
||||
parameter AXI_DDR_MAX_BURST_LEN = 256,
|
||||
parameter AXI_DDR_NARROW_BURST = 0,
|
||||
|
||||
// Application block configuration
|
||||
parameter APP_ID = 32'h00000000,
|
||||
parameter APP_ENABLE = 0,
|
||||
@ -364,6 +374,52 @@ module fpga_core #
|
||||
input wire qsfp1_intl,
|
||||
output wire qsfp1_lpmode,
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
input wire [DDR_CH-1:0] ddr_clk,
|
||||
input wire [DDR_CH-1:0] ddr_rst,
|
||||
|
||||
output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid,
|
||||
output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr,
|
||||
output wire [DDR_CH*8-1:0] m_axi_ddr_awlen,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_awsize,
|
||||
output wire [DDR_CH*2-1:0] m_axi_ddr_awburst,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_awlock,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_awcache,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_awprot,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_awqos,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_awvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_awready,
|
||||
output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata,
|
||||
output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_wlast,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_wvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_wready,
|
||||
input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid,
|
||||
input wire [DDR_CH*2-1:0] m_axi_ddr_bresp,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_bvalid,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_bready,
|
||||
output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid,
|
||||
output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr,
|
||||
output wire [DDR_CH*8-1:0] m_axi_ddr_arlen,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_arsize,
|
||||
output wire [DDR_CH*2-1:0] m_axi_ddr_arburst,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_arlock,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_arcache,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_arprot,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_arqos,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_arvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_arready,
|
||||
input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid,
|
||||
input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata,
|
||||
input wire [DDR_CH*2-1:0] m_axi_ddr_rresp,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_rlast,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_rvalid,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_rready,
|
||||
|
||||
input wire [DDR_CH-1:0] ddr_status,
|
||||
|
||||
/*
|
||||
* QSPI flash
|
||||
*/
|
||||
@ -903,6 +959,25 @@ mqnic_core_pcie_us #(
|
||||
.TX_RAM_SIZE(TX_RAM_SIZE),
|
||||
.RX_RAM_SIZE(RX_RAM_SIZE),
|
||||
|
||||
// RAM configuration
|
||||
.DDR_CH(DDR_CH),
|
||||
.DDR_ENABLE(DDR_ENABLE),
|
||||
.DDR_GROUP_SIZE(1),
|
||||
.AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH),
|
||||
.AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH),
|
||||
.AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH),
|
||||
.AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH),
|
||||
.AXI_DDR_AWUSER_ENABLE(0),
|
||||
.AXI_DDR_WUSER_ENABLE(0),
|
||||
.AXI_DDR_BUSER_ENABLE(0),
|
||||
.AXI_DDR_ARUSER_ENABLE(0),
|
||||
.AXI_DDR_RUSER_ENABLE(0),
|
||||
.AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN),
|
||||
.AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST),
|
||||
.AXI_DDR_FIXED_BURST(0),
|
||||
.AXI_DDR_WRAP_BURST(1),
|
||||
.HBM_ENABLE(0),
|
||||
|
||||
// Application block configuration
|
||||
.APP_ID(APP_ID),
|
||||
.APP_ENABLE(APP_ENABLE),
|
||||
@ -1180,6 +1255,108 @@ core_inst (
|
||||
|
||||
.eth_rx_status(eth_rx_status),
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
.ddr_clk(ddr_clk),
|
||||
.ddr_rst(ddr_rst),
|
||||
|
||||
.m_axi_ddr_awid(m_axi_ddr_awid),
|
||||
.m_axi_ddr_awaddr(m_axi_ddr_awaddr),
|
||||
.m_axi_ddr_awlen(m_axi_ddr_awlen),
|
||||
.m_axi_ddr_awsize(m_axi_ddr_awsize),
|
||||
.m_axi_ddr_awburst(m_axi_ddr_awburst),
|
||||
.m_axi_ddr_awlock(m_axi_ddr_awlock),
|
||||
.m_axi_ddr_awcache(m_axi_ddr_awcache),
|
||||
.m_axi_ddr_awprot(m_axi_ddr_awprot),
|
||||
.m_axi_ddr_awqos(m_axi_ddr_awqos),
|
||||
.m_axi_ddr_awuser(),
|
||||
.m_axi_ddr_awvalid(m_axi_ddr_awvalid),
|
||||
.m_axi_ddr_awready(m_axi_ddr_awready),
|
||||
.m_axi_ddr_wdata(m_axi_ddr_wdata),
|
||||
.m_axi_ddr_wstrb(m_axi_ddr_wstrb),
|
||||
.m_axi_ddr_wlast(m_axi_ddr_wlast),
|
||||
.m_axi_ddr_wuser(),
|
||||
.m_axi_ddr_wvalid(m_axi_ddr_wvalid),
|
||||
.m_axi_ddr_wready(m_axi_ddr_wready),
|
||||
.m_axi_ddr_bid(m_axi_ddr_bid),
|
||||
.m_axi_ddr_bresp(m_axi_ddr_bresp),
|
||||
.m_axi_ddr_buser(0),
|
||||
.m_axi_ddr_bvalid(m_axi_ddr_bvalid),
|
||||
.m_axi_ddr_bready(m_axi_ddr_bready),
|
||||
.m_axi_ddr_arid(m_axi_ddr_arid),
|
||||
.m_axi_ddr_araddr(m_axi_ddr_araddr),
|
||||
.m_axi_ddr_arlen(m_axi_ddr_arlen),
|
||||
.m_axi_ddr_arsize(m_axi_ddr_arsize),
|
||||
.m_axi_ddr_arburst(m_axi_ddr_arburst),
|
||||
.m_axi_ddr_arlock(m_axi_ddr_arlock),
|
||||
.m_axi_ddr_arcache(m_axi_ddr_arcache),
|
||||
.m_axi_ddr_arprot(m_axi_ddr_arprot),
|
||||
.m_axi_ddr_arqos(m_axi_ddr_arqos),
|
||||
.m_axi_ddr_aruser(),
|
||||
.m_axi_ddr_arvalid(m_axi_ddr_arvalid),
|
||||
.m_axi_ddr_arready(m_axi_ddr_arready),
|
||||
.m_axi_ddr_rid(m_axi_ddr_rid),
|
||||
.m_axi_ddr_rdata(m_axi_ddr_rdata),
|
||||
.m_axi_ddr_rresp(m_axi_ddr_rresp),
|
||||
.m_axi_ddr_rlast(m_axi_ddr_rlast),
|
||||
.m_axi_ddr_ruser(0),
|
||||
.m_axi_ddr_rvalid(m_axi_ddr_rvalid),
|
||||
.m_axi_ddr_rready(m_axi_ddr_rready),
|
||||
|
||||
.ddr_status(ddr_status),
|
||||
|
||||
/*
|
||||
* HBM
|
||||
*/
|
||||
.hbm_clk(0),
|
||||
.hbm_rst(0),
|
||||
|
||||
.m_axi_hbm_awid(),
|
||||
.m_axi_hbm_awaddr(),
|
||||
.m_axi_hbm_awlen(),
|
||||
.m_axi_hbm_awsize(),
|
||||
.m_axi_hbm_awburst(),
|
||||
.m_axi_hbm_awlock(),
|
||||
.m_axi_hbm_awcache(),
|
||||
.m_axi_hbm_awprot(),
|
||||
.m_axi_hbm_awqos(),
|
||||
.m_axi_hbm_awuser(),
|
||||
.m_axi_hbm_awvalid(),
|
||||
.m_axi_hbm_awready(0),
|
||||
.m_axi_hbm_wdata(),
|
||||
.m_axi_hbm_wstrb(),
|
||||
.m_axi_hbm_wlast(),
|
||||
.m_axi_hbm_wuser(),
|
||||
.m_axi_hbm_wvalid(),
|
||||
.m_axi_hbm_wready(0),
|
||||
.m_axi_hbm_bid(0),
|
||||
.m_axi_hbm_bresp(0),
|
||||
.m_axi_hbm_buser(0),
|
||||
.m_axi_hbm_bvalid(0),
|
||||
.m_axi_hbm_bready(),
|
||||
.m_axi_hbm_arid(),
|
||||
.m_axi_hbm_araddr(),
|
||||
.m_axi_hbm_arlen(),
|
||||
.m_axi_hbm_arsize(),
|
||||
.m_axi_hbm_arburst(),
|
||||
.m_axi_hbm_arlock(),
|
||||
.m_axi_hbm_arcache(),
|
||||
.m_axi_hbm_arprot(),
|
||||
.m_axi_hbm_arqos(),
|
||||
.m_axi_hbm_aruser(),
|
||||
.m_axi_hbm_arvalid(),
|
||||
.m_axi_hbm_arready(0),
|
||||
.m_axi_hbm_rid(0),
|
||||
.m_axi_hbm_rdata(0),
|
||||
.m_axi_hbm_rresp(0),
|
||||
.m_axi_hbm_rlast(0),
|
||||
.m_axi_hbm_ruser(0),
|
||||
.m_axi_hbm_rvalid(0),
|
||||
.m_axi_hbm_rready(),
|
||||
|
||||
.hbm_status(0),
|
||||
|
||||
/*
|
||||
* Statistics input
|
||||
*/
|
||||
|
||||
@ -4,8 +4,9 @@
|
||||
|
||||
This design targets the Xilinx Alveo U200 FPGA board.
|
||||
|
||||
FPGA: xcu200-fsgd2104-2-e
|
||||
PHY: 10G BASE-R PHY IP core and internal GTY transceiver
|
||||
* FPGA: xcu200-fsgd2104-2-e
|
||||
* PHY: 10G BASE-R PHY IP core and internal GTY transceiver
|
||||
* RAM: 64 GB DDR4 2400 (4x 2G x72 DIMM)
|
||||
|
||||
## How to build
|
||||
|
||||
|
||||
@ -17,23 +17,23 @@ set_operating_conditions -design_power_budget 160
|
||||
|
||||
# System clocks
|
||||
# 300 MHz (DDR 0)
|
||||
#set_property -dict {LOC AY37 IOSTANDARD LVDS} [get_ports clk_300mhz_0_p]
|
||||
#set_property -dict {LOC AY38 IOSTANDARD LVDS} [get_ports clk_300mhz_0_n]
|
||||
set_property -dict {LOC AY37 IOSTANDARD LVDS} [get_ports clk_300mhz_0_p]
|
||||
set_property -dict {LOC AY38 IOSTANDARD LVDS} [get_ports clk_300mhz_0_n]
|
||||
#create_clock -period 3.333 -name clk_300mhz_0 [get_ports clk_300mhz_0_p]
|
||||
|
||||
# 300 MHz (DDR 1)
|
||||
#set_property -dict {LOC AW20 IOSTANDARD LVDS} [get_ports clk_300mhz_1_p]
|
||||
#set_property -dict {LOC AW19 IOSTANDARD LVDS} [get_ports clk_300mhz_1_n]
|
||||
set_property -dict {LOC AW20 IOSTANDARD LVDS} [get_ports clk_300mhz_1_p]
|
||||
set_property -dict {LOC AW19 IOSTANDARD LVDS} [get_ports clk_300mhz_1_n]
|
||||
#create_clock -period 3.333 -name clk_300mhz_1 [get_ports clk_300mhz_1_p]
|
||||
|
||||
# 300 MHz (DDR 2)
|
||||
#set_property -dict {LOC F32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_p]
|
||||
#set_property -dict {LOC E32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_n]
|
||||
set_property -dict {LOC F32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_p]
|
||||
set_property -dict {LOC E32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_n]
|
||||
#create_clock -period 3.333 -name clk_300mhz_2 [get_ports clk_300mhz_2_p]
|
||||
|
||||
# 300 MHz (DDR 3)
|
||||
#set_property -dict {LOC J16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_p]
|
||||
#set_property -dict {LOC H16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_n]
|
||||
set_property -dict {LOC J16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_p]
|
||||
set_property -dict {LOC H16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_n]
|
||||
#create_clock -period 3.333 -name clk_300mhz_3 [get_ports clk_300mhz_3_p]
|
||||
|
||||
# SI570 user clock
|
||||
@ -257,3 +257,591 @@ create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_p]
|
||||
|
||||
set_false_path -from [get_ports {pcie_reset_n}]
|
||||
set_input_delay 0 [get_ports {pcie_reset_n}]
|
||||
|
||||
# DDR4 C0
|
||||
set_property -dict {LOC AT36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}]
|
||||
set_property -dict {LOC AV36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}]
|
||||
set_property -dict {LOC AV37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}]
|
||||
set_property -dict {LOC AW35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}]
|
||||
set_property -dict {LOC AW36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}]
|
||||
set_property -dict {LOC AY36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}]
|
||||
set_property -dict {LOC AY35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}]
|
||||
set_property -dict {LOC BA40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}]
|
||||
set_property -dict {LOC BA37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}]
|
||||
set_property -dict {LOC BB37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}]
|
||||
set_property -dict {LOC AR35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}]
|
||||
set_property -dict {LOC BA39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}]
|
||||
set_property -dict {LOC BB40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}]
|
||||
set_property -dict {LOC AN36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}]
|
||||
set_property -dict {LOC AP35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}]
|
||||
set_property -dict {LOC AP36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}]
|
||||
set_property -dict {LOC AR36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}]
|
||||
set_property -dict {LOC AT35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}]
|
||||
set_property -dict {LOC AT34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}]
|
||||
set_property -dict {LOC BC37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}]
|
||||
set_property -dict {LOC BC39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}]
|
||||
set_property -dict {LOC AV38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t[0]}]
|
||||
set_property -dict {LOC AW38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c[0]}]
|
||||
#set_property -dict {LOC AU34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t[1]}]
|
||||
#set_property -dict {LOC AU35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c[1]}]
|
||||
set_property -dict {LOC BC38 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[0]}]
|
||||
#set_property -dict {LOC BC40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[1]}]
|
||||
set_property -dict {LOC AR33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[0]}]
|
||||
#set_property -dict {LOC AP33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[1]}]
|
||||
#set_property -dict {LOC AN33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[2]}]
|
||||
#set_property -dict {LOC AM34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[3]}]
|
||||
set_property -dict {LOC BB39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}]
|
||||
set_property -dict {LOC AP34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[0]}]
|
||||
#set_property -dict {LOC AN34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[1]}]
|
||||
set_property -dict {LOC AU36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}]
|
||||
set_property -dict {LOC AU31 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_reset_n}]
|
||||
|
||||
set_property -dict {LOC AW28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}]
|
||||
set_property -dict {LOC AW29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}]
|
||||
set_property -dict {LOC BA28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}]
|
||||
set_property -dict {LOC BA27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}]
|
||||
set_property -dict {LOC BB29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}]
|
||||
set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}]
|
||||
set_property -dict {LOC BC27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}]
|
||||
set_property -dict {LOC BB27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}]
|
||||
set_property -dict {LOC BE28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}]
|
||||
set_property -dict {LOC BF28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}]
|
||||
set_property -dict {LOC BE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}]
|
||||
set_property -dict {LOC BD30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}]
|
||||
set_property -dict {LOC BF27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}]
|
||||
set_property -dict {LOC BE27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}]
|
||||
set_property -dict {LOC BF30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}]
|
||||
set_property -dict {LOC BF29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}]
|
||||
set_property -dict {LOC BB31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}]
|
||||
set_property -dict {LOC BB32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}]
|
||||
set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}]
|
||||
set_property -dict {LOC AY33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}]
|
||||
set_property -dict {LOC BC32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}]
|
||||
set_property -dict {LOC BC33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}]
|
||||
set_property -dict {LOC BB34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}]
|
||||
set_property -dict {LOC BC34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}]
|
||||
set_property -dict {LOC AV31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}]
|
||||
set_property -dict {LOC AV32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}]
|
||||
set_property -dict {LOC AV34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}]
|
||||
set_property -dict {LOC AW34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}]
|
||||
set_property -dict {LOC AW31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}]
|
||||
set_property -dict {LOC AY31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}]
|
||||
set_property -dict {LOC BA35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}]
|
||||
set_property -dict {LOC BA34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}]
|
||||
set_property -dict {LOC AL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}]
|
||||
set_property -dict {LOC AM30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}]
|
||||
set_property -dict {LOC AU32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}]
|
||||
set_property -dict {LOC AT32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}]
|
||||
set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}]
|
||||
set_property -dict {LOC AN32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}]
|
||||
set_property -dict {LOC AR32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}]
|
||||
set_property -dict {LOC AR31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}]
|
||||
set_property -dict {LOC AP29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}]
|
||||
set_property -dict {LOC AP28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}]
|
||||
set_property -dict {LOC AN27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}]
|
||||
set_property -dict {LOC AM27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}]
|
||||
set_property -dict {LOC AN29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}]
|
||||
set_property -dict {LOC AM29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}]
|
||||
set_property -dict {LOC AR27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}]
|
||||
set_property -dict {LOC AR28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}]
|
||||
set_property -dict {LOC AT28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}]
|
||||
set_property -dict {LOC AV27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}]
|
||||
set_property -dict {LOC AU27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}]
|
||||
set_property -dict {LOC AT27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}]
|
||||
set_property -dict {LOC AV29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}]
|
||||
set_property -dict {LOC AY30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}]
|
||||
set_property -dict {LOC AW30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}]
|
||||
set_property -dict {LOC AV28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}]
|
||||
set_property -dict {LOC BD34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}]
|
||||
set_property -dict {LOC BD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}]
|
||||
set_property -dict {LOC BE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}]
|
||||
set_property -dict {LOC BD35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}]
|
||||
set_property -dict {LOC BF32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}]
|
||||
set_property -dict {LOC BF33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}]
|
||||
set_property -dict {LOC BF34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}]
|
||||
set_property -dict {LOC BF35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}]
|
||||
set_property -dict {LOC BD40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}]
|
||||
set_property -dict {LOC BD39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}]
|
||||
set_property -dict {LOC BF43 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}]
|
||||
set_property -dict {LOC BF42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}]
|
||||
set_property -dict {LOC BF37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}]
|
||||
set_property -dict {LOC BE37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}]
|
||||
set_property -dict {LOC BE40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}]
|
||||
set_property -dict {LOC BF41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}]
|
||||
set_property -dict {LOC BA30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}]
|
||||
set_property -dict {LOC BB30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}]
|
||||
set_property -dict {LOC BB26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}]
|
||||
set_property -dict {LOC BC26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}]
|
||||
set_property -dict {LOC BD28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}]
|
||||
set_property -dict {LOC BD29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}]
|
||||
set_property -dict {LOC BD26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}]
|
||||
set_property -dict {LOC BE26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}]
|
||||
set_property -dict {LOC BB35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}]
|
||||
set_property -dict {LOC BB36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}]
|
||||
set_property -dict {LOC BC31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}]
|
||||
set_property -dict {LOC BD31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}]
|
||||
set_property -dict {LOC AV33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}]
|
||||
set_property -dict {LOC AW33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}]
|
||||
set_property -dict {LOC BA32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}]
|
||||
set_property -dict {LOC BA33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}]
|
||||
set_property -dict {LOC AM31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}]
|
||||
set_property -dict {LOC AM32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}]
|
||||
set_property -dict {LOC AP30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[9]}]
|
||||
set_property -dict {LOC AP31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[9]}]
|
||||
set_property -dict {LOC AL28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[10]}]
|
||||
set_property -dict {LOC AL29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[10]}]
|
||||
set_property -dict {LOC AR30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[11]}]
|
||||
set_property -dict {LOC AT30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[11]}]
|
||||
set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[12]}]
|
||||
set_property -dict {LOC AU30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[12]}]
|
||||
set_property -dict {LOC AY27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[13]}]
|
||||
set_property -dict {LOC AY28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[13]}]
|
||||
set_property -dict {LOC BE35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[14]}]
|
||||
set_property -dict {LOC BE36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[14]}]
|
||||
set_property -dict {LOC BE31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[15]}]
|
||||
set_property -dict {LOC BE32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[15]}]
|
||||
set_property -dict {LOC BE38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[16]}]
|
||||
set_property -dict {LOC BF38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[16]}]
|
||||
set_property -dict {LOC BF39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[17]}]
|
||||
set_property -dict {LOC BF40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[17]}]
|
||||
|
||||
# DDR4 C1
|
||||
set_property -dict {LOC AN24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}]
|
||||
set_property -dict {LOC AT24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}]
|
||||
set_property -dict {LOC AW24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}]
|
||||
set_property -dict {LOC AN26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}]
|
||||
set_property -dict {LOC AY22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}]
|
||||
set_property -dict {LOC AY23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}]
|
||||
set_property -dict {LOC AV24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}]
|
||||
set_property -dict {LOC BA22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}]
|
||||
set_property -dict {LOC AY25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}]
|
||||
set_property -dict {LOC BA23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}]
|
||||
set_property -dict {LOC AM26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}]
|
||||
set_property -dict {LOC BA25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}]
|
||||
set_property -dict {LOC BB22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}]
|
||||
set_property -dict {LOC AL24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}]
|
||||
set_property -dict {LOC AL25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}]
|
||||
set_property -dict {LOC AM25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}]
|
||||
set_property -dict {LOC AN23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}]
|
||||
set_property -dict {LOC AU24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}]
|
||||
set_property -dict {LOC AP26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}]
|
||||
set_property -dict {LOC BC22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}]
|
||||
set_property -dict {LOC AW26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}]
|
||||
set_property -dict {LOC AT25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t[0]}]
|
||||
set_property -dict {LOC AU25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c[0]}]
|
||||
#set_property -dict {LOC AU26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t[1]}]
|
||||
#set_property -dict {LOC AV26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c[1]}]
|
||||
set_property -dict {LOC BB25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[0]}]
|
||||
#set_property -dict {LOC BB24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[1]}]
|
||||
set_property -dict {LOC AV23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[0]}]
|
||||
#set_property -dict {LOC AP25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[1]}]
|
||||
#set_property -dict {LOC AR23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[2]}]
|
||||
#set_property -dict {LOC AP23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[3]}]
|
||||
set_property -dict {LOC AW25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}]
|
||||
set_property -dict {LOC AW23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[0]}]
|
||||
#set_property -dict {LOC AP24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[1]}]
|
||||
set_property -dict {LOC AT23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}]
|
||||
set_property -dict {LOC AR17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}]
|
||||
|
||||
set_property -dict {LOC BD9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}]
|
||||
set_property -dict {LOC BD7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}]
|
||||
set_property -dict {LOC BC7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}]
|
||||
set_property -dict {LOC BD8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}]
|
||||
set_property -dict {LOC BD10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}]
|
||||
set_property -dict {LOC BE10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}]
|
||||
set_property -dict {LOC BE7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}]
|
||||
set_property -dict {LOC BF7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}]
|
||||
set_property -dict {LOC AU13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}]
|
||||
set_property -dict {LOC AV13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}]
|
||||
set_property -dict {LOC AW13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}]
|
||||
set_property -dict {LOC AW14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}]
|
||||
set_property -dict {LOC AU14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}]
|
||||
set_property -dict {LOC AY11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}]
|
||||
set_property -dict {LOC AV14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}]
|
||||
set_property -dict {LOC BA11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}]
|
||||
set_property -dict {LOC BA12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}]
|
||||
set_property -dict {LOC BB12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}]
|
||||
set_property -dict {LOC BA13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}]
|
||||
set_property -dict {LOC BA14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}]
|
||||
set_property -dict {LOC BC9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}]
|
||||
set_property -dict {LOC BB9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}]
|
||||
set_property -dict {LOC BA7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}]
|
||||
set_property -dict {LOC BA8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}]
|
||||
set_property -dict {LOC AN13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}]
|
||||
set_property -dict {LOC AR13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}]
|
||||
set_property -dict {LOC AM13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}]
|
||||
set_property -dict {LOC AP13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}]
|
||||
set_property -dict {LOC AM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}]
|
||||
set_property -dict {LOC AR15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}]
|
||||
set_property -dict {LOC AL14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}]
|
||||
set_property -dict {LOC AT15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}]
|
||||
set_property -dict {LOC BE13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}]
|
||||
set_property -dict {LOC BD14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}]
|
||||
set_property -dict {LOC BF12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}]
|
||||
set_property -dict {LOC BD13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}]
|
||||
set_property -dict {LOC BD15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}]
|
||||
set_property -dict {LOC BD16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}]
|
||||
set_property -dict {LOC BF14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}]
|
||||
set_property -dict {LOC BF13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}]
|
||||
set_property -dict {LOC AY17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}]
|
||||
set_property -dict {LOC BA17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}]
|
||||
set_property -dict {LOC AY18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}]
|
||||
set_property -dict {LOC BA18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}]
|
||||
set_property -dict {LOC BA15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}]
|
||||
set_property -dict {LOC BB15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}]
|
||||
set_property -dict {LOC BC11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}]
|
||||
set_property -dict {LOC BD11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}]
|
||||
set_property -dict {LOC AV16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}]
|
||||
set_property -dict {LOC AV17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}]
|
||||
set_property -dict {LOC AU16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}]
|
||||
set_property -dict {LOC AU17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}]
|
||||
set_property -dict {LOC BB17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}]
|
||||
set_property -dict {LOC BB16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}]
|
||||
set_property -dict {LOC AT18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}]
|
||||
set_property -dict {LOC AT17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}]
|
||||
set_property -dict {LOC AM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}]
|
||||
set_property -dict {LOC AL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}]
|
||||
set_property -dict {LOC AN17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}]
|
||||
set_property -dict {LOC AN16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}]
|
||||
set_property -dict {LOC AR18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}]
|
||||
set_property -dict {LOC AP18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}]
|
||||
set_property -dict {LOC AL17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}]
|
||||
set_property -dict {LOC AL16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}]
|
||||
set_property -dict {LOC BF25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}]
|
||||
set_property -dict {LOC BF24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}]
|
||||
set_property -dict {LOC BD25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}]
|
||||
set_property -dict {LOC BE25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}]
|
||||
set_property -dict {LOC BD23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}]
|
||||
set_property -dict {LOC BC23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}]
|
||||
set_property -dict {LOC BF23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}]
|
||||
set_property -dict {LOC BE23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}]
|
||||
set_property -dict {LOC BF10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}]
|
||||
set_property -dict {LOC BF9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}]
|
||||
set_property -dict {LOC BE8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}]
|
||||
set_property -dict {LOC BF8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}]
|
||||
set_property -dict {LOC AW15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}]
|
||||
set_property -dict {LOC AY15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}]
|
||||
set_property -dict {LOC AY13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}]
|
||||
set_property -dict {LOC AY12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}]
|
||||
set_property -dict {LOC BB11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}]
|
||||
set_property -dict {LOC BB10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}]
|
||||
set_property -dict {LOC BA10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}]
|
||||
set_property -dict {LOC BA9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}]
|
||||
set_property -dict {LOC AT14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}]
|
||||
set_property -dict {LOC AT13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}]
|
||||
set_property -dict {LOC AN14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}]
|
||||
set_property -dict {LOC AP14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}]
|
||||
set_property -dict {LOC BE12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}]
|
||||
set_property -dict {LOC BE11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}]
|
||||
set_property -dict {LOC BE15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}]
|
||||
set_property -dict {LOC BF15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}]
|
||||
set_property -dict {LOC BC13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[10]}]
|
||||
set_property -dict {LOC BC12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[10]}]
|
||||
set_property -dict {LOC BB14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[11]}]
|
||||
set_property -dict {LOC BC14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[11]}]
|
||||
set_property -dict {LOC AV18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[12]}]
|
||||
set_property -dict {LOC AW18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[12]}]
|
||||
set_property -dict {LOC AW16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[13]}]
|
||||
set_property -dict {LOC AY16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[13]}]
|
||||
set_property -dict {LOC AP16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[14]}]
|
||||
set_property -dict {LOC AR16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[14]}]
|
||||
set_property -dict {LOC AM17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[15]}]
|
||||
set_property -dict {LOC AM16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[15]}]
|
||||
set_property -dict {LOC BC24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[16]}]
|
||||
set_property -dict {LOC BD24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[16]}]
|
||||
set_property -dict {LOC BE22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[17]}]
|
||||
set_property -dict {LOC BF22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[17]}]
|
||||
|
||||
# DDR4 C2
|
||||
set_property -dict {LOC L29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[0]}]
|
||||
set_property -dict {LOC A33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[1]}]
|
||||
set_property -dict {LOC C33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[2]}]
|
||||
set_property -dict {LOC J29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[3]}]
|
||||
set_property -dict {LOC H31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[4]}]
|
||||
set_property -dict {LOC G31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[5]}]
|
||||
set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[6]}]
|
||||
set_property -dict {LOC B32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[7]}]
|
||||
set_property -dict {LOC A32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[8]}]
|
||||
set_property -dict {LOC D31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[9]}]
|
||||
set_property -dict {LOC A34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[10]}]
|
||||
set_property -dict {LOC E31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[11]}]
|
||||
set_property -dict {LOC M30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[12]}]
|
||||
set_property -dict {LOC F33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[13]}]
|
||||
set_property -dict {LOC A35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[14]}]
|
||||
set_property -dict {LOC G32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[15]}]
|
||||
set_property -dict {LOC K30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[16]}]
|
||||
set_property -dict {LOC D33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[0]}]
|
||||
set_property -dict {LOC B36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[1]}]
|
||||
set_property -dict {LOC C31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[0]}]
|
||||
set_property -dict {LOC J30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[1]}]
|
||||
set_property -dict {LOC C34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t[0]}]
|
||||
set_property -dict {LOC B34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c[0]}]
|
||||
#set_property -dict {LOC D34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t[1]}]
|
||||
#set_property -dict {LOC D35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c[1]}]
|
||||
set_property -dict {LOC G30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[0]}]
|
||||
#set_property -dict {LOC E30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[1]}]
|
||||
set_property -dict {LOC B35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[0]}]
|
||||
#set_property -dict {LOC J31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[1]}]
|
||||
#set_property -dict {LOC L30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[2]}]
|
||||
#set_property -dict {LOC K31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[3]}]
|
||||
set_property -dict {LOC B31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_act_n}]
|
||||
set_property -dict {LOC E33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[0]}]
|
||||
#set_property -dict {LOC F34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[1]}]
|
||||
set_property -dict {LOC M29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_par}]
|
||||
set_property -dict {LOC D36 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_reset_n}]
|
||||
|
||||
set_property -dict {LOC R25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[0]}]
|
||||
set_property -dict {LOC P25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[1]}]
|
||||
set_property -dict {LOC M25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[2]}]
|
||||
set_property -dict {LOC L25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[3]}]
|
||||
set_property -dict {LOC P26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[4]}]
|
||||
set_property -dict {LOC R26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[5]}]
|
||||
set_property -dict {LOC N27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[6]}]
|
||||
set_property -dict {LOC N28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[7]}]
|
||||
set_property -dict {LOC J28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[8]}]
|
||||
set_property -dict {LOC H29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[9]}]
|
||||
set_property -dict {LOC H28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[10]}]
|
||||
set_property -dict {LOC G29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[11]}]
|
||||
set_property -dict {LOC K25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[12]}]
|
||||
set_property -dict {LOC L27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[13]}]
|
||||
set_property -dict {LOC K26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[14]}]
|
||||
set_property -dict {LOC K27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[15]}]
|
||||
set_property -dict {LOC F27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[16]}]
|
||||
set_property -dict {LOC E27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[17]}]
|
||||
set_property -dict {LOC E28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[18]}]
|
||||
set_property -dict {LOC D28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[19]}]
|
||||
set_property -dict {LOC G27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[20]}]
|
||||
set_property -dict {LOC G26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[21]}]
|
||||
set_property -dict {LOC F28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[22]}]
|
||||
set_property -dict {LOC F29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[23]}]
|
||||
set_property -dict {LOC D26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[24]}]
|
||||
set_property -dict {LOC C26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[25]}]
|
||||
set_property -dict {LOC B27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[26]}]
|
||||
set_property -dict {LOC B26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[27]}]
|
||||
set_property -dict {LOC A29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[28]}]
|
||||
set_property -dict {LOC A30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[29]}]
|
||||
set_property -dict {LOC C27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[30]}]
|
||||
set_property -dict {LOC C28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[31]}]
|
||||
set_property -dict {LOC F35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[32]}]
|
||||
set_property -dict {LOC E38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[33]}]
|
||||
set_property -dict {LOC D38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[34]}]
|
||||
set_property -dict {LOC E35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[35]}]
|
||||
set_property -dict {LOC E36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[36]}]
|
||||
set_property -dict {LOC E37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[37]}]
|
||||
set_property -dict {LOC F38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[38]}]
|
||||
set_property -dict {LOC G38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[39]}]
|
||||
set_property -dict {LOC P30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[40]}]
|
||||
set_property -dict {LOC R30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[41]}]
|
||||
set_property -dict {LOC P29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[42]}]
|
||||
set_property -dict {LOC N29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[43]}]
|
||||
set_property -dict {LOC L32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[44]}]
|
||||
set_property -dict {LOC M32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[45]}]
|
||||
set_property -dict {LOC P31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[46]}]
|
||||
set_property -dict {LOC N32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[47]}]
|
||||
set_property -dict {LOC J35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[48]}]
|
||||
set_property -dict {LOC K35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[49]}]
|
||||
set_property -dict {LOC L33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[50]}]
|
||||
set_property -dict {LOC K33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[51]}]
|
||||
set_property -dict {LOC J34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[52]}]
|
||||
set_property -dict {LOC J33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[53]}]
|
||||
set_property -dict {LOC N34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[54]}]
|
||||
set_property -dict {LOC P34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[55]}]
|
||||
set_property -dict {LOC H36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[56]}]
|
||||
set_property -dict {LOC G36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[57]}]
|
||||
set_property -dict {LOC H37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[58]}]
|
||||
set_property -dict {LOC J36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[59]}]
|
||||
set_property -dict {LOC K37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[60]}]
|
||||
set_property -dict {LOC K38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[61]}]
|
||||
set_property -dict {LOC G35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[62]}]
|
||||
set_property -dict {LOC G34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[63]}]
|
||||
set_property -dict {LOC C36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[64]}]
|
||||
set_property -dict {LOC B37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[65]}]
|
||||
set_property -dict {LOC A37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[66]}]
|
||||
set_property -dict {LOC A38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[67]}]
|
||||
set_property -dict {LOC C39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[68]}]
|
||||
set_property -dict {LOC D39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[69]}]
|
||||
set_property -dict {LOC A40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[70]}]
|
||||
set_property -dict {LOC B40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[71]}]
|
||||
set_property -dict {LOC N26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[0]}]
|
||||
set_property -dict {LOC M26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[0]}]
|
||||
set_property -dict {LOC R28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[1]}]
|
||||
set_property -dict {LOC P28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[1]}]
|
||||
set_property -dict {LOC J25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[2]}]
|
||||
set_property -dict {LOC J26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[2]}]
|
||||
set_property -dict {LOC M27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[3]}]
|
||||
set_property -dict {LOC L28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[3]}]
|
||||
set_property -dict {LOC D29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[4]}]
|
||||
set_property -dict {LOC D30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[4]}]
|
||||
set_property -dict {LOC H26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[5]}]
|
||||
set_property -dict {LOC H27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[5]}]
|
||||
set_property -dict {LOC A27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[6]}]
|
||||
set_property -dict {LOC A28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[6]}]
|
||||
set_property -dict {LOC C29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[7]}]
|
||||
set_property -dict {LOC B29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[7]}]
|
||||
set_property -dict {LOC E39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[8]}]
|
||||
set_property -dict {LOC E40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[8]}]
|
||||
set_property -dict {LOC G37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[9]}]
|
||||
set_property -dict {LOC F37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[9]}]
|
||||
set_property -dict {LOC N31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[10]}]
|
||||
set_property -dict {LOC M31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[10]}]
|
||||
set_property -dict {LOC T30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[11]}]
|
||||
set_property -dict {LOC R31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[11]}]
|
||||
set_property -dict {LOC L35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[12]}]
|
||||
set_property -dict {LOC L36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[12]}]
|
||||
set_property -dict {LOC M34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[13]}]
|
||||
set_property -dict {LOC L34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[13]}]
|
||||
set_property -dict {LOC J38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[14]}]
|
||||
set_property -dict {LOC H38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[14]}]
|
||||
set_property -dict {LOC H33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[15]}]
|
||||
set_property -dict {LOC H34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[15]}]
|
||||
set_property -dict {LOC B39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[16]}]
|
||||
set_property -dict {LOC A39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[16]}]
|
||||
set_property -dict {LOC C37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[17]}]
|
||||
set_property -dict {LOC C38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[17]}]
|
||||
|
||||
# DDR4 C3
|
||||
set_property -dict {LOC K15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[0]}]
|
||||
set_property -dict {LOC B15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[1]}]
|
||||
set_property -dict {LOC F14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[2]}]
|
||||
set_property -dict {LOC A15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[3]}]
|
||||
set_property -dict {LOC C14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[4]}]
|
||||
set_property -dict {LOC A14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[5]}]
|
||||
set_property -dict {LOC B14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[6]}]
|
||||
set_property -dict {LOC E13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[7]}]
|
||||
set_property -dict {LOC F13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[8]}]
|
||||
set_property -dict {LOC A13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[9]}]
|
||||
set_property -dict {LOC D14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[10]}]
|
||||
set_property -dict {LOC C13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[11]}]
|
||||
set_property -dict {LOC B13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[12]}]
|
||||
set_property -dict {LOC K16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[13]}]
|
||||
set_property -dict {LOC D15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[14]}]
|
||||
set_property -dict {LOC E15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[15]}]
|
||||
set_property -dict {LOC F15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[16]}]
|
||||
set_property -dict {LOC J15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[0]}]
|
||||
set_property -dict {LOC H14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[1]}]
|
||||
set_property -dict {LOC D13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[0]}]
|
||||
set_property -dict {LOC J13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[1]}]
|
||||
set_property -dict {LOC L14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t[0]}]
|
||||
set_property -dict {LOC L13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c[0]}]
|
||||
#set_property -dict {LOC G14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t[1]}]
|
||||
#set_property -dict {LOC G13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c[1]}]
|
||||
set_property -dict {LOC K13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[0]}]
|
||||
#set_property -dict {LOC L15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[1]}]
|
||||
set_property -dict {LOC B16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[0]}]
|
||||
#set_property -dict {LOC D16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[1]}]
|
||||
#set_property -dict {LOC M14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[2]}]
|
||||
#set_property -dict {LOC M13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[3]}]
|
||||
set_property -dict {LOC H13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_act_n}]
|
||||
set_property -dict {LOC C16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[0]}]
|
||||
#set_property -dict {LOC E16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[1]}]
|
||||
set_property -dict {LOC J14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_par}]
|
||||
set_property -dict {LOC D21 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c3_reset_n}]
|
||||
|
||||
set_property -dict {LOC P24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[0]}]
|
||||
set_property -dict {LOC N24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[1]}]
|
||||
set_property -dict {LOC T24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[2]}]
|
||||
set_property -dict {LOC R23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[3]}]
|
||||
set_property -dict {LOC N23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[4]}]
|
||||
set_property -dict {LOC P21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[5]}]
|
||||
set_property -dict {LOC P23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[6]}]
|
||||
set_property -dict {LOC R21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[7]}]
|
||||
set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[8]}]
|
||||
set_property -dict {LOC J23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[9]}]
|
||||
set_property -dict {LOC H24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[10]}]
|
||||
set_property -dict {LOC G24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[11]}]
|
||||
set_property -dict {LOC L24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[12]}]
|
||||
set_property -dict {LOC L23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[13]}]
|
||||
set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[14]}]
|
||||
set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[15]}]
|
||||
set_property -dict {LOC G20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[16]}]
|
||||
set_property -dict {LOC H17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[17]}]
|
||||
set_property -dict {LOC F19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[18]}]
|
||||
set_property -dict {LOC G17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[19]}]
|
||||
set_property -dict {LOC J20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[20]}]
|
||||
set_property -dict {LOC L19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[21]}]
|
||||
set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[22]}]
|
||||
set_property -dict {LOC J19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[23]}]
|
||||
set_property -dict {LOC M19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[24]}]
|
||||
set_property -dict {LOC M20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[25]}]
|
||||
set_property -dict {LOC R18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[26]}]
|
||||
set_property -dict {LOC R17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[27]}]
|
||||
set_property -dict {LOC R20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[28]}]
|
||||
set_property -dict {LOC T20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[29]}]
|
||||
set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[30]}]
|
||||
set_property -dict {LOC N19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[31]}]
|
||||
set_property -dict {LOC A23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[32]}]
|
||||
set_property -dict {LOC A22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[33]}]
|
||||
set_property -dict {LOC B24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[34]}]
|
||||
set_property -dict {LOC B25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[35]}]
|
||||
set_property -dict {LOC B22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[36]}]
|
||||
set_property -dict {LOC C22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[37]}]
|
||||
set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[38]}]
|
||||
set_property -dict {LOC C23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[39]}]
|
||||
set_property -dict {LOC C19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[40]}]
|
||||
set_property -dict {LOC C18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[41]}]
|
||||
set_property -dict {LOC C21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[42]}]
|
||||
set_property -dict {LOC B21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[43]}]
|
||||
set_property -dict {LOC A18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[44]}]
|
||||
set_property -dict {LOC A17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[45]}]
|
||||
set_property -dict {LOC A20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[46]}]
|
||||
set_property -dict {LOC B20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[47]}]
|
||||
set_property -dict {LOC E17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[48]}]
|
||||
set_property -dict {LOC F20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[49]}]
|
||||
set_property -dict {LOC E18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[50]}]
|
||||
set_property -dict {LOC E20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[51]}]
|
||||
set_property -dict {LOC D19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[52]}]
|
||||
set_property -dict {LOC D20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[53]}]
|
||||
set_property -dict {LOC H18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[54]}]
|
||||
set_property -dict {LOC J18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[55]}]
|
||||
set_property -dict {LOC F22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[56]}]
|
||||
set_property -dict {LOC E22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[57]}]
|
||||
set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[58]}]
|
||||
set_property -dict {LOC G21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[59]}]
|
||||
set_property -dict {LOC F24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[60]}]
|
||||
set_property -dict {LOC E25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[61]}]
|
||||
set_property -dict {LOC F25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[62]}]
|
||||
set_property -dict {LOC G25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[63]}]
|
||||
set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[64]}]
|
||||
set_property -dict {LOC N16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[65]}]
|
||||
set_property -dict {LOC N13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[66]}]
|
||||
set_property -dict {LOC N14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[67]}]
|
||||
set_property -dict {LOC T15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[68]}]
|
||||
set_property -dict {LOC R15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[69]}]
|
||||
set_property -dict {LOC P13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[70]}]
|
||||
set_property -dict {LOC P14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[71]}]
|
||||
set_property -dict {LOC T22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[0]}]
|
||||
set_property -dict {LOC R22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[0]}]
|
||||
set_property -dict {LOC N22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[1]}]
|
||||
set_property -dict {LOC N21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[1]}]
|
||||
set_property -dict {LOC J21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[2]}]
|
||||
set_property -dict {LOC H21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[2]}]
|
||||
set_property -dict {LOC M22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[3]}]
|
||||
set_property -dict {LOC L22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[3]}]
|
||||
set_property -dict {LOC L20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[4]}]
|
||||
set_property -dict {LOC K20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[4]}]
|
||||
set_property -dict {LOC K18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[5]}]
|
||||
set_property -dict {LOC K17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[5]}]
|
||||
set_property -dict {LOC P19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[6]}]
|
||||
set_property -dict {LOC P18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[6]}]
|
||||
set_property -dict {LOC N17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[7]}]
|
||||
set_property -dict {LOC M17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[7]}]
|
||||
set_property -dict {LOC A25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[8]}]
|
||||
set_property -dict {LOC A24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[8]}]
|
||||
set_property -dict {LOC D24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[9]}]
|
||||
set_property -dict {LOC D23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[9]}]
|
||||
set_property -dict {LOC C17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[10]}]
|
||||
set_property -dict {LOC B17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[10]}]
|
||||
set_property -dict {LOC B19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[11]}]
|
||||
set_property -dict {LOC A19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[11]}]
|
||||
set_property -dict {LOC F18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[12]}]
|
||||
set_property -dict {LOC F17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[12]}]
|
||||
set_property -dict {LOC H19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[13]}]
|
||||
set_property -dict {LOC G19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[13]}]
|
||||
set_property -dict {LOC F23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[14]}]
|
||||
set_property -dict {LOC E23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[14]}]
|
||||
set_property -dict {LOC H23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[15]}]
|
||||
set_property -dict {LOC H22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[15]}]
|
||||
set_property -dict {LOC R16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[16]}]
|
||||
set_property -dict {LOC P15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[16]}]
|
||||
set_property -dict {LOC T13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[17]}]
|
||||
set_property -dict {LOC R13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[17]}]
|
||||
|
||||
@ -145,6 +145,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
|
||||
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
|
||||
IP_TCL_FILES += ip/eth_xcvr_gty.tcl
|
||||
IP_TCL_FILES += ip/cms.tcl
|
||||
IP_TCL_FILES += ip/ddr4_0.tcl
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
@ -148,6 +148,12 @@ dict set params MAX_TX_SIZE "9214"
|
||||
dict set params MAX_RX_SIZE "9214"
|
||||
dict set params TX_RAM_SIZE "32768"
|
||||
dict set params RX_RAM_SIZE "131072"
|
||||
|
||||
# RAM configuration
|
||||
dict set params DDR_CH "4"
|
||||
dict set params DDR_ENABLE "1"
|
||||
dict set params AXI_DDR_ID_WIDTH "8"
|
||||
dict set params AXI_DDR_MAX_BURST_LEN "256"
|
||||
|
||||
# Application block configuration
|
||||
dict set params APP_ID "32'h00000000"
|
||||
@ -200,6 +206,19 @@ dict set params STAT_PCIE_ENABLE "1"
|
||||
dict set params STAT_INC_WIDTH "24"
|
||||
dict set params STAT_ID_WIDTH "12"
|
||||
|
||||
# DDR4 MIG settings
|
||||
if {[dict get $params DDR_ENABLE]} {
|
||||
set ddr4 [get_ips ddr4_0]
|
||||
|
||||
# set AXI ID width
|
||||
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
|
||||
|
||||
# extract AXI configuration
|
||||
dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4]
|
||||
dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4]
|
||||
dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1]
|
||||
}
|
||||
|
||||
# PCIe IP core settings
|
||||
set pcie [get_ips pcie4_uscale_plus_0]
|
||||
|
||||
|
||||
@ -145,6 +145,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
|
||||
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
|
||||
IP_TCL_FILES += ip/eth_xcvr_gty.tcl
|
||||
IP_TCL_FILES += ip/cms.tcl
|
||||
IP_TCL_FILES += ip/ddr4_0.tcl
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
@ -148,6 +148,12 @@ dict set params MAX_TX_SIZE "9214"
|
||||
dict set params MAX_RX_SIZE "9214"
|
||||
dict set params TX_RAM_SIZE "32768"
|
||||
dict set params RX_RAM_SIZE "32768"
|
||||
|
||||
# RAM configuration
|
||||
dict set params DDR_CH "4"
|
||||
dict set params DDR_ENABLE "1"
|
||||
dict set params AXI_DDR_ID_WIDTH "8"
|
||||
dict set params AXI_DDR_MAX_BURST_LEN "256"
|
||||
|
||||
# Application block configuration
|
||||
dict set params APP_ID "32'h00000000"
|
||||
@ -200,6 +206,19 @@ dict set params STAT_PCIE_ENABLE "1"
|
||||
dict set params STAT_INC_WIDTH "24"
|
||||
dict set params STAT_ID_WIDTH "12"
|
||||
|
||||
# DDR4 MIG settings
|
||||
if {[dict get $params DDR_ENABLE]} {
|
||||
set ddr4 [get_ips ddr4_0]
|
||||
|
||||
# set AXI ID width
|
||||
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
|
||||
|
||||
# extract AXI configuration
|
||||
dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4]
|
||||
dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4]
|
||||
dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1]
|
||||
}
|
||||
|
||||
# PCIe IP core settings
|
||||
set pcie [get_ips pcie4_uscale_plus_0]
|
||||
|
||||
|
||||
17
fpga/mqnic/AU200/fpga_25g/ip/ddr4_0.tcl
Normal file
17
fpga/mqnic/AU200/fpga_25g/ip/ddr4_0.tcl
Normal file
@ -0,0 +1,17 @@
|
||||
|
||||
create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0
|
||||
|
||||
set_property -dict [list \
|
||||
CONFIG.C0.DDR4_AxiSelection {true} \
|
||||
CONFIG.C0.DDR4_AxiDataWidth {512} \
|
||||
CONFIG.C0.DDR4_AxiIDWidth {8} \
|
||||
CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \
|
||||
CONFIG.C0.DDR4_TimePeriod {833} \
|
||||
CONFIG.C0.DDR4_InputClockPeriod {3332} \
|
||||
CONFIG.C0.DDR4_MemoryType {RDIMMs} \
|
||||
CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PZ-2G3} \
|
||||
CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \
|
||||
CONFIG.C0.DDR4_CasLatency {17} \
|
||||
CONFIG.C0.DDR4_CasWriteLatency {12} \
|
||||
CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV}
|
||||
] [get_ips ddr4_0]
|
||||
@ -112,6 +112,15 @@ module fpga #
|
||||
parameter TX_RAM_SIZE = 32768,
|
||||
parameter RX_RAM_SIZE = 32768,
|
||||
|
||||
// RAM configuration
|
||||
parameter DDR_CH = 4,
|
||||
parameter DDR_ENABLE = 1,
|
||||
parameter AXI_DDR_DATA_WIDTH = 512,
|
||||
parameter AXI_DDR_ADDR_WIDTH = 34,
|
||||
parameter AXI_DDR_ID_WIDTH = 8,
|
||||
parameter AXI_DDR_MAX_BURST_LEN = 256,
|
||||
parameter AXI_DDR_NARROW_BURST = 0,
|
||||
|
||||
// Application block configuration
|
||||
parameter APP_ID = 32'h00000000,
|
||||
parameter APP_ENABLE = 0,
|
||||
@ -177,6 +186,18 @@ module fpga #
|
||||
parameter STAT_ID_WIDTH = 12
|
||||
)
|
||||
(
|
||||
/*
|
||||
* Clock and reset
|
||||
*/
|
||||
input wire clk_300mhz_0_p,
|
||||
input wire clk_300mhz_0_n,
|
||||
input wire clk_300mhz_1_p,
|
||||
input wire clk_300mhz_1_n,
|
||||
input wire clk_300mhz_2_p,
|
||||
input wire clk_300mhz_2_n,
|
||||
input wire clk_300mhz_3_p,
|
||||
input wire clk_300mhz_3_n,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
@ -260,7 +281,70 @@ module fpga #
|
||||
input wire qsfp1_intl,
|
||||
output wire qsfp1_lpmode,
|
||||
output wire qsfp1_refclk_reset,
|
||||
output wire [1:0] qsfp1_fs
|
||||
output wire [1:0] qsfp1_fs,
|
||||
|
||||
/*
|
||||
* DDR4
|
||||
*/
|
||||
output wire [16:0] ddr4_c0_adr,
|
||||
output wire [1:0] ddr4_c0_ba,
|
||||
output wire [1:0] ddr4_c0_bg,
|
||||
output wire [0:0] ddr4_c0_ck_t,
|
||||
output wire [0:0] ddr4_c0_ck_c,
|
||||
output wire [0:0] ddr4_c0_cke,
|
||||
output wire [0:0] ddr4_c0_cs_n,
|
||||
output wire ddr4_c0_act_n,
|
||||
output wire [0:0] ddr4_c0_odt,
|
||||
output wire ddr4_c0_par,
|
||||
output wire ddr4_c0_reset_n,
|
||||
inout wire [71:0] ddr4_c0_dq,
|
||||
inout wire [17:0] ddr4_c0_dqs_t,
|
||||
inout wire [17:0] ddr4_c0_dqs_c,
|
||||
|
||||
output wire [16:0] ddr4_c1_adr,
|
||||
output wire [1:0] ddr4_c1_ba,
|
||||
output wire [1:0] ddr4_c1_bg,
|
||||
output wire [0:0] ddr4_c1_ck_t,
|
||||
output wire [0:0] ddr4_c1_ck_c,
|
||||
output wire [0:0] ddr4_c1_cke,
|
||||
output wire [0:0] ddr4_c1_cs_n,
|
||||
output wire ddr4_c1_act_n,
|
||||
output wire [0:0] ddr4_c1_odt,
|
||||
output wire ddr4_c1_par,
|
||||
output wire ddr4_c1_reset_n,
|
||||
inout wire [71:0] ddr4_c1_dq,
|
||||
inout wire [17:0] ddr4_c1_dqs_t,
|
||||
inout wire [17:0] ddr4_c1_dqs_c,
|
||||
|
||||
output wire [16:0] ddr4_c2_adr,
|
||||
output wire [1:0] ddr4_c2_ba,
|
||||
output wire [1:0] ddr4_c2_bg,
|
||||
output wire [0:0] ddr4_c2_ck_t,
|
||||
output wire [0:0] ddr4_c2_ck_c,
|
||||
output wire [0:0] ddr4_c2_cke,
|
||||
output wire [0:0] ddr4_c2_cs_n,
|
||||
output wire ddr4_c2_act_n,
|
||||
output wire [0:0] ddr4_c2_odt,
|
||||
output wire ddr4_c2_par,
|
||||
output wire ddr4_c2_reset_n,
|
||||
inout wire [71:0] ddr4_c2_dq,
|
||||
inout wire [17:0] ddr4_c2_dqs_t,
|
||||
inout wire [17:0] ddr4_c2_dqs_c,
|
||||
|
||||
output wire [16:0] ddr4_c3_adr,
|
||||
output wire [1:0] ddr4_c3_ba,
|
||||
output wire [1:0] ddr4_c3_bg,
|
||||
output wire [0:0] ddr4_c3_ck_t,
|
||||
output wire [0:0] ddr4_c3_ck_c,
|
||||
output wire [0:0] ddr4_c3_cke,
|
||||
output wire [0:0] ddr4_c3_cs_n,
|
||||
output wire ddr4_c3_act_n,
|
||||
output wire [0:0] ddr4_c3_odt,
|
||||
output wire ddr4_c3_par,
|
||||
output wire ddr4_c3_reset_n,
|
||||
inout wire [71:0] ddr4_c3_dq,
|
||||
inout wire [17:0] ddr4_c3_dqs_t,
|
||||
inout wire [17:0] ddr4_c3_dqs_c
|
||||
);
|
||||
|
||||
// PTP configuration
|
||||
@ -274,6 +358,9 @@ parameter IF_PTP_PERIOD_FNS = 16'h6666;
|
||||
// Interface configuration
|
||||
parameter TX_TAG_WIDTH = 16;
|
||||
|
||||
// RAM configuration
|
||||
parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8);
|
||||
|
||||
// Ethernet interface configuration
|
||||
parameter XGMII_DATA_WIDTH = 64;
|
||||
parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8;
|
||||
@ -1487,6 +1574,519 @@ assign ptp_clk = qsfp0_mgt_refclk_1_bufg;
|
||||
assign ptp_rst = qsfp0_rst;
|
||||
assign ptp_sample_clk = clk_125mhz_int;
|
||||
|
||||
// DDR4
|
||||
wire [DDR_CH-1:0] ddr_clk;
|
||||
wire [DDR_CH-1:0] ddr_rst;
|
||||
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid;
|
||||
wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr;
|
||||
wire [DDR_CH*8-1:0] m_axi_ddr_awlen;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_awsize;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_awburst;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_awlock;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_awcache;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_awprot;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_awqos;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_awvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_awready;
|
||||
wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata;
|
||||
wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_wlast;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_wvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_wready;
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_bresp;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_bvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_bready;
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid;
|
||||
wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr;
|
||||
wire [DDR_CH*8-1:0] m_axi_ddr_arlen;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_arsize;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_arburst;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_arlock;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_arcache;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_arprot;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_arqos;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_arvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_arready;
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid;
|
||||
wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_rresp;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_rlast;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_rvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_rready;
|
||||
|
||||
wire [DDR_CH-1:0] ddr_status;
|
||||
|
||||
generate
|
||||
|
||||
if (DDR_ENABLE && DDR_CH > 0) begin
|
||||
|
||||
ddr4_0 ddr4_c0_inst (
|
||||
.c0_sys_clk_p(clk_300mhz_0_p),
|
||||
.c0_sys_clk_n(clk_300mhz_0_n),
|
||||
.sys_rst(pcie_user_reset),
|
||||
|
||||
.c0_init_calib_complete(ddr_status[0 +: 1]),
|
||||
.c0_ddr4_interrupt(),
|
||||
.dbg_clk(),
|
||||
.dbg_bus(),
|
||||
|
||||
.c0_ddr4_adr(ddr4_c0_adr),
|
||||
.c0_ddr4_ba(ddr4_c0_ba),
|
||||
.c0_ddr4_cke(ddr4_c0_cke),
|
||||
.c0_ddr4_cs_n(ddr4_c0_cs_n),
|
||||
.c0_ddr4_dq(ddr4_c0_dq),
|
||||
.c0_ddr4_dqs_t(ddr4_c0_dqs_t),
|
||||
.c0_ddr4_dqs_c(ddr4_c0_dqs_c),
|
||||
.c0_ddr4_odt(ddr4_c0_odt),
|
||||
.c0_ddr4_parity(ddr4_c0_par),
|
||||
.c0_ddr4_bg(ddr4_c0_bg),
|
||||
.c0_ddr4_reset_n(ddr4_c0_reset_n),
|
||||
.c0_ddr4_act_n(ddr4_c0_act_n),
|
||||
.c0_ddr4_ck_t(ddr4_c0_ck_t),
|
||||
.c0_ddr4_ck_c(ddr4_c0_ck_c),
|
||||
|
||||
.c0_ddr4_ui_clk(ddr_clk[0 +: 1]),
|
||||
.c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]),
|
||||
|
||||
.c0_ddr4_aresetn(!ddr_rst[0 +: 1]),
|
||||
|
||||
.c0_ddr4_s_axi_ctrl_awvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_awready(),
|
||||
.c0_ddr4_s_axi_ctrl_awaddr(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_wvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_wready(),
|
||||
.c0_ddr4_s_axi_ctrl_wdata(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_bvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_bready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_bresp(),
|
||||
.c0_ddr4_s_axi_ctrl_arvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_arready(),
|
||||
.c0_ddr4_s_axi_ctrl_araddr(31'd0),
|
||||
.c0_ddr4_s_axi_ctrl_rvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_rready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_rdata(),
|
||||
.c0_ddr4_s_axi_ctrl_rresp(),
|
||||
|
||||
.c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]),
|
||||
.c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]),
|
||||
.c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]),
|
||||
.c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]),
|
||||
.c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]),
|
||||
.c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]),
|
||||
.c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]),
|
||||
.c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH])
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign ddr4_c0_adr = {17{1'bz}};
|
||||
assign ddr4_c0_ba = {2{1'bz}};
|
||||
assign ddr4_c0_bg = {2{1'bz}};
|
||||
assign ddr4_c0_cke = 1'bz;
|
||||
assign ddr4_c0_cs_n = 1'bz;
|
||||
assign ddr4_c0_act_n = 1'bz;
|
||||
assign ddr4_c0_odt = 1'bz;
|
||||
assign ddr4_c0_par = 1'bz;
|
||||
assign ddr4_c0_reset_n = 1'b0;
|
||||
assign ddr4_c0_dq = {72{1'bz}};
|
||||
assign ddr4_c0_dqs_t = {18{1'bz}};
|
||||
assign ddr4_c0_dqs_c = {18{1'bz}};
|
||||
|
||||
OBUFTDS ddr4_c0_ck_obuftds_inst (
|
||||
.I(1'b0),
|
||||
.T(1'b1),
|
||||
.O(ddr4_c0_ck_t),
|
||||
.OB(ddr4_c0_ck_c)
|
||||
);
|
||||
|
||||
assign ddr_clk = 0;
|
||||
assign ddr_rst = 0;
|
||||
|
||||
assign m_axi_ddr_awready = 0;
|
||||
assign m_axi_ddr_wready = 0;
|
||||
assign m_axi_ddr_bid = 0;
|
||||
assign m_axi_ddr_bresp = 0;
|
||||
assign m_axi_ddr_bvalid = 0;
|
||||
assign m_axi_ddr_arready = 0;
|
||||
assign m_axi_ddr_rid = 0;
|
||||
assign m_axi_ddr_rdata = 0;
|
||||
assign m_axi_ddr_rresp = 0;
|
||||
assign m_axi_ddr_rlast = 0;
|
||||
assign m_axi_ddr_rvalid = 0;
|
||||
|
||||
assign ddr_status = 0;
|
||||
|
||||
end
|
||||
|
||||
if (DDR_ENABLE && DDR_CH > 1) begin
|
||||
|
||||
ddr4_0 ddr4_c1_inst (
|
||||
.c0_sys_clk_p(clk_300mhz_1_p),
|
||||
.c0_sys_clk_n(clk_300mhz_1_n),
|
||||
.sys_rst(pcie_user_reset),
|
||||
|
||||
.c0_init_calib_complete(ddr_status[1 +: 1]),
|
||||
.c0_ddr4_interrupt(),
|
||||
.dbg_clk(),
|
||||
.dbg_bus(),
|
||||
|
||||
.c0_ddr4_adr(ddr4_c1_adr),
|
||||
.c0_ddr4_ba(ddr4_c1_ba),
|
||||
.c0_ddr4_cke(ddr4_c1_cke),
|
||||
.c0_ddr4_cs_n(ddr4_c1_cs_n),
|
||||
.c0_ddr4_dq(ddr4_c1_dq),
|
||||
.c0_ddr4_dqs_t(ddr4_c1_dqs_t),
|
||||
.c0_ddr4_dqs_c(ddr4_c1_dqs_c),
|
||||
.c0_ddr4_odt(ddr4_c1_odt),
|
||||
.c0_ddr4_parity(ddr4_c1_par),
|
||||
.c0_ddr4_bg(ddr4_c1_bg),
|
||||
.c0_ddr4_reset_n(ddr4_c1_reset_n),
|
||||
.c0_ddr4_act_n(ddr4_c1_act_n),
|
||||
.c0_ddr4_ck_t(ddr4_c1_ck_t),
|
||||
.c0_ddr4_ck_c(ddr4_c1_ck_c),
|
||||
|
||||
.c0_ddr4_ui_clk(ddr_clk[1 +: 1]),
|
||||
.c0_ddr4_ui_clk_sync_rst(ddr_rst[1 +: 1]),
|
||||
|
||||
.c0_ddr4_aresetn(!ddr_rst[1 +: 1]),
|
||||
|
||||
.c0_ddr4_s_axi_ctrl_awvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_awready(),
|
||||
.c0_ddr4_s_axi_ctrl_awaddr(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_wvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_wready(),
|
||||
.c0_ddr4_s_axi_ctrl_wdata(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_bvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_bready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_bresp(),
|
||||
.c0_ddr4_s_axi_ctrl_arvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_arready(),
|
||||
.c0_ddr4_s_axi_ctrl_araddr(31'd0),
|
||||
.c0_ddr4_s_axi_ctrl_rvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_rready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_rdata(),
|
||||
.c0_ddr4_s_axi_ctrl_rresp(),
|
||||
|
||||
.c0_ddr4_s_axi_awid(m_axi_ddr_awid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[1*8 +: 8]),
|
||||
.c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[1*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[1*2 +: 2]),
|
||||
.c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[1 +: 1]),
|
||||
.c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[1*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[1*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[1*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_awready(m_axi_ddr_awready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]),
|
||||
.c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[1*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]),
|
||||
.c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[1 +: 1]),
|
||||
.c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_wready(m_axi_ddr_wready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_bready(m_axi_ddr_bready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_bid(m_axi_ddr_bid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[1*2 +: 2]),
|
||||
.c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_arid(m_axi_ddr_arid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[1*8 +: 8]),
|
||||
.c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[1*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[1*2 +: 2]),
|
||||
.c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[1 +: 1]),
|
||||
.c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[1*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[1*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[1*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_arready(m_axi_ddr_arready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_rready(m_axi_ddr_rready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[1 +: 1]),
|
||||
.c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[1*2 +: 2]),
|
||||
.c0_ddr4_s_axi_rid(m_axi_ddr_rid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH])
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign ddr4_c1_adr = {17{1'bz}};
|
||||
assign ddr4_c1_ba = {2{1'bz}};
|
||||
assign ddr4_c1_bg = {2{1'bz}};
|
||||
assign ddr4_c1_cke = 1'bz;
|
||||
assign ddr4_c1_cs_n = 1'bz;
|
||||
assign ddr4_c1_act_n = 1'bz;
|
||||
assign ddr4_c1_odt = 1'bz;
|
||||
assign ddr4_c1_par = 1'bz;
|
||||
assign ddr4_c1_reset_n = 1'b0;
|
||||
assign ddr4_c1_dq = {72{1'bz}};
|
||||
assign ddr4_c1_dqs_t = {18{1'bz}};
|
||||
assign ddr4_c1_dqs_c = {18{1'bz}};
|
||||
|
||||
OBUFTDS ddr4_c1_ck_obuftds_inst (
|
||||
.I(1'b0),
|
||||
.T(1'b1),
|
||||
.O(ddr4_c1_ck_t),
|
||||
.OB(ddr4_c1_ck_c)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
if (DDR_ENABLE && DDR_CH > 2) begin
|
||||
|
||||
ddr4_0 ddr4_c2_inst (
|
||||
.c0_sys_clk_p(clk_300mhz_2_p),
|
||||
.c0_sys_clk_n(clk_300mhz_2_n),
|
||||
.sys_rst(pcie_user_reset),
|
||||
|
||||
.c0_init_calib_complete(ddr_status[2 +: 1]),
|
||||
.c0_ddr4_interrupt(),
|
||||
.dbg_clk(),
|
||||
.dbg_bus(),
|
||||
|
||||
.c0_ddr4_adr(ddr4_c2_adr),
|
||||
.c0_ddr4_ba(ddr4_c2_ba),
|
||||
.c0_ddr4_cke(ddr4_c2_cke),
|
||||
.c0_ddr4_cs_n(ddr4_c2_cs_n),
|
||||
.c0_ddr4_dq(ddr4_c2_dq),
|
||||
.c0_ddr4_dqs_t(ddr4_c2_dqs_t),
|
||||
.c0_ddr4_dqs_c(ddr4_c2_dqs_c),
|
||||
.c0_ddr4_odt(ddr4_c2_odt),
|
||||
.c0_ddr4_parity(ddr4_c2_par),
|
||||
.c0_ddr4_bg(ddr4_c2_bg),
|
||||
.c0_ddr4_reset_n(ddr4_c2_reset_n),
|
||||
.c0_ddr4_act_n(ddr4_c2_act_n),
|
||||
.c0_ddr4_ck_t(ddr4_c2_ck_t),
|
||||
.c0_ddr4_ck_c(ddr4_c2_ck_c),
|
||||
|
||||
.c0_ddr4_ui_clk(ddr_clk[2 +: 1]),
|
||||
.c0_ddr4_ui_clk_sync_rst(ddr_rst[2 +: 1]),
|
||||
|
||||
.c0_ddr4_aresetn(!ddr_rst[2 +: 1]),
|
||||
|
||||
.c0_ddr4_s_axi_ctrl_awvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_awready(),
|
||||
.c0_ddr4_s_axi_ctrl_awaddr(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_wvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_wready(),
|
||||
.c0_ddr4_s_axi_ctrl_wdata(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_bvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_bready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_bresp(),
|
||||
.c0_ddr4_s_axi_ctrl_arvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_arready(),
|
||||
.c0_ddr4_s_axi_ctrl_araddr(31'd0),
|
||||
.c0_ddr4_s_axi_ctrl_rvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_rready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_rdata(),
|
||||
.c0_ddr4_s_axi_ctrl_rresp(),
|
||||
|
||||
.c0_ddr4_s_axi_awid(m_axi_ddr_awid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[2*8 +: 8]),
|
||||
.c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[2*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[2*2 +: 2]),
|
||||
.c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[2 +: 1]),
|
||||
.c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[2*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[2*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[2*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[2 +: 1]),
|
||||
.c0_ddr4_s_axi_awready(m_axi_ddr_awready[2 +: 1]),
|
||||
.c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]),
|
||||
.c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[2*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]),
|
||||
.c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[2 +: 1]),
|
||||
.c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[2 +: 1]),
|
||||
.c0_ddr4_s_axi_wready(m_axi_ddr_wready[2 +: 1]),
|
||||
.c0_ddr4_s_axi_bready(m_axi_ddr_bready[2 +: 1]),
|
||||
.c0_ddr4_s_axi_bid(m_axi_ddr_bid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[2*2 +: 2]),
|
||||
.c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[2 +: 1]),
|
||||
.c0_ddr4_s_axi_arid(m_axi_ddr_arid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[2*8 +: 8]),
|
||||
.c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[2*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[2*2 +: 2]),
|
||||
.c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[2 +: 1]),
|
||||
.c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[2*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[2*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[2*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[2 +: 1]),
|
||||
.c0_ddr4_s_axi_arready(m_axi_ddr_arready[2 +: 1]),
|
||||
.c0_ddr4_s_axi_rready(m_axi_ddr_rready[2 +: 1]),
|
||||
.c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[2 +: 1]),
|
||||
.c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[2 +: 1]),
|
||||
.c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[2*2 +: 2]),
|
||||
.c0_ddr4_s_axi_rid(m_axi_ddr_rid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH])
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign ddr4_c2_adr = {17{1'bz}};
|
||||
assign ddr4_c2_ba = {2{1'bz}};
|
||||
assign ddr4_c2_bg = {2{1'bz}};
|
||||
assign ddr4_c2_cke = 1'bz;
|
||||
assign ddr4_c2_cs_n = 1'bz;
|
||||
assign ddr4_c2_act_n = 1'bz;
|
||||
assign ddr4_c2_odt = 1'bz;
|
||||
assign ddr4_c2_par = 1'bz;
|
||||
assign ddr4_c2_reset_n = 1'b0;
|
||||
assign ddr4_c2_dq = {72{1'bz}};
|
||||
assign ddr4_c2_dqs_t = {18{1'bz}};
|
||||
assign ddr4_c2_dqs_c = {18{1'bz}};
|
||||
|
||||
OBUFTDS ddr4_c2_ck_obuftds_inst (
|
||||
.I(1'b0),
|
||||
.T(1'b1),
|
||||
.O(ddr4_c2_ck_t),
|
||||
.OB(ddr4_c2_ck_c)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
if (DDR_ENABLE && DDR_CH > 3) begin
|
||||
|
||||
ddr4_0 ddr4_c3_inst (
|
||||
.c0_sys_clk_p(clk_300mhz_3_p),
|
||||
.c0_sys_clk_n(clk_300mhz_3_n),
|
||||
.sys_rst(pcie_user_reset),
|
||||
|
||||
.c0_init_calib_complete(ddr_status[3 +: 1]),
|
||||
.c0_ddr4_interrupt(),
|
||||
.dbg_clk(),
|
||||
.dbg_bus(),
|
||||
|
||||
.c0_ddr4_adr(ddr4_c3_adr),
|
||||
.c0_ddr4_ba(ddr4_c3_ba),
|
||||
.c0_ddr4_cke(ddr4_c3_cke),
|
||||
.c0_ddr4_cs_n(ddr4_c3_cs_n),
|
||||
.c0_ddr4_dq(ddr4_c3_dq),
|
||||
.c0_ddr4_dqs_t(ddr4_c3_dqs_t),
|
||||
.c0_ddr4_dqs_c(ddr4_c3_dqs_c),
|
||||
.c0_ddr4_odt(ddr4_c3_odt),
|
||||
.c0_ddr4_parity(ddr4_c3_par),
|
||||
.c0_ddr4_bg(ddr4_c3_bg),
|
||||
.c0_ddr4_reset_n(ddr4_c3_reset_n),
|
||||
.c0_ddr4_act_n(ddr4_c3_act_n),
|
||||
.c0_ddr4_ck_t(ddr4_c3_ck_t),
|
||||
.c0_ddr4_ck_c(ddr4_c3_ck_c),
|
||||
|
||||
.c0_ddr4_ui_clk(ddr_clk[3 +: 1]),
|
||||
.c0_ddr4_ui_clk_sync_rst(ddr_rst[3 +: 1]),
|
||||
|
||||
.c0_ddr4_aresetn(!ddr_rst[3 +: 1]),
|
||||
|
||||
.c0_ddr4_s_axi_ctrl_awvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_awready(),
|
||||
.c0_ddr4_s_axi_ctrl_awaddr(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_wvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_wready(),
|
||||
.c0_ddr4_s_axi_ctrl_wdata(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_bvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_bready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_bresp(),
|
||||
.c0_ddr4_s_axi_ctrl_arvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_arready(),
|
||||
.c0_ddr4_s_axi_ctrl_araddr(31'd0),
|
||||
.c0_ddr4_s_axi_ctrl_rvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_rready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_rdata(),
|
||||
.c0_ddr4_s_axi_ctrl_rresp(),
|
||||
|
||||
.c0_ddr4_s_axi_awid(m_axi_ddr_awid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[3*8 +: 8]),
|
||||
.c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[3*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[3*2 +: 2]),
|
||||
.c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[3 +: 1]),
|
||||
.c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[3*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[3*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[3*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[3 +: 1]),
|
||||
.c0_ddr4_s_axi_awready(m_axi_ddr_awready[3 +: 1]),
|
||||
.c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]),
|
||||
.c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[3*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]),
|
||||
.c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[3 +: 1]),
|
||||
.c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[3 +: 1]),
|
||||
.c0_ddr4_s_axi_wready(m_axi_ddr_wready[3 +: 1]),
|
||||
.c0_ddr4_s_axi_bready(m_axi_ddr_bready[3 +: 1]),
|
||||
.c0_ddr4_s_axi_bid(m_axi_ddr_bid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[3*2 +: 2]),
|
||||
.c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[3 +: 1]),
|
||||
.c0_ddr4_s_axi_arid(m_axi_ddr_arid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[3*8 +: 8]),
|
||||
.c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[3*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[3*2 +: 2]),
|
||||
.c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[3 +: 1]),
|
||||
.c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[3*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[3*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[3*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[3 +: 1]),
|
||||
.c0_ddr4_s_axi_arready(m_axi_ddr_arready[3 +: 1]),
|
||||
.c0_ddr4_s_axi_rready(m_axi_ddr_rready[3 +: 1]),
|
||||
.c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[3 +: 1]),
|
||||
.c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[3 +: 1]),
|
||||
.c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[3*2 +: 2]),
|
||||
.c0_ddr4_s_axi_rid(m_axi_ddr_rid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH])
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign ddr4_c3_adr = {17{1'bz}};
|
||||
assign ddr4_c3_ba = {2{1'bz}};
|
||||
assign ddr4_c3_bg = {2{1'bz}};
|
||||
assign ddr4_c3_cke = 1'bz;
|
||||
assign ddr4_c3_cs_n = 1'bz;
|
||||
assign ddr4_c3_act_n = 1'bz;
|
||||
assign ddr4_c3_odt = 1'bz;
|
||||
assign ddr4_c3_par = 1'bz;
|
||||
assign ddr4_c3_reset_n = 1'b0;
|
||||
assign ddr4_c3_dq = {72{1'bz}};
|
||||
assign ddr4_c3_dqs_t = {18{1'bz}};
|
||||
assign ddr4_c3_dqs_c = {18{1'bz}};
|
||||
|
||||
OBUFTDS ddr4_c3_ck_obuftds_inst (
|
||||
.I(1'b0),
|
||||
.T(1'b1),
|
||||
.O(ddr4_c3_ck_t),
|
||||
.OB(ddr4_c3_ck_c)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
fpga_core #(
|
||||
// FW and board IDs
|
||||
.FPGA_ID(FPGA_ID),
|
||||
@ -1563,6 +2163,16 @@ fpga_core #(
|
||||
.TX_RAM_SIZE(TX_RAM_SIZE),
|
||||
.RX_RAM_SIZE(RX_RAM_SIZE),
|
||||
|
||||
// RAM configuration
|
||||
.DDR_CH(DDR_CH),
|
||||
.DDR_ENABLE(DDR_ENABLE),
|
||||
.AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH),
|
||||
.AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH),
|
||||
.AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH),
|
||||
.AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH),
|
||||
.AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN),
|
||||
.AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST),
|
||||
|
||||
// Application block configuration
|
||||
.APP_ID(APP_ID),
|
||||
.APP_ENABLE(APP_ENABLE),
|
||||
@ -1868,6 +2478,52 @@ core_inst (
|
||||
.qsfp1_intl(qsfp1_intl_int),
|
||||
.qsfp1_lpmode(qsfp1_lpmode),
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
.ddr_clk(ddr_clk),
|
||||
.ddr_rst(ddr_rst),
|
||||
|
||||
.m_axi_ddr_awid(m_axi_ddr_awid),
|
||||
.m_axi_ddr_awaddr(m_axi_ddr_awaddr),
|
||||
.m_axi_ddr_awlen(m_axi_ddr_awlen),
|
||||
.m_axi_ddr_awsize(m_axi_ddr_awsize),
|
||||
.m_axi_ddr_awburst(m_axi_ddr_awburst),
|
||||
.m_axi_ddr_awlock(m_axi_ddr_awlock),
|
||||
.m_axi_ddr_awcache(m_axi_ddr_awcache),
|
||||
.m_axi_ddr_awprot(m_axi_ddr_awprot),
|
||||
.m_axi_ddr_awqos(m_axi_ddr_awqos),
|
||||
.m_axi_ddr_awvalid(m_axi_ddr_awvalid),
|
||||
.m_axi_ddr_awready(m_axi_ddr_awready),
|
||||
.m_axi_ddr_wdata(m_axi_ddr_wdata),
|
||||
.m_axi_ddr_wstrb(m_axi_ddr_wstrb),
|
||||
.m_axi_ddr_wlast(m_axi_ddr_wlast),
|
||||
.m_axi_ddr_wvalid(m_axi_ddr_wvalid),
|
||||
.m_axi_ddr_wready(m_axi_ddr_wready),
|
||||
.m_axi_ddr_bid(m_axi_ddr_bid),
|
||||
.m_axi_ddr_bresp(m_axi_ddr_bresp),
|
||||
.m_axi_ddr_bvalid(m_axi_ddr_bvalid),
|
||||
.m_axi_ddr_bready(m_axi_ddr_bready),
|
||||
.m_axi_ddr_arid(m_axi_ddr_arid),
|
||||
.m_axi_ddr_araddr(m_axi_ddr_araddr),
|
||||
.m_axi_ddr_arlen(m_axi_ddr_arlen),
|
||||
.m_axi_ddr_arsize(m_axi_ddr_arsize),
|
||||
.m_axi_ddr_arburst(m_axi_ddr_arburst),
|
||||
.m_axi_ddr_arlock(m_axi_ddr_arlock),
|
||||
.m_axi_ddr_arcache(m_axi_ddr_arcache),
|
||||
.m_axi_ddr_arprot(m_axi_ddr_arprot),
|
||||
.m_axi_ddr_arqos(m_axi_ddr_arqos),
|
||||
.m_axi_ddr_arvalid(m_axi_ddr_arvalid),
|
||||
.m_axi_ddr_arready(m_axi_ddr_arready),
|
||||
.m_axi_ddr_rid(m_axi_ddr_rid),
|
||||
.m_axi_ddr_rdata(m_axi_ddr_rdata),
|
||||
.m_axi_ddr_rresp(m_axi_ddr_rresp),
|
||||
.m_axi_ddr_rlast(m_axi_ddr_rlast),
|
||||
.m_axi_ddr_rvalid(m_axi_ddr_rvalid),
|
||||
.m_axi_ddr_rready(m_axi_ddr_rready),
|
||||
|
||||
.ddr_status(ddr_status),
|
||||
|
||||
/*
|
||||
* QSPI flash
|
||||
*/
|
||||
|
||||
@ -122,6 +122,16 @@ module fpga_core #
|
||||
parameter TX_RAM_SIZE = 32768,
|
||||
parameter RX_RAM_SIZE = 32768,
|
||||
|
||||
// RAM configuration
|
||||
parameter DDR_CH = 4,
|
||||
parameter DDR_ENABLE = 1,
|
||||
parameter AXI_DDR_DATA_WIDTH = 512,
|
||||
parameter AXI_DDR_ADDR_WIDTH = 34,
|
||||
parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8),
|
||||
parameter AXI_DDR_ID_WIDTH = 8,
|
||||
parameter AXI_DDR_MAX_BURST_LEN = 256,
|
||||
parameter AXI_DDR_NARROW_BURST = 0,
|
||||
|
||||
// Application block configuration
|
||||
parameter APP_ID = 32'h00000000,
|
||||
parameter APP_ENABLE = 0,
|
||||
@ -429,6 +439,52 @@ module fpga_core #
|
||||
input wire qsfp1_intl,
|
||||
output wire qsfp1_lpmode,
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
input wire [DDR_CH-1:0] ddr_clk,
|
||||
input wire [DDR_CH-1:0] ddr_rst,
|
||||
|
||||
output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid,
|
||||
output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr,
|
||||
output wire [DDR_CH*8-1:0] m_axi_ddr_awlen,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_awsize,
|
||||
output wire [DDR_CH*2-1:0] m_axi_ddr_awburst,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_awlock,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_awcache,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_awprot,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_awqos,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_awvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_awready,
|
||||
output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata,
|
||||
output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_wlast,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_wvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_wready,
|
||||
input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid,
|
||||
input wire [DDR_CH*2-1:0] m_axi_ddr_bresp,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_bvalid,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_bready,
|
||||
output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid,
|
||||
output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr,
|
||||
output wire [DDR_CH*8-1:0] m_axi_ddr_arlen,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_arsize,
|
||||
output wire [DDR_CH*2-1:0] m_axi_ddr_arburst,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_arlock,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_arcache,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_arprot,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_arqos,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_arvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_arready,
|
||||
input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid,
|
||||
input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata,
|
||||
input wire [DDR_CH*2-1:0] m_axi_ddr_rresp,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_rlast,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_rvalid,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_rready,
|
||||
|
||||
input wire [DDR_CH-1:0] ddr_status,
|
||||
|
||||
/*
|
||||
* QSPI flash
|
||||
*/
|
||||
@ -1170,6 +1226,25 @@ mqnic_core_pcie_us #(
|
||||
.TX_RAM_SIZE(TX_RAM_SIZE),
|
||||
.RX_RAM_SIZE(RX_RAM_SIZE),
|
||||
|
||||
// RAM configuration
|
||||
.DDR_CH(DDR_CH),
|
||||
.DDR_ENABLE(DDR_ENABLE),
|
||||
.DDR_GROUP_SIZE(1),
|
||||
.AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH),
|
||||
.AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH),
|
||||
.AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH),
|
||||
.AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH),
|
||||
.AXI_DDR_AWUSER_ENABLE(0),
|
||||
.AXI_DDR_WUSER_ENABLE(0),
|
||||
.AXI_DDR_BUSER_ENABLE(0),
|
||||
.AXI_DDR_ARUSER_ENABLE(0),
|
||||
.AXI_DDR_RUSER_ENABLE(0),
|
||||
.AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN),
|
||||
.AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST),
|
||||
.AXI_DDR_FIXED_BURST(0),
|
||||
.AXI_DDR_WRAP_BURST(1),
|
||||
.HBM_ENABLE(0),
|
||||
|
||||
// Application block configuration
|
||||
.APP_ID(APP_ID),
|
||||
.APP_ENABLE(APP_ENABLE),
|
||||
@ -1447,6 +1522,108 @@ core_inst (
|
||||
|
||||
.eth_rx_status(eth_rx_status),
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
.ddr_clk(ddr_clk),
|
||||
.ddr_rst(ddr_rst),
|
||||
|
||||
.m_axi_ddr_awid(m_axi_ddr_awid),
|
||||
.m_axi_ddr_awaddr(m_axi_ddr_awaddr),
|
||||
.m_axi_ddr_awlen(m_axi_ddr_awlen),
|
||||
.m_axi_ddr_awsize(m_axi_ddr_awsize),
|
||||
.m_axi_ddr_awburst(m_axi_ddr_awburst),
|
||||
.m_axi_ddr_awlock(m_axi_ddr_awlock),
|
||||
.m_axi_ddr_awcache(m_axi_ddr_awcache),
|
||||
.m_axi_ddr_awprot(m_axi_ddr_awprot),
|
||||
.m_axi_ddr_awqos(m_axi_ddr_awqos),
|
||||
.m_axi_ddr_awuser(),
|
||||
.m_axi_ddr_awvalid(m_axi_ddr_awvalid),
|
||||
.m_axi_ddr_awready(m_axi_ddr_awready),
|
||||
.m_axi_ddr_wdata(m_axi_ddr_wdata),
|
||||
.m_axi_ddr_wstrb(m_axi_ddr_wstrb),
|
||||
.m_axi_ddr_wlast(m_axi_ddr_wlast),
|
||||
.m_axi_ddr_wuser(),
|
||||
.m_axi_ddr_wvalid(m_axi_ddr_wvalid),
|
||||
.m_axi_ddr_wready(m_axi_ddr_wready),
|
||||
.m_axi_ddr_bid(m_axi_ddr_bid),
|
||||
.m_axi_ddr_bresp(m_axi_ddr_bresp),
|
||||
.m_axi_ddr_buser(0),
|
||||
.m_axi_ddr_bvalid(m_axi_ddr_bvalid),
|
||||
.m_axi_ddr_bready(m_axi_ddr_bready),
|
||||
.m_axi_ddr_arid(m_axi_ddr_arid),
|
||||
.m_axi_ddr_araddr(m_axi_ddr_araddr),
|
||||
.m_axi_ddr_arlen(m_axi_ddr_arlen),
|
||||
.m_axi_ddr_arsize(m_axi_ddr_arsize),
|
||||
.m_axi_ddr_arburst(m_axi_ddr_arburst),
|
||||
.m_axi_ddr_arlock(m_axi_ddr_arlock),
|
||||
.m_axi_ddr_arcache(m_axi_ddr_arcache),
|
||||
.m_axi_ddr_arprot(m_axi_ddr_arprot),
|
||||
.m_axi_ddr_arqos(m_axi_ddr_arqos),
|
||||
.m_axi_ddr_aruser(),
|
||||
.m_axi_ddr_arvalid(m_axi_ddr_arvalid),
|
||||
.m_axi_ddr_arready(m_axi_ddr_arready),
|
||||
.m_axi_ddr_rid(m_axi_ddr_rid),
|
||||
.m_axi_ddr_rdata(m_axi_ddr_rdata),
|
||||
.m_axi_ddr_rresp(m_axi_ddr_rresp),
|
||||
.m_axi_ddr_rlast(m_axi_ddr_rlast),
|
||||
.m_axi_ddr_ruser(0),
|
||||
.m_axi_ddr_rvalid(m_axi_ddr_rvalid),
|
||||
.m_axi_ddr_rready(m_axi_ddr_rready),
|
||||
|
||||
.ddr_status(ddr_status),
|
||||
|
||||
/*
|
||||
* HBM
|
||||
*/
|
||||
.hbm_clk(0),
|
||||
.hbm_rst(0),
|
||||
|
||||
.m_axi_hbm_awid(),
|
||||
.m_axi_hbm_awaddr(),
|
||||
.m_axi_hbm_awlen(),
|
||||
.m_axi_hbm_awsize(),
|
||||
.m_axi_hbm_awburst(),
|
||||
.m_axi_hbm_awlock(),
|
||||
.m_axi_hbm_awcache(),
|
||||
.m_axi_hbm_awprot(),
|
||||
.m_axi_hbm_awqos(),
|
||||
.m_axi_hbm_awuser(),
|
||||
.m_axi_hbm_awvalid(),
|
||||
.m_axi_hbm_awready(0),
|
||||
.m_axi_hbm_wdata(),
|
||||
.m_axi_hbm_wstrb(),
|
||||
.m_axi_hbm_wlast(),
|
||||
.m_axi_hbm_wuser(),
|
||||
.m_axi_hbm_wvalid(),
|
||||
.m_axi_hbm_wready(0),
|
||||
.m_axi_hbm_bid(0),
|
||||
.m_axi_hbm_bresp(0),
|
||||
.m_axi_hbm_buser(0),
|
||||
.m_axi_hbm_bvalid(0),
|
||||
.m_axi_hbm_bready(),
|
||||
.m_axi_hbm_arid(),
|
||||
.m_axi_hbm_araddr(),
|
||||
.m_axi_hbm_arlen(),
|
||||
.m_axi_hbm_arsize(),
|
||||
.m_axi_hbm_arburst(),
|
||||
.m_axi_hbm_arlock(),
|
||||
.m_axi_hbm_arcache(),
|
||||
.m_axi_hbm_arprot(),
|
||||
.m_axi_hbm_arqos(),
|
||||
.m_axi_hbm_aruser(),
|
||||
.m_axi_hbm_arvalid(),
|
||||
.m_axi_hbm_arready(0),
|
||||
.m_axi_hbm_rid(0),
|
||||
.m_axi_hbm_rdata(0),
|
||||
.m_axi_hbm_rresp(0),
|
||||
.m_axi_hbm_rlast(0),
|
||||
.m_axi_hbm_ruser(0),
|
||||
.m_axi_hbm_rvalid(0),
|
||||
.m_axi_hbm_rready(),
|
||||
|
||||
.hbm_status(0),
|
||||
|
||||
/*
|
||||
* Statistics input
|
||||
*/
|
||||
|
||||
@ -7,6 +7,7 @@ This design targets the Xilinx Alveo U250 FPGA board.
|
||||
* FPGA: xcu250-figd2104-2-e
|
||||
* MAC: Xilinx 100G CMAC
|
||||
* PHY: 100G CAUI-4 CMAC and internal GTY transceivers
|
||||
* RAM: 64 GB DDR4 2400 (4x 2G x72 DIMM)
|
||||
|
||||
## How to build
|
||||
|
||||
|
||||
@ -17,23 +17,23 @@ set_operating_conditions -design_power_budget 160
|
||||
|
||||
# System clocks
|
||||
# 300 MHz (DDR 0)
|
||||
#set_property -dict {LOC AY37 IOSTANDARD LVDS} [get_ports clk_300mhz_0_p]
|
||||
#set_property -dict {LOC AY38 IOSTANDARD LVDS} [get_ports clk_300mhz_0_n]
|
||||
set_property -dict {LOC AY37 IOSTANDARD LVDS} [get_ports clk_300mhz_0_p]
|
||||
set_property -dict {LOC AY38 IOSTANDARD LVDS} [get_ports clk_300mhz_0_n]
|
||||
#create_clock -period 3.333 -name clk_300mhz_0 [get_ports clk_300mhz_0_p]
|
||||
|
||||
# 300 MHz (DDR 1)
|
||||
#set_property -dict {LOC AW20 IOSTANDARD LVDS} [get_ports clk_300mhz_1_p]
|
||||
#set_property -dict {LOC AW19 IOSTANDARD LVDS} [get_ports clk_300mhz_1_n]
|
||||
set_property -dict {LOC AW20 IOSTANDARD LVDS} [get_ports clk_300mhz_1_p]
|
||||
set_property -dict {LOC AW19 IOSTANDARD LVDS} [get_ports clk_300mhz_1_n]
|
||||
#create_clock -period 3.333 -name clk_300mhz_1 [get_ports clk_300mhz_1_p]
|
||||
|
||||
# 300 MHz (DDR 2)
|
||||
#set_property -dict {LOC F32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_p]
|
||||
#set_property -dict {LOC E32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_n]
|
||||
set_property -dict {LOC F32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_p]
|
||||
set_property -dict {LOC E32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_n]
|
||||
#create_clock -period 3.333 -name clk_300mhz_2 [get_ports clk_300mhz_2_p]
|
||||
|
||||
# 300 MHz (DDR 3)
|
||||
#set_property -dict {LOC J16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_p]
|
||||
#set_property -dict {LOC H16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_n]
|
||||
set_property -dict {LOC J16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_p]
|
||||
set_property -dict {LOC H16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_n]
|
||||
#create_clock -period 3.333 -name clk_300mhz_3 [get_ports clk_300mhz_3_p]
|
||||
|
||||
# SI570 user clock
|
||||
@ -257,3 +257,591 @@ create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_p]
|
||||
|
||||
set_false_path -from [get_ports {pcie_reset_n}]
|
||||
set_input_delay 0 [get_ports {pcie_reset_n}]
|
||||
|
||||
# DDR4 C0
|
||||
set_property -dict {LOC AT36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}]
|
||||
set_property -dict {LOC AV36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}]
|
||||
set_property -dict {LOC AV37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}]
|
||||
set_property -dict {LOC AW35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}]
|
||||
set_property -dict {LOC AW36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}]
|
||||
set_property -dict {LOC AY36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}]
|
||||
set_property -dict {LOC AY35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}]
|
||||
set_property -dict {LOC BA40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}]
|
||||
set_property -dict {LOC BA37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}]
|
||||
set_property -dict {LOC BB37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}]
|
||||
set_property -dict {LOC AR35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}]
|
||||
set_property -dict {LOC BA39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}]
|
||||
set_property -dict {LOC BB40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}]
|
||||
set_property -dict {LOC AN36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}]
|
||||
set_property -dict {LOC AP35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}]
|
||||
set_property -dict {LOC AP36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}]
|
||||
set_property -dict {LOC AR36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}]
|
||||
set_property -dict {LOC AT35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}]
|
||||
set_property -dict {LOC AT34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}]
|
||||
set_property -dict {LOC BC37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}]
|
||||
set_property -dict {LOC BC39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}]
|
||||
set_property -dict {LOC AV38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t[0]}]
|
||||
set_property -dict {LOC AW38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c[0]}]
|
||||
#set_property -dict {LOC AU34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t[1]}]
|
||||
#set_property -dict {LOC AU35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c[1]}]
|
||||
set_property -dict {LOC BC38 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[0]}]
|
||||
#set_property -dict {LOC BC40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[1]}]
|
||||
set_property -dict {LOC AR33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[0]}]
|
||||
#set_property -dict {LOC AP33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[1]}]
|
||||
#set_property -dict {LOC AN33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[2]}]
|
||||
#set_property -dict {LOC AM34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[3]}]
|
||||
set_property -dict {LOC BB39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}]
|
||||
set_property -dict {LOC AP34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[0]}]
|
||||
#set_property -dict {LOC AN34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[1]}]
|
||||
set_property -dict {LOC AU36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}]
|
||||
set_property -dict {LOC AU31 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_reset_n}]
|
||||
|
||||
set_property -dict {LOC AW28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}]
|
||||
set_property -dict {LOC AW29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}]
|
||||
set_property -dict {LOC BA28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}]
|
||||
set_property -dict {LOC BA27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}]
|
||||
set_property -dict {LOC BB29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}]
|
||||
set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}]
|
||||
set_property -dict {LOC BC27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}]
|
||||
set_property -dict {LOC BB27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}]
|
||||
set_property -dict {LOC BE28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}]
|
||||
set_property -dict {LOC BF28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}]
|
||||
set_property -dict {LOC BE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}]
|
||||
set_property -dict {LOC BD30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}]
|
||||
set_property -dict {LOC BF27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}]
|
||||
set_property -dict {LOC BE27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}]
|
||||
set_property -dict {LOC BF30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}]
|
||||
set_property -dict {LOC BF29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}]
|
||||
set_property -dict {LOC BB31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}]
|
||||
set_property -dict {LOC BB32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}]
|
||||
set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}]
|
||||
set_property -dict {LOC AY33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}]
|
||||
set_property -dict {LOC BC32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}]
|
||||
set_property -dict {LOC BC33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}]
|
||||
set_property -dict {LOC BB34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}]
|
||||
set_property -dict {LOC BC34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}]
|
||||
set_property -dict {LOC AV31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}]
|
||||
set_property -dict {LOC AV32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}]
|
||||
set_property -dict {LOC AV34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}]
|
||||
set_property -dict {LOC AW34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}]
|
||||
set_property -dict {LOC AW31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}]
|
||||
set_property -dict {LOC AY31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}]
|
||||
set_property -dict {LOC BA35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}]
|
||||
set_property -dict {LOC BA34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}]
|
||||
set_property -dict {LOC AL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}]
|
||||
set_property -dict {LOC AM30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}]
|
||||
set_property -dict {LOC AU32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}]
|
||||
set_property -dict {LOC AT32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}]
|
||||
set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}]
|
||||
set_property -dict {LOC AN32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}]
|
||||
set_property -dict {LOC AR32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}]
|
||||
set_property -dict {LOC AR31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}]
|
||||
set_property -dict {LOC AP29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}]
|
||||
set_property -dict {LOC AP28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}]
|
||||
set_property -dict {LOC AN27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}]
|
||||
set_property -dict {LOC AM27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}]
|
||||
set_property -dict {LOC AN29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}]
|
||||
set_property -dict {LOC AM29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}]
|
||||
set_property -dict {LOC AR27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}]
|
||||
set_property -dict {LOC AR28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}]
|
||||
set_property -dict {LOC AT28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}]
|
||||
set_property -dict {LOC AV27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}]
|
||||
set_property -dict {LOC AU27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}]
|
||||
set_property -dict {LOC AT27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}]
|
||||
set_property -dict {LOC AV29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}]
|
||||
set_property -dict {LOC AY30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}]
|
||||
set_property -dict {LOC AW30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}]
|
||||
set_property -dict {LOC AV28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}]
|
||||
set_property -dict {LOC BD34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}]
|
||||
set_property -dict {LOC BD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}]
|
||||
set_property -dict {LOC BE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}]
|
||||
set_property -dict {LOC BD35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}]
|
||||
set_property -dict {LOC BF32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}]
|
||||
set_property -dict {LOC BF33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}]
|
||||
set_property -dict {LOC BF34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}]
|
||||
set_property -dict {LOC BF35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}]
|
||||
set_property -dict {LOC BD40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}]
|
||||
set_property -dict {LOC BD39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}]
|
||||
set_property -dict {LOC BF43 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}]
|
||||
set_property -dict {LOC BF42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}]
|
||||
set_property -dict {LOC BF37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}]
|
||||
set_property -dict {LOC BE37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}]
|
||||
set_property -dict {LOC BE40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}]
|
||||
set_property -dict {LOC BF41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}]
|
||||
set_property -dict {LOC BA30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}]
|
||||
set_property -dict {LOC BB30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}]
|
||||
set_property -dict {LOC BB26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}]
|
||||
set_property -dict {LOC BC26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}]
|
||||
set_property -dict {LOC BD28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}]
|
||||
set_property -dict {LOC BD29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}]
|
||||
set_property -dict {LOC BD26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}]
|
||||
set_property -dict {LOC BE26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}]
|
||||
set_property -dict {LOC BB35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}]
|
||||
set_property -dict {LOC BB36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}]
|
||||
set_property -dict {LOC BC31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}]
|
||||
set_property -dict {LOC BD31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}]
|
||||
set_property -dict {LOC AV33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}]
|
||||
set_property -dict {LOC AW33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}]
|
||||
set_property -dict {LOC BA32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}]
|
||||
set_property -dict {LOC BA33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}]
|
||||
set_property -dict {LOC AM31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}]
|
||||
set_property -dict {LOC AM32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}]
|
||||
set_property -dict {LOC AP30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[9]}]
|
||||
set_property -dict {LOC AP31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[9]}]
|
||||
set_property -dict {LOC AL28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[10]}]
|
||||
set_property -dict {LOC AL29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[10]}]
|
||||
set_property -dict {LOC AR30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[11]}]
|
||||
set_property -dict {LOC AT30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[11]}]
|
||||
set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[12]}]
|
||||
set_property -dict {LOC AU30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[12]}]
|
||||
set_property -dict {LOC AY27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[13]}]
|
||||
set_property -dict {LOC AY28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[13]}]
|
||||
set_property -dict {LOC BE35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[14]}]
|
||||
set_property -dict {LOC BE36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[14]}]
|
||||
set_property -dict {LOC BE31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[15]}]
|
||||
set_property -dict {LOC BE32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[15]}]
|
||||
set_property -dict {LOC BE38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[16]}]
|
||||
set_property -dict {LOC BF38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[16]}]
|
||||
set_property -dict {LOC BF39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[17]}]
|
||||
set_property -dict {LOC BF40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[17]}]
|
||||
|
||||
# DDR4 C1
|
||||
set_property -dict {LOC AN24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}]
|
||||
set_property -dict {LOC AT24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}]
|
||||
set_property -dict {LOC AW24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}]
|
||||
set_property -dict {LOC AN26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}]
|
||||
set_property -dict {LOC AY22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}]
|
||||
set_property -dict {LOC AY23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}]
|
||||
set_property -dict {LOC AV24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}]
|
||||
set_property -dict {LOC BA22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}]
|
||||
set_property -dict {LOC AY25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}]
|
||||
set_property -dict {LOC BA23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}]
|
||||
set_property -dict {LOC AM26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}]
|
||||
set_property -dict {LOC BA25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}]
|
||||
set_property -dict {LOC BB22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}]
|
||||
set_property -dict {LOC AL24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}]
|
||||
set_property -dict {LOC AL25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}]
|
||||
set_property -dict {LOC AM25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}]
|
||||
set_property -dict {LOC AN23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}]
|
||||
set_property -dict {LOC AU24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}]
|
||||
set_property -dict {LOC AP26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}]
|
||||
set_property -dict {LOC BC22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}]
|
||||
set_property -dict {LOC AW26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}]
|
||||
set_property -dict {LOC AT25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t[0]}]
|
||||
set_property -dict {LOC AU25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c[0]}]
|
||||
#set_property -dict {LOC AU26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t[1]}]
|
||||
#set_property -dict {LOC AV26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c[1]}]
|
||||
set_property -dict {LOC BB25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[0]}]
|
||||
#set_property -dict {LOC BB24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[1]}]
|
||||
set_property -dict {LOC AV23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[0]}]
|
||||
#set_property -dict {LOC AP25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[1]}]
|
||||
#set_property -dict {LOC AR23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[2]}]
|
||||
#set_property -dict {LOC AP23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[3]}]
|
||||
set_property -dict {LOC AW25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}]
|
||||
set_property -dict {LOC AW23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[0]}]
|
||||
#set_property -dict {LOC AP24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[1]}]
|
||||
set_property -dict {LOC AT23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}]
|
||||
set_property -dict {LOC AR17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}]
|
||||
|
||||
set_property -dict {LOC BD9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}]
|
||||
set_property -dict {LOC BD7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}]
|
||||
set_property -dict {LOC BC7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}]
|
||||
set_property -dict {LOC BD8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}]
|
||||
set_property -dict {LOC BD10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}]
|
||||
set_property -dict {LOC BE10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}]
|
||||
set_property -dict {LOC BE7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}]
|
||||
set_property -dict {LOC BF7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}]
|
||||
set_property -dict {LOC AU13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}]
|
||||
set_property -dict {LOC AV13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}]
|
||||
set_property -dict {LOC AW13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}]
|
||||
set_property -dict {LOC AW14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}]
|
||||
set_property -dict {LOC AU14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}]
|
||||
set_property -dict {LOC AY11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}]
|
||||
set_property -dict {LOC AV14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}]
|
||||
set_property -dict {LOC BA11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}]
|
||||
set_property -dict {LOC BA12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}]
|
||||
set_property -dict {LOC BB12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}]
|
||||
set_property -dict {LOC BA13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}]
|
||||
set_property -dict {LOC BA14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}]
|
||||
set_property -dict {LOC BC9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}]
|
||||
set_property -dict {LOC BB9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}]
|
||||
set_property -dict {LOC BA7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}]
|
||||
set_property -dict {LOC BA8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}]
|
||||
set_property -dict {LOC AN13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}]
|
||||
set_property -dict {LOC AR13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}]
|
||||
set_property -dict {LOC AM13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}]
|
||||
set_property -dict {LOC AP13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}]
|
||||
set_property -dict {LOC AM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}]
|
||||
set_property -dict {LOC AR15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}]
|
||||
set_property -dict {LOC AL14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}]
|
||||
set_property -dict {LOC AT15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}]
|
||||
set_property -dict {LOC BE13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}]
|
||||
set_property -dict {LOC BD14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}]
|
||||
set_property -dict {LOC BF12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}]
|
||||
set_property -dict {LOC BD13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}]
|
||||
set_property -dict {LOC BD15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}]
|
||||
set_property -dict {LOC BD16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}]
|
||||
set_property -dict {LOC BF14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}]
|
||||
set_property -dict {LOC BF13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}]
|
||||
set_property -dict {LOC AY17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}]
|
||||
set_property -dict {LOC BA17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}]
|
||||
set_property -dict {LOC AY18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}]
|
||||
set_property -dict {LOC BA18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}]
|
||||
set_property -dict {LOC BA15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}]
|
||||
set_property -dict {LOC BB15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}]
|
||||
set_property -dict {LOC BC11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}]
|
||||
set_property -dict {LOC BD11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}]
|
||||
set_property -dict {LOC AV16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}]
|
||||
set_property -dict {LOC AV17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}]
|
||||
set_property -dict {LOC AU16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}]
|
||||
set_property -dict {LOC AU17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}]
|
||||
set_property -dict {LOC BB17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}]
|
||||
set_property -dict {LOC BB16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}]
|
||||
set_property -dict {LOC AT18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}]
|
||||
set_property -dict {LOC AT17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}]
|
||||
set_property -dict {LOC AM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}]
|
||||
set_property -dict {LOC AL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}]
|
||||
set_property -dict {LOC AN17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}]
|
||||
set_property -dict {LOC AN16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}]
|
||||
set_property -dict {LOC AR18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}]
|
||||
set_property -dict {LOC AP18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}]
|
||||
set_property -dict {LOC AL17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}]
|
||||
set_property -dict {LOC AL16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}]
|
||||
set_property -dict {LOC BF25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}]
|
||||
set_property -dict {LOC BF24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}]
|
||||
set_property -dict {LOC BD25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}]
|
||||
set_property -dict {LOC BE25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}]
|
||||
set_property -dict {LOC BD23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}]
|
||||
set_property -dict {LOC BC23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}]
|
||||
set_property -dict {LOC BF23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}]
|
||||
set_property -dict {LOC BE23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}]
|
||||
set_property -dict {LOC BF10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}]
|
||||
set_property -dict {LOC BF9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}]
|
||||
set_property -dict {LOC BE8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}]
|
||||
set_property -dict {LOC BF8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}]
|
||||
set_property -dict {LOC AW15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}]
|
||||
set_property -dict {LOC AY15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}]
|
||||
set_property -dict {LOC AY13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}]
|
||||
set_property -dict {LOC AY12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}]
|
||||
set_property -dict {LOC BB11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}]
|
||||
set_property -dict {LOC BB10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}]
|
||||
set_property -dict {LOC BA10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}]
|
||||
set_property -dict {LOC BA9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}]
|
||||
set_property -dict {LOC AT14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}]
|
||||
set_property -dict {LOC AT13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}]
|
||||
set_property -dict {LOC AN14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}]
|
||||
set_property -dict {LOC AP14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}]
|
||||
set_property -dict {LOC BE12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}]
|
||||
set_property -dict {LOC BE11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}]
|
||||
set_property -dict {LOC BE15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}]
|
||||
set_property -dict {LOC BF15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}]
|
||||
set_property -dict {LOC BC13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[10]}]
|
||||
set_property -dict {LOC BC12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[10]}]
|
||||
set_property -dict {LOC BB14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[11]}]
|
||||
set_property -dict {LOC BC14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[11]}]
|
||||
set_property -dict {LOC AV18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[12]}]
|
||||
set_property -dict {LOC AW18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[12]}]
|
||||
set_property -dict {LOC AW16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[13]}]
|
||||
set_property -dict {LOC AY16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[13]}]
|
||||
set_property -dict {LOC AP16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[14]}]
|
||||
set_property -dict {LOC AR16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[14]}]
|
||||
set_property -dict {LOC AM17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[15]}]
|
||||
set_property -dict {LOC AM16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[15]}]
|
||||
set_property -dict {LOC BC24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[16]}]
|
||||
set_property -dict {LOC BD24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[16]}]
|
||||
set_property -dict {LOC BE22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[17]}]
|
||||
set_property -dict {LOC BF22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[17]}]
|
||||
|
||||
# DDR4 C2
|
||||
set_property -dict {LOC L29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[0]}]
|
||||
set_property -dict {LOC A33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[1]}]
|
||||
set_property -dict {LOC C33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[2]}]
|
||||
set_property -dict {LOC J29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[3]}]
|
||||
set_property -dict {LOC H31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[4]}]
|
||||
set_property -dict {LOC G31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[5]}]
|
||||
set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[6]}]
|
||||
set_property -dict {LOC B32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[7]}]
|
||||
set_property -dict {LOC A32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[8]}]
|
||||
set_property -dict {LOC D31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[9]}]
|
||||
set_property -dict {LOC A34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[10]}]
|
||||
set_property -dict {LOC E31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[11]}]
|
||||
set_property -dict {LOC M30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[12]}]
|
||||
set_property -dict {LOC F33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[13]}]
|
||||
set_property -dict {LOC A35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[14]}]
|
||||
set_property -dict {LOC G32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[15]}]
|
||||
set_property -dict {LOC K30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[16]}]
|
||||
set_property -dict {LOC D33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[0]}]
|
||||
set_property -dict {LOC B36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[1]}]
|
||||
set_property -dict {LOC C31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[0]}]
|
||||
set_property -dict {LOC J30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[1]}]
|
||||
set_property -dict {LOC C34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t[0]}]
|
||||
set_property -dict {LOC B34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c[0]}]
|
||||
#set_property -dict {LOC D34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t[1]}]
|
||||
#set_property -dict {LOC D35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c[1]}]
|
||||
set_property -dict {LOC G30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[0]}]
|
||||
#set_property -dict {LOC E30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[1]}]
|
||||
set_property -dict {LOC B35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[0]}]
|
||||
#set_property -dict {LOC J31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[1]}]
|
||||
#set_property -dict {LOC L30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[2]}]
|
||||
#set_property -dict {LOC K31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[3]}]
|
||||
set_property -dict {LOC B31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_act_n}]
|
||||
set_property -dict {LOC E33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[0]}]
|
||||
#set_property -dict {LOC F34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[1]}]
|
||||
set_property -dict {LOC M29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_par}]
|
||||
set_property -dict {LOC D36 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_reset_n}]
|
||||
|
||||
set_property -dict {LOC R25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[0]}]
|
||||
set_property -dict {LOC P25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[1]}]
|
||||
set_property -dict {LOC M25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[2]}]
|
||||
set_property -dict {LOC L25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[3]}]
|
||||
set_property -dict {LOC P26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[4]}]
|
||||
set_property -dict {LOC R26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[5]}]
|
||||
set_property -dict {LOC N27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[6]}]
|
||||
set_property -dict {LOC N28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[7]}]
|
||||
set_property -dict {LOC J28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[8]}]
|
||||
set_property -dict {LOC H29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[9]}]
|
||||
set_property -dict {LOC H28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[10]}]
|
||||
set_property -dict {LOC G29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[11]}]
|
||||
set_property -dict {LOC K25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[12]}]
|
||||
set_property -dict {LOC L27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[13]}]
|
||||
set_property -dict {LOC K26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[14]}]
|
||||
set_property -dict {LOC K27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[15]}]
|
||||
set_property -dict {LOC F27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[16]}]
|
||||
set_property -dict {LOC E27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[17]}]
|
||||
set_property -dict {LOC E28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[18]}]
|
||||
set_property -dict {LOC D28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[19]}]
|
||||
set_property -dict {LOC G27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[20]}]
|
||||
set_property -dict {LOC G26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[21]}]
|
||||
set_property -dict {LOC F28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[22]}]
|
||||
set_property -dict {LOC F29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[23]}]
|
||||
set_property -dict {LOC D26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[24]}]
|
||||
set_property -dict {LOC C26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[25]}]
|
||||
set_property -dict {LOC B27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[26]}]
|
||||
set_property -dict {LOC B26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[27]}]
|
||||
set_property -dict {LOC A29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[28]}]
|
||||
set_property -dict {LOC A30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[29]}]
|
||||
set_property -dict {LOC C27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[30]}]
|
||||
set_property -dict {LOC C28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[31]}]
|
||||
set_property -dict {LOC F35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[32]}]
|
||||
set_property -dict {LOC E38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[33]}]
|
||||
set_property -dict {LOC D38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[34]}]
|
||||
set_property -dict {LOC E35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[35]}]
|
||||
set_property -dict {LOC E36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[36]}]
|
||||
set_property -dict {LOC E37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[37]}]
|
||||
set_property -dict {LOC F38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[38]}]
|
||||
set_property -dict {LOC G38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[39]}]
|
||||
set_property -dict {LOC P30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[40]}]
|
||||
set_property -dict {LOC R30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[41]}]
|
||||
set_property -dict {LOC P29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[42]}]
|
||||
set_property -dict {LOC N29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[43]}]
|
||||
set_property -dict {LOC L32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[44]}]
|
||||
set_property -dict {LOC M32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[45]}]
|
||||
set_property -dict {LOC P31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[46]}]
|
||||
set_property -dict {LOC N32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[47]}]
|
||||
set_property -dict {LOC J35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[48]}]
|
||||
set_property -dict {LOC K35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[49]}]
|
||||
set_property -dict {LOC L33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[50]}]
|
||||
set_property -dict {LOC K33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[51]}]
|
||||
set_property -dict {LOC J34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[52]}]
|
||||
set_property -dict {LOC J33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[53]}]
|
||||
set_property -dict {LOC N34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[54]}]
|
||||
set_property -dict {LOC P34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[55]}]
|
||||
set_property -dict {LOC H36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[56]}]
|
||||
set_property -dict {LOC G36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[57]}]
|
||||
set_property -dict {LOC H37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[58]}]
|
||||
set_property -dict {LOC J36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[59]}]
|
||||
set_property -dict {LOC K37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[60]}]
|
||||
set_property -dict {LOC K38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[61]}]
|
||||
set_property -dict {LOC G35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[62]}]
|
||||
set_property -dict {LOC G34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[63]}]
|
||||
set_property -dict {LOC C36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[64]}]
|
||||
set_property -dict {LOC B37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[65]}]
|
||||
set_property -dict {LOC A37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[66]}]
|
||||
set_property -dict {LOC A38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[67]}]
|
||||
set_property -dict {LOC C39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[68]}]
|
||||
set_property -dict {LOC D39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[69]}]
|
||||
set_property -dict {LOC A40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[70]}]
|
||||
set_property -dict {LOC B40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[71]}]
|
||||
set_property -dict {LOC N26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[0]}]
|
||||
set_property -dict {LOC M26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[0]}]
|
||||
set_property -dict {LOC R28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[1]}]
|
||||
set_property -dict {LOC P28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[1]}]
|
||||
set_property -dict {LOC J25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[2]}]
|
||||
set_property -dict {LOC J26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[2]}]
|
||||
set_property -dict {LOC M27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[3]}]
|
||||
set_property -dict {LOC L28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[3]}]
|
||||
set_property -dict {LOC D29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[4]}]
|
||||
set_property -dict {LOC D30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[4]}]
|
||||
set_property -dict {LOC H26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[5]}]
|
||||
set_property -dict {LOC H27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[5]}]
|
||||
set_property -dict {LOC A27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[6]}]
|
||||
set_property -dict {LOC A28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[6]}]
|
||||
set_property -dict {LOC C29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[7]}]
|
||||
set_property -dict {LOC B29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[7]}]
|
||||
set_property -dict {LOC E39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[8]}]
|
||||
set_property -dict {LOC E40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[8]}]
|
||||
set_property -dict {LOC G37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[9]}]
|
||||
set_property -dict {LOC F37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[9]}]
|
||||
set_property -dict {LOC N31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[10]}]
|
||||
set_property -dict {LOC M31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[10]}]
|
||||
set_property -dict {LOC T30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[11]}]
|
||||
set_property -dict {LOC R31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[11]}]
|
||||
set_property -dict {LOC L35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[12]}]
|
||||
set_property -dict {LOC L36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[12]}]
|
||||
set_property -dict {LOC M34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[13]}]
|
||||
set_property -dict {LOC L34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[13]}]
|
||||
set_property -dict {LOC J38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[14]}]
|
||||
set_property -dict {LOC H38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[14]}]
|
||||
set_property -dict {LOC H33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[15]}]
|
||||
set_property -dict {LOC H34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[15]}]
|
||||
set_property -dict {LOC B39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[16]}]
|
||||
set_property -dict {LOC A39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[16]}]
|
||||
set_property -dict {LOC C37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[17]}]
|
||||
set_property -dict {LOC C38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[17]}]
|
||||
|
||||
# DDR4 C3
|
||||
set_property -dict {LOC K15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[0]}]
|
||||
set_property -dict {LOC B15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[1]}]
|
||||
set_property -dict {LOC F14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[2]}]
|
||||
set_property -dict {LOC A15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[3]}]
|
||||
set_property -dict {LOC C14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[4]}]
|
||||
set_property -dict {LOC A14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[5]}]
|
||||
set_property -dict {LOC B14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[6]}]
|
||||
set_property -dict {LOC E13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[7]}]
|
||||
set_property -dict {LOC F13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[8]}]
|
||||
set_property -dict {LOC A13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[9]}]
|
||||
set_property -dict {LOC D14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[10]}]
|
||||
set_property -dict {LOC C13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[11]}]
|
||||
set_property -dict {LOC B13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[12]}]
|
||||
set_property -dict {LOC K16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[13]}]
|
||||
set_property -dict {LOC D15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[14]}]
|
||||
set_property -dict {LOC E15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[15]}]
|
||||
set_property -dict {LOC F15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[16]}]
|
||||
set_property -dict {LOC J15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[0]}]
|
||||
set_property -dict {LOC H14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[1]}]
|
||||
set_property -dict {LOC D13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[0]}]
|
||||
set_property -dict {LOC J13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[1]}]
|
||||
set_property -dict {LOC L14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t[0]}]
|
||||
set_property -dict {LOC L13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c[0]}]
|
||||
#set_property -dict {LOC G14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t[1]}]
|
||||
#set_property -dict {LOC G13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c[1]}]
|
||||
set_property -dict {LOC K13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[0]}]
|
||||
#set_property -dict {LOC L15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[1]}]
|
||||
set_property -dict {LOC B16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[0]}]
|
||||
#set_property -dict {LOC D16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[1]}]
|
||||
#set_property -dict {LOC M14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[2]}]
|
||||
#set_property -dict {LOC M13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[3]}]
|
||||
set_property -dict {LOC H13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_act_n}]
|
||||
set_property -dict {LOC C16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[0]}]
|
||||
#set_property -dict {LOC E16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[1]}]
|
||||
set_property -dict {LOC J14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_par}]
|
||||
set_property -dict {LOC D21 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c3_reset_n}]
|
||||
|
||||
set_property -dict {LOC P24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[0]}]
|
||||
set_property -dict {LOC N24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[1]}]
|
||||
set_property -dict {LOC T24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[2]}]
|
||||
set_property -dict {LOC R23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[3]}]
|
||||
set_property -dict {LOC N23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[4]}]
|
||||
set_property -dict {LOC P21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[5]}]
|
||||
set_property -dict {LOC P23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[6]}]
|
||||
set_property -dict {LOC R21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[7]}]
|
||||
set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[8]}]
|
||||
set_property -dict {LOC J23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[9]}]
|
||||
set_property -dict {LOC H24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[10]}]
|
||||
set_property -dict {LOC G24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[11]}]
|
||||
set_property -dict {LOC L24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[12]}]
|
||||
set_property -dict {LOC L23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[13]}]
|
||||
set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[14]}]
|
||||
set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[15]}]
|
||||
set_property -dict {LOC G20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[16]}]
|
||||
set_property -dict {LOC H17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[17]}]
|
||||
set_property -dict {LOC F19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[18]}]
|
||||
set_property -dict {LOC G17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[19]}]
|
||||
set_property -dict {LOC J20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[20]}]
|
||||
set_property -dict {LOC L19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[21]}]
|
||||
set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[22]}]
|
||||
set_property -dict {LOC J19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[23]}]
|
||||
set_property -dict {LOC M19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[24]}]
|
||||
set_property -dict {LOC M20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[25]}]
|
||||
set_property -dict {LOC R18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[26]}]
|
||||
set_property -dict {LOC R17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[27]}]
|
||||
set_property -dict {LOC R20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[28]}]
|
||||
set_property -dict {LOC T20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[29]}]
|
||||
set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[30]}]
|
||||
set_property -dict {LOC N19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[31]}]
|
||||
set_property -dict {LOC A23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[32]}]
|
||||
set_property -dict {LOC A22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[33]}]
|
||||
set_property -dict {LOC B24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[34]}]
|
||||
set_property -dict {LOC B25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[35]}]
|
||||
set_property -dict {LOC B22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[36]}]
|
||||
set_property -dict {LOC C22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[37]}]
|
||||
set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[38]}]
|
||||
set_property -dict {LOC C23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[39]}]
|
||||
set_property -dict {LOC C19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[40]}]
|
||||
set_property -dict {LOC C18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[41]}]
|
||||
set_property -dict {LOC C21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[42]}]
|
||||
set_property -dict {LOC B21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[43]}]
|
||||
set_property -dict {LOC A18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[44]}]
|
||||
set_property -dict {LOC A17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[45]}]
|
||||
set_property -dict {LOC A20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[46]}]
|
||||
set_property -dict {LOC B20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[47]}]
|
||||
set_property -dict {LOC E17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[48]}]
|
||||
set_property -dict {LOC F20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[49]}]
|
||||
set_property -dict {LOC E18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[50]}]
|
||||
set_property -dict {LOC E20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[51]}]
|
||||
set_property -dict {LOC D19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[52]}]
|
||||
set_property -dict {LOC D20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[53]}]
|
||||
set_property -dict {LOC H18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[54]}]
|
||||
set_property -dict {LOC J18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[55]}]
|
||||
set_property -dict {LOC F22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[56]}]
|
||||
set_property -dict {LOC E22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[57]}]
|
||||
set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[58]}]
|
||||
set_property -dict {LOC G21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[59]}]
|
||||
set_property -dict {LOC F24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[60]}]
|
||||
set_property -dict {LOC E25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[61]}]
|
||||
set_property -dict {LOC F25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[62]}]
|
||||
set_property -dict {LOC G25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[63]}]
|
||||
set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[64]}]
|
||||
set_property -dict {LOC N16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[65]}]
|
||||
set_property -dict {LOC N13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[66]}]
|
||||
set_property -dict {LOC N14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[67]}]
|
||||
set_property -dict {LOC T15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[68]}]
|
||||
set_property -dict {LOC R15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[69]}]
|
||||
set_property -dict {LOC P13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[70]}]
|
||||
set_property -dict {LOC P14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[71]}]
|
||||
set_property -dict {LOC T22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[0]}]
|
||||
set_property -dict {LOC R22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[0]}]
|
||||
set_property -dict {LOC N22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[1]}]
|
||||
set_property -dict {LOC N21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[1]}]
|
||||
set_property -dict {LOC J21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[2]}]
|
||||
set_property -dict {LOC H21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[2]}]
|
||||
set_property -dict {LOC M22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[3]}]
|
||||
set_property -dict {LOC L22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[3]}]
|
||||
set_property -dict {LOC L20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[4]}]
|
||||
set_property -dict {LOC K20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[4]}]
|
||||
set_property -dict {LOC K18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[5]}]
|
||||
set_property -dict {LOC K17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[5]}]
|
||||
set_property -dict {LOC P19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[6]}]
|
||||
set_property -dict {LOC P18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[6]}]
|
||||
set_property -dict {LOC N17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[7]}]
|
||||
set_property -dict {LOC M17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[7]}]
|
||||
set_property -dict {LOC A25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[8]}]
|
||||
set_property -dict {LOC A24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[8]}]
|
||||
set_property -dict {LOC D24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[9]}]
|
||||
set_property -dict {LOC D23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[9]}]
|
||||
set_property -dict {LOC C17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[10]}]
|
||||
set_property -dict {LOC B17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[10]}]
|
||||
set_property -dict {LOC B19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[11]}]
|
||||
set_property -dict {LOC A19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[11]}]
|
||||
set_property -dict {LOC F18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[12]}]
|
||||
set_property -dict {LOC F17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[12]}]
|
||||
set_property -dict {LOC H19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[13]}]
|
||||
set_property -dict {LOC G19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[13]}]
|
||||
set_property -dict {LOC F23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[14]}]
|
||||
set_property -dict {LOC E23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[14]}]
|
||||
set_property -dict {LOC H23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[15]}]
|
||||
set_property -dict {LOC H22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[15]}]
|
||||
set_property -dict {LOC R16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[16]}]
|
||||
set_property -dict {LOC P15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[16]}]
|
||||
set_property -dict {LOC T13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[17]}]
|
||||
set_property -dict {LOC R13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[17]}]
|
||||
|
||||
@ -125,6 +125,7 @@ IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
|
||||
IP_TCL_FILES += ip/cmac_usplus_0.tcl
|
||||
IP_TCL_FILES += ip/cmac_usplus_1.tcl
|
||||
IP_TCL_FILES += ip/cms.tcl
|
||||
IP_TCL_FILES += ip/ddr4_0.tcl
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
@ -136,6 +136,12 @@ dict set params MAX_TX_SIZE "9214"
|
||||
dict set params MAX_RX_SIZE "9214"
|
||||
dict set params TX_RAM_SIZE "131072"
|
||||
dict set params RX_RAM_SIZE "131072"
|
||||
|
||||
# RAM configuration
|
||||
dict set params DDR_CH "4"
|
||||
dict set params DDR_ENABLE "1"
|
||||
dict set params AXI_DDR_ID_WIDTH "8"
|
||||
dict set params AXI_DDR_MAX_BURST_LEN "256"
|
||||
|
||||
# Application block configuration
|
||||
dict set params APP_ID "32'h00000000"
|
||||
@ -187,6 +193,19 @@ dict set params STAT_PCIE_ENABLE "1"
|
||||
dict set params STAT_INC_WIDTH "24"
|
||||
dict set params STAT_ID_WIDTH "12"
|
||||
|
||||
# DDR4 MIG settings
|
||||
if {[dict get $params DDR_ENABLE]} {
|
||||
set ddr4 [get_ips ddr4_0]
|
||||
|
||||
# set AXI ID width
|
||||
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
|
||||
|
||||
# extract AXI configuration
|
||||
dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4]
|
||||
dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4]
|
||||
dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1]
|
||||
}
|
||||
|
||||
# PCIe IP core settings
|
||||
set pcie [get_ips pcie4_uscale_plus_0]
|
||||
|
||||
|
||||
17
fpga/mqnic/AU250/fpga_100g/ip/ddr4_0.tcl
Normal file
17
fpga/mqnic/AU250/fpga_100g/ip/ddr4_0.tcl
Normal file
@ -0,0 +1,17 @@
|
||||
|
||||
create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0
|
||||
|
||||
set_property -dict [list \
|
||||
CONFIG.C0.DDR4_AxiSelection {true} \
|
||||
CONFIG.C0.DDR4_AxiDataWidth {512} \
|
||||
CONFIG.C0.DDR4_AxiIDWidth {8} \
|
||||
CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \
|
||||
CONFIG.C0.DDR4_TimePeriod {833} \
|
||||
CONFIG.C0.DDR4_InputClockPeriod {3332} \
|
||||
CONFIG.C0.DDR4_MemoryType {RDIMMs} \
|
||||
CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PZ-2G3} \
|
||||
CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \
|
||||
CONFIG.C0.DDR4_CasLatency {17} \
|
||||
CONFIG.C0.DDR4_CasWriteLatency {12} \
|
||||
CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV}
|
||||
] [get_ips ddr4_0]
|
||||
@ -109,6 +109,15 @@ module fpga #
|
||||
parameter TX_RAM_SIZE = 131072,
|
||||
parameter RX_RAM_SIZE = 131072,
|
||||
|
||||
// RAM configuration
|
||||
parameter DDR_CH = 4,
|
||||
parameter DDR_ENABLE = 1,
|
||||
parameter AXI_DDR_DATA_WIDTH = 512,
|
||||
parameter AXI_DDR_ADDR_WIDTH = 34,
|
||||
parameter AXI_DDR_ID_WIDTH = 8,
|
||||
parameter AXI_DDR_MAX_BURST_LEN = 256,
|
||||
parameter AXI_DDR_NARROW_BURST = 0,
|
||||
|
||||
// Application block configuration
|
||||
parameter APP_ID = 32'h00000000,
|
||||
parameter APP_ENABLE = 0,
|
||||
@ -173,6 +182,18 @@ module fpga #
|
||||
parameter STAT_ID_WIDTH = 12
|
||||
)
|
||||
(
|
||||
/*
|
||||
* Clock and reset
|
||||
*/
|
||||
input wire clk_300mhz_0_p,
|
||||
input wire clk_300mhz_0_n,
|
||||
input wire clk_300mhz_1_p,
|
||||
input wire clk_300mhz_1_n,
|
||||
input wire clk_300mhz_2_p,
|
||||
input wire clk_300mhz_2_n,
|
||||
input wire clk_300mhz_3_p,
|
||||
input wire clk_300mhz_3_n,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
@ -256,7 +277,70 @@ module fpga #
|
||||
input wire qsfp1_intl,
|
||||
output wire qsfp1_lpmode,
|
||||
output wire qsfp1_refclk_reset,
|
||||
output wire [1:0] qsfp1_fs
|
||||
output wire [1:0] qsfp1_fs,
|
||||
|
||||
/*
|
||||
* DDR4
|
||||
*/
|
||||
output wire [16:0] ddr4_c0_adr,
|
||||
output wire [1:0] ddr4_c0_ba,
|
||||
output wire [1:0] ddr4_c0_bg,
|
||||
output wire [0:0] ddr4_c0_ck_t,
|
||||
output wire [0:0] ddr4_c0_ck_c,
|
||||
output wire [0:0] ddr4_c0_cke,
|
||||
output wire [0:0] ddr4_c0_cs_n,
|
||||
output wire ddr4_c0_act_n,
|
||||
output wire [0:0] ddr4_c0_odt,
|
||||
output wire ddr4_c0_par,
|
||||
output wire ddr4_c0_reset_n,
|
||||
inout wire [71:0] ddr4_c0_dq,
|
||||
inout wire [17:0] ddr4_c0_dqs_t,
|
||||
inout wire [17:0] ddr4_c0_dqs_c,
|
||||
|
||||
output wire [16:0] ddr4_c1_adr,
|
||||
output wire [1:0] ddr4_c1_ba,
|
||||
output wire [1:0] ddr4_c1_bg,
|
||||
output wire [0:0] ddr4_c1_ck_t,
|
||||
output wire [0:0] ddr4_c1_ck_c,
|
||||
output wire [0:0] ddr4_c1_cke,
|
||||
output wire [0:0] ddr4_c1_cs_n,
|
||||
output wire ddr4_c1_act_n,
|
||||
output wire [0:0] ddr4_c1_odt,
|
||||
output wire ddr4_c1_par,
|
||||
output wire ddr4_c1_reset_n,
|
||||
inout wire [71:0] ddr4_c1_dq,
|
||||
inout wire [17:0] ddr4_c1_dqs_t,
|
||||
inout wire [17:0] ddr4_c1_dqs_c,
|
||||
|
||||
output wire [16:0] ddr4_c2_adr,
|
||||
output wire [1:0] ddr4_c2_ba,
|
||||
output wire [1:0] ddr4_c2_bg,
|
||||
output wire [0:0] ddr4_c2_ck_t,
|
||||
output wire [0:0] ddr4_c2_ck_c,
|
||||
output wire [0:0] ddr4_c2_cke,
|
||||
output wire [0:0] ddr4_c2_cs_n,
|
||||
output wire ddr4_c2_act_n,
|
||||
output wire [0:0] ddr4_c2_odt,
|
||||
output wire ddr4_c2_par,
|
||||
output wire ddr4_c2_reset_n,
|
||||
inout wire [71:0] ddr4_c2_dq,
|
||||
inout wire [17:0] ddr4_c2_dqs_t,
|
||||
inout wire [17:0] ddr4_c2_dqs_c,
|
||||
|
||||
output wire [16:0] ddr4_c3_adr,
|
||||
output wire [1:0] ddr4_c3_ba,
|
||||
output wire [1:0] ddr4_c3_bg,
|
||||
output wire [0:0] ddr4_c3_ck_t,
|
||||
output wire [0:0] ddr4_c3_ck_c,
|
||||
output wire [0:0] ddr4_c3_cke,
|
||||
output wire [0:0] ddr4_c3_cs_n,
|
||||
output wire ddr4_c3_act_n,
|
||||
output wire [0:0] ddr4_c3_odt,
|
||||
output wire ddr4_c3_par,
|
||||
output wire ddr4_c3_reset_n,
|
||||
inout wire [71:0] ddr4_c3_dq,
|
||||
inout wire [17:0] ddr4_c3_dqs_t,
|
||||
inout wire [17:0] ddr4_c3_dqs_c
|
||||
);
|
||||
|
||||
// PTP configuration
|
||||
@ -269,6 +353,9 @@ parameter PTP_SEPARATE_RX_CLOCK = 1;
|
||||
// Interface configuration
|
||||
parameter TX_TAG_WIDTH = 16;
|
||||
|
||||
// RAM configuration
|
||||
parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8);
|
||||
|
||||
// Ethernet interface configuration
|
||||
parameter AXIS_ETH_DATA_WIDTH = 512;
|
||||
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8;
|
||||
@ -1889,6 +1976,519 @@ assign led[0] = led_int[0]; // red
|
||||
assign led[1] = qsfp1_rx_status; // yellow
|
||||
assign led[2] = qsfp0_rx_status; // green
|
||||
|
||||
// DDR4
|
||||
wire [DDR_CH-1:0] ddr_clk;
|
||||
wire [DDR_CH-1:0] ddr_rst;
|
||||
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid;
|
||||
wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr;
|
||||
wire [DDR_CH*8-1:0] m_axi_ddr_awlen;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_awsize;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_awburst;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_awlock;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_awcache;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_awprot;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_awqos;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_awvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_awready;
|
||||
wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata;
|
||||
wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_wlast;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_wvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_wready;
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_bresp;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_bvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_bready;
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid;
|
||||
wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr;
|
||||
wire [DDR_CH*8-1:0] m_axi_ddr_arlen;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_arsize;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_arburst;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_arlock;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_arcache;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_arprot;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_arqos;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_arvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_arready;
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid;
|
||||
wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_rresp;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_rlast;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_rvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_rready;
|
||||
|
||||
wire [DDR_CH-1:0] ddr_status;
|
||||
|
||||
generate
|
||||
|
||||
if (DDR_ENABLE && DDR_CH > 0) begin
|
||||
|
||||
ddr4_0 ddr4_c0_inst (
|
||||
.c0_sys_clk_p(clk_300mhz_0_p),
|
||||
.c0_sys_clk_n(clk_300mhz_0_n),
|
||||
.sys_rst(pcie_user_reset),
|
||||
|
||||
.c0_init_calib_complete(ddr_status[0 +: 1]),
|
||||
.c0_ddr4_interrupt(),
|
||||
.dbg_clk(),
|
||||
.dbg_bus(),
|
||||
|
||||
.c0_ddr4_adr(ddr4_c0_adr),
|
||||
.c0_ddr4_ba(ddr4_c0_ba),
|
||||
.c0_ddr4_cke(ddr4_c0_cke),
|
||||
.c0_ddr4_cs_n(ddr4_c0_cs_n),
|
||||
.c0_ddr4_dq(ddr4_c0_dq),
|
||||
.c0_ddr4_dqs_t(ddr4_c0_dqs_t),
|
||||
.c0_ddr4_dqs_c(ddr4_c0_dqs_c),
|
||||
.c0_ddr4_odt(ddr4_c0_odt),
|
||||
.c0_ddr4_parity(ddr4_c0_par),
|
||||
.c0_ddr4_bg(ddr4_c0_bg),
|
||||
.c0_ddr4_reset_n(ddr4_c0_reset_n),
|
||||
.c0_ddr4_act_n(ddr4_c0_act_n),
|
||||
.c0_ddr4_ck_t(ddr4_c0_ck_t),
|
||||
.c0_ddr4_ck_c(ddr4_c0_ck_c),
|
||||
|
||||
.c0_ddr4_ui_clk(ddr_clk[0 +: 1]),
|
||||
.c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]),
|
||||
|
||||
.c0_ddr4_aresetn(!ddr_rst[0 +: 1]),
|
||||
|
||||
.c0_ddr4_s_axi_ctrl_awvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_awready(),
|
||||
.c0_ddr4_s_axi_ctrl_awaddr(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_wvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_wready(),
|
||||
.c0_ddr4_s_axi_ctrl_wdata(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_bvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_bready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_bresp(),
|
||||
.c0_ddr4_s_axi_ctrl_arvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_arready(),
|
||||
.c0_ddr4_s_axi_ctrl_araddr(31'd0),
|
||||
.c0_ddr4_s_axi_ctrl_rvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_rready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_rdata(),
|
||||
.c0_ddr4_s_axi_ctrl_rresp(),
|
||||
|
||||
.c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]),
|
||||
.c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]),
|
||||
.c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]),
|
||||
.c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]),
|
||||
.c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]),
|
||||
.c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]),
|
||||
.c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]),
|
||||
.c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH])
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign ddr4_c0_adr = {17{1'bz}};
|
||||
assign ddr4_c0_ba = {2{1'bz}};
|
||||
assign ddr4_c0_bg = {2{1'bz}};
|
||||
assign ddr4_c0_cke = 1'bz;
|
||||
assign ddr4_c0_cs_n = 1'bz;
|
||||
assign ddr4_c0_act_n = 1'bz;
|
||||
assign ddr4_c0_odt = 1'bz;
|
||||
assign ddr4_c0_par = 1'bz;
|
||||
assign ddr4_c0_reset_n = 1'b0;
|
||||
assign ddr4_c0_dq = {72{1'bz}};
|
||||
assign ddr4_c0_dqs_t = {18{1'bz}};
|
||||
assign ddr4_c0_dqs_c = {18{1'bz}};
|
||||
|
||||
OBUFTDS ddr4_c0_ck_obuftds_inst (
|
||||
.I(1'b0),
|
||||
.T(1'b1),
|
||||
.O(ddr4_c0_ck_t),
|
||||
.OB(ddr4_c0_ck_c)
|
||||
);
|
||||
|
||||
assign ddr_clk = 0;
|
||||
assign ddr_rst = 0;
|
||||
|
||||
assign m_axi_ddr_awready = 0;
|
||||
assign m_axi_ddr_wready = 0;
|
||||
assign m_axi_ddr_bid = 0;
|
||||
assign m_axi_ddr_bresp = 0;
|
||||
assign m_axi_ddr_bvalid = 0;
|
||||
assign m_axi_ddr_arready = 0;
|
||||
assign m_axi_ddr_rid = 0;
|
||||
assign m_axi_ddr_rdata = 0;
|
||||
assign m_axi_ddr_rresp = 0;
|
||||
assign m_axi_ddr_rlast = 0;
|
||||
assign m_axi_ddr_rvalid = 0;
|
||||
|
||||
assign ddr_status = 0;
|
||||
|
||||
end
|
||||
|
||||
if (DDR_ENABLE && DDR_CH > 1) begin
|
||||
|
||||
ddr4_0 ddr4_c1_inst (
|
||||
.c0_sys_clk_p(clk_300mhz_1_p),
|
||||
.c0_sys_clk_n(clk_300mhz_1_n),
|
||||
.sys_rst(pcie_user_reset),
|
||||
|
||||
.c0_init_calib_complete(ddr_status[1 +: 1]),
|
||||
.c0_ddr4_interrupt(),
|
||||
.dbg_clk(),
|
||||
.dbg_bus(),
|
||||
|
||||
.c0_ddr4_adr(ddr4_c1_adr),
|
||||
.c0_ddr4_ba(ddr4_c1_ba),
|
||||
.c0_ddr4_cke(ddr4_c1_cke),
|
||||
.c0_ddr4_cs_n(ddr4_c1_cs_n),
|
||||
.c0_ddr4_dq(ddr4_c1_dq),
|
||||
.c0_ddr4_dqs_t(ddr4_c1_dqs_t),
|
||||
.c0_ddr4_dqs_c(ddr4_c1_dqs_c),
|
||||
.c0_ddr4_odt(ddr4_c1_odt),
|
||||
.c0_ddr4_parity(ddr4_c1_par),
|
||||
.c0_ddr4_bg(ddr4_c1_bg),
|
||||
.c0_ddr4_reset_n(ddr4_c1_reset_n),
|
||||
.c0_ddr4_act_n(ddr4_c1_act_n),
|
||||
.c0_ddr4_ck_t(ddr4_c1_ck_t),
|
||||
.c0_ddr4_ck_c(ddr4_c1_ck_c),
|
||||
|
||||
.c0_ddr4_ui_clk(ddr_clk[1 +: 1]),
|
||||
.c0_ddr4_ui_clk_sync_rst(ddr_rst[1 +: 1]),
|
||||
|
||||
.c0_ddr4_aresetn(!ddr_rst[1 +: 1]),
|
||||
|
||||
.c0_ddr4_s_axi_ctrl_awvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_awready(),
|
||||
.c0_ddr4_s_axi_ctrl_awaddr(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_wvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_wready(),
|
||||
.c0_ddr4_s_axi_ctrl_wdata(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_bvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_bready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_bresp(),
|
||||
.c0_ddr4_s_axi_ctrl_arvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_arready(),
|
||||
.c0_ddr4_s_axi_ctrl_araddr(31'd0),
|
||||
.c0_ddr4_s_axi_ctrl_rvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_rready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_rdata(),
|
||||
.c0_ddr4_s_axi_ctrl_rresp(),
|
||||
|
||||
.c0_ddr4_s_axi_awid(m_axi_ddr_awid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[1*8 +: 8]),
|
||||
.c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[1*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[1*2 +: 2]),
|
||||
.c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[1 +: 1]),
|
||||
.c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[1*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[1*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[1*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_awready(m_axi_ddr_awready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]),
|
||||
.c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[1*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]),
|
||||
.c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[1 +: 1]),
|
||||
.c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_wready(m_axi_ddr_wready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_bready(m_axi_ddr_bready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_bid(m_axi_ddr_bid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[1*2 +: 2]),
|
||||
.c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_arid(m_axi_ddr_arid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[1*8 +: 8]),
|
||||
.c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[1*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[1*2 +: 2]),
|
||||
.c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[1 +: 1]),
|
||||
.c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[1*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[1*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[1*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_arready(m_axi_ddr_arready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_rready(m_axi_ddr_rready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[1 +: 1]),
|
||||
.c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[1*2 +: 2]),
|
||||
.c0_ddr4_s_axi_rid(m_axi_ddr_rid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH])
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign ddr4_c1_adr = {17{1'bz}};
|
||||
assign ddr4_c1_ba = {2{1'bz}};
|
||||
assign ddr4_c1_bg = {2{1'bz}};
|
||||
assign ddr4_c1_cke = 1'bz;
|
||||
assign ddr4_c1_cs_n = 1'bz;
|
||||
assign ddr4_c1_act_n = 1'bz;
|
||||
assign ddr4_c1_odt = 1'bz;
|
||||
assign ddr4_c1_par = 1'bz;
|
||||
assign ddr4_c1_reset_n = 1'b0;
|
||||
assign ddr4_c1_dq = {72{1'bz}};
|
||||
assign ddr4_c1_dqs_t = {18{1'bz}};
|
||||
assign ddr4_c1_dqs_c = {18{1'bz}};
|
||||
|
||||
OBUFTDS ddr4_c1_ck_obuftds_inst (
|
||||
.I(1'b0),
|
||||
.T(1'b1),
|
||||
.O(ddr4_c1_ck_t),
|
||||
.OB(ddr4_c1_ck_c)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
if (DDR_ENABLE && DDR_CH > 2) begin
|
||||
|
||||
ddr4_0 ddr4_c2_inst (
|
||||
.c0_sys_clk_p(clk_300mhz_2_p),
|
||||
.c0_sys_clk_n(clk_300mhz_2_n),
|
||||
.sys_rst(pcie_user_reset),
|
||||
|
||||
.c0_init_calib_complete(ddr_status[2 +: 1]),
|
||||
.c0_ddr4_interrupt(),
|
||||
.dbg_clk(),
|
||||
.dbg_bus(),
|
||||
|
||||
.c0_ddr4_adr(ddr4_c2_adr),
|
||||
.c0_ddr4_ba(ddr4_c2_ba),
|
||||
.c0_ddr4_cke(ddr4_c2_cke),
|
||||
.c0_ddr4_cs_n(ddr4_c2_cs_n),
|
||||
.c0_ddr4_dq(ddr4_c2_dq),
|
||||
.c0_ddr4_dqs_t(ddr4_c2_dqs_t),
|
||||
.c0_ddr4_dqs_c(ddr4_c2_dqs_c),
|
||||
.c0_ddr4_odt(ddr4_c2_odt),
|
||||
.c0_ddr4_parity(ddr4_c2_par),
|
||||
.c0_ddr4_bg(ddr4_c2_bg),
|
||||
.c0_ddr4_reset_n(ddr4_c2_reset_n),
|
||||
.c0_ddr4_act_n(ddr4_c2_act_n),
|
||||
.c0_ddr4_ck_t(ddr4_c2_ck_t),
|
||||
.c0_ddr4_ck_c(ddr4_c2_ck_c),
|
||||
|
||||
.c0_ddr4_ui_clk(ddr_clk[2 +: 1]),
|
||||
.c0_ddr4_ui_clk_sync_rst(ddr_rst[2 +: 1]),
|
||||
|
||||
.c0_ddr4_aresetn(!ddr_rst[2 +: 1]),
|
||||
|
||||
.c0_ddr4_s_axi_ctrl_awvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_awready(),
|
||||
.c0_ddr4_s_axi_ctrl_awaddr(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_wvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_wready(),
|
||||
.c0_ddr4_s_axi_ctrl_wdata(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_bvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_bready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_bresp(),
|
||||
.c0_ddr4_s_axi_ctrl_arvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_arready(),
|
||||
.c0_ddr4_s_axi_ctrl_araddr(31'd0),
|
||||
.c0_ddr4_s_axi_ctrl_rvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_rready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_rdata(),
|
||||
.c0_ddr4_s_axi_ctrl_rresp(),
|
||||
|
||||
.c0_ddr4_s_axi_awid(m_axi_ddr_awid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[2*8 +: 8]),
|
||||
.c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[2*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[2*2 +: 2]),
|
||||
.c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[2 +: 1]),
|
||||
.c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[2*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[2*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[2*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[2 +: 1]),
|
||||
.c0_ddr4_s_axi_awready(m_axi_ddr_awready[2 +: 1]),
|
||||
.c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]),
|
||||
.c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[2*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]),
|
||||
.c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[2 +: 1]),
|
||||
.c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[2 +: 1]),
|
||||
.c0_ddr4_s_axi_wready(m_axi_ddr_wready[2 +: 1]),
|
||||
.c0_ddr4_s_axi_bready(m_axi_ddr_bready[2 +: 1]),
|
||||
.c0_ddr4_s_axi_bid(m_axi_ddr_bid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[2*2 +: 2]),
|
||||
.c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[2 +: 1]),
|
||||
.c0_ddr4_s_axi_arid(m_axi_ddr_arid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[2*8 +: 8]),
|
||||
.c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[2*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[2*2 +: 2]),
|
||||
.c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[2 +: 1]),
|
||||
.c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[2*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[2*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[2*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[2 +: 1]),
|
||||
.c0_ddr4_s_axi_arready(m_axi_ddr_arready[2 +: 1]),
|
||||
.c0_ddr4_s_axi_rready(m_axi_ddr_rready[2 +: 1]),
|
||||
.c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[2 +: 1]),
|
||||
.c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[2 +: 1]),
|
||||
.c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[2*2 +: 2]),
|
||||
.c0_ddr4_s_axi_rid(m_axi_ddr_rid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH])
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign ddr4_c2_adr = {17{1'bz}};
|
||||
assign ddr4_c2_ba = {2{1'bz}};
|
||||
assign ddr4_c2_bg = {2{1'bz}};
|
||||
assign ddr4_c2_cke = 1'bz;
|
||||
assign ddr4_c2_cs_n = 1'bz;
|
||||
assign ddr4_c2_act_n = 1'bz;
|
||||
assign ddr4_c2_odt = 1'bz;
|
||||
assign ddr4_c2_par = 1'bz;
|
||||
assign ddr4_c2_reset_n = 1'b0;
|
||||
assign ddr4_c2_dq = {72{1'bz}};
|
||||
assign ddr4_c2_dqs_t = {18{1'bz}};
|
||||
assign ddr4_c2_dqs_c = {18{1'bz}};
|
||||
|
||||
OBUFTDS ddr4_c2_ck_obuftds_inst (
|
||||
.I(1'b0),
|
||||
.T(1'b1),
|
||||
.O(ddr4_c2_ck_t),
|
||||
.OB(ddr4_c2_ck_c)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
if (DDR_ENABLE && DDR_CH > 3) begin
|
||||
|
||||
ddr4_0 ddr4_c3_inst (
|
||||
.c0_sys_clk_p(clk_300mhz_3_p),
|
||||
.c0_sys_clk_n(clk_300mhz_3_n),
|
||||
.sys_rst(pcie_user_reset),
|
||||
|
||||
.c0_init_calib_complete(ddr_status[3 +: 1]),
|
||||
.c0_ddr4_interrupt(),
|
||||
.dbg_clk(),
|
||||
.dbg_bus(),
|
||||
|
||||
.c0_ddr4_adr(ddr4_c3_adr),
|
||||
.c0_ddr4_ba(ddr4_c3_ba),
|
||||
.c0_ddr4_cke(ddr4_c3_cke),
|
||||
.c0_ddr4_cs_n(ddr4_c3_cs_n),
|
||||
.c0_ddr4_dq(ddr4_c3_dq),
|
||||
.c0_ddr4_dqs_t(ddr4_c3_dqs_t),
|
||||
.c0_ddr4_dqs_c(ddr4_c3_dqs_c),
|
||||
.c0_ddr4_odt(ddr4_c3_odt),
|
||||
.c0_ddr4_parity(ddr4_c3_par),
|
||||
.c0_ddr4_bg(ddr4_c3_bg),
|
||||
.c0_ddr4_reset_n(ddr4_c3_reset_n),
|
||||
.c0_ddr4_act_n(ddr4_c3_act_n),
|
||||
.c0_ddr4_ck_t(ddr4_c3_ck_t),
|
||||
.c0_ddr4_ck_c(ddr4_c3_ck_c),
|
||||
|
||||
.c0_ddr4_ui_clk(ddr_clk[3 +: 1]),
|
||||
.c0_ddr4_ui_clk_sync_rst(ddr_rst[3 +: 1]),
|
||||
|
||||
.c0_ddr4_aresetn(!ddr_rst[3 +: 1]),
|
||||
|
||||
.c0_ddr4_s_axi_ctrl_awvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_awready(),
|
||||
.c0_ddr4_s_axi_ctrl_awaddr(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_wvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_wready(),
|
||||
.c0_ddr4_s_axi_ctrl_wdata(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_bvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_bready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_bresp(),
|
||||
.c0_ddr4_s_axi_ctrl_arvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_arready(),
|
||||
.c0_ddr4_s_axi_ctrl_araddr(31'd0),
|
||||
.c0_ddr4_s_axi_ctrl_rvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_rready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_rdata(),
|
||||
.c0_ddr4_s_axi_ctrl_rresp(),
|
||||
|
||||
.c0_ddr4_s_axi_awid(m_axi_ddr_awid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[3*8 +: 8]),
|
||||
.c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[3*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[3*2 +: 2]),
|
||||
.c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[3 +: 1]),
|
||||
.c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[3*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[3*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[3*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[3 +: 1]),
|
||||
.c0_ddr4_s_axi_awready(m_axi_ddr_awready[3 +: 1]),
|
||||
.c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]),
|
||||
.c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[3*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]),
|
||||
.c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[3 +: 1]),
|
||||
.c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[3 +: 1]),
|
||||
.c0_ddr4_s_axi_wready(m_axi_ddr_wready[3 +: 1]),
|
||||
.c0_ddr4_s_axi_bready(m_axi_ddr_bready[3 +: 1]),
|
||||
.c0_ddr4_s_axi_bid(m_axi_ddr_bid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[3*2 +: 2]),
|
||||
.c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[3 +: 1]),
|
||||
.c0_ddr4_s_axi_arid(m_axi_ddr_arid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[3*8 +: 8]),
|
||||
.c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[3*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[3*2 +: 2]),
|
||||
.c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[3 +: 1]),
|
||||
.c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[3*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[3*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[3*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[3 +: 1]),
|
||||
.c0_ddr4_s_axi_arready(m_axi_ddr_arready[3 +: 1]),
|
||||
.c0_ddr4_s_axi_rready(m_axi_ddr_rready[3 +: 1]),
|
||||
.c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[3 +: 1]),
|
||||
.c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[3 +: 1]),
|
||||
.c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[3*2 +: 2]),
|
||||
.c0_ddr4_s_axi_rid(m_axi_ddr_rid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH])
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign ddr4_c3_adr = {17{1'bz}};
|
||||
assign ddr4_c3_ba = {2{1'bz}};
|
||||
assign ddr4_c3_bg = {2{1'bz}};
|
||||
assign ddr4_c3_cke = 1'bz;
|
||||
assign ddr4_c3_cs_n = 1'bz;
|
||||
assign ddr4_c3_act_n = 1'bz;
|
||||
assign ddr4_c3_odt = 1'bz;
|
||||
assign ddr4_c3_par = 1'bz;
|
||||
assign ddr4_c3_reset_n = 1'b0;
|
||||
assign ddr4_c3_dq = {72{1'bz}};
|
||||
assign ddr4_c3_dqs_t = {18{1'bz}};
|
||||
assign ddr4_c3_dqs_c = {18{1'bz}};
|
||||
|
||||
OBUFTDS ddr4_c3_ck_obuftds_inst (
|
||||
.I(1'b0),
|
||||
.T(1'b1),
|
||||
.O(ddr4_c3_ck_t),
|
||||
.OB(ddr4_c3_ck_c)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
fpga_core #(
|
||||
// FW and board IDs
|
||||
.FPGA_ID(FPGA_ID),
|
||||
@ -1963,6 +2563,16 @@ fpga_core #(
|
||||
.TX_RAM_SIZE(TX_RAM_SIZE),
|
||||
.RX_RAM_SIZE(RX_RAM_SIZE),
|
||||
|
||||
// RAM configuration
|
||||
.DDR_CH(DDR_CH),
|
||||
.DDR_ENABLE(DDR_ENABLE),
|
||||
.AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH),
|
||||
.AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH),
|
||||
.AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH),
|
||||
.AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH),
|
||||
.AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN),
|
||||
.AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST),
|
||||
|
||||
// Application block configuration
|
||||
.APP_ID(APP_ID),
|
||||
.APP_ENABLE(APP_ENABLE),
|
||||
@ -2200,6 +2810,52 @@ core_inst (
|
||||
.qsfp1_intl(qsfp1_intl_int),
|
||||
.qsfp1_lpmode(qsfp1_lpmode),
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
.ddr_clk(ddr_clk),
|
||||
.ddr_rst(ddr_rst),
|
||||
|
||||
.m_axi_ddr_awid(m_axi_ddr_awid),
|
||||
.m_axi_ddr_awaddr(m_axi_ddr_awaddr),
|
||||
.m_axi_ddr_awlen(m_axi_ddr_awlen),
|
||||
.m_axi_ddr_awsize(m_axi_ddr_awsize),
|
||||
.m_axi_ddr_awburst(m_axi_ddr_awburst),
|
||||
.m_axi_ddr_awlock(m_axi_ddr_awlock),
|
||||
.m_axi_ddr_awcache(m_axi_ddr_awcache),
|
||||
.m_axi_ddr_awprot(m_axi_ddr_awprot),
|
||||
.m_axi_ddr_awqos(m_axi_ddr_awqos),
|
||||
.m_axi_ddr_awvalid(m_axi_ddr_awvalid),
|
||||
.m_axi_ddr_awready(m_axi_ddr_awready),
|
||||
.m_axi_ddr_wdata(m_axi_ddr_wdata),
|
||||
.m_axi_ddr_wstrb(m_axi_ddr_wstrb),
|
||||
.m_axi_ddr_wlast(m_axi_ddr_wlast),
|
||||
.m_axi_ddr_wvalid(m_axi_ddr_wvalid),
|
||||
.m_axi_ddr_wready(m_axi_ddr_wready),
|
||||
.m_axi_ddr_bid(m_axi_ddr_bid),
|
||||
.m_axi_ddr_bresp(m_axi_ddr_bresp),
|
||||
.m_axi_ddr_bvalid(m_axi_ddr_bvalid),
|
||||
.m_axi_ddr_bready(m_axi_ddr_bready),
|
||||
.m_axi_ddr_arid(m_axi_ddr_arid),
|
||||
.m_axi_ddr_araddr(m_axi_ddr_araddr),
|
||||
.m_axi_ddr_arlen(m_axi_ddr_arlen),
|
||||
.m_axi_ddr_arsize(m_axi_ddr_arsize),
|
||||
.m_axi_ddr_arburst(m_axi_ddr_arburst),
|
||||
.m_axi_ddr_arlock(m_axi_ddr_arlock),
|
||||
.m_axi_ddr_arcache(m_axi_ddr_arcache),
|
||||
.m_axi_ddr_arprot(m_axi_ddr_arprot),
|
||||
.m_axi_ddr_arqos(m_axi_ddr_arqos),
|
||||
.m_axi_ddr_arvalid(m_axi_ddr_arvalid),
|
||||
.m_axi_ddr_arready(m_axi_ddr_arready),
|
||||
.m_axi_ddr_rid(m_axi_ddr_rid),
|
||||
.m_axi_ddr_rdata(m_axi_ddr_rdata),
|
||||
.m_axi_ddr_rresp(m_axi_ddr_rresp),
|
||||
.m_axi_ddr_rlast(m_axi_ddr_rlast),
|
||||
.m_axi_ddr_rvalid(m_axi_ddr_rvalid),
|
||||
.m_axi_ddr_rready(m_axi_ddr_rready),
|
||||
|
||||
.ddr_status(ddr_status),
|
||||
|
||||
/*
|
||||
* QSPI flash
|
||||
*/
|
||||
|
||||
@ -115,6 +115,16 @@ module fpga_core #
|
||||
parameter TX_RAM_SIZE = 131072,
|
||||
parameter RX_RAM_SIZE = 131072,
|
||||
|
||||
// RAM configuration
|
||||
parameter DDR_CH = 4,
|
||||
parameter DDR_ENABLE = 1,
|
||||
parameter AXI_DDR_DATA_WIDTH = 512,
|
||||
parameter AXI_DDR_ADDR_WIDTH = 34,
|
||||
parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8),
|
||||
parameter AXI_DDR_ID_WIDTH = 8,
|
||||
parameter AXI_DDR_MAX_BURST_LEN = 256,
|
||||
parameter AXI_DDR_NARROW_BURST = 0,
|
||||
|
||||
// Application block configuration
|
||||
parameter APP_ID = 32'h00000000,
|
||||
parameter APP_ENABLE = 0,
|
||||
@ -364,6 +374,52 @@ module fpga_core #
|
||||
input wire qsfp1_intl,
|
||||
output wire qsfp1_lpmode,
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
input wire [DDR_CH-1:0] ddr_clk,
|
||||
input wire [DDR_CH-1:0] ddr_rst,
|
||||
|
||||
output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid,
|
||||
output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr,
|
||||
output wire [DDR_CH*8-1:0] m_axi_ddr_awlen,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_awsize,
|
||||
output wire [DDR_CH*2-1:0] m_axi_ddr_awburst,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_awlock,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_awcache,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_awprot,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_awqos,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_awvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_awready,
|
||||
output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata,
|
||||
output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_wlast,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_wvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_wready,
|
||||
input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid,
|
||||
input wire [DDR_CH*2-1:0] m_axi_ddr_bresp,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_bvalid,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_bready,
|
||||
output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid,
|
||||
output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr,
|
||||
output wire [DDR_CH*8-1:0] m_axi_ddr_arlen,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_arsize,
|
||||
output wire [DDR_CH*2-1:0] m_axi_ddr_arburst,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_arlock,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_arcache,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_arprot,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_arqos,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_arvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_arready,
|
||||
input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid,
|
||||
input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata,
|
||||
input wire [DDR_CH*2-1:0] m_axi_ddr_rresp,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_rlast,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_rvalid,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_rready,
|
||||
|
||||
input wire [DDR_CH-1:0] ddr_status,
|
||||
|
||||
/*
|
||||
* QSPI flash
|
||||
*/
|
||||
@ -903,6 +959,25 @@ mqnic_core_pcie_us #(
|
||||
.TX_RAM_SIZE(TX_RAM_SIZE),
|
||||
.RX_RAM_SIZE(RX_RAM_SIZE),
|
||||
|
||||
// RAM configuration
|
||||
.DDR_CH(DDR_CH),
|
||||
.DDR_ENABLE(DDR_ENABLE),
|
||||
.DDR_GROUP_SIZE(1),
|
||||
.AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH),
|
||||
.AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH),
|
||||
.AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH),
|
||||
.AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH),
|
||||
.AXI_DDR_AWUSER_ENABLE(0),
|
||||
.AXI_DDR_WUSER_ENABLE(0),
|
||||
.AXI_DDR_BUSER_ENABLE(0),
|
||||
.AXI_DDR_ARUSER_ENABLE(0),
|
||||
.AXI_DDR_RUSER_ENABLE(0),
|
||||
.AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN),
|
||||
.AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST),
|
||||
.AXI_DDR_FIXED_BURST(0),
|
||||
.AXI_DDR_WRAP_BURST(1),
|
||||
.HBM_ENABLE(0),
|
||||
|
||||
// Application block configuration
|
||||
.APP_ID(APP_ID),
|
||||
.APP_ENABLE(APP_ENABLE),
|
||||
@ -1180,6 +1255,108 @@ core_inst (
|
||||
|
||||
.eth_rx_status(eth_rx_status),
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
.ddr_clk(ddr_clk),
|
||||
.ddr_rst(ddr_rst),
|
||||
|
||||
.m_axi_ddr_awid(m_axi_ddr_awid),
|
||||
.m_axi_ddr_awaddr(m_axi_ddr_awaddr),
|
||||
.m_axi_ddr_awlen(m_axi_ddr_awlen),
|
||||
.m_axi_ddr_awsize(m_axi_ddr_awsize),
|
||||
.m_axi_ddr_awburst(m_axi_ddr_awburst),
|
||||
.m_axi_ddr_awlock(m_axi_ddr_awlock),
|
||||
.m_axi_ddr_awcache(m_axi_ddr_awcache),
|
||||
.m_axi_ddr_awprot(m_axi_ddr_awprot),
|
||||
.m_axi_ddr_awqos(m_axi_ddr_awqos),
|
||||
.m_axi_ddr_awuser(),
|
||||
.m_axi_ddr_awvalid(m_axi_ddr_awvalid),
|
||||
.m_axi_ddr_awready(m_axi_ddr_awready),
|
||||
.m_axi_ddr_wdata(m_axi_ddr_wdata),
|
||||
.m_axi_ddr_wstrb(m_axi_ddr_wstrb),
|
||||
.m_axi_ddr_wlast(m_axi_ddr_wlast),
|
||||
.m_axi_ddr_wuser(),
|
||||
.m_axi_ddr_wvalid(m_axi_ddr_wvalid),
|
||||
.m_axi_ddr_wready(m_axi_ddr_wready),
|
||||
.m_axi_ddr_bid(m_axi_ddr_bid),
|
||||
.m_axi_ddr_bresp(m_axi_ddr_bresp),
|
||||
.m_axi_ddr_buser(0),
|
||||
.m_axi_ddr_bvalid(m_axi_ddr_bvalid),
|
||||
.m_axi_ddr_bready(m_axi_ddr_bready),
|
||||
.m_axi_ddr_arid(m_axi_ddr_arid),
|
||||
.m_axi_ddr_araddr(m_axi_ddr_araddr),
|
||||
.m_axi_ddr_arlen(m_axi_ddr_arlen),
|
||||
.m_axi_ddr_arsize(m_axi_ddr_arsize),
|
||||
.m_axi_ddr_arburst(m_axi_ddr_arburst),
|
||||
.m_axi_ddr_arlock(m_axi_ddr_arlock),
|
||||
.m_axi_ddr_arcache(m_axi_ddr_arcache),
|
||||
.m_axi_ddr_arprot(m_axi_ddr_arprot),
|
||||
.m_axi_ddr_arqos(m_axi_ddr_arqos),
|
||||
.m_axi_ddr_aruser(),
|
||||
.m_axi_ddr_arvalid(m_axi_ddr_arvalid),
|
||||
.m_axi_ddr_arready(m_axi_ddr_arready),
|
||||
.m_axi_ddr_rid(m_axi_ddr_rid),
|
||||
.m_axi_ddr_rdata(m_axi_ddr_rdata),
|
||||
.m_axi_ddr_rresp(m_axi_ddr_rresp),
|
||||
.m_axi_ddr_rlast(m_axi_ddr_rlast),
|
||||
.m_axi_ddr_ruser(0),
|
||||
.m_axi_ddr_rvalid(m_axi_ddr_rvalid),
|
||||
.m_axi_ddr_rready(m_axi_ddr_rready),
|
||||
|
||||
.ddr_status(ddr_status),
|
||||
|
||||
/*
|
||||
* HBM
|
||||
*/
|
||||
.hbm_clk(0),
|
||||
.hbm_rst(0),
|
||||
|
||||
.m_axi_hbm_awid(),
|
||||
.m_axi_hbm_awaddr(),
|
||||
.m_axi_hbm_awlen(),
|
||||
.m_axi_hbm_awsize(),
|
||||
.m_axi_hbm_awburst(),
|
||||
.m_axi_hbm_awlock(),
|
||||
.m_axi_hbm_awcache(),
|
||||
.m_axi_hbm_awprot(),
|
||||
.m_axi_hbm_awqos(),
|
||||
.m_axi_hbm_awuser(),
|
||||
.m_axi_hbm_awvalid(),
|
||||
.m_axi_hbm_awready(0),
|
||||
.m_axi_hbm_wdata(),
|
||||
.m_axi_hbm_wstrb(),
|
||||
.m_axi_hbm_wlast(),
|
||||
.m_axi_hbm_wuser(),
|
||||
.m_axi_hbm_wvalid(),
|
||||
.m_axi_hbm_wready(0),
|
||||
.m_axi_hbm_bid(0),
|
||||
.m_axi_hbm_bresp(0),
|
||||
.m_axi_hbm_buser(0),
|
||||
.m_axi_hbm_bvalid(0),
|
||||
.m_axi_hbm_bready(),
|
||||
.m_axi_hbm_arid(),
|
||||
.m_axi_hbm_araddr(),
|
||||
.m_axi_hbm_arlen(),
|
||||
.m_axi_hbm_arsize(),
|
||||
.m_axi_hbm_arburst(),
|
||||
.m_axi_hbm_arlock(),
|
||||
.m_axi_hbm_arcache(),
|
||||
.m_axi_hbm_arprot(),
|
||||
.m_axi_hbm_arqos(),
|
||||
.m_axi_hbm_aruser(),
|
||||
.m_axi_hbm_arvalid(),
|
||||
.m_axi_hbm_arready(0),
|
||||
.m_axi_hbm_rid(0),
|
||||
.m_axi_hbm_rdata(0),
|
||||
.m_axi_hbm_rresp(0),
|
||||
.m_axi_hbm_rlast(0),
|
||||
.m_axi_hbm_ruser(0),
|
||||
.m_axi_hbm_rvalid(0),
|
||||
.m_axi_hbm_rready(),
|
||||
|
||||
.hbm_status(0),
|
||||
|
||||
/*
|
||||
* Statistics input
|
||||
*/
|
||||
|
||||
@ -4,8 +4,9 @@
|
||||
|
||||
This design targets the Xilinx Alveo U250 FPGA board.
|
||||
|
||||
FPGA: xcu250-figd2104-2-e
|
||||
PHY: 10G BASE-R PHY IP core and internal GTY transceiver
|
||||
* FPGA: xcu250-figd2104-2-e
|
||||
* PHY: 10G BASE-R PHY IP core and internal GTY transceiver
|
||||
* RAM: 64 GB DDR4 2400 (4x 2G x72 DIMM)
|
||||
|
||||
## How to build
|
||||
|
||||
|
||||
@ -17,23 +17,23 @@ set_operating_conditions -design_power_budget 160
|
||||
|
||||
# System clocks
|
||||
# 300 MHz (DDR 0)
|
||||
#set_property -dict {LOC AY37 IOSTANDARD LVDS} [get_ports clk_300mhz_0_p]
|
||||
#set_property -dict {LOC AY38 IOSTANDARD LVDS} [get_ports clk_300mhz_0_n]
|
||||
set_property -dict {LOC AY37 IOSTANDARD LVDS} [get_ports clk_300mhz_0_p]
|
||||
set_property -dict {LOC AY38 IOSTANDARD LVDS} [get_ports clk_300mhz_0_n]
|
||||
#create_clock -period 3.333 -name clk_300mhz_0 [get_ports clk_300mhz_0_p]
|
||||
|
||||
# 300 MHz (DDR 1)
|
||||
#set_property -dict {LOC AW20 IOSTANDARD LVDS} [get_ports clk_300mhz_1_p]
|
||||
#set_property -dict {LOC AW19 IOSTANDARD LVDS} [get_ports clk_300mhz_1_n]
|
||||
set_property -dict {LOC AW20 IOSTANDARD LVDS} [get_ports clk_300mhz_1_p]
|
||||
set_property -dict {LOC AW19 IOSTANDARD LVDS} [get_ports clk_300mhz_1_n]
|
||||
#create_clock -period 3.333 -name clk_300mhz_1 [get_ports clk_300mhz_1_p]
|
||||
|
||||
# 300 MHz (DDR 2)
|
||||
#set_property -dict {LOC F32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_p]
|
||||
#set_property -dict {LOC E32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_n]
|
||||
set_property -dict {LOC F32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_p]
|
||||
set_property -dict {LOC E32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_n]
|
||||
#create_clock -period 3.333 -name clk_300mhz_2 [get_ports clk_300mhz_2_p]
|
||||
|
||||
# 300 MHz (DDR 3)
|
||||
#set_property -dict {LOC J16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_p]
|
||||
#set_property -dict {LOC H16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_n]
|
||||
set_property -dict {LOC J16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_p]
|
||||
set_property -dict {LOC H16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_n]
|
||||
#create_clock -period 3.333 -name clk_300mhz_3 [get_ports clk_300mhz_3_p]
|
||||
|
||||
# SI570 user clock
|
||||
@ -257,3 +257,591 @@ create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_p]
|
||||
|
||||
set_false_path -from [get_ports {pcie_reset_n}]
|
||||
set_input_delay 0 [get_ports {pcie_reset_n}]
|
||||
|
||||
# DDR4 C0
|
||||
set_property -dict {LOC AT36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}]
|
||||
set_property -dict {LOC AV36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}]
|
||||
set_property -dict {LOC AV37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}]
|
||||
set_property -dict {LOC AW35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}]
|
||||
set_property -dict {LOC AW36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}]
|
||||
set_property -dict {LOC AY36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}]
|
||||
set_property -dict {LOC AY35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}]
|
||||
set_property -dict {LOC BA40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}]
|
||||
set_property -dict {LOC BA37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}]
|
||||
set_property -dict {LOC BB37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}]
|
||||
set_property -dict {LOC AR35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}]
|
||||
set_property -dict {LOC BA39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}]
|
||||
set_property -dict {LOC BB40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}]
|
||||
set_property -dict {LOC AN36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}]
|
||||
set_property -dict {LOC AP35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}]
|
||||
set_property -dict {LOC AP36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}]
|
||||
set_property -dict {LOC AR36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}]
|
||||
set_property -dict {LOC AT35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}]
|
||||
set_property -dict {LOC AT34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}]
|
||||
set_property -dict {LOC BC37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}]
|
||||
set_property -dict {LOC BC39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}]
|
||||
set_property -dict {LOC AV38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t[0]}]
|
||||
set_property -dict {LOC AW38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c[0]}]
|
||||
#set_property -dict {LOC AU34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t[1]}]
|
||||
#set_property -dict {LOC AU35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c[1]}]
|
||||
set_property -dict {LOC BC38 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[0]}]
|
||||
#set_property -dict {LOC BC40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[1]}]
|
||||
set_property -dict {LOC AR33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[0]}]
|
||||
#set_property -dict {LOC AP33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[1]}]
|
||||
#set_property -dict {LOC AN33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[2]}]
|
||||
#set_property -dict {LOC AM34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[3]}]
|
||||
set_property -dict {LOC BB39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}]
|
||||
set_property -dict {LOC AP34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[0]}]
|
||||
#set_property -dict {LOC AN34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[1]}]
|
||||
set_property -dict {LOC AU36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}]
|
||||
set_property -dict {LOC AU31 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_reset_n}]
|
||||
|
||||
set_property -dict {LOC AW28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}]
|
||||
set_property -dict {LOC AW29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}]
|
||||
set_property -dict {LOC BA28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}]
|
||||
set_property -dict {LOC BA27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}]
|
||||
set_property -dict {LOC BB29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}]
|
||||
set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}]
|
||||
set_property -dict {LOC BC27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}]
|
||||
set_property -dict {LOC BB27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}]
|
||||
set_property -dict {LOC BE28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}]
|
||||
set_property -dict {LOC BF28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}]
|
||||
set_property -dict {LOC BE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}]
|
||||
set_property -dict {LOC BD30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}]
|
||||
set_property -dict {LOC BF27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}]
|
||||
set_property -dict {LOC BE27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}]
|
||||
set_property -dict {LOC BF30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}]
|
||||
set_property -dict {LOC BF29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}]
|
||||
set_property -dict {LOC BB31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}]
|
||||
set_property -dict {LOC BB32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}]
|
||||
set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}]
|
||||
set_property -dict {LOC AY33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}]
|
||||
set_property -dict {LOC BC32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}]
|
||||
set_property -dict {LOC BC33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}]
|
||||
set_property -dict {LOC BB34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}]
|
||||
set_property -dict {LOC BC34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}]
|
||||
set_property -dict {LOC AV31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}]
|
||||
set_property -dict {LOC AV32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}]
|
||||
set_property -dict {LOC AV34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}]
|
||||
set_property -dict {LOC AW34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}]
|
||||
set_property -dict {LOC AW31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}]
|
||||
set_property -dict {LOC AY31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}]
|
||||
set_property -dict {LOC BA35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}]
|
||||
set_property -dict {LOC BA34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}]
|
||||
set_property -dict {LOC AL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}]
|
||||
set_property -dict {LOC AM30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}]
|
||||
set_property -dict {LOC AU32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}]
|
||||
set_property -dict {LOC AT32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}]
|
||||
set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}]
|
||||
set_property -dict {LOC AN32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}]
|
||||
set_property -dict {LOC AR32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}]
|
||||
set_property -dict {LOC AR31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}]
|
||||
set_property -dict {LOC AP29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}]
|
||||
set_property -dict {LOC AP28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}]
|
||||
set_property -dict {LOC AN27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}]
|
||||
set_property -dict {LOC AM27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}]
|
||||
set_property -dict {LOC AN29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}]
|
||||
set_property -dict {LOC AM29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}]
|
||||
set_property -dict {LOC AR27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}]
|
||||
set_property -dict {LOC AR28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}]
|
||||
set_property -dict {LOC AT28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}]
|
||||
set_property -dict {LOC AV27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}]
|
||||
set_property -dict {LOC AU27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}]
|
||||
set_property -dict {LOC AT27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}]
|
||||
set_property -dict {LOC AV29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}]
|
||||
set_property -dict {LOC AY30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}]
|
||||
set_property -dict {LOC AW30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}]
|
||||
set_property -dict {LOC AV28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}]
|
||||
set_property -dict {LOC BD34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}]
|
||||
set_property -dict {LOC BD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}]
|
||||
set_property -dict {LOC BE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}]
|
||||
set_property -dict {LOC BD35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}]
|
||||
set_property -dict {LOC BF32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}]
|
||||
set_property -dict {LOC BF33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}]
|
||||
set_property -dict {LOC BF34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}]
|
||||
set_property -dict {LOC BF35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}]
|
||||
set_property -dict {LOC BD40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}]
|
||||
set_property -dict {LOC BD39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}]
|
||||
set_property -dict {LOC BF43 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}]
|
||||
set_property -dict {LOC BF42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}]
|
||||
set_property -dict {LOC BF37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}]
|
||||
set_property -dict {LOC BE37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}]
|
||||
set_property -dict {LOC BE40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}]
|
||||
set_property -dict {LOC BF41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}]
|
||||
set_property -dict {LOC BA30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}]
|
||||
set_property -dict {LOC BB30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}]
|
||||
set_property -dict {LOC BB26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}]
|
||||
set_property -dict {LOC BC26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}]
|
||||
set_property -dict {LOC BD28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}]
|
||||
set_property -dict {LOC BD29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}]
|
||||
set_property -dict {LOC BD26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}]
|
||||
set_property -dict {LOC BE26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}]
|
||||
set_property -dict {LOC BB35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}]
|
||||
set_property -dict {LOC BB36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}]
|
||||
set_property -dict {LOC BC31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}]
|
||||
set_property -dict {LOC BD31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}]
|
||||
set_property -dict {LOC AV33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}]
|
||||
set_property -dict {LOC AW33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}]
|
||||
set_property -dict {LOC BA32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}]
|
||||
set_property -dict {LOC BA33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}]
|
||||
set_property -dict {LOC AM31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}]
|
||||
set_property -dict {LOC AM32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}]
|
||||
set_property -dict {LOC AP30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[9]}]
|
||||
set_property -dict {LOC AP31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[9]}]
|
||||
set_property -dict {LOC AL28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[10]}]
|
||||
set_property -dict {LOC AL29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[10]}]
|
||||
set_property -dict {LOC AR30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[11]}]
|
||||
set_property -dict {LOC AT30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[11]}]
|
||||
set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[12]}]
|
||||
set_property -dict {LOC AU30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[12]}]
|
||||
set_property -dict {LOC AY27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[13]}]
|
||||
set_property -dict {LOC AY28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[13]}]
|
||||
set_property -dict {LOC BE35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[14]}]
|
||||
set_property -dict {LOC BE36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[14]}]
|
||||
set_property -dict {LOC BE31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[15]}]
|
||||
set_property -dict {LOC BE32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[15]}]
|
||||
set_property -dict {LOC BE38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[16]}]
|
||||
set_property -dict {LOC BF38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[16]}]
|
||||
set_property -dict {LOC BF39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[17]}]
|
||||
set_property -dict {LOC BF40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[17]}]
|
||||
|
||||
# DDR4 C1
|
||||
set_property -dict {LOC AN24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}]
|
||||
set_property -dict {LOC AT24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}]
|
||||
set_property -dict {LOC AW24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}]
|
||||
set_property -dict {LOC AN26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}]
|
||||
set_property -dict {LOC AY22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}]
|
||||
set_property -dict {LOC AY23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}]
|
||||
set_property -dict {LOC AV24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}]
|
||||
set_property -dict {LOC BA22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}]
|
||||
set_property -dict {LOC AY25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}]
|
||||
set_property -dict {LOC BA23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}]
|
||||
set_property -dict {LOC AM26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}]
|
||||
set_property -dict {LOC BA25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}]
|
||||
set_property -dict {LOC BB22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}]
|
||||
set_property -dict {LOC AL24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}]
|
||||
set_property -dict {LOC AL25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}]
|
||||
set_property -dict {LOC AM25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}]
|
||||
set_property -dict {LOC AN23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}]
|
||||
set_property -dict {LOC AU24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}]
|
||||
set_property -dict {LOC AP26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}]
|
||||
set_property -dict {LOC BC22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}]
|
||||
set_property -dict {LOC AW26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}]
|
||||
set_property -dict {LOC AT25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t[0]}]
|
||||
set_property -dict {LOC AU25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c[0]}]
|
||||
#set_property -dict {LOC AU26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t[1]}]
|
||||
#set_property -dict {LOC AV26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c[1]}]
|
||||
set_property -dict {LOC BB25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[0]}]
|
||||
#set_property -dict {LOC BB24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[1]}]
|
||||
set_property -dict {LOC AV23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[0]}]
|
||||
#set_property -dict {LOC AP25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[1]}]
|
||||
#set_property -dict {LOC AR23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[2]}]
|
||||
#set_property -dict {LOC AP23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[3]}]
|
||||
set_property -dict {LOC AW25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}]
|
||||
set_property -dict {LOC AW23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[0]}]
|
||||
#set_property -dict {LOC AP24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[1]}]
|
||||
set_property -dict {LOC AT23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}]
|
||||
set_property -dict {LOC AR17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}]
|
||||
|
||||
set_property -dict {LOC BD9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}]
|
||||
set_property -dict {LOC BD7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}]
|
||||
set_property -dict {LOC BC7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}]
|
||||
set_property -dict {LOC BD8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}]
|
||||
set_property -dict {LOC BD10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}]
|
||||
set_property -dict {LOC BE10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}]
|
||||
set_property -dict {LOC BE7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}]
|
||||
set_property -dict {LOC BF7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}]
|
||||
set_property -dict {LOC AU13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}]
|
||||
set_property -dict {LOC AV13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}]
|
||||
set_property -dict {LOC AW13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}]
|
||||
set_property -dict {LOC AW14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}]
|
||||
set_property -dict {LOC AU14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}]
|
||||
set_property -dict {LOC AY11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}]
|
||||
set_property -dict {LOC AV14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}]
|
||||
set_property -dict {LOC BA11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}]
|
||||
set_property -dict {LOC BA12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}]
|
||||
set_property -dict {LOC BB12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}]
|
||||
set_property -dict {LOC BA13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}]
|
||||
set_property -dict {LOC BA14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}]
|
||||
set_property -dict {LOC BC9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}]
|
||||
set_property -dict {LOC BB9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}]
|
||||
set_property -dict {LOC BA7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}]
|
||||
set_property -dict {LOC BA8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}]
|
||||
set_property -dict {LOC AN13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}]
|
||||
set_property -dict {LOC AR13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}]
|
||||
set_property -dict {LOC AM13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}]
|
||||
set_property -dict {LOC AP13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}]
|
||||
set_property -dict {LOC AM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}]
|
||||
set_property -dict {LOC AR15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}]
|
||||
set_property -dict {LOC AL14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}]
|
||||
set_property -dict {LOC AT15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}]
|
||||
set_property -dict {LOC BE13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}]
|
||||
set_property -dict {LOC BD14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}]
|
||||
set_property -dict {LOC BF12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}]
|
||||
set_property -dict {LOC BD13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}]
|
||||
set_property -dict {LOC BD15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}]
|
||||
set_property -dict {LOC BD16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}]
|
||||
set_property -dict {LOC BF14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}]
|
||||
set_property -dict {LOC BF13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}]
|
||||
set_property -dict {LOC AY17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}]
|
||||
set_property -dict {LOC BA17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}]
|
||||
set_property -dict {LOC AY18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}]
|
||||
set_property -dict {LOC BA18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}]
|
||||
set_property -dict {LOC BA15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}]
|
||||
set_property -dict {LOC BB15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}]
|
||||
set_property -dict {LOC BC11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}]
|
||||
set_property -dict {LOC BD11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}]
|
||||
set_property -dict {LOC AV16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}]
|
||||
set_property -dict {LOC AV17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}]
|
||||
set_property -dict {LOC AU16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}]
|
||||
set_property -dict {LOC AU17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}]
|
||||
set_property -dict {LOC BB17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}]
|
||||
set_property -dict {LOC BB16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}]
|
||||
set_property -dict {LOC AT18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}]
|
||||
set_property -dict {LOC AT17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}]
|
||||
set_property -dict {LOC AM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}]
|
||||
set_property -dict {LOC AL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}]
|
||||
set_property -dict {LOC AN17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}]
|
||||
set_property -dict {LOC AN16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}]
|
||||
set_property -dict {LOC AR18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}]
|
||||
set_property -dict {LOC AP18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}]
|
||||
set_property -dict {LOC AL17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}]
|
||||
set_property -dict {LOC AL16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}]
|
||||
set_property -dict {LOC BF25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}]
|
||||
set_property -dict {LOC BF24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}]
|
||||
set_property -dict {LOC BD25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}]
|
||||
set_property -dict {LOC BE25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}]
|
||||
set_property -dict {LOC BD23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}]
|
||||
set_property -dict {LOC BC23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}]
|
||||
set_property -dict {LOC BF23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}]
|
||||
set_property -dict {LOC BE23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}]
|
||||
set_property -dict {LOC BF10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}]
|
||||
set_property -dict {LOC BF9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}]
|
||||
set_property -dict {LOC BE8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}]
|
||||
set_property -dict {LOC BF8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}]
|
||||
set_property -dict {LOC AW15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}]
|
||||
set_property -dict {LOC AY15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}]
|
||||
set_property -dict {LOC AY13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}]
|
||||
set_property -dict {LOC AY12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}]
|
||||
set_property -dict {LOC BB11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}]
|
||||
set_property -dict {LOC BB10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}]
|
||||
set_property -dict {LOC BA10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}]
|
||||
set_property -dict {LOC BA9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}]
|
||||
set_property -dict {LOC AT14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}]
|
||||
set_property -dict {LOC AT13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}]
|
||||
set_property -dict {LOC AN14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}]
|
||||
set_property -dict {LOC AP14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}]
|
||||
set_property -dict {LOC BE12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}]
|
||||
set_property -dict {LOC BE11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}]
|
||||
set_property -dict {LOC BE15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}]
|
||||
set_property -dict {LOC BF15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}]
|
||||
set_property -dict {LOC BC13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[10]}]
|
||||
set_property -dict {LOC BC12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[10]}]
|
||||
set_property -dict {LOC BB14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[11]}]
|
||||
set_property -dict {LOC BC14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[11]}]
|
||||
set_property -dict {LOC AV18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[12]}]
|
||||
set_property -dict {LOC AW18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[12]}]
|
||||
set_property -dict {LOC AW16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[13]}]
|
||||
set_property -dict {LOC AY16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[13]}]
|
||||
set_property -dict {LOC AP16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[14]}]
|
||||
set_property -dict {LOC AR16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[14]}]
|
||||
set_property -dict {LOC AM17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[15]}]
|
||||
set_property -dict {LOC AM16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[15]}]
|
||||
set_property -dict {LOC BC24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[16]}]
|
||||
set_property -dict {LOC BD24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[16]}]
|
||||
set_property -dict {LOC BE22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[17]}]
|
||||
set_property -dict {LOC BF22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[17]}]
|
||||
|
||||
# DDR4 C2
|
||||
set_property -dict {LOC L29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[0]}]
|
||||
set_property -dict {LOC A33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[1]}]
|
||||
set_property -dict {LOC C33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[2]}]
|
||||
set_property -dict {LOC J29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[3]}]
|
||||
set_property -dict {LOC H31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[4]}]
|
||||
set_property -dict {LOC G31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[5]}]
|
||||
set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[6]}]
|
||||
set_property -dict {LOC B32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[7]}]
|
||||
set_property -dict {LOC A32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[8]}]
|
||||
set_property -dict {LOC D31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[9]}]
|
||||
set_property -dict {LOC A34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[10]}]
|
||||
set_property -dict {LOC E31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[11]}]
|
||||
set_property -dict {LOC M30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[12]}]
|
||||
set_property -dict {LOC F33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[13]}]
|
||||
set_property -dict {LOC A35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[14]}]
|
||||
set_property -dict {LOC G32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[15]}]
|
||||
set_property -dict {LOC K30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[16]}]
|
||||
set_property -dict {LOC D33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[0]}]
|
||||
set_property -dict {LOC B36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[1]}]
|
||||
set_property -dict {LOC C31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[0]}]
|
||||
set_property -dict {LOC J30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[1]}]
|
||||
set_property -dict {LOC C34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t[0]}]
|
||||
set_property -dict {LOC B34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c[0]}]
|
||||
#set_property -dict {LOC D34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t[1]}]
|
||||
#set_property -dict {LOC D35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c[1]}]
|
||||
set_property -dict {LOC G30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[0]}]
|
||||
#set_property -dict {LOC E30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[1]}]
|
||||
set_property -dict {LOC B35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[0]}]
|
||||
#set_property -dict {LOC J31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[1]}]
|
||||
#set_property -dict {LOC L30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[2]}]
|
||||
#set_property -dict {LOC K31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[3]}]
|
||||
set_property -dict {LOC B31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_act_n}]
|
||||
set_property -dict {LOC E33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[0]}]
|
||||
#set_property -dict {LOC F34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[1]}]
|
||||
set_property -dict {LOC M29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_par}]
|
||||
set_property -dict {LOC D36 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_reset_n}]
|
||||
|
||||
set_property -dict {LOC R25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[0]}]
|
||||
set_property -dict {LOC P25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[1]}]
|
||||
set_property -dict {LOC M25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[2]}]
|
||||
set_property -dict {LOC L25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[3]}]
|
||||
set_property -dict {LOC P26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[4]}]
|
||||
set_property -dict {LOC R26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[5]}]
|
||||
set_property -dict {LOC N27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[6]}]
|
||||
set_property -dict {LOC N28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[7]}]
|
||||
set_property -dict {LOC J28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[8]}]
|
||||
set_property -dict {LOC H29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[9]}]
|
||||
set_property -dict {LOC H28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[10]}]
|
||||
set_property -dict {LOC G29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[11]}]
|
||||
set_property -dict {LOC K25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[12]}]
|
||||
set_property -dict {LOC L27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[13]}]
|
||||
set_property -dict {LOC K26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[14]}]
|
||||
set_property -dict {LOC K27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[15]}]
|
||||
set_property -dict {LOC F27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[16]}]
|
||||
set_property -dict {LOC E27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[17]}]
|
||||
set_property -dict {LOC E28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[18]}]
|
||||
set_property -dict {LOC D28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[19]}]
|
||||
set_property -dict {LOC G27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[20]}]
|
||||
set_property -dict {LOC G26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[21]}]
|
||||
set_property -dict {LOC F28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[22]}]
|
||||
set_property -dict {LOC F29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[23]}]
|
||||
set_property -dict {LOC D26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[24]}]
|
||||
set_property -dict {LOC C26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[25]}]
|
||||
set_property -dict {LOC B27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[26]}]
|
||||
set_property -dict {LOC B26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[27]}]
|
||||
set_property -dict {LOC A29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[28]}]
|
||||
set_property -dict {LOC A30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[29]}]
|
||||
set_property -dict {LOC C27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[30]}]
|
||||
set_property -dict {LOC C28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[31]}]
|
||||
set_property -dict {LOC F35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[32]}]
|
||||
set_property -dict {LOC E38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[33]}]
|
||||
set_property -dict {LOC D38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[34]}]
|
||||
set_property -dict {LOC E35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[35]}]
|
||||
set_property -dict {LOC E36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[36]}]
|
||||
set_property -dict {LOC E37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[37]}]
|
||||
set_property -dict {LOC F38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[38]}]
|
||||
set_property -dict {LOC G38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[39]}]
|
||||
set_property -dict {LOC P30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[40]}]
|
||||
set_property -dict {LOC R30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[41]}]
|
||||
set_property -dict {LOC P29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[42]}]
|
||||
set_property -dict {LOC N29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[43]}]
|
||||
set_property -dict {LOC L32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[44]}]
|
||||
set_property -dict {LOC M32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[45]}]
|
||||
set_property -dict {LOC P31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[46]}]
|
||||
set_property -dict {LOC N32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[47]}]
|
||||
set_property -dict {LOC J35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[48]}]
|
||||
set_property -dict {LOC K35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[49]}]
|
||||
set_property -dict {LOC L33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[50]}]
|
||||
set_property -dict {LOC K33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[51]}]
|
||||
set_property -dict {LOC J34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[52]}]
|
||||
set_property -dict {LOC J33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[53]}]
|
||||
set_property -dict {LOC N34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[54]}]
|
||||
set_property -dict {LOC P34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[55]}]
|
||||
set_property -dict {LOC H36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[56]}]
|
||||
set_property -dict {LOC G36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[57]}]
|
||||
set_property -dict {LOC H37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[58]}]
|
||||
set_property -dict {LOC J36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[59]}]
|
||||
set_property -dict {LOC K37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[60]}]
|
||||
set_property -dict {LOC K38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[61]}]
|
||||
set_property -dict {LOC G35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[62]}]
|
||||
set_property -dict {LOC G34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[63]}]
|
||||
set_property -dict {LOC C36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[64]}]
|
||||
set_property -dict {LOC B37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[65]}]
|
||||
set_property -dict {LOC A37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[66]}]
|
||||
set_property -dict {LOC A38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[67]}]
|
||||
set_property -dict {LOC C39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[68]}]
|
||||
set_property -dict {LOC D39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[69]}]
|
||||
set_property -dict {LOC A40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[70]}]
|
||||
set_property -dict {LOC B40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[71]}]
|
||||
set_property -dict {LOC N26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[0]}]
|
||||
set_property -dict {LOC M26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[0]}]
|
||||
set_property -dict {LOC R28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[1]}]
|
||||
set_property -dict {LOC P28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[1]}]
|
||||
set_property -dict {LOC J25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[2]}]
|
||||
set_property -dict {LOC J26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[2]}]
|
||||
set_property -dict {LOC M27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[3]}]
|
||||
set_property -dict {LOC L28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[3]}]
|
||||
set_property -dict {LOC D29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[4]}]
|
||||
set_property -dict {LOC D30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[4]}]
|
||||
set_property -dict {LOC H26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[5]}]
|
||||
set_property -dict {LOC H27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[5]}]
|
||||
set_property -dict {LOC A27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[6]}]
|
||||
set_property -dict {LOC A28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[6]}]
|
||||
set_property -dict {LOC C29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[7]}]
|
||||
set_property -dict {LOC B29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[7]}]
|
||||
set_property -dict {LOC E39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[8]}]
|
||||
set_property -dict {LOC E40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[8]}]
|
||||
set_property -dict {LOC G37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[9]}]
|
||||
set_property -dict {LOC F37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[9]}]
|
||||
set_property -dict {LOC N31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[10]}]
|
||||
set_property -dict {LOC M31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[10]}]
|
||||
set_property -dict {LOC T30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[11]}]
|
||||
set_property -dict {LOC R31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[11]}]
|
||||
set_property -dict {LOC L35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[12]}]
|
||||
set_property -dict {LOC L36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[12]}]
|
||||
set_property -dict {LOC M34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[13]}]
|
||||
set_property -dict {LOC L34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[13]}]
|
||||
set_property -dict {LOC J38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[14]}]
|
||||
set_property -dict {LOC H38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[14]}]
|
||||
set_property -dict {LOC H33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[15]}]
|
||||
set_property -dict {LOC H34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[15]}]
|
||||
set_property -dict {LOC B39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[16]}]
|
||||
set_property -dict {LOC A39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[16]}]
|
||||
set_property -dict {LOC C37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[17]}]
|
||||
set_property -dict {LOC C38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[17]}]
|
||||
|
||||
# DDR4 C3
|
||||
set_property -dict {LOC K15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[0]}]
|
||||
set_property -dict {LOC B15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[1]}]
|
||||
set_property -dict {LOC F14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[2]}]
|
||||
set_property -dict {LOC A15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[3]}]
|
||||
set_property -dict {LOC C14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[4]}]
|
||||
set_property -dict {LOC A14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[5]}]
|
||||
set_property -dict {LOC B14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[6]}]
|
||||
set_property -dict {LOC E13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[7]}]
|
||||
set_property -dict {LOC F13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[8]}]
|
||||
set_property -dict {LOC A13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[9]}]
|
||||
set_property -dict {LOC D14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[10]}]
|
||||
set_property -dict {LOC C13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[11]}]
|
||||
set_property -dict {LOC B13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[12]}]
|
||||
set_property -dict {LOC K16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[13]}]
|
||||
set_property -dict {LOC D15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[14]}]
|
||||
set_property -dict {LOC E15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[15]}]
|
||||
set_property -dict {LOC F15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[16]}]
|
||||
set_property -dict {LOC J15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[0]}]
|
||||
set_property -dict {LOC H14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[1]}]
|
||||
set_property -dict {LOC D13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[0]}]
|
||||
set_property -dict {LOC J13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[1]}]
|
||||
set_property -dict {LOC L14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t[0]}]
|
||||
set_property -dict {LOC L13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c[0]}]
|
||||
#set_property -dict {LOC G14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t[1]}]
|
||||
#set_property -dict {LOC G13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c[1]}]
|
||||
set_property -dict {LOC K13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[0]}]
|
||||
#set_property -dict {LOC L15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[1]}]
|
||||
set_property -dict {LOC B16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[0]}]
|
||||
#set_property -dict {LOC D16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[1]}]
|
||||
#set_property -dict {LOC M14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[2]}]
|
||||
#set_property -dict {LOC M13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[3]}]
|
||||
set_property -dict {LOC H13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_act_n}]
|
||||
set_property -dict {LOC C16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[0]}]
|
||||
#set_property -dict {LOC E16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[1]}]
|
||||
set_property -dict {LOC J14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_par}]
|
||||
set_property -dict {LOC D21 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c3_reset_n}]
|
||||
|
||||
set_property -dict {LOC P24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[0]}]
|
||||
set_property -dict {LOC N24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[1]}]
|
||||
set_property -dict {LOC T24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[2]}]
|
||||
set_property -dict {LOC R23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[3]}]
|
||||
set_property -dict {LOC N23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[4]}]
|
||||
set_property -dict {LOC P21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[5]}]
|
||||
set_property -dict {LOC P23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[6]}]
|
||||
set_property -dict {LOC R21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[7]}]
|
||||
set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[8]}]
|
||||
set_property -dict {LOC J23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[9]}]
|
||||
set_property -dict {LOC H24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[10]}]
|
||||
set_property -dict {LOC G24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[11]}]
|
||||
set_property -dict {LOC L24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[12]}]
|
||||
set_property -dict {LOC L23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[13]}]
|
||||
set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[14]}]
|
||||
set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[15]}]
|
||||
set_property -dict {LOC G20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[16]}]
|
||||
set_property -dict {LOC H17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[17]}]
|
||||
set_property -dict {LOC F19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[18]}]
|
||||
set_property -dict {LOC G17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[19]}]
|
||||
set_property -dict {LOC J20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[20]}]
|
||||
set_property -dict {LOC L19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[21]}]
|
||||
set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[22]}]
|
||||
set_property -dict {LOC J19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[23]}]
|
||||
set_property -dict {LOC M19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[24]}]
|
||||
set_property -dict {LOC M20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[25]}]
|
||||
set_property -dict {LOC R18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[26]}]
|
||||
set_property -dict {LOC R17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[27]}]
|
||||
set_property -dict {LOC R20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[28]}]
|
||||
set_property -dict {LOC T20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[29]}]
|
||||
set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[30]}]
|
||||
set_property -dict {LOC N19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[31]}]
|
||||
set_property -dict {LOC A23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[32]}]
|
||||
set_property -dict {LOC A22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[33]}]
|
||||
set_property -dict {LOC B24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[34]}]
|
||||
set_property -dict {LOC B25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[35]}]
|
||||
set_property -dict {LOC B22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[36]}]
|
||||
set_property -dict {LOC C22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[37]}]
|
||||
set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[38]}]
|
||||
set_property -dict {LOC C23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[39]}]
|
||||
set_property -dict {LOC C19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[40]}]
|
||||
set_property -dict {LOC C18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[41]}]
|
||||
set_property -dict {LOC C21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[42]}]
|
||||
set_property -dict {LOC B21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[43]}]
|
||||
set_property -dict {LOC A18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[44]}]
|
||||
set_property -dict {LOC A17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[45]}]
|
||||
set_property -dict {LOC A20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[46]}]
|
||||
set_property -dict {LOC B20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[47]}]
|
||||
set_property -dict {LOC E17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[48]}]
|
||||
set_property -dict {LOC F20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[49]}]
|
||||
set_property -dict {LOC E18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[50]}]
|
||||
set_property -dict {LOC E20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[51]}]
|
||||
set_property -dict {LOC D19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[52]}]
|
||||
set_property -dict {LOC D20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[53]}]
|
||||
set_property -dict {LOC H18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[54]}]
|
||||
set_property -dict {LOC J18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[55]}]
|
||||
set_property -dict {LOC F22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[56]}]
|
||||
set_property -dict {LOC E22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[57]}]
|
||||
set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[58]}]
|
||||
set_property -dict {LOC G21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[59]}]
|
||||
set_property -dict {LOC F24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[60]}]
|
||||
set_property -dict {LOC E25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[61]}]
|
||||
set_property -dict {LOC F25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[62]}]
|
||||
set_property -dict {LOC G25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[63]}]
|
||||
set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[64]}]
|
||||
set_property -dict {LOC N16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[65]}]
|
||||
set_property -dict {LOC N13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[66]}]
|
||||
set_property -dict {LOC N14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[67]}]
|
||||
set_property -dict {LOC T15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[68]}]
|
||||
set_property -dict {LOC R15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[69]}]
|
||||
set_property -dict {LOC P13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[70]}]
|
||||
set_property -dict {LOC P14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[71]}]
|
||||
set_property -dict {LOC T22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[0]}]
|
||||
set_property -dict {LOC R22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[0]}]
|
||||
set_property -dict {LOC N22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[1]}]
|
||||
set_property -dict {LOC N21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[1]}]
|
||||
set_property -dict {LOC J21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[2]}]
|
||||
set_property -dict {LOC H21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[2]}]
|
||||
set_property -dict {LOC M22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[3]}]
|
||||
set_property -dict {LOC L22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[3]}]
|
||||
set_property -dict {LOC L20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[4]}]
|
||||
set_property -dict {LOC K20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[4]}]
|
||||
set_property -dict {LOC K18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[5]}]
|
||||
set_property -dict {LOC K17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[5]}]
|
||||
set_property -dict {LOC P19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[6]}]
|
||||
set_property -dict {LOC P18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[6]}]
|
||||
set_property -dict {LOC N17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[7]}]
|
||||
set_property -dict {LOC M17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[7]}]
|
||||
set_property -dict {LOC A25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[8]}]
|
||||
set_property -dict {LOC A24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[8]}]
|
||||
set_property -dict {LOC D24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[9]}]
|
||||
set_property -dict {LOC D23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[9]}]
|
||||
set_property -dict {LOC C17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[10]}]
|
||||
set_property -dict {LOC B17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[10]}]
|
||||
set_property -dict {LOC B19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[11]}]
|
||||
set_property -dict {LOC A19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[11]}]
|
||||
set_property -dict {LOC F18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[12]}]
|
||||
set_property -dict {LOC F17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[12]}]
|
||||
set_property -dict {LOC H19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[13]}]
|
||||
set_property -dict {LOC G19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[13]}]
|
||||
set_property -dict {LOC F23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[14]}]
|
||||
set_property -dict {LOC E23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[14]}]
|
||||
set_property -dict {LOC H23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[15]}]
|
||||
set_property -dict {LOC H22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[15]}]
|
||||
set_property -dict {LOC R16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[16]}]
|
||||
set_property -dict {LOC P15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[16]}]
|
||||
set_property -dict {LOC T13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[17]}]
|
||||
set_property -dict {LOC R13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[17]}]
|
||||
|
||||
@ -145,6 +145,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
|
||||
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
|
||||
IP_TCL_FILES += ip/eth_xcvr_gty.tcl
|
||||
IP_TCL_FILES += ip/cms.tcl
|
||||
IP_TCL_FILES += ip/ddr4_0.tcl
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
@ -148,6 +148,12 @@ dict set params MAX_TX_SIZE "9214"
|
||||
dict set params MAX_RX_SIZE "9214"
|
||||
dict set params TX_RAM_SIZE "32768"
|
||||
dict set params RX_RAM_SIZE "131072"
|
||||
|
||||
# RAM configuration
|
||||
dict set params DDR_CH "4"
|
||||
dict set params DDR_ENABLE "1"
|
||||
dict set params AXI_DDR_ID_WIDTH "8"
|
||||
dict set params AXI_DDR_MAX_BURST_LEN "256"
|
||||
|
||||
# Application block configuration
|
||||
dict set params APP_ID "32'h00000000"
|
||||
@ -200,6 +206,19 @@ dict set params STAT_PCIE_ENABLE "1"
|
||||
dict set params STAT_INC_WIDTH "24"
|
||||
dict set params STAT_ID_WIDTH "12"
|
||||
|
||||
# DDR4 MIG settings
|
||||
if {[dict get $params DDR_ENABLE]} {
|
||||
set ddr4 [get_ips ddr4_0]
|
||||
|
||||
# set AXI ID width
|
||||
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
|
||||
|
||||
# extract AXI configuration
|
||||
dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4]
|
||||
dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4]
|
||||
dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1]
|
||||
}
|
||||
|
||||
# PCIe IP core settings
|
||||
set pcie [get_ips pcie4_uscale_plus_0]
|
||||
|
||||
|
||||
@ -145,6 +145,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
|
||||
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
|
||||
IP_TCL_FILES += ip/eth_xcvr_gty.tcl
|
||||
IP_TCL_FILES += ip/cms.tcl
|
||||
IP_TCL_FILES += ip/ddr4_0.tcl
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
@ -148,6 +148,12 @@ dict set params MAX_TX_SIZE "9214"
|
||||
dict set params MAX_RX_SIZE "9214"
|
||||
dict set params TX_RAM_SIZE "32768"
|
||||
dict set params RX_RAM_SIZE "32768"
|
||||
|
||||
# RAM configuration
|
||||
dict set params DDR_CH "4"
|
||||
dict set params DDR_ENABLE "1"
|
||||
dict set params AXI_DDR_ID_WIDTH "8"
|
||||
dict set params AXI_DDR_MAX_BURST_LEN "256"
|
||||
|
||||
# Application block configuration
|
||||
dict set params APP_ID "32'h00000000"
|
||||
@ -200,6 +206,19 @@ dict set params STAT_PCIE_ENABLE "1"
|
||||
dict set params STAT_INC_WIDTH "24"
|
||||
dict set params STAT_ID_WIDTH "12"
|
||||
|
||||
# DDR4 MIG settings
|
||||
if {[dict get $params DDR_ENABLE]} {
|
||||
set ddr4 [get_ips ddr4_0]
|
||||
|
||||
# set AXI ID width
|
||||
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
|
||||
|
||||
# extract AXI configuration
|
||||
dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4]
|
||||
dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4]
|
||||
dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1]
|
||||
}
|
||||
|
||||
# PCIe IP core settings
|
||||
set pcie [get_ips pcie4_uscale_plus_0]
|
||||
|
||||
|
||||
17
fpga/mqnic/AU250/fpga_25g/ip/ddr4_0.tcl
Normal file
17
fpga/mqnic/AU250/fpga_25g/ip/ddr4_0.tcl
Normal file
@ -0,0 +1,17 @@
|
||||
|
||||
create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0
|
||||
|
||||
set_property -dict [list \
|
||||
CONFIG.C0.DDR4_AxiSelection {true} \
|
||||
CONFIG.C0.DDR4_AxiDataWidth {512} \
|
||||
CONFIG.C0.DDR4_AxiIDWidth {8} \
|
||||
CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \
|
||||
CONFIG.C0.DDR4_TimePeriod {833} \
|
||||
CONFIG.C0.DDR4_InputClockPeriod {3332} \
|
||||
CONFIG.C0.DDR4_MemoryType {RDIMMs} \
|
||||
CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PZ-2G3} \
|
||||
CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \
|
||||
CONFIG.C0.DDR4_CasLatency {17} \
|
||||
CONFIG.C0.DDR4_CasWriteLatency {12} \
|
||||
CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV}
|
||||
] [get_ips ddr4_0]
|
||||
@ -112,6 +112,15 @@ module fpga #
|
||||
parameter TX_RAM_SIZE = 32768,
|
||||
parameter RX_RAM_SIZE = 32768,
|
||||
|
||||
// RAM configuration
|
||||
parameter DDR_CH = 4,
|
||||
parameter DDR_ENABLE = 1,
|
||||
parameter AXI_DDR_DATA_WIDTH = 512,
|
||||
parameter AXI_DDR_ADDR_WIDTH = 34,
|
||||
parameter AXI_DDR_ID_WIDTH = 8,
|
||||
parameter AXI_DDR_MAX_BURST_LEN = 256,
|
||||
parameter AXI_DDR_NARROW_BURST = 0,
|
||||
|
||||
// Application block configuration
|
||||
parameter APP_ID = 32'h00000000,
|
||||
parameter APP_ENABLE = 0,
|
||||
@ -177,6 +186,18 @@ module fpga #
|
||||
parameter STAT_ID_WIDTH = 12
|
||||
)
|
||||
(
|
||||
/*
|
||||
* Clock and reset
|
||||
*/
|
||||
input wire clk_300mhz_0_p,
|
||||
input wire clk_300mhz_0_n,
|
||||
input wire clk_300mhz_1_p,
|
||||
input wire clk_300mhz_1_n,
|
||||
input wire clk_300mhz_2_p,
|
||||
input wire clk_300mhz_2_n,
|
||||
input wire clk_300mhz_3_p,
|
||||
input wire clk_300mhz_3_n,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
*/
|
||||
@ -260,7 +281,70 @@ module fpga #
|
||||
input wire qsfp1_intl,
|
||||
output wire qsfp1_lpmode,
|
||||
output wire qsfp1_refclk_reset,
|
||||
output wire [1:0] qsfp1_fs
|
||||
output wire [1:0] qsfp1_fs,
|
||||
|
||||
/*
|
||||
* DDR4
|
||||
*/
|
||||
output wire [16:0] ddr4_c0_adr,
|
||||
output wire [1:0] ddr4_c0_ba,
|
||||
output wire [1:0] ddr4_c0_bg,
|
||||
output wire [0:0] ddr4_c0_ck_t,
|
||||
output wire [0:0] ddr4_c0_ck_c,
|
||||
output wire [0:0] ddr4_c0_cke,
|
||||
output wire [0:0] ddr4_c0_cs_n,
|
||||
output wire ddr4_c0_act_n,
|
||||
output wire [0:0] ddr4_c0_odt,
|
||||
output wire ddr4_c0_par,
|
||||
output wire ddr4_c0_reset_n,
|
||||
inout wire [71:0] ddr4_c0_dq,
|
||||
inout wire [17:0] ddr4_c0_dqs_t,
|
||||
inout wire [17:0] ddr4_c0_dqs_c,
|
||||
|
||||
output wire [16:0] ddr4_c1_adr,
|
||||
output wire [1:0] ddr4_c1_ba,
|
||||
output wire [1:0] ddr4_c1_bg,
|
||||
output wire [0:0] ddr4_c1_ck_t,
|
||||
output wire [0:0] ddr4_c1_ck_c,
|
||||
output wire [0:0] ddr4_c1_cke,
|
||||
output wire [0:0] ddr4_c1_cs_n,
|
||||
output wire ddr4_c1_act_n,
|
||||
output wire [0:0] ddr4_c1_odt,
|
||||
output wire ddr4_c1_par,
|
||||
output wire ddr4_c1_reset_n,
|
||||
inout wire [71:0] ddr4_c1_dq,
|
||||
inout wire [17:0] ddr4_c1_dqs_t,
|
||||
inout wire [17:0] ddr4_c1_dqs_c,
|
||||
|
||||
output wire [16:0] ddr4_c2_adr,
|
||||
output wire [1:0] ddr4_c2_ba,
|
||||
output wire [1:0] ddr4_c2_bg,
|
||||
output wire [0:0] ddr4_c2_ck_t,
|
||||
output wire [0:0] ddr4_c2_ck_c,
|
||||
output wire [0:0] ddr4_c2_cke,
|
||||
output wire [0:0] ddr4_c2_cs_n,
|
||||
output wire ddr4_c2_act_n,
|
||||
output wire [0:0] ddr4_c2_odt,
|
||||
output wire ddr4_c2_par,
|
||||
output wire ddr4_c2_reset_n,
|
||||
inout wire [71:0] ddr4_c2_dq,
|
||||
inout wire [17:0] ddr4_c2_dqs_t,
|
||||
inout wire [17:0] ddr4_c2_dqs_c,
|
||||
|
||||
output wire [16:0] ddr4_c3_adr,
|
||||
output wire [1:0] ddr4_c3_ba,
|
||||
output wire [1:0] ddr4_c3_bg,
|
||||
output wire [0:0] ddr4_c3_ck_t,
|
||||
output wire [0:0] ddr4_c3_ck_c,
|
||||
output wire [0:0] ddr4_c3_cke,
|
||||
output wire [0:0] ddr4_c3_cs_n,
|
||||
output wire ddr4_c3_act_n,
|
||||
output wire [0:0] ddr4_c3_odt,
|
||||
output wire ddr4_c3_par,
|
||||
output wire ddr4_c3_reset_n,
|
||||
inout wire [71:0] ddr4_c3_dq,
|
||||
inout wire [17:0] ddr4_c3_dqs_t,
|
||||
inout wire [17:0] ddr4_c3_dqs_c
|
||||
);
|
||||
|
||||
// PTP configuration
|
||||
@ -274,6 +358,9 @@ parameter IF_PTP_PERIOD_FNS = 16'h6666;
|
||||
// Interface configuration
|
||||
parameter TX_TAG_WIDTH = 16;
|
||||
|
||||
// RAM configuration
|
||||
parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8);
|
||||
|
||||
// Ethernet interface configuration
|
||||
parameter XGMII_DATA_WIDTH = 64;
|
||||
parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8;
|
||||
@ -1487,6 +1574,519 @@ assign ptp_clk = qsfp0_mgt_refclk_1_bufg;
|
||||
assign ptp_rst = qsfp0_rst;
|
||||
assign ptp_sample_clk = clk_125mhz_int;
|
||||
|
||||
// DDR4
|
||||
wire [DDR_CH-1:0] ddr_clk;
|
||||
wire [DDR_CH-1:0] ddr_rst;
|
||||
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid;
|
||||
wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr;
|
||||
wire [DDR_CH*8-1:0] m_axi_ddr_awlen;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_awsize;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_awburst;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_awlock;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_awcache;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_awprot;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_awqos;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_awvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_awready;
|
||||
wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata;
|
||||
wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_wlast;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_wvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_wready;
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_bresp;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_bvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_bready;
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid;
|
||||
wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr;
|
||||
wire [DDR_CH*8-1:0] m_axi_ddr_arlen;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_arsize;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_arburst;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_arlock;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_arcache;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_arprot;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_arqos;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_arvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_arready;
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid;
|
||||
wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_rresp;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_rlast;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_rvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_rready;
|
||||
|
||||
wire [DDR_CH-1:0] ddr_status;
|
||||
|
||||
generate
|
||||
|
||||
if (DDR_ENABLE && DDR_CH > 0) begin
|
||||
|
||||
ddr4_0 ddr4_c0_inst (
|
||||
.c0_sys_clk_p(clk_300mhz_0_p),
|
||||
.c0_sys_clk_n(clk_300mhz_0_n),
|
||||
.sys_rst(pcie_user_reset),
|
||||
|
||||
.c0_init_calib_complete(ddr_status[0 +: 1]),
|
||||
.c0_ddr4_interrupt(),
|
||||
.dbg_clk(),
|
||||
.dbg_bus(),
|
||||
|
||||
.c0_ddr4_adr(ddr4_c0_adr),
|
||||
.c0_ddr4_ba(ddr4_c0_ba),
|
||||
.c0_ddr4_cke(ddr4_c0_cke),
|
||||
.c0_ddr4_cs_n(ddr4_c0_cs_n),
|
||||
.c0_ddr4_dq(ddr4_c0_dq),
|
||||
.c0_ddr4_dqs_t(ddr4_c0_dqs_t),
|
||||
.c0_ddr4_dqs_c(ddr4_c0_dqs_c),
|
||||
.c0_ddr4_odt(ddr4_c0_odt),
|
||||
.c0_ddr4_parity(ddr4_c0_par),
|
||||
.c0_ddr4_bg(ddr4_c0_bg),
|
||||
.c0_ddr4_reset_n(ddr4_c0_reset_n),
|
||||
.c0_ddr4_act_n(ddr4_c0_act_n),
|
||||
.c0_ddr4_ck_t(ddr4_c0_ck_t),
|
||||
.c0_ddr4_ck_c(ddr4_c0_ck_c),
|
||||
|
||||
.c0_ddr4_ui_clk(ddr_clk[0 +: 1]),
|
||||
.c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]),
|
||||
|
||||
.c0_ddr4_aresetn(!ddr_rst[0 +: 1]),
|
||||
|
||||
.c0_ddr4_s_axi_ctrl_awvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_awready(),
|
||||
.c0_ddr4_s_axi_ctrl_awaddr(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_wvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_wready(),
|
||||
.c0_ddr4_s_axi_ctrl_wdata(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_bvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_bready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_bresp(),
|
||||
.c0_ddr4_s_axi_ctrl_arvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_arready(),
|
||||
.c0_ddr4_s_axi_ctrl_araddr(31'd0),
|
||||
.c0_ddr4_s_axi_ctrl_rvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_rready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_rdata(),
|
||||
.c0_ddr4_s_axi_ctrl_rresp(),
|
||||
|
||||
.c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]),
|
||||
.c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]),
|
||||
.c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]),
|
||||
.c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]),
|
||||
.c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]),
|
||||
.c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]),
|
||||
.c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]),
|
||||
.c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH])
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign ddr4_c0_adr = {17{1'bz}};
|
||||
assign ddr4_c0_ba = {2{1'bz}};
|
||||
assign ddr4_c0_bg = {2{1'bz}};
|
||||
assign ddr4_c0_cke = 1'bz;
|
||||
assign ddr4_c0_cs_n = 1'bz;
|
||||
assign ddr4_c0_act_n = 1'bz;
|
||||
assign ddr4_c0_odt = 1'bz;
|
||||
assign ddr4_c0_par = 1'bz;
|
||||
assign ddr4_c0_reset_n = 1'b0;
|
||||
assign ddr4_c0_dq = {72{1'bz}};
|
||||
assign ddr4_c0_dqs_t = {18{1'bz}};
|
||||
assign ddr4_c0_dqs_c = {18{1'bz}};
|
||||
|
||||
OBUFTDS ddr4_c0_ck_obuftds_inst (
|
||||
.I(1'b0),
|
||||
.T(1'b1),
|
||||
.O(ddr4_c0_ck_t),
|
||||
.OB(ddr4_c0_ck_c)
|
||||
);
|
||||
|
||||
assign ddr_clk = 0;
|
||||
assign ddr_rst = 0;
|
||||
|
||||
assign m_axi_ddr_awready = 0;
|
||||
assign m_axi_ddr_wready = 0;
|
||||
assign m_axi_ddr_bid = 0;
|
||||
assign m_axi_ddr_bresp = 0;
|
||||
assign m_axi_ddr_bvalid = 0;
|
||||
assign m_axi_ddr_arready = 0;
|
||||
assign m_axi_ddr_rid = 0;
|
||||
assign m_axi_ddr_rdata = 0;
|
||||
assign m_axi_ddr_rresp = 0;
|
||||
assign m_axi_ddr_rlast = 0;
|
||||
assign m_axi_ddr_rvalid = 0;
|
||||
|
||||
assign ddr_status = 0;
|
||||
|
||||
end
|
||||
|
||||
if (DDR_ENABLE && DDR_CH > 1) begin
|
||||
|
||||
ddr4_0 ddr4_c1_inst (
|
||||
.c0_sys_clk_p(clk_300mhz_1_p),
|
||||
.c0_sys_clk_n(clk_300mhz_1_n),
|
||||
.sys_rst(pcie_user_reset),
|
||||
|
||||
.c0_init_calib_complete(ddr_status[1 +: 1]),
|
||||
.c0_ddr4_interrupt(),
|
||||
.dbg_clk(),
|
||||
.dbg_bus(),
|
||||
|
||||
.c0_ddr4_adr(ddr4_c1_adr),
|
||||
.c0_ddr4_ba(ddr4_c1_ba),
|
||||
.c0_ddr4_cke(ddr4_c1_cke),
|
||||
.c0_ddr4_cs_n(ddr4_c1_cs_n),
|
||||
.c0_ddr4_dq(ddr4_c1_dq),
|
||||
.c0_ddr4_dqs_t(ddr4_c1_dqs_t),
|
||||
.c0_ddr4_dqs_c(ddr4_c1_dqs_c),
|
||||
.c0_ddr4_odt(ddr4_c1_odt),
|
||||
.c0_ddr4_parity(ddr4_c1_par),
|
||||
.c0_ddr4_bg(ddr4_c1_bg),
|
||||
.c0_ddr4_reset_n(ddr4_c1_reset_n),
|
||||
.c0_ddr4_act_n(ddr4_c1_act_n),
|
||||
.c0_ddr4_ck_t(ddr4_c1_ck_t),
|
||||
.c0_ddr4_ck_c(ddr4_c1_ck_c),
|
||||
|
||||
.c0_ddr4_ui_clk(ddr_clk[1 +: 1]),
|
||||
.c0_ddr4_ui_clk_sync_rst(ddr_rst[1 +: 1]),
|
||||
|
||||
.c0_ddr4_aresetn(!ddr_rst[1 +: 1]),
|
||||
|
||||
.c0_ddr4_s_axi_ctrl_awvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_awready(),
|
||||
.c0_ddr4_s_axi_ctrl_awaddr(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_wvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_wready(),
|
||||
.c0_ddr4_s_axi_ctrl_wdata(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_bvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_bready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_bresp(),
|
||||
.c0_ddr4_s_axi_ctrl_arvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_arready(),
|
||||
.c0_ddr4_s_axi_ctrl_araddr(31'd0),
|
||||
.c0_ddr4_s_axi_ctrl_rvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_rready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_rdata(),
|
||||
.c0_ddr4_s_axi_ctrl_rresp(),
|
||||
|
||||
.c0_ddr4_s_axi_awid(m_axi_ddr_awid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[1*8 +: 8]),
|
||||
.c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[1*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[1*2 +: 2]),
|
||||
.c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[1 +: 1]),
|
||||
.c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[1*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[1*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[1*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_awready(m_axi_ddr_awready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]),
|
||||
.c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[1*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]),
|
||||
.c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[1 +: 1]),
|
||||
.c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_wready(m_axi_ddr_wready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_bready(m_axi_ddr_bready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_bid(m_axi_ddr_bid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[1*2 +: 2]),
|
||||
.c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_arid(m_axi_ddr_arid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[1*8 +: 8]),
|
||||
.c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[1*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[1*2 +: 2]),
|
||||
.c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[1 +: 1]),
|
||||
.c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[1*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[1*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[1*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_arready(m_axi_ddr_arready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_rready(m_axi_ddr_rready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[1 +: 1]),
|
||||
.c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[1*2 +: 2]),
|
||||
.c0_ddr4_s_axi_rid(m_axi_ddr_rid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH])
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign ddr4_c1_adr = {17{1'bz}};
|
||||
assign ddr4_c1_ba = {2{1'bz}};
|
||||
assign ddr4_c1_bg = {2{1'bz}};
|
||||
assign ddr4_c1_cke = 1'bz;
|
||||
assign ddr4_c1_cs_n = 1'bz;
|
||||
assign ddr4_c1_act_n = 1'bz;
|
||||
assign ddr4_c1_odt = 1'bz;
|
||||
assign ddr4_c1_par = 1'bz;
|
||||
assign ddr4_c1_reset_n = 1'b0;
|
||||
assign ddr4_c1_dq = {72{1'bz}};
|
||||
assign ddr4_c1_dqs_t = {18{1'bz}};
|
||||
assign ddr4_c1_dqs_c = {18{1'bz}};
|
||||
|
||||
OBUFTDS ddr4_c1_ck_obuftds_inst (
|
||||
.I(1'b0),
|
||||
.T(1'b1),
|
||||
.O(ddr4_c1_ck_t),
|
||||
.OB(ddr4_c1_ck_c)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
if (DDR_ENABLE && DDR_CH > 2) begin
|
||||
|
||||
ddr4_0 ddr4_c2_inst (
|
||||
.c0_sys_clk_p(clk_300mhz_2_p),
|
||||
.c0_sys_clk_n(clk_300mhz_2_n),
|
||||
.sys_rst(pcie_user_reset),
|
||||
|
||||
.c0_init_calib_complete(ddr_status[2 +: 1]),
|
||||
.c0_ddr4_interrupt(),
|
||||
.dbg_clk(),
|
||||
.dbg_bus(),
|
||||
|
||||
.c0_ddr4_adr(ddr4_c2_adr),
|
||||
.c0_ddr4_ba(ddr4_c2_ba),
|
||||
.c0_ddr4_cke(ddr4_c2_cke),
|
||||
.c0_ddr4_cs_n(ddr4_c2_cs_n),
|
||||
.c0_ddr4_dq(ddr4_c2_dq),
|
||||
.c0_ddr4_dqs_t(ddr4_c2_dqs_t),
|
||||
.c0_ddr4_dqs_c(ddr4_c2_dqs_c),
|
||||
.c0_ddr4_odt(ddr4_c2_odt),
|
||||
.c0_ddr4_parity(ddr4_c2_par),
|
||||
.c0_ddr4_bg(ddr4_c2_bg),
|
||||
.c0_ddr4_reset_n(ddr4_c2_reset_n),
|
||||
.c0_ddr4_act_n(ddr4_c2_act_n),
|
||||
.c0_ddr4_ck_t(ddr4_c2_ck_t),
|
||||
.c0_ddr4_ck_c(ddr4_c2_ck_c),
|
||||
|
||||
.c0_ddr4_ui_clk(ddr_clk[2 +: 1]),
|
||||
.c0_ddr4_ui_clk_sync_rst(ddr_rst[2 +: 1]),
|
||||
|
||||
.c0_ddr4_aresetn(!ddr_rst[2 +: 1]),
|
||||
|
||||
.c0_ddr4_s_axi_ctrl_awvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_awready(),
|
||||
.c0_ddr4_s_axi_ctrl_awaddr(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_wvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_wready(),
|
||||
.c0_ddr4_s_axi_ctrl_wdata(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_bvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_bready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_bresp(),
|
||||
.c0_ddr4_s_axi_ctrl_arvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_arready(),
|
||||
.c0_ddr4_s_axi_ctrl_araddr(31'd0),
|
||||
.c0_ddr4_s_axi_ctrl_rvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_rready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_rdata(),
|
||||
.c0_ddr4_s_axi_ctrl_rresp(),
|
||||
|
||||
.c0_ddr4_s_axi_awid(m_axi_ddr_awid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[2*8 +: 8]),
|
||||
.c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[2*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[2*2 +: 2]),
|
||||
.c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[2 +: 1]),
|
||||
.c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[2*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[2*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[2*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[2 +: 1]),
|
||||
.c0_ddr4_s_axi_awready(m_axi_ddr_awready[2 +: 1]),
|
||||
.c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]),
|
||||
.c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[2*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]),
|
||||
.c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[2 +: 1]),
|
||||
.c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[2 +: 1]),
|
||||
.c0_ddr4_s_axi_wready(m_axi_ddr_wready[2 +: 1]),
|
||||
.c0_ddr4_s_axi_bready(m_axi_ddr_bready[2 +: 1]),
|
||||
.c0_ddr4_s_axi_bid(m_axi_ddr_bid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[2*2 +: 2]),
|
||||
.c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[2 +: 1]),
|
||||
.c0_ddr4_s_axi_arid(m_axi_ddr_arid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[2*8 +: 8]),
|
||||
.c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[2*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[2*2 +: 2]),
|
||||
.c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[2 +: 1]),
|
||||
.c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[2*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[2*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[2*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[2 +: 1]),
|
||||
.c0_ddr4_s_axi_arready(m_axi_ddr_arready[2 +: 1]),
|
||||
.c0_ddr4_s_axi_rready(m_axi_ddr_rready[2 +: 1]),
|
||||
.c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[2 +: 1]),
|
||||
.c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[2 +: 1]),
|
||||
.c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[2*2 +: 2]),
|
||||
.c0_ddr4_s_axi_rid(m_axi_ddr_rid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH])
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign ddr4_c2_adr = {17{1'bz}};
|
||||
assign ddr4_c2_ba = {2{1'bz}};
|
||||
assign ddr4_c2_bg = {2{1'bz}};
|
||||
assign ddr4_c2_cke = 1'bz;
|
||||
assign ddr4_c2_cs_n = 1'bz;
|
||||
assign ddr4_c2_act_n = 1'bz;
|
||||
assign ddr4_c2_odt = 1'bz;
|
||||
assign ddr4_c2_par = 1'bz;
|
||||
assign ddr4_c2_reset_n = 1'b0;
|
||||
assign ddr4_c2_dq = {72{1'bz}};
|
||||
assign ddr4_c2_dqs_t = {18{1'bz}};
|
||||
assign ddr4_c2_dqs_c = {18{1'bz}};
|
||||
|
||||
OBUFTDS ddr4_c2_ck_obuftds_inst (
|
||||
.I(1'b0),
|
||||
.T(1'b1),
|
||||
.O(ddr4_c2_ck_t),
|
||||
.OB(ddr4_c2_ck_c)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
if (DDR_ENABLE && DDR_CH > 3) begin
|
||||
|
||||
ddr4_0 ddr4_c3_inst (
|
||||
.c0_sys_clk_p(clk_300mhz_3_p),
|
||||
.c0_sys_clk_n(clk_300mhz_3_n),
|
||||
.sys_rst(pcie_user_reset),
|
||||
|
||||
.c0_init_calib_complete(ddr_status[3 +: 1]),
|
||||
.c0_ddr4_interrupt(),
|
||||
.dbg_clk(),
|
||||
.dbg_bus(),
|
||||
|
||||
.c0_ddr4_adr(ddr4_c3_adr),
|
||||
.c0_ddr4_ba(ddr4_c3_ba),
|
||||
.c0_ddr4_cke(ddr4_c3_cke),
|
||||
.c0_ddr4_cs_n(ddr4_c3_cs_n),
|
||||
.c0_ddr4_dq(ddr4_c3_dq),
|
||||
.c0_ddr4_dqs_t(ddr4_c3_dqs_t),
|
||||
.c0_ddr4_dqs_c(ddr4_c3_dqs_c),
|
||||
.c0_ddr4_odt(ddr4_c3_odt),
|
||||
.c0_ddr4_parity(ddr4_c3_par),
|
||||
.c0_ddr4_bg(ddr4_c3_bg),
|
||||
.c0_ddr4_reset_n(ddr4_c3_reset_n),
|
||||
.c0_ddr4_act_n(ddr4_c3_act_n),
|
||||
.c0_ddr4_ck_t(ddr4_c3_ck_t),
|
||||
.c0_ddr4_ck_c(ddr4_c3_ck_c),
|
||||
|
||||
.c0_ddr4_ui_clk(ddr_clk[3 +: 1]),
|
||||
.c0_ddr4_ui_clk_sync_rst(ddr_rst[3 +: 1]),
|
||||
|
||||
.c0_ddr4_aresetn(!ddr_rst[3 +: 1]),
|
||||
|
||||
.c0_ddr4_s_axi_ctrl_awvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_awready(),
|
||||
.c0_ddr4_s_axi_ctrl_awaddr(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_wvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_wready(),
|
||||
.c0_ddr4_s_axi_ctrl_wdata(32'd0),
|
||||
.c0_ddr4_s_axi_ctrl_bvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_bready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_bresp(),
|
||||
.c0_ddr4_s_axi_ctrl_arvalid(1'b0),
|
||||
.c0_ddr4_s_axi_ctrl_arready(),
|
||||
.c0_ddr4_s_axi_ctrl_araddr(31'd0),
|
||||
.c0_ddr4_s_axi_ctrl_rvalid(),
|
||||
.c0_ddr4_s_axi_ctrl_rready(1'b1),
|
||||
.c0_ddr4_s_axi_ctrl_rdata(),
|
||||
.c0_ddr4_s_axi_ctrl_rresp(),
|
||||
|
||||
.c0_ddr4_s_axi_awid(m_axi_ddr_awid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[3*8 +: 8]),
|
||||
.c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[3*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[3*2 +: 2]),
|
||||
.c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[3 +: 1]),
|
||||
.c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[3*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[3*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[3*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[3 +: 1]),
|
||||
.c0_ddr4_s_axi_awready(m_axi_ddr_awready[3 +: 1]),
|
||||
.c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]),
|
||||
.c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[3*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]),
|
||||
.c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[3 +: 1]),
|
||||
.c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[3 +: 1]),
|
||||
.c0_ddr4_s_axi_wready(m_axi_ddr_wready[3 +: 1]),
|
||||
.c0_ddr4_s_axi_bready(m_axi_ddr_bready[3 +: 1]),
|
||||
.c0_ddr4_s_axi_bid(m_axi_ddr_bid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[3*2 +: 2]),
|
||||
.c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[3 +: 1]),
|
||||
.c0_ddr4_s_axi_arid(m_axi_ddr_arid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[3*8 +: 8]),
|
||||
.c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[3*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[3*2 +: 2]),
|
||||
.c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[3 +: 1]),
|
||||
.c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[3*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[3*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[3*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[3 +: 1]),
|
||||
.c0_ddr4_s_axi_arready(m_axi_ddr_arready[3 +: 1]),
|
||||
.c0_ddr4_s_axi_rready(m_axi_ddr_rready[3 +: 1]),
|
||||
.c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[3 +: 1]),
|
||||
.c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[3 +: 1]),
|
||||
.c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[3*2 +: 2]),
|
||||
.c0_ddr4_s_axi_rid(m_axi_ddr_rid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH])
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign ddr4_c3_adr = {17{1'bz}};
|
||||
assign ddr4_c3_ba = {2{1'bz}};
|
||||
assign ddr4_c3_bg = {2{1'bz}};
|
||||
assign ddr4_c3_cke = 1'bz;
|
||||
assign ddr4_c3_cs_n = 1'bz;
|
||||
assign ddr4_c3_act_n = 1'bz;
|
||||
assign ddr4_c3_odt = 1'bz;
|
||||
assign ddr4_c3_par = 1'bz;
|
||||
assign ddr4_c3_reset_n = 1'b0;
|
||||
assign ddr4_c3_dq = {72{1'bz}};
|
||||
assign ddr4_c3_dqs_t = {18{1'bz}};
|
||||
assign ddr4_c3_dqs_c = {18{1'bz}};
|
||||
|
||||
OBUFTDS ddr4_c3_ck_obuftds_inst (
|
||||
.I(1'b0),
|
||||
.T(1'b1),
|
||||
.O(ddr4_c3_ck_t),
|
||||
.OB(ddr4_c3_ck_c)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
fpga_core #(
|
||||
// FW and board IDs
|
||||
.FPGA_ID(FPGA_ID),
|
||||
@ -1563,6 +2163,16 @@ fpga_core #(
|
||||
.TX_RAM_SIZE(TX_RAM_SIZE),
|
||||
.RX_RAM_SIZE(RX_RAM_SIZE),
|
||||
|
||||
// RAM configuration
|
||||
.DDR_CH(DDR_CH),
|
||||
.DDR_ENABLE(DDR_ENABLE),
|
||||
.AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH),
|
||||
.AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH),
|
||||
.AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH),
|
||||
.AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH),
|
||||
.AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN),
|
||||
.AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST),
|
||||
|
||||
// Application block configuration
|
||||
.APP_ID(APP_ID),
|
||||
.APP_ENABLE(APP_ENABLE),
|
||||
@ -1868,6 +2478,52 @@ core_inst (
|
||||
.qsfp1_intl(qsfp1_intl_int),
|
||||
.qsfp1_lpmode(qsfp1_lpmode),
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
.ddr_clk(ddr_clk),
|
||||
.ddr_rst(ddr_rst),
|
||||
|
||||
.m_axi_ddr_awid(m_axi_ddr_awid),
|
||||
.m_axi_ddr_awaddr(m_axi_ddr_awaddr),
|
||||
.m_axi_ddr_awlen(m_axi_ddr_awlen),
|
||||
.m_axi_ddr_awsize(m_axi_ddr_awsize),
|
||||
.m_axi_ddr_awburst(m_axi_ddr_awburst),
|
||||
.m_axi_ddr_awlock(m_axi_ddr_awlock),
|
||||
.m_axi_ddr_awcache(m_axi_ddr_awcache),
|
||||
.m_axi_ddr_awprot(m_axi_ddr_awprot),
|
||||
.m_axi_ddr_awqos(m_axi_ddr_awqos),
|
||||
.m_axi_ddr_awvalid(m_axi_ddr_awvalid),
|
||||
.m_axi_ddr_awready(m_axi_ddr_awready),
|
||||
.m_axi_ddr_wdata(m_axi_ddr_wdata),
|
||||
.m_axi_ddr_wstrb(m_axi_ddr_wstrb),
|
||||
.m_axi_ddr_wlast(m_axi_ddr_wlast),
|
||||
.m_axi_ddr_wvalid(m_axi_ddr_wvalid),
|
||||
.m_axi_ddr_wready(m_axi_ddr_wready),
|
||||
.m_axi_ddr_bid(m_axi_ddr_bid),
|
||||
.m_axi_ddr_bresp(m_axi_ddr_bresp),
|
||||
.m_axi_ddr_bvalid(m_axi_ddr_bvalid),
|
||||
.m_axi_ddr_bready(m_axi_ddr_bready),
|
||||
.m_axi_ddr_arid(m_axi_ddr_arid),
|
||||
.m_axi_ddr_araddr(m_axi_ddr_araddr),
|
||||
.m_axi_ddr_arlen(m_axi_ddr_arlen),
|
||||
.m_axi_ddr_arsize(m_axi_ddr_arsize),
|
||||
.m_axi_ddr_arburst(m_axi_ddr_arburst),
|
||||
.m_axi_ddr_arlock(m_axi_ddr_arlock),
|
||||
.m_axi_ddr_arcache(m_axi_ddr_arcache),
|
||||
.m_axi_ddr_arprot(m_axi_ddr_arprot),
|
||||
.m_axi_ddr_arqos(m_axi_ddr_arqos),
|
||||
.m_axi_ddr_arvalid(m_axi_ddr_arvalid),
|
||||
.m_axi_ddr_arready(m_axi_ddr_arready),
|
||||
.m_axi_ddr_rid(m_axi_ddr_rid),
|
||||
.m_axi_ddr_rdata(m_axi_ddr_rdata),
|
||||
.m_axi_ddr_rresp(m_axi_ddr_rresp),
|
||||
.m_axi_ddr_rlast(m_axi_ddr_rlast),
|
||||
.m_axi_ddr_rvalid(m_axi_ddr_rvalid),
|
||||
.m_axi_ddr_rready(m_axi_ddr_rready),
|
||||
|
||||
.ddr_status(ddr_status),
|
||||
|
||||
/*
|
||||
* QSPI flash
|
||||
*/
|
||||
|
||||
@ -122,6 +122,16 @@ module fpga_core #
|
||||
parameter TX_RAM_SIZE = 32768,
|
||||
parameter RX_RAM_SIZE = 32768,
|
||||
|
||||
// RAM configuration
|
||||
parameter DDR_CH = 4,
|
||||
parameter DDR_ENABLE = 1,
|
||||
parameter AXI_DDR_DATA_WIDTH = 512,
|
||||
parameter AXI_DDR_ADDR_WIDTH = 34,
|
||||
parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8),
|
||||
parameter AXI_DDR_ID_WIDTH = 8,
|
||||
parameter AXI_DDR_MAX_BURST_LEN = 256,
|
||||
parameter AXI_DDR_NARROW_BURST = 0,
|
||||
|
||||
// Application block configuration
|
||||
parameter APP_ID = 32'h00000000,
|
||||
parameter APP_ENABLE = 0,
|
||||
@ -429,6 +439,52 @@ module fpga_core #
|
||||
input wire qsfp1_intl,
|
||||
output wire qsfp1_lpmode,
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
input wire [DDR_CH-1:0] ddr_clk,
|
||||
input wire [DDR_CH-1:0] ddr_rst,
|
||||
|
||||
output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid,
|
||||
output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr,
|
||||
output wire [DDR_CH*8-1:0] m_axi_ddr_awlen,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_awsize,
|
||||
output wire [DDR_CH*2-1:0] m_axi_ddr_awburst,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_awlock,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_awcache,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_awprot,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_awqos,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_awvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_awready,
|
||||
output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata,
|
||||
output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_wlast,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_wvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_wready,
|
||||
input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid,
|
||||
input wire [DDR_CH*2-1:0] m_axi_ddr_bresp,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_bvalid,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_bready,
|
||||
output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid,
|
||||
output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr,
|
||||
output wire [DDR_CH*8-1:0] m_axi_ddr_arlen,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_arsize,
|
||||
output wire [DDR_CH*2-1:0] m_axi_ddr_arburst,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_arlock,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_arcache,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_arprot,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_arqos,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_arvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_arready,
|
||||
input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid,
|
||||
input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata,
|
||||
input wire [DDR_CH*2-1:0] m_axi_ddr_rresp,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_rlast,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_rvalid,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_rready,
|
||||
|
||||
input wire [DDR_CH-1:0] ddr_status,
|
||||
|
||||
/*
|
||||
* QSPI flash
|
||||
*/
|
||||
@ -1170,6 +1226,25 @@ mqnic_core_pcie_us #(
|
||||
.TX_RAM_SIZE(TX_RAM_SIZE),
|
||||
.RX_RAM_SIZE(RX_RAM_SIZE),
|
||||
|
||||
// RAM configuration
|
||||
.DDR_CH(DDR_CH),
|
||||
.DDR_ENABLE(DDR_ENABLE),
|
||||
.DDR_GROUP_SIZE(1),
|
||||
.AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH),
|
||||
.AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH),
|
||||
.AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH),
|
||||
.AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH),
|
||||
.AXI_DDR_AWUSER_ENABLE(0),
|
||||
.AXI_DDR_WUSER_ENABLE(0),
|
||||
.AXI_DDR_BUSER_ENABLE(0),
|
||||
.AXI_DDR_ARUSER_ENABLE(0),
|
||||
.AXI_DDR_RUSER_ENABLE(0),
|
||||
.AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN),
|
||||
.AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST),
|
||||
.AXI_DDR_FIXED_BURST(0),
|
||||
.AXI_DDR_WRAP_BURST(1),
|
||||
.HBM_ENABLE(0),
|
||||
|
||||
// Application block configuration
|
||||
.APP_ID(APP_ID),
|
||||
.APP_ENABLE(APP_ENABLE),
|
||||
@ -1447,6 +1522,108 @@ core_inst (
|
||||
|
||||
.eth_rx_status(eth_rx_status),
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
.ddr_clk(ddr_clk),
|
||||
.ddr_rst(ddr_rst),
|
||||
|
||||
.m_axi_ddr_awid(m_axi_ddr_awid),
|
||||
.m_axi_ddr_awaddr(m_axi_ddr_awaddr),
|
||||
.m_axi_ddr_awlen(m_axi_ddr_awlen),
|
||||
.m_axi_ddr_awsize(m_axi_ddr_awsize),
|
||||
.m_axi_ddr_awburst(m_axi_ddr_awburst),
|
||||
.m_axi_ddr_awlock(m_axi_ddr_awlock),
|
||||
.m_axi_ddr_awcache(m_axi_ddr_awcache),
|
||||
.m_axi_ddr_awprot(m_axi_ddr_awprot),
|
||||
.m_axi_ddr_awqos(m_axi_ddr_awqos),
|
||||
.m_axi_ddr_awuser(),
|
||||
.m_axi_ddr_awvalid(m_axi_ddr_awvalid),
|
||||
.m_axi_ddr_awready(m_axi_ddr_awready),
|
||||
.m_axi_ddr_wdata(m_axi_ddr_wdata),
|
||||
.m_axi_ddr_wstrb(m_axi_ddr_wstrb),
|
||||
.m_axi_ddr_wlast(m_axi_ddr_wlast),
|
||||
.m_axi_ddr_wuser(),
|
||||
.m_axi_ddr_wvalid(m_axi_ddr_wvalid),
|
||||
.m_axi_ddr_wready(m_axi_ddr_wready),
|
||||
.m_axi_ddr_bid(m_axi_ddr_bid),
|
||||
.m_axi_ddr_bresp(m_axi_ddr_bresp),
|
||||
.m_axi_ddr_buser(0),
|
||||
.m_axi_ddr_bvalid(m_axi_ddr_bvalid),
|
||||
.m_axi_ddr_bready(m_axi_ddr_bready),
|
||||
.m_axi_ddr_arid(m_axi_ddr_arid),
|
||||
.m_axi_ddr_araddr(m_axi_ddr_araddr),
|
||||
.m_axi_ddr_arlen(m_axi_ddr_arlen),
|
||||
.m_axi_ddr_arsize(m_axi_ddr_arsize),
|
||||
.m_axi_ddr_arburst(m_axi_ddr_arburst),
|
||||
.m_axi_ddr_arlock(m_axi_ddr_arlock),
|
||||
.m_axi_ddr_arcache(m_axi_ddr_arcache),
|
||||
.m_axi_ddr_arprot(m_axi_ddr_arprot),
|
||||
.m_axi_ddr_arqos(m_axi_ddr_arqos),
|
||||
.m_axi_ddr_aruser(),
|
||||
.m_axi_ddr_arvalid(m_axi_ddr_arvalid),
|
||||
.m_axi_ddr_arready(m_axi_ddr_arready),
|
||||
.m_axi_ddr_rid(m_axi_ddr_rid),
|
||||
.m_axi_ddr_rdata(m_axi_ddr_rdata),
|
||||
.m_axi_ddr_rresp(m_axi_ddr_rresp),
|
||||
.m_axi_ddr_rlast(m_axi_ddr_rlast),
|
||||
.m_axi_ddr_ruser(0),
|
||||
.m_axi_ddr_rvalid(m_axi_ddr_rvalid),
|
||||
.m_axi_ddr_rready(m_axi_ddr_rready),
|
||||
|
||||
.ddr_status(ddr_status),
|
||||
|
||||
/*
|
||||
* HBM
|
||||
*/
|
||||
.hbm_clk(0),
|
||||
.hbm_rst(0),
|
||||
|
||||
.m_axi_hbm_awid(),
|
||||
.m_axi_hbm_awaddr(),
|
||||
.m_axi_hbm_awlen(),
|
||||
.m_axi_hbm_awsize(),
|
||||
.m_axi_hbm_awburst(),
|
||||
.m_axi_hbm_awlock(),
|
||||
.m_axi_hbm_awcache(),
|
||||
.m_axi_hbm_awprot(),
|
||||
.m_axi_hbm_awqos(),
|
||||
.m_axi_hbm_awuser(),
|
||||
.m_axi_hbm_awvalid(),
|
||||
.m_axi_hbm_awready(0),
|
||||
.m_axi_hbm_wdata(),
|
||||
.m_axi_hbm_wstrb(),
|
||||
.m_axi_hbm_wlast(),
|
||||
.m_axi_hbm_wuser(),
|
||||
.m_axi_hbm_wvalid(),
|
||||
.m_axi_hbm_wready(0),
|
||||
.m_axi_hbm_bid(0),
|
||||
.m_axi_hbm_bresp(0),
|
||||
.m_axi_hbm_buser(0),
|
||||
.m_axi_hbm_bvalid(0),
|
||||
.m_axi_hbm_bready(),
|
||||
.m_axi_hbm_arid(),
|
||||
.m_axi_hbm_araddr(),
|
||||
.m_axi_hbm_arlen(),
|
||||
.m_axi_hbm_arsize(),
|
||||
.m_axi_hbm_arburst(),
|
||||
.m_axi_hbm_arlock(),
|
||||
.m_axi_hbm_arcache(),
|
||||
.m_axi_hbm_arprot(),
|
||||
.m_axi_hbm_arqos(),
|
||||
.m_axi_hbm_aruser(),
|
||||
.m_axi_hbm_arvalid(),
|
||||
.m_axi_hbm_arready(0),
|
||||
.m_axi_hbm_rid(0),
|
||||
.m_axi_hbm_rdata(0),
|
||||
.m_axi_hbm_rresp(0),
|
||||
.m_axi_hbm_rlast(0),
|
||||
.m_axi_hbm_ruser(0),
|
||||
.m_axi_hbm_rvalid(0),
|
||||
.m_axi_hbm_rready(),
|
||||
|
||||
.hbm_status(0),
|
||||
|
||||
/*
|
||||
* Statistics input
|
||||
*/
|
||||
|
||||
@ -7,6 +7,8 @@ This design targets the Xilinx Alveo U280 FPGA board.
|
||||
* FPGA: xcu280-fsvh2892-2L-e
|
||||
* MAC: Xilinx 100G CMAC
|
||||
* PHY: 100G CAUI-4 CMAC and internal GTY transceivers
|
||||
* RAM: 32 GB DDR4 2400 (2x 2G x72 DIMM)
|
||||
* HBM: 8GB HBM2
|
||||
|
||||
## How to build
|
||||
|
||||
|
||||
@ -18,14 +18,14 @@ set_operating_conditions -design_power_budget 160
|
||||
|
||||
# System clocks
|
||||
# 100 MHz (DDR4)
|
||||
#set_property -dict {LOC BJ43 IOSTANDARD LVDS} [get_ports clk_100mhz_0_p]
|
||||
#set_property -dict {LOC BJ44 IOSTANDARD LVDS} [get_ports clk_100mhz_0_n]
|
||||
#create_clock -period 10 -name clk_100mhz_0 [get_ports clk_100mhz_0_p]
|
||||
set_property -dict {LOC BJ43 IOSTANDARD LVDS} [get_ports clk_100mhz_0_p]
|
||||
set_property -dict {LOC BJ44 IOSTANDARD LVDS} [get_ports clk_100mhz_0_n]
|
||||
create_clock -period 10 -name clk_100mhz_0 [get_ports clk_100mhz_0_p]
|
||||
|
||||
# 100 MHz (DDR4)
|
||||
#set_property -dict {LOC BH6 IOSTANDARD LVDS} [get_ports clk_100mhz_1_p]
|
||||
#set_property -dict {LOC BJ6 IOSTANDARD LVDS} [get_ports clk_100mhz_1_n]
|
||||
#create_clock -period 10 -name clk_100mhz_1 [get_ports clk_100mhz_1_p]
|
||||
set_property -dict {LOC BH6 IOSTANDARD LVDS} [get_ports clk_100mhz_1_p]
|
||||
set_property -dict {LOC BJ6 IOSTANDARD LVDS} [get_ports clk_100mhz_1_n]
|
||||
create_clock -period 10 -name clk_100mhz_1 [get_ports clk_100mhz_1_p]
|
||||
|
||||
# 100 MHz
|
||||
#set_property -dict {LOC G31 IOSTANDARD LVDS} [get_ports clk_100mhz_2_p]
|
||||
@ -225,3 +225,283 @@ create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_1_p]
|
||||
|
||||
set_false_path -from [get_ports {pcie_reset_n}]
|
||||
set_input_delay 0 [get_ports {pcie_reset_n}]
|
||||
|
||||
# DDR4 C0
|
||||
set_property -dict {LOC BF46 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}]
|
||||
set_property -dict {LOC BG43 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}]
|
||||
set_property -dict {LOC BK45 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}]
|
||||
set_property -dict {LOC BF42 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}]
|
||||
set_property -dict {LOC BL45 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}]
|
||||
set_property -dict {LOC BF43 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}]
|
||||
set_property -dict {LOC BG42 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}]
|
||||
set_property -dict {LOC BL43 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}]
|
||||
set_property -dict {LOC BK43 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}]
|
||||
set_property -dict {LOC BM42 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}]
|
||||
set_property -dict {LOC BG45 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}]
|
||||
set_property -dict {LOC BD41 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}]
|
||||
set_property -dict {LOC BL42 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}]
|
||||
set_property -dict {LOC BE44 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}]
|
||||
set_property -dict {LOC BE43 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}]
|
||||
set_property -dict {LOC BL46 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}]
|
||||
set_property -dict {LOC BH44 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}]
|
||||
set_property -dict {LOC BH45 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}]
|
||||
set_property -dict {LOC BM47 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}]
|
||||
set_property -dict {LOC BF41 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}]
|
||||
set_property -dict {LOC BE41 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}]
|
||||
set_property -dict {LOC BH46 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c0_ck_t}]
|
||||
set_property -dict {LOC BJ46 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c0_ck_c}]
|
||||
set_property -dict {LOC BH42 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke}]
|
||||
set_property -dict {LOC BK46 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n}]
|
||||
set_property -dict {LOC BH41 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}]
|
||||
set_property -dict {LOC BG44 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt}]
|
||||
set_property -dict {LOC BF45 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}]
|
||||
set_property -dict {LOC BG33 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_c0_reset_n}]
|
||||
|
||||
set_property -dict {LOC BN32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}]
|
||||
set_property -dict {LOC BP32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}]
|
||||
set_property -dict {LOC BL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}]
|
||||
set_property -dict {LOC BM30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}]
|
||||
set_property -dict {LOC BP29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}]
|
||||
set_property -dict {LOC BP28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}]
|
||||
set_property -dict {LOC BP31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}]
|
||||
set_property -dict {LOC BN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}]
|
||||
set_property -dict {LOC BJ31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}]
|
||||
set_property -dict {LOC BH31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}]
|
||||
set_property -dict {LOC BF32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}]
|
||||
set_property -dict {LOC BF33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}]
|
||||
set_property -dict {LOC BH29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}]
|
||||
set_property -dict {LOC BH30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}]
|
||||
set_property -dict {LOC BF31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}]
|
||||
set_property -dict {LOC BG32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}]
|
||||
set_property -dict {LOC BK31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}]
|
||||
set_property -dict {LOC BL31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}]
|
||||
set_property -dict {LOC BK33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}]
|
||||
set_property -dict {LOC BL33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}]
|
||||
set_property -dict {LOC BL32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}]
|
||||
set_property -dict {LOC BM33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}]
|
||||
set_property -dict {LOC BN34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}]
|
||||
set_property -dict {LOC BP34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}]
|
||||
set_property -dict {LOC BH34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}]
|
||||
set_property -dict {LOC BH35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}]
|
||||
set_property -dict {LOC BF35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}]
|
||||
set_property -dict {LOC BF36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}]
|
||||
set_property -dict {LOC BJ33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}]
|
||||
set_property -dict {LOC BJ34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}]
|
||||
set_property -dict {LOC BG34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}]
|
||||
set_property -dict {LOC BG35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}]
|
||||
set_property -dict {LOC BM52 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}]
|
||||
set_property -dict {LOC BL53 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}]
|
||||
set_property -dict {LOC BL52 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}]
|
||||
set_property -dict {LOC BL51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}]
|
||||
set_property -dict {LOC BN50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}]
|
||||
set_property -dict {LOC BN51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}]
|
||||
set_property -dict {LOC BN49 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}]
|
||||
set_property -dict {LOC BM48 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}]
|
||||
set_property -dict {LOC BE50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}]
|
||||
set_property -dict {LOC BE49 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}]
|
||||
set_property -dict {LOC BE51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}]
|
||||
set_property -dict {LOC BD51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}]
|
||||
set_property -dict {LOC BF52 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}]
|
||||
set_property -dict {LOC BF51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}]
|
||||
set_property -dict {LOC BG50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}]
|
||||
set_property -dict {LOC BF50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}]
|
||||
set_property -dict {LOC BH50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}]
|
||||
set_property -dict {LOC BJ51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}]
|
||||
set_property -dict {LOC BH51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}]
|
||||
set_property -dict {LOC BH49 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}]
|
||||
set_property -dict {LOC BK50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}]
|
||||
set_property -dict {LOC BK51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}]
|
||||
set_property -dict {LOC BJ49 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}]
|
||||
set_property -dict {LOC BJ48 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}]
|
||||
set_property -dict {LOC BN44 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}]
|
||||
set_property -dict {LOC BN45 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}]
|
||||
set_property -dict {LOC BM44 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}]
|
||||
set_property -dict {LOC BM45 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}]
|
||||
set_property -dict {LOC BP43 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}]
|
||||
set_property -dict {LOC BP44 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}]
|
||||
set_property -dict {LOC BN47 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}]
|
||||
set_property -dict {LOC BP47 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}]
|
||||
set_property -dict {LOC BG54 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}]
|
||||
set_property -dict {LOC BG53 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}]
|
||||
set_property -dict {LOC BE53 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}]
|
||||
set_property -dict {LOC BE54 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}]
|
||||
set_property -dict {LOC BH52 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}]
|
||||
set_property -dict {LOC BG52 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}]
|
||||
set_property -dict {LOC BK54 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}]
|
||||
set_property -dict {LOC BK53 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}]
|
||||
set_property -dict {LOC BN29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}]
|
||||
set_property -dict {LOC BN30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}]
|
||||
set_property -dict {LOC BM28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}]
|
||||
set_property -dict {LOC BM29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}]
|
||||
set_property -dict {LOC BJ29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}]
|
||||
set_property -dict {LOC BK30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}]
|
||||
set_property -dict {LOC BG29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}]
|
||||
set_property -dict {LOC BG30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}]
|
||||
set_property -dict {LOC BL35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}]
|
||||
set_property -dict {LOC BM35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}]
|
||||
set_property -dict {LOC BM34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}]
|
||||
set_property -dict {LOC BN35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}]
|
||||
set_property -dict {LOC BK34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}]
|
||||
set_property -dict {LOC BK35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}]
|
||||
set_property -dict {LOC BH32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}]
|
||||
set_property -dict {LOC BJ32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}]
|
||||
set_property -dict {LOC BM49 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}]
|
||||
set_property -dict {LOC BM50 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}]
|
||||
set_property -dict {LOC BP48 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[9]}]
|
||||
set_property -dict {LOC BP49 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[9]}]
|
||||
set_property -dict {LOC BF47 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[10]}]
|
||||
set_property -dict {LOC BF48 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[10]}]
|
||||
set_property -dict {LOC BG48 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[11]}]
|
||||
set_property -dict {LOC BG49 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[11]}]
|
||||
set_property -dict {LOC BH47 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[12]}]
|
||||
set_property -dict {LOC BJ47 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[12]}]
|
||||
set_property -dict {LOC BK48 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[13]}]
|
||||
set_property -dict {LOC BK49 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[13]}]
|
||||
set_property -dict {LOC BN46 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[14]}]
|
||||
set_property -dict {LOC BP46 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[14]}]
|
||||
set_property -dict {LOC BN42 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[15]}]
|
||||
set_property -dict {LOC BP42 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[15]}]
|
||||
set_property -dict {LOC BH54 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[16]}]
|
||||
set_property -dict {LOC BJ54 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[16]}]
|
||||
set_property -dict {LOC BJ52 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[17]}]
|
||||
set_property -dict {LOC BJ53 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[17]}]
|
||||
|
||||
# DDR4 C1
|
||||
set_property -dict {LOC BF7 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}]
|
||||
set_property -dict {LOC BK1 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}]
|
||||
set_property -dict {LOC BF6 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}]
|
||||
set_property -dict {LOC BF5 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}]
|
||||
set_property -dict {LOC BE3 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}]
|
||||
set_property -dict {LOC BE6 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}]
|
||||
set_property -dict {LOC BE5 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}]
|
||||
set_property -dict {LOC BG7 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}]
|
||||
set_property -dict {LOC BJ1 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}]
|
||||
set_property -dict {LOC BG2 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}]
|
||||
set_property -dict {LOC BJ8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}]
|
||||
set_property -dict {LOC BE4 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}]
|
||||
set_property -dict {LOC BL2 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}]
|
||||
set_property -dict {LOC BK5 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}]
|
||||
set_property -dict {LOC BK8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}]
|
||||
set_property -dict {LOC BJ4 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}]
|
||||
set_property -dict {LOC BF8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}]
|
||||
set_property -dict {LOC BG8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}]
|
||||
set_property -dict {LOC BK4 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}]
|
||||
set_property -dict {LOC BF3 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}]
|
||||
set_property -dict {LOC BF2 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}]
|
||||
set_property -dict {LOC BJ3 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c1_ck_t}]
|
||||
set_property -dict {LOC BJ2 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c1_ck_c}]
|
||||
set_property -dict {LOC BE1 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke}]
|
||||
set_property -dict {LOC BL3 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n}]
|
||||
set_property -dict {LOC BG3 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}]
|
||||
set_property -dict {LOC BH2 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt}]
|
||||
set_property -dict {LOC BH1 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}]
|
||||
set_property -dict {LOC BH12 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_c1_reset_n}]
|
||||
|
||||
set_property -dict {LOC A11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}]
|
||||
set_property -dict {LOC A10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}]
|
||||
set_property -dict {LOC A9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}]
|
||||
set_property -dict {LOC A8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}]
|
||||
set_property -dict {LOC B12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}]
|
||||
set_property -dict {LOC B10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}]
|
||||
set_property -dict {LOC C12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}]
|
||||
set_property -dict {LOC B11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}]
|
||||
set_property -dict {LOC E11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}]
|
||||
set_property -dict {LOC D11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}]
|
||||
set_property -dict {LOC E12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}]
|
||||
set_property -dict {LOC F11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}]
|
||||
set_property -dict {LOC F10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}]
|
||||
set_property -dict {LOC E9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}]
|
||||
set_property -dict {LOC F9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}]
|
||||
set_property -dict {LOC G11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}]
|
||||
set_property -dict {LOC H12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}]
|
||||
set_property -dict {LOC G13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}]
|
||||
set_property -dict {LOC H13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}]
|
||||
set_property -dict {LOC H14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}]
|
||||
set_property -dict {LOC J11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}]
|
||||
set_property -dict {LOC J12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}]
|
||||
set_property -dict {LOC J15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}]
|
||||
set_property -dict {LOC J14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}]
|
||||
set_property -dict {LOC A14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}]
|
||||
set_property -dict {LOC C15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}]
|
||||
set_property -dict {LOC A15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}]
|
||||
set_property -dict {LOC B15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}]
|
||||
set_property -dict {LOC F15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}]
|
||||
set_property -dict {LOC E14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}]
|
||||
set_property -dict {LOC F14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}]
|
||||
set_property -dict {LOC F13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}]
|
||||
set_property -dict {LOC BM3 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}]
|
||||
set_property -dict {LOC BM4 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}]
|
||||
set_property -dict {LOC BM5 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}]
|
||||
set_property -dict {LOC BL6 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}]
|
||||
set_property -dict {LOC BN4 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}]
|
||||
set_property -dict {LOC BN5 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}]
|
||||
set_property -dict {LOC BN6 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}]
|
||||
set_property -dict {LOC BN7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}]
|
||||
set_property -dict {LOC BJ9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}]
|
||||
set_property -dict {LOC BK9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}]
|
||||
set_property -dict {LOC BK10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}]
|
||||
set_property -dict {LOC BL10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}]
|
||||
set_property -dict {LOC BM9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}]
|
||||
set_property -dict {LOC BN9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}]
|
||||
set_property -dict {LOC BN10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}]
|
||||
set_property -dict {LOC BM10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}]
|
||||
set_property -dict {LOC BM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}]
|
||||
set_property -dict {LOC BM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}]
|
||||
set_property -dict {LOC BL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}]
|
||||
set_property -dict {LOC BM13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}]
|
||||
set_property -dict {LOC BN12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}]
|
||||
set_property -dict {LOC BM12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}]
|
||||
set_property -dict {LOC BP13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}]
|
||||
set_property -dict {LOC BP14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}]
|
||||
set_property -dict {LOC BJ13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}]
|
||||
set_property -dict {LOC BJ12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}]
|
||||
set_property -dict {LOC BH15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}]
|
||||
set_property -dict {LOC BH14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}]
|
||||
set_property -dict {LOC BK14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}]
|
||||
set_property -dict {LOC BK15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}]
|
||||
set_property -dict {LOC BL12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}]
|
||||
set_property -dict {LOC BL13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}]
|
||||
set_property -dict {LOC BE9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}]
|
||||
set_property -dict {LOC BE10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}]
|
||||
set_property -dict {LOC BF10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}]
|
||||
set_property -dict {LOC BE11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}]
|
||||
set_property -dict {LOC BG13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}]
|
||||
set_property -dict {LOC BG12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}]
|
||||
set_property -dict {LOC BG9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}]
|
||||
set_property -dict {LOC BG10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}]
|
||||
set_property -dict {LOC B13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}]
|
||||
set_property -dict {LOC A13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}]
|
||||
set_property -dict {LOC C10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}]
|
||||
set_property -dict {LOC C9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}]
|
||||
set_property -dict {LOC D10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}]
|
||||
set_property -dict {LOC D9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}]
|
||||
set_property -dict {LOC H10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}]
|
||||
set_property -dict {LOC G10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}]
|
||||
set_property -dict {LOC H15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}]
|
||||
set_property -dict {LOC G15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}]
|
||||
set_property -dict {LOC K14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}]
|
||||
set_property -dict {LOC K13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}]
|
||||
set_property -dict {LOC D15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}]
|
||||
set_property -dict {LOC D14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}]
|
||||
set_property -dict {LOC E13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}]
|
||||
set_property -dict {LOC D12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}]
|
||||
set_property -dict {LOC BL7 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}]
|
||||
set_property -dict {LOC BM7 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}]
|
||||
set_property -dict {LOC BP7 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}]
|
||||
set_property -dict {LOC BP6 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}]
|
||||
set_property -dict {LOC BL8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[10]}]
|
||||
set_property -dict {LOC BM8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[10]}]
|
||||
set_property -dict {LOC BP9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[11]}]
|
||||
set_property -dict {LOC BP8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[11]}]
|
||||
set_property -dict {LOC BN15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[12]}]
|
||||
set_property -dict {LOC BN14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[12]}]
|
||||
set_property -dict {LOC BP12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[13]}]
|
||||
set_property -dict {LOC BP11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[13]}]
|
||||
set_property -dict {LOC BJ14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[14]}]
|
||||
set_property -dict {LOC BK13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[14]}]
|
||||
set_property -dict {LOC BJ11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[15]}]
|
||||
set_property -dict {LOC BK11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[15]}]
|
||||
set_property -dict {LOC BF12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[16]}]
|
||||
set_property -dict {LOC BF11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[16]}]
|
||||
set_property -dict {LOC BH10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[17]}]
|
||||
set_property -dict {LOC BH9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[17]}]
|
||||
|
||||
@ -117,12 +117,15 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
|
||||
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
|
||||
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
|
||||
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
|
||||
XDC_FILES += hbm.xdc
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl
|
||||
IP_TCL_FILES += ip/cmac_usplus_0.tcl
|
||||
IP_TCL_FILES += ip/cmac_usplus_1.tcl
|
||||
IP_TCL_FILES += ip/cms.tcl
|
||||
IP_TCL_FILES += ip/hbm_0.tcl
|
||||
IP_TCL_FILES += ip/ddr4_0.tcl
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
@ -136,6 +136,17 @@ dict set params MAX_TX_SIZE "9214"
|
||||
dict set params MAX_RX_SIZE "9214"
|
||||
dict set params TX_RAM_SIZE "131072"
|
||||
dict set params RX_RAM_SIZE "131072"
|
||||
|
||||
# RAM configuration
|
||||
dict set params DDR_CH "2"
|
||||
dict set params DDR_ENABLE "1"
|
||||
dict set params AXI_DDR_ID_WIDTH "8"
|
||||
dict set params AXI_DDR_MAX_BURST_LEN "256"
|
||||
dict set params HBM_CH "32"
|
||||
dict set params HBM_ENABLE "1"
|
||||
dict set params HBM_GROUP_SIZE "32"
|
||||
dict set params AXI_HBM_ADDR_WIDTH "33"
|
||||
dict set params AXI_HBM_MAX_BURST_LEN "256"
|
||||
|
||||
# Application block configuration
|
||||
dict set params APP_ID "32'h00000000"
|
||||
@ -187,6 +198,19 @@ dict set params STAT_PCIE_ENABLE "1"
|
||||
dict set params STAT_INC_WIDTH "24"
|
||||
dict set params STAT_ID_WIDTH "12"
|
||||
|
||||
# DDR4 MIG settings
|
||||
if {[dict get $params DDR_ENABLE]} {
|
||||
set ddr4 [get_ips ddr4_0]
|
||||
|
||||
# set AXI ID width
|
||||
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
|
||||
|
||||
# extract AXI configuration
|
||||
dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4]
|
||||
dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4]
|
||||
dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1]
|
||||
}
|
||||
|
||||
# PCIe IP core settings
|
||||
set pcie [get_ips pcie4c_uscale_plus_0]
|
||||
|
||||
|
||||
2
fpga/mqnic/AU280/fpga_100g/hbm.xdc
Normal file
2
fpga/mqnic/AU280/fpga_100g/hbm.xdc
Normal file
@ -0,0 +1,2 @@
|
||||
# force debug hub to use HBM APB clock to prevent CDC issues
|
||||
connect_debug_port dbg_hub/clk [get_nets */APB_0_PCLK]
|
||||
18
fpga/mqnic/AU280/fpga_100g/ip/ddr4_0.tcl
Normal file
18
fpga/mqnic/AU280/fpga_100g/ip/ddr4_0.tcl
Normal file
@ -0,0 +1,18 @@
|
||||
|
||||
create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0
|
||||
|
||||
set_property -dict [list \
|
||||
CONFIG.System_Clock {No_Buffer} \
|
||||
CONFIG.C0.DDR4_AxiSelection {true} \
|
||||
CONFIG.C0.DDR4_AxiDataWidth {512} \
|
||||
CONFIG.C0.DDR4_AxiIDWidth {8} \
|
||||
CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \
|
||||
CONFIG.C0.DDR4_TimePeriod {833} \
|
||||
CONFIG.C0.DDR4_InputClockPeriod {9996} \
|
||||
CONFIG.C0.DDR4_MemoryType {RDIMMs} \
|
||||
CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PZ-2G3} \
|
||||
CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \
|
||||
CONFIG.C0.DDR4_CasLatency {17} \
|
||||
CONFIG.C0.DDR4_CasWriteLatency {12} \
|
||||
CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV}
|
||||
] [get_ips ddr4_0]
|
||||
23
fpga/mqnic/AU280/fpga_100g/ip/hbm_0.tcl
Normal file
23
fpga/mqnic/AU280/fpga_100g/ip/hbm_0.tcl
Normal file
@ -0,0 +1,23 @@
|
||||
|
||||
create_ip -name hbm -vendor xilinx.com -library ip -module_name hbm_0
|
||||
|
||||
set_property -dict [list \
|
||||
CONFIG.USER_HBM_DENSITY {8GB} \
|
||||
CONFIG.USER_HBM_STACK {2} \
|
||||
CONFIG.USER_MC0_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC1_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC2_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC3_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC4_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC5_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC6_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC7_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC8_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC9_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC10_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC11_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC12_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC13_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC14_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC15_ENABLE_ECC_CORRECTION {true}
|
||||
] [get_ips hbm_0]
|
||||
File diff suppressed because it is too large
Load Diff
@ -115,6 +115,24 @@ module fpga_core #
|
||||
parameter TX_RAM_SIZE = 131072,
|
||||
parameter RX_RAM_SIZE = 131072,
|
||||
|
||||
// RAM configuration
|
||||
parameter DDR_CH = 2,
|
||||
parameter DDR_ENABLE = 1,
|
||||
parameter AXI_DDR_DATA_WIDTH = 512,
|
||||
parameter AXI_DDR_ADDR_WIDTH = 34,
|
||||
parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8),
|
||||
parameter AXI_DDR_ID_WIDTH = 8,
|
||||
parameter AXI_DDR_MAX_BURST_LEN = 256,
|
||||
parameter AXI_DDR_NARROW_BURST = 0,
|
||||
parameter HBM_CH = 32,
|
||||
parameter HBM_ENABLE = 1,
|
||||
parameter HBM_GROUP_SIZE = 32,
|
||||
parameter AXI_HBM_DATA_WIDTH = 256,
|
||||
parameter AXI_HBM_ADDR_WIDTH = 33,
|
||||
parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8),
|
||||
parameter AXI_HBM_ID_WIDTH = 6,
|
||||
parameter AXI_HBM_MAX_BURST_LEN = 256,
|
||||
|
||||
// Application block configuration
|
||||
parameter APP_ID = 32'h00000000,
|
||||
parameter APP_ENABLE = 0,
|
||||
@ -336,6 +354,98 @@ module fpga_core #
|
||||
|
||||
input wire qsfp1_rx_status,
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
input wire [DDR_CH-1:0] ddr_clk,
|
||||
input wire [DDR_CH-1:0] ddr_rst,
|
||||
|
||||
output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid,
|
||||
output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr,
|
||||
output wire [DDR_CH*8-1:0] m_axi_ddr_awlen,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_awsize,
|
||||
output wire [DDR_CH*2-1:0] m_axi_ddr_awburst,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_awlock,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_awcache,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_awprot,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_awqos,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_awvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_awready,
|
||||
output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata,
|
||||
output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_wlast,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_wvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_wready,
|
||||
input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid,
|
||||
input wire [DDR_CH*2-1:0] m_axi_ddr_bresp,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_bvalid,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_bready,
|
||||
output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid,
|
||||
output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr,
|
||||
output wire [DDR_CH*8-1:0] m_axi_ddr_arlen,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_arsize,
|
||||
output wire [DDR_CH*2-1:0] m_axi_ddr_arburst,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_arlock,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_arcache,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_arprot,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_arqos,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_arvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_arready,
|
||||
input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid,
|
||||
input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata,
|
||||
input wire [DDR_CH*2-1:0] m_axi_ddr_rresp,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_rlast,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_rvalid,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_rready,
|
||||
|
||||
input wire [DDR_CH-1:0] ddr_status,
|
||||
|
||||
/*
|
||||
* HBM
|
||||
*/
|
||||
input wire [HBM_CH-1:0] hbm_clk,
|
||||
input wire [HBM_CH-1:0] hbm_rst,
|
||||
|
||||
output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_awid,
|
||||
output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_awaddr,
|
||||
output wire [HBM_CH*8-1:0] m_axi_hbm_awlen,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_awsize,
|
||||
output wire [HBM_CH*2-1:0] m_axi_hbm_awburst,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_awlock,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_awcache,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_awprot,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_awqos,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_awvalid,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_awready,
|
||||
output wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_wdata,
|
||||
output wire [HBM_CH*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_wstrb,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_wlast,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_wvalid,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_wready,
|
||||
input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_bid,
|
||||
input wire [HBM_CH*2-1:0] m_axi_hbm_bresp,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_bvalid,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_bready,
|
||||
output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_arid,
|
||||
output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_araddr,
|
||||
output wire [HBM_CH*8-1:0] m_axi_hbm_arlen,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_arsize,
|
||||
output wire [HBM_CH*2-1:0] m_axi_hbm_arburst,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_arlock,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_arcache,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_arprot,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_arqos,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_arvalid,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_arready,
|
||||
input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_rid,
|
||||
input wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_rdata,
|
||||
input wire [HBM_CH*2-1:0] m_axi_hbm_rresp,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_rlast,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_rvalid,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_rready,
|
||||
|
||||
input wire [HBM_CH-1:0] hbm_status,
|
||||
|
||||
/*
|
||||
* QSPI flash
|
||||
*/
|
||||
@ -792,6 +902,40 @@ mqnic_core_pcie_us #(
|
||||
.TX_RAM_SIZE(TX_RAM_SIZE),
|
||||
.RX_RAM_SIZE(RX_RAM_SIZE),
|
||||
|
||||
// RAM configuration
|
||||
.DDR_CH(DDR_CH),
|
||||
.DDR_ENABLE(DDR_ENABLE),
|
||||
.DDR_GROUP_SIZE(1),
|
||||
.AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH),
|
||||
.AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH),
|
||||
.AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH),
|
||||
.AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH),
|
||||
.AXI_DDR_AWUSER_ENABLE(0),
|
||||
.AXI_DDR_WUSER_ENABLE(0),
|
||||
.AXI_DDR_BUSER_ENABLE(0),
|
||||
.AXI_DDR_ARUSER_ENABLE(0),
|
||||
.AXI_DDR_RUSER_ENABLE(0),
|
||||
.AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN),
|
||||
.AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST),
|
||||
.AXI_DDR_FIXED_BURST(0),
|
||||
.AXI_DDR_WRAP_BURST(1),
|
||||
.HBM_CH(HBM_CH),
|
||||
.HBM_ENABLE(HBM_ENABLE),
|
||||
.HBM_GROUP_SIZE(HBM_GROUP_SIZE),
|
||||
.AXI_HBM_DATA_WIDTH(AXI_HBM_DATA_WIDTH),
|
||||
.AXI_HBM_ADDR_WIDTH(AXI_HBM_ADDR_WIDTH),
|
||||
.AXI_HBM_STRB_WIDTH(AXI_HBM_STRB_WIDTH),
|
||||
.AXI_HBM_ID_WIDTH(AXI_HBM_ID_WIDTH),
|
||||
.AXI_HBM_AWUSER_ENABLE(0),
|
||||
.AXI_HBM_WUSER_ENABLE(0),
|
||||
.AXI_HBM_BUSER_ENABLE(0),
|
||||
.AXI_HBM_ARUSER_ENABLE(0),
|
||||
.AXI_HBM_RUSER_ENABLE(0),
|
||||
.AXI_HBM_MAX_BURST_LEN(AXI_HBM_MAX_BURST_LEN),
|
||||
.AXI_HBM_NARROW_BURST(0),
|
||||
.AXI_HBM_FIXED_BURST(0),
|
||||
.AXI_HBM_WRAP_BURST(1),
|
||||
|
||||
// Application block configuration
|
||||
.APP_ID(APP_ID),
|
||||
.APP_ENABLE(APP_ENABLE),
|
||||
@ -1069,6 +1213,108 @@ core_inst (
|
||||
|
||||
.eth_rx_status(eth_rx_status),
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
.ddr_clk(ddr_clk),
|
||||
.ddr_rst(ddr_rst),
|
||||
|
||||
.m_axi_ddr_awid(m_axi_ddr_awid),
|
||||
.m_axi_ddr_awaddr(m_axi_ddr_awaddr),
|
||||
.m_axi_ddr_awlen(m_axi_ddr_awlen),
|
||||
.m_axi_ddr_awsize(m_axi_ddr_awsize),
|
||||
.m_axi_ddr_awburst(m_axi_ddr_awburst),
|
||||
.m_axi_ddr_awlock(m_axi_ddr_awlock),
|
||||
.m_axi_ddr_awcache(m_axi_ddr_awcache),
|
||||
.m_axi_ddr_awprot(m_axi_ddr_awprot),
|
||||
.m_axi_ddr_awqos(m_axi_ddr_awqos),
|
||||
.m_axi_ddr_awuser(),
|
||||
.m_axi_ddr_awvalid(m_axi_ddr_awvalid),
|
||||
.m_axi_ddr_awready(m_axi_ddr_awready),
|
||||
.m_axi_ddr_wdata(m_axi_ddr_wdata),
|
||||
.m_axi_ddr_wstrb(m_axi_ddr_wstrb),
|
||||
.m_axi_ddr_wlast(m_axi_ddr_wlast),
|
||||
.m_axi_ddr_wuser(),
|
||||
.m_axi_ddr_wvalid(m_axi_ddr_wvalid),
|
||||
.m_axi_ddr_wready(m_axi_ddr_wready),
|
||||
.m_axi_ddr_bid(m_axi_ddr_bid),
|
||||
.m_axi_ddr_bresp(m_axi_ddr_bresp),
|
||||
.m_axi_ddr_buser(0),
|
||||
.m_axi_ddr_bvalid(m_axi_ddr_bvalid),
|
||||
.m_axi_ddr_bready(m_axi_ddr_bready),
|
||||
.m_axi_ddr_arid(m_axi_ddr_arid),
|
||||
.m_axi_ddr_araddr(m_axi_ddr_araddr),
|
||||
.m_axi_ddr_arlen(m_axi_ddr_arlen),
|
||||
.m_axi_ddr_arsize(m_axi_ddr_arsize),
|
||||
.m_axi_ddr_arburst(m_axi_ddr_arburst),
|
||||
.m_axi_ddr_arlock(m_axi_ddr_arlock),
|
||||
.m_axi_ddr_arcache(m_axi_ddr_arcache),
|
||||
.m_axi_ddr_arprot(m_axi_ddr_arprot),
|
||||
.m_axi_ddr_arqos(m_axi_ddr_arqos),
|
||||
.m_axi_ddr_aruser(),
|
||||
.m_axi_ddr_arvalid(m_axi_ddr_arvalid),
|
||||
.m_axi_ddr_arready(m_axi_ddr_arready),
|
||||
.m_axi_ddr_rid(m_axi_ddr_rid),
|
||||
.m_axi_ddr_rdata(m_axi_ddr_rdata),
|
||||
.m_axi_ddr_rresp(m_axi_ddr_rresp),
|
||||
.m_axi_ddr_rlast(m_axi_ddr_rlast),
|
||||
.m_axi_ddr_ruser(0),
|
||||
.m_axi_ddr_rvalid(m_axi_ddr_rvalid),
|
||||
.m_axi_ddr_rready(m_axi_ddr_rready),
|
||||
|
||||
.ddr_status(ddr_status),
|
||||
|
||||
/*
|
||||
* HBM
|
||||
*/
|
||||
.hbm_clk(hbm_clk),
|
||||
.hbm_rst(hbm_rst),
|
||||
|
||||
.m_axi_hbm_awid(m_axi_hbm_awid),
|
||||
.m_axi_hbm_awaddr(m_axi_hbm_awaddr),
|
||||
.m_axi_hbm_awlen(m_axi_hbm_awlen),
|
||||
.m_axi_hbm_awsize(m_axi_hbm_awsize),
|
||||
.m_axi_hbm_awburst(m_axi_hbm_awburst),
|
||||
.m_axi_hbm_awlock(m_axi_hbm_awlock),
|
||||
.m_axi_hbm_awcache(m_axi_hbm_awcache),
|
||||
.m_axi_hbm_awprot(m_axi_hbm_awprot),
|
||||
.m_axi_hbm_awqos(m_axi_hbm_awqos),
|
||||
.m_axi_hbm_awuser(),
|
||||
.m_axi_hbm_awvalid(m_axi_hbm_awvalid),
|
||||
.m_axi_hbm_awready(m_axi_hbm_awready),
|
||||
.m_axi_hbm_wdata(m_axi_hbm_wdata),
|
||||
.m_axi_hbm_wstrb(m_axi_hbm_wstrb),
|
||||
.m_axi_hbm_wlast(m_axi_hbm_wlast),
|
||||
.m_axi_hbm_wuser(),
|
||||
.m_axi_hbm_wvalid(m_axi_hbm_wvalid),
|
||||
.m_axi_hbm_wready(m_axi_hbm_wready),
|
||||
.m_axi_hbm_bid(m_axi_hbm_bid),
|
||||
.m_axi_hbm_bresp(m_axi_hbm_bresp),
|
||||
.m_axi_hbm_buser(0),
|
||||
.m_axi_hbm_bvalid(m_axi_hbm_bvalid),
|
||||
.m_axi_hbm_bready(m_axi_hbm_bready),
|
||||
.m_axi_hbm_arid(m_axi_hbm_arid),
|
||||
.m_axi_hbm_araddr(m_axi_hbm_araddr),
|
||||
.m_axi_hbm_arlen(m_axi_hbm_arlen),
|
||||
.m_axi_hbm_arsize(m_axi_hbm_arsize),
|
||||
.m_axi_hbm_arburst(m_axi_hbm_arburst),
|
||||
.m_axi_hbm_arlock(m_axi_hbm_arlock),
|
||||
.m_axi_hbm_arcache(m_axi_hbm_arcache),
|
||||
.m_axi_hbm_arprot(m_axi_hbm_arprot),
|
||||
.m_axi_hbm_arqos(m_axi_hbm_arqos),
|
||||
.m_axi_hbm_aruser(),
|
||||
.m_axi_hbm_arvalid(m_axi_hbm_arvalid),
|
||||
.m_axi_hbm_arready(m_axi_hbm_arready),
|
||||
.m_axi_hbm_rid(m_axi_hbm_rid),
|
||||
.m_axi_hbm_rdata(m_axi_hbm_rdata),
|
||||
.m_axi_hbm_rresp(m_axi_hbm_rresp),
|
||||
.m_axi_hbm_rlast(m_axi_hbm_rlast),
|
||||
.m_axi_hbm_ruser(0),
|
||||
.m_axi_hbm_rvalid(m_axi_hbm_rvalid),
|
||||
.m_axi_hbm_rready(m_axi_hbm_rready),
|
||||
|
||||
.hbm_status(hbm_status),
|
||||
|
||||
/*
|
||||
* Statistics input
|
||||
*/
|
||||
|
||||
@ -6,6 +6,8 @@ This design targets the Xilinx Alveo U280 FPGA board.
|
||||
|
||||
* FPGA: xcu280-fsvh2892-2L-e
|
||||
* PHY: 10G BASE-R PHY IP core and internal GTY transceivers
|
||||
* RAM: 32 GB DDR4 2400 (2x 2G x72 DIMM)
|
||||
* HBM: 8GB HBM2
|
||||
|
||||
## How to build
|
||||
|
||||
|
||||
@ -18,14 +18,14 @@ set_operating_conditions -design_power_budget 160
|
||||
|
||||
# System clocks
|
||||
# 100 MHz (DDR4)
|
||||
#set_property -dict {LOC BJ43 IOSTANDARD LVDS} [get_ports clk_100mhz_0_p]
|
||||
#set_property -dict {LOC BJ44 IOSTANDARD LVDS} [get_ports clk_100mhz_0_n]
|
||||
#create_clock -period 10 -name clk_100mhz_0 [get_ports clk_100mhz_0_p]
|
||||
set_property -dict {LOC BJ43 IOSTANDARD LVDS} [get_ports clk_100mhz_0_p]
|
||||
set_property -dict {LOC BJ44 IOSTANDARD LVDS} [get_ports clk_100mhz_0_n]
|
||||
create_clock -period 10 -name clk_100mhz_0 [get_ports clk_100mhz_0_p]
|
||||
|
||||
# 100 MHz (DDR4)
|
||||
#set_property -dict {LOC BH6 IOSTANDARD LVDS} [get_ports clk_100mhz_1_p]
|
||||
#set_property -dict {LOC BJ6 IOSTANDARD LVDS} [get_ports clk_100mhz_1_n]
|
||||
#create_clock -period 10 -name clk_100mhz_1 [get_ports clk_100mhz_1_p]
|
||||
set_property -dict {LOC BH6 IOSTANDARD LVDS} [get_ports clk_100mhz_1_p]
|
||||
set_property -dict {LOC BJ6 IOSTANDARD LVDS} [get_ports clk_100mhz_1_n]
|
||||
create_clock -period 10 -name clk_100mhz_1 [get_ports clk_100mhz_1_p]
|
||||
|
||||
# 100 MHz
|
||||
#set_property -dict {LOC G31 IOSTANDARD LVDS} [get_ports clk_100mhz_2_p]
|
||||
@ -225,3 +225,283 @@ create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_1_p]
|
||||
|
||||
set_false_path -from [get_ports {pcie_reset_n}]
|
||||
set_input_delay 0 [get_ports {pcie_reset_n}]
|
||||
|
||||
# DDR4 C0
|
||||
set_property -dict {LOC BF46 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}]
|
||||
set_property -dict {LOC BG43 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}]
|
||||
set_property -dict {LOC BK45 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}]
|
||||
set_property -dict {LOC BF42 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}]
|
||||
set_property -dict {LOC BL45 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}]
|
||||
set_property -dict {LOC BF43 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}]
|
||||
set_property -dict {LOC BG42 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}]
|
||||
set_property -dict {LOC BL43 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}]
|
||||
set_property -dict {LOC BK43 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}]
|
||||
set_property -dict {LOC BM42 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}]
|
||||
set_property -dict {LOC BG45 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}]
|
||||
set_property -dict {LOC BD41 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}]
|
||||
set_property -dict {LOC BL42 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}]
|
||||
set_property -dict {LOC BE44 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}]
|
||||
set_property -dict {LOC BE43 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}]
|
||||
set_property -dict {LOC BL46 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}]
|
||||
set_property -dict {LOC BH44 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}]
|
||||
set_property -dict {LOC BH45 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}]
|
||||
set_property -dict {LOC BM47 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}]
|
||||
set_property -dict {LOC BF41 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}]
|
||||
set_property -dict {LOC BE41 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}]
|
||||
set_property -dict {LOC BH46 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c0_ck_t}]
|
||||
set_property -dict {LOC BJ46 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c0_ck_c}]
|
||||
set_property -dict {LOC BH42 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke}]
|
||||
set_property -dict {LOC BK46 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n}]
|
||||
set_property -dict {LOC BH41 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}]
|
||||
set_property -dict {LOC BG44 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt}]
|
||||
set_property -dict {LOC BF45 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}]
|
||||
set_property -dict {LOC BG33 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_c0_reset_n}]
|
||||
|
||||
set_property -dict {LOC BN32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}]
|
||||
set_property -dict {LOC BP32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}]
|
||||
set_property -dict {LOC BL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}]
|
||||
set_property -dict {LOC BM30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}]
|
||||
set_property -dict {LOC BP29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}]
|
||||
set_property -dict {LOC BP28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}]
|
||||
set_property -dict {LOC BP31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}]
|
||||
set_property -dict {LOC BN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}]
|
||||
set_property -dict {LOC BJ31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}]
|
||||
set_property -dict {LOC BH31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}]
|
||||
set_property -dict {LOC BF32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}]
|
||||
set_property -dict {LOC BF33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}]
|
||||
set_property -dict {LOC BH29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}]
|
||||
set_property -dict {LOC BH30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}]
|
||||
set_property -dict {LOC BF31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}]
|
||||
set_property -dict {LOC BG32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}]
|
||||
set_property -dict {LOC BK31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}]
|
||||
set_property -dict {LOC BL31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}]
|
||||
set_property -dict {LOC BK33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}]
|
||||
set_property -dict {LOC BL33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}]
|
||||
set_property -dict {LOC BL32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}]
|
||||
set_property -dict {LOC BM33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}]
|
||||
set_property -dict {LOC BN34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}]
|
||||
set_property -dict {LOC BP34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}]
|
||||
set_property -dict {LOC BH34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}]
|
||||
set_property -dict {LOC BH35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}]
|
||||
set_property -dict {LOC BF35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}]
|
||||
set_property -dict {LOC BF36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}]
|
||||
set_property -dict {LOC BJ33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}]
|
||||
set_property -dict {LOC BJ34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}]
|
||||
set_property -dict {LOC BG34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}]
|
||||
set_property -dict {LOC BG35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}]
|
||||
set_property -dict {LOC BM52 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}]
|
||||
set_property -dict {LOC BL53 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}]
|
||||
set_property -dict {LOC BL52 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}]
|
||||
set_property -dict {LOC BL51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}]
|
||||
set_property -dict {LOC BN50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}]
|
||||
set_property -dict {LOC BN51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}]
|
||||
set_property -dict {LOC BN49 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}]
|
||||
set_property -dict {LOC BM48 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}]
|
||||
set_property -dict {LOC BE50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}]
|
||||
set_property -dict {LOC BE49 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}]
|
||||
set_property -dict {LOC BE51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}]
|
||||
set_property -dict {LOC BD51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}]
|
||||
set_property -dict {LOC BF52 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}]
|
||||
set_property -dict {LOC BF51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}]
|
||||
set_property -dict {LOC BG50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}]
|
||||
set_property -dict {LOC BF50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}]
|
||||
set_property -dict {LOC BH50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}]
|
||||
set_property -dict {LOC BJ51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}]
|
||||
set_property -dict {LOC BH51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}]
|
||||
set_property -dict {LOC BH49 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}]
|
||||
set_property -dict {LOC BK50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}]
|
||||
set_property -dict {LOC BK51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}]
|
||||
set_property -dict {LOC BJ49 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}]
|
||||
set_property -dict {LOC BJ48 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}]
|
||||
set_property -dict {LOC BN44 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}]
|
||||
set_property -dict {LOC BN45 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}]
|
||||
set_property -dict {LOC BM44 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}]
|
||||
set_property -dict {LOC BM45 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}]
|
||||
set_property -dict {LOC BP43 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}]
|
||||
set_property -dict {LOC BP44 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}]
|
||||
set_property -dict {LOC BN47 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}]
|
||||
set_property -dict {LOC BP47 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}]
|
||||
set_property -dict {LOC BG54 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}]
|
||||
set_property -dict {LOC BG53 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}]
|
||||
set_property -dict {LOC BE53 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}]
|
||||
set_property -dict {LOC BE54 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}]
|
||||
set_property -dict {LOC BH52 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}]
|
||||
set_property -dict {LOC BG52 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}]
|
||||
set_property -dict {LOC BK54 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}]
|
||||
set_property -dict {LOC BK53 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}]
|
||||
set_property -dict {LOC BN29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}]
|
||||
set_property -dict {LOC BN30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}]
|
||||
set_property -dict {LOC BM28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}]
|
||||
set_property -dict {LOC BM29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}]
|
||||
set_property -dict {LOC BJ29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}]
|
||||
set_property -dict {LOC BK30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}]
|
||||
set_property -dict {LOC BG29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}]
|
||||
set_property -dict {LOC BG30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}]
|
||||
set_property -dict {LOC BL35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}]
|
||||
set_property -dict {LOC BM35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}]
|
||||
set_property -dict {LOC BM34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}]
|
||||
set_property -dict {LOC BN35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}]
|
||||
set_property -dict {LOC BK34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}]
|
||||
set_property -dict {LOC BK35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}]
|
||||
set_property -dict {LOC BH32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}]
|
||||
set_property -dict {LOC BJ32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}]
|
||||
set_property -dict {LOC BM49 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}]
|
||||
set_property -dict {LOC BM50 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}]
|
||||
set_property -dict {LOC BP48 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[9]}]
|
||||
set_property -dict {LOC BP49 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[9]}]
|
||||
set_property -dict {LOC BF47 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[10]}]
|
||||
set_property -dict {LOC BF48 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[10]}]
|
||||
set_property -dict {LOC BG48 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[11]}]
|
||||
set_property -dict {LOC BG49 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[11]}]
|
||||
set_property -dict {LOC BH47 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[12]}]
|
||||
set_property -dict {LOC BJ47 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[12]}]
|
||||
set_property -dict {LOC BK48 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[13]}]
|
||||
set_property -dict {LOC BK49 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[13]}]
|
||||
set_property -dict {LOC BN46 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[14]}]
|
||||
set_property -dict {LOC BP46 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[14]}]
|
||||
set_property -dict {LOC BN42 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[15]}]
|
||||
set_property -dict {LOC BP42 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[15]}]
|
||||
set_property -dict {LOC BH54 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[16]}]
|
||||
set_property -dict {LOC BJ54 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[16]}]
|
||||
set_property -dict {LOC BJ52 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[17]}]
|
||||
set_property -dict {LOC BJ53 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[17]}]
|
||||
|
||||
# DDR4 C1
|
||||
set_property -dict {LOC BF7 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}]
|
||||
set_property -dict {LOC BK1 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}]
|
||||
set_property -dict {LOC BF6 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}]
|
||||
set_property -dict {LOC BF5 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}]
|
||||
set_property -dict {LOC BE3 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}]
|
||||
set_property -dict {LOC BE6 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}]
|
||||
set_property -dict {LOC BE5 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}]
|
||||
set_property -dict {LOC BG7 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}]
|
||||
set_property -dict {LOC BJ1 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}]
|
||||
set_property -dict {LOC BG2 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}]
|
||||
set_property -dict {LOC BJ8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}]
|
||||
set_property -dict {LOC BE4 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}]
|
||||
set_property -dict {LOC BL2 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}]
|
||||
set_property -dict {LOC BK5 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}]
|
||||
set_property -dict {LOC BK8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}]
|
||||
set_property -dict {LOC BJ4 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}]
|
||||
set_property -dict {LOC BF8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}]
|
||||
set_property -dict {LOC BG8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}]
|
||||
set_property -dict {LOC BK4 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}]
|
||||
set_property -dict {LOC BF3 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}]
|
||||
set_property -dict {LOC BF2 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}]
|
||||
set_property -dict {LOC BJ3 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c1_ck_t}]
|
||||
set_property -dict {LOC BJ2 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c1_ck_c}]
|
||||
set_property -dict {LOC BE1 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke}]
|
||||
set_property -dict {LOC BL3 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n}]
|
||||
set_property -dict {LOC BG3 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}]
|
||||
set_property -dict {LOC BH2 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt}]
|
||||
set_property -dict {LOC BH1 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}]
|
||||
set_property -dict {LOC BH12 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_c1_reset_n}]
|
||||
|
||||
set_property -dict {LOC A11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}]
|
||||
set_property -dict {LOC A10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}]
|
||||
set_property -dict {LOC A9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}]
|
||||
set_property -dict {LOC A8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}]
|
||||
set_property -dict {LOC B12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}]
|
||||
set_property -dict {LOC B10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}]
|
||||
set_property -dict {LOC C12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}]
|
||||
set_property -dict {LOC B11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}]
|
||||
set_property -dict {LOC E11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}]
|
||||
set_property -dict {LOC D11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}]
|
||||
set_property -dict {LOC E12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}]
|
||||
set_property -dict {LOC F11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}]
|
||||
set_property -dict {LOC F10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}]
|
||||
set_property -dict {LOC E9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}]
|
||||
set_property -dict {LOC F9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}]
|
||||
set_property -dict {LOC G11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}]
|
||||
set_property -dict {LOC H12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}]
|
||||
set_property -dict {LOC G13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}]
|
||||
set_property -dict {LOC H13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}]
|
||||
set_property -dict {LOC H14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}]
|
||||
set_property -dict {LOC J11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}]
|
||||
set_property -dict {LOC J12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}]
|
||||
set_property -dict {LOC J15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}]
|
||||
set_property -dict {LOC J14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}]
|
||||
set_property -dict {LOC A14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}]
|
||||
set_property -dict {LOC C15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}]
|
||||
set_property -dict {LOC A15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}]
|
||||
set_property -dict {LOC B15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}]
|
||||
set_property -dict {LOC F15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}]
|
||||
set_property -dict {LOC E14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}]
|
||||
set_property -dict {LOC F14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}]
|
||||
set_property -dict {LOC F13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}]
|
||||
set_property -dict {LOC BM3 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}]
|
||||
set_property -dict {LOC BM4 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}]
|
||||
set_property -dict {LOC BM5 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}]
|
||||
set_property -dict {LOC BL6 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}]
|
||||
set_property -dict {LOC BN4 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}]
|
||||
set_property -dict {LOC BN5 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}]
|
||||
set_property -dict {LOC BN6 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}]
|
||||
set_property -dict {LOC BN7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}]
|
||||
set_property -dict {LOC BJ9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}]
|
||||
set_property -dict {LOC BK9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}]
|
||||
set_property -dict {LOC BK10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}]
|
||||
set_property -dict {LOC BL10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}]
|
||||
set_property -dict {LOC BM9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}]
|
||||
set_property -dict {LOC BN9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}]
|
||||
set_property -dict {LOC BN10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}]
|
||||
set_property -dict {LOC BM10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}]
|
||||
set_property -dict {LOC BM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}]
|
||||
set_property -dict {LOC BM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}]
|
||||
set_property -dict {LOC BL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}]
|
||||
set_property -dict {LOC BM13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}]
|
||||
set_property -dict {LOC BN12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}]
|
||||
set_property -dict {LOC BM12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}]
|
||||
set_property -dict {LOC BP13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}]
|
||||
set_property -dict {LOC BP14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}]
|
||||
set_property -dict {LOC BJ13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}]
|
||||
set_property -dict {LOC BJ12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}]
|
||||
set_property -dict {LOC BH15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}]
|
||||
set_property -dict {LOC BH14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}]
|
||||
set_property -dict {LOC BK14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}]
|
||||
set_property -dict {LOC BK15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}]
|
||||
set_property -dict {LOC BL12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}]
|
||||
set_property -dict {LOC BL13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}]
|
||||
set_property -dict {LOC BE9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}]
|
||||
set_property -dict {LOC BE10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}]
|
||||
set_property -dict {LOC BF10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}]
|
||||
set_property -dict {LOC BE11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}]
|
||||
set_property -dict {LOC BG13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}]
|
||||
set_property -dict {LOC BG12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}]
|
||||
set_property -dict {LOC BG9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}]
|
||||
set_property -dict {LOC BG10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}]
|
||||
set_property -dict {LOC B13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}]
|
||||
set_property -dict {LOC A13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}]
|
||||
set_property -dict {LOC C10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}]
|
||||
set_property -dict {LOC C9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}]
|
||||
set_property -dict {LOC D10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}]
|
||||
set_property -dict {LOC D9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}]
|
||||
set_property -dict {LOC H10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}]
|
||||
set_property -dict {LOC G10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}]
|
||||
set_property -dict {LOC H15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}]
|
||||
set_property -dict {LOC G15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}]
|
||||
set_property -dict {LOC K14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}]
|
||||
set_property -dict {LOC K13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}]
|
||||
set_property -dict {LOC D15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}]
|
||||
set_property -dict {LOC D14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}]
|
||||
set_property -dict {LOC E13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}]
|
||||
set_property -dict {LOC D12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}]
|
||||
set_property -dict {LOC BL7 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}]
|
||||
set_property -dict {LOC BM7 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}]
|
||||
set_property -dict {LOC BP7 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}]
|
||||
set_property -dict {LOC BP6 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}]
|
||||
set_property -dict {LOC BL8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[10]}]
|
||||
set_property -dict {LOC BM8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[10]}]
|
||||
set_property -dict {LOC BP9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[11]}]
|
||||
set_property -dict {LOC BP8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[11]}]
|
||||
set_property -dict {LOC BN15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[12]}]
|
||||
set_property -dict {LOC BN14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[12]}]
|
||||
set_property -dict {LOC BP12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[13]}]
|
||||
set_property -dict {LOC BP11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[13]}]
|
||||
set_property -dict {LOC BJ14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[14]}]
|
||||
set_property -dict {LOC BK13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[14]}]
|
||||
set_property -dict {LOC BJ11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[15]}]
|
||||
set_property -dict {LOC BK11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[15]}]
|
||||
set_property -dict {LOC BF12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[16]}]
|
||||
set_property -dict {LOC BF11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[16]}]
|
||||
set_property -dict {LOC BH10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[17]}]
|
||||
set_property -dict {LOC BH9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[17]}]
|
||||
|
||||
@ -138,11 +138,14 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
|
||||
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
|
||||
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
|
||||
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
|
||||
XDC_FILES += hbm.xdc
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl
|
||||
IP_TCL_FILES += ip/eth_xcvr_gty.tcl
|
||||
IP_TCL_FILES += ip/cms.tcl
|
||||
IP_TCL_FILES += ip/hbm_0.tcl
|
||||
IP_TCL_FILES += ip/ddr4_0.tcl
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
@ -148,6 +148,17 @@ dict set params MAX_TX_SIZE "9214"
|
||||
dict set params MAX_RX_SIZE "9214"
|
||||
dict set params TX_RAM_SIZE "32768"
|
||||
dict set params RX_RAM_SIZE "131072"
|
||||
|
||||
# RAM configuration
|
||||
dict set params DDR_CH "2"
|
||||
dict set params DDR_ENABLE "1"
|
||||
dict set params AXI_DDR_ID_WIDTH "8"
|
||||
dict set params AXI_DDR_MAX_BURST_LEN "256"
|
||||
dict set params HBM_CH "32"
|
||||
dict set params HBM_ENABLE "1"
|
||||
dict set params HBM_GROUP_SIZE "32"
|
||||
dict set params AXI_HBM_ADDR_WIDTH "33"
|
||||
dict set params AXI_HBM_MAX_BURST_LEN "256"
|
||||
|
||||
# Application block configuration
|
||||
dict set params APP_ID "32'h00000000"
|
||||
@ -200,6 +211,19 @@ dict set params STAT_PCIE_ENABLE "1"
|
||||
dict set params STAT_INC_WIDTH "24"
|
||||
dict set params STAT_ID_WIDTH "12"
|
||||
|
||||
# DDR4 MIG settings
|
||||
if {[dict get $params DDR_ENABLE]} {
|
||||
set ddr4 [get_ips ddr4_0]
|
||||
|
||||
# set AXI ID width
|
||||
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
|
||||
|
||||
# extract AXI configuration
|
||||
dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4]
|
||||
dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4]
|
||||
dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1]
|
||||
}
|
||||
|
||||
# PCIe IP core settings
|
||||
set pcie [get_ips pcie4c_uscale_plus_0]
|
||||
|
||||
|
||||
@ -138,11 +138,14 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
|
||||
XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl
|
||||
XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
|
||||
XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl
|
||||
XDC_FILES += hbm.xdc
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl
|
||||
IP_TCL_FILES += ip/eth_xcvr_gty.tcl
|
||||
IP_TCL_FILES += ip/cms.tcl
|
||||
IP_TCL_FILES += ip/hbm_0.tcl
|
||||
IP_TCL_FILES += ip/ddr4_0.tcl
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
@ -148,6 +148,17 @@ dict set params MAX_TX_SIZE "9214"
|
||||
dict set params MAX_RX_SIZE "9214"
|
||||
dict set params TX_RAM_SIZE "32768"
|
||||
dict set params RX_RAM_SIZE "32768"
|
||||
|
||||
# RAM configuration
|
||||
dict set params DDR_CH "2"
|
||||
dict set params DDR_ENABLE "1"
|
||||
dict set params AXI_DDR_ID_WIDTH "8"
|
||||
dict set params AXI_DDR_MAX_BURST_LEN "256"
|
||||
dict set params HBM_CH "32"
|
||||
dict set params HBM_ENABLE "1"
|
||||
dict set params HBM_GROUP_SIZE "32"
|
||||
dict set params AXI_HBM_ADDR_WIDTH "33"
|
||||
dict set params AXI_HBM_MAX_BURST_LEN "256"
|
||||
|
||||
# Application block configuration
|
||||
dict set params APP_ID "32'h00000000"
|
||||
@ -200,6 +211,19 @@ dict set params STAT_PCIE_ENABLE "1"
|
||||
dict set params STAT_INC_WIDTH "24"
|
||||
dict set params STAT_ID_WIDTH "12"
|
||||
|
||||
# DDR4 MIG settings
|
||||
if {[dict get $params DDR_ENABLE]} {
|
||||
set ddr4 [get_ips ddr4_0]
|
||||
|
||||
# set AXI ID width
|
||||
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
|
||||
|
||||
# extract AXI configuration
|
||||
dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4]
|
||||
dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4]
|
||||
dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1]
|
||||
}
|
||||
|
||||
# PCIe IP core settings
|
||||
set pcie [get_ips pcie4c_uscale_plus_0]
|
||||
|
||||
|
||||
2
fpga/mqnic/AU280/fpga_25g/hbm.xdc
Normal file
2
fpga/mqnic/AU280/fpga_25g/hbm.xdc
Normal file
@ -0,0 +1,2 @@
|
||||
# force debug hub to use HBM APB clock to prevent CDC issues
|
||||
connect_debug_port dbg_hub/clk [get_nets */APB_0_PCLK]
|
||||
18
fpga/mqnic/AU280/fpga_25g/ip/ddr4_0.tcl
Normal file
18
fpga/mqnic/AU280/fpga_25g/ip/ddr4_0.tcl
Normal file
@ -0,0 +1,18 @@
|
||||
|
||||
create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0
|
||||
|
||||
set_property -dict [list \
|
||||
CONFIG.System_Clock {No_Buffer} \
|
||||
CONFIG.C0.DDR4_AxiSelection {true} \
|
||||
CONFIG.C0.DDR4_AxiDataWidth {512} \
|
||||
CONFIG.C0.DDR4_AxiIDWidth {8} \
|
||||
CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \
|
||||
CONFIG.C0.DDR4_TimePeriod {833} \
|
||||
CONFIG.C0.DDR4_InputClockPeriod {9996} \
|
||||
CONFIG.C0.DDR4_MemoryType {RDIMMs} \
|
||||
CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PZ-2G3} \
|
||||
CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \
|
||||
CONFIG.C0.DDR4_CasLatency {17} \
|
||||
CONFIG.C0.DDR4_CasWriteLatency {12} \
|
||||
CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV}
|
||||
] [get_ips ddr4_0]
|
||||
23
fpga/mqnic/AU280/fpga_25g/ip/hbm_0.tcl
Normal file
23
fpga/mqnic/AU280/fpga_25g/ip/hbm_0.tcl
Normal file
@ -0,0 +1,23 @@
|
||||
|
||||
create_ip -name hbm -vendor xilinx.com -library ip -module_name hbm_0
|
||||
|
||||
set_property -dict [list \
|
||||
CONFIG.USER_HBM_DENSITY {8GB} \
|
||||
CONFIG.USER_HBM_STACK {2} \
|
||||
CONFIG.USER_MC0_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC1_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC2_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC3_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC4_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC5_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC6_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC7_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC8_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC9_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC10_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC11_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC12_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC13_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC14_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC15_ENABLE_ECC_CORRECTION {true}
|
||||
] [get_ips hbm_0]
|
||||
File diff suppressed because it is too large
Load Diff
@ -122,6 +122,24 @@ module fpga_core #
|
||||
parameter TX_RAM_SIZE = 32768,
|
||||
parameter RX_RAM_SIZE = 32768,
|
||||
|
||||
// RAM configuration
|
||||
parameter DDR_CH = 2,
|
||||
parameter DDR_ENABLE = 1,
|
||||
parameter AXI_DDR_DATA_WIDTH = 512,
|
||||
parameter AXI_DDR_ADDR_WIDTH = 34,
|
||||
parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8),
|
||||
parameter AXI_DDR_ID_WIDTH = 8,
|
||||
parameter AXI_DDR_MAX_BURST_LEN = 256,
|
||||
parameter AXI_DDR_NARROW_BURST = 0,
|
||||
parameter HBM_CH = 32,
|
||||
parameter HBM_ENABLE = 1,
|
||||
parameter HBM_GROUP_SIZE = 32,
|
||||
parameter AXI_HBM_DATA_WIDTH = 256,
|
||||
parameter AXI_HBM_ADDR_WIDTH = 33,
|
||||
parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8),
|
||||
parameter AXI_HBM_ID_WIDTH = 6,
|
||||
parameter AXI_HBM_MAX_BURST_LEN = 256,
|
||||
|
||||
// Application block configuration
|
||||
parameter APP_ID = 32'h00000000,
|
||||
parameter APP_ENABLE = 0,
|
||||
@ -401,6 +419,98 @@ module fpga_core #
|
||||
input wire [15:0] qsfp1_drp_do,
|
||||
input wire qsfp1_drp_rdy,
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
input wire [DDR_CH-1:0] ddr_clk,
|
||||
input wire [DDR_CH-1:0] ddr_rst,
|
||||
|
||||
output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid,
|
||||
output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr,
|
||||
output wire [DDR_CH*8-1:0] m_axi_ddr_awlen,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_awsize,
|
||||
output wire [DDR_CH*2-1:0] m_axi_ddr_awburst,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_awlock,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_awcache,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_awprot,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_awqos,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_awvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_awready,
|
||||
output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata,
|
||||
output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_wlast,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_wvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_wready,
|
||||
input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid,
|
||||
input wire [DDR_CH*2-1:0] m_axi_ddr_bresp,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_bvalid,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_bready,
|
||||
output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid,
|
||||
output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr,
|
||||
output wire [DDR_CH*8-1:0] m_axi_ddr_arlen,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_arsize,
|
||||
output wire [DDR_CH*2-1:0] m_axi_ddr_arburst,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_arlock,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_arcache,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_arprot,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_arqos,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_arvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_arready,
|
||||
input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid,
|
||||
input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata,
|
||||
input wire [DDR_CH*2-1:0] m_axi_ddr_rresp,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_rlast,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_rvalid,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_rready,
|
||||
|
||||
input wire [DDR_CH-1:0] ddr_status,
|
||||
|
||||
/*
|
||||
* HBM
|
||||
*/
|
||||
input wire [HBM_CH-1:0] hbm_clk,
|
||||
input wire [HBM_CH-1:0] hbm_rst,
|
||||
|
||||
output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_awid,
|
||||
output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_awaddr,
|
||||
output wire [HBM_CH*8-1:0] m_axi_hbm_awlen,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_awsize,
|
||||
output wire [HBM_CH*2-1:0] m_axi_hbm_awburst,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_awlock,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_awcache,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_awprot,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_awqos,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_awvalid,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_awready,
|
||||
output wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_wdata,
|
||||
output wire [HBM_CH*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_wstrb,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_wlast,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_wvalid,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_wready,
|
||||
input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_bid,
|
||||
input wire [HBM_CH*2-1:0] m_axi_hbm_bresp,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_bvalid,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_bready,
|
||||
output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_arid,
|
||||
output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_araddr,
|
||||
output wire [HBM_CH*8-1:0] m_axi_hbm_arlen,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_arsize,
|
||||
output wire [HBM_CH*2-1:0] m_axi_hbm_arburst,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_arlock,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_arcache,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_arprot,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_arqos,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_arvalid,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_arready,
|
||||
input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_rid,
|
||||
input wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_rdata,
|
||||
input wire [HBM_CH*2-1:0] m_axi_hbm_rresp,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_rlast,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_rvalid,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_rready,
|
||||
|
||||
input wire [HBM_CH-1:0] hbm_status,
|
||||
|
||||
/*
|
||||
* QSPI flash
|
||||
*/
|
||||
@ -1059,6 +1169,40 @@ mqnic_core_pcie_us #(
|
||||
.TX_RAM_SIZE(TX_RAM_SIZE),
|
||||
.RX_RAM_SIZE(RX_RAM_SIZE),
|
||||
|
||||
// RAM configuration
|
||||
.DDR_CH(DDR_CH),
|
||||
.DDR_ENABLE(DDR_ENABLE),
|
||||
.DDR_GROUP_SIZE(1),
|
||||
.AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH),
|
||||
.AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH),
|
||||
.AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH),
|
||||
.AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH),
|
||||
.AXI_DDR_AWUSER_ENABLE(0),
|
||||
.AXI_DDR_WUSER_ENABLE(0),
|
||||
.AXI_DDR_BUSER_ENABLE(0),
|
||||
.AXI_DDR_ARUSER_ENABLE(0),
|
||||
.AXI_DDR_RUSER_ENABLE(0),
|
||||
.AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN),
|
||||
.AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST),
|
||||
.AXI_DDR_FIXED_BURST(0),
|
||||
.AXI_DDR_WRAP_BURST(1),
|
||||
.HBM_CH(HBM_CH),
|
||||
.HBM_ENABLE(HBM_ENABLE),
|
||||
.HBM_GROUP_SIZE(HBM_GROUP_SIZE),
|
||||
.AXI_HBM_DATA_WIDTH(AXI_HBM_DATA_WIDTH),
|
||||
.AXI_HBM_ADDR_WIDTH(AXI_HBM_ADDR_WIDTH),
|
||||
.AXI_HBM_STRB_WIDTH(AXI_HBM_STRB_WIDTH),
|
||||
.AXI_HBM_ID_WIDTH(AXI_HBM_ID_WIDTH),
|
||||
.AXI_HBM_AWUSER_ENABLE(0),
|
||||
.AXI_HBM_WUSER_ENABLE(0),
|
||||
.AXI_HBM_BUSER_ENABLE(0),
|
||||
.AXI_HBM_ARUSER_ENABLE(0),
|
||||
.AXI_HBM_RUSER_ENABLE(0),
|
||||
.AXI_HBM_MAX_BURST_LEN(AXI_HBM_MAX_BURST_LEN),
|
||||
.AXI_HBM_NARROW_BURST(0),
|
||||
.AXI_HBM_FIXED_BURST(0),
|
||||
.AXI_HBM_WRAP_BURST(1),
|
||||
|
||||
// Application block configuration
|
||||
.APP_ID(APP_ID),
|
||||
.APP_ENABLE(APP_ENABLE),
|
||||
@ -1336,6 +1480,108 @@ core_inst (
|
||||
|
||||
.eth_rx_status(eth_rx_status),
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
.ddr_clk(ddr_clk),
|
||||
.ddr_rst(ddr_rst),
|
||||
|
||||
.m_axi_ddr_awid(m_axi_ddr_awid),
|
||||
.m_axi_ddr_awaddr(m_axi_ddr_awaddr),
|
||||
.m_axi_ddr_awlen(m_axi_ddr_awlen),
|
||||
.m_axi_ddr_awsize(m_axi_ddr_awsize),
|
||||
.m_axi_ddr_awburst(m_axi_ddr_awburst),
|
||||
.m_axi_ddr_awlock(m_axi_ddr_awlock),
|
||||
.m_axi_ddr_awcache(m_axi_ddr_awcache),
|
||||
.m_axi_ddr_awprot(m_axi_ddr_awprot),
|
||||
.m_axi_ddr_awqos(m_axi_ddr_awqos),
|
||||
.m_axi_ddr_awuser(),
|
||||
.m_axi_ddr_awvalid(m_axi_ddr_awvalid),
|
||||
.m_axi_ddr_awready(m_axi_ddr_awready),
|
||||
.m_axi_ddr_wdata(m_axi_ddr_wdata),
|
||||
.m_axi_ddr_wstrb(m_axi_ddr_wstrb),
|
||||
.m_axi_ddr_wlast(m_axi_ddr_wlast),
|
||||
.m_axi_ddr_wuser(),
|
||||
.m_axi_ddr_wvalid(m_axi_ddr_wvalid),
|
||||
.m_axi_ddr_wready(m_axi_ddr_wready),
|
||||
.m_axi_ddr_bid(m_axi_ddr_bid),
|
||||
.m_axi_ddr_bresp(m_axi_ddr_bresp),
|
||||
.m_axi_ddr_buser(0),
|
||||
.m_axi_ddr_bvalid(m_axi_ddr_bvalid),
|
||||
.m_axi_ddr_bready(m_axi_ddr_bready),
|
||||
.m_axi_ddr_arid(m_axi_ddr_arid),
|
||||
.m_axi_ddr_araddr(m_axi_ddr_araddr),
|
||||
.m_axi_ddr_arlen(m_axi_ddr_arlen),
|
||||
.m_axi_ddr_arsize(m_axi_ddr_arsize),
|
||||
.m_axi_ddr_arburst(m_axi_ddr_arburst),
|
||||
.m_axi_ddr_arlock(m_axi_ddr_arlock),
|
||||
.m_axi_ddr_arcache(m_axi_ddr_arcache),
|
||||
.m_axi_ddr_arprot(m_axi_ddr_arprot),
|
||||
.m_axi_ddr_arqos(m_axi_ddr_arqos),
|
||||
.m_axi_ddr_aruser(),
|
||||
.m_axi_ddr_arvalid(m_axi_ddr_arvalid),
|
||||
.m_axi_ddr_arready(m_axi_ddr_arready),
|
||||
.m_axi_ddr_rid(m_axi_ddr_rid),
|
||||
.m_axi_ddr_rdata(m_axi_ddr_rdata),
|
||||
.m_axi_ddr_rresp(m_axi_ddr_rresp),
|
||||
.m_axi_ddr_rlast(m_axi_ddr_rlast),
|
||||
.m_axi_ddr_ruser(0),
|
||||
.m_axi_ddr_rvalid(m_axi_ddr_rvalid),
|
||||
.m_axi_ddr_rready(m_axi_ddr_rready),
|
||||
|
||||
.ddr_status(ddr_status),
|
||||
|
||||
/*
|
||||
* HBM
|
||||
*/
|
||||
.hbm_clk(hbm_clk),
|
||||
.hbm_rst(hbm_rst),
|
||||
|
||||
.m_axi_hbm_awid(m_axi_hbm_awid),
|
||||
.m_axi_hbm_awaddr(m_axi_hbm_awaddr),
|
||||
.m_axi_hbm_awlen(m_axi_hbm_awlen),
|
||||
.m_axi_hbm_awsize(m_axi_hbm_awsize),
|
||||
.m_axi_hbm_awburst(m_axi_hbm_awburst),
|
||||
.m_axi_hbm_awlock(m_axi_hbm_awlock),
|
||||
.m_axi_hbm_awcache(m_axi_hbm_awcache),
|
||||
.m_axi_hbm_awprot(m_axi_hbm_awprot),
|
||||
.m_axi_hbm_awqos(m_axi_hbm_awqos),
|
||||
.m_axi_hbm_awuser(),
|
||||
.m_axi_hbm_awvalid(m_axi_hbm_awvalid),
|
||||
.m_axi_hbm_awready(m_axi_hbm_awready),
|
||||
.m_axi_hbm_wdata(m_axi_hbm_wdata),
|
||||
.m_axi_hbm_wstrb(m_axi_hbm_wstrb),
|
||||
.m_axi_hbm_wlast(m_axi_hbm_wlast),
|
||||
.m_axi_hbm_wuser(),
|
||||
.m_axi_hbm_wvalid(m_axi_hbm_wvalid),
|
||||
.m_axi_hbm_wready(m_axi_hbm_wready),
|
||||
.m_axi_hbm_bid(m_axi_hbm_bid),
|
||||
.m_axi_hbm_bresp(m_axi_hbm_bresp),
|
||||
.m_axi_hbm_buser(0),
|
||||
.m_axi_hbm_bvalid(m_axi_hbm_bvalid),
|
||||
.m_axi_hbm_bready(m_axi_hbm_bready),
|
||||
.m_axi_hbm_arid(m_axi_hbm_arid),
|
||||
.m_axi_hbm_araddr(m_axi_hbm_araddr),
|
||||
.m_axi_hbm_arlen(m_axi_hbm_arlen),
|
||||
.m_axi_hbm_arsize(m_axi_hbm_arsize),
|
||||
.m_axi_hbm_arburst(m_axi_hbm_arburst),
|
||||
.m_axi_hbm_arlock(m_axi_hbm_arlock),
|
||||
.m_axi_hbm_arcache(m_axi_hbm_arcache),
|
||||
.m_axi_hbm_arprot(m_axi_hbm_arprot),
|
||||
.m_axi_hbm_arqos(m_axi_hbm_arqos),
|
||||
.m_axi_hbm_aruser(),
|
||||
.m_axi_hbm_arvalid(m_axi_hbm_arvalid),
|
||||
.m_axi_hbm_arready(m_axi_hbm_arready),
|
||||
.m_axi_hbm_rid(m_axi_hbm_rid),
|
||||
.m_axi_hbm_rdata(m_axi_hbm_rdata),
|
||||
.m_axi_hbm_rresp(m_axi_hbm_rresp),
|
||||
.m_axi_hbm_rlast(m_axi_hbm_rlast),
|
||||
.m_axi_hbm_ruser(0),
|
||||
.m_axi_hbm_rvalid(m_axi_hbm_rvalid),
|
||||
.m_axi_hbm_rready(m_axi_hbm_rready),
|
||||
|
||||
.hbm_status(hbm_status),
|
||||
|
||||
/*
|
||||
* Statistics input
|
||||
*/
|
||||
|
||||
@ -7,6 +7,7 @@ This design targets the Xilinx Alveo U50 FPGA board.
|
||||
* FPGA: xcu50-fsvh2104-2-e
|
||||
* MAC: Xilinx 100G CMAC
|
||||
* PHY: 100G CAUI-4 CMAC and internal GTY transceivers
|
||||
* RAM: 8GB HBM2
|
||||
|
||||
## How to build
|
||||
|
||||
|
||||
@ -23,9 +23,9 @@ set_operating_conditions -design_power_budget 63
|
||||
#create_clock -period 10 -name clk_100mhz_0 [get_ports clk_100mhz_0_p]
|
||||
|
||||
# 100 MHz
|
||||
#set_property -dict {LOC BB18 IOSTANDARD LVDS} [get_ports clk_100mhz_1_p]
|
||||
#set_property -dict {LOC BC18 IOSTANDARD LVDS} [get_ports clk_100mhz_1_n]
|
||||
#create_clock -period 10 -name clk_100mhz_1 [get_ports clk_100mhz_1_p]
|
||||
set_property -dict {LOC BB18 IOSTANDARD LVDS} [get_ports clk_100mhz_1_p]
|
||||
set_property -dict {LOC BC18 IOSTANDARD LVDS} [get_ports clk_100mhz_1_n]
|
||||
create_clock -period 10 -name clk_100mhz_1 [get_ports clk_100mhz_1_p]
|
||||
|
||||
# LEDs
|
||||
set_property -dict {LOC E18 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp_led_act]
|
||||
|
||||
@ -117,11 +117,13 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
|
||||
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
|
||||
XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl
|
||||
XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl
|
||||
XDC_FILES += hbm.xdc
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl
|
||||
IP_TCL_FILES += ip/cmac_usplus_0.tcl
|
||||
IP_TCL_FILES += ip/cms.tcl
|
||||
IP_TCL_FILES += ip/hbm_0.tcl
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
@ -136,6 +136,13 @@ dict set params MAX_TX_SIZE "9214"
|
||||
dict set params MAX_RX_SIZE "9214"
|
||||
dict set params TX_RAM_SIZE "131072"
|
||||
dict set params RX_RAM_SIZE "131072"
|
||||
|
||||
# RAM configuration
|
||||
dict set params HBM_CH "32"
|
||||
dict set params HBM_ENABLE "1"
|
||||
dict set params HBM_GROUP_SIZE "32"
|
||||
dict set params AXI_HBM_ADDR_WIDTH "33"
|
||||
dict set params AXI_HBM_MAX_BURST_LEN "256"
|
||||
|
||||
# Application block configuration
|
||||
dict set params APP_ID "32'h00000000"
|
||||
|
||||
2
fpga/mqnic/AU50/fpga_100g/hbm.xdc
Normal file
2
fpga/mqnic/AU50/fpga_100g/hbm.xdc
Normal file
@ -0,0 +1,2 @@
|
||||
# force debug hub to use HBM APB clock to prevent CDC issues
|
||||
connect_debug_port dbg_hub/clk [get_nets */APB_0_PCLK]
|
||||
23
fpga/mqnic/AU50/fpga_100g/ip/hbm_0.tcl
Normal file
23
fpga/mqnic/AU50/fpga_100g/ip/hbm_0.tcl
Normal file
@ -0,0 +1,23 @@
|
||||
|
||||
create_ip -name hbm -vendor xilinx.com -library ip -module_name hbm_0
|
||||
|
||||
set_property -dict [list \
|
||||
CONFIG.USER_HBM_DENSITY {8GB} \
|
||||
CONFIG.USER_HBM_STACK {2} \
|
||||
CONFIG.USER_MC0_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC1_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC2_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC3_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC4_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC5_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC6_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC7_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC8_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC9_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC10_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC11_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC12_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC13_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC14_ENABLE_ECC_CORRECTION {true} \
|
||||
CONFIG.USER_MC15_ENABLE_ECC_CORRECTION {true}
|
||||
] [get_ips hbm_0]
|
||||
File diff suppressed because it is too large
Load Diff
@ -115,6 +115,16 @@ module fpga_core #
|
||||
parameter TX_RAM_SIZE = 131072,
|
||||
parameter RX_RAM_SIZE = 131072,
|
||||
|
||||
// RAM configuration
|
||||
parameter HBM_CH = 32,
|
||||
parameter HBM_ENABLE = 1,
|
||||
parameter HBM_GROUP_SIZE = 32,
|
||||
parameter AXI_HBM_DATA_WIDTH = 256,
|
||||
parameter AXI_HBM_ADDR_WIDTH = 33,
|
||||
parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8),
|
||||
parameter AXI_HBM_ID_WIDTH = 6,
|
||||
parameter AXI_HBM_MAX_BURST_LEN = 256,
|
||||
|
||||
// Application block configuration
|
||||
parameter APP_ID = 32'h00000000,
|
||||
parameter APP_ENABLE = 0,
|
||||
@ -313,6 +323,52 @@ module fpga_core #
|
||||
|
||||
input wire qsfp_rx_status,
|
||||
|
||||
/*
|
||||
* HBM
|
||||
*/
|
||||
input wire [HBM_CH-1:0] hbm_clk,
|
||||
input wire [HBM_CH-1:0] hbm_rst,
|
||||
|
||||
output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_awid,
|
||||
output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_awaddr,
|
||||
output wire [HBM_CH*8-1:0] m_axi_hbm_awlen,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_awsize,
|
||||
output wire [HBM_CH*2-1:0] m_axi_hbm_awburst,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_awlock,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_awcache,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_awprot,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_awqos,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_awvalid,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_awready,
|
||||
output wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_wdata,
|
||||
output wire [HBM_CH*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_wstrb,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_wlast,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_wvalid,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_wready,
|
||||
input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_bid,
|
||||
input wire [HBM_CH*2-1:0] m_axi_hbm_bresp,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_bvalid,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_bready,
|
||||
output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_arid,
|
||||
output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_araddr,
|
||||
output wire [HBM_CH*8-1:0] m_axi_hbm_arlen,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_arsize,
|
||||
output wire [HBM_CH*2-1:0] m_axi_hbm_arburst,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_arlock,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_arcache,
|
||||
output wire [HBM_CH*3-1:0] m_axi_hbm_arprot,
|
||||
output wire [HBM_CH*4-1:0] m_axi_hbm_arqos,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_arvalid,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_arready,
|
||||
input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_rid,
|
||||
input wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_rdata,
|
||||
input wire [HBM_CH*2-1:0] m_axi_hbm_rresp,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_rlast,
|
||||
input wire [HBM_CH-1:0] m_axi_hbm_rvalid,
|
||||
output wire [HBM_CH-1:0] m_axi_hbm_rready,
|
||||
|
||||
input wire [HBM_CH-1:0] hbm_status,
|
||||
|
||||
/*
|
||||
* QSPI flash
|
||||
*/
|
||||
@ -769,6 +825,25 @@ mqnic_core_pcie_us #(
|
||||
.TX_RAM_SIZE(TX_RAM_SIZE),
|
||||
.RX_RAM_SIZE(RX_RAM_SIZE),
|
||||
|
||||
// RAM configuration
|
||||
.DDR_ENABLE(0),
|
||||
.HBM_CH(HBM_CH),
|
||||
.HBM_ENABLE(HBM_ENABLE),
|
||||
.HBM_GROUP_SIZE(HBM_GROUP_SIZE),
|
||||
.AXI_HBM_DATA_WIDTH(AXI_HBM_DATA_WIDTH),
|
||||
.AXI_HBM_ADDR_WIDTH(AXI_HBM_ADDR_WIDTH),
|
||||
.AXI_HBM_STRB_WIDTH(AXI_HBM_STRB_WIDTH),
|
||||
.AXI_HBM_ID_WIDTH(AXI_HBM_ID_WIDTH),
|
||||
.AXI_HBM_AWUSER_ENABLE(0),
|
||||
.AXI_HBM_WUSER_ENABLE(0),
|
||||
.AXI_HBM_BUSER_ENABLE(0),
|
||||
.AXI_HBM_ARUSER_ENABLE(0),
|
||||
.AXI_HBM_RUSER_ENABLE(0),
|
||||
.AXI_HBM_MAX_BURST_LEN(AXI_HBM_MAX_BURST_LEN),
|
||||
.AXI_HBM_NARROW_BURST(0),
|
||||
.AXI_HBM_FIXED_BURST(0),
|
||||
.AXI_HBM_WRAP_BURST(1),
|
||||
|
||||
// Application block configuration
|
||||
.APP_ID(APP_ID),
|
||||
.APP_ENABLE(APP_ENABLE),
|
||||
@ -1046,6 +1121,108 @@ core_inst (
|
||||
|
||||
.eth_rx_status(eth_rx_status),
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
.ddr_clk(0),
|
||||
.ddr_rst(0),
|
||||
|
||||
.m_axi_ddr_awid(),
|
||||
.m_axi_ddr_awaddr(),
|
||||
.m_axi_ddr_awlen(),
|
||||
.m_axi_ddr_awsize(),
|
||||
.m_axi_ddr_awburst(),
|
||||
.m_axi_ddr_awlock(),
|
||||
.m_axi_ddr_awcache(),
|
||||
.m_axi_ddr_awprot(),
|
||||
.m_axi_ddr_awqos(),
|
||||
.m_axi_ddr_awuser(),
|
||||
.m_axi_ddr_awvalid(),
|
||||
.m_axi_ddr_awready(0),
|
||||
.m_axi_ddr_wdata(),
|
||||
.m_axi_ddr_wstrb(),
|
||||
.m_axi_ddr_wlast(),
|
||||
.m_axi_ddr_wuser(),
|
||||
.m_axi_ddr_wvalid(),
|
||||
.m_axi_ddr_wready(0),
|
||||
.m_axi_ddr_bid(0),
|
||||
.m_axi_ddr_bresp(0),
|
||||
.m_axi_ddr_buser(0),
|
||||
.m_axi_ddr_bvalid(0),
|
||||
.m_axi_ddr_bready(),
|
||||
.m_axi_ddr_arid(),
|
||||
.m_axi_ddr_araddr(),
|
||||
.m_axi_ddr_arlen(),
|
||||
.m_axi_ddr_arsize(),
|
||||
.m_axi_ddr_arburst(),
|
||||
.m_axi_ddr_arlock(),
|
||||
.m_axi_ddr_arcache(),
|
||||
.m_axi_ddr_arprot(),
|
||||
.m_axi_ddr_arqos(),
|
||||
.m_axi_ddr_aruser(),
|
||||
.m_axi_ddr_arvalid(),
|
||||
.m_axi_ddr_arready(0),
|
||||
.m_axi_ddr_rid(0),
|
||||
.m_axi_ddr_rdata(0),
|
||||
.m_axi_ddr_rresp(0),
|
||||
.m_axi_ddr_rlast(0),
|
||||
.m_axi_ddr_ruser(0),
|
||||
.m_axi_ddr_rvalid(0),
|
||||
.m_axi_ddr_rready(),
|
||||
|
||||
.ddr_status(0),
|
||||
|
||||
/*
|
||||
* HBM
|
||||
*/
|
||||
.hbm_clk(hbm_clk),
|
||||
.hbm_rst(hbm_rst),
|
||||
|
||||
.m_axi_hbm_awid(m_axi_hbm_awid),
|
||||
.m_axi_hbm_awaddr(m_axi_hbm_awaddr),
|
||||
.m_axi_hbm_awlen(m_axi_hbm_awlen),
|
||||
.m_axi_hbm_awsize(m_axi_hbm_awsize),
|
||||
.m_axi_hbm_awburst(m_axi_hbm_awburst),
|
||||
.m_axi_hbm_awlock(m_axi_hbm_awlock),
|
||||
.m_axi_hbm_awcache(m_axi_hbm_awcache),
|
||||
.m_axi_hbm_awprot(m_axi_hbm_awprot),
|
||||
.m_axi_hbm_awqos(m_axi_hbm_awqos),
|
||||
.m_axi_hbm_awuser(),
|
||||
.m_axi_hbm_awvalid(m_axi_hbm_awvalid),
|
||||
.m_axi_hbm_awready(m_axi_hbm_awready),
|
||||
.m_axi_hbm_wdata(m_axi_hbm_wdata),
|
||||
.m_axi_hbm_wstrb(m_axi_hbm_wstrb),
|
||||
.m_axi_hbm_wlast(m_axi_hbm_wlast),
|
||||
.m_axi_hbm_wuser(),
|
||||
.m_axi_hbm_wvalid(m_axi_hbm_wvalid),
|
||||
.m_axi_hbm_wready(m_axi_hbm_wready),
|
||||
.m_axi_hbm_bid(m_axi_hbm_bid),
|
||||
.m_axi_hbm_bresp(m_axi_hbm_bresp),
|
||||
.m_axi_hbm_buser(0),
|
||||
.m_axi_hbm_bvalid(m_axi_hbm_bvalid),
|
||||
.m_axi_hbm_bready(m_axi_hbm_bready),
|
||||
.m_axi_hbm_arid(m_axi_hbm_arid),
|
||||
.m_axi_hbm_araddr(m_axi_hbm_araddr),
|
||||
.m_axi_hbm_arlen(m_axi_hbm_arlen),
|
||||
.m_axi_hbm_arsize(m_axi_hbm_arsize),
|
||||
.m_axi_hbm_arburst(m_axi_hbm_arburst),
|
||||
.m_axi_hbm_arlock(m_axi_hbm_arlock),
|
||||
.m_axi_hbm_arcache(m_axi_hbm_arcache),
|
||||
.m_axi_hbm_arprot(m_axi_hbm_arprot),
|
||||
.m_axi_hbm_arqos(m_axi_hbm_arqos),
|
||||
.m_axi_hbm_aruser(),
|
||||
.m_axi_hbm_arvalid(m_axi_hbm_arvalid),
|
||||
.m_axi_hbm_arready(m_axi_hbm_arready),
|
||||
.m_axi_hbm_rid(m_axi_hbm_rid),
|
||||
.m_axi_hbm_rdata(m_axi_hbm_rdata),
|
||||
.m_axi_hbm_rresp(m_axi_hbm_rresp),
|
||||
.m_axi_hbm_rlast(m_axi_hbm_rlast),
|
||||
.m_axi_hbm_ruser(0),
|
||||
.m_axi_hbm_rvalid(m_axi_hbm_rvalid),
|
||||
.m_axi_hbm_rready(m_axi_hbm_rready),
|
||||
|
||||
.hbm_status(hbm_status),
|
||||
|
||||
/*
|
||||
* Statistics input
|
||||
*/
|
||||
|
||||
@ -6,6 +6,7 @@ This design targets the Xilinx Alveo U50 FPGA board.
|
||||
|
||||
* FPGA: xcu50-fsvh2104-2-e
|
||||
* PHY: 10G BASE-R PHY IP core and internal GTY transceivers
|
||||
* RAM: 8GB HBM2
|
||||
|
||||
## How to build
|
||||
|
||||
|
||||
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Reference in New Issue
Block a user