diff --git a/docs/source/devicelist.rst b/docs/source/devicelist.rst index 2c0f643cb..bbbf77e6a 100644 --- a/docs/source/devicelist.rst +++ b/docs/source/devicelist.rst @@ -49,9 +49,9 @@ This section details PCIe form-factor targets, which interface with a separate h Nexus K35-S Gen 3 x8 2x SFP+ \- \- Nexus K3P-S Gen 3 x8 2x SFP28 4 GB DDR4 (1G x32) \- Nexus K3P-Q Gen 3 x8 2x QSFP28 8 GB DDR4 (1G x72) \- - fb2CG\@KU15P Gen 3 x16 2x QSFP28 16 GB DDR4 2400 (4x 512M x72) \- + fb2CG\@KU15P Gen 3 x16 2x QSFP28 16 GB DDR4 2666 (4x 512M x72) \- NetFPGA SUME Gen 3 x8 4x SFP+ 8 GB DDR3 1866 (2x 512M x64) \- - 250-SoC Gen 3 x16 2x QSFP28 4 GB DDR4 2400 (512M x72) \- + 250-SoC Gen 3 x16 2x QSFP28 4 GB DDR4 2666 (512M x72) \- XUP-P3R Gen 3 x16 4x QSFP28 4x DDR4 2400 DIMM (4x x72) \- DK-DEV-1SMX-H-A Gen 3 x16 2x QSFP28 8 GB DDR4 2666 (2x 512M x72) 8 GB DK-DEV-1SMC-H-A Gen 3 x16 2x QSFP28 8 GB DDR4 2666 (2x 512M x72) 16 GB @@ -62,7 +62,7 @@ This section details PCIe form-factor targets, which interface with a separate h Alveo U250 Gen 3 x16 2x QSFP28 64 GB DDR4 2400 (4x 2G x72) \- Alveo U280 Gen 3 x16 2x QSFP28 32 GB DDR4 2400 (2x 2G x72) 8 GB VCU108 Gen 3 x8 1x QSFP28 4 GB DDR4 2400 (2x 256M x80) \- - VCU118 Gen 3 x16 2x QSFP28 4 GB DDR4 2400 (2x 256M x80) \- + VCU118 Gen 3 x16 2x QSFP28 4 GB DDR4 2666 (2x 256M x80) \- VCU1525 Gen 3 x16 2x QSFP28 64 GB DDR4 2400 (4x 2G x72) \- ZCU106 Gen 3 x4 2x SFP+ 2 GB DDR4 2400 (256M x64) \- ======================= ========= ========== =============================== ===== @@ -186,7 +186,7 @@ This section details SoC targets, which interface with CPU cores on the same dev ================= ========= ========== =============================== ===== Board PCIe IF Network IF DDR HBM ================= ========= ========== =============================== ===== - ZCU102 \- 4x SFP+ 2 GB DDR4 2400 (256M x64) \- + ZCU102 \- 4x SFP+ 512 MB DDR4 2400 (256M x16) \- ZCU106 Gen 3 x4 2x SFP+ 2 GB DDR4 2400 (256M x64) \- ================= ========= ========== =============================== ===== diff --git a/fpga/mqnic/250_SoC/fpga_100g/README.md b/fpga/mqnic/250_SoC/fpga_100g/README.md index 9265883b0..9c04efda3 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/README.md +++ b/fpga/mqnic/250_SoC/fpga_100g/README.md @@ -7,6 +7,7 @@ This design targets the BittWare 250-SoC FPGA board. * FPGA: xczu19eg-ffvd1760-2-e * MAC: Xilinx 100G CMAC * PHY: 100G CAUI-4 CMAC and internal GTY transceivers +* RAM: 4 GB DDR4 2666 (512M x72) ## How to build diff --git a/fpga/mqnic/250_SoC/fpga_100g/fpga.xdc b/fpga/mqnic/250_SoC/fpga_100g/fpga.xdc index c1a2eb25c..023dd585a 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/fpga.xdc +++ b/fpga/mqnic/250_SoC/fpga_100g/fpga.xdc @@ -6,8 +6,8 @@ set_property BITSTREAM.GENERAL.COMPRESS true [current_design] # System clocks # 200 MHz (DDR 0) -set_property -dict {LOC J19 IOSTANDARD DIFF_SSTL12} [get_ports clk_200mhz_p] -set_property -dict {LOC J18 IOSTANDARD DIFF_SSTL12} [get_ports clk_200mhz_n] +set_property -dict {LOC J19 IOSTANDARD DIFF_SSTL12 ODT RTT_48} [get_ports clk_200mhz_p] +set_property -dict {LOC J18 IOSTANDARD DIFF_SSTL12 ODT RTT_48} [get_ports clk_200mhz_n] create_clock -period 5 -name clk_200mhz [get_ports clk_200mhz_p] # LEDs @@ -183,3 +183,133 @@ create_clock -period 10 -name pcie_mgt_refclk_0 [get_ports pcie_refclk_0_p] set_false_path -from [get_ports {pcie_reset_n}] set_input_delay 0 [get_ports {pcie_reset_n}] + +# DDR4 +# 5x MT40A512M16HA-075E +set_property -dict {LOC N16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[0]}] +set_property -dict {LOC H17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[1]}] +set_property -dict {LOC R18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[2]}] +set_property -dict {LOC G18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[3]}] +set_property -dict {LOC H16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[4]}] +set_property -dict {LOC M19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[5]}] +set_property -dict {LOC N19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[6]}] +set_property -dict {LOC N20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[7]}] +set_property -dict {LOC P19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[8]}] +set_property -dict {LOC N17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[9]}] +set_property -dict {LOC G16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[10]}] +set_property -dict {LOC R20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[11]}] +set_property -dict {LOC G19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[12]}] +set_property -dict {LOC P20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[13]}] +set_property -dict {LOC K18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[14]}] +set_property -dict {LOC M16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[15]}] +set_property -dict {LOC J17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[16]}] +set_property -dict {LOC L20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_ba[0]}] +set_property -dict {LOC L19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_ba[1]}] +set_property -dict {LOC L18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_bg[0]}] +set_property -dict {LOC K17 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_ck_t}] +set_property -dict {LOC K16 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_ck_c}] +set_property -dict {LOC L16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_cke}] +set_property -dict {LOC F19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_cs_n}] +set_property -dict {LOC F16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_act_n}] +set_property -dict {LOC E17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_odt}] +set_property -dict {LOC G17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_reset_n}] + +set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[0]}] +set_property -dict {LOC H22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[1]}] +set_property -dict {LOC J22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[2]}] +set_property -dict {LOC J23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[3]}] +set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[4]}] +set_property -dict {LOC K23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[5]}] +set_property -dict {LOC H24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[6]}] +set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[7]}] +set_property -dict {LOC R22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[8]}] +set_property -dict {LOC M22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[9]}] +set_property -dict {LOC P23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[10]}] +set_property -dict {LOC N24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[11]}] +set_property -dict {LOC R23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[12]}] +set_property -dict {LOC M23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[13]}] +set_property -dict {LOC P22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[14]}] +set_property -dict {LOC M24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[15]}] +set_property -dict {LOC F20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[16]}] +set_property -dict {LOC E23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[17]}] +set_property -dict {LOC E22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[18]}] +set_property -dict {LOC G24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[19]}] +set_property -dict {LOC F21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[20]}] +set_property -dict {LOC G23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[21]}] +set_property -dict {LOC G21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[22]}] +set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[23]}] +set_property -dict {LOC C16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[24]}] +set_property -dict {LOC C19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[25]}] +set_property -dict {LOC A16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[26]}] +set_property -dict {LOC A18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[27]}] +set_property -dict {LOC B16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[28]}] +set_property -dict {LOC B19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[29]}] +set_property -dict {LOC C17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[30]}] +set_property -dict {LOC A19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[31]}] +set_property -dict {LOC A21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[32]}] +set_property -dict {LOC D20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[33]}] +set_property -dict {LOC A20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[34]}] +set_property -dict {LOC C21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[35]}] +set_property -dict {LOC A23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[36]}] +set_property -dict {LOC C22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[37]}] +set_property -dict {LOC B22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[38]}] +set_property -dict {LOC B23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[39]}] +set_property -dict {LOC B24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[40]}] +set_property -dict {LOC B28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[41]}] +set_property -dict {LOC A24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[42]}] +set_property -dict {LOC A26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[43]}] +set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[44]}] +set_property -dict {LOC C27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[45]}] +set_property -dict {LOC A25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[46]}] +set_property -dict {LOC B26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[47]}] +set_property -dict {LOC D28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[48]}] +set_property -dict {LOC G27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[49]}] +set_property -dict {LOC E26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[50]}] +set_property -dict {LOC F26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[51]}] +set_property -dict {LOC D27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[52]}] +set_property -dict {LOC F28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[53]}] +set_property -dict {LOC E25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[54]}] +set_property -dict {LOC F25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[55]}] +set_property -dict {LOC J25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[56]}] +set_property -dict {LOC K28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[57]}] +set_property -dict {LOC H27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[58]}] +set_property -dict {LOC K26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[59]}] +set_property -dict {LOC H26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[60]}] +set_property -dict {LOC K27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[61]}] +set_property -dict {LOC G28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[62]}] +set_property -dict {LOC K25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[63]}] +set_property -dict {LOC M27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[64]}] +set_property -dict {LOC R26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[65]}] +set_property -dict {LOC M28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[66]}] +set_property -dict {LOC P26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[67]}] +set_property -dict {LOC N26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[68]}] +set_property -dict {LOC P28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[69]}] +set_property -dict {LOC N27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[70]}] +set_property -dict {LOC P27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[71]}] +set_property -dict {LOC K20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[0]}] +set_property -dict {LOC J20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[0]}] +set_property -dict {LOC N21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[1]}] +set_property -dict {LOC N22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[1]}] +set_property -dict {LOC F23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[2]}] +set_property -dict {LOC F24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[2]}] +set_property -dict {LOC B18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[3]}] +set_property -dict {LOC B17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[3]}] +set_property -dict {LOC C20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[4]}] +set_property -dict {LOC B21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[4]}] +set_property -dict {LOC B27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[5]}] +set_property -dict {LOC A28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[5]}] +set_property -dict {LOC E27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[6]}] +set_property -dict {LOC E28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[6]}] +set_property -dict {LOC J27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[7]}] +set_property -dict {LOC J28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[7]}] +set_property -dict {LOC P25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[8]}] +set_property -dict {LOC N25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[8]}] +set_property -dict {LOC M21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[0]}] +set_property -dict {LOC R24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[1]}] +set_property -dict {LOC H20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[2]}] +set_property -dict {LOC D18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[3]}] +set_property -dict {LOC D22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[4]}] +set_property -dict {LOC C25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[5]}] +set_property -dict {LOC H25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[6]}] +set_property -dict {LOC L25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[7]}] +set_property -dict {LOC R27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[8]}] diff --git a/fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile b/fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile index 940aae536..d52c3e3b8 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile @@ -117,6 +117,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/cmac_usplus_0.tcl IP_TCL_FILES += ip/cmac_usplus_1.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl b/fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl index b83ad613f..05c6257e2 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/250_SoC/fpga_100g/fpga/config.tcl @@ -136,6 +136,12 @@ dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "131072" dict set params RX_RAM_SIZE "131072" + +# RAM configuration +dict set params DDR_CH "1" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" # Application block configuration dict set params APP_ID "32'h00000000" @@ -187,6 +193,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/250_SoC/fpga_100g/ip/ddr4_0.tcl b/fpga/mqnic/250_SoC/fpga_100g/ip/ddr4_0.tcl new file mode 100644 index 000000000..af4b20818 --- /dev/null +++ b/fpga/mqnic/250_SoC/fpga_100g/ip/ddr4_0.tcl @@ -0,0 +1,20 @@ + +create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 + +set_property -dict [list \ + CONFIG.System_Clock {No_Buffer} \ + CONFIG.C0.DDR4_AxiSelection {true} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_AxiIDWidth {8} \ + CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ + CONFIG.C0.DDR4_TimePeriod {750} \ + CONFIG.C0.DDR4_InputClockPeriod {5000} \ + CONFIG.C0.DDR4_MemoryType {Components} \ + CONFIG.C0.DDR4_MemoryPart {MT40A512M16HA-075E} \ + CONFIG.C0.DDR4_DataWidth {72} \ + CONFIG.C0.DDR4_DataMask {NO_DM_NO_DBI} \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_CasLatency {18} \ + CONFIG.C0.DDR4_CasWriteLatency {14} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} +] [get_ips ddr4_0] diff --git a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v index b186108e3..76a761192 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v @@ -109,6 +109,15 @@ module fpga # parameter TX_RAM_SIZE = 131072, parameter RX_RAM_SIZE = 131072, + // RAM configuration + parameter DDR_CH = 1, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 32, + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -255,7 +264,25 @@ module fpga # output wire qsfp1_resetl, input wire qsfp1_modprsl, input wire qsfp1_intl, - output wire qsfp1_lpmode + output wire qsfp1_lpmode, + + /* + * DDR4 + */ + output wire [16:0] ddr4_adr, + output wire [1:0] ddr4_ba, + output wire [0:0] ddr4_bg, + output wire [0:0] ddr4_ck_t, + output wire [0:0] ddr4_ck_c, + output wire [0:0] ddr4_cke, + output wire [0:0] ddr4_cs_n, + output wire ddr4_act_n, + output wire [0:0] ddr4_odt, + output wire ddr4_reset_n, + inout wire [71:0] ddr4_dq, + inout wire [8:0] ddr4_dqs_t, + inout wire [8:0] ddr4_dqs_c, + inout wire [8:0] ddr4_dm_dbi_n ); // PTP configuration @@ -268,6 +295,9 @@ parameter PTP_SEPARATE_RX_CLOCK = 1; // Interface configuration parameter TX_TAG_WIDTH = 16; +// RAM configuration +parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8); + // Ethernet interface configuration parameter AXIS_ETH_DATA_WIDTH = 512; parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; @@ -1553,6 +1583,182 @@ assign led[1] = qsfp1_rx_status; assign led[2] = led_int[2]; assign led[3] = led_int[3]; +// DDR4 +wire [DDR_CH-1:0] ddr_clk; +wire [DDR_CH-1:0] ddr_rst; + +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr; +wire [DDR_CH*8-1:0] m_axi_ddr_awlen; +wire [DDR_CH*3-1:0] m_axi_ddr_awsize; +wire [DDR_CH*2-1:0] m_axi_ddr_awburst; +wire [DDR_CH-1:0] m_axi_ddr_awlock; +wire [DDR_CH*4-1:0] m_axi_ddr_awcache; +wire [DDR_CH*3-1:0] m_axi_ddr_awprot; +wire [DDR_CH*4-1:0] m_axi_ddr_awqos; +wire [DDR_CH-1:0] m_axi_ddr_awvalid; +wire [DDR_CH-1:0] m_axi_ddr_awready; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata; +wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb; +wire [DDR_CH-1:0] m_axi_ddr_wlast; +wire [DDR_CH-1:0] m_axi_ddr_wvalid; +wire [DDR_CH-1:0] m_axi_ddr_wready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid; +wire [DDR_CH*2-1:0] m_axi_ddr_bresp; +wire [DDR_CH-1:0] m_axi_ddr_bvalid; +wire [DDR_CH-1:0] m_axi_ddr_bready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr; +wire [DDR_CH*8-1:0] m_axi_ddr_arlen; +wire [DDR_CH*3-1:0] m_axi_ddr_arsize; +wire [DDR_CH*2-1:0] m_axi_ddr_arburst; +wire [DDR_CH-1:0] m_axi_ddr_arlock; +wire [DDR_CH*4-1:0] m_axi_ddr_arcache; +wire [DDR_CH*3-1:0] m_axi_ddr_arprot; +wire [DDR_CH*4-1:0] m_axi_ddr_arqos; +wire [DDR_CH-1:0] m_axi_ddr_arvalid; +wire [DDR_CH-1:0] m_axi_ddr_arready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata; +wire [DDR_CH*2-1:0] m_axi_ddr_rresp; +wire [DDR_CH-1:0] m_axi_ddr_rlast; +wire [DDR_CH-1:0] m_axi_ddr_rvalid; +wire [DDR_CH-1:0] m_axi_ddr_rready; + +wire [DDR_CH-1:0] ddr_status; + +generate + +if (DDR_ENABLE && DDR_CH > 0) begin + +ddr4_0 ddr4_inst ( + .c0_sys_clk_i(clk_200mhz_ibufg), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[0 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_adr), + .c0_ddr4_ba(ddr4_ba), + .c0_ddr4_cke(ddr4_cke), + .c0_ddr4_cs_n(ddr4_cs_n), + .c0_ddr4_dq(ddr4_dq), + .c0_ddr4_dqs_t(ddr4_dqs_t), + .c0_ddr4_dqs_c(ddr4_dqs_c), + .c0_ddr4_dm_dbi_n(ddr4_dm_dbi_n), + .c0_ddr4_odt(ddr4_odt), + .c0_ddr4_bg(ddr4_bg), + .c0_ddr4_reset_n(ddr4_reset_n), + .c0_ddr4_act_n(ddr4_act_n), + .c0_ddr4_ck_t(ddr4_ck_t), + .c0_ddr4_ck_c(ddr4_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[0 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[0 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_adr = {17{1'bz}}; +assign ddr4_ba = {2{1'bz}}; +assign ddr4_bg = {1{1'bz}}; +assign ddr4_cke = 1'bz; +assign ddr4_cs_n = 1'bz; +assign ddr4_act_n = 1'bz; +assign ddr4_odt = 1'bz; +assign ddr4_reset_n = 1'b0; +assign ddr4_dq = {72{1'bz}}; +assign ddr4_dqs_t = {9{1'bz}}; +assign ddr4_dqs_c = {9{1'bz}}; +assign ddr4_dm_dbi_n = {9{1'bz}}; + +OBUFTDS ddr4_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_ck_t), + .OB(ddr4_ck_c) +); + +assign ddr_clk = 0; +assign ddr_rst = 0; + +assign m_axi_ddr_awready = 0; +assign m_axi_ddr_wready = 0; +assign m_axi_ddr_bid = 0; +assign m_axi_ddr_bresp = 0; +assign m_axi_ddr_bvalid = 0; +assign m_axi_ddr_arready = 0; +assign m_axi_ddr_rid = 0; +assign m_axi_ddr_rdata = 0; +assign m_axi_ddr_rresp = 0; +assign m_axi_ddr_rlast = 0; +assign m_axi_ddr_rvalid = 0; + +assign ddr_status = 0; + +end + +endgenerate + fpga_core #( // FW and board IDs .FPGA_ID(FPGA_ID), @@ -1627,6 +1833,16 @@ fpga_core #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1871,7 +2087,53 @@ core_inst ( .qsfp1_modprsl(qsfp1_modprsl_int), .qsfp1_resetl(qsfp1_resetl), .qsfp1_intl(qsfp1_intl_int), - .qsfp1_lpmode(qsfp1_lpmode) + .qsfp1_lpmode(qsfp1_lpmode), + + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status) ); endmodule diff --git a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v index baaaf4347..ad45c722a 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v @@ -115,6 +115,16 @@ module fpga_core # parameter TX_RAM_SIZE = 131072, parameter RX_RAM_SIZE = 131072, + // RAM configuration + parameter DDR_CH = 1, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 32, + parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -373,7 +383,53 @@ module fpga_core # output wire qsfp1_resetl, input wire qsfp1_modprsl, input wire qsfp1_intl, - output wire qsfp1_lpmode + output wire qsfp1_lpmode, + + /* + * DDR + */ + input wire [DDR_CH-1:0] ddr_clk, + input wire [DDR_CH-1:0] ddr_rst, + + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, + output wire [DDR_CH-1:0] m_axi_ddr_awlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, + output wire [DDR_CH-1:0] m_axi_ddr_awvalid, + input wire [DDR_CH-1:0] m_axi_ddr_awready, + output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, + output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, + output wire [DDR_CH-1:0] m_axi_ddr_wlast, + output wire [DDR_CH-1:0] m_axi_ddr_wvalid, + input wire [DDR_CH-1:0] m_axi_ddr_wready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, + input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, + input wire [DDR_CH-1:0] m_axi_ddr_bvalid, + output wire [DDR_CH-1:0] m_axi_ddr_bready, + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, + output wire [DDR_CH-1:0] m_axi_ddr_arlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, + output wire [DDR_CH-1:0] m_axi_ddr_arvalid, + input wire [DDR_CH-1:0] m_axi_ddr_arready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, + input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, + input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, + input wire [DDR_CH-1:0] m_axi_ddr_rlast, + input wire [DDR_CH-1:0] m_axi_ddr_rvalid, + output wire [DDR_CH-1:0] m_axi_ddr_rready, + + input wire [DDR_CH-1:0] ddr_status ); parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF; @@ -826,6 +882,25 @@ mqnic_core_pcie_us #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .DDR_GROUP_SIZE(1), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_AWUSER_ENABLE(0), + .AXI_DDR_WUSER_ENABLE(0), + .AXI_DDR_BUSER_ENABLE(0), + .AXI_DDR_ARUSER_ENABLE(0), + .AXI_DDR_RUSER_ENABLE(0), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + .AXI_DDR_FIXED_BURST(0), + .AXI_DDR_WRAP_BURST(1), + .HBM_ENABLE(0), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1103,6 +1178,108 @@ core_inst ( .eth_rx_status(eth_rx_status), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awuser(), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wuser(), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_buser(0), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_aruser(), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_ruser(0), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + + /* + * HBM + */ + .hbm_clk(0), + .hbm_rst(0), + + .m_axi_hbm_awid(), + .m_axi_hbm_awaddr(), + .m_axi_hbm_awlen(), + .m_axi_hbm_awsize(), + .m_axi_hbm_awburst(), + .m_axi_hbm_awlock(), + .m_axi_hbm_awcache(), + .m_axi_hbm_awprot(), + .m_axi_hbm_awqos(), + .m_axi_hbm_awuser(), + .m_axi_hbm_awvalid(), + .m_axi_hbm_awready(0), + .m_axi_hbm_wdata(), + .m_axi_hbm_wstrb(), + .m_axi_hbm_wlast(), + .m_axi_hbm_wuser(), + .m_axi_hbm_wvalid(), + .m_axi_hbm_wready(0), + .m_axi_hbm_bid(0), + .m_axi_hbm_bresp(0), + .m_axi_hbm_buser(0), + .m_axi_hbm_bvalid(0), + .m_axi_hbm_bready(), + .m_axi_hbm_arid(), + .m_axi_hbm_araddr(), + .m_axi_hbm_arlen(), + .m_axi_hbm_arsize(), + .m_axi_hbm_arburst(), + .m_axi_hbm_arlock(), + .m_axi_hbm_arcache(), + .m_axi_hbm_arprot(), + .m_axi_hbm_arqos(), + .m_axi_hbm_aruser(), + .m_axi_hbm_arvalid(), + .m_axi_hbm_arready(0), + .m_axi_hbm_rid(0), + .m_axi_hbm_rdata(0), + .m_axi_hbm_rresp(0), + .m_axi_hbm_rlast(0), + .m_axi_hbm_ruser(0), + .m_axi_hbm_rvalid(0), + .m_axi_hbm_rready(), + + .hbm_status(0), + /* * Statistics input */ diff --git a/fpga/mqnic/250_SoC/fpga_25g/README.md b/fpga/mqnic/250_SoC/fpga_25g/README.md index 778c6fa49..bcd40ddc9 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/README.md +++ b/fpga/mqnic/250_SoC/fpga_25g/README.md @@ -6,6 +6,7 @@ This design targets the BittWare 250-SoC FPGA board. * FPGA: xczu19eg-ffvd1760-2-e * PHY: 10G BASE-R PHY IP core and internal GTY transceiver +* RAM: 4 GB DDR4 2666 (512M x72) ## How to build diff --git a/fpga/mqnic/250_SoC/fpga_25g/fpga.xdc b/fpga/mqnic/250_SoC/fpga_25g/fpga.xdc index c71314c9b..b9483af66 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/fpga.xdc +++ b/fpga/mqnic/250_SoC/fpga_25g/fpga.xdc @@ -6,8 +6,8 @@ set_property BITSTREAM.GENERAL.COMPRESS true [current_design] # System clocks # 200 MHz (DDR 0) -set_property -dict {LOC J19 IOSTANDARD DIFF_SSTL12} [get_ports clk_200mhz_p] -set_property -dict {LOC J18 IOSTANDARD DIFF_SSTL12} [get_ports clk_200mhz_n] +set_property -dict {LOC J19 IOSTANDARD DIFF_SSTL12 ODT RTT_48} [get_ports clk_200mhz_p] +set_property -dict {LOC J18 IOSTANDARD DIFF_SSTL12 ODT RTT_48} [get_ports clk_200mhz_n] create_clock -period 5 -name clk_200mhz [get_ports clk_200mhz_p] # LEDs @@ -183,3 +183,133 @@ create_clock -period 10 -name pcie_mgt_refclk_0 [get_ports pcie_refclk_0_p] set_false_path -from [get_ports {pcie_reset_n}] set_input_delay 0 [get_ports {pcie_reset_n}] + +# DDR4 +# 5x MT40A512M16HA-075E +set_property -dict {LOC N16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[0]}] +set_property -dict {LOC H17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[1]}] +set_property -dict {LOC R18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[2]}] +set_property -dict {LOC G18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[3]}] +set_property -dict {LOC H16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[4]}] +set_property -dict {LOC M19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[5]}] +set_property -dict {LOC N19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[6]}] +set_property -dict {LOC N20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[7]}] +set_property -dict {LOC P19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[8]}] +set_property -dict {LOC N17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[9]}] +set_property -dict {LOC G16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[10]}] +set_property -dict {LOC R20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[11]}] +set_property -dict {LOC G19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[12]}] +set_property -dict {LOC P20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[13]}] +set_property -dict {LOC K18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[14]}] +set_property -dict {LOC M16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[15]}] +set_property -dict {LOC J17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[16]}] +set_property -dict {LOC L20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_ba[0]}] +set_property -dict {LOC L19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_ba[1]}] +set_property -dict {LOC L18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_bg[0]}] +set_property -dict {LOC K17 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_ck_t}] +set_property -dict {LOC K16 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_ck_c}] +set_property -dict {LOC L16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_cke}] +set_property -dict {LOC F19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_cs_n}] +set_property -dict {LOC F16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_act_n}] +set_property -dict {LOC E17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_odt}] +set_property -dict {LOC G17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_reset_n}] + +set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[0]}] +set_property -dict {LOC H22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[1]}] +set_property -dict {LOC J22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[2]}] +set_property -dict {LOC J23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[3]}] +set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[4]}] +set_property -dict {LOC K23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[5]}] +set_property -dict {LOC H24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[6]}] +set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[7]}] +set_property -dict {LOC R22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[8]}] +set_property -dict {LOC M22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[9]}] +set_property -dict {LOC P23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[10]}] +set_property -dict {LOC N24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[11]}] +set_property -dict {LOC R23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[12]}] +set_property -dict {LOC M23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[13]}] +set_property -dict {LOC P22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[14]}] +set_property -dict {LOC M24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[15]}] +set_property -dict {LOC F20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[16]}] +set_property -dict {LOC E23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[17]}] +set_property -dict {LOC E22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[18]}] +set_property -dict {LOC G24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[19]}] +set_property -dict {LOC F21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[20]}] +set_property -dict {LOC G23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[21]}] +set_property -dict {LOC G21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[22]}] +set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[23]}] +set_property -dict {LOC C16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[24]}] +set_property -dict {LOC C19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[25]}] +set_property -dict {LOC A16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[26]}] +set_property -dict {LOC A18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[27]}] +set_property -dict {LOC B16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[28]}] +set_property -dict {LOC B19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[29]}] +set_property -dict {LOC C17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[30]}] +set_property -dict {LOC A19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[31]}] +set_property -dict {LOC A21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[32]}] +set_property -dict {LOC D20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[33]}] +set_property -dict {LOC A20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[34]}] +set_property -dict {LOC C21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[35]}] +set_property -dict {LOC A23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[36]}] +set_property -dict {LOC C22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[37]}] +set_property -dict {LOC B22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[38]}] +set_property -dict {LOC B23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[39]}] +set_property -dict {LOC B24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[40]}] +set_property -dict {LOC B28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[41]}] +set_property -dict {LOC A24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[42]}] +set_property -dict {LOC A26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[43]}] +set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[44]}] +set_property -dict {LOC C27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[45]}] +set_property -dict {LOC A25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[46]}] +set_property -dict {LOC B26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[47]}] +set_property -dict {LOC D28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[48]}] +set_property -dict {LOC G27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[49]}] +set_property -dict {LOC E26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[50]}] +set_property -dict {LOC F26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[51]}] +set_property -dict {LOC D27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[52]}] +set_property -dict {LOC F28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[53]}] +set_property -dict {LOC E25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[54]}] +set_property -dict {LOC F25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[55]}] +set_property -dict {LOC J25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[56]}] +set_property -dict {LOC K28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[57]}] +set_property -dict {LOC H27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[58]}] +set_property -dict {LOC K26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[59]}] +set_property -dict {LOC H26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[60]}] +set_property -dict {LOC K27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[61]}] +set_property -dict {LOC G28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[62]}] +set_property -dict {LOC K25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[63]}] +set_property -dict {LOC M27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[64]}] +set_property -dict {LOC R26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[65]}] +set_property -dict {LOC M28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[66]}] +set_property -dict {LOC P26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[67]}] +set_property -dict {LOC N26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[68]}] +set_property -dict {LOC P28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[69]}] +set_property -dict {LOC N27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[70]}] +set_property -dict {LOC P27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[71]}] +set_property -dict {LOC K20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[0]}] +set_property -dict {LOC J20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[0]}] +set_property -dict {LOC N21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[1]}] +set_property -dict {LOC N22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[1]}] +set_property -dict {LOC F23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[2]}] +set_property -dict {LOC F24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[2]}] +set_property -dict {LOC B18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[3]}] +set_property -dict {LOC B17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[3]}] +set_property -dict {LOC C20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[4]}] +set_property -dict {LOC B21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[4]}] +set_property -dict {LOC B27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[5]}] +set_property -dict {LOC A28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[5]}] +set_property -dict {LOC E27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[6]}] +set_property -dict {LOC E28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[6]}] +set_property -dict {LOC J27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[7]}] +set_property -dict {LOC J28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[7]}] +set_property -dict {LOC P25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[8]}] +set_property -dict {LOC N25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[8]}] +set_property -dict {LOC M21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[0]}] +set_property -dict {LOC R24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[1]}] +set_property -dict {LOC H20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[2]}] +set_property -dict {LOC D18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[3]}] +set_property -dict {LOC D22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[4]}] +set_property -dict {LOC C25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[5]}] +set_property -dict {LOC H25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[6]}] +set_property -dict {LOC L25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[7]}] +set_property -dict {LOC R27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[8]}] diff --git a/fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile b/fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile index b6200a0c0..078ad2056 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile @@ -137,6 +137,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl b/fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl index abfa02265..3929a6827 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/250_SoC/fpga_25g/fpga/config.tcl @@ -148,6 +148,12 @@ dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" dict set params RX_RAM_SIZE "131072" + +# RAM configuration +dict set params DDR_CH "1" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" # Application block configuration dict set params APP_ID "32'h00000000" @@ -200,6 +206,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile index b6200a0c0..078ad2056 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile @@ -137,6 +137,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl index f93942eaa..014623dc1 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/config.tcl @@ -148,6 +148,12 @@ dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" dict set params RX_RAM_SIZE "32768" + +# RAM configuration +dict set params DDR_CH "1" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" # Application block configuration dict set params APP_ID "32'h00000000" @@ -200,6 +206,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/250_SoC/fpga_25g/ip/ddr4_0.tcl b/fpga/mqnic/250_SoC/fpga_25g/ip/ddr4_0.tcl new file mode 100644 index 000000000..af4b20818 --- /dev/null +++ b/fpga/mqnic/250_SoC/fpga_25g/ip/ddr4_0.tcl @@ -0,0 +1,20 @@ + +create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 + +set_property -dict [list \ + CONFIG.System_Clock {No_Buffer} \ + CONFIG.C0.DDR4_AxiSelection {true} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_AxiIDWidth {8} \ + CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ + CONFIG.C0.DDR4_TimePeriod {750} \ + CONFIG.C0.DDR4_InputClockPeriod {5000} \ + CONFIG.C0.DDR4_MemoryType {Components} \ + CONFIG.C0.DDR4_MemoryPart {MT40A512M16HA-075E} \ + CONFIG.C0.DDR4_DataWidth {72} \ + CONFIG.C0.DDR4_DataMask {NO_DM_NO_DBI} \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_CasLatency {18} \ + CONFIG.C0.DDR4_CasWriteLatency {14} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} +] [get_ips ddr4_0] diff --git a/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v b/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v index af13e1e5f..6e8671d40 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v @@ -112,6 +112,15 @@ module fpga # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // RAM configuration + parameter DDR_CH = 1, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 32, + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -259,7 +268,25 @@ module fpga # output wire qsfp1_resetl, input wire qsfp1_modprsl, input wire qsfp1_intl, - output wire qsfp1_lpmode + output wire qsfp1_lpmode, + + /* + * DDR4 + */ + output wire [16:0] ddr4_adr, + output wire [1:0] ddr4_ba, + output wire [0:0] ddr4_bg, + output wire [0:0] ddr4_ck_t, + output wire [0:0] ddr4_ck_c, + output wire [0:0] ddr4_cke, + output wire [0:0] ddr4_cs_n, + output wire ddr4_act_n, + output wire [0:0] ddr4_odt, + output wire ddr4_reset_n, + inout wire [71:0] ddr4_dq, + inout wire [8:0] ddr4_dqs_t, + inout wire [8:0] ddr4_dqs_c, + inout wire [8:0] ddr4_dm_dbi_n ); // PTP configuration @@ -273,6 +300,9 @@ parameter IF_PTP_PERIOD_FNS = 16'h6666; // Interface configuration parameter TX_TAG_WIDTH = 16; +// RAM configuration +parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8); + // Ethernet interface configuration parameter XGMII_DATA_WIDTH = 64; parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8; @@ -1150,6 +1180,182 @@ assign ptp_clk = qsfp0_mgt_refclk_bufg; assign ptp_rst = qsfp0_rst; assign ptp_sample_clk = clk_125mhz_int; +// DDR4 +wire [DDR_CH-1:0] ddr_clk; +wire [DDR_CH-1:0] ddr_rst; + +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr; +wire [DDR_CH*8-1:0] m_axi_ddr_awlen; +wire [DDR_CH*3-1:0] m_axi_ddr_awsize; +wire [DDR_CH*2-1:0] m_axi_ddr_awburst; +wire [DDR_CH-1:0] m_axi_ddr_awlock; +wire [DDR_CH*4-1:0] m_axi_ddr_awcache; +wire [DDR_CH*3-1:0] m_axi_ddr_awprot; +wire [DDR_CH*4-1:0] m_axi_ddr_awqos; +wire [DDR_CH-1:0] m_axi_ddr_awvalid; +wire [DDR_CH-1:0] m_axi_ddr_awready; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata; +wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb; +wire [DDR_CH-1:0] m_axi_ddr_wlast; +wire [DDR_CH-1:0] m_axi_ddr_wvalid; +wire [DDR_CH-1:0] m_axi_ddr_wready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid; +wire [DDR_CH*2-1:0] m_axi_ddr_bresp; +wire [DDR_CH-1:0] m_axi_ddr_bvalid; +wire [DDR_CH-1:0] m_axi_ddr_bready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr; +wire [DDR_CH*8-1:0] m_axi_ddr_arlen; +wire [DDR_CH*3-1:0] m_axi_ddr_arsize; +wire [DDR_CH*2-1:0] m_axi_ddr_arburst; +wire [DDR_CH-1:0] m_axi_ddr_arlock; +wire [DDR_CH*4-1:0] m_axi_ddr_arcache; +wire [DDR_CH*3-1:0] m_axi_ddr_arprot; +wire [DDR_CH*4-1:0] m_axi_ddr_arqos; +wire [DDR_CH-1:0] m_axi_ddr_arvalid; +wire [DDR_CH-1:0] m_axi_ddr_arready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata; +wire [DDR_CH*2-1:0] m_axi_ddr_rresp; +wire [DDR_CH-1:0] m_axi_ddr_rlast; +wire [DDR_CH-1:0] m_axi_ddr_rvalid; +wire [DDR_CH-1:0] m_axi_ddr_rready; + +wire [DDR_CH-1:0] ddr_status; + +generate + +if (DDR_ENABLE && DDR_CH > 0) begin + +ddr4_0 ddr4_inst ( + .c0_sys_clk_i(clk_200mhz_ibufg), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[0 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_adr), + .c0_ddr4_ba(ddr4_ba), + .c0_ddr4_cke(ddr4_cke), + .c0_ddr4_cs_n(ddr4_cs_n), + .c0_ddr4_dq(ddr4_dq), + .c0_ddr4_dqs_t(ddr4_dqs_t), + .c0_ddr4_dqs_c(ddr4_dqs_c), + .c0_ddr4_dm_dbi_n(ddr4_dm_dbi_n), + .c0_ddr4_odt(ddr4_odt), + .c0_ddr4_bg(ddr4_bg), + .c0_ddr4_reset_n(ddr4_reset_n), + .c0_ddr4_act_n(ddr4_act_n), + .c0_ddr4_ck_t(ddr4_ck_t), + .c0_ddr4_ck_c(ddr4_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[0 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[0 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_adr = {17{1'bz}}; +assign ddr4_ba = {2{1'bz}}; +assign ddr4_bg = {1{1'bz}}; +assign ddr4_cke = 1'bz; +assign ddr4_cs_n = 1'bz; +assign ddr4_act_n = 1'bz; +assign ddr4_odt = 1'bz; +assign ddr4_reset_n = 1'b0; +assign ddr4_dq = {72{1'bz}}; +assign ddr4_dqs_t = {9{1'bz}}; +assign ddr4_dqs_c = {9{1'bz}}; +assign ddr4_dm_dbi_n = {9{1'bz}}; + +OBUFTDS ddr4_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_ck_t), + .OB(ddr4_ck_c) +); + +assign ddr_clk = 0; +assign ddr_rst = 0; + +assign m_axi_ddr_awready = 0; +assign m_axi_ddr_wready = 0; +assign m_axi_ddr_bid = 0; +assign m_axi_ddr_bresp = 0; +assign m_axi_ddr_bvalid = 0; +assign m_axi_ddr_arready = 0; +assign m_axi_ddr_rid = 0; +assign m_axi_ddr_rdata = 0; +assign m_axi_ddr_rresp = 0; +assign m_axi_ddr_rlast = 0; +assign m_axi_ddr_rvalid = 0; + +assign ddr_status = 0; + +end + +endgenerate + fpga_core #( // FW and board IDs .FPGA_ID(FPGA_ID), @@ -1226,6 +1432,16 @@ fpga_core #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1540,7 +1756,53 @@ core_inst ( .qsfp1_modprsl(qsfp1_modprsl_int), .qsfp1_resetl(qsfp1_resetl), .qsfp1_intl(qsfp1_intl_int), - .qsfp1_lpmode(qsfp1_lpmode) + .qsfp1_lpmode(qsfp1_lpmode), + + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status) ); endmodule diff --git a/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v index 361ca213a..be3e61657 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v @@ -122,6 +122,16 @@ module fpga_core # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // RAM configuration + parameter DDR_CH = 1, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 32, + parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -438,7 +448,53 @@ module fpga_core # output wire qsfp1_resetl, input wire qsfp1_modprsl, input wire qsfp1_intl, - output wire qsfp1_lpmode + output wire qsfp1_lpmode, + + /* + * DDR + */ + input wire [DDR_CH-1:0] ddr_clk, + input wire [DDR_CH-1:0] ddr_rst, + + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, + output wire [DDR_CH-1:0] m_axi_ddr_awlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, + output wire [DDR_CH-1:0] m_axi_ddr_awvalid, + input wire [DDR_CH-1:0] m_axi_ddr_awready, + output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, + output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, + output wire [DDR_CH-1:0] m_axi_ddr_wlast, + output wire [DDR_CH-1:0] m_axi_ddr_wvalid, + input wire [DDR_CH-1:0] m_axi_ddr_wready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, + input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, + input wire [DDR_CH-1:0] m_axi_ddr_bvalid, + output wire [DDR_CH-1:0] m_axi_ddr_bready, + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, + output wire [DDR_CH-1:0] m_axi_ddr_arlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, + output wire [DDR_CH-1:0] m_axi_ddr_arvalid, + input wire [DDR_CH-1:0] m_axi_ddr_arready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, + input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, + input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, + input wire [DDR_CH-1:0] m_axi_ddr_rlast, + input wire [DDR_CH-1:0] m_axi_ddr_rvalid, + output wire [DDR_CH-1:0] m_axi_ddr_rready, + + input wire [DDR_CH-1:0] ddr_status ); parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF; @@ -1093,6 +1149,25 @@ mqnic_core_pcie_us #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .DDR_GROUP_SIZE(1), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_AWUSER_ENABLE(0), + .AXI_DDR_WUSER_ENABLE(0), + .AXI_DDR_BUSER_ENABLE(0), + .AXI_DDR_ARUSER_ENABLE(0), + .AXI_DDR_RUSER_ENABLE(0), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + .AXI_DDR_FIXED_BURST(0), + .AXI_DDR_WRAP_BURST(1), + .HBM_ENABLE(0), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1370,6 +1445,108 @@ core_inst ( .eth_rx_status(eth_rx_status), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awuser(), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wuser(), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_buser(0), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_aruser(), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_ruser(0), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + + /* + * HBM + */ + .hbm_clk(0), + .hbm_rst(0), + + .m_axi_hbm_awid(), + .m_axi_hbm_awaddr(), + .m_axi_hbm_awlen(), + .m_axi_hbm_awsize(), + .m_axi_hbm_awburst(), + .m_axi_hbm_awlock(), + .m_axi_hbm_awcache(), + .m_axi_hbm_awprot(), + .m_axi_hbm_awqos(), + .m_axi_hbm_awuser(), + .m_axi_hbm_awvalid(), + .m_axi_hbm_awready(0), + .m_axi_hbm_wdata(), + .m_axi_hbm_wstrb(), + .m_axi_hbm_wlast(), + .m_axi_hbm_wuser(), + .m_axi_hbm_wvalid(), + .m_axi_hbm_wready(0), + .m_axi_hbm_bid(0), + .m_axi_hbm_bresp(0), + .m_axi_hbm_buser(0), + .m_axi_hbm_bvalid(0), + .m_axi_hbm_bready(), + .m_axi_hbm_arid(), + .m_axi_hbm_araddr(), + .m_axi_hbm_arlen(), + .m_axi_hbm_arsize(), + .m_axi_hbm_arburst(), + .m_axi_hbm_arlock(), + .m_axi_hbm_arcache(), + .m_axi_hbm_arprot(), + .m_axi_hbm_arqos(), + .m_axi_hbm_aruser(), + .m_axi_hbm_arvalid(), + .m_axi_hbm_arready(0), + .m_axi_hbm_rid(0), + .m_axi_hbm_rdata(0), + .m_axi_hbm_rresp(0), + .m_axi_hbm_rlast(0), + .m_axi_hbm_ruser(0), + .m_axi_hbm_rvalid(0), + .m_axi_hbm_rready(), + + .hbm_status(0), + /* * Statistics input */ diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/README.md b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/README.md index 1c718d7af..407bf7010 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/README.md +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/README.md @@ -7,6 +7,7 @@ This design targets the Alpha Data ADM-PCIE-9V3 FPGA board. * FPGA: xcvu3p-ffvc1517-2-i * MAC: Xilinx 100G CMAC * PHY: 100G CAUI-4 CMAC and internal GTY transceivers +* RAM: 16 GB DDR4 2400 (2x 1G x72) ## How to build diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga.xdc b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga.xdc index c12dc8b4a..efcc0aebe 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga.xdc +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga.xdc @@ -17,6 +17,16 @@ set_property -dict {LOC AP26 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports set_property -dict {LOC AP27 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports clk_300mhz_n] create_clock -period 3.333 -name clk_300mhz [get_ports clk_300mhz_p] +# 300 MHz memory clock (C0) +set_property -dict {LOC G31 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports mem_clk_300mhz_0_p] +set_property -dict {LOC G32 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports mem_clk_300mhz_0_n] +# create_clock -period 3.333 -name mem_clk_300mhz_0 [get_ports mem_clk_300mhz_0_p] + +# 300 MHz memory clock (C1) +set_property -dict {LOC AN25 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports mem_clk_300mhz_1_p] +set_property -dict {LOC AN26 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports mem_clk_300mhz_1_n] +# create_clock -period 3.333 -name mem_clk_300mhz_1 [get_ports mem_clk_300mhz_1_p] + # LEDs set_property -dict {LOC AT27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {user_led_g[0]}] set_property -dict {LOC AU27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {user_led_g[1]}] @@ -193,6 +203,282 @@ create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_1_p] set_false_path -from [get_ports {perst_0}] set_input_delay 0 [get_ports {perst_0}] +# DDR4 C0 +# 5x K4A8G085WB-RC +set_property -dict {LOC F9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}] +set_property -dict {LOC G9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}] +set_property -dict {LOC G11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}] +set_property -dict {LOC D11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}] +set_property -dict {LOC E12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}] +set_property -dict {LOC G10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}] +set_property -dict {LOC F10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}] +set_property -dict {LOC J9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}] +set_property -dict {LOC J8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}] +set_property -dict {LOC F12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}] +set_property -dict {LOC D9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}] +set_property -dict {LOC H11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}] +set_property -dict {LOC E8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}] +set_property -dict {LOC J11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}] +set_property -dict {LOC C9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}] +set_property -dict {LOC B11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}] +set_property -dict {LOC K12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}] +# set_property -dict {LOC H9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[17]}] +set_property -dict {LOC F8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}] +set_property -dict {LOC H8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}] +set_property -dict {LOC D10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}] +set_property -dict {LOC E11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}] +# set_property -dict {LOC B10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_c[0]}] +# set_property -dict {LOC C11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_c[1]}] +# set_property -dict {LOC A9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_c[2]}] +set_property -dict {LOC H12 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t}] +set_property -dict {LOC G12 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c}] +set_property -dict {LOC B9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke}] +set_property -dict {LOC E10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n}] +set_property -dict {LOC C12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}] +set_property -dict {LOC A10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt}] +set_property -dict {LOC G7 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}] +set_property -dict {LOC F7 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_reset_n}] +set_property -dict {LOC H7 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_alert_n}] +set_property -dict {LOC J10 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_ten}] + +set_property -dict {LOC L10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}] +set_property -dict {LOC L9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}] +set_property -dict {LOC N9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}] +set_property -dict {LOC M9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}] +set_property -dict {LOC M10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}] +set_property -dict {LOC K11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}] +set_property -dict {LOC M11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}] +set_property -dict {LOC K10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}] +set_property -dict {LOC L17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}] +set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}] +set_property -dict {LOC M15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}] +set_property -dict {LOC M17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}] +set_property -dict {LOC M14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}] +set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}] +set_property -dict {LOC N16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}] +set_property -dict {LOC N17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}] +set_property -dict {LOC F15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}] +set_property -dict {LOC E16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}] +set_property -dict {LOC F14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}] +set_property -dict {LOC E17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}] +set_property -dict {LOC G16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}] +set_property -dict {LOC F17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}] +set_property -dict {LOC E15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}] +set_property -dict {LOC G17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}] +set_property -dict {LOC A17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}] +set_property -dict {LOC C16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}] +set_property -dict {LOC B16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}] +set_property -dict {LOC A14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}] +set_property -dict {LOC B17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}] +set_property -dict {LOC B14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}] +set_property -dict {LOC D16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}] +set_property -dict {LOC D15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}] +set_property -dict {LOC F18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}] +set_property -dict {LOC F20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}] +set_property -dict {LOC F19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}] +set_property -dict {LOC D21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}] +set_property -dict {LOC E18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}] +set_property -dict {LOC G19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}] +set_property -dict {LOC E21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}] +set_property -dict {LOC G20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}] +set_property -dict {LOC D18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}] +set_property -dict {LOC B22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}] +set_property -dict {LOC A19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}] +set_property -dict {LOC A18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}] +set_property -dict {LOC C19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}] +set_property -dict {LOC B19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}] +set_property -dict {LOC A22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}] +set_property -dict {LOC C18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}] +set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}] +set_property -dict {LOC J20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}] +set_property -dict {LOC H19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}] +set_property -dict {LOC J19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}] +set_property -dict {LOC H18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}] +set_property -dict {LOC J18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}] +set_property -dict {LOC G21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}] +set_property -dict {LOC K18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}] +set_property -dict {LOC L20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}] +set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}] +set_property -dict {LOC N19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}] +set_property -dict {LOC M21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}] +set_property -dict {LOC M19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}] +set_property -dict {LOC M22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}] +set_property -dict {LOC L19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}] +set_property -dict {LOC M20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}] +set_property -dict {LOC H16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}] +set_property -dict {LOC K15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}] +set_property -dict {LOC J16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}] +set_property -dict {LOC J14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}] +set_property -dict {LOC K13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}] +set_property -dict {LOC L13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}] +set_property -dict {LOC H14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}] +set_property -dict {LOC J15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}] +set_property -dict {LOC M12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}] +set_property -dict {LOC L12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}] +set_property -dict {LOC L15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}] +set_property -dict {LOC L14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}] +set_property -dict {LOC F13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}] +set_property -dict {LOC E13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}] +set_property -dict {LOC B15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}] +set_property -dict {LOC A15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}] +set_property -dict {LOC F22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}] +set_property -dict {LOC E22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}] +set_property -dict {LOC C21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}] +set_property -dict {LOC B21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}] +set_property -dict {LOC K21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}] +set_property -dict {LOC K20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}] +set_property -dict {LOC L22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}] +set_property -dict {LOC K22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}] +set_property -dict {LOC K17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}] +set_property -dict {LOC K16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}] +set_property -dict {LOC N12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[0]}] +set_property -dict {LOC P14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[1]}] +set_property -dict {LOC G15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[2]}] +set_property -dict {LOC D14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[3]}] +set_property -dict {LOC E20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[4]}] +set_property -dict {LOC B20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[5]}] +set_property -dict {LOC H22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[6]}] +set_property -dict {LOC N22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[7]}] +set_property -dict {LOC J13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[8]}] + +# DDR4 C1 +# 5x K4A8G085WB-RC +set_property -dict {LOC AN9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}] +set_property -dict {LOC AM9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}] +set_property -dict {LOC AP11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}] +set_property -dict {LOC AU9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}] +set_property -dict {LOC AT10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}] +set_property -dict {LOC AL12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}] +set_property -dict {LOC AM12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}] +set_property -dict {LOC AM10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}] +set_property -dict {LOC AL11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}] +set_property -dict {LOC AP7 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}] +set_property -dict {LOC AR8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}] +set_property -dict {LOC AL10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}] +set_property -dict {LOC AP8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}] +set_property -dict {LOC AK11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}] +set_property -dict {LOC AP9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}] +set_property -dict {LOC AV10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}] +set_property -dict {LOC AT11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}] +# set_property -dict {LOC AL8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[17]}] +set_property -dict {LOC AN11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}] +set_property -dict {LOC AR9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}] +set_property -dict {LOC AP12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}] +set_property -dict {LOC AN10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}] +# set_property -dict {LOC AW13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_c[0]}] +# set_property -dict {LOC AU10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_c[1]}] +# set_property -dict {LOC AW11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_c[2]}] +set_property -dict {LOC AM7 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t}] +set_property -dict {LOC AN7 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c}] +set_property -dict {LOC AU12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke}] +set_property -dict {LOC AT12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n}] +set_property -dict {LOC AV9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}] +set_property -dict {LOC AR11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt}] +set_property -dict {LOC AM8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}] +set_property -dict {LOC AN12 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}] +set_property -dict {LOC AR10 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_alert_n}] +set_property -dict {LOC AV11 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_ten}] + +set_property -dict {LOC AK9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] +set_property -dict {LOC AK10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] +set_property -dict {LOC AH10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] +set_property -dict {LOC AJ11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] +set_property -dict {LOC AJ9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] +set_property -dict {LOC AH12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] +set_property -dict {LOC AG10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] +set_property -dict {LOC AJ12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] +set_property -dict {LOC AM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] +set_property -dict {LOC AN14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] +set_property -dict {LOC AL13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] +set_property -dict {LOC AM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] +set_property -dict {LOC AL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] +set_property -dict {LOC AM17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] +set_property -dict {LOC AL17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] +set_property -dict {LOC AM13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] +set_property -dict {LOC AR15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] +set_property -dict {LOC AP14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] +set_property -dict {LOC AT15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] +set_property -dict {LOC AR14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] +set_property -dict {LOC AP17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] +set_property -dict {LOC AN16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] +set_property -dict {LOC AN17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] +set_property -dict {LOC AN15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] +set_property -dict {LOC AU15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] +set_property -dict {LOC AT17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] +set_property -dict {LOC AV15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] +set_property -dict {LOC AT16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] +set_property -dict {LOC AV14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] +set_property -dict {LOC AW17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] +set_property -dict {LOC AW14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] +set_property -dict {LOC AW18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] +set_property -dict {LOC AP19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] +set_property -dict {LOC AT20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] +set_property -dict {LOC AN21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] +set_property -dict {LOC AR19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] +set_property -dict {LOC AN20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] +set_property -dict {LOC AR18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] +set_property -dict {LOC AR20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] +set_property -dict {LOC AP18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] +set_property -dict {LOC AW19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] +set_property -dict {LOC AU22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] +set_property -dict {LOC AV19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] +set_property -dict {LOC AW22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] +set_property -dict {LOC AU18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] +set_property -dict {LOC AT22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] +set_property -dict {LOC AW21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] +set_property -dict {LOC AU19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] +set_property -dict {LOC AH19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] +set_property -dict {LOC AJ22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] +set_property -dict {LOC AF21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] +set_property -dict {LOC AH22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] +set_property -dict {LOC AF20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] +set_property -dict {LOC AJ19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] +set_property -dict {LOC AH21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] +set_property -dict {LOC AJ21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] +set_property -dict {LOC AM19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] +set_property -dict {LOC AK20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] +set_property -dict {LOC AM22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] +set_property -dict {LOC AL22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] +set_property -dict {LOC AM20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] +set_property -dict {LOC AK19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] +set_property -dict {LOC AN19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] +set_property -dict {LOC AL20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] +set_property -dict {LOC AF15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}] +set_property -dict {LOC AJ17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}] +set_property -dict {LOC AH17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}] +set_property -dict {LOC AJ14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}] +set_property -dict {LOC AG15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}] +set_property -dict {LOC AJ13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}] +set_property -dict {LOC AG17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}] +set_property -dict {LOC AJ16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}] +set_property -dict {LOC AG9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] +set_property -dict {LOC AH9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] +set_property -dict {LOC AK16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] +set_property -dict {LOC AL16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] +set_property -dict {LOC AR13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] +set_property -dict {LOC AT13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] +set_property -dict {LOC AU17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] +set_property -dict {LOC AV17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] +set_property -dict {LOC AN22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] +set_property -dict {LOC AP22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] +set_property -dict {LOC AV22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] +set_property -dict {LOC AV21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] +set_property -dict {LOC AG20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] +set_property -dict {LOC AH20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] +set_property -dict {LOC AK21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] +set_property -dict {LOC AL21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] +set_property -dict {LOC AH16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}] +set_property -dict {LOC AH15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}] +set_property -dict {LOC AG12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[0]}] +set_property -dict {LOC AK15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[1]}] +set_property -dict {LOC AP16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[2]}] +set_property -dict {LOC AV16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[3]}] +set_property -dict {LOC AP21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[4]}] +set_property -dict {LOC AU20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[5]}] +set_property -dict {LOC AG19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[6]}] +set_property -dict {LOC AL18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[7]}] +set_property -dict {LOC AG14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[8]}] + # QSPI flash set_property -dict {LOC AF30 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[0]}] set_property -dict {LOC AG30 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[1]}] diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile index c9a01f61b..694f11f92 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile @@ -119,6 +119,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/cmac_usplus_0.tcl IP_TCL_FILES += ip/cmac_usplus_1.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl index c5b86e09b..64280337c 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/config.tcl @@ -136,6 +136,12 @@ dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "131072" dict set params RX_RAM_SIZE "131072" + +# RAM configuration +dict set params DDR_CH "2" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" # Application block configuration dict set params APP_ID "32'h00000000" @@ -187,6 +193,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile index 40ede8699..ed7fb41bc 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile @@ -121,6 +121,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/cmac_usplus_0.tcl IP_TCL_FILES += ip/cmac_usplus_1.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl index b55ec5b84..2cdcd5cbf 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/config.tcl @@ -136,6 +136,12 @@ dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "131072" dict set params RX_RAM_SIZE "131072" + +# RAM configuration +dict set params DDR_CH "2" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" # Application block configuration dict set params APP_ID "32'h00000000" @@ -187,6 +193,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/ip/custom_parts_2400.csv b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/ip/custom_parts_2400.csv new file mode 100644 index 000000000..1af01b1bb --- /dev/null +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/ip/custom_parts_2400.csv @@ -0,0 +1,5 @@ +Part type,Part name,Rank,StackHeight,CA Mirror,Data mask,Address width,Row width,Column width,Bank width,Bank group width,CS width,CKE width,ODT width,CK width,Memory speed grade,Memory density,Component density,Memory device width,Memory component width,Data bits per strobe,IO Voltages,Data widths,Min period,Max period,tCKE,tFAW,tFAW_dlr,tMRD,tRAS,tRCD,tREFI,tRFC,tRFC_dlr,tRP,tRRD_S,tRRD_L,tRRD_dlr,tRTP,tWR,tWTR_S,tWTR_L,tXPR,tZQCS,tZQINIT,tCCD_3ds,cas latency,cas write latency,burst length,RTT (nominal) - ODT +Components,CUSTOM_MT40A1G8PM-083E,1,1,0,1,17,16,10,2,2,1,1,1,1,083E,8Gb,8Gb,8,8,8,1.2V,"72",833,1600,5000 ps,21000 ps,0,8 tck,32000 ps,13320 ps,7800000 ps,350000 ps,0,13320 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,"17","12",8,RZQ/6 +Components,CUSTOM_DBI_RD_MT40A1G8PM-083E,1,1,0,1,17,16,10,2,2,1,1,1,1,083E,8Gb,8Gb,8,8,8,1.2V,"72",833,1600,5000 ps,21000 ps,0,8 tck,32000 ps,13320 ps,7800000 ps,350000 ps,0,13320 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,"20","12",8,RZQ/6 +Components,CUSTOM_K4A8G085WB-RC,1,1,0,1,17,16,10,2,2,1,1,1,1,083,8Gb,8Gb,8,8,8,1.2V,"72",833,1600,5000 ps,21000 ps,0,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,0,14160 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,"17","12",8,RZQ/6 +Components,CUSTOM_DBI_RD_K4A8G085WB-RC,1,1,0,1,17,16,10,2,2,1,1,1,1,083,8Gb,8Gb,8,8,8,1.2V,"72",833,1600,5000 ps,21000 ps,0,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,0,14160 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,"20","12",8,RZQ/6 diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/ip/ddr4_0.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/ip/ddr4_0.tcl new file mode 100644 index 000000000..b53fcef5e --- /dev/null +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/ip/ddr4_0.tcl @@ -0,0 +1,23 @@ + +create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 + +set path [file dirname [file normalize [info script]]] + +set_property -dict [list \ + CONFIG.C0.DDR4_AxiSelection {true} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_AxiIDWidth {8} \ + CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ + CONFIG.C0.DDR4_TimePeriod {833} \ + CONFIG.C0.DDR4_InputClockPeriod {3332} \ + CONFIG.C0.DDR4_CustomParts "$path/custom_parts_2400.csv" \ + CONFIG.C0.DDR4_isCustom {true} \ + CONFIG.C0.DDR4_MemoryType {Components} \ + CONFIG.C0.DDR4_MemoryPart {CUSTOM_K4A8G085WB-RC} \ + CONFIG.C0.DDR4_DataWidth {72} \ + CONFIG.C0.DDR4_DataMask {NO_DM_NO_DBI} \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_CasLatency {17} \ + CONFIG.C0.DDR4_CasWriteLatency {12} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} +] [get_ips ddr4_0] diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v index b94b463f2..67593ffe4 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v @@ -109,6 +109,15 @@ module fpga # parameter TX_RAM_SIZE = 131072, parameter RX_RAM_SIZE = 131072, + // RAM configuration + parameter DDR_CH = 2, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 33, + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -178,6 +187,10 @@ module fpga # */ input wire clk_300mhz_p, input wire clk_300mhz_n, + input wire mem_clk_300mhz_0_p, + input wire mem_clk_300mhz_0_n, + input wire mem_clk_300mhz_1_p, + input wire mem_clk_300mhz_1_n, /* * GPIO @@ -253,6 +266,45 @@ module fpga # inout wire eeprom_i2c_sda, output wire eeprom_wp, + /* + * DDR4 + */ + output wire [16:0] ddr4_c0_adr, + output wire [1:0] ddr4_c0_ba, + output wire [1:0] ddr4_c0_bg, + output wire ddr4_c0_ck_t, + output wire ddr4_c0_ck_c, + output wire ddr4_c0_cke, + output wire ddr4_c0_cs_n, + output wire ddr4_c0_act_n, + output wire ddr4_c0_odt, + output wire ddr4_c0_par, + input wire ddr4_c0_alert_n, + output wire ddr4_c0_reset_n, + output wire ddr4_c0_ten, + inout wire [71:0] ddr4_c0_dq, + inout wire [8:0] ddr4_c0_dqs_t, + inout wire [8:0] ddr4_c0_dqs_c, + inout wire [8:0] ddr4_c0_dm_dbi_n, + + output wire [16:0] ddr4_c1_adr, + output wire [1:0] ddr4_c1_ba, + output wire [1:0] ddr4_c1_bg, + output wire ddr4_c1_ck_t, + output wire ddr4_c1_ck_c, + output wire ddr4_c1_cke, + output wire ddr4_c1_cs_n, + output wire ddr4_c1_act_n, + output wire ddr4_c1_odt, + output wire ddr4_c1_par, + input wire ddr4_c1_alert_n, + output wire ddr4_c1_reset_n, + output wire ddr4_c1_ten, + inout wire [71:0] ddr4_c1_dq, + inout wire [8:0] ddr4_c1_dqs_t, + inout wire [8:0] ddr4_c1_dqs_c, + inout wire [8:0] ddr4_c1_dm_dbi_n, + /* * QSPI */ @@ -270,6 +322,8 @@ parameter PTP_SEPARATE_RX_CLOCK = 1; // Interface configuration parameter TX_TAG_WIDTH = 16; +// RAM configuration +parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8); // Ethernet interface configuration parameter AXIS_ETH_DATA_WIDTH = 512; @@ -1757,6 +1811,301 @@ sync_reset_ptp_rst_inst ( assign front_led[0] = qsfp_0_rx_status; assign front_led[1] = qsfp_1_rx_status; +// DDR4 +wire [DDR_CH-1:0] ddr_clk; +wire [DDR_CH-1:0] ddr_rst; + +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr; +wire [DDR_CH*8-1:0] m_axi_ddr_awlen; +wire [DDR_CH*3-1:0] m_axi_ddr_awsize; +wire [DDR_CH*2-1:0] m_axi_ddr_awburst; +wire [DDR_CH-1:0] m_axi_ddr_awlock; +wire [DDR_CH*4-1:0] m_axi_ddr_awcache; +wire [DDR_CH*3-1:0] m_axi_ddr_awprot; +wire [DDR_CH*4-1:0] m_axi_ddr_awqos; +wire [DDR_CH-1:0] m_axi_ddr_awvalid; +wire [DDR_CH-1:0] m_axi_ddr_awready; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata; +wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb; +wire [DDR_CH-1:0] m_axi_ddr_wlast; +wire [DDR_CH-1:0] m_axi_ddr_wvalid; +wire [DDR_CH-1:0] m_axi_ddr_wready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid; +wire [DDR_CH*2-1:0] m_axi_ddr_bresp; +wire [DDR_CH-1:0] m_axi_ddr_bvalid; +wire [DDR_CH-1:0] m_axi_ddr_bready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr; +wire [DDR_CH*8-1:0] m_axi_ddr_arlen; +wire [DDR_CH*3-1:0] m_axi_ddr_arsize; +wire [DDR_CH*2-1:0] m_axi_ddr_arburst; +wire [DDR_CH-1:0] m_axi_ddr_arlock; +wire [DDR_CH*4-1:0] m_axi_ddr_arcache; +wire [DDR_CH*3-1:0] m_axi_ddr_arprot; +wire [DDR_CH*4-1:0] m_axi_ddr_arqos; +wire [DDR_CH-1:0] m_axi_ddr_arvalid; +wire [DDR_CH-1:0] m_axi_ddr_arready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata; +wire [DDR_CH*2-1:0] m_axi_ddr_rresp; +wire [DDR_CH-1:0] m_axi_ddr_rlast; +wire [DDR_CH-1:0] m_axi_ddr_rvalid; +wire [DDR_CH-1:0] m_axi_ddr_rready; + +wire [DDR_CH-1:0] ddr_status; + +generate + +if (DDR_ENABLE && DDR_CH > 0) begin + +ddr4_0 ddr4_c0_inst ( + .c0_sys_clk_p(mem_clk_300mhz_0_p), + .c0_sys_clk_n(mem_clk_300mhz_0_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[0 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c0_adr), + .c0_ddr4_ba(ddr4_c0_ba), + .c0_ddr4_cke(ddr4_c0_cke), + .c0_ddr4_cs_n(ddr4_c0_cs_n), + .c0_ddr4_dq(ddr4_c0_dq), + .c0_ddr4_dqs_t(ddr4_c0_dqs_t), + .c0_ddr4_dqs_c(ddr4_c0_dqs_c), + .c0_ddr4_dm_dbi_n(ddr4_c0_dm_dbi_n), + .c0_ddr4_odt(ddr4_c0_odt), + .c0_ddr4_bg(ddr4_c0_bg), + .c0_ddr4_reset_n(ddr4_c0_reset_n), + .c0_ddr4_act_n(ddr4_c0_act_n), + .c0_ddr4_ck_t(ddr4_c0_ck_t), + .c0_ddr4_ck_c(ddr4_c0_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[0 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[0 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c0_adr = {17{1'bz}}; +assign ddr4_c0_ba = {2{1'bz}}; +assign ddr4_c0_bg = {2{1'bz}}; +assign ddr4_c0_cke = 1'bz; +assign ddr4_c0_cs_n = 1'bz; +assign ddr4_c0_act_n = 1'bz; +assign ddr4_c0_odt = 1'bz; +assign ddr4_c0_reset_n = 1'b0; +assign ddr4_c0_dq = {80{1'bz}}; +assign ddr4_c0_dqs_t = {10{1'bz}}; +assign ddr4_c0_dqs_c = {10{1'bz}}; +assign ddr4_c0_dm_dbi_n = {10{1'bz}}; + +OBUFTDS ddr4_c0_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c0_ck_t), + .OB(ddr4_c0_ck_c) +); + +assign ddr_clk = 0; +assign ddr_rst = 0; + +assign m_axi_ddr_awready = 0; +assign m_axi_ddr_wready = 0; +assign m_axi_ddr_bid = 0; +assign m_axi_ddr_bresp = 0; +assign m_axi_ddr_bvalid = 0; +assign m_axi_ddr_arready = 0; +assign m_axi_ddr_rid = 0; +assign m_axi_ddr_rdata = 0; +assign m_axi_ddr_rresp = 0; +assign m_axi_ddr_rlast = 0; +assign m_axi_ddr_rvalid = 0; + +assign ddr_status = 0; + +end + +assign ddr4_c0_par = 1'b0; +assign ddr4_c0_ten = 1'b0; + +if (DDR_ENABLE && DDR_CH > 1) begin + +ddr4_0 ddr4_c1_inst ( + .c0_sys_clk_p(mem_clk_300mhz_1_p), + .c0_sys_clk_n(mem_clk_300mhz_1_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[1 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c1_adr), + .c0_ddr4_ba(ddr4_c1_ba), + .c0_ddr4_cke(ddr4_c1_cke), + .c0_ddr4_cs_n(ddr4_c1_cs_n), + .c0_ddr4_dq(ddr4_c1_dq), + .c0_ddr4_dqs_t(ddr4_c1_dqs_t), + .c0_ddr4_dqs_c(ddr4_c1_dqs_c), + .c0_ddr4_dm_dbi_n(ddr4_c1_dm_dbi_n), + .c0_ddr4_odt(ddr4_c1_odt), + .c0_ddr4_bg(ddr4_c1_bg), + .c0_ddr4_reset_n(ddr4_c1_reset_n), + .c0_ddr4_act_n(ddr4_c1_act_n), + .c0_ddr4_ck_t(ddr4_c1_ck_t), + .c0_ddr4_ck_c(ddr4_c1_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[1 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[1 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[1 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[1*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[1*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[1*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[1 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[1*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[1*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[1*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[1 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[1 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[1*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[1 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[1 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[1 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[1 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[1*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[1 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[1*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[1*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[1*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[1 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[1*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[1*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[1*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[1 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[1 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[1 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[1 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[1 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[1*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c1_adr = {17{1'bz}}; +assign ddr4_c1_ba = {2{1'bz}}; +assign ddr4_c1_bg = {2{1'bz}}; +assign ddr4_c1_cke = 1'bz; +assign ddr4_c1_cs_n = 1'bz; +assign ddr4_c1_act_n = 1'bz; +assign ddr4_c1_odt = 1'bz; +assign ddr4_c1_reset_n = 1'b0; +assign ddr4_c1_dq = {80{1'bz}}; +assign ddr4_c1_dqs_t = {10{1'bz}}; +assign ddr4_c1_dqs_c = {10{1'bz}}; +assign ddr4_c1_dm_dbi_n = {10{1'bz}}; + +OBUFTDS ddr4_c1_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c1_ck_t), + .OB(ddr4_c1_ck_c) +); + +end + +assign ddr4_c1_par = 1'b0; +assign ddr4_c1_ten = 1'b0; + +endgenerate + fpga_core #( // FW and board IDs .FPGA_ID(FPGA_ID), @@ -1831,6 +2180,16 @@ fpga_core #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -2070,6 +2429,50 @@ core_inst ( .eeprom_i2c_sda_t(eeprom_i2c_sda_t), .eeprom_wp(eeprom_wp), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + /* * QSPI flash */ diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v index bf14c05b8..fc2f42ad5 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v @@ -115,6 +115,16 @@ module fpga_core # parameter TX_RAM_SIZE = 131072, parameter RX_RAM_SIZE = 131072, + // RAM configuration + parameter DDR_CH = 2, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 33, + parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -368,6 +378,52 @@ module fpga_core # output wire eeprom_i2c_sda_t, output wire eeprom_wp, + /* + * DDR + */ + input wire [DDR_CH-1:0] ddr_clk, + input wire [DDR_CH-1:0] ddr_rst, + + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, + output wire [DDR_CH-1:0] m_axi_ddr_awlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, + output wire [DDR_CH-1:0] m_axi_ddr_awvalid, + input wire [DDR_CH-1:0] m_axi_ddr_awready, + output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, + output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, + output wire [DDR_CH-1:0] m_axi_ddr_wlast, + output wire [DDR_CH-1:0] m_axi_ddr_wvalid, + input wire [DDR_CH-1:0] m_axi_ddr_wready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, + input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, + input wire [DDR_CH-1:0] m_axi_ddr_bvalid, + output wire [DDR_CH-1:0] m_axi_ddr_bready, + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, + output wire [DDR_CH-1:0] m_axi_ddr_arlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, + output wire [DDR_CH-1:0] m_axi_ddr_arvalid, + input wire [DDR_CH-1:0] m_axi_ddr_arready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, + input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, + input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, + input wire [DDR_CH-1:0] m_axi_ddr_rlast, + input wire [DDR_CH-1:0] m_axi_ddr_rvalid, + output wire [DDR_CH-1:0] m_axi_ddr_rready, + + input wire [DDR_CH-1:0] ddr_status, + /* * QSPI flash */ @@ -895,6 +951,25 @@ mqnic_core_pcie_us #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .DDR_GROUP_SIZE(1), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_AWUSER_ENABLE(0), + .AXI_DDR_WUSER_ENABLE(0), + .AXI_DDR_BUSER_ENABLE(0), + .AXI_DDR_ARUSER_ENABLE(0), + .AXI_DDR_RUSER_ENABLE(0), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + .AXI_DDR_FIXED_BURST(0), + .AXI_DDR_WRAP_BURST(1), + .HBM_ENABLE(0), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1172,6 +1247,108 @@ core_inst ( .eth_rx_status(eth_rx_status), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awuser(), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wuser(), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_buser(0), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_aruser(), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_ruser(0), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + + /* + * HBM + */ + .hbm_clk(0), + .hbm_rst(0), + + .m_axi_hbm_awid(), + .m_axi_hbm_awaddr(), + .m_axi_hbm_awlen(), + .m_axi_hbm_awsize(), + .m_axi_hbm_awburst(), + .m_axi_hbm_awlock(), + .m_axi_hbm_awcache(), + .m_axi_hbm_awprot(), + .m_axi_hbm_awqos(), + .m_axi_hbm_awuser(), + .m_axi_hbm_awvalid(), + .m_axi_hbm_awready(0), + .m_axi_hbm_wdata(), + .m_axi_hbm_wstrb(), + .m_axi_hbm_wlast(), + .m_axi_hbm_wuser(), + .m_axi_hbm_wvalid(), + .m_axi_hbm_wready(0), + .m_axi_hbm_bid(0), + .m_axi_hbm_bresp(0), + .m_axi_hbm_buser(0), + .m_axi_hbm_bvalid(0), + .m_axi_hbm_bready(), + .m_axi_hbm_arid(), + .m_axi_hbm_araddr(), + .m_axi_hbm_arlen(), + .m_axi_hbm_arsize(), + .m_axi_hbm_arburst(), + .m_axi_hbm_arlock(), + .m_axi_hbm_arcache(), + .m_axi_hbm_arprot(), + .m_axi_hbm_arqos(), + .m_axi_hbm_aruser(), + .m_axi_hbm_arvalid(), + .m_axi_hbm_arready(0), + .m_axi_hbm_rid(0), + .m_axi_hbm_rdata(0), + .m_axi_hbm_rresp(0), + .m_axi_hbm_rlast(0), + .m_axi_hbm_ruser(0), + .m_axi_hbm_rvalid(0), + .m_axi_hbm_rready(), + + .hbm_status(0), + /* * Statistics input */ diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/README.md b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/README.md index 34cf688db..0faf60644 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/README.md +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/README.md @@ -4,8 +4,9 @@ This design targets the Alpha Data ADM-PCIE-9V3 FPGA board. -FPGA: xcvu3p-ffvc1517-2-i -PHY: 25G BASE-R PHY IP core and internal GTY transceiver +* FPGA: xcvu3p-ffvc1517-2-i +* PHY: 25G BASE-R PHY IP core and internal GTY transceiver +* RAM: 16 GB DDR4 2400 (2x 1G x72) ## How to build diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga.xdc b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga.xdc index 519acd9d5..ec3fc2998 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga.xdc +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga.xdc @@ -17,6 +17,16 @@ set_property -dict {LOC AP26 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports set_property -dict {LOC AP27 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports clk_300mhz_n] create_clock -period 3.333 -name clk_300mhz [get_ports clk_300mhz_p] +# 300 MHz memory clock (C0) +set_property -dict {LOC G31 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports mem_clk_300mhz_0_p] +set_property -dict {LOC G32 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports mem_clk_300mhz_0_n] +# create_clock -period 3.333 -name mem_clk_300mhz_0 [get_ports mem_clk_300mhz_0_p] + +# 300 MHz memory clock (C1) +set_property -dict {LOC AN25 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports mem_clk_300mhz_1_p] +set_property -dict {LOC AN26 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports mem_clk_300mhz_1_n] +# create_clock -period 3.333 -name mem_clk_300mhz_1 [get_ports mem_clk_300mhz_1_p] + # LEDs set_property -dict {LOC AT27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {user_led_g[0]}] set_property -dict {LOC AU27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports {user_led_g[1]}] @@ -193,6 +203,282 @@ create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_1_p] set_false_path -from [get_ports {perst_0}] set_input_delay 0 [get_ports {perst_0}] +# DDR4 C0 +# 5x K4A8G085WB-RC +set_property -dict {LOC F9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}] +set_property -dict {LOC G9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}] +set_property -dict {LOC G11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}] +set_property -dict {LOC D11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}] +set_property -dict {LOC E12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}] +set_property -dict {LOC G10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}] +set_property -dict {LOC F10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}] +set_property -dict {LOC J9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}] +set_property -dict {LOC J8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}] +set_property -dict {LOC F12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}] +set_property -dict {LOC D9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}] +set_property -dict {LOC H11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}] +set_property -dict {LOC E8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}] +set_property -dict {LOC J11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}] +set_property -dict {LOC C9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}] +set_property -dict {LOC B11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}] +set_property -dict {LOC K12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}] +# set_property -dict {LOC H9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[17]}] +set_property -dict {LOC F8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}] +set_property -dict {LOC H8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}] +set_property -dict {LOC D10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}] +set_property -dict {LOC E11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}] +# set_property -dict {LOC B10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_c[0]}] +# set_property -dict {LOC C11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_c[1]}] +# set_property -dict {LOC A9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_c[2]}] +set_property -dict {LOC H12 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t}] +set_property -dict {LOC G12 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c}] +set_property -dict {LOC B9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke}] +set_property -dict {LOC E10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n}] +set_property -dict {LOC C12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}] +set_property -dict {LOC A10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt}] +set_property -dict {LOC G7 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}] +set_property -dict {LOC F7 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_reset_n}] +set_property -dict {LOC H7 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_alert_n}] +set_property -dict {LOC J10 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_ten}] + +set_property -dict {LOC L10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}] +set_property -dict {LOC L9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}] +set_property -dict {LOC N9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}] +set_property -dict {LOC M9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}] +set_property -dict {LOC M10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}] +set_property -dict {LOC K11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}] +set_property -dict {LOC M11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}] +set_property -dict {LOC K10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}] +set_property -dict {LOC L17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}] +set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}] +set_property -dict {LOC M15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}] +set_property -dict {LOC M17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}] +set_property -dict {LOC M14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}] +set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}] +set_property -dict {LOC N16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}] +set_property -dict {LOC N17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}] +set_property -dict {LOC F15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}] +set_property -dict {LOC E16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}] +set_property -dict {LOC F14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}] +set_property -dict {LOC E17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}] +set_property -dict {LOC G16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}] +set_property -dict {LOC F17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}] +set_property -dict {LOC E15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}] +set_property -dict {LOC G17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}] +set_property -dict {LOC A17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}] +set_property -dict {LOC C16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}] +set_property -dict {LOC B16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}] +set_property -dict {LOC A14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}] +set_property -dict {LOC B17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}] +set_property -dict {LOC B14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}] +set_property -dict {LOC D16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}] +set_property -dict {LOC D15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}] +set_property -dict {LOC F18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}] +set_property -dict {LOC F20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}] +set_property -dict {LOC F19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}] +set_property -dict {LOC D21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}] +set_property -dict {LOC E18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}] +set_property -dict {LOC G19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}] +set_property -dict {LOC E21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}] +set_property -dict {LOC G20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}] +set_property -dict {LOC D18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}] +set_property -dict {LOC B22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}] +set_property -dict {LOC A19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}] +set_property -dict {LOC A18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}] +set_property -dict {LOC C19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}] +set_property -dict {LOC B19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}] +set_property -dict {LOC A22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}] +set_property -dict {LOC C18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}] +set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}] +set_property -dict {LOC J20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}] +set_property -dict {LOC H19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}] +set_property -dict {LOC J19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}] +set_property -dict {LOC H18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}] +set_property -dict {LOC J18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}] +set_property -dict {LOC G21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}] +set_property -dict {LOC K18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}] +set_property -dict {LOC L20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}] +set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}] +set_property -dict {LOC N19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}] +set_property -dict {LOC M21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}] +set_property -dict {LOC M19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}] +set_property -dict {LOC M22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}] +set_property -dict {LOC L19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}] +set_property -dict {LOC M20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}] +set_property -dict {LOC H16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}] +set_property -dict {LOC K15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}] +set_property -dict {LOC J16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}] +set_property -dict {LOC J14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}] +set_property -dict {LOC K13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}] +set_property -dict {LOC L13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}] +set_property -dict {LOC H14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}] +set_property -dict {LOC J15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}] +set_property -dict {LOC M12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}] +set_property -dict {LOC L12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}] +set_property -dict {LOC L15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}] +set_property -dict {LOC L14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}] +set_property -dict {LOC F13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}] +set_property -dict {LOC E13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}] +set_property -dict {LOC B15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}] +set_property -dict {LOC A15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}] +set_property -dict {LOC F22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}] +set_property -dict {LOC E22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}] +set_property -dict {LOC C21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}] +set_property -dict {LOC B21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}] +set_property -dict {LOC K21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}] +set_property -dict {LOC K20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}] +set_property -dict {LOC L22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}] +set_property -dict {LOC K22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}] +set_property -dict {LOC K17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}] +set_property -dict {LOC K16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}] +set_property -dict {LOC N12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[0]}] +set_property -dict {LOC P14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[1]}] +set_property -dict {LOC G15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[2]}] +set_property -dict {LOC D14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[3]}] +set_property -dict {LOC E20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[4]}] +set_property -dict {LOC B20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[5]}] +set_property -dict {LOC H22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[6]}] +set_property -dict {LOC N22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[7]}] +set_property -dict {LOC J13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[8]}] + +# DDR4 C1 +# 5x K4A8G085WB-RC +set_property -dict {LOC AN9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}] +set_property -dict {LOC AM9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}] +set_property -dict {LOC AP11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}] +set_property -dict {LOC AU9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}] +set_property -dict {LOC AT10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}] +set_property -dict {LOC AL12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}] +set_property -dict {LOC AM12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}] +set_property -dict {LOC AM10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}] +set_property -dict {LOC AL11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}] +set_property -dict {LOC AP7 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}] +set_property -dict {LOC AR8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}] +set_property -dict {LOC AL10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}] +set_property -dict {LOC AP8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}] +set_property -dict {LOC AK11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}] +set_property -dict {LOC AP9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}] +set_property -dict {LOC AV10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}] +set_property -dict {LOC AT11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}] +# set_property -dict {LOC AL8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[17]}] +set_property -dict {LOC AN11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}] +set_property -dict {LOC AR9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}] +set_property -dict {LOC AP12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}] +set_property -dict {LOC AN10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}] +# set_property -dict {LOC AW13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_c[0]}] +# set_property -dict {LOC AU10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_c[1]}] +# set_property -dict {LOC AW11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_c[2]}] +set_property -dict {LOC AM7 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t}] +set_property -dict {LOC AN7 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c}] +set_property -dict {LOC AU12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke}] +set_property -dict {LOC AT12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n}] +set_property -dict {LOC AV9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}] +set_property -dict {LOC AR11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt}] +set_property -dict {LOC AM8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}] +set_property -dict {LOC AN12 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}] +set_property -dict {LOC AR10 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_alert_n}] +set_property -dict {LOC AV11 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_ten}] + +set_property -dict {LOC AK9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] +set_property -dict {LOC AK10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] +set_property -dict {LOC AH10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] +set_property -dict {LOC AJ11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] +set_property -dict {LOC AJ9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] +set_property -dict {LOC AH12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] +set_property -dict {LOC AG10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] +set_property -dict {LOC AJ12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] +set_property -dict {LOC AM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] +set_property -dict {LOC AN14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] +set_property -dict {LOC AL13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] +set_property -dict {LOC AM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] +set_property -dict {LOC AL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] +set_property -dict {LOC AM17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] +set_property -dict {LOC AL17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] +set_property -dict {LOC AM13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] +set_property -dict {LOC AR15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] +set_property -dict {LOC AP14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] +set_property -dict {LOC AT15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] +set_property -dict {LOC AR14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] +set_property -dict {LOC AP17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] +set_property -dict {LOC AN16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] +set_property -dict {LOC AN17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] +set_property -dict {LOC AN15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] +set_property -dict {LOC AU15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] +set_property -dict {LOC AT17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] +set_property -dict {LOC AV15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] +set_property -dict {LOC AT16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] +set_property -dict {LOC AV14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] +set_property -dict {LOC AW17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] +set_property -dict {LOC AW14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] +set_property -dict {LOC AW18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] +set_property -dict {LOC AP19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] +set_property -dict {LOC AT20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] +set_property -dict {LOC AN21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] +set_property -dict {LOC AR19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] +set_property -dict {LOC AN20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] +set_property -dict {LOC AR18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] +set_property -dict {LOC AR20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] +set_property -dict {LOC AP18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] +set_property -dict {LOC AW19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] +set_property -dict {LOC AU22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] +set_property -dict {LOC AV19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] +set_property -dict {LOC AW22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] +set_property -dict {LOC AU18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] +set_property -dict {LOC AT22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] +set_property -dict {LOC AW21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] +set_property -dict {LOC AU19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] +set_property -dict {LOC AH19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] +set_property -dict {LOC AJ22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] +set_property -dict {LOC AF21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] +set_property -dict {LOC AH22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] +set_property -dict {LOC AF20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] +set_property -dict {LOC AJ19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] +set_property -dict {LOC AH21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] +set_property -dict {LOC AJ21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] +set_property -dict {LOC AM19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] +set_property -dict {LOC AK20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] +set_property -dict {LOC AM22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] +set_property -dict {LOC AL22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] +set_property -dict {LOC AM20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] +set_property -dict {LOC AK19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] +set_property -dict {LOC AN19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] +set_property -dict {LOC AL20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] +set_property -dict {LOC AF15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}] +set_property -dict {LOC AJ17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}] +set_property -dict {LOC AH17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}] +set_property -dict {LOC AJ14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}] +set_property -dict {LOC AG15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}] +set_property -dict {LOC AJ13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}] +set_property -dict {LOC AG17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}] +set_property -dict {LOC AJ16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}] +set_property -dict {LOC AG9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] +set_property -dict {LOC AH9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] +set_property -dict {LOC AK16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] +set_property -dict {LOC AL16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] +set_property -dict {LOC AR13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] +set_property -dict {LOC AT13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] +set_property -dict {LOC AU17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] +set_property -dict {LOC AV17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] +set_property -dict {LOC AN22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] +set_property -dict {LOC AP22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] +set_property -dict {LOC AV22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] +set_property -dict {LOC AV21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] +set_property -dict {LOC AG20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] +set_property -dict {LOC AH20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] +set_property -dict {LOC AK21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] +set_property -dict {LOC AL21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] +set_property -dict {LOC AH16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}] +set_property -dict {LOC AH15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}] +set_property -dict {LOC AG12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[0]}] +set_property -dict {LOC AK15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[1]}] +set_property -dict {LOC AP16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[2]}] +set_property -dict {LOC AV16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[3]}] +set_property -dict {LOC AP21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[4]}] +set_property -dict {LOC AU20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[5]}] +set_property -dict {LOC AG19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[6]}] +set_property -dict {LOC AL18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[7]}] +set_property -dict {LOC AG14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[8]}] + # QSPI flash set_property -dict {LOC AF30 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[0]}] set_property -dict {LOC AG30 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[1]}] diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile index e2be57e70..27703739c 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile @@ -139,6 +139,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl index efc928bce..aee9005c5 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/config.tcl @@ -148,6 +148,12 @@ dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" dict set params RX_RAM_SIZE "131072" + +# RAM configuration +dict set params DDR_CH "2" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" # Application block configuration dict set params APP_ID "32'h00000000" @@ -200,6 +206,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile index e2be57e70..27703739c 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile @@ -139,6 +139,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl index f30df7a36..8411fe320 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/config.tcl @@ -148,6 +148,12 @@ dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" dict set params RX_RAM_SIZE "32768" + +# RAM configuration +dict set params DDR_CH "2" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" # Application block configuration dict set params APP_ID "32'h00000000" @@ -200,6 +206,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile index 0871281c9..9028375ae 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile @@ -140,6 +140,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl index 26d305dbe..2b6ba0a37 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/config.tcl @@ -148,6 +148,12 @@ dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" dict set params RX_RAM_SIZE "131072" + +# RAM configuration +dict set params DDR_CH "2" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" # Application block configuration dict set params APP_ID "32'h00000000" @@ -200,6 +206,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/ip/custom_parts_2400.csv b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/ip/custom_parts_2400.csv new file mode 100644 index 000000000..1af01b1bb --- /dev/null +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/ip/custom_parts_2400.csv @@ -0,0 +1,5 @@ +Part type,Part name,Rank,StackHeight,CA Mirror,Data mask,Address width,Row width,Column width,Bank width,Bank group width,CS width,CKE width,ODT width,CK width,Memory speed grade,Memory density,Component density,Memory device width,Memory component width,Data bits per strobe,IO Voltages,Data widths,Min period,Max period,tCKE,tFAW,tFAW_dlr,tMRD,tRAS,tRCD,tREFI,tRFC,tRFC_dlr,tRP,tRRD_S,tRRD_L,tRRD_dlr,tRTP,tWR,tWTR_S,tWTR_L,tXPR,tZQCS,tZQINIT,tCCD_3ds,cas latency,cas write latency,burst length,RTT (nominal) - ODT +Components,CUSTOM_MT40A1G8PM-083E,1,1,0,1,17,16,10,2,2,1,1,1,1,083E,8Gb,8Gb,8,8,8,1.2V,"72",833,1600,5000 ps,21000 ps,0,8 tck,32000 ps,13320 ps,7800000 ps,350000 ps,0,13320 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,"17","12",8,RZQ/6 +Components,CUSTOM_DBI_RD_MT40A1G8PM-083E,1,1,0,1,17,16,10,2,2,1,1,1,1,083E,8Gb,8Gb,8,8,8,1.2V,"72",833,1600,5000 ps,21000 ps,0,8 tck,32000 ps,13320 ps,7800000 ps,350000 ps,0,13320 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,"20","12",8,RZQ/6 +Components,CUSTOM_K4A8G085WB-RC,1,1,0,1,17,16,10,2,2,1,1,1,1,083,8Gb,8Gb,8,8,8,1.2V,"72",833,1600,5000 ps,21000 ps,0,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,0,14160 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,"17","12",8,RZQ/6 +Components,CUSTOM_DBI_RD_K4A8G085WB-RC,1,1,0,1,17,16,10,2,2,1,1,1,1,083,8Gb,8Gb,8,8,8,1.2V,"72",833,1600,5000 ps,21000 ps,0,8 tck,32000 ps,14160 ps,7800000 ps,350000 ps,0,14160 ps,3300 ps,4900 ps,0,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,0,"20","12",8,RZQ/6 diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/ip/ddr4_0.tcl b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/ip/ddr4_0.tcl new file mode 100644 index 000000000..b53fcef5e --- /dev/null +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/ip/ddr4_0.tcl @@ -0,0 +1,23 @@ + +create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 + +set path [file dirname [file normalize [info script]]] + +set_property -dict [list \ + CONFIG.C0.DDR4_AxiSelection {true} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_AxiIDWidth {8} \ + CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ + CONFIG.C0.DDR4_TimePeriod {833} \ + CONFIG.C0.DDR4_InputClockPeriod {3332} \ + CONFIG.C0.DDR4_CustomParts "$path/custom_parts_2400.csv" \ + CONFIG.C0.DDR4_isCustom {true} \ + CONFIG.C0.DDR4_MemoryType {Components} \ + CONFIG.C0.DDR4_MemoryPart {CUSTOM_K4A8G085WB-RC} \ + CONFIG.C0.DDR4_DataWidth {72} \ + CONFIG.C0.DDR4_DataMask {NO_DM_NO_DBI} \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_CasLatency {17} \ + CONFIG.C0.DDR4_CasWriteLatency {12} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} +] [get_ips ddr4_0] diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v index 49bb48b55..7ea8c6d3c 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v @@ -112,6 +112,15 @@ module fpga # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // RAM configuration + parameter DDR_CH = 2, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 33, + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -182,6 +191,10 @@ module fpga # */ input wire clk_300mhz_p, input wire clk_300mhz_n, + input wire mem_clk_300mhz_0_p, + input wire mem_clk_300mhz_0_n, + input wire mem_clk_300mhz_1_p, + input wire mem_clk_300mhz_1_n, /* * GPIO @@ -257,6 +270,45 @@ module fpga # inout wire eeprom_i2c_sda, output wire eeprom_wp, + /* + * DDR4 + */ + output wire [16:0] ddr4_c0_adr, + output wire [1:0] ddr4_c0_ba, + output wire [1:0] ddr4_c0_bg, + output wire ddr4_c0_ck_t, + output wire ddr4_c0_ck_c, + output wire ddr4_c0_cke, + output wire ddr4_c0_cs_n, + output wire ddr4_c0_act_n, + output wire ddr4_c0_odt, + output wire ddr4_c0_par, + input wire ddr4_c0_alert_n, + output wire ddr4_c0_reset_n, + output wire ddr4_c0_ten, + inout wire [71:0] ddr4_c0_dq, + inout wire [8:0] ddr4_c0_dqs_t, + inout wire [8:0] ddr4_c0_dqs_c, + inout wire [8:0] ddr4_c0_dm_dbi_n, + + output wire [16:0] ddr4_c1_adr, + output wire [1:0] ddr4_c1_ba, + output wire [1:0] ddr4_c1_bg, + output wire ddr4_c1_ck_t, + output wire ddr4_c1_ck_c, + output wire ddr4_c1_cke, + output wire ddr4_c1_cs_n, + output wire ddr4_c1_act_n, + output wire ddr4_c1_odt, + output wire ddr4_c1_par, + input wire ddr4_c1_alert_n, + output wire ddr4_c1_reset_n, + output wire ddr4_c1_ten, + inout wire [71:0] ddr4_c1_dq, + inout wire [8:0] ddr4_c1_dqs_t, + inout wire [8:0] ddr4_c1_dqs_c, + inout wire [8:0] ddr4_c1_dm_dbi_n, + /* * QSPI */ @@ -275,6 +327,9 @@ parameter IF_PTP_PERIOD_FNS = 16'h8F5C; // Interface configuration parameter TX_TAG_WIDTH = 16; +// RAM configuration +parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8); + // Ethernet interface configuration parameter XGMII_DATA_WIDTH = 64; parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8; @@ -1357,6 +1412,301 @@ assign ptp_clk = qsfp_0_mgt_refclk_bufg; assign ptp_rst = qsfp_0_rst; assign ptp_sample_clk = clk_125mhz_int; +// DDR4 +wire [DDR_CH-1:0] ddr_clk; +wire [DDR_CH-1:0] ddr_rst; + +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr; +wire [DDR_CH*8-1:0] m_axi_ddr_awlen; +wire [DDR_CH*3-1:0] m_axi_ddr_awsize; +wire [DDR_CH*2-1:0] m_axi_ddr_awburst; +wire [DDR_CH-1:0] m_axi_ddr_awlock; +wire [DDR_CH*4-1:0] m_axi_ddr_awcache; +wire [DDR_CH*3-1:0] m_axi_ddr_awprot; +wire [DDR_CH*4-1:0] m_axi_ddr_awqos; +wire [DDR_CH-1:0] m_axi_ddr_awvalid; +wire [DDR_CH-1:0] m_axi_ddr_awready; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata; +wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb; +wire [DDR_CH-1:0] m_axi_ddr_wlast; +wire [DDR_CH-1:0] m_axi_ddr_wvalid; +wire [DDR_CH-1:0] m_axi_ddr_wready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid; +wire [DDR_CH*2-1:0] m_axi_ddr_bresp; +wire [DDR_CH-1:0] m_axi_ddr_bvalid; +wire [DDR_CH-1:0] m_axi_ddr_bready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr; +wire [DDR_CH*8-1:0] m_axi_ddr_arlen; +wire [DDR_CH*3-1:0] m_axi_ddr_arsize; +wire [DDR_CH*2-1:0] m_axi_ddr_arburst; +wire [DDR_CH-1:0] m_axi_ddr_arlock; +wire [DDR_CH*4-1:0] m_axi_ddr_arcache; +wire [DDR_CH*3-1:0] m_axi_ddr_arprot; +wire [DDR_CH*4-1:0] m_axi_ddr_arqos; +wire [DDR_CH-1:0] m_axi_ddr_arvalid; +wire [DDR_CH-1:0] m_axi_ddr_arready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata; +wire [DDR_CH*2-1:0] m_axi_ddr_rresp; +wire [DDR_CH-1:0] m_axi_ddr_rlast; +wire [DDR_CH-1:0] m_axi_ddr_rvalid; +wire [DDR_CH-1:0] m_axi_ddr_rready; + +wire [DDR_CH-1:0] ddr_status; + +generate + +if (DDR_ENABLE && DDR_CH > 0) begin + +ddr4_0 ddr4_c0_inst ( + .c0_sys_clk_p(mem_clk_300mhz_0_p), + .c0_sys_clk_n(mem_clk_300mhz_0_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[0 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c0_adr), + .c0_ddr4_ba(ddr4_c0_ba), + .c0_ddr4_cke(ddr4_c0_cke), + .c0_ddr4_cs_n(ddr4_c0_cs_n), + .c0_ddr4_dq(ddr4_c0_dq), + .c0_ddr4_dqs_t(ddr4_c0_dqs_t), + .c0_ddr4_dqs_c(ddr4_c0_dqs_c), + .c0_ddr4_dm_dbi_n(ddr4_c0_dm_dbi_n), + .c0_ddr4_odt(ddr4_c0_odt), + .c0_ddr4_bg(ddr4_c0_bg), + .c0_ddr4_reset_n(ddr4_c0_reset_n), + .c0_ddr4_act_n(ddr4_c0_act_n), + .c0_ddr4_ck_t(ddr4_c0_ck_t), + .c0_ddr4_ck_c(ddr4_c0_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[0 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[0 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c0_adr = {17{1'bz}}; +assign ddr4_c0_ba = {2{1'bz}}; +assign ddr4_c0_bg = {2{1'bz}}; +assign ddr4_c0_cke = 1'bz; +assign ddr4_c0_cs_n = 1'bz; +assign ddr4_c0_act_n = 1'bz; +assign ddr4_c0_odt = 1'bz; +assign ddr4_c0_reset_n = 1'b0; +assign ddr4_c0_dq = {80{1'bz}}; +assign ddr4_c0_dqs_t = {10{1'bz}}; +assign ddr4_c0_dqs_c = {10{1'bz}}; +assign ddr4_c0_dm_dbi_n = {10{1'bz}}; + +OBUFTDS ddr4_c0_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c0_ck_t), + .OB(ddr4_c0_ck_c) +); + +assign ddr_clk = 0; +assign ddr_rst = 0; + +assign m_axi_ddr_awready = 0; +assign m_axi_ddr_wready = 0; +assign m_axi_ddr_bid = 0; +assign m_axi_ddr_bresp = 0; +assign m_axi_ddr_bvalid = 0; +assign m_axi_ddr_arready = 0; +assign m_axi_ddr_rid = 0; +assign m_axi_ddr_rdata = 0; +assign m_axi_ddr_rresp = 0; +assign m_axi_ddr_rlast = 0; +assign m_axi_ddr_rvalid = 0; + +assign ddr_status = 0; + +end + +assign ddr4_c0_par = 1'b0; +assign ddr4_c0_ten = 1'b0; + +if (DDR_ENABLE && DDR_CH > 1) begin + +ddr4_0 ddr4_c1_inst ( + .c0_sys_clk_p(mem_clk_300mhz_1_p), + .c0_sys_clk_n(mem_clk_300mhz_1_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[1 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c1_adr), + .c0_ddr4_ba(ddr4_c1_ba), + .c0_ddr4_cke(ddr4_c1_cke), + .c0_ddr4_cs_n(ddr4_c1_cs_n), + .c0_ddr4_dq(ddr4_c1_dq), + .c0_ddr4_dqs_t(ddr4_c1_dqs_t), + .c0_ddr4_dqs_c(ddr4_c1_dqs_c), + .c0_ddr4_dm_dbi_n(ddr4_c1_dm_dbi_n), + .c0_ddr4_odt(ddr4_c1_odt), + .c0_ddr4_bg(ddr4_c1_bg), + .c0_ddr4_reset_n(ddr4_c1_reset_n), + .c0_ddr4_act_n(ddr4_c1_act_n), + .c0_ddr4_ck_t(ddr4_c1_ck_t), + .c0_ddr4_ck_c(ddr4_c1_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[1 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[1 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[1 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[1*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[1*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[1*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[1 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[1*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[1*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[1*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[1 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[1 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[1*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[1 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[1 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[1 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[1 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[1*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[1 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[1*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[1*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[1*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[1 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[1*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[1*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[1*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[1 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[1 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[1 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[1 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[1 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[1*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c1_adr = {17{1'bz}}; +assign ddr4_c1_ba = {2{1'bz}}; +assign ddr4_c1_bg = {2{1'bz}}; +assign ddr4_c1_cke = 1'bz; +assign ddr4_c1_cs_n = 1'bz; +assign ddr4_c1_act_n = 1'bz; +assign ddr4_c1_odt = 1'bz; +assign ddr4_c1_reset_n = 1'b0; +assign ddr4_c1_dq = {80{1'bz}}; +assign ddr4_c1_dqs_t = {10{1'bz}}; +assign ddr4_c1_dqs_c = {10{1'bz}}; +assign ddr4_c1_dm_dbi_n = {10{1'bz}}; + +OBUFTDS ddr4_c1_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c1_ck_t), + .OB(ddr4_c1_ck_c) +); + +end + +assign ddr4_c1_par = 1'b0; +assign ddr4_c1_ten = 1'b0; + +endgenerate + fpga_core #( // FW and board IDs .FPGA_ID(FPGA_ID), @@ -1433,6 +1783,16 @@ fpga_core #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1742,6 +2102,50 @@ core_inst ( .eeprom_i2c_sda_t(eeprom_i2c_sda_t), .eeprom_wp(eeprom_wp), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + /* * QSPI flash */ diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v index 731ed070e..dd8d628e9 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v @@ -122,6 +122,16 @@ module fpga_core # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // RAM configuration + parameter DDR_CH = 2, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 33, + parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -433,6 +443,52 @@ module fpga_core # output wire eeprom_i2c_sda_t, output wire eeprom_wp, + /* + * DDR + */ + input wire [DDR_CH-1:0] ddr_clk, + input wire [DDR_CH-1:0] ddr_rst, + + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, + output wire [DDR_CH-1:0] m_axi_ddr_awlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, + output wire [DDR_CH-1:0] m_axi_ddr_awvalid, + input wire [DDR_CH-1:0] m_axi_ddr_awready, + output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, + output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, + output wire [DDR_CH-1:0] m_axi_ddr_wlast, + output wire [DDR_CH-1:0] m_axi_ddr_wvalid, + input wire [DDR_CH-1:0] m_axi_ddr_wready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, + input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, + input wire [DDR_CH-1:0] m_axi_ddr_bvalid, + output wire [DDR_CH-1:0] m_axi_ddr_bready, + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, + output wire [DDR_CH-1:0] m_axi_ddr_arlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, + output wire [DDR_CH-1:0] m_axi_ddr_arvalid, + input wire [DDR_CH-1:0] m_axi_ddr_arready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, + input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, + input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, + input wire [DDR_CH-1:0] m_axi_ddr_rlast, + input wire [DDR_CH-1:0] m_axi_ddr_rvalid, + output wire [DDR_CH-1:0] m_axi_ddr_rready, + + input wire [DDR_CH-1:0] ddr_status, + /* * QSPI flash */ @@ -1161,6 +1217,25 @@ mqnic_core_pcie_us #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .DDR_GROUP_SIZE(1), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_AWUSER_ENABLE(0), + .AXI_DDR_WUSER_ENABLE(0), + .AXI_DDR_BUSER_ENABLE(0), + .AXI_DDR_ARUSER_ENABLE(0), + .AXI_DDR_RUSER_ENABLE(0), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + .AXI_DDR_FIXED_BURST(0), + .AXI_DDR_WRAP_BURST(1), + .HBM_ENABLE(0), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1438,6 +1513,108 @@ core_inst ( .eth_rx_status(eth_rx_status), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awuser(), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wuser(), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_buser(0), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_aruser(), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_ruser(0), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + + /* + * HBM + */ + .hbm_clk(0), + .hbm_rst(0), + + .m_axi_hbm_awid(), + .m_axi_hbm_awaddr(), + .m_axi_hbm_awlen(), + .m_axi_hbm_awsize(), + .m_axi_hbm_awburst(), + .m_axi_hbm_awlock(), + .m_axi_hbm_awcache(), + .m_axi_hbm_awprot(), + .m_axi_hbm_awqos(), + .m_axi_hbm_awuser(), + .m_axi_hbm_awvalid(), + .m_axi_hbm_awready(0), + .m_axi_hbm_wdata(), + .m_axi_hbm_wstrb(), + .m_axi_hbm_wlast(), + .m_axi_hbm_wuser(), + .m_axi_hbm_wvalid(), + .m_axi_hbm_wready(0), + .m_axi_hbm_bid(0), + .m_axi_hbm_bresp(0), + .m_axi_hbm_buser(0), + .m_axi_hbm_bvalid(0), + .m_axi_hbm_bready(), + .m_axi_hbm_arid(), + .m_axi_hbm_araddr(), + .m_axi_hbm_arlen(), + .m_axi_hbm_arsize(), + .m_axi_hbm_arburst(), + .m_axi_hbm_arlock(), + .m_axi_hbm_arcache(), + .m_axi_hbm_arprot(), + .m_axi_hbm_arqos(), + .m_axi_hbm_aruser(), + .m_axi_hbm_arvalid(), + .m_axi_hbm_arready(0), + .m_axi_hbm_rid(0), + .m_axi_hbm_rdata(0), + .m_axi_hbm_rresp(0), + .m_axi_hbm_rlast(0), + .m_axi_hbm_ruser(0), + .m_axi_hbm_rvalid(0), + .m_axi_hbm_rready(), + + .hbm_status(0), + /* * Statistics input */ diff --git a/fpga/mqnic/AU200/fpga_100g/README.md b/fpga/mqnic/AU200/fpga_100g/README.md index d3fe85385..7e4fffa57 100644 --- a/fpga/mqnic/AU200/fpga_100g/README.md +++ b/fpga/mqnic/AU200/fpga_100g/README.md @@ -7,6 +7,7 @@ This design targets the Xilinx Alveo U200 FPGA board. * FPGA: xcu200-fsgd2104-2-e * MAC: Xilinx 100G CMAC * PHY: 100G CAUI-4 CMAC and internal GTY transceivers +* RAM: 64 GB DDR4 2400 (4x 2G x72 DIMM) ## How to build diff --git a/fpga/mqnic/AU200/fpga_100g/fpga.xdc b/fpga/mqnic/AU200/fpga_100g/fpga.xdc index c83afd19b..9c3423356 100644 --- a/fpga/mqnic/AU200/fpga_100g/fpga.xdc +++ b/fpga/mqnic/AU200/fpga_100g/fpga.xdc @@ -17,23 +17,23 @@ set_operating_conditions -design_power_budget 160 # System clocks # 300 MHz (DDR 0) -#set_property -dict {LOC AY37 IOSTANDARD LVDS} [get_ports clk_300mhz_0_p] -#set_property -dict {LOC AY38 IOSTANDARD LVDS} [get_ports clk_300mhz_0_n] +set_property -dict {LOC AY37 IOSTANDARD LVDS} [get_ports clk_300mhz_0_p] +set_property -dict {LOC AY38 IOSTANDARD LVDS} [get_ports clk_300mhz_0_n] #create_clock -period 3.333 -name clk_300mhz_0 [get_ports clk_300mhz_0_p] # 300 MHz (DDR 1) -#set_property -dict {LOC AW20 IOSTANDARD LVDS} [get_ports clk_300mhz_1_p] -#set_property -dict {LOC AW19 IOSTANDARD LVDS} [get_ports clk_300mhz_1_n] +set_property -dict {LOC AW20 IOSTANDARD LVDS} [get_ports clk_300mhz_1_p] +set_property -dict {LOC AW19 IOSTANDARD LVDS} [get_ports clk_300mhz_1_n] #create_clock -period 3.333 -name clk_300mhz_1 [get_ports clk_300mhz_1_p] # 300 MHz (DDR 2) -#set_property -dict {LOC F32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_p] -#set_property -dict {LOC E32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_n] +set_property -dict {LOC F32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_p] +set_property -dict {LOC E32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_n] #create_clock -period 3.333 -name clk_300mhz_2 [get_ports clk_300mhz_2_p] # 300 MHz (DDR 3) -#set_property -dict {LOC J16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_p] -#set_property -dict {LOC H16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_n] +set_property -dict {LOC J16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_p] +set_property -dict {LOC H16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_n] #create_clock -period 3.333 -name clk_300mhz_3 [get_ports clk_300mhz_3_p] # SI570 user clock @@ -257,3 +257,591 @@ create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_p] set_false_path -from [get_ports {pcie_reset_n}] set_input_delay 0 [get_ports {pcie_reset_n}] + +# DDR4 C0 +set_property -dict {LOC AT36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}] +set_property -dict {LOC AV36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}] +set_property -dict {LOC AV37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}] +set_property -dict {LOC AW35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}] +set_property -dict {LOC AW36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}] +set_property -dict {LOC AY36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}] +set_property -dict {LOC AY35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}] +set_property -dict {LOC BA40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}] +set_property -dict {LOC BA37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}] +set_property -dict {LOC BB37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}] +set_property -dict {LOC AR35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}] +set_property -dict {LOC BA39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}] +set_property -dict {LOC BB40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}] +set_property -dict {LOC AN36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}] +set_property -dict {LOC AP35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}] +set_property -dict {LOC AP36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}] +set_property -dict {LOC AR36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}] +set_property -dict {LOC AT35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}] +set_property -dict {LOC AT34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}] +set_property -dict {LOC BC37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}] +set_property -dict {LOC BC39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}] +set_property -dict {LOC AV38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t[0]}] +set_property -dict {LOC AW38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c[0]}] +#set_property -dict {LOC AU34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t[1]}] +#set_property -dict {LOC AU35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c[1]}] +set_property -dict {LOC BC38 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[0]}] +#set_property -dict {LOC BC40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[1]}] +set_property -dict {LOC AR33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[0]}] +#set_property -dict {LOC AP33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[1]}] +#set_property -dict {LOC AN33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[2]}] +#set_property -dict {LOC AM34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[3]}] +set_property -dict {LOC BB39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}] +set_property -dict {LOC AP34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[0]}] +#set_property -dict {LOC AN34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[1]}] +set_property -dict {LOC AU36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}] +set_property -dict {LOC AU31 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_reset_n}] + +set_property -dict {LOC AW28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}] +set_property -dict {LOC AW29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}] +set_property -dict {LOC BA28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}] +set_property -dict {LOC BA27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}] +set_property -dict {LOC BB29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}] +set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}] +set_property -dict {LOC BC27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}] +set_property -dict {LOC BB27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}] +set_property -dict {LOC BE28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}] +set_property -dict {LOC BF28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}] +set_property -dict {LOC BE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}] +set_property -dict {LOC BD30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}] +set_property -dict {LOC BF27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}] +set_property -dict {LOC BE27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}] +set_property -dict {LOC BF30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}] +set_property -dict {LOC BF29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}] +set_property -dict {LOC BB31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}] +set_property -dict {LOC BB32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}] +set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}] +set_property -dict {LOC AY33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}] +set_property -dict {LOC BC32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}] +set_property -dict {LOC BC33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}] +set_property -dict {LOC BB34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}] +set_property -dict {LOC BC34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}] +set_property -dict {LOC AV31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}] +set_property -dict {LOC AV32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}] +set_property -dict {LOC AV34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}] +set_property -dict {LOC AW34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}] +set_property -dict {LOC AW31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}] +set_property -dict {LOC AY31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}] +set_property -dict {LOC BA35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}] +set_property -dict {LOC BA34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}] +set_property -dict {LOC AL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}] +set_property -dict {LOC AM30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}] +set_property -dict {LOC AU32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}] +set_property -dict {LOC AT32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}] +set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}] +set_property -dict {LOC AN32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}] +set_property -dict {LOC AR32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}] +set_property -dict {LOC AR31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}] +set_property -dict {LOC AP29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}] +set_property -dict {LOC AP28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}] +set_property -dict {LOC AN27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}] +set_property -dict {LOC AM27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}] +set_property -dict {LOC AN29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}] +set_property -dict {LOC AM29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}] +set_property -dict {LOC AR27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}] +set_property -dict {LOC AR28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}] +set_property -dict {LOC AT28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}] +set_property -dict {LOC AV27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}] +set_property -dict {LOC AU27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}] +set_property -dict {LOC AT27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}] +set_property -dict {LOC AV29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}] +set_property -dict {LOC AY30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}] +set_property -dict {LOC AW30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}] +set_property -dict {LOC AV28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}] +set_property -dict {LOC BD34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}] +set_property -dict {LOC BD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}] +set_property -dict {LOC BE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}] +set_property -dict {LOC BD35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}] +set_property -dict {LOC BF32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}] +set_property -dict {LOC BF33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}] +set_property -dict {LOC BF34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}] +set_property -dict {LOC BF35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}] +set_property -dict {LOC BD40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}] +set_property -dict {LOC BD39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}] +set_property -dict {LOC BF43 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}] +set_property -dict {LOC BF42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}] +set_property -dict {LOC BF37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}] +set_property -dict {LOC BE37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}] +set_property -dict {LOC BE40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}] +set_property -dict {LOC BF41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}] +set_property -dict {LOC BA30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}] +set_property -dict {LOC BB30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}] +set_property -dict {LOC BB26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}] +set_property -dict {LOC BC26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}] +set_property -dict {LOC BD28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}] +set_property -dict {LOC BD29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}] +set_property -dict {LOC BD26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}] +set_property -dict {LOC BE26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}] +set_property -dict {LOC BB35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}] +set_property -dict {LOC BB36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}] +set_property -dict {LOC BC31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}] +set_property -dict {LOC BD31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}] +set_property -dict {LOC AV33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}] +set_property -dict {LOC AW33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}] +set_property -dict {LOC BA32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}] +set_property -dict {LOC BA33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}] +set_property -dict {LOC AM31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}] +set_property -dict {LOC AM32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}] +set_property -dict {LOC AP30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[9]}] +set_property -dict {LOC AP31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[9]}] +set_property -dict {LOC AL28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[10]}] +set_property -dict {LOC AL29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[10]}] +set_property -dict {LOC AR30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[11]}] +set_property -dict {LOC AT30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[11]}] +set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[12]}] +set_property -dict {LOC AU30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[12]}] +set_property -dict {LOC AY27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[13]}] +set_property -dict {LOC AY28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[13]}] +set_property -dict {LOC BE35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[14]}] +set_property -dict {LOC BE36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[14]}] +set_property -dict {LOC BE31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[15]}] +set_property -dict {LOC BE32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[15]}] +set_property -dict {LOC BE38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[16]}] +set_property -dict {LOC BF38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[16]}] +set_property -dict {LOC BF39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[17]}] +set_property -dict {LOC BF40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[17]}] + +# DDR4 C1 +set_property -dict {LOC AN24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}] +set_property -dict {LOC AT24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}] +set_property -dict {LOC AW24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}] +set_property -dict {LOC AN26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}] +set_property -dict {LOC AY22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}] +set_property -dict {LOC AY23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}] +set_property -dict {LOC AV24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}] +set_property -dict {LOC BA22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}] +set_property -dict {LOC AY25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}] +set_property -dict {LOC BA23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}] +set_property -dict {LOC AM26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}] +set_property -dict {LOC BA25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}] +set_property -dict {LOC BB22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}] +set_property -dict {LOC AL24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}] +set_property -dict {LOC AL25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}] +set_property -dict {LOC AM25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}] +set_property -dict {LOC AN23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}] +set_property -dict {LOC AU24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}] +set_property -dict {LOC AP26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}] +set_property -dict {LOC BC22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}] +set_property -dict {LOC AW26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}] +set_property -dict {LOC AT25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t[0]}] +set_property -dict {LOC AU25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c[0]}] +#set_property -dict {LOC AU26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t[1]}] +#set_property -dict {LOC AV26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c[1]}] +set_property -dict {LOC BB25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[0]}] +#set_property -dict {LOC BB24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[1]}] +set_property -dict {LOC AV23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[0]}] +#set_property -dict {LOC AP25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[1]}] +#set_property -dict {LOC AR23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[2]}] +#set_property -dict {LOC AP23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[3]}] +set_property -dict {LOC AW25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}] +set_property -dict {LOC AW23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[0]}] +#set_property -dict {LOC AP24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[1]}] +set_property -dict {LOC AT23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}] +set_property -dict {LOC AR17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}] + +set_property -dict {LOC BD9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] +set_property -dict {LOC BD7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] +set_property -dict {LOC BC7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] +set_property -dict {LOC BD8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] +set_property -dict {LOC BD10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] +set_property -dict {LOC BE10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] +set_property -dict {LOC BE7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] +set_property -dict {LOC BF7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] +set_property -dict {LOC AU13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] +set_property -dict {LOC AV13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] +set_property -dict {LOC AW13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] +set_property -dict {LOC AW14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] +set_property -dict {LOC AU14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] +set_property -dict {LOC AY11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] +set_property -dict {LOC AV14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] +set_property -dict {LOC BA11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] +set_property -dict {LOC BA12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] +set_property -dict {LOC BB12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] +set_property -dict {LOC BA13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] +set_property -dict {LOC BA14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] +set_property -dict {LOC BC9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] +set_property -dict {LOC BB9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] +set_property -dict {LOC BA7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] +set_property -dict {LOC BA8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] +set_property -dict {LOC AN13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] +set_property -dict {LOC AR13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] +set_property -dict {LOC AM13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] +set_property -dict {LOC AP13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] +set_property -dict {LOC AM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] +set_property -dict {LOC AR15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] +set_property -dict {LOC AL14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] +set_property -dict {LOC AT15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] +set_property -dict {LOC BE13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] +set_property -dict {LOC BD14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] +set_property -dict {LOC BF12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] +set_property -dict {LOC BD13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] +set_property -dict {LOC BD15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] +set_property -dict {LOC BD16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] +set_property -dict {LOC BF14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] +set_property -dict {LOC BF13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] +set_property -dict {LOC AY17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] +set_property -dict {LOC BA17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] +set_property -dict {LOC AY18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] +set_property -dict {LOC BA18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] +set_property -dict {LOC BA15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] +set_property -dict {LOC BB15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] +set_property -dict {LOC BC11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] +set_property -dict {LOC BD11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] +set_property -dict {LOC AV16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] +set_property -dict {LOC AV17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] +set_property -dict {LOC AU16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] +set_property -dict {LOC AU17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] +set_property -dict {LOC BB17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] +set_property -dict {LOC BB16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] +set_property -dict {LOC AT18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] +set_property -dict {LOC AT17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] +set_property -dict {LOC AM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] +set_property -dict {LOC AL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] +set_property -dict {LOC AN17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] +set_property -dict {LOC AN16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] +set_property -dict {LOC AR18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] +set_property -dict {LOC AP18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] +set_property -dict {LOC AL17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] +set_property -dict {LOC AL16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] +set_property -dict {LOC BF25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}] +set_property -dict {LOC BF24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}] +set_property -dict {LOC BD25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}] +set_property -dict {LOC BE25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}] +set_property -dict {LOC BD23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}] +set_property -dict {LOC BC23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}] +set_property -dict {LOC BF23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}] +set_property -dict {LOC BE23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}] +set_property -dict {LOC BF10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] +set_property -dict {LOC BF9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] +set_property -dict {LOC BE8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] +set_property -dict {LOC BF8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] +set_property -dict {LOC AW15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] +set_property -dict {LOC AY15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] +set_property -dict {LOC AY13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] +set_property -dict {LOC AY12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] +set_property -dict {LOC BB11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] +set_property -dict {LOC BB10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] +set_property -dict {LOC BA10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] +set_property -dict {LOC BA9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] +set_property -dict {LOC AT14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] +set_property -dict {LOC AT13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] +set_property -dict {LOC AN14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] +set_property -dict {LOC AP14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] +set_property -dict {LOC BE12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}] +set_property -dict {LOC BE11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}] +set_property -dict {LOC BE15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}] +set_property -dict {LOC BF15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}] +set_property -dict {LOC BC13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[10]}] +set_property -dict {LOC BC12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[10]}] +set_property -dict {LOC BB14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[11]}] +set_property -dict {LOC BC14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[11]}] +set_property -dict {LOC AV18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[12]}] +set_property -dict {LOC AW18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[12]}] +set_property -dict {LOC AW16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[13]}] +set_property -dict {LOC AY16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[13]}] +set_property -dict {LOC AP16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[14]}] +set_property -dict {LOC AR16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[14]}] +set_property -dict {LOC AM17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[15]}] +set_property -dict {LOC AM16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[15]}] +set_property -dict {LOC BC24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[16]}] +set_property -dict {LOC BD24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[16]}] +set_property -dict {LOC BE22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[17]}] +set_property -dict {LOC BF22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[17]}] + +# DDR4 C2 +set_property -dict {LOC L29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[0]}] +set_property -dict {LOC A33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[1]}] +set_property -dict {LOC C33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[2]}] +set_property -dict {LOC J29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[3]}] +set_property -dict {LOC H31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[4]}] +set_property -dict {LOC G31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[5]}] +set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[6]}] +set_property -dict {LOC B32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[7]}] +set_property -dict {LOC A32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[8]}] +set_property -dict {LOC D31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[9]}] +set_property -dict {LOC A34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[10]}] +set_property -dict {LOC E31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[11]}] +set_property -dict {LOC M30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[12]}] +set_property -dict {LOC F33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[13]}] +set_property -dict {LOC A35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[14]}] +set_property -dict {LOC G32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[15]}] +set_property -dict {LOC K30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[16]}] +set_property -dict {LOC D33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[0]}] +set_property -dict {LOC B36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[1]}] +set_property -dict {LOC C31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[0]}] +set_property -dict {LOC J30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[1]}] +set_property -dict {LOC C34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t[0]}] +set_property -dict {LOC B34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c[0]}] +#set_property -dict {LOC D34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t[1]}] +#set_property -dict {LOC D35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c[1]}] +set_property -dict {LOC G30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[0]}] +#set_property -dict {LOC E30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[1]}] +set_property -dict {LOC B35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[0]}] +#set_property -dict {LOC J31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[1]}] +#set_property -dict {LOC L30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[2]}] +#set_property -dict {LOC K31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[3]}] +set_property -dict {LOC B31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_act_n}] +set_property -dict {LOC E33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[0]}] +#set_property -dict {LOC F34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[1]}] +set_property -dict {LOC M29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_par}] +set_property -dict {LOC D36 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_reset_n}] + +set_property -dict {LOC R25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[0]}] +set_property -dict {LOC P25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[1]}] +set_property -dict {LOC M25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[2]}] +set_property -dict {LOC L25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[3]}] +set_property -dict {LOC P26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[4]}] +set_property -dict {LOC R26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[5]}] +set_property -dict {LOC N27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[6]}] +set_property -dict {LOC N28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[7]}] +set_property -dict {LOC J28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[8]}] +set_property -dict {LOC H29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[9]}] +set_property -dict {LOC H28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[10]}] +set_property -dict {LOC G29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[11]}] +set_property -dict {LOC K25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[12]}] +set_property -dict {LOC L27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[13]}] +set_property -dict {LOC K26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[14]}] +set_property -dict {LOC K27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[15]}] +set_property -dict {LOC F27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[16]}] +set_property -dict {LOC E27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[17]}] +set_property -dict {LOC E28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[18]}] +set_property -dict {LOC D28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[19]}] +set_property -dict {LOC G27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[20]}] +set_property -dict {LOC G26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[21]}] +set_property -dict {LOC F28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[22]}] +set_property -dict {LOC F29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[23]}] +set_property -dict {LOC D26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[24]}] +set_property -dict {LOC C26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[25]}] +set_property -dict {LOC B27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[26]}] +set_property -dict {LOC B26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[27]}] +set_property -dict {LOC A29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[28]}] +set_property -dict {LOC A30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[29]}] +set_property -dict {LOC C27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[30]}] +set_property -dict {LOC C28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[31]}] +set_property -dict {LOC F35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[32]}] +set_property -dict {LOC E38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[33]}] +set_property -dict {LOC D38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[34]}] +set_property -dict {LOC E35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[35]}] +set_property -dict {LOC E36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[36]}] +set_property -dict {LOC E37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[37]}] +set_property -dict {LOC F38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[38]}] +set_property -dict {LOC G38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[39]}] +set_property -dict {LOC P30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[40]}] +set_property -dict {LOC R30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[41]}] +set_property -dict {LOC P29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[42]}] +set_property -dict {LOC N29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[43]}] +set_property -dict {LOC L32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[44]}] +set_property -dict {LOC M32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[45]}] +set_property -dict {LOC P31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[46]}] +set_property -dict {LOC N32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[47]}] +set_property -dict {LOC J35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[48]}] +set_property -dict {LOC K35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[49]}] +set_property -dict {LOC L33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[50]}] +set_property -dict {LOC K33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[51]}] +set_property -dict {LOC J34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[52]}] +set_property -dict {LOC J33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[53]}] +set_property -dict {LOC N34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[54]}] +set_property -dict {LOC P34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[55]}] +set_property -dict {LOC H36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[56]}] +set_property -dict {LOC G36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[57]}] +set_property -dict {LOC H37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[58]}] +set_property -dict {LOC J36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[59]}] +set_property -dict {LOC K37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[60]}] +set_property -dict {LOC K38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[61]}] +set_property -dict {LOC G35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[62]}] +set_property -dict {LOC G34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[63]}] +set_property -dict {LOC C36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[64]}] +set_property -dict {LOC B37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[65]}] +set_property -dict {LOC A37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[66]}] +set_property -dict {LOC A38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[67]}] +set_property -dict {LOC C39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[68]}] +set_property -dict {LOC D39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[69]}] +set_property -dict {LOC A40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[70]}] +set_property -dict {LOC B40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[71]}] +set_property -dict {LOC N26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[0]}] +set_property -dict {LOC M26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[0]}] +set_property -dict {LOC R28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[1]}] +set_property -dict {LOC P28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[1]}] +set_property -dict {LOC J25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[2]}] +set_property -dict {LOC J26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[2]}] +set_property -dict {LOC M27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[3]}] +set_property -dict {LOC L28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[3]}] +set_property -dict {LOC D29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[4]}] +set_property -dict {LOC D30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[4]}] +set_property -dict {LOC H26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[5]}] +set_property -dict {LOC H27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[5]}] +set_property -dict {LOC A27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[6]}] +set_property -dict {LOC A28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[6]}] +set_property -dict {LOC C29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[7]}] +set_property -dict {LOC B29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[7]}] +set_property -dict {LOC E39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[8]}] +set_property -dict {LOC E40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[8]}] +set_property -dict {LOC G37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[9]}] +set_property -dict {LOC F37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[9]}] +set_property -dict {LOC N31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[10]}] +set_property -dict {LOC M31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[10]}] +set_property -dict {LOC T30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[11]}] +set_property -dict {LOC R31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[11]}] +set_property -dict {LOC L35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[12]}] +set_property -dict {LOC L36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[12]}] +set_property -dict {LOC M34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[13]}] +set_property -dict {LOC L34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[13]}] +set_property -dict {LOC J38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[14]}] +set_property -dict {LOC H38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[14]}] +set_property -dict {LOC H33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[15]}] +set_property -dict {LOC H34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[15]}] +set_property -dict {LOC B39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[16]}] +set_property -dict {LOC A39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[16]}] +set_property -dict {LOC C37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[17]}] +set_property -dict {LOC C38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[17]}] + +# DDR4 C3 +set_property -dict {LOC K15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[0]}] +set_property -dict {LOC B15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[1]}] +set_property -dict {LOC F14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[2]}] +set_property -dict {LOC A15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[3]}] +set_property -dict {LOC C14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[4]}] +set_property -dict {LOC A14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[5]}] +set_property -dict {LOC B14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[6]}] +set_property -dict {LOC E13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[7]}] +set_property -dict {LOC F13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[8]}] +set_property -dict {LOC A13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[9]}] +set_property -dict {LOC D14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[10]}] +set_property -dict {LOC C13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[11]}] +set_property -dict {LOC B13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[12]}] +set_property -dict {LOC K16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[13]}] +set_property -dict {LOC D15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[14]}] +set_property -dict {LOC E15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[15]}] +set_property -dict {LOC F15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[16]}] +set_property -dict {LOC J15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[0]}] +set_property -dict {LOC H14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[1]}] +set_property -dict {LOC D13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[0]}] +set_property -dict {LOC J13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[1]}] +set_property -dict {LOC L14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t[0]}] +set_property -dict {LOC L13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c[0]}] +#set_property -dict {LOC G14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t[1]}] +#set_property -dict {LOC G13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c[1]}] +set_property -dict {LOC K13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[0]}] +#set_property -dict {LOC L15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[1]}] +set_property -dict {LOC B16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[0]}] +#set_property -dict {LOC D16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[1]}] +#set_property -dict {LOC M14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[2]}] +#set_property -dict {LOC M13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[3]}] +set_property -dict {LOC H13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_act_n}] +set_property -dict {LOC C16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[0]}] +#set_property -dict {LOC E16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[1]}] +set_property -dict {LOC J14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_par}] +set_property -dict {LOC D21 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c3_reset_n}] + +set_property -dict {LOC P24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[0]}] +set_property -dict {LOC N24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[1]}] +set_property -dict {LOC T24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[2]}] +set_property -dict {LOC R23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[3]}] +set_property -dict {LOC N23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[4]}] +set_property -dict {LOC P21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[5]}] +set_property -dict {LOC P23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[6]}] +set_property -dict {LOC R21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[7]}] +set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[8]}] +set_property -dict {LOC J23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[9]}] +set_property -dict {LOC H24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[10]}] +set_property -dict {LOC G24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[11]}] +set_property -dict {LOC L24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[12]}] +set_property -dict {LOC L23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[13]}] +set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[14]}] +set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[15]}] +set_property -dict {LOC G20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[16]}] +set_property -dict {LOC H17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[17]}] +set_property -dict {LOC F19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[18]}] +set_property -dict {LOC G17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[19]}] +set_property -dict {LOC J20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[20]}] +set_property -dict {LOC L19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[21]}] +set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[22]}] +set_property -dict {LOC J19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[23]}] +set_property -dict {LOC M19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[24]}] +set_property -dict {LOC M20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[25]}] +set_property -dict {LOC R18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[26]}] +set_property -dict {LOC R17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[27]}] +set_property -dict {LOC R20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[28]}] +set_property -dict {LOC T20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[29]}] +set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[30]}] +set_property -dict {LOC N19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[31]}] +set_property -dict {LOC A23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[32]}] +set_property -dict {LOC A22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[33]}] +set_property -dict {LOC B24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[34]}] +set_property -dict {LOC B25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[35]}] +set_property -dict {LOC B22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[36]}] +set_property -dict {LOC C22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[37]}] +set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[38]}] +set_property -dict {LOC C23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[39]}] +set_property -dict {LOC C19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[40]}] +set_property -dict {LOC C18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[41]}] +set_property -dict {LOC C21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[42]}] +set_property -dict {LOC B21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[43]}] +set_property -dict {LOC A18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[44]}] +set_property -dict {LOC A17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[45]}] +set_property -dict {LOC A20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[46]}] +set_property -dict {LOC B20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[47]}] +set_property -dict {LOC E17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[48]}] +set_property -dict {LOC F20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[49]}] +set_property -dict {LOC E18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[50]}] +set_property -dict {LOC E20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[51]}] +set_property -dict {LOC D19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[52]}] +set_property -dict {LOC D20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[53]}] +set_property -dict {LOC H18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[54]}] +set_property -dict {LOC J18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[55]}] +set_property -dict {LOC F22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[56]}] +set_property -dict {LOC E22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[57]}] +set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[58]}] +set_property -dict {LOC G21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[59]}] +set_property -dict {LOC F24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[60]}] +set_property -dict {LOC E25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[61]}] +set_property -dict {LOC F25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[62]}] +set_property -dict {LOC G25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[63]}] +set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[64]}] +set_property -dict {LOC N16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[65]}] +set_property -dict {LOC N13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[66]}] +set_property -dict {LOC N14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[67]}] +set_property -dict {LOC T15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[68]}] +set_property -dict {LOC R15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[69]}] +set_property -dict {LOC P13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[70]}] +set_property -dict {LOC P14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[71]}] +set_property -dict {LOC T22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[0]}] +set_property -dict {LOC R22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[0]}] +set_property -dict {LOC N22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[1]}] +set_property -dict {LOC N21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[1]}] +set_property -dict {LOC J21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[2]}] +set_property -dict {LOC H21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[2]}] +set_property -dict {LOC M22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[3]}] +set_property -dict {LOC L22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[3]}] +set_property -dict {LOC L20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[4]}] +set_property -dict {LOC K20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[4]}] +set_property -dict {LOC K18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[5]}] +set_property -dict {LOC K17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[5]}] +set_property -dict {LOC P19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[6]}] +set_property -dict {LOC P18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[6]}] +set_property -dict {LOC N17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[7]}] +set_property -dict {LOC M17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[7]}] +set_property -dict {LOC A25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[8]}] +set_property -dict {LOC A24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[8]}] +set_property -dict {LOC D24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[9]}] +set_property -dict {LOC D23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[9]}] +set_property -dict {LOC C17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[10]}] +set_property -dict {LOC B17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[10]}] +set_property -dict {LOC B19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[11]}] +set_property -dict {LOC A19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[11]}] +set_property -dict {LOC F18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[12]}] +set_property -dict {LOC F17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[12]}] +set_property -dict {LOC H19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[13]}] +set_property -dict {LOC G19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[13]}] +set_property -dict {LOC F23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[14]}] +set_property -dict {LOC E23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[14]}] +set_property -dict {LOC H23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[15]}] +set_property -dict {LOC H22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[15]}] +set_property -dict {LOC R16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[16]}] +set_property -dict {LOC P15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[16]}] +set_property -dict {LOC T13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[17]}] +set_property -dict {LOC R13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[17]}] diff --git a/fpga/mqnic/AU200/fpga_100g/fpga/Makefile b/fpga/mqnic/AU200/fpga_100g/fpga/Makefile index 8c627182b..f13ace56c 100644 --- a/fpga/mqnic/AU200/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/AU200/fpga_100g/fpga/Makefile @@ -125,6 +125,7 @@ IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/cmac_usplus_0.tcl IP_TCL_FILES += ip/cmac_usplus_1.tcl IP_TCL_FILES += ip/cms.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/AU200/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU200/fpga_100g/fpga/config.tcl index cd99ce297..bc354ac6d 100644 --- a/fpga/mqnic/AU200/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/AU200/fpga_100g/fpga/config.tcl @@ -136,6 +136,12 @@ dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "131072" dict set params RX_RAM_SIZE "131072" + +# RAM configuration +dict set params DDR_CH "4" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" # Application block configuration dict set params APP_ID "32'h00000000" @@ -187,6 +193,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/AU200/fpga_100g/ip/ddr4_0.tcl b/fpga/mqnic/AU200/fpga_100g/ip/ddr4_0.tcl new file mode 100644 index 000000000..27252f502 --- /dev/null +++ b/fpga/mqnic/AU200/fpga_100g/ip/ddr4_0.tcl @@ -0,0 +1,17 @@ + +create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 + +set_property -dict [list \ + CONFIG.C0.DDR4_AxiSelection {true} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_AxiIDWidth {8} \ + CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ + CONFIG.C0.DDR4_TimePeriod {833} \ + CONFIG.C0.DDR4_InputClockPeriod {3332} \ + CONFIG.C0.DDR4_MemoryType {RDIMMs} \ + CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PZ-2G3} \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_CasLatency {17} \ + CONFIG.C0.DDR4_CasWriteLatency {12} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} +] [get_ips ddr4_0] diff --git a/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v index 4ab880ab5..08ac520c4 100644 --- a/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/AU200/fpga_100g/rtl/fpga.v @@ -109,6 +109,15 @@ module fpga # parameter TX_RAM_SIZE = 131072, parameter RX_RAM_SIZE = 131072, + // RAM configuration + parameter DDR_CH = 4, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 34, + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -173,6 +182,18 @@ module fpga # parameter STAT_ID_WIDTH = 12 ) ( + /* + * Clock and reset + */ + input wire clk_300mhz_0_p, + input wire clk_300mhz_0_n, + input wire clk_300mhz_1_p, + input wire clk_300mhz_1_n, + input wire clk_300mhz_2_p, + input wire clk_300mhz_2_n, + input wire clk_300mhz_3_p, + input wire clk_300mhz_3_n, + /* * GPIO */ @@ -256,7 +277,70 @@ module fpga # input wire qsfp1_intl, output wire qsfp1_lpmode, output wire qsfp1_refclk_reset, - output wire [1:0] qsfp1_fs + output wire [1:0] qsfp1_fs, + + /* + * DDR4 + */ + output wire [16:0] ddr4_c0_adr, + output wire [1:0] ddr4_c0_ba, + output wire [1:0] ddr4_c0_bg, + output wire [0:0] ddr4_c0_ck_t, + output wire [0:0] ddr4_c0_ck_c, + output wire [0:0] ddr4_c0_cke, + output wire [0:0] ddr4_c0_cs_n, + output wire ddr4_c0_act_n, + output wire [0:0] ddr4_c0_odt, + output wire ddr4_c0_par, + output wire ddr4_c0_reset_n, + inout wire [71:0] ddr4_c0_dq, + inout wire [17:0] ddr4_c0_dqs_t, + inout wire [17:0] ddr4_c0_dqs_c, + + output wire [16:0] ddr4_c1_adr, + output wire [1:0] ddr4_c1_ba, + output wire [1:0] ddr4_c1_bg, + output wire [0:0] ddr4_c1_ck_t, + output wire [0:0] ddr4_c1_ck_c, + output wire [0:0] ddr4_c1_cke, + output wire [0:0] ddr4_c1_cs_n, + output wire ddr4_c1_act_n, + output wire [0:0] ddr4_c1_odt, + output wire ddr4_c1_par, + output wire ddr4_c1_reset_n, + inout wire [71:0] ddr4_c1_dq, + inout wire [17:0] ddr4_c1_dqs_t, + inout wire [17:0] ddr4_c1_dqs_c, + + output wire [16:0] ddr4_c2_adr, + output wire [1:0] ddr4_c2_ba, + output wire [1:0] ddr4_c2_bg, + output wire [0:0] ddr4_c2_ck_t, + output wire [0:0] ddr4_c2_ck_c, + output wire [0:0] ddr4_c2_cke, + output wire [0:0] ddr4_c2_cs_n, + output wire ddr4_c2_act_n, + output wire [0:0] ddr4_c2_odt, + output wire ddr4_c2_par, + output wire ddr4_c2_reset_n, + inout wire [71:0] ddr4_c2_dq, + inout wire [17:0] ddr4_c2_dqs_t, + inout wire [17:0] ddr4_c2_dqs_c, + + output wire [16:0] ddr4_c3_adr, + output wire [1:0] ddr4_c3_ba, + output wire [1:0] ddr4_c3_bg, + output wire [0:0] ddr4_c3_ck_t, + output wire [0:0] ddr4_c3_ck_c, + output wire [0:0] ddr4_c3_cke, + output wire [0:0] ddr4_c3_cs_n, + output wire ddr4_c3_act_n, + output wire [0:0] ddr4_c3_odt, + output wire ddr4_c3_par, + output wire ddr4_c3_reset_n, + inout wire [71:0] ddr4_c3_dq, + inout wire [17:0] ddr4_c3_dqs_t, + inout wire [17:0] ddr4_c3_dqs_c ); // PTP configuration @@ -269,6 +353,9 @@ parameter PTP_SEPARATE_RX_CLOCK = 1; // Interface configuration parameter TX_TAG_WIDTH = 16; +// RAM configuration +parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8); + // Ethernet interface configuration parameter AXIS_ETH_DATA_WIDTH = 512; parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; @@ -1889,6 +1976,519 @@ assign led[0] = led_int[0]; // red assign led[1] = qsfp1_rx_status; // yellow assign led[2] = qsfp0_rx_status; // green +// DDR4 +wire [DDR_CH-1:0] ddr_clk; +wire [DDR_CH-1:0] ddr_rst; + +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr; +wire [DDR_CH*8-1:0] m_axi_ddr_awlen; +wire [DDR_CH*3-1:0] m_axi_ddr_awsize; +wire [DDR_CH*2-1:0] m_axi_ddr_awburst; +wire [DDR_CH-1:0] m_axi_ddr_awlock; +wire [DDR_CH*4-1:0] m_axi_ddr_awcache; +wire [DDR_CH*3-1:0] m_axi_ddr_awprot; +wire [DDR_CH*4-1:0] m_axi_ddr_awqos; +wire [DDR_CH-1:0] m_axi_ddr_awvalid; +wire [DDR_CH-1:0] m_axi_ddr_awready; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata; +wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb; +wire [DDR_CH-1:0] m_axi_ddr_wlast; +wire [DDR_CH-1:0] m_axi_ddr_wvalid; +wire [DDR_CH-1:0] m_axi_ddr_wready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid; +wire [DDR_CH*2-1:0] m_axi_ddr_bresp; +wire [DDR_CH-1:0] m_axi_ddr_bvalid; +wire [DDR_CH-1:0] m_axi_ddr_bready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr; +wire [DDR_CH*8-1:0] m_axi_ddr_arlen; +wire [DDR_CH*3-1:0] m_axi_ddr_arsize; +wire [DDR_CH*2-1:0] m_axi_ddr_arburst; +wire [DDR_CH-1:0] m_axi_ddr_arlock; +wire [DDR_CH*4-1:0] m_axi_ddr_arcache; +wire [DDR_CH*3-1:0] m_axi_ddr_arprot; +wire [DDR_CH*4-1:0] m_axi_ddr_arqos; +wire [DDR_CH-1:0] m_axi_ddr_arvalid; +wire [DDR_CH-1:0] m_axi_ddr_arready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata; +wire [DDR_CH*2-1:0] m_axi_ddr_rresp; +wire [DDR_CH-1:0] m_axi_ddr_rlast; +wire [DDR_CH-1:0] m_axi_ddr_rvalid; +wire [DDR_CH-1:0] m_axi_ddr_rready; + +wire [DDR_CH-1:0] ddr_status; + +generate + +if (DDR_ENABLE && DDR_CH > 0) begin + +ddr4_0 ddr4_c0_inst ( + .c0_sys_clk_p(clk_300mhz_0_p), + .c0_sys_clk_n(clk_300mhz_0_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[0 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c0_adr), + .c0_ddr4_ba(ddr4_c0_ba), + .c0_ddr4_cke(ddr4_c0_cke), + .c0_ddr4_cs_n(ddr4_c0_cs_n), + .c0_ddr4_dq(ddr4_c0_dq), + .c0_ddr4_dqs_t(ddr4_c0_dqs_t), + .c0_ddr4_dqs_c(ddr4_c0_dqs_c), + .c0_ddr4_odt(ddr4_c0_odt), + .c0_ddr4_parity(ddr4_c0_par), + .c0_ddr4_bg(ddr4_c0_bg), + .c0_ddr4_reset_n(ddr4_c0_reset_n), + .c0_ddr4_act_n(ddr4_c0_act_n), + .c0_ddr4_ck_t(ddr4_c0_ck_t), + .c0_ddr4_ck_c(ddr4_c0_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[0 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[0 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c0_adr = {17{1'bz}}; +assign ddr4_c0_ba = {2{1'bz}}; +assign ddr4_c0_bg = {2{1'bz}}; +assign ddr4_c0_cke = 1'bz; +assign ddr4_c0_cs_n = 1'bz; +assign ddr4_c0_act_n = 1'bz; +assign ddr4_c0_odt = 1'bz; +assign ddr4_c0_par = 1'bz; +assign ddr4_c0_reset_n = 1'b0; +assign ddr4_c0_dq = {72{1'bz}}; +assign ddr4_c0_dqs_t = {18{1'bz}}; +assign ddr4_c0_dqs_c = {18{1'bz}}; + +OBUFTDS ddr4_c0_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c0_ck_t), + .OB(ddr4_c0_ck_c) +); + +assign ddr_clk = 0; +assign ddr_rst = 0; + +assign m_axi_ddr_awready = 0; +assign m_axi_ddr_wready = 0; +assign m_axi_ddr_bid = 0; +assign m_axi_ddr_bresp = 0; +assign m_axi_ddr_bvalid = 0; +assign m_axi_ddr_arready = 0; +assign m_axi_ddr_rid = 0; +assign m_axi_ddr_rdata = 0; +assign m_axi_ddr_rresp = 0; +assign m_axi_ddr_rlast = 0; +assign m_axi_ddr_rvalid = 0; + +assign ddr_status = 0; + +end + +if (DDR_ENABLE && DDR_CH > 1) begin + +ddr4_0 ddr4_c1_inst ( + .c0_sys_clk_p(clk_300mhz_1_p), + .c0_sys_clk_n(clk_300mhz_1_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[1 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c1_adr), + .c0_ddr4_ba(ddr4_c1_ba), + .c0_ddr4_cke(ddr4_c1_cke), + .c0_ddr4_cs_n(ddr4_c1_cs_n), + .c0_ddr4_dq(ddr4_c1_dq), + .c0_ddr4_dqs_t(ddr4_c1_dqs_t), + .c0_ddr4_dqs_c(ddr4_c1_dqs_c), + .c0_ddr4_odt(ddr4_c1_odt), + .c0_ddr4_parity(ddr4_c1_par), + .c0_ddr4_bg(ddr4_c1_bg), + .c0_ddr4_reset_n(ddr4_c1_reset_n), + .c0_ddr4_act_n(ddr4_c1_act_n), + .c0_ddr4_ck_t(ddr4_c1_ck_t), + .c0_ddr4_ck_c(ddr4_c1_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[1 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[1 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[1 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[1*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[1*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[1*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[1 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[1*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[1*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[1*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[1 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[1 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[1*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[1 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[1 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[1 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[1 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[1*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[1 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[1*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[1*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[1*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[1 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[1*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[1*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[1*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[1 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[1 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[1 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[1 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[1 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[1*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c1_adr = {17{1'bz}}; +assign ddr4_c1_ba = {2{1'bz}}; +assign ddr4_c1_bg = {2{1'bz}}; +assign ddr4_c1_cke = 1'bz; +assign ddr4_c1_cs_n = 1'bz; +assign ddr4_c1_act_n = 1'bz; +assign ddr4_c1_odt = 1'bz; +assign ddr4_c1_par = 1'bz; +assign ddr4_c1_reset_n = 1'b0; +assign ddr4_c1_dq = {72{1'bz}}; +assign ddr4_c1_dqs_t = {18{1'bz}}; +assign ddr4_c1_dqs_c = {18{1'bz}}; + +OBUFTDS ddr4_c1_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c1_ck_t), + .OB(ddr4_c1_ck_c) +); + +end + +if (DDR_ENABLE && DDR_CH > 2) begin + +ddr4_0 ddr4_c2_inst ( + .c0_sys_clk_p(clk_300mhz_2_p), + .c0_sys_clk_n(clk_300mhz_2_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[2 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c2_adr), + .c0_ddr4_ba(ddr4_c2_ba), + .c0_ddr4_cke(ddr4_c2_cke), + .c0_ddr4_cs_n(ddr4_c2_cs_n), + .c0_ddr4_dq(ddr4_c2_dq), + .c0_ddr4_dqs_t(ddr4_c2_dqs_t), + .c0_ddr4_dqs_c(ddr4_c2_dqs_c), + .c0_ddr4_odt(ddr4_c2_odt), + .c0_ddr4_parity(ddr4_c2_par), + .c0_ddr4_bg(ddr4_c2_bg), + .c0_ddr4_reset_n(ddr4_c2_reset_n), + .c0_ddr4_act_n(ddr4_c2_act_n), + .c0_ddr4_ck_t(ddr4_c2_ck_t), + .c0_ddr4_ck_c(ddr4_c2_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[2 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[2 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[2 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[2*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[2*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[2*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[2 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[2*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[2*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[2*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[2 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[2 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[2*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[2 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[2 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[2 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[2 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[2*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[2 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[2*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[2*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[2*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[2 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[2*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[2*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[2*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[2 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[2 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[2 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[2 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[2 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[2*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c2_adr = {17{1'bz}}; +assign ddr4_c2_ba = {2{1'bz}}; +assign ddr4_c2_bg = {2{1'bz}}; +assign ddr4_c2_cke = 1'bz; +assign ddr4_c2_cs_n = 1'bz; +assign ddr4_c2_act_n = 1'bz; +assign ddr4_c2_odt = 1'bz; +assign ddr4_c2_par = 1'bz; +assign ddr4_c2_reset_n = 1'b0; +assign ddr4_c2_dq = {72{1'bz}}; +assign ddr4_c2_dqs_t = {18{1'bz}}; +assign ddr4_c2_dqs_c = {18{1'bz}}; + +OBUFTDS ddr4_c2_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c2_ck_t), + .OB(ddr4_c2_ck_c) +); + +end + +if (DDR_ENABLE && DDR_CH > 3) begin + +ddr4_0 ddr4_c3_inst ( + .c0_sys_clk_p(clk_300mhz_3_p), + .c0_sys_clk_n(clk_300mhz_3_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[3 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c3_adr), + .c0_ddr4_ba(ddr4_c3_ba), + .c0_ddr4_cke(ddr4_c3_cke), + .c0_ddr4_cs_n(ddr4_c3_cs_n), + .c0_ddr4_dq(ddr4_c3_dq), + .c0_ddr4_dqs_t(ddr4_c3_dqs_t), + .c0_ddr4_dqs_c(ddr4_c3_dqs_c), + .c0_ddr4_odt(ddr4_c3_odt), + .c0_ddr4_parity(ddr4_c3_par), + .c0_ddr4_bg(ddr4_c3_bg), + .c0_ddr4_reset_n(ddr4_c3_reset_n), + .c0_ddr4_act_n(ddr4_c3_act_n), + .c0_ddr4_ck_t(ddr4_c3_ck_t), + .c0_ddr4_ck_c(ddr4_c3_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[3 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[3 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[3 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[3*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[3*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[3*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[3 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[3*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[3*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[3*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[3 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[3 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[3*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[3 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[3 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[3 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[3 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[3*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[3 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[3*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[3*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[3*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[3 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[3*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[3*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[3*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[3 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[3 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[3 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[3 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[3 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[3*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c3_adr = {17{1'bz}}; +assign ddr4_c3_ba = {2{1'bz}}; +assign ddr4_c3_bg = {2{1'bz}}; +assign ddr4_c3_cke = 1'bz; +assign ddr4_c3_cs_n = 1'bz; +assign ddr4_c3_act_n = 1'bz; +assign ddr4_c3_odt = 1'bz; +assign ddr4_c3_par = 1'bz; +assign ddr4_c3_reset_n = 1'b0; +assign ddr4_c3_dq = {72{1'bz}}; +assign ddr4_c3_dqs_t = {18{1'bz}}; +assign ddr4_c3_dqs_c = {18{1'bz}}; + +OBUFTDS ddr4_c3_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c3_ck_t), + .OB(ddr4_c3_ck_c) +); + +end + +endgenerate + fpga_core #( // FW and board IDs .FPGA_ID(FPGA_ID), @@ -1963,6 +2563,16 @@ fpga_core #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -2200,6 +2810,52 @@ core_inst ( .qsfp1_intl(qsfp1_intl_int), .qsfp1_lpmode(qsfp1_lpmode), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + /* * QSPI flash */ diff --git a/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v index 5c8a0a93e..02088d212 100644 --- a/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v @@ -115,6 +115,16 @@ module fpga_core # parameter TX_RAM_SIZE = 131072, parameter RX_RAM_SIZE = 131072, + // RAM configuration + parameter DDR_CH = 4, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 34, + parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -364,6 +374,52 @@ module fpga_core # input wire qsfp1_intl, output wire qsfp1_lpmode, + /* + * DDR + */ + input wire [DDR_CH-1:0] ddr_clk, + input wire [DDR_CH-1:0] ddr_rst, + + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, + output wire [DDR_CH-1:0] m_axi_ddr_awlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, + output wire [DDR_CH-1:0] m_axi_ddr_awvalid, + input wire [DDR_CH-1:0] m_axi_ddr_awready, + output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, + output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, + output wire [DDR_CH-1:0] m_axi_ddr_wlast, + output wire [DDR_CH-1:0] m_axi_ddr_wvalid, + input wire [DDR_CH-1:0] m_axi_ddr_wready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, + input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, + input wire [DDR_CH-1:0] m_axi_ddr_bvalid, + output wire [DDR_CH-1:0] m_axi_ddr_bready, + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, + output wire [DDR_CH-1:0] m_axi_ddr_arlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, + output wire [DDR_CH-1:0] m_axi_ddr_arvalid, + input wire [DDR_CH-1:0] m_axi_ddr_arready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, + input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, + input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, + input wire [DDR_CH-1:0] m_axi_ddr_rlast, + input wire [DDR_CH-1:0] m_axi_ddr_rvalid, + output wire [DDR_CH-1:0] m_axi_ddr_rready, + + input wire [DDR_CH-1:0] ddr_status, + /* * QSPI flash */ @@ -903,6 +959,25 @@ mqnic_core_pcie_us #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .DDR_GROUP_SIZE(1), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_AWUSER_ENABLE(0), + .AXI_DDR_WUSER_ENABLE(0), + .AXI_DDR_BUSER_ENABLE(0), + .AXI_DDR_ARUSER_ENABLE(0), + .AXI_DDR_RUSER_ENABLE(0), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + .AXI_DDR_FIXED_BURST(0), + .AXI_DDR_WRAP_BURST(1), + .HBM_ENABLE(0), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1180,6 +1255,108 @@ core_inst ( .eth_rx_status(eth_rx_status), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awuser(), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wuser(), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_buser(0), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_aruser(), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_ruser(0), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + + /* + * HBM + */ + .hbm_clk(0), + .hbm_rst(0), + + .m_axi_hbm_awid(), + .m_axi_hbm_awaddr(), + .m_axi_hbm_awlen(), + .m_axi_hbm_awsize(), + .m_axi_hbm_awburst(), + .m_axi_hbm_awlock(), + .m_axi_hbm_awcache(), + .m_axi_hbm_awprot(), + .m_axi_hbm_awqos(), + .m_axi_hbm_awuser(), + .m_axi_hbm_awvalid(), + .m_axi_hbm_awready(0), + .m_axi_hbm_wdata(), + .m_axi_hbm_wstrb(), + .m_axi_hbm_wlast(), + .m_axi_hbm_wuser(), + .m_axi_hbm_wvalid(), + .m_axi_hbm_wready(0), + .m_axi_hbm_bid(0), + .m_axi_hbm_bresp(0), + .m_axi_hbm_buser(0), + .m_axi_hbm_bvalid(0), + .m_axi_hbm_bready(), + .m_axi_hbm_arid(), + .m_axi_hbm_araddr(), + .m_axi_hbm_arlen(), + .m_axi_hbm_arsize(), + .m_axi_hbm_arburst(), + .m_axi_hbm_arlock(), + .m_axi_hbm_arcache(), + .m_axi_hbm_arprot(), + .m_axi_hbm_arqos(), + .m_axi_hbm_aruser(), + .m_axi_hbm_arvalid(), + .m_axi_hbm_arready(0), + .m_axi_hbm_rid(0), + .m_axi_hbm_rdata(0), + .m_axi_hbm_rresp(0), + .m_axi_hbm_rlast(0), + .m_axi_hbm_ruser(0), + .m_axi_hbm_rvalid(0), + .m_axi_hbm_rready(), + + .hbm_status(0), + /* * Statistics input */ diff --git a/fpga/mqnic/AU200/fpga_25g/README.md b/fpga/mqnic/AU200/fpga_25g/README.md index cd60ee1cb..ce9243f47 100644 --- a/fpga/mqnic/AU200/fpga_25g/README.md +++ b/fpga/mqnic/AU200/fpga_25g/README.md @@ -4,8 +4,9 @@ This design targets the Xilinx Alveo U200 FPGA board. -FPGA: xcu200-fsgd2104-2-e -PHY: 10G BASE-R PHY IP core and internal GTY transceiver +* FPGA: xcu200-fsgd2104-2-e +* PHY: 10G BASE-R PHY IP core and internal GTY transceiver +* RAM: 64 GB DDR4 2400 (4x 2G x72 DIMM) ## How to build diff --git a/fpga/mqnic/AU200/fpga_25g/fpga.xdc b/fpga/mqnic/AU200/fpga_25g/fpga.xdc index be5af950f..3b7a4df83 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga.xdc +++ b/fpga/mqnic/AU200/fpga_25g/fpga.xdc @@ -17,23 +17,23 @@ set_operating_conditions -design_power_budget 160 # System clocks # 300 MHz (DDR 0) -#set_property -dict {LOC AY37 IOSTANDARD LVDS} [get_ports clk_300mhz_0_p] -#set_property -dict {LOC AY38 IOSTANDARD LVDS} [get_ports clk_300mhz_0_n] +set_property -dict {LOC AY37 IOSTANDARD LVDS} [get_ports clk_300mhz_0_p] +set_property -dict {LOC AY38 IOSTANDARD LVDS} [get_ports clk_300mhz_0_n] #create_clock -period 3.333 -name clk_300mhz_0 [get_ports clk_300mhz_0_p] # 300 MHz (DDR 1) -#set_property -dict {LOC AW20 IOSTANDARD LVDS} [get_ports clk_300mhz_1_p] -#set_property -dict {LOC AW19 IOSTANDARD LVDS} [get_ports clk_300mhz_1_n] +set_property -dict {LOC AW20 IOSTANDARD LVDS} [get_ports clk_300mhz_1_p] +set_property -dict {LOC AW19 IOSTANDARD LVDS} [get_ports clk_300mhz_1_n] #create_clock -period 3.333 -name clk_300mhz_1 [get_ports clk_300mhz_1_p] # 300 MHz (DDR 2) -#set_property -dict {LOC F32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_p] -#set_property -dict {LOC E32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_n] +set_property -dict {LOC F32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_p] +set_property -dict {LOC E32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_n] #create_clock -period 3.333 -name clk_300mhz_2 [get_ports clk_300mhz_2_p] # 300 MHz (DDR 3) -#set_property -dict {LOC J16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_p] -#set_property -dict {LOC H16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_n] +set_property -dict {LOC J16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_p] +set_property -dict {LOC H16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_n] #create_clock -period 3.333 -name clk_300mhz_3 [get_ports clk_300mhz_3_p] # SI570 user clock @@ -257,3 +257,591 @@ create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_p] set_false_path -from [get_ports {pcie_reset_n}] set_input_delay 0 [get_ports {pcie_reset_n}] + +# DDR4 C0 +set_property -dict {LOC AT36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}] +set_property -dict {LOC AV36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}] +set_property -dict {LOC AV37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}] +set_property -dict {LOC AW35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}] +set_property -dict {LOC AW36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}] +set_property -dict {LOC AY36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}] +set_property -dict {LOC AY35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}] +set_property -dict {LOC BA40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}] +set_property -dict {LOC BA37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}] +set_property -dict {LOC BB37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}] +set_property -dict {LOC AR35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}] +set_property -dict {LOC BA39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}] +set_property -dict {LOC BB40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}] +set_property -dict {LOC AN36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}] +set_property -dict {LOC AP35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}] +set_property -dict {LOC AP36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}] +set_property -dict {LOC AR36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}] +set_property -dict {LOC AT35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}] +set_property -dict {LOC AT34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}] +set_property -dict {LOC BC37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}] +set_property -dict {LOC BC39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}] +set_property -dict {LOC AV38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t[0]}] +set_property -dict {LOC AW38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c[0]}] +#set_property -dict {LOC AU34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t[1]}] +#set_property -dict {LOC AU35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c[1]}] +set_property -dict {LOC BC38 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[0]}] +#set_property -dict {LOC BC40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[1]}] +set_property -dict {LOC AR33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[0]}] +#set_property -dict {LOC AP33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[1]}] +#set_property -dict {LOC AN33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[2]}] +#set_property -dict {LOC AM34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[3]}] +set_property -dict {LOC BB39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}] +set_property -dict {LOC AP34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[0]}] +#set_property -dict {LOC AN34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[1]}] +set_property -dict {LOC AU36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}] +set_property -dict {LOC AU31 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_reset_n}] + +set_property -dict {LOC AW28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}] +set_property -dict {LOC AW29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}] +set_property -dict {LOC BA28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}] +set_property -dict {LOC BA27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}] +set_property -dict {LOC BB29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}] +set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}] +set_property -dict {LOC BC27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}] +set_property -dict {LOC BB27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}] +set_property -dict {LOC BE28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}] +set_property -dict {LOC BF28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}] +set_property -dict {LOC BE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}] +set_property -dict {LOC BD30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}] +set_property -dict {LOC BF27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}] +set_property -dict {LOC BE27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}] +set_property -dict {LOC BF30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}] +set_property -dict {LOC BF29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}] +set_property -dict {LOC BB31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}] +set_property -dict {LOC BB32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}] +set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}] +set_property -dict {LOC AY33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}] +set_property -dict {LOC BC32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}] +set_property -dict {LOC BC33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}] +set_property -dict {LOC BB34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}] +set_property -dict {LOC BC34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}] +set_property -dict {LOC AV31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}] +set_property -dict {LOC AV32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}] +set_property -dict {LOC AV34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}] +set_property -dict {LOC AW34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}] +set_property -dict {LOC AW31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}] +set_property -dict {LOC AY31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}] +set_property -dict {LOC BA35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}] +set_property -dict {LOC BA34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}] +set_property -dict {LOC AL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}] +set_property -dict {LOC AM30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}] +set_property -dict {LOC AU32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}] +set_property -dict {LOC AT32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}] +set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}] +set_property -dict {LOC AN32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}] +set_property -dict {LOC AR32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}] +set_property -dict {LOC AR31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}] +set_property -dict {LOC AP29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}] +set_property -dict {LOC AP28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}] +set_property -dict {LOC AN27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}] +set_property -dict {LOC AM27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}] +set_property -dict {LOC AN29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}] +set_property -dict {LOC AM29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}] +set_property -dict {LOC AR27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}] +set_property -dict {LOC AR28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}] +set_property -dict {LOC AT28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}] +set_property -dict {LOC AV27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}] +set_property -dict {LOC AU27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}] +set_property -dict {LOC AT27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}] +set_property -dict {LOC AV29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}] +set_property -dict {LOC AY30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}] +set_property -dict {LOC AW30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}] +set_property -dict {LOC AV28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}] +set_property -dict {LOC BD34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}] +set_property -dict {LOC BD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}] +set_property -dict {LOC BE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}] +set_property -dict {LOC BD35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}] +set_property -dict {LOC BF32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}] +set_property -dict {LOC BF33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}] +set_property -dict {LOC BF34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}] +set_property -dict {LOC BF35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}] +set_property -dict {LOC BD40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}] +set_property -dict {LOC BD39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}] +set_property -dict {LOC BF43 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}] +set_property -dict {LOC BF42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}] +set_property -dict {LOC BF37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}] +set_property -dict {LOC BE37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}] +set_property -dict {LOC BE40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}] +set_property -dict {LOC BF41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}] +set_property -dict {LOC BA30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}] +set_property -dict {LOC BB30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}] +set_property -dict {LOC BB26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}] +set_property -dict {LOC BC26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}] +set_property -dict {LOC BD28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}] +set_property -dict {LOC BD29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}] +set_property -dict {LOC BD26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}] +set_property -dict {LOC BE26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}] +set_property -dict {LOC BB35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}] +set_property -dict {LOC BB36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}] +set_property -dict {LOC BC31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}] +set_property -dict {LOC BD31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}] +set_property -dict {LOC AV33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}] +set_property -dict {LOC AW33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}] +set_property -dict {LOC BA32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}] +set_property -dict {LOC BA33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}] +set_property -dict {LOC AM31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}] +set_property -dict {LOC AM32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}] +set_property -dict {LOC AP30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[9]}] +set_property -dict {LOC AP31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[9]}] +set_property -dict {LOC AL28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[10]}] +set_property -dict {LOC AL29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[10]}] +set_property -dict {LOC AR30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[11]}] +set_property -dict {LOC AT30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[11]}] +set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[12]}] +set_property -dict {LOC AU30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[12]}] +set_property -dict {LOC AY27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[13]}] +set_property -dict {LOC AY28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[13]}] +set_property -dict {LOC BE35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[14]}] +set_property -dict {LOC BE36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[14]}] +set_property -dict {LOC BE31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[15]}] +set_property -dict {LOC BE32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[15]}] +set_property -dict {LOC BE38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[16]}] +set_property -dict {LOC BF38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[16]}] +set_property -dict {LOC BF39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[17]}] +set_property -dict {LOC BF40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[17]}] + +# DDR4 C1 +set_property -dict {LOC AN24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}] +set_property -dict {LOC AT24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}] +set_property -dict {LOC AW24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}] +set_property -dict {LOC AN26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}] +set_property -dict {LOC AY22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}] +set_property -dict {LOC AY23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}] +set_property -dict {LOC AV24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}] +set_property -dict {LOC BA22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}] +set_property -dict {LOC AY25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}] +set_property -dict {LOC BA23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}] +set_property -dict {LOC AM26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}] +set_property -dict {LOC BA25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}] +set_property -dict {LOC BB22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}] +set_property -dict {LOC AL24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}] +set_property -dict {LOC AL25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}] +set_property -dict {LOC AM25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}] +set_property -dict {LOC AN23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}] +set_property -dict {LOC AU24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}] +set_property -dict {LOC AP26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}] +set_property -dict {LOC BC22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}] +set_property -dict {LOC AW26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}] +set_property -dict {LOC AT25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t[0]}] +set_property -dict {LOC AU25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c[0]}] +#set_property -dict {LOC AU26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t[1]}] +#set_property -dict {LOC AV26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c[1]}] +set_property -dict {LOC BB25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[0]}] +#set_property -dict {LOC BB24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[1]}] +set_property -dict {LOC AV23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[0]}] +#set_property -dict {LOC AP25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[1]}] +#set_property -dict {LOC AR23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[2]}] +#set_property -dict {LOC AP23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[3]}] +set_property -dict {LOC AW25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}] +set_property -dict {LOC AW23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[0]}] +#set_property -dict {LOC AP24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[1]}] +set_property -dict {LOC AT23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}] +set_property -dict {LOC AR17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}] + +set_property -dict {LOC BD9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] +set_property -dict {LOC BD7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] +set_property -dict {LOC BC7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] +set_property -dict {LOC BD8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] +set_property -dict {LOC BD10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] +set_property -dict {LOC BE10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] +set_property -dict {LOC BE7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] +set_property -dict {LOC BF7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] +set_property -dict {LOC AU13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] +set_property -dict {LOC AV13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] +set_property -dict {LOC AW13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] +set_property -dict {LOC AW14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] +set_property -dict {LOC AU14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] +set_property -dict {LOC AY11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] +set_property -dict {LOC AV14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] +set_property -dict {LOC BA11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] +set_property -dict {LOC BA12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] +set_property -dict {LOC BB12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] +set_property -dict {LOC BA13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] +set_property -dict {LOC BA14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] +set_property -dict {LOC BC9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] +set_property -dict {LOC BB9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] +set_property -dict {LOC BA7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] +set_property -dict {LOC BA8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] +set_property -dict {LOC AN13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] +set_property -dict {LOC AR13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] +set_property -dict {LOC AM13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] +set_property -dict {LOC AP13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] +set_property -dict {LOC AM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] +set_property -dict {LOC AR15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] +set_property -dict {LOC AL14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] +set_property -dict {LOC AT15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] +set_property -dict {LOC BE13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] +set_property -dict {LOC BD14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] +set_property -dict {LOC BF12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] +set_property -dict {LOC BD13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] +set_property -dict {LOC BD15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] +set_property -dict {LOC BD16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] +set_property -dict {LOC BF14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] +set_property -dict {LOC BF13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] +set_property -dict {LOC AY17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] +set_property -dict {LOC BA17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] +set_property -dict {LOC AY18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] +set_property -dict {LOC BA18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] +set_property -dict {LOC BA15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] +set_property -dict {LOC BB15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] +set_property -dict {LOC BC11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] +set_property -dict {LOC BD11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] +set_property -dict {LOC AV16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] +set_property -dict {LOC AV17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] +set_property -dict {LOC AU16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] +set_property -dict {LOC AU17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] +set_property -dict {LOC BB17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] +set_property -dict {LOC BB16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] +set_property -dict {LOC AT18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] +set_property -dict {LOC AT17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] +set_property -dict {LOC AM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] +set_property -dict {LOC AL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] +set_property -dict {LOC AN17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] +set_property -dict {LOC AN16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] +set_property -dict {LOC AR18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] +set_property -dict {LOC AP18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] +set_property -dict {LOC AL17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] +set_property -dict {LOC AL16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] +set_property -dict {LOC BF25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}] +set_property -dict {LOC BF24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}] +set_property -dict {LOC BD25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}] +set_property -dict {LOC BE25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}] +set_property -dict {LOC BD23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}] +set_property -dict {LOC BC23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}] +set_property -dict {LOC BF23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}] +set_property -dict {LOC BE23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}] +set_property -dict {LOC BF10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] +set_property -dict {LOC BF9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] +set_property -dict {LOC BE8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] +set_property -dict {LOC BF8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] +set_property -dict {LOC AW15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] +set_property -dict {LOC AY15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] +set_property -dict {LOC AY13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] +set_property -dict {LOC AY12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] +set_property -dict {LOC BB11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] +set_property -dict {LOC BB10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] +set_property -dict {LOC BA10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] +set_property -dict {LOC BA9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] +set_property -dict {LOC AT14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] +set_property -dict {LOC AT13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] +set_property -dict {LOC AN14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] +set_property -dict {LOC AP14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] +set_property -dict {LOC BE12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}] +set_property -dict {LOC BE11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}] +set_property -dict {LOC BE15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}] +set_property -dict {LOC BF15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}] +set_property -dict {LOC BC13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[10]}] +set_property -dict {LOC BC12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[10]}] +set_property -dict {LOC BB14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[11]}] +set_property -dict {LOC BC14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[11]}] +set_property -dict {LOC AV18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[12]}] +set_property -dict {LOC AW18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[12]}] +set_property -dict {LOC AW16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[13]}] +set_property -dict {LOC AY16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[13]}] +set_property -dict {LOC AP16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[14]}] +set_property -dict {LOC AR16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[14]}] +set_property -dict {LOC AM17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[15]}] +set_property -dict {LOC AM16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[15]}] +set_property -dict {LOC BC24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[16]}] +set_property -dict {LOC BD24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[16]}] +set_property -dict {LOC BE22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[17]}] +set_property -dict {LOC BF22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[17]}] + +# DDR4 C2 +set_property -dict {LOC L29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[0]}] +set_property -dict {LOC A33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[1]}] +set_property -dict {LOC C33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[2]}] +set_property -dict {LOC J29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[3]}] +set_property -dict {LOC H31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[4]}] +set_property -dict {LOC G31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[5]}] +set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[6]}] +set_property -dict {LOC B32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[7]}] +set_property -dict {LOC A32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[8]}] +set_property -dict {LOC D31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[9]}] +set_property -dict {LOC A34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[10]}] +set_property -dict {LOC E31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[11]}] +set_property -dict {LOC M30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[12]}] +set_property -dict {LOC F33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[13]}] +set_property -dict {LOC A35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[14]}] +set_property -dict {LOC G32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[15]}] +set_property -dict {LOC K30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[16]}] +set_property -dict {LOC D33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[0]}] +set_property -dict {LOC B36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[1]}] +set_property -dict {LOC C31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[0]}] +set_property -dict {LOC J30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[1]}] +set_property -dict {LOC C34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t[0]}] +set_property -dict {LOC B34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c[0]}] +#set_property -dict {LOC D34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t[1]}] +#set_property -dict {LOC D35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c[1]}] +set_property -dict {LOC G30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[0]}] +#set_property -dict {LOC E30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[1]}] +set_property -dict {LOC B35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[0]}] +#set_property -dict {LOC J31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[1]}] +#set_property -dict {LOC L30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[2]}] +#set_property -dict {LOC K31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[3]}] +set_property -dict {LOC B31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_act_n}] +set_property -dict {LOC E33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[0]}] +#set_property -dict {LOC F34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[1]}] +set_property -dict {LOC M29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_par}] +set_property -dict {LOC D36 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_reset_n}] + +set_property -dict {LOC R25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[0]}] +set_property -dict {LOC P25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[1]}] +set_property -dict {LOC M25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[2]}] +set_property -dict {LOC L25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[3]}] +set_property -dict {LOC P26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[4]}] +set_property -dict {LOC R26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[5]}] +set_property -dict {LOC N27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[6]}] +set_property -dict {LOC N28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[7]}] +set_property -dict {LOC J28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[8]}] +set_property -dict {LOC H29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[9]}] +set_property -dict {LOC H28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[10]}] +set_property -dict {LOC G29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[11]}] +set_property -dict {LOC K25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[12]}] +set_property -dict {LOC L27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[13]}] +set_property -dict {LOC K26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[14]}] +set_property -dict {LOC K27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[15]}] +set_property -dict {LOC F27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[16]}] +set_property -dict {LOC E27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[17]}] +set_property -dict {LOC E28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[18]}] +set_property -dict {LOC D28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[19]}] +set_property -dict {LOC G27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[20]}] +set_property -dict {LOC G26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[21]}] +set_property -dict {LOC F28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[22]}] +set_property -dict {LOC F29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[23]}] +set_property -dict {LOC D26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[24]}] +set_property -dict {LOC C26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[25]}] +set_property -dict {LOC B27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[26]}] +set_property -dict {LOC B26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[27]}] +set_property -dict {LOC A29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[28]}] +set_property -dict {LOC A30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[29]}] +set_property -dict {LOC C27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[30]}] +set_property -dict {LOC C28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[31]}] +set_property -dict {LOC F35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[32]}] +set_property -dict {LOC E38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[33]}] +set_property -dict {LOC D38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[34]}] +set_property -dict {LOC E35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[35]}] +set_property -dict {LOC E36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[36]}] +set_property -dict {LOC E37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[37]}] +set_property -dict {LOC F38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[38]}] +set_property -dict {LOC G38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[39]}] +set_property -dict {LOC P30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[40]}] +set_property -dict {LOC R30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[41]}] +set_property -dict {LOC P29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[42]}] +set_property -dict {LOC N29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[43]}] +set_property -dict {LOC L32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[44]}] +set_property -dict {LOC M32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[45]}] +set_property -dict {LOC P31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[46]}] +set_property -dict {LOC N32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[47]}] +set_property -dict {LOC J35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[48]}] +set_property -dict {LOC K35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[49]}] +set_property -dict {LOC L33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[50]}] +set_property -dict {LOC K33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[51]}] +set_property -dict {LOC J34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[52]}] +set_property -dict {LOC J33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[53]}] +set_property -dict {LOC N34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[54]}] +set_property -dict {LOC P34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[55]}] +set_property -dict {LOC H36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[56]}] +set_property -dict {LOC G36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[57]}] +set_property -dict {LOC H37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[58]}] +set_property -dict {LOC J36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[59]}] +set_property -dict {LOC K37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[60]}] +set_property -dict {LOC K38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[61]}] +set_property -dict {LOC G35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[62]}] +set_property -dict {LOC G34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[63]}] +set_property -dict {LOC C36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[64]}] +set_property -dict {LOC B37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[65]}] +set_property -dict {LOC A37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[66]}] +set_property -dict {LOC A38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[67]}] +set_property -dict {LOC C39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[68]}] +set_property -dict {LOC D39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[69]}] +set_property -dict {LOC A40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[70]}] +set_property -dict {LOC B40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[71]}] +set_property -dict {LOC N26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[0]}] +set_property -dict {LOC M26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[0]}] +set_property -dict {LOC R28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[1]}] +set_property -dict {LOC P28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[1]}] +set_property -dict {LOC J25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[2]}] +set_property -dict {LOC J26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[2]}] +set_property -dict {LOC M27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[3]}] +set_property -dict {LOC L28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[3]}] +set_property -dict {LOC D29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[4]}] +set_property -dict {LOC D30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[4]}] +set_property -dict {LOC H26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[5]}] +set_property -dict {LOC H27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[5]}] +set_property -dict {LOC A27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[6]}] +set_property -dict {LOC A28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[6]}] +set_property -dict {LOC C29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[7]}] +set_property -dict {LOC B29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[7]}] +set_property -dict {LOC E39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[8]}] +set_property -dict {LOC E40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[8]}] +set_property -dict {LOC G37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[9]}] +set_property -dict {LOC F37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[9]}] +set_property -dict {LOC N31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[10]}] +set_property -dict {LOC M31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[10]}] +set_property -dict {LOC T30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[11]}] +set_property -dict {LOC R31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[11]}] +set_property -dict {LOC L35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[12]}] +set_property -dict {LOC L36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[12]}] +set_property -dict {LOC M34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[13]}] +set_property -dict {LOC L34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[13]}] +set_property -dict {LOC J38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[14]}] +set_property -dict {LOC H38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[14]}] +set_property -dict {LOC H33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[15]}] +set_property -dict {LOC H34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[15]}] +set_property -dict {LOC B39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[16]}] +set_property -dict {LOC A39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[16]}] +set_property -dict {LOC C37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[17]}] +set_property -dict {LOC C38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[17]}] + +# DDR4 C3 +set_property -dict {LOC K15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[0]}] +set_property -dict {LOC B15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[1]}] +set_property -dict {LOC F14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[2]}] +set_property -dict {LOC A15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[3]}] +set_property -dict {LOC C14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[4]}] +set_property -dict {LOC A14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[5]}] +set_property -dict {LOC B14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[6]}] +set_property -dict {LOC E13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[7]}] +set_property -dict {LOC F13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[8]}] +set_property -dict {LOC A13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[9]}] +set_property -dict {LOC D14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[10]}] +set_property -dict {LOC C13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[11]}] +set_property -dict {LOC B13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[12]}] +set_property -dict {LOC K16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[13]}] +set_property -dict {LOC D15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[14]}] +set_property -dict {LOC E15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[15]}] +set_property -dict {LOC F15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[16]}] +set_property -dict {LOC J15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[0]}] +set_property -dict {LOC H14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[1]}] +set_property -dict {LOC D13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[0]}] +set_property -dict {LOC J13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[1]}] +set_property -dict {LOC L14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t[0]}] +set_property -dict {LOC L13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c[0]}] +#set_property -dict {LOC G14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t[1]}] +#set_property -dict {LOC G13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c[1]}] +set_property -dict {LOC K13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[0]}] +#set_property -dict {LOC L15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[1]}] +set_property -dict {LOC B16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[0]}] +#set_property -dict {LOC D16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[1]}] +#set_property -dict {LOC M14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[2]}] +#set_property -dict {LOC M13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[3]}] +set_property -dict {LOC H13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_act_n}] +set_property -dict {LOC C16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[0]}] +#set_property -dict {LOC E16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[1]}] +set_property -dict {LOC J14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_par}] +set_property -dict {LOC D21 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c3_reset_n}] + +set_property -dict {LOC P24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[0]}] +set_property -dict {LOC N24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[1]}] +set_property -dict {LOC T24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[2]}] +set_property -dict {LOC R23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[3]}] +set_property -dict {LOC N23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[4]}] +set_property -dict {LOC P21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[5]}] +set_property -dict {LOC P23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[6]}] +set_property -dict {LOC R21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[7]}] +set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[8]}] +set_property -dict {LOC J23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[9]}] +set_property -dict {LOC H24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[10]}] +set_property -dict {LOC G24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[11]}] +set_property -dict {LOC L24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[12]}] +set_property -dict {LOC L23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[13]}] +set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[14]}] +set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[15]}] +set_property -dict {LOC G20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[16]}] +set_property -dict {LOC H17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[17]}] +set_property -dict {LOC F19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[18]}] +set_property -dict {LOC G17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[19]}] +set_property -dict {LOC J20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[20]}] +set_property -dict {LOC L19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[21]}] +set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[22]}] +set_property -dict {LOC J19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[23]}] +set_property -dict {LOC M19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[24]}] +set_property -dict {LOC M20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[25]}] +set_property -dict {LOC R18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[26]}] +set_property -dict {LOC R17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[27]}] +set_property -dict {LOC R20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[28]}] +set_property -dict {LOC T20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[29]}] +set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[30]}] +set_property -dict {LOC N19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[31]}] +set_property -dict {LOC A23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[32]}] +set_property -dict {LOC A22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[33]}] +set_property -dict {LOC B24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[34]}] +set_property -dict {LOC B25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[35]}] +set_property -dict {LOC B22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[36]}] +set_property -dict {LOC C22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[37]}] +set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[38]}] +set_property -dict {LOC C23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[39]}] +set_property -dict {LOC C19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[40]}] +set_property -dict {LOC C18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[41]}] +set_property -dict {LOC C21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[42]}] +set_property -dict {LOC B21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[43]}] +set_property -dict {LOC A18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[44]}] +set_property -dict {LOC A17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[45]}] +set_property -dict {LOC A20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[46]}] +set_property -dict {LOC B20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[47]}] +set_property -dict {LOC E17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[48]}] +set_property -dict {LOC F20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[49]}] +set_property -dict {LOC E18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[50]}] +set_property -dict {LOC E20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[51]}] +set_property -dict {LOC D19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[52]}] +set_property -dict {LOC D20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[53]}] +set_property -dict {LOC H18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[54]}] +set_property -dict {LOC J18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[55]}] +set_property -dict {LOC F22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[56]}] +set_property -dict {LOC E22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[57]}] +set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[58]}] +set_property -dict {LOC G21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[59]}] +set_property -dict {LOC F24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[60]}] +set_property -dict {LOC E25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[61]}] +set_property -dict {LOC F25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[62]}] +set_property -dict {LOC G25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[63]}] +set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[64]}] +set_property -dict {LOC N16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[65]}] +set_property -dict {LOC N13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[66]}] +set_property -dict {LOC N14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[67]}] +set_property -dict {LOC T15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[68]}] +set_property -dict {LOC R15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[69]}] +set_property -dict {LOC P13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[70]}] +set_property -dict {LOC P14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[71]}] +set_property -dict {LOC T22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[0]}] +set_property -dict {LOC R22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[0]}] +set_property -dict {LOC N22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[1]}] +set_property -dict {LOC N21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[1]}] +set_property -dict {LOC J21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[2]}] +set_property -dict {LOC H21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[2]}] +set_property -dict {LOC M22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[3]}] +set_property -dict {LOC L22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[3]}] +set_property -dict {LOC L20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[4]}] +set_property -dict {LOC K20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[4]}] +set_property -dict {LOC K18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[5]}] +set_property -dict {LOC K17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[5]}] +set_property -dict {LOC P19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[6]}] +set_property -dict {LOC P18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[6]}] +set_property -dict {LOC N17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[7]}] +set_property -dict {LOC M17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[7]}] +set_property -dict {LOC A25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[8]}] +set_property -dict {LOC A24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[8]}] +set_property -dict {LOC D24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[9]}] +set_property -dict {LOC D23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[9]}] +set_property -dict {LOC C17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[10]}] +set_property -dict {LOC B17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[10]}] +set_property -dict {LOC B19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[11]}] +set_property -dict {LOC A19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[11]}] +set_property -dict {LOC F18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[12]}] +set_property -dict {LOC F17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[12]}] +set_property -dict {LOC H19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[13]}] +set_property -dict {LOC G19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[13]}] +set_property -dict {LOC F23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[14]}] +set_property -dict {LOC E23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[14]}] +set_property -dict {LOC H23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[15]}] +set_property -dict {LOC H22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[15]}] +set_property -dict {LOC R16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[16]}] +set_property -dict {LOC P15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[16]}] +set_property -dict {LOC T13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[17]}] +set_property -dict {LOC R13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[17]}] diff --git a/fpga/mqnic/AU200/fpga_25g/fpga/Makefile b/fpga/mqnic/AU200/fpga_25g/fpga/Makefile index 4989842a9..fe1f365d1 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/AU200/fpga_25g/fpga/Makefile @@ -145,6 +145,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl IP_TCL_FILES += ip/cms.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl index 95d71a0c7..c8815c906 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/AU200/fpga_25g/fpga/config.tcl @@ -148,6 +148,12 @@ dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" dict set params RX_RAM_SIZE "131072" + +# RAM configuration +dict set params DDR_CH "4" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" # Application block configuration dict set params APP_ID "32'h00000000" @@ -200,6 +206,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile index 4989842a9..fe1f365d1 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile @@ -145,6 +145,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl IP_TCL_FILES += ip/cms.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl index 67ff1e397..aa9bef37e 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/AU200/fpga_25g/fpga_10g/config.tcl @@ -148,6 +148,12 @@ dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" dict set params RX_RAM_SIZE "32768" + +# RAM configuration +dict set params DDR_CH "4" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" # Application block configuration dict set params APP_ID "32'h00000000" @@ -200,6 +206,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/AU200/fpga_25g/ip/ddr4_0.tcl b/fpga/mqnic/AU200/fpga_25g/ip/ddr4_0.tcl new file mode 100644 index 000000000..27252f502 --- /dev/null +++ b/fpga/mqnic/AU200/fpga_25g/ip/ddr4_0.tcl @@ -0,0 +1,17 @@ + +create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 + +set_property -dict [list \ + CONFIG.C0.DDR4_AxiSelection {true} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_AxiIDWidth {8} \ + CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ + CONFIG.C0.DDR4_TimePeriod {833} \ + CONFIG.C0.DDR4_InputClockPeriod {3332} \ + CONFIG.C0.DDR4_MemoryType {RDIMMs} \ + CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PZ-2G3} \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_CasLatency {17} \ + CONFIG.C0.DDR4_CasWriteLatency {12} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} +] [get_ips ddr4_0] diff --git a/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v index 3ed3d69f0..d86cbf41e 100644 --- a/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/AU200/fpga_25g/rtl/fpga.v @@ -112,6 +112,15 @@ module fpga # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // RAM configuration + parameter DDR_CH = 4, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 34, + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -177,6 +186,18 @@ module fpga # parameter STAT_ID_WIDTH = 12 ) ( + /* + * Clock and reset + */ + input wire clk_300mhz_0_p, + input wire clk_300mhz_0_n, + input wire clk_300mhz_1_p, + input wire clk_300mhz_1_n, + input wire clk_300mhz_2_p, + input wire clk_300mhz_2_n, + input wire clk_300mhz_3_p, + input wire clk_300mhz_3_n, + /* * GPIO */ @@ -260,7 +281,70 @@ module fpga # input wire qsfp1_intl, output wire qsfp1_lpmode, output wire qsfp1_refclk_reset, - output wire [1:0] qsfp1_fs + output wire [1:0] qsfp1_fs, + + /* + * DDR4 + */ + output wire [16:0] ddr4_c0_adr, + output wire [1:0] ddr4_c0_ba, + output wire [1:0] ddr4_c0_bg, + output wire [0:0] ddr4_c0_ck_t, + output wire [0:0] ddr4_c0_ck_c, + output wire [0:0] ddr4_c0_cke, + output wire [0:0] ddr4_c0_cs_n, + output wire ddr4_c0_act_n, + output wire [0:0] ddr4_c0_odt, + output wire ddr4_c0_par, + output wire ddr4_c0_reset_n, + inout wire [71:0] ddr4_c0_dq, + inout wire [17:0] ddr4_c0_dqs_t, + inout wire [17:0] ddr4_c0_dqs_c, + + output wire [16:0] ddr4_c1_adr, + output wire [1:0] ddr4_c1_ba, + output wire [1:0] ddr4_c1_bg, + output wire [0:0] ddr4_c1_ck_t, + output wire [0:0] ddr4_c1_ck_c, + output wire [0:0] ddr4_c1_cke, + output wire [0:0] ddr4_c1_cs_n, + output wire ddr4_c1_act_n, + output wire [0:0] ddr4_c1_odt, + output wire ddr4_c1_par, + output wire ddr4_c1_reset_n, + inout wire [71:0] ddr4_c1_dq, + inout wire [17:0] ddr4_c1_dqs_t, + inout wire [17:0] ddr4_c1_dqs_c, + + output wire [16:0] ddr4_c2_adr, + output wire [1:0] ddr4_c2_ba, + output wire [1:0] ddr4_c2_bg, + output wire [0:0] ddr4_c2_ck_t, + output wire [0:0] ddr4_c2_ck_c, + output wire [0:0] ddr4_c2_cke, + output wire [0:0] ddr4_c2_cs_n, + output wire ddr4_c2_act_n, + output wire [0:0] ddr4_c2_odt, + output wire ddr4_c2_par, + output wire ddr4_c2_reset_n, + inout wire [71:0] ddr4_c2_dq, + inout wire [17:0] ddr4_c2_dqs_t, + inout wire [17:0] ddr4_c2_dqs_c, + + output wire [16:0] ddr4_c3_adr, + output wire [1:0] ddr4_c3_ba, + output wire [1:0] ddr4_c3_bg, + output wire [0:0] ddr4_c3_ck_t, + output wire [0:0] ddr4_c3_ck_c, + output wire [0:0] ddr4_c3_cke, + output wire [0:0] ddr4_c3_cs_n, + output wire ddr4_c3_act_n, + output wire [0:0] ddr4_c3_odt, + output wire ddr4_c3_par, + output wire ddr4_c3_reset_n, + inout wire [71:0] ddr4_c3_dq, + inout wire [17:0] ddr4_c3_dqs_t, + inout wire [17:0] ddr4_c3_dqs_c ); // PTP configuration @@ -274,6 +358,9 @@ parameter IF_PTP_PERIOD_FNS = 16'h6666; // Interface configuration parameter TX_TAG_WIDTH = 16; +// RAM configuration +parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8); + // Ethernet interface configuration parameter XGMII_DATA_WIDTH = 64; parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8; @@ -1487,6 +1574,519 @@ assign ptp_clk = qsfp0_mgt_refclk_1_bufg; assign ptp_rst = qsfp0_rst; assign ptp_sample_clk = clk_125mhz_int; +// DDR4 +wire [DDR_CH-1:0] ddr_clk; +wire [DDR_CH-1:0] ddr_rst; + +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr; +wire [DDR_CH*8-1:0] m_axi_ddr_awlen; +wire [DDR_CH*3-1:0] m_axi_ddr_awsize; +wire [DDR_CH*2-1:0] m_axi_ddr_awburst; +wire [DDR_CH-1:0] m_axi_ddr_awlock; +wire [DDR_CH*4-1:0] m_axi_ddr_awcache; +wire [DDR_CH*3-1:0] m_axi_ddr_awprot; +wire [DDR_CH*4-1:0] m_axi_ddr_awqos; +wire [DDR_CH-1:0] m_axi_ddr_awvalid; +wire [DDR_CH-1:0] m_axi_ddr_awready; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata; +wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb; +wire [DDR_CH-1:0] m_axi_ddr_wlast; +wire [DDR_CH-1:0] m_axi_ddr_wvalid; +wire [DDR_CH-1:0] m_axi_ddr_wready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid; +wire [DDR_CH*2-1:0] m_axi_ddr_bresp; +wire [DDR_CH-1:0] m_axi_ddr_bvalid; +wire [DDR_CH-1:0] m_axi_ddr_bready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr; +wire [DDR_CH*8-1:0] m_axi_ddr_arlen; +wire [DDR_CH*3-1:0] m_axi_ddr_arsize; +wire [DDR_CH*2-1:0] m_axi_ddr_arburst; +wire [DDR_CH-1:0] m_axi_ddr_arlock; +wire [DDR_CH*4-1:0] m_axi_ddr_arcache; +wire [DDR_CH*3-1:0] m_axi_ddr_arprot; +wire [DDR_CH*4-1:0] m_axi_ddr_arqos; +wire [DDR_CH-1:0] m_axi_ddr_arvalid; +wire [DDR_CH-1:0] m_axi_ddr_arready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata; +wire [DDR_CH*2-1:0] m_axi_ddr_rresp; +wire [DDR_CH-1:0] m_axi_ddr_rlast; +wire [DDR_CH-1:0] m_axi_ddr_rvalid; +wire [DDR_CH-1:0] m_axi_ddr_rready; + +wire [DDR_CH-1:0] ddr_status; + +generate + +if (DDR_ENABLE && DDR_CH > 0) begin + +ddr4_0 ddr4_c0_inst ( + .c0_sys_clk_p(clk_300mhz_0_p), + .c0_sys_clk_n(clk_300mhz_0_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[0 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c0_adr), + .c0_ddr4_ba(ddr4_c0_ba), + .c0_ddr4_cke(ddr4_c0_cke), + .c0_ddr4_cs_n(ddr4_c0_cs_n), + .c0_ddr4_dq(ddr4_c0_dq), + .c0_ddr4_dqs_t(ddr4_c0_dqs_t), + .c0_ddr4_dqs_c(ddr4_c0_dqs_c), + .c0_ddr4_odt(ddr4_c0_odt), + .c0_ddr4_parity(ddr4_c0_par), + .c0_ddr4_bg(ddr4_c0_bg), + .c0_ddr4_reset_n(ddr4_c0_reset_n), + .c0_ddr4_act_n(ddr4_c0_act_n), + .c0_ddr4_ck_t(ddr4_c0_ck_t), + .c0_ddr4_ck_c(ddr4_c0_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[0 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[0 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c0_adr = {17{1'bz}}; +assign ddr4_c0_ba = {2{1'bz}}; +assign ddr4_c0_bg = {2{1'bz}}; +assign ddr4_c0_cke = 1'bz; +assign ddr4_c0_cs_n = 1'bz; +assign ddr4_c0_act_n = 1'bz; +assign ddr4_c0_odt = 1'bz; +assign ddr4_c0_par = 1'bz; +assign ddr4_c0_reset_n = 1'b0; +assign ddr4_c0_dq = {72{1'bz}}; +assign ddr4_c0_dqs_t = {18{1'bz}}; +assign ddr4_c0_dqs_c = {18{1'bz}}; + +OBUFTDS ddr4_c0_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c0_ck_t), + .OB(ddr4_c0_ck_c) +); + +assign ddr_clk = 0; +assign ddr_rst = 0; + +assign m_axi_ddr_awready = 0; +assign m_axi_ddr_wready = 0; +assign m_axi_ddr_bid = 0; +assign m_axi_ddr_bresp = 0; +assign m_axi_ddr_bvalid = 0; +assign m_axi_ddr_arready = 0; +assign m_axi_ddr_rid = 0; +assign m_axi_ddr_rdata = 0; +assign m_axi_ddr_rresp = 0; +assign m_axi_ddr_rlast = 0; +assign m_axi_ddr_rvalid = 0; + +assign ddr_status = 0; + +end + +if (DDR_ENABLE && DDR_CH > 1) begin + +ddr4_0 ddr4_c1_inst ( + .c0_sys_clk_p(clk_300mhz_1_p), + .c0_sys_clk_n(clk_300mhz_1_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[1 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c1_adr), + .c0_ddr4_ba(ddr4_c1_ba), + .c0_ddr4_cke(ddr4_c1_cke), + .c0_ddr4_cs_n(ddr4_c1_cs_n), + .c0_ddr4_dq(ddr4_c1_dq), + .c0_ddr4_dqs_t(ddr4_c1_dqs_t), + .c0_ddr4_dqs_c(ddr4_c1_dqs_c), + .c0_ddr4_odt(ddr4_c1_odt), + .c0_ddr4_parity(ddr4_c1_par), + .c0_ddr4_bg(ddr4_c1_bg), + .c0_ddr4_reset_n(ddr4_c1_reset_n), + .c0_ddr4_act_n(ddr4_c1_act_n), + .c0_ddr4_ck_t(ddr4_c1_ck_t), + .c0_ddr4_ck_c(ddr4_c1_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[1 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[1 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[1 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[1*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[1*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[1*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[1 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[1*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[1*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[1*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[1 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[1 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[1*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[1 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[1 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[1 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[1 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[1*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[1 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[1*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[1*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[1*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[1 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[1*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[1*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[1*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[1 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[1 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[1 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[1 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[1 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[1*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c1_adr = {17{1'bz}}; +assign ddr4_c1_ba = {2{1'bz}}; +assign ddr4_c1_bg = {2{1'bz}}; +assign ddr4_c1_cke = 1'bz; +assign ddr4_c1_cs_n = 1'bz; +assign ddr4_c1_act_n = 1'bz; +assign ddr4_c1_odt = 1'bz; +assign ddr4_c1_par = 1'bz; +assign ddr4_c1_reset_n = 1'b0; +assign ddr4_c1_dq = {72{1'bz}}; +assign ddr4_c1_dqs_t = {18{1'bz}}; +assign ddr4_c1_dqs_c = {18{1'bz}}; + +OBUFTDS ddr4_c1_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c1_ck_t), + .OB(ddr4_c1_ck_c) +); + +end + +if (DDR_ENABLE && DDR_CH > 2) begin + +ddr4_0 ddr4_c2_inst ( + .c0_sys_clk_p(clk_300mhz_2_p), + .c0_sys_clk_n(clk_300mhz_2_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[2 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c2_adr), + .c0_ddr4_ba(ddr4_c2_ba), + .c0_ddr4_cke(ddr4_c2_cke), + .c0_ddr4_cs_n(ddr4_c2_cs_n), + .c0_ddr4_dq(ddr4_c2_dq), + .c0_ddr4_dqs_t(ddr4_c2_dqs_t), + .c0_ddr4_dqs_c(ddr4_c2_dqs_c), + .c0_ddr4_odt(ddr4_c2_odt), + .c0_ddr4_parity(ddr4_c2_par), + .c0_ddr4_bg(ddr4_c2_bg), + .c0_ddr4_reset_n(ddr4_c2_reset_n), + .c0_ddr4_act_n(ddr4_c2_act_n), + .c0_ddr4_ck_t(ddr4_c2_ck_t), + .c0_ddr4_ck_c(ddr4_c2_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[2 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[2 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[2 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[2*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[2*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[2*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[2 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[2*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[2*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[2*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[2 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[2 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[2*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[2 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[2 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[2 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[2 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[2*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[2 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[2*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[2*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[2*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[2 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[2*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[2*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[2*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[2 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[2 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[2 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[2 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[2 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[2*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c2_adr = {17{1'bz}}; +assign ddr4_c2_ba = {2{1'bz}}; +assign ddr4_c2_bg = {2{1'bz}}; +assign ddr4_c2_cke = 1'bz; +assign ddr4_c2_cs_n = 1'bz; +assign ddr4_c2_act_n = 1'bz; +assign ddr4_c2_odt = 1'bz; +assign ddr4_c2_par = 1'bz; +assign ddr4_c2_reset_n = 1'b0; +assign ddr4_c2_dq = {72{1'bz}}; +assign ddr4_c2_dqs_t = {18{1'bz}}; +assign ddr4_c2_dqs_c = {18{1'bz}}; + +OBUFTDS ddr4_c2_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c2_ck_t), + .OB(ddr4_c2_ck_c) +); + +end + +if (DDR_ENABLE && DDR_CH > 3) begin + +ddr4_0 ddr4_c3_inst ( + .c0_sys_clk_p(clk_300mhz_3_p), + .c0_sys_clk_n(clk_300mhz_3_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[3 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c3_adr), + .c0_ddr4_ba(ddr4_c3_ba), + .c0_ddr4_cke(ddr4_c3_cke), + .c0_ddr4_cs_n(ddr4_c3_cs_n), + .c0_ddr4_dq(ddr4_c3_dq), + .c0_ddr4_dqs_t(ddr4_c3_dqs_t), + .c0_ddr4_dqs_c(ddr4_c3_dqs_c), + .c0_ddr4_odt(ddr4_c3_odt), + .c0_ddr4_parity(ddr4_c3_par), + .c0_ddr4_bg(ddr4_c3_bg), + .c0_ddr4_reset_n(ddr4_c3_reset_n), + .c0_ddr4_act_n(ddr4_c3_act_n), + .c0_ddr4_ck_t(ddr4_c3_ck_t), + .c0_ddr4_ck_c(ddr4_c3_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[3 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[3 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[3 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[3*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[3*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[3*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[3 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[3*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[3*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[3*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[3 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[3 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[3*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[3 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[3 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[3 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[3 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[3*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[3 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[3*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[3*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[3*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[3 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[3*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[3*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[3*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[3 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[3 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[3 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[3 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[3 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[3*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c3_adr = {17{1'bz}}; +assign ddr4_c3_ba = {2{1'bz}}; +assign ddr4_c3_bg = {2{1'bz}}; +assign ddr4_c3_cke = 1'bz; +assign ddr4_c3_cs_n = 1'bz; +assign ddr4_c3_act_n = 1'bz; +assign ddr4_c3_odt = 1'bz; +assign ddr4_c3_par = 1'bz; +assign ddr4_c3_reset_n = 1'b0; +assign ddr4_c3_dq = {72{1'bz}}; +assign ddr4_c3_dqs_t = {18{1'bz}}; +assign ddr4_c3_dqs_c = {18{1'bz}}; + +OBUFTDS ddr4_c3_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c3_ck_t), + .OB(ddr4_c3_ck_c) +); + +end + +endgenerate + fpga_core #( // FW and board IDs .FPGA_ID(FPGA_ID), @@ -1563,6 +2163,16 @@ fpga_core #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1868,6 +2478,52 @@ core_inst ( .qsfp1_intl(qsfp1_intl_int), .qsfp1_lpmode(qsfp1_lpmode), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + /* * QSPI flash */ diff --git a/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v index 88fcc1762..9bf1044e3 100644 --- a/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v @@ -122,6 +122,16 @@ module fpga_core # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // RAM configuration + parameter DDR_CH = 4, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 34, + parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -429,6 +439,52 @@ module fpga_core # input wire qsfp1_intl, output wire qsfp1_lpmode, + /* + * DDR + */ + input wire [DDR_CH-1:0] ddr_clk, + input wire [DDR_CH-1:0] ddr_rst, + + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, + output wire [DDR_CH-1:0] m_axi_ddr_awlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, + output wire [DDR_CH-1:0] m_axi_ddr_awvalid, + input wire [DDR_CH-1:0] m_axi_ddr_awready, + output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, + output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, + output wire [DDR_CH-1:0] m_axi_ddr_wlast, + output wire [DDR_CH-1:0] m_axi_ddr_wvalid, + input wire [DDR_CH-1:0] m_axi_ddr_wready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, + input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, + input wire [DDR_CH-1:0] m_axi_ddr_bvalid, + output wire [DDR_CH-1:0] m_axi_ddr_bready, + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, + output wire [DDR_CH-1:0] m_axi_ddr_arlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, + output wire [DDR_CH-1:0] m_axi_ddr_arvalid, + input wire [DDR_CH-1:0] m_axi_ddr_arready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, + input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, + input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, + input wire [DDR_CH-1:0] m_axi_ddr_rlast, + input wire [DDR_CH-1:0] m_axi_ddr_rvalid, + output wire [DDR_CH-1:0] m_axi_ddr_rready, + + input wire [DDR_CH-1:0] ddr_status, + /* * QSPI flash */ @@ -1170,6 +1226,25 @@ mqnic_core_pcie_us #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .DDR_GROUP_SIZE(1), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_AWUSER_ENABLE(0), + .AXI_DDR_WUSER_ENABLE(0), + .AXI_DDR_BUSER_ENABLE(0), + .AXI_DDR_ARUSER_ENABLE(0), + .AXI_DDR_RUSER_ENABLE(0), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + .AXI_DDR_FIXED_BURST(0), + .AXI_DDR_WRAP_BURST(1), + .HBM_ENABLE(0), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1447,6 +1522,108 @@ core_inst ( .eth_rx_status(eth_rx_status), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awuser(), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wuser(), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_buser(0), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_aruser(), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_ruser(0), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + + /* + * HBM + */ + .hbm_clk(0), + .hbm_rst(0), + + .m_axi_hbm_awid(), + .m_axi_hbm_awaddr(), + .m_axi_hbm_awlen(), + .m_axi_hbm_awsize(), + .m_axi_hbm_awburst(), + .m_axi_hbm_awlock(), + .m_axi_hbm_awcache(), + .m_axi_hbm_awprot(), + .m_axi_hbm_awqos(), + .m_axi_hbm_awuser(), + .m_axi_hbm_awvalid(), + .m_axi_hbm_awready(0), + .m_axi_hbm_wdata(), + .m_axi_hbm_wstrb(), + .m_axi_hbm_wlast(), + .m_axi_hbm_wuser(), + .m_axi_hbm_wvalid(), + .m_axi_hbm_wready(0), + .m_axi_hbm_bid(0), + .m_axi_hbm_bresp(0), + .m_axi_hbm_buser(0), + .m_axi_hbm_bvalid(0), + .m_axi_hbm_bready(), + .m_axi_hbm_arid(), + .m_axi_hbm_araddr(), + .m_axi_hbm_arlen(), + .m_axi_hbm_arsize(), + .m_axi_hbm_arburst(), + .m_axi_hbm_arlock(), + .m_axi_hbm_arcache(), + .m_axi_hbm_arprot(), + .m_axi_hbm_arqos(), + .m_axi_hbm_aruser(), + .m_axi_hbm_arvalid(), + .m_axi_hbm_arready(0), + .m_axi_hbm_rid(0), + .m_axi_hbm_rdata(0), + .m_axi_hbm_rresp(0), + .m_axi_hbm_rlast(0), + .m_axi_hbm_ruser(0), + .m_axi_hbm_rvalid(0), + .m_axi_hbm_rready(), + + .hbm_status(0), + /* * Statistics input */ diff --git a/fpga/mqnic/AU250/fpga_100g/README.md b/fpga/mqnic/AU250/fpga_100g/README.md index 6f4664eb6..b45f4dc65 100644 --- a/fpga/mqnic/AU250/fpga_100g/README.md +++ b/fpga/mqnic/AU250/fpga_100g/README.md @@ -7,6 +7,7 @@ This design targets the Xilinx Alveo U250 FPGA board. * FPGA: xcu250-figd2104-2-e * MAC: Xilinx 100G CMAC * PHY: 100G CAUI-4 CMAC and internal GTY transceivers +* RAM: 64 GB DDR4 2400 (4x 2G x72 DIMM) ## How to build diff --git a/fpga/mqnic/AU250/fpga_100g/fpga.xdc b/fpga/mqnic/AU250/fpga_100g/fpga.xdc index cd32c07bf..c77349170 100644 --- a/fpga/mqnic/AU250/fpga_100g/fpga.xdc +++ b/fpga/mqnic/AU250/fpga_100g/fpga.xdc @@ -17,23 +17,23 @@ set_operating_conditions -design_power_budget 160 # System clocks # 300 MHz (DDR 0) -#set_property -dict {LOC AY37 IOSTANDARD LVDS} [get_ports clk_300mhz_0_p] -#set_property -dict {LOC AY38 IOSTANDARD LVDS} [get_ports clk_300mhz_0_n] +set_property -dict {LOC AY37 IOSTANDARD LVDS} [get_ports clk_300mhz_0_p] +set_property -dict {LOC AY38 IOSTANDARD LVDS} [get_ports clk_300mhz_0_n] #create_clock -period 3.333 -name clk_300mhz_0 [get_ports clk_300mhz_0_p] # 300 MHz (DDR 1) -#set_property -dict {LOC AW20 IOSTANDARD LVDS} [get_ports clk_300mhz_1_p] -#set_property -dict {LOC AW19 IOSTANDARD LVDS} [get_ports clk_300mhz_1_n] +set_property -dict {LOC AW20 IOSTANDARD LVDS} [get_ports clk_300mhz_1_p] +set_property -dict {LOC AW19 IOSTANDARD LVDS} [get_ports clk_300mhz_1_n] #create_clock -period 3.333 -name clk_300mhz_1 [get_ports clk_300mhz_1_p] # 300 MHz (DDR 2) -#set_property -dict {LOC F32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_p] -#set_property -dict {LOC E32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_n] +set_property -dict {LOC F32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_p] +set_property -dict {LOC E32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_n] #create_clock -period 3.333 -name clk_300mhz_2 [get_ports clk_300mhz_2_p] # 300 MHz (DDR 3) -#set_property -dict {LOC J16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_p] -#set_property -dict {LOC H16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_n] +set_property -dict {LOC J16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_p] +set_property -dict {LOC H16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_n] #create_clock -period 3.333 -name clk_300mhz_3 [get_ports clk_300mhz_3_p] # SI570 user clock @@ -257,3 +257,591 @@ create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_p] set_false_path -from [get_ports {pcie_reset_n}] set_input_delay 0 [get_ports {pcie_reset_n}] + +# DDR4 C0 +set_property -dict {LOC AT36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}] +set_property -dict {LOC AV36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}] +set_property -dict {LOC AV37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}] +set_property -dict {LOC AW35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}] +set_property -dict {LOC AW36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}] +set_property -dict {LOC AY36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}] +set_property -dict {LOC AY35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}] +set_property -dict {LOC BA40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}] +set_property -dict {LOC BA37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}] +set_property -dict {LOC BB37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}] +set_property -dict {LOC AR35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}] +set_property -dict {LOC BA39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}] +set_property -dict {LOC BB40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}] +set_property -dict {LOC AN36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}] +set_property -dict {LOC AP35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}] +set_property -dict {LOC AP36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}] +set_property -dict {LOC AR36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}] +set_property -dict {LOC AT35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}] +set_property -dict {LOC AT34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}] +set_property -dict {LOC BC37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}] +set_property -dict {LOC BC39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}] +set_property -dict {LOC AV38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t[0]}] +set_property -dict {LOC AW38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c[0]}] +#set_property -dict {LOC AU34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t[1]}] +#set_property -dict {LOC AU35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c[1]}] +set_property -dict {LOC BC38 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[0]}] +#set_property -dict {LOC BC40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[1]}] +set_property -dict {LOC AR33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[0]}] +#set_property -dict {LOC AP33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[1]}] +#set_property -dict {LOC AN33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[2]}] +#set_property -dict {LOC AM34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[3]}] +set_property -dict {LOC BB39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}] +set_property -dict {LOC AP34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[0]}] +#set_property -dict {LOC AN34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[1]}] +set_property -dict {LOC AU36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}] +set_property -dict {LOC AU31 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_reset_n}] + +set_property -dict {LOC AW28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}] +set_property -dict {LOC AW29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}] +set_property -dict {LOC BA28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}] +set_property -dict {LOC BA27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}] +set_property -dict {LOC BB29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}] +set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}] +set_property -dict {LOC BC27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}] +set_property -dict {LOC BB27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}] +set_property -dict {LOC BE28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}] +set_property -dict {LOC BF28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}] +set_property -dict {LOC BE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}] +set_property -dict {LOC BD30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}] +set_property -dict {LOC BF27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}] +set_property -dict {LOC BE27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}] +set_property -dict {LOC BF30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}] +set_property -dict {LOC BF29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}] +set_property -dict {LOC BB31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}] +set_property -dict {LOC BB32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}] +set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}] +set_property -dict {LOC AY33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}] +set_property -dict {LOC BC32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}] +set_property -dict {LOC BC33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}] +set_property -dict {LOC BB34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}] +set_property -dict {LOC BC34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}] +set_property -dict {LOC AV31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}] +set_property -dict {LOC AV32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}] +set_property -dict {LOC AV34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}] +set_property -dict {LOC AW34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}] +set_property -dict {LOC AW31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}] +set_property -dict {LOC AY31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}] +set_property -dict {LOC BA35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}] +set_property -dict {LOC BA34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}] +set_property -dict {LOC AL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}] +set_property -dict {LOC AM30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}] +set_property -dict {LOC AU32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}] +set_property -dict {LOC AT32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}] +set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}] +set_property -dict {LOC AN32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}] +set_property -dict {LOC AR32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}] +set_property -dict {LOC AR31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}] +set_property -dict {LOC AP29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}] +set_property -dict {LOC AP28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}] +set_property -dict {LOC AN27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}] +set_property -dict {LOC AM27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}] +set_property -dict {LOC AN29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}] +set_property -dict {LOC AM29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}] +set_property -dict {LOC AR27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}] +set_property -dict {LOC AR28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}] +set_property -dict {LOC AT28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}] +set_property -dict {LOC AV27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}] +set_property -dict {LOC AU27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}] +set_property -dict {LOC AT27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}] +set_property -dict {LOC AV29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}] +set_property -dict {LOC AY30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}] +set_property -dict {LOC AW30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}] +set_property -dict {LOC AV28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}] +set_property -dict {LOC BD34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}] +set_property -dict {LOC BD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}] +set_property -dict {LOC BE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}] +set_property -dict {LOC BD35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}] +set_property -dict {LOC BF32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}] +set_property -dict {LOC BF33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}] +set_property -dict {LOC BF34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}] +set_property -dict {LOC BF35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}] +set_property -dict {LOC BD40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}] +set_property -dict {LOC BD39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}] +set_property -dict {LOC BF43 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}] +set_property -dict {LOC BF42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}] +set_property -dict {LOC BF37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}] +set_property -dict {LOC BE37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}] +set_property -dict {LOC BE40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}] +set_property -dict {LOC BF41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}] +set_property -dict {LOC BA30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}] +set_property -dict {LOC BB30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}] +set_property -dict {LOC BB26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}] +set_property -dict {LOC BC26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}] +set_property -dict {LOC BD28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}] +set_property -dict {LOC BD29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}] +set_property -dict {LOC BD26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}] +set_property -dict {LOC BE26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}] +set_property -dict {LOC BB35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}] +set_property -dict {LOC BB36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}] +set_property -dict {LOC BC31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}] +set_property -dict {LOC BD31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}] +set_property -dict {LOC AV33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}] +set_property -dict {LOC AW33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}] +set_property -dict {LOC BA32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}] +set_property -dict {LOC BA33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}] +set_property -dict {LOC AM31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}] +set_property -dict {LOC AM32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}] +set_property -dict {LOC AP30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[9]}] +set_property -dict {LOC AP31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[9]}] +set_property -dict {LOC AL28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[10]}] +set_property -dict {LOC AL29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[10]}] +set_property -dict {LOC AR30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[11]}] +set_property -dict {LOC AT30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[11]}] +set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[12]}] +set_property -dict {LOC AU30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[12]}] +set_property -dict {LOC AY27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[13]}] +set_property -dict {LOC AY28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[13]}] +set_property -dict {LOC BE35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[14]}] +set_property -dict {LOC BE36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[14]}] +set_property -dict {LOC BE31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[15]}] +set_property -dict {LOC BE32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[15]}] +set_property -dict {LOC BE38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[16]}] +set_property -dict {LOC BF38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[16]}] +set_property -dict {LOC BF39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[17]}] +set_property -dict {LOC BF40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[17]}] + +# DDR4 C1 +set_property -dict {LOC AN24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}] +set_property -dict {LOC AT24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}] +set_property -dict {LOC AW24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}] +set_property -dict {LOC AN26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}] +set_property -dict {LOC AY22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}] +set_property -dict {LOC AY23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}] +set_property -dict {LOC AV24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}] +set_property -dict {LOC BA22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}] +set_property -dict {LOC AY25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}] +set_property -dict {LOC BA23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}] +set_property -dict {LOC AM26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}] +set_property -dict {LOC BA25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}] +set_property -dict {LOC BB22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}] +set_property -dict {LOC AL24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}] +set_property -dict {LOC AL25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}] +set_property -dict {LOC AM25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}] +set_property -dict {LOC AN23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}] +set_property -dict {LOC AU24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}] +set_property -dict {LOC AP26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}] +set_property -dict {LOC BC22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}] +set_property -dict {LOC AW26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}] +set_property -dict {LOC AT25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t[0]}] +set_property -dict {LOC AU25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c[0]}] +#set_property -dict {LOC AU26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t[1]}] +#set_property -dict {LOC AV26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c[1]}] +set_property -dict {LOC BB25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[0]}] +#set_property -dict {LOC BB24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[1]}] +set_property -dict {LOC AV23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[0]}] +#set_property -dict {LOC AP25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[1]}] +#set_property -dict {LOC AR23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[2]}] +#set_property -dict {LOC AP23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[3]}] +set_property -dict {LOC AW25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}] +set_property -dict {LOC AW23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[0]}] +#set_property -dict {LOC AP24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[1]}] +set_property -dict {LOC AT23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}] +set_property -dict {LOC AR17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}] + +set_property -dict {LOC BD9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] +set_property -dict {LOC BD7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] +set_property -dict {LOC BC7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] +set_property -dict {LOC BD8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] +set_property -dict {LOC BD10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] +set_property -dict {LOC BE10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] +set_property -dict {LOC BE7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] +set_property -dict {LOC BF7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] +set_property -dict {LOC AU13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] +set_property -dict {LOC AV13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] +set_property -dict {LOC AW13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] +set_property -dict {LOC AW14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] +set_property -dict {LOC AU14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] +set_property -dict {LOC AY11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] +set_property -dict {LOC AV14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] +set_property -dict {LOC BA11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] +set_property -dict {LOC BA12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] +set_property -dict {LOC BB12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] +set_property -dict {LOC BA13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] +set_property -dict {LOC BA14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] +set_property -dict {LOC BC9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] +set_property -dict {LOC BB9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] +set_property -dict {LOC BA7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] +set_property -dict {LOC BA8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] +set_property -dict {LOC AN13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] +set_property -dict {LOC AR13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] +set_property -dict {LOC AM13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] +set_property -dict {LOC AP13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] +set_property -dict {LOC AM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] +set_property -dict {LOC AR15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] +set_property -dict {LOC AL14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] +set_property -dict {LOC AT15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] +set_property -dict {LOC BE13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] +set_property -dict {LOC BD14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] +set_property -dict {LOC BF12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] +set_property -dict {LOC BD13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] +set_property -dict {LOC BD15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] +set_property -dict {LOC BD16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] +set_property -dict {LOC BF14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] +set_property -dict {LOC BF13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] +set_property -dict {LOC AY17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] +set_property -dict {LOC BA17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] +set_property -dict {LOC AY18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] +set_property -dict {LOC BA18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] +set_property -dict {LOC BA15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] +set_property -dict {LOC BB15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] +set_property -dict {LOC BC11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] +set_property -dict {LOC BD11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] +set_property -dict {LOC AV16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] +set_property -dict {LOC AV17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] +set_property -dict {LOC AU16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] +set_property -dict {LOC AU17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] +set_property -dict {LOC BB17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] +set_property -dict {LOC BB16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] +set_property -dict {LOC AT18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] +set_property -dict {LOC AT17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] +set_property -dict {LOC AM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] +set_property -dict {LOC AL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] +set_property -dict {LOC AN17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] +set_property -dict {LOC AN16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] +set_property -dict {LOC AR18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] +set_property -dict {LOC AP18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] +set_property -dict {LOC AL17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] +set_property -dict {LOC AL16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] +set_property -dict {LOC BF25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}] +set_property -dict {LOC BF24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}] +set_property -dict {LOC BD25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}] +set_property -dict {LOC BE25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}] +set_property -dict {LOC BD23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}] +set_property -dict {LOC BC23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}] +set_property -dict {LOC BF23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}] +set_property -dict {LOC BE23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}] +set_property -dict {LOC BF10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] +set_property -dict {LOC BF9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] +set_property -dict {LOC BE8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] +set_property -dict {LOC BF8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] +set_property -dict {LOC AW15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] +set_property -dict {LOC AY15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] +set_property -dict {LOC AY13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] +set_property -dict {LOC AY12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] +set_property -dict {LOC BB11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] +set_property -dict {LOC BB10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] +set_property -dict {LOC BA10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] +set_property -dict {LOC BA9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] +set_property -dict {LOC AT14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] +set_property -dict {LOC AT13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] +set_property -dict {LOC AN14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] +set_property -dict {LOC AP14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] +set_property -dict {LOC BE12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}] +set_property -dict {LOC BE11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}] +set_property -dict {LOC BE15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}] +set_property -dict {LOC BF15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}] +set_property -dict {LOC BC13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[10]}] +set_property -dict {LOC BC12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[10]}] +set_property -dict {LOC BB14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[11]}] +set_property -dict {LOC BC14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[11]}] +set_property -dict {LOC AV18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[12]}] +set_property -dict {LOC AW18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[12]}] +set_property -dict {LOC AW16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[13]}] +set_property -dict {LOC AY16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[13]}] +set_property -dict {LOC AP16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[14]}] +set_property -dict {LOC AR16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[14]}] +set_property -dict {LOC AM17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[15]}] +set_property -dict {LOC AM16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[15]}] +set_property -dict {LOC BC24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[16]}] +set_property -dict {LOC BD24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[16]}] +set_property -dict {LOC BE22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[17]}] +set_property -dict {LOC BF22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[17]}] + +# DDR4 C2 +set_property -dict {LOC L29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[0]}] +set_property -dict {LOC A33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[1]}] +set_property -dict {LOC C33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[2]}] +set_property -dict {LOC J29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[3]}] +set_property -dict {LOC H31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[4]}] +set_property -dict {LOC G31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[5]}] +set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[6]}] +set_property -dict {LOC B32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[7]}] +set_property -dict {LOC A32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[8]}] +set_property -dict {LOC D31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[9]}] +set_property -dict {LOC A34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[10]}] +set_property -dict {LOC E31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[11]}] +set_property -dict {LOC M30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[12]}] +set_property -dict {LOC F33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[13]}] +set_property -dict {LOC A35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[14]}] +set_property -dict {LOC G32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[15]}] +set_property -dict {LOC K30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[16]}] +set_property -dict {LOC D33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[0]}] +set_property -dict {LOC B36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[1]}] +set_property -dict {LOC C31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[0]}] +set_property -dict {LOC J30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[1]}] +set_property -dict {LOC C34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t[0]}] +set_property -dict {LOC B34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c[0]}] +#set_property -dict {LOC D34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t[1]}] +#set_property -dict {LOC D35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c[1]}] +set_property -dict {LOC G30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[0]}] +#set_property -dict {LOC E30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[1]}] +set_property -dict {LOC B35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[0]}] +#set_property -dict {LOC J31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[1]}] +#set_property -dict {LOC L30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[2]}] +#set_property -dict {LOC K31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[3]}] +set_property -dict {LOC B31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_act_n}] +set_property -dict {LOC E33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[0]}] +#set_property -dict {LOC F34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[1]}] +set_property -dict {LOC M29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_par}] +set_property -dict {LOC D36 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_reset_n}] + +set_property -dict {LOC R25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[0]}] +set_property -dict {LOC P25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[1]}] +set_property -dict {LOC M25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[2]}] +set_property -dict {LOC L25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[3]}] +set_property -dict {LOC P26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[4]}] +set_property -dict {LOC R26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[5]}] +set_property -dict {LOC N27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[6]}] +set_property -dict {LOC N28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[7]}] +set_property -dict {LOC J28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[8]}] +set_property -dict {LOC H29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[9]}] +set_property -dict {LOC H28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[10]}] +set_property -dict {LOC G29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[11]}] +set_property -dict {LOC K25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[12]}] +set_property -dict {LOC L27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[13]}] +set_property -dict {LOC K26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[14]}] +set_property -dict {LOC K27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[15]}] +set_property -dict {LOC F27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[16]}] +set_property -dict {LOC E27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[17]}] +set_property -dict {LOC E28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[18]}] +set_property -dict {LOC D28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[19]}] +set_property -dict {LOC G27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[20]}] +set_property -dict {LOC G26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[21]}] +set_property -dict {LOC F28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[22]}] +set_property -dict {LOC F29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[23]}] +set_property -dict {LOC D26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[24]}] +set_property -dict {LOC C26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[25]}] +set_property -dict {LOC B27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[26]}] +set_property -dict {LOC B26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[27]}] +set_property -dict {LOC A29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[28]}] +set_property -dict {LOC A30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[29]}] +set_property -dict {LOC C27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[30]}] +set_property -dict {LOC C28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[31]}] +set_property -dict {LOC F35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[32]}] +set_property -dict {LOC E38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[33]}] +set_property -dict {LOC D38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[34]}] +set_property -dict {LOC E35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[35]}] +set_property -dict {LOC E36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[36]}] +set_property -dict {LOC E37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[37]}] +set_property -dict {LOC F38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[38]}] +set_property -dict {LOC G38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[39]}] +set_property -dict {LOC P30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[40]}] +set_property -dict {LOC R30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[41]}] +set_property -dict {LOC P29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[42]}] +set_property -dict {LOC N29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[43]}] +set_property -dict {LOC L32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[44]}] +set_property -dict {LOC M32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[45]}] +set_property -dict {LOC P31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[46]}] +set_property -dict {LOC N32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[47]}] +set_property -dict {LOC J35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[48]}] +set_property -dict {LOC K35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[49]}] +set_property -dict {LOC L33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[50]}] +set_property -dict {LOC K33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[51]}] +set_property -dict {LOC J34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[52]}] +set_property -dict {LOC J33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[53]}] +set_property -dict {LOC N34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[54]}] +set_property -dict {LOC P34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[55]}] +set_property -dict {LOC H36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[56]}] +set_property -dict {LOC G36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[57]}] +set_property -dict {LOC H37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[58]}] +set_property -dict {LOC J36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[59]}] +set_property -dict {LOC K37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[60]}] +set_property -dict {LOC K38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[61]}] +set_property -dict {LOC G35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[62]}] +set_property -dict {LOC G34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[63]}] +set_property -dict {LOC C36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[64]}] +set_property -dict {LOC B37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[65]}] +set_property -dict {LOC A37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[66]}] +set_property -dict {LOC A38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[67]}] +set_property -dict {LOC C39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[68]}] +set_property -dict {LOC D39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[69]}] +set_property -dict {LOC A40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[70]}] +set_property -dict {LOC B40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[71]}] +set_property -dict {LOC N26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[0]}] +set_property -dict {LOC M26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[0]}] +set_property -dict {LOC R28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[1]}] +set_property -dict {LOC P28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[1]}] +set_property -dict {LOC J25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[2]}] +set_property -dict {LOC J26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[2]}] +set_property -dict {LOC M27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[3]}] +set_property -dict {LOC L28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[3]}] +set_property -dict {LOC D29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[4]}] +set_property -dict {LOC D30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[4]}] +set_property -dict {LOC H26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[5]}] +set_property -dict {LOC H27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[5]}] +set_property -dict {LOC A27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[6]}] +set_property -dict {LOC A28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[6]}] +set_property -dict {LOC C29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[7]}] +set_property -dict {LOC B29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[7]}] +set_property -dict {LOC E39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[8]}] +set_property -dict {LOC E40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[8]}] +set_property -dict {LOC G37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[9]}] +set_property -dict {LOC F37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[9]}] +set_property -dict {LOC N31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[10]}] +set_property -dict {LOC M31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[10]}] +set_property -dict {LOC T30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[11]}] +set_property -dict {LOC R31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[11]}] +set_property -dict {LOC L35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[12]}] +set_property -dict {LOC L36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[12]}] +set_property -dict {LOC M34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[13]}] +set_property -dict {LOC L34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[13]}] +set_property -dict {LOC J38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[14]}] +set_property -dict {LOC H38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[14]}] +set_property -dict {LOC H33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[15]}] +set_property -dict {LOC H34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[15]}] +set_property -dict {LOC B39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[16]}] +set_property -dict {LOC A39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[16]}] +set_property -dict {LOC C37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[17]}] +set_property -dict {LOC C38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[17]}] + +# DDR4 C3 +set_property -dict {LOC K15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[0]}] +set_property -dict {LOC B15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[1]}] +set_property -dict {LOC F14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[2]}] +set_property -dict {LOC A15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[3]}] +set_property -dict {LOC C14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[4]}] +set_property -dict {LOC A14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[5]}] +set_property -dict {LOC B14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[6]}] +set_property -dict {LOC E13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[7]}] +set_property -dict {LOC F13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[8]}] +set_property -dict {LOC A13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[9]}] +set_property -dict {LOC D14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[10]}] +set_property -dict {LOC C13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[11]}] +set_property -dict {LOC B13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[12]}] +set_property -dict {LOC K16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[13]}] +set_property -dict {LOC D15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[14]}] +set_property -dict {LOC E15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[15]}] +set_property -dict {LOC F15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[16]}] +set_property -dict {LOC J15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[0]}] +set_property -dict {LOC H14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[1]}] +set_property -dict {LOC D13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[0]}] +set_property -dict {LOC J13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[1]}] +set_property -dict {LOC L14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t[0]}] +set_property -dict {LOC L13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c[0]}] +#set_property -dict {LOC G14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t[1]}] +#set_property -dict {LOC G13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c[1]}] +set_property -dict {LOC K13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[0]}] +#set_property -dict {LOC L15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[1]}] +set_property -dict {LOC B16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[0]}] +#set_property -dict {LOC D16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[1]}] +#set_property -dict {LOC M14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[2]}] +#set_property -dict {LOC M13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[3]}] +set_property -dict {LOC H13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_act_n}] +set_property -dict {LOC C16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[0]}] +#set_property -dict {LOC E16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[1]}] +set_property -dict {LOC J14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_par}] +set_property -dict {LOC D21 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c3_reset_n}] + +set_property -dict {LOC P24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[0]}] +set_property -dict {LOC N24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[1]}] +set_property -dict {LOC T24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[2]}] +set_property -dict {LOC R23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[3]}] +set_property -dict {LOC N23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[4]}] +set_property -dict {LOC P21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[5]}] +set_property -dict {LOC P23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[6]}] +set_property -dict {LOC R21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[7]}] +set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[8]}] +set_property -dict {LOC J23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[9]}] +set_property -dict {LOC H24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[10]}] +set_property -dict {LOC G24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[11]}] +set_property -dict {LOC L24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[12]}] +set_property -dict {LOC L23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[13]}] +set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[14]}] +set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[15]}] +set_property -dict {LOC G20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[16]}] +set_property -dict {LOC H17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[17]}] +set_property -dict {LOC F19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[18]}] +set_property -dict {LOC G17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[19]}] +set_property -dict {LOC J20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[20]}] +set_property -dict {LOC L19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[21]}] +set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[22]}] +set_property -dict {LOC J19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[23]}] +set_property -dict {LOC M19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[24]}] +set_property -dict {LOC M20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[25]}] +set_property -dict {LOC R18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[26]}] +set_property -dict {LOC R17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[27]}] +set_property -dict {LOC R20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[28]}] +set_property -dict {LOC T20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[29]}] +set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[30]}] +set_property -dict {LOC N19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[31]}] +set_property -dict {LOC A23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[32]}] +set_property -dict {LOC A22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[33]}] +set_property -dict {LOC B24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[34]}] +set_property -dict {LOC B25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[35]}] +set_property -dict {LOC B22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[36]}] +set_property -dict {LOC C22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[37]}] +set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[38]}] +set_property -dict {LOC C23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[39]}] +set_property -dict {LOC C19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[40]}] +set_property -dict {LOC C18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[41]}] +set_property -dict {LOC C21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[42]}] +set_property -dict {LOC B21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[43]}] +set_property -dict {LOC A18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[44]}] +set_property -dict {LOC A17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[45]}] +set_property -dict {LOC A20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[46]}] +set_property -dict {LOC B20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[47]}] +set_property -dict {LOC E17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[48]}] +set_property -dict {LOC F20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[49]}] +set_property -dict {LOC E18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[50]}] +set_property -dict {LOC E20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[51]}] +set_property -dict {LOC D19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[52]}] +set_property -dict {LOC D20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[53]}] +set_property -dict {LOC H18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[54]}] +set_property -dict {LOC J18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[55]}] +set_property -dict {LOC F22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[56]}] +set_property -dict {LOC E22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[57]}] +set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[58]}] +set_property -dict {LOC G21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[59]}] +set_property -dict {LOC F24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[60]}] +set_property -dict {LOC E25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[61]}] +set_property -dict {LOC F25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[62]}] +set_property -dict {LOC G25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[63]}] +set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[64]}] +set_property -dict {LOC N16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[65]}] +set_property -dict {LOC N13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[66]}] +set_property -dict {LOC N14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[67]}] +set_property -dict {LOC T15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[68]}] +set_property -dict {LOC R15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[69]}] +set_property -dict {LOC P13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[70]}] +set_property -dict {LOC P14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[71]}] +set_property -dict {LOC T22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[0]}] +set_property -dict {LOC R22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[0]}] +set_property -dict {LOC N22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[1]}] +set_property -dict {LOC N21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[1]}] +set_property -dict {LOC J21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[2]}] +set_property -dict {LOC H21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[2]}] +set_property -dict {LOC M22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[3]}] +set_property -dict {LOC L22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[3]}] +set_property -dict {LOC L20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[4]}] +set_property -dict {LOC K20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[4]}] +set_property -dict {LOC K18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[5]}] +set_property -dict {LOC K17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[5]}] +set_property -dict {LOC P19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[6]}] +set_property -dict {LOC P18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[6]}] +set_property -dict {LOC N17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[7]}] +set_property -dict {LOC M17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[7]}] +set_property -dict {LOC A25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[8]}] +set_property -dict {LOC A24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[8]}] +set_property -dict {LOC D24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[9]}] +set_property -dict {LOC D23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[9]}] +set_property -dict {LOC C17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[10]}] +set_property -dict {LOC B17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[10]}] +set_property -dict {LOC B19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[11]}] +set_property -dict {LOC A19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[11]}] +set_property -dict {LOC F18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[12]}] +set_property -dict {LOC F17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[12]}] +set_property -dict {LOC H19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[13]}] +set_property -dict {LOC G19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[13]}] +set_property -dict {LOC F23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[14]}] +set_property -dict {LOC E23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[14]}] +set_property -dict {LOC H23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[15]}] +set_property -dict {LOC H22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[15]}] +set_property -dict {LOC R16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[16]}] +set_property -dict {LOC P15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[16]}] +set_property -dict {LOC T13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[17]}] +set_property -dict {LOC R13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[17]}] diff --git a/fpga/mqnic/AU250/fpga_100g/fpga/Makefile b/fpga/mqnic/AU250/fpga_100g/fpga/Makefile index e24846446..a7ceeb9d5 100644 --- a/fpga/mqnic/AU250/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/AU250/fpga_100g/fpga/Makefile @@ -125,6 +125,7 @@ IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/cmac_usplus_0.tcl IP_TCL_FILES += ip/cmac_usplus_1.tcl IP_TCL_FILES += ip/cms.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/AU250/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU250/fpga_100g/fpga/config.tcl index 90dea6058..00879da2e 100644 --- a/fpga/mqnic/AU250/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/AU250/fpga_100g/fpga/config.tcl @@ -136,6 +136,12 @@ dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "131072" dict set params RX_RAM_SIZE "131072" + +# RAM configuration +dict set params DDR_CH "4" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" # Application block configuration dict set params APP_ID "32'h00000000" @@ -187,6 +193,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/AU250/fpga_100g/ip/ddr4_0.tcl b/fpga/mqnic/AU250/fpga_100g/ip/ddr4_0.tcl new file mode 100644 index 000000000..27252f502 --- /dev/null +++ b/fpga/mqnic/AU250/fpga_100g/ip/ddr4_0.tcl @@ -0,0 +1,17 @@ + +create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 + +set_property -dict [list \ + CONFIG.C0.DDR4_AxiSelection {true} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_AxiIDWidth {8} \ + CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ + CONFIG.C0.DDR4_TimePeriod {833} \ + CONFIG.C0.DDR4_InputClockPeriod {3332} \ + CONFIG.C0.DDR4_MemoryType {RDIMMs} \ + CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PZ-2G3} \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_CasLatency {17} \ + CONFIG.C0.DDR4_CasWriteLatency {12} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} +] [get_ips ddr4_0] diff --git a/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v index 913154f3e..061cdb895 100644 --- a/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/AU250/fpga_100g/rtl/fpga.v @@ -109,6 +109,15 @@ module fpga # parameter TX_RAM_SIZE = 131072, parameter RX_RAM_SIZE = 131072, + // RAM configuration + parameter DDR_CH = 4, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 34, + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -173,6 +182,18 @@ module fpga # parameter STAT_ID_WIDTH = 12 ) ( + /* + * Clock and reset + */ + input wire clk_300mhz_0_p, + input wire clk_300mhz_0_n, + input wire clk_300mhz_1_p, + input wire clk_300mhz_1_n, + input wire clk_300mhz_2_p, + input wire clk_300mhz_2_n, + input wire clk_300mhz_3_p, + input wire clk_300mhz_3_n, + /* * GPIO */ @@ -256,7 +277,70 @@ module fpga # input wire qsfp1_intl, output wire qsfp1_lpmode, output wire qsfp1_refclk_reset, - output wire [1:0] qsfp1_fs + output wire [1:0] qsfp1_fs, + + /* + * DDR4 + */ + output wire [16:0] ddr4_c0_adr, + output wire [1:0] ddr4_c0_ba, + output wire [1:0] ddr4_c0_bg, + output wire [0:0] ddr4_c0_ck_t, + output wire [0:0] ddr4_c0_ck_c, + output wire [0:0] ddr4_c0_cke, + output wire [0:0] ddr4_c0_cs_n, + output wire ddr4_c0_act_n, + output wire [0:0] ddr4_c0_odt, + output wire ddr4_c0_par, + output wire ddr4_c0_reset_n, + inout wire [71:0] ddr4_c0_dq, + inout wire [17:0] ddr4_c0_dqs_t, + inout wire [17:0] ddr4_c0_dqs_c, + + output wire [16:0] ddr4_c1_adr, + output wire [1:0] ddr4_c1_ba, + output wire [1:0] ddr4_c1_bg, + output wire [0:0] ddr4_c1_ck_t, + output wire [0:0] ddr4_c1_ck_c, + output wire [0:0] ddr4_c1_cke, + output wire [0:0] ddr4_c1_cs_n, + output wire ddr4_c1_act_n, + output wire [0:0] ddr4_c1_odt, + output wire ddr4_c1_par, + output wire ddr4_c1_reset_n, + inout wire [71:0] ddr4_c1_dq, + inout wire [17:0] ddr4_c1_dqs_t, + inout wire [17:0] ddr4_c1_dqs_c, + + output wire [16:0] ddr4_c2_adr, + output wire [1:0] ddr4_c2_ba, + output wire [1:0] ddr4_c2_bg, + output wire [0:0] ddr4_c2_ck_t, + output wire [0:0] ddr4_c2_ck_c, + output wire [0:0] ddr4_c2_cke, + output wire [0:0] ddr4_c2_cs_n, + output wire ddr4_c2_act_n, + output wire [0:0] ddr4_c2_odt, + output wire ddr4_c2_par, + output wire ddr4_c2_reset_n, + inout wire [71:0] ddr4_c2_dq, + inout wire [17:0] ddr4_c2_dqs_t, + inout wire [17:0] ddr4_c2_dqs_c, + + output wire [16:0] ddr4_c3_adr, + output wire [1:0] ddr4_c3_ba, + output wire [1:0] ddr4_c3_bg, + output wire [0:0] ddr4_c3_ck_t, + output wire [0:0] ddr4_c3_ck_c, + output wire [0:0] ddr4_c3_cke, + output wire [0:0] ddr4_c3_cs_n, + output wire ddr4_c3_act_n, + output wire [0:0] ddr4_c3_odt, + output wire ddr4_c3_par, + output wire ddr4_c3_reset_n, + inout wire [71:0] ddr4_c3_dq, + inout wire [17:0] ddr4_c3_dqs_t, + inout wire [17:0] ddr4_c3_dqs_c ); // PTP configuration @@ -269,6 +353,9 @@ parameter PTP_SEPARATE_RX_CLOCK = 1; // Interface configuration parameter TX_TAG_WIDTH = 16; +// RAM configuration +parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8); + // Ethernet interface configuration parameter AXIS_ETH_DATA_WIDTH = 512; parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; @@ -1889,6 +1976,519 @@ assign led[0] = led_int[0]; // red assign led[1] = qsfp1_rx_status; // yellow assign led[2] = qsfp0_rx_status; // green +// DDR4 +wire [DDR_CH-1:0] ddr_clk; +wire [DDR_CH-1:0] ddr_rst; + +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr; +wire [DDR_CH*8-1:0] m_axi_ddr_awlen; +wire [DDR_CH*3-1:0] m_axi_ddr_awsize; +wire [DDR_CH*2-1:0] m_axi_ddr_awburst; +wire [DDR_CH-1:0] m_axi_ddr_awlock; +wire [DDR_CH*4-1:0] m_axi_ddr_awcache; +wire [DDR_CH*3-1:0] m_axi_ddr_awprot; +wire [DDR_CH*4-1:0] m_axi_ddr_awqos; +wire [DDR_CH-1:0] m_axi_ddr_awvalid; +wire [DDR_CH-1:0] m_axi_ddr_awready; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata; +wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb; +wire [DDR_CH-1:0] m_axi_ddr_wlast; +wire [DDR_CH-1:0] m_axi_ddr_wvalid; +wire [DDR_CH-1:0] m_axi_ddr_wready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid; +wire [DDR_CH*2-1:0] m_axi_ddr_bresp; +wire [DDR_CH-1:0] m_axi_ddr_bvalid; +wire [DDR_CH-1:0] m_axi_ddr_bready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr; +wire [DDR_CH*8-1:0] m_axi_ddr_arlen; +wire [DDR_CH*3-1:0] m_axi_ddr_arsize; +wire [DDR_CH*2-1:0] m_axi_ddr_arburst; +wire [DDR_CH-1:0] m_axi_ddr_arlock; +wire [DDR_CH*4-1:0] m_axi_ddr_arcache; +wire [DDR_CH*3-1:0] m_axi_ddr_arprot; +wire [DDR_CH*4-1:0] m_axi_ddr_arqos; +wire [DDR_CH-1:0] m_axi_ddr_arvalid; +wire [DDR_CH-1:0] m_axi_ddr_arready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata; +wire [DDR_CH*2-1:0] m_axi_ddr_rresp; +wire [DDR_CH-1:0] m_axi_ddr_rlast; +wire [DDR_CH-1:0] m_axi_ddr_rvalid; +wire [DDR_CH-1:0] m_axi_ddr_rready; + +wire [DDR_CH-1:0] ddr_status; + +generate + +if (DDR_ENABLE && DDR_CH > 0) begin + +ddr4_0 ddr4_c0_inst ( + .c0_sys_clk_p(clk_300mhz_0_p), + .c0_sys_clk_n(clk_300mhz_0_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[0 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c0_adr), + .c0_ddr4_ba(ddr4_c0_ba), + .c0_ddr4_cke(ddr4_c0_cke), + .c0_ddr4_cs_n(ddr4_c0_cs_n), + .c0_ddr4_dq(ddr4_c0_dq), + .c0_ddr4_dqs_t(ddr4_c0_dqs_t), + .c0_ddr4_dqs_c(ddr4_c0_dqs_c), + .c0_ddr4_odt(ddr4_c0_odt), + .c0_ddr4_parity(ddr4_c0_par), + .c0_ddr4_bg(ddr4_c0_bg), + .c0_ddr4_reset_n(ddr4_c0_reset_n), + .c0_ddr4_act_n(ddr4_c0_act_n), + .c0_ddr4_ck_t(ddr4_c0_ck_t), + .c0_ddr4_ck_c(ddr4_c0_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[0 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[0 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c0_adr = {17{1'bz}}; +assign ddr4_c0_ba = {2{1'bz}}; +assign ddr4_c0_bg = {2{1'bz}}; +assign ddr4_c0_cke = 1'bz; +assign ddr4_c0_cs_n = 1'bz; +assign ddr4_c0_act_n = 1'bz; +assign ddr4_c0_odt = 1'bz; +assign ddr4_c0_par = 1'bz; +assign ddr4_c0_reset_n = 1'b0; +assign ddr4_c0_dq = {72{1'bz}}; +assign ddr4_c0_dqs_t = {18{1'bz}}; +assign ddr4_c0_dqs_c = {18{1'bz}}; + +OBUFTDS ddr4_c0_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c0_ck_t), + .OB(ddr4_c0_ck_c) +); + +assign ddr_clk = 0; +assign ddr_rst = 0; + +assign m_axi_ddr_awready = 0; +assign m_axi_ddr_wready = 0; +assign m_axi_ddr_bid = 0; +assign m_axi_ddr_bresp = 0; +assign m_axi_ddr_bvalid = 0; +assign m_axi_ddr_arready = 0; +assign m_axi_ddr_rid = 0; +assign m_axi_ddr_rdata = 0; +assign m_axi_ddr_rresp = 0; +assign m_axi_ddr_rlast = 0; +assign m_axi_ddr_rvalid = 0; + +assign ddr_status = 0; + +end + +if (DDR_ENABLE && DDR_CH > 1) begin + +ddr4_0 ddr4_c1_inst ( + .c0_sys_clk_p(clk_300mhz_1_p), + .c0_sys_clk_n(clk_300mhz_1_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[1 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c1_adr), + .c0_ddr4_ba(ddr4_c1_ba), + .c0_ddr4_cke(ddr4_c1_cke), + .c0_ddr4_cs_n(ddr4_c1_cs_n), + .c0_ddr4_dq(ddr4_c1_dq), + .c0_ddr4_dqs_t(ddr4_c1_dqs_t), + .c0_ddr4_dqs_c(ddr4_c1_dqs_c), + .c0_ddr4_odt(ddr4_c1_odt), + .c0_ddr4_parity(ddr4_c1_par), + .c0_ddr4_bg(ddr4_c1_bg), + .c0_ddr4_reset_n(ddr4_c1_reset_n), + .c0_ddr4_act_n(ddr4_c1_act_n), + .c0_ddr4_ck_t(ddr4_c1_ck_t), + .c0_ddr4_ck_c(ddr4_c1_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[1 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[1 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[1 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[1*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[1*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[1*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[1 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[1*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[1*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[1*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[1 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[1 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[1*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[1 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[1 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[1 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[1 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[1*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[1 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[1*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[1*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[1*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[1 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[1*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[1*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[1*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[1 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[1 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[1 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[1 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[1 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[1*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c1_adr = {17{1'bz}}; +assign ddr4_c1_ba = {2{1'bz}}; +assign ddr4_c1_bg = {2{1'bz}}; +assign ddr4_c1_cke = 1'bz; +assign ddr4_c1_cs_n = 1'bz; +assign ddr4_c1_act_n = 1'bz; +assign ddr4_c1_odt = 1'bz; +assign ddr4_c1_par = 1'bz; +assign ddr4_c1_reset_n = 1'b0; +assign ddr4_c1_dq = {72{1'bz}}; +assign ddr4_c1_dqs_t = {18{1'bz}}; +assign ddr4_c1_dqs_c = {18{1'bz}}; + +OBUFTDS ddr4_c1_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c1_ck_t), + .OB(ddr4_c1_ck_c) +); + +end + +if (DDR_ENABLE && DDR_CH > 2) begin + +ddr4_0 ddr4_c2_inst ( + .c0_sys_clk_p(clk_300mhz_2_p), + .c0_sys_clk_n(clk_300mhz_2_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[2 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c2_adr), + .c0_ddr4_ba(ddr4_c2_ba), + .c0_ddr4_cke(ddr4_c2_cke), + .c0_ddr4_cs_n(ddr4_c2_cs_n), + .c0_ddr4_dq(ddr4_c2_dq), + .c0_ddr4_dqs_t(ddr4_c2_dqs_t), + .c0_ddr4_dqs_c(ddr4_c2_dqs_c), + .c0_ddr4_odt(ddr4_c2_odt), + .c0_ddr4_parity(ddr4_c2_par), + .c0_ddr4_bg(ddr4_c2_bg), + .c0_ddr4_reset_n(ddr4_c2_reset_n), + .c0_ddr4_act_n(ddr4_c2_act_n), + .c0_ddr4_ck_t(ddr4_c2_ck_t), + .c0_ddr4_ck_c(ddr4_c2_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[2 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[2 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[2 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[2*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[2*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[2*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[2 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[2*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[2*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[2*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[2 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[2 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[2*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[2 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[2 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[2 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[2 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[2*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[2 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[2*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[2*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[2*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[2 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[2*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[2*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[2*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[2 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[2 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[2 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[2 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[2 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[2*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c2_adr = {17{1'bz}}; +assign ddr4_c2_ba = {2{1'bz}}; +assign ddr4_c2_bg = {2{1'bz}}; +assign ddr4_c2_cke = 1'bz; +assign ddr4_c2_cs_n = 1'bz; +assign ddr4_c2_act_n = 1'bz; +assign ddr4_c2_odt = 1'bz; +assign ddr4_c2_par = 1'bz; +assign ddr4_c2_reset_n = 1'b0; +assign ddr4_c2_dq = {72{1'bz}}; +assign ddr4_c2_dqs_t = {18{1'bz}}; +assign ddr4_c2_dqs_c = {18{1'bz}}; + +OBUFTDS ddr4_c2_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c2_ck_t), + .OB(ddr4_c2_ck_c) +); + +end + +if (DDR_ENABLE && DDR_CH > 3) begin + +ddr4_0 ddr4_c3_inst ( + .c0_sys_clk_p(clk_300mhz_3_p), + .c0_sys_clk_n(clk_300mhz_3_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[3 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c3_adr), + .c0_ddr4_ba(ddr4_c3_ba), + .c0_ddr4_cke(ddr4_c3_cke), + .c0_ddr4_cs_n(ddr4_c3_cs_n), + .c0_ddr4_dq(ddr4_c3_dq), + .c0_ddr4_dqs_t(ddr4_c3_dqs_t), + .c0_ddr4_dqs_c(ddr4_c3_dqs_c), + .c0_ddr4_odt(ddr4_c3_odt), + .c0_ddr4_parity(ddr4_c3_par), + .c0_ddr4_bg(ddr4_c3_bg), + .c0_ddr4_reset_n(ddr4_c3_reset_n), + .c0_ddr4_act_n(ddr4_c3_act_n), + .c0_ddr4_ck_t(ddr4_c3_ck_t), + .c0_ddr4_ck_c(ddr4_c3_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[3 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[3 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[3 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[3*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[3*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[3*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[3 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[3*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[3*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[3*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[3 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[3 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[3*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[3 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[3 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[3 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[3 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[3*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[3 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[3*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[3*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[3*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[3 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[3*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[3*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[3*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[3 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[3 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[3 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[3 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[3 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[3*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c3_adr = {17{1'bz}}; +assign ddr4_c3_ba = {2{1'bz}}; +assign ddr4_c3_bg = {2{1'bz}}; +assign ddr4_c3_cke = 1'bz; +assign ddr4_c3_cs_n = 1'bz; +assign ddr4_c3_act_n = 1'bz; +assign ddr4_c3_odt = 1'bz; +assign ddr4_c3_par = 1'bz; +assign ddr4_c3_reset_n = 1'b0; +assign ddr4_c3_dq = {72{1'bz}}; +assign ddr4_c3_dqs_t = {18{1'bz}}; +assign ddr4_c3_dqs_c = {18{1'bz}}; + +OBUFTDS ddr4_c3_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c3_ck_t), + .OB(ddr4_c3_ck_c) +); + +end + +endgenerate + fpga_core #( // FW and board IDs .FPGA_ID(FPGA_ID), @@ -1963,6 +2563,16 @@ fpga_core #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -2200,6 +2810,52 @@ core_inst ( .qsfp1_intl(qsfp1_intl_int), .qsfp1_lpmode(qsfp1_lpmode), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + /* * QSPI flash */ diff --git a/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v index 2dc3c9af7..34831b2ce 100644 --- a/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v @@ -115,6 +115,16 @@ module fpga_core # parameter TX_RAM_SIZE = 131072, parameter RX_RAM_SIZE = 131072, + // RAM configuration + parameter DDR_CH = 4, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 34, + parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -364,6 +374,52 @@ module fpga_core # input wire qsfp1_intl, output wire qsfp1_lpmode, + /* + * DDR + */ + input wire [DDR_CH-1:0] ddr_clk, + input wire [DDR_CH-1:0] ddr_rst, + + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, + output wire [DDR_CH-1:0] m_axi_ddr_awlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, + output wire [DDR_CH-1:0] m_axi_ddr_awvalid, + input wire [DDR_CH-1:0] m_axi_ddr_awready, + output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, + output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, + output wire [DDR_CH-1:0] m_axi_ddr_wlast, + output wire [DDR_CH-1:0] m_axi_ddr_wvalid, + input wire [DDR_CH-1:0] m_axi_ddr_wready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, + input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, + input wire [DDR_CH-1:0] m_axi_ddr_bvalid, + output wire [DDR_CH-1:0] m_axi_ddr_bready, + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, + output wire [DDR_CH-1:0] m_axi_ddr_arlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, + output wire [DDR_CH-1:0] m_axi_ddr_arvalid, + input wire [DDR_CH-1:0] m_axi_ddr_arready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, + input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, + input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, + input wire [DDR_CH-1:0] m_axi_ddr_rlast, + input wire [DDR_CH-1:0] m_axi_ddr_rvalid, + output wire [DDR_CH-1:0] m_axi_ddr_rready, + + input wire [DDR_CH-1:0] ddr_status, + /* * QSPI flash */ @@ -903,6 +959,25 @@ mqnic_core_pcie_us #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .DDR_GROUP_SIZE(1), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_AWUSER_ENABLE(0), + .AXI_DDR_WUSER_ENABLE(0), + .AXI_DDR_BUSER_ENABLE(0), + .AXI_DDR_ARUSER_ENABLE(0), + .AXI_DDR_RUSER_ENABLE(0), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + .AXI_DDR_FIXED_BURST(0), + .AXI_DDR_WRAP_BURST(1), + .HBM_ENABLE(0), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1180,6 +1255,108 @@ core_inst ( .eth_rx_status(eth_rx_status), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awuser(), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wuser(), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_buser(0), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_aruser(), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_ruser(0), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + + /* + * HBM + */ + .hbm_clk(0), + .hbm_rst(0), + + .m_axi_hbm_awid(), + .m_axi_hbm_awaddr(), + .m_axi_hbm_awlen(), + .m_axi_hbm_awsize(), + .m_axi_hbm_awburst(), + .m_axi_hbm_awlock(), + .m_axi_hbm_awcache(), + .m_axi_hbm_awprot(), + .m_axi_hbm_awqos(), + .m_axi_hbm_awuser(), + .m_axi_hbm_awvalid(), + .m_axi_hbm_awready(0), + .m_axi_hbm_wdata(), + .m_axi_hbm_wstrb(), + .m_axi_hbm_wlast(), + .m_axi_hbm_wuser(), + .m_axi_hbm_wvalid(), + .m_axi_hbm_wready(0), + .m_axi_hbm_bid(0), + .m_axi_hbm_bresp(0), + .m_axi_hbm_buser(0), + .m_axi_hbm_bvalid(0), + .m_axi_hbm_bready(), + .m_axi_hbm_arid(), + .m_axi_hbm_araddr(), + .m_axi_hbm_arlen(), + .m_axi_hbm_arsize(), + .m_axi_hbm_arburst(), + .m_axi_hbm_arlock(), + .m_axi_hbm_arcache(), + .m_axi_hbm_arprot(), + .m_axi_hbm_arqos(), + .m_axi_hbm_aruser(), + .m_axi_hbm_arvalid(), + .m_axi_hbm_arready(0), + .m_axi_hbm_rid(0), + .m_axi_hbm_rdata(0), + .m_axi_hbm_rresp(0), + .m_axi_hbm_rlast(0), + .m_axi_hbm_ruser(0), + .m_axi_hbm_rvalid(0), + .m_axi_hbm_rready(), + + .hbm_status(0), + /* * Statistics input */ diff --git a/fpga/mqnic/AU250/fpga_25g/README.md b/fpga/mqnic/AU250/fpga_25g/README.md index 78bb2315b..dac806b2f 100644 --- a/fpga/mqnic/AU250/fpga_25g/README.md +++ b/fpga/mqnic/AU250/fpga_25g/README.md @@ -4,8 +4,9 @@ This design targets the Xilinx Alveo U250 FPGA board. -FPGA: xcu250-figd2104-2-e -PHY: 10G BASE-R PHY IP core and internal GTY transceiver +* FPGA: xcu250-figd2104-2-e +* PHY: 10G BASE-R PHY IP core and internal GTY transceiver +* RAM: 64 GB DDR4 2400 (4x 2G x72 DIMM) ## How to build diff --git a/fpga/mqnic/AU250/fpga_25g/fpga.xdc b/fpga/mqnic/AU250/fpga_25g/fpga.xdc index 7aab18b13..ac4d3ca3f 100644 --- a/fpga/mqnic/AU250/fpga_25g/fpga.xdc +++ b/fpga/mqnic/AU250/fpga_25g/fpga.xdc @@ -17,23 +17,23 @@ set_operating_conditions -design_power_budget 160 # System clocks # 300 MHz (DDR 0) -#set_property -dict {LOC AY37 IOSTANDARD LVDS} [get_ports clk_300mhz_0_p] -#set_property -dict {LOC AY38 IOSTANDARD LVDS} [get_ports clk_300mhz_0_n] +set_property -dict {LOC AY37 IOSTANDARD LVDS} [get_ports clk_300mhz_0_p] +set_property -dict {LOC AY38 IOSTANDARD LVDS} [get_ports clk_300mhz_0_n] #create_clock -period 3.333 -name clk_300mhz_0 [get_ports clk_300mhz_0_p] # 300 MHz (DDR 1) -#set_property -dict {LOC AW20 IOSTANDARD LVDS} [get_ports clk_300mhz_1_p] -#set_property -dict {LOC AW19 IOSTANDARD LVDS} [get_ports clk_300mhz_1_n] +set_property -dict {LOC AW20 IOSTANDARD LVDS} [get_ports clk_300mhz_1_p] +set_property -dict {LOC AW19 IOSTANDARD LVDS} [get_ports clk_300mhz_1_n] #create_clock -period 3.333 -name clk_300mhz_1 [get_ports clk_300mhz_1_p] # 300 MHz (DDR 2) -#set_property -dict {LOC F32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_p] -#set_property -dict {LOC E32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_n] +set_property -dict {LOC F32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_p] +set_property -dict {LOC E32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_n] #create_clock -period 3.333 -name clk_300mhz_2 [get_ports clk_300mhz_2_p] # 300 MHz (DDR 3) -#set_property -dict {LOC J16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_p] -#set_property -dict {LOC H16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_n] +set_property -dict {LOC J16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_p] +set_property -dict {LOC H16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_n] #create_clock -period 3.333 -name clk_300mhz_3 [get_ports clk_300mhz_3_p] # SI570 user clock @@ -257,3 +257,591 @@ create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_p] set_false_path -from [get_ports {pcie_reset_n}] set_input_delay 0 [get_ports {pcie_reset_n}] + +# DDR4 C0 +set_property -dict {LOC AT36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}] +set_property -dict {LOC AV36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}] +set_property -dict {LOC AV37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}] +set_property -dict {LOC AW35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}] +set_property -dict {LOC AW36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}] +set_property -dict {LOC AY36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}] +set_property -dict {LOC AY35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}] +set_property -dict {LOC BA40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}] +set_property -dict {LOC BA37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}] +set_property -dict {LOC BB37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}] +set_property -dict {LOC AR35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}] +set_property -dict {LOC BA39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}] +set_property -dict {LOC BB40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}] +set_property -dict {LOC AN36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}] +set_property -dict {LOC AP35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}] +set_property -dict {LOC AP36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}] +set_property -dict {LOC AR36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}] +set_property -dict {LOC AT35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}] +set_property -dict {LOC AT34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}] +set_property -dict {LOC BC37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}] +set_property -dict {LOC BC39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}] +set_property -dict {LOC AV38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t[0]}] +set_property -dict {LOC AW38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c[0]}] +#set_property -dict {LOC AU34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t[1]}] +#set_property -dict {LOC AU35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c[1]}] +set_property -dict {LOC BC38 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[0]}] +#set_property -dict {LOC BC40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[1]}] +set_property -dict {LOC AR33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[0]}] +#set_property -dict {LOC AP33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[1]}] +#set_property -dict {LOC AN33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[2]}] +#set_property -dict {LOC AM34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[3]}] +set_property -dict {LOC BB39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}] +set_property -dict {LOC AP34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[0]}] +#set_property -dict {LOC AN34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[1]}] +set_property -dict {LOC AU36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}] +set_property -dict {LOC AU31 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_reset_n}] + +set_property -dict {LOC AW28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}] +set_property -dict {LOC AW29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}] +set_property -dict {LOC BA28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}] +set_property -dict {LOC BA27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}] +set_property -dict {LOC BB29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}] +set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}] +set_property -dict {LOC BC27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}] +set_property -dict {LOC BB27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}] +set_property -dict {LOC BE28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}] +set_property -dict {LOC BF28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}] +set_property -dict {LOC BE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}] +set_property -dict {LOC BD30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}] +set_property -dict {LOC BF27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}] +set_property -dict {LOC BE27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}] +set_property -dict {LOC BF30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}] +set_property -dict {LOC BF29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}] +set_property -dict {LOC BB31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}] +set_property -dict {LOC BB32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}] +set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}] +set_property -dict {LOC AY33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}] +set_property -dict {LOC BC32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}] +set_property -dict {LOC BC33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}] +set_property -dict {LOC BB34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}] +set_property -dict {LOC BC34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}] +set_property -dict {LOC AV31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}] +set_property -dict {LOC AV32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}] +set_property -dict {LOC AV34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}] +set_property -dict {LOC AW34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}] +set_property -dict {LOC AW31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}] +set_property -dict {LOC AY31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}] +set_property -dict {LOC BA35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}] +set_property -dict {LOC BA34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}] +set_property -dict {LOC AL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}] +set_property -dict {LOC AM30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}] +set_property -dict {LOC AU32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}] +set_property -dict {LOC AT32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}] +set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}] +set_property -dict {LOC AN32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}] +set_property -dict {LOC AR32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}] +set_property -dict {LOC AR31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}] +set_property -dict {LOC AP29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}] +set_property -dict {LOC AP28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}] +set_property -dict {LOC AN27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}] +set_property -dict {LOC AM27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}] +set_property -dict {LOC AN29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}] +set_property -dict {LOC AM29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}] +set_property -dict {LOC AR27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}] +set_property -dict {LOC AR28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}] +set_property -dict {LOC AT28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}] +set_property -dict {LOC AV27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}] +set_property -dict {LOC AU27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}] +set_property -dict {LOC AT27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}] +set_property -dict {LOC AV29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}] +set_property -dict {LOC AY30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}] +set_property -dict {LOC AW30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}] +set_property -dict {LOC AV28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}] +set_property -dict {LOC BD34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}] +set_property -dict {LOC BD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}] +set_property -dict {LOC BE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}] +set_property -dict {LOC BD35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}] +set_property -dict {LOC BF32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}] +set_property -dict {LOC BF33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}] +set_property -dict {LOC BF34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}] +set_property -dict {LOC BF35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}] +set_property -dict {LOC BD40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}] +set_property -dict {LOC BD39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}] +set_property -dict {LOC BF43 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}] +set_property -dict {LOC BF42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}] +set_property -dict {LOC BF37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}] +set_property -dict {LOC BE37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}] +set_property -dict {LOC BE40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}] +set_property -dict {LOC BF41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}] +set_property -dict {LOC BA30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}] +set_property -dict {LOC BB30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}] +set_property -dict {LOC BB26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}] +set_property -dict {LOC BC26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}] +set_property -dict {LOC BD28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}] +set_property -dict {LOC BD29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}] +set_property -dict {LOC BD26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}] +set_property -dict {LOC BE26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}] +set_property -dict {LOC BB35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}] +set_property -dict {LOC BB36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}] +set_property -dict {LOC BC31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}] +set_property -dict {LOC BD31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}] +set_property -dict {LOC AV33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}] +set_property -dict {LOC AW33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}] +set_property -dict {LOC BA32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}] +set_property -dict {LOC BA33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}] +set_property -dict {LOC AM31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}] +set_property -dict {LOC AM32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}] +set_property -dict {LOC AP30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[9]}] +set_property -dict {LOC AP31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[9]}] +set_property -dict {LOC AL28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[10]}] +set_property -dict {LOC AL29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[10]}] +set_property -dict {LOC AR30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[11]}] +set_property -dict {LOC AT30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[11]}] +set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[12]}] +set_property -dict {LOC AU30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[12]}] +set_property -dict {LOC AY27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[13]}] +set_property -dict {LOC AY28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[13]}] +set_property -dict {LOC BE35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[14]}] +set_property -dict {LOC BE36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[14]}] +set_property -dict {LOC BE31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[15]}] +set_property -dict {LOC BE32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[15]}] +set_property -dict {LOC BE38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[16]}] +set_property -dict {LOC BF38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[16]}] +set_property -dict {LOC BF39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[17]}] +set_property -dict {LOC BF40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[17]}] + +# DDR4 C1 +set_property -dict {LOC AN24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}] +set_property -dict {LOC AT24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}] +set_property -dict {LOC AW24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}] +set_property -dict {LOC AN26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}] +set_property -dict {LOC AY22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}] +set_property -dict {LOC AY23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}] +set_property -dict {LOC AV24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}] +set_property -dict {LOC BA22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}] +set_property -dict {LOC AY25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}] +set_property -dict {LOC BA23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}] +set_property -dict {LOC AM26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}] +set_property -dict {LOC BA25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}] +set_property -dict {LOC BB22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}] +set_property -dict {LOC AL24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}] +set_property -dict {LOC AL25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}] +set_property -dict {LOC AM25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}] +set_property -dict {LOC AN23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}] +set_property -dict {LOC AU24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}] +set_property -dict {LOC AP26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}] +set_property -dict {LOC BC22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}] +set_property -dict {LOC AW26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}] +set_property -dict {LOC AT25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t[0]}] +set_property -dict {LOC AU25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c[0]}] +#set_property -dict {LOC AU26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t[1]}] +#set_property -dict {LOC AV26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c[1]}] +set_property -dict {LOC BB25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[0]}] +#set_property -dict {LOC BB24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[1]}] +set_property -dict {LOC AV23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[0]}] +#set_property -dict {LOC AP25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[1]}] +#set_property -dict {LOC AR23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[2]}] +#set_property -dict {LOC AP23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[3]}] +set_property -dict {LOC AW25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}] +set_property -dict {LOC AW23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[0]}] +#set_property -dict {LOC AP24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[1]}] +set_property -dict {LOC AT23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}] +set_property -dict {LOC AR17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}] + +set_property -dict {LOC BD9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] +set_property -dict {LOC BD7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] +set_property -dict {LOC BC7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] +set_property -dict {LOC BD8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] +set_property -dict {LOC BD10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] +set_property -dict {LOC BE10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] +set_property -dict {LOC BE7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] +set_property -dict {LOC BF7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] +set_property -dict {LOC AU13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] +set_property -dict {LOC AV13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] +set_property -dict {LOC AW13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] +set_property -dict {LOC AW14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] +set_property -dict {LOC AU14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] +set_property -dict {LOC AY11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] +set_property -dict {LOC AV14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] +set_property -dict {LOC BA11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] +set_property -dict {LOC BA12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] +set_property -dict {LOC BB12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] +set_property -dict {LOC BA13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] +set_property -dict {LOC BA14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] +set_property -dict {LOC BC9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] +set_property -dict {LOC BB9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] +set_property -dict {LOC BA7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] +set_property -dict {LOC BA8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] +set_property -dict {LOC AN13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] +set_property -dict {LOC AR13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] +set_property -dict {LOC AM13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] +set_property -dict {LOC AP13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] +set_property -dict {LOC AM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] +set_property -dict {LOC AR15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] +set_property -dict {LOC AL14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] +set_property -dict {LOC AT15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] +set_property -dict {LOC BE13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] +set_property -dict {LOC BD14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] +set_property -dict {LOC BF12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] +set_property -dict {LOC BD13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] +set_property -dict {LOC BD15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] +set_property -dict {LOC BD16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] +set_property -dict {LOC BF14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] +set_property -dict {LOC BF13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] +set_property -dict {LOC AY17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] +set_property -dict {LOC BA17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] +set_property -dict {LOC AY18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] +set_property -dict {LOC BA18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] +set_property -dict {LOC BA15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] +set_property -dict {LOC BB15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] +set_property -dict {LOC BC11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] +set_property -dict {LOC BD11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] +set_property -dict {LOC AV16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] +set_property -dict {LOC AV17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] +set_property -dict {LOC AU16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] +set_property -dict {LOC AU17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] +set_property -dict {LOC BB17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] +set_property -dict {LOC BB16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] +set_property -dict {LOC AT18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] +set_property -dict {LOC AT17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] +set_property -dict {LOC AM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] +set_property -dict {LOC AL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] +set_property -dict {LOC AN17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] +set_property -dict {LOC AN16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] +set_property -dict {LOC AR18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] +set_property -dict {LOC AP18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] +set_property -dict {LOC AL17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] +set_property -dict {LOC AL16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] +set_property -dict {LOC BF25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}] +set_property -dict {LOC BF24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}] +set_property -dict {LOC BD25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}] +set_property -dict {LOC BE25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}] +set_property -dict {LOC BD23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}] +set_property -dict {LOC BC23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}] +set_property -dict {LOC BF23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}] +set_property -dict {LOC BE23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}] +set_property -dict {LOC BF10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] +set_property -dict {LOC BF9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] +set_property -dict {LOC BE8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] +set_property -dict {LOC BF8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] +set_property -dict {LOC AW15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] +set_property -dict {LOC AY15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] +set_property -dict {LOC AY13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] +set_property -dict {LOC AY12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] +set_property -dict {LOC BB11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] +set_property -dict {LOC BB10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] +set_property -dict {LOC BA10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] +set_property -dict {LOC BA9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] +set_property -dict {LOC AT14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] +set_property -dict {LOC AT13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] +set_property -dict {LOC AN14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] +set_property -dict {LOC AP14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] +set_property -dict {LOC BE12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}] +set_property -dict {LOC BE11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}] +set_property -dict {LOC BE15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}] +set_property -dict {LOC BF15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}] +set_property -dict {LOC BC13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[10]}] +set_property -dict {LOC BC12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[10]}] +set_property -dict {LOC BB14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[11]}] +set_property -dict {LOC BC14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[11]}] +set_property -dict {LOC AV18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[12]}] +set_property -dict {LOC AW18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[12]}] +set_property -dict {LOC AW16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[13]}] +set_property -dict {LOC AY16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[13]}] +set_property -dict {LOC AP16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[14]}] +set_property -dict {LOC AR16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[14]}] +set_property -dict {LOC AM17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[15]}] +set_property -dict {LOC AM16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[15]}] +set_property -dict {LOC BC24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[16]}] +set_property -dict {LOC BD24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[16]}] +set_property -dict {LOC BE22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[17]}] +set_property -dict {LOC BF22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[17]}] + +# DDR4 C2 +set_property -dict {LOC L29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[0]}] +set_property -dict {LOC A33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[1]}] +set_property -dict {LOC C33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[2]}] +set_property -dict {LOC J29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[3]}] +set_property -dict {LOC H31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[4]}] +set_property -dict {LOC G31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[5]}] +set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[6]}] +set_property -dict {LOC B32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[7]}] +set_property -dict {LOC A32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[8]}] +set_property -dict {LOC D31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[9]}] +set_property -dict {LOC A34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[10]}] +set_property -dict {LOC E31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[11]}] +set_property -dict {LOC M30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[12]}] +set_property -dict {LOC F33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[13]}] +set_property -dict {LOC A35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[14]}] +set_property -dict {LOC G32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[15]}] +set_property -dict {LOC K30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[16]}] +set_property -dict {LOC D33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[0]}] +set_property -dict {LOC B36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[1]}] +set_property -dict {LOC C31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[0]}] +set_property -dict {LOC J30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[1]}] +set_property -dict {LOC C34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t[0]}] +set_property -dict {LOC B34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c[0]}] +#set_property -dict {LOC D34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t[1]}] +#set_property -dict {LOC D35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c[1]}] +set_property -dict {LOC G30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[0]}] +#set_property -dict {LOC E30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[1]}] +set_property -dict {LOC B35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[0]}] +#set_property -dict {LOC J31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[1]}] +#set_property -dict {LOC L30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[2]}] +#set_property -dict {LOC K31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[3]}] +set_property -dict {LOC B31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_act_n}] +set_property -dict {LOC E33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[0]}] +#set_property -dict {LOC F34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[1]}] +set_property -dict {LOC M29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_par}] +set_property -dict {LOC D36 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_reset_n}] + +set_property -dict {LOC R25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[0]}] +set_property -dict {LOC P25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[1]}] +set_property -dict {LOC M25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[2]}] +set_property -dict {LOC L25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[3]}] +set_property -dict {LOC P26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[4]}] +set_property -dict {LOC R26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[5]}] +set_property -dict {LOC N27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[6]}] +set_property -dict {LOC N28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[7]}] +set_property -dict {LOC J28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[8]}] +set_property -dict {LOC H29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[9]}] +set_property -dict {LOC H28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[10]}] +set_property -dict {LOC G29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[11]}] +set_property -dict {LOC K25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[12]}] +set_property -dict {LOC L27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[13]}] +set_property -dict {LOC K26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[14]}] +set_property -dict {LOC K27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[15]}] +set_property -dict {LOC F27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[16]}] +set_property -dict {LOC E27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[17]}] +set_property -dict {LOC E28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[18]}] +set_property -dict {LOC D28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[19]}] +set_property -dict {LOC G27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[20]}] +set_property -dict {LOC G26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[21]}] +set_property -dict {LOC F28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[22]}] +set_property -dict {LOC F29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[23]}] +set_property -dict {LOC D26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[24]}] +set_property -dict {LOC C26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[25]}] +set_property -dict {LOC B27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[26]}] +set_property -dict {LOC B26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[27]}] +set_property -dict {LOC A29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[28]}] +set_property -dict {LOC A30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[29]}] +set_property -dict {LOC C27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[30]}] +set_property -dict {LOC C28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[31]}] +set_property -dict {LOC F35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[32]}] +set_property -dict {LOC E38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[33]}] +set_property -dict {LOC D38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[34]}] +set_property -dict {LOC E35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[35]}] +set_property -dict {LOC E36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[36]}] +set_property -dict {LOC E37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[37]}] +set_property -dict {LOC F38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[38]}] +set_property -dict {LOC G38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[39]}] +set_property -dict {LOC P30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[40]}] +set_property -dict {LOC R30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[41]}] +set_property -dict {LOC P29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[42]}] +set_property -dict {LOC N29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[43]}] +set_property -dict {LOC L32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[44]}] +set_property -dict {LOC M32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[45]}] +set_property -dict {LOC P31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[46]}] +set_property -dict {LOC N32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[47]}] +set_property -dict {LOC J35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[48]}] +set_property -dict {LOC K35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[49]}] +set_property -dict {LOC L33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[50]}] +set_property -dict {LOC K33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[51]}] +set_property -dict {LOC J34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[52]}] +set_property -dict {LOC J33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[53]}] +set_property -dict {LOC N34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[54]}] +set_property -dict {LOC P34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[55]}] +set_property -dict {LOC H36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[56]}] +set_property -dict {LOC G36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[57]}] +set_property -dict {LOC H37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[58]}] +set_property -dict {LOC J36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[59]}] +set_property -dict {LOC K37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[60]}] +set_property -dict {LOC K38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[61]}] +set_property -dict {LOC G35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[62]}] +set_property -dict {LOC G34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[63]}] +set_property -dict {LOC C36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[64]}] +set_property -dict {LOC B37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[65]}] +set_property -dict {LOC A37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[66]}] +set_property -dict {LOC A38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[67]}] +set_property -dict {LOC C39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[68]}] +set_property -dict {LOC D39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[69]}] +set_property -dict {LOC A40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[70]}] +set_property -dict {LOC B40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[71]}] +set_property -dict {LOC N26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[0]}] +set_property -dict {LOC M26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[0]}] +set_property -dict {LOC R28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[1]}] +set_property -dict {LOC P28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[1]}] +set_property -dict {LOC J25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[2]}] +set_property -dict {LOC J26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[2]}] +set_property -dict {LOC M27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[3]}] +set_property -dict {LOC L28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[3]}] +set_property -dict {LOC D29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[4]}] +set_property -dict {LOC D30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[4]}] +set_property -dict {LOC H26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[5]}] +set_property -dict {LOC H27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[5]}] +set_property -dict {LOC A27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[6]}] +set_property -dict {LOC A28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[6]}] +set_property -dict {LOC C29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[7]}] +set_property -dict {LOC B29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[7]}] +set_property -dict {LOC E39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[8]}] +set_property -dict {LOC E40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[8]}] +set_property -dict {LOC G37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[9]}] +set_property -dict {LOC F37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[9]}] +set_property -dict {LOC N31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[10]}] +set_property -dict {LOC M31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[10]}] +set_property -dict {LOC T30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[11]}] +set_property -dict {LOC R31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[11]}] +set_property -dict {LOC L35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[12]}] +set_property -dict {LOC L36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[12]}] +set_property -dict {LOC M34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[13]}] +set_property -dict {LOC L34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[13]}] +set_property -dict {LOC J38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[14]}] +set_property -dict {LOC H38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[14]}] +set_property -dict {LOC H33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[15]}] +set_property -dict {LOC H34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[15]}] +set_property -dict {LOC B39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[16]}] +set_property -dict {LOC A39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[16]}] +set_property -dict {LOC C37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[17]}] +set_property -dict {LOC C38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[17]}] + +# DDR4 C3 +set_property -dict {LOC K15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[0]}] +set_property -dict {LOC B15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[1]}] +set_property -dict {LOC F14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[2]}] +set_property -dict {LOC A15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[3]}] +set_property -dict {LOC C14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[4]}] +set_property -dict {LOC A14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[5]}] +set_property -dict {LOC B14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[6]}] +set_property -dict {LOC E13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[7]}] +set_property -dict {LOC F13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[8]}] +set_property -dict {LOC A13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[9]}] +set_property -dict {LOC D14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[10]}] +set_property -dict {LOC C13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[11]}] +set_property -dict {LOC B13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[12]}] +set_property -dict {LOC K16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[13]}] +set_property -dict {LOC D15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[14]}] +set_property -dict {LOC E15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[15]}] +set_property -dict {LOC F15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[16]}] +set_property -dict {LOC J15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[0]}] +set_property -dict {LOC H14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[1]}] +set_property -dict {LOC D13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[0]}] +set_property -dict {LOC J13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[1]}] +set_property -dict {LOC L14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t[0]}] +set_property -dict {LOC L13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c[0]}] +#set_property -dict {LOC G14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t[1]}] +#set_property -dict {LOC G13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c[1]}] +set_property -dict {LOC K13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[0]}] +#set_property -dict {LOC L15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[1]}] +set_property -dict {LOC B16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[0]}] +#set_property -dict {LOC D16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[1]}] +#set_property -dict {LOC M14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[2]}] +#set_property -dict {LOC M13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[3]}] +set_property -dict {LOC H13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_act_n}] +set_property -dict {LOC C16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[0]}] +#set_property -dict {LOC E16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[1]}] +set_property -dict {LOC J14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_par}] +set_property -dict {LOC D21 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c3_reset_n}] + +set_property -dict {LOC P24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[0]}] +set_property -dict {LOC N24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[1]}] +set_property -dict {LOC T24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[2]}] +set_property -dict {LOC R23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[3]}] +set_property -dict {LOC N23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[4]}] +set_property -dict {LOC P21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[5]}] +set_property -dict {LOC P23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[6]}] +set_property -dict {LOC R21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[7]}] +set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[8]}] +set_property -dict {LOC J23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[9]}] +set_property -dict {LOC H24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[10]}] +set_property -dict {LOC G24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[11]}] +set_property -dict {LOC L24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[12]}] +set_property -dict {LOC L23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[13]}] +set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[14]}] +set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[15]}] +set_property -dict {LOC G20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[16]}] +set_property -dict {LOC H17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[17]}] +set_property -dict {LOC F19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[18]}] +set_property -dict {LOC G17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[19]}] +set_property -dict {LOC J20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[20]}] +set_property -dict {LOC L19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[21]}] +set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[22]}] +set_property -dict {LOC J19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[23]}] +set_property -dict {LOC M19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[24]}] +set_property -dict {LOC M20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[25]}] +set_property -dict {LOC R18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[26]}] +set_property -dict {LOC R17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[27]}] +set_property -dict {LOC R20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[28]}] +set_property -dict {LOC T20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[29]}] +set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[30]}] +set_property -dict {LOC N19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[31]}] +set_property -dict {LOC A23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[32]}] +set_property -dict {LOC A22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[33]}] +set_property -dict {LOC B24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[34]}] +set_property -dict {LOC B25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[35]}] +set_property -dict {LOC B22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[36]}] +set_property -dict {LOC C22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[37]}] +set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[38]}] +set_property -dict {LOC C23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[39]}] +set_property -dict {LOC C19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[40]}] +set_property -dict {LOC C18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[41]}] +set_property -dict {LOC C21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[42]}] +set_property -dict {LOC B21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[43]}] +set_property -dict {LOC A18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[44]}] +set_property -dict {LOC A17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[45]}] +set_property -dict {LOC A20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[46]}] +set_property -dict {LOC B20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[47]}] +set_property -dict {LOC E17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[48]}] +set_property -dict {LOC F20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[49]}] +set_property -dict {LOC E18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[50]}] +set_property -dict {LOC E20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[51]}] +set_property -dict {LOC D19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[52]}] +set_property -dict {LOC D20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[53]}] +set_property -dict {LOC H18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[54]}] +set_property -dict {LOC J18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[55]}] +set_property -dict {LOC F22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[56]}] +set_property -dict {LOC E22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[57]}] +set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[58]}] +set_property -dict {LOC G21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[59]}] +set_property -dict {LOC F24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[60]}] +set_property -dict {LOC E25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[61]}] +set_property -dict {LOC F25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[62]}] +set_property -dict {LOC G25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[63]}] +set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[64]}] +set_property -dict {LOC N16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[65]}] +set_property -dict {LOC N13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[66]}] +set_property -dict {LOC N14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[67]}] +set_property -dict {LOC T15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[68]}] +set_property -dict {LOC R15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[69]}] +set_property -dict {LOC P13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[70]}] +set_property -dict {LOC P14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[71]}] +set_property -dict {LOC T22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[0]}] +set_property -dict {LOC R22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[0]}] +set_property -dict {LOC N22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[1]}] +set_property -dict {LOC N21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[1]}] +set_property -dict {LOC J21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[2]}] +set_property -dict {LOC H21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[2]}] +set_property -dict {LOC M22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[3]}] +set_property -dict {LOC L22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[3]}] +set_property -dict {LOC L20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[4]}] +set_property -dict {LOC K20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[4]}] +set_property -dict {LOC K18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[5]}] +set_property -dict {LOC K17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[5]}] +set_property -dict {LOC P19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[6]}] +set_property -dict {LOC P18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[6]}] +set_property -dict {LOC N17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[7]}] +set_property -dict {LOC M17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[7]}] +set_property -dict {LOC A25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[8]}] +set_property -dict {LOC A24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[8]}] +set_property -dict {LOC D24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[9]}] +set_property -dict {LOC D23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[9]}] +set_property -dict {LOC C17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[10]}] +set_property -dict {LOC B17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[10]}] +set_property -dict {LOC B19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[11]}] +set_property -dict {LOC A19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[11]}] +set_property -dict {LOC F18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[12]}] +set_property -dict {LOC F17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[12]}] +set_property -dict {LOC H19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[13]}] +set_property -dict {LOC G19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[13]}] +set_property -dict {LOC F23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[14]}] +set_property -dict {LOC E23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[14]}] +set_property -dict {LOC H23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[15]}] +set_property -dict {LOC H22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[15]}] +set_property -dict {LOC R16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[16]}] +set_property -dict {LOC P15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[16]}] +set_property -dict {LOC T13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[17]}] +set_property -dict {LOC R13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[17]}] diff --git a/fpga/mqnic/AU250/fpga_25g/fpga/Makefile b/fpga/mqnic/AU250/fpga_25g/fpga/Makefile index 4365b3707..1cd444bb6 100644 --- a/fpga/mqnic/AU250/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/AU250/fpga_25g/fpga/Makefile @@ -145,6 +145,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl IP_TCL_FILES += ip/cms.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl index c3633f8b9..ec821353f 100644 --- a/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/AU250/fpga_25g/fpga/config.tcl @@ -148,6 +148,12 @@ dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" dict set params RX_RAM_SIZE "131072" + +# RAM configuration +dict set params DDR_CH "4" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" # Application block configuration dict set params APP_ID "32'h00000000" @@ -200,6 +206,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile index 4365b3707..1cd444bb6 100644 --- a/fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile @@ -145,6 +145,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl IP_TCL_FILES += ip/cms.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl index cdb1450bf..2365599ae 100644 --- a/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/AU250/fpga_25g/fpga_10g/config.tcl @@ -148,6 +148,12 @@ dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" dict set params RX_RAM_SIZE "32768" + +# RAM configuration +dict set params DDR_CH "4" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" # Application block configuration dict set params APP_ID "32'h00000000" @@ -200,6 +206,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/AU250/fpga_25g/ip/ddr4_0.tcl b/fpga/mqnic/AU250/fpga_25g/ip/ddr4_0.tcl new file mode 100644 index 000000000..27252f502 --- /dev/null +++ b/fpga/mqnic/AU250/fpga_25g/ip/ddr4_0.tcl @@ -0,0 +1,17 @@ + +create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 + +set_property -dict [list \ + CONFIG.C0.DDR4_AxiSelection {true} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_AxiIDWidth {8} \ + CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ + CONFIG.C0.DDR4_TimePeriod {833} \ + CONFIG.C0.DDR4_InputClockPeriod {3332} \ + CONFIG.C0.DDR4_MemoryType {RDIMMs} \ + CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PZ-2G3} \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_CasLatency {17} \ + CONFIG.C0.DDR4_CasWriteLatency {12} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} +] [get_ips ddr4_0] diff --git a/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v index 01c5f92bf..7b63e22ec 100644 --- a/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/AU250/fpga_25g/rtl/fpga.v @@ -112,6 +112,15 @@ module fpga # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // RAM configuration + parameter DDR_CH = 4, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 34, + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -177,6 +186,18 @@ module fpga # parameter STAT_ID_WIDTH = 12 ) ( + /* + * Clock and reset + */ + input wire clk_300mhz_0_p, + input wire clk_300mhz_0_n, + input wire clk_300mhz_1_p, + input wire clk_300mhz_1_n, + input wire clk_300mhz_2_p, + input wire clk_300mhz_2_n, + input wire clk_300mhz_3_p, + input wire clk_300mhz_3_n, + /* * GPIO */ @@ -260,7 +281,70 @@ module fpga # input wire qsfp1_intl, output wire qsfp1_lpmode, output wire qsfp1_refclk_reset, - output wire [1:0] qsfp1_fs + output wire [1:0] qsfp1_fs, + + /* + * DDR4 + */ + output wire [16:0] ddr4_c0_adr, + output wire [1:0] ddr4_c0_ba, + output wire [1:0] ddr4_c0_bg, + output wire [0:0] ddr4_c0_ck_t, + output wire [0:0] ddr4_c0_ck_c, + output wire [0:0] ddr4_c0_cke, + output wire [0:0] ddr4_c0_cs_n, + output wire ddr4_c0_act_n, + output wire [0:0] ddr4_c0_odt, + output wire ddr4_c0_par, + output wire ddr4_c0_reset_n, + inout wire [71:0] ddr4_c0_dq, + inout wire [17:0] ddr4_c0_dqs_t, + inout wire [17:0] ddr4_c0_dqs_c, + + output wire [16:0] ddr4_c1_adr, + output wire [1:0] ddr4_c1_ba, + output wire [1:0] ddr4_c1_bg, + output wire [0:0] ddr4_c1_ck_t, + output wire [0:0] ddr4_c1_ck_c, + output wire [0:0] ddr4_c1_cke, + output wire [0:0] ddr4_c1_cs_n, + output wire ddr4_c1_act_n, + output wire [0:0] ddr4_c1_odt, + output wire ddr4_c1_par, + output wire ddr4_c1_reset_n, + inout wire [71:0] ddr4_c1_dq, + inout wire [17:0] ddr4_c1_dqs_t, + inout wire [17:0] ddr4_c1_dqs_c, + + output wire [16:0] ddr4_c2_adr, + output wire [1:0] ddr4_c2_ba, + output wire [1:0] ddr4_c2_bg, + output wire [0:0] ddr4_c2_ck_t, + output wire [0:0] ddr4_c2_ck_c, + output wire [0:0] ddr4_c2_cke, + output wire [0:0] ddr4_c2_cs_n, + output wire ddr4_c2_act_n, + output wire [0:0] ddr4_c2_odt, + output wire ddr4_c2_par, + output wire ddr4_c2_reset_n, + inout wire [71:0] ddr4_c2_dq, + inout wire [17:0] ddr4_c2_dqs_t, + inout wire [17:0] ddr4_c2_dqs_c, + + output wire [16:0] ddr4_c3_adr, + output wire [1:0] ddr4_c3_ba, + output wire [1:0] ddr4_c3_bg, + output wire [0:0] ddr4_c3_ck_t, + output wire [0:0] ddr4_c3_ck_c, + output wire [0:0] ddr4_c3_cke, + output wire [0:0] ddr4_c3_cs_n, + output wire ddr4_c3_act_n, + output wire [0:0] ddr4_c3_odt, + output wire ddr4_c3_par, + output wire ddr4_c3_reset_n, + inout wire [71:0] ddr4_c3_dq, + inout wire [17:0] ddr4_c3_dqs_t, + inout wire [17:0] ddr4_c3_dqs_c ); // PTP configuration @@ -274,6 +358,9 @@ parameter IF_PTP_PERIOD_FNS = 16'h6666; // Interface configuration parameter TX_TAG_WIDTH = 16; +// RAM configuration +parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8); + // Ethernet interface configuration parameter XGMII_DATA_WIDTH = 64; parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8; @@ -1487,6 +1574,519 @@ assign ptp_clk = qsfp0_mgt_refclk_1_bufg; assign ptp_rst = qsfp0_rst; assign ptp_sample_clk = clk_125mhz_int; +// DDR4 +wire [DDR_CH-1:0] ddr_clk; +wire [DDR_CH-1:0] ddr_rst; + +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr; +wire [DDR_CH*8-1:0] m_axi_ddr_awlen; +wire [DDR_CH*3-1:0] m_axi_ddr_awsize; +wire [DDR_CH*2-1:0] m_axi_ddr_awburst; +wire [DDR_CH-1:0] m_axi_ddr_awlock; +wire [DDR_CH*4-1:0] m_axi_ddr_awcache; +wire [DDR_CH*3-1:0] m_axi_ddr_awprot; +wire [DDR_CH*4-1:0] m_axi_ddr_awqos; +wire [DDR_CH-1:0] m_axi_ddr_awvalid; +wire [DDR_CH-1:0] m_axi_ddr_awready; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata; +wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb; +wire [DDR_CH-1:0] m_axi_ddr_wlast; +wire [DDR_CH-1:0] m_axi_ddr_wvalid; +wire [DDR_CH-1:0] m_axi_ddr_wready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid; +wire [DDR_CH*2-1:0] m_axi_ddr_bresp; +wire [DDR_CH-1:0] m_axi_ddr_bvalid; +wire [DDR_CH-1:0] m_axi_ddr_bready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr; +wire [DDR_CH*8-1:0] m_axi_ddr_arlen; +wire [DDR_CH*3-1:0] m_axi_ddr_arsize; +wire [DDR_CH*2-1:0] m_axi_ddr_arburst; +wire [DDR_CH-1:0] m_axi_ddr_arlock; +wire [DDR_CH*4-1:0] m_axi_ddr_arcache; +wire [DDR_CH*3-1:0] m_axi_ddr_arprot; +wire [DDR_CH*4-1:0] m_axi_ddr_arqos; +wire [DDR_CH-1:0] m_axi_ddr_arvalid; +wire [DDR_CH-1:0] m_axi_ddr_arready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata; +wire [DDR_CH*2-1:0] m_axi_ddr_rresp; +wire [DDR_CH-1:0] m_axi_ddr_rlast; +wire [DDR_CH-1:0] m_axi_ddr_rvalid; +wire [DDR_CH-1:0] m_axi_ddr_rready; + +wire [DDR_CH-1:0] ddr_status; + +generate + +if (DDR_ENABLE && DDR_CH > 0) begin + +ddr4_0 ddr4_c0_inst ( + .c0_sys_clk_p(clk_300mhz_0_p), + .c0_sys_clk_n(clk_300mhz_0_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[0 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c0_adr), + .c0_ddr4_ba(ddr4_c0_ba), + .c0_ddr4_cke(ddr4_c0_cke), + .c0_ddr4_cs_n(ddr4_c0_cs_n), + .c0_ddr4_dq(ddr4_c0_dq), + .c0_ddr4_dqs_t(ddr4_c0_dqs_t), + .c0_ddr4_dqs_c(ddr4_c0_dqs_c), + .c0_ddr4_odt(ddr4_c0_odt), + .c0_ddr4_parity(ddr4_c0_par), + .c0_ddr4_bg(ddr4_c0_bg), + .c0_ddr4_reset_n(ddr4_c0_reset_n), + .c0_ddr4_act_n(ddr4_c0_act_n), + .c0_ddr4_ck_t(ddr4_c0_ck_t), + .c0_ddr4_ck_c(ddr4_c0_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[0 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[0 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c0_adr = {17{1'bz}}; +assign ddr4_c0_ba = {2{1'bz}}; +assign ddr4_c0_bg = {2{1'bz}}; +assign ddr4_c0_cke = 1'bz; +assign ddr4_c0_cs_n = 1'bz; +assign ddr4_c0_act_n = 1'bz; +assign ddr4_c0_odt = 1'bz; +assign ddr4_c0_par = 1'bz; +assign ddr4_c0_reset_n = 1'b0; +assign ddr4_c0_dq = {72{1'bz}}; +assign ddr4_c0_dqs_t = {18{1'bz}}; +assign ddr4_c0_dqs_c = {18{1'bz}}; + +OBUFTDS ddr4_c0_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c0_ck_t), + .OB(ddr4_c0_ck_c) +); + +assign ddr_clk = 0; +assign ddr_rst = 0; + +assign m_axi_ddr_awready = 0; +assign m_axi_ddr_wready = 0; +assign m_axi_ddr_bid = 0; +assign m_axi_ddr_bresp = 0; +assign m_axi_ddr_bvalid = 0; +assign m_axi_ddr_arready = 0; +assign m_axi_ddr_rid = 0; +assign m_axi_ddr_rdata = 0; +assign m_axi_ddr_rresp = 0; +assign m_axi_ddr_rlast = 0; +assign m_axi_ddr_rvalid = 0; + +assign ddr_status = 0; + +end + +if (DDR_ENABLE && DDR_CH > 1) begin + +ddr4_0 ddr4_c1_inst ( + .c0_sys_clk_p(clk_300mhz_1_p), + .c0_sys_clk_n(clk_300mhz_1_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[1 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c1_adr), + .c0_ddr4_ba(ddr4_c1_ba), + .c0_ddr4_cke(ddr4_c1_cke), + .c0_ddr4_cs_n(ddr4_c1_cs_n), + .c0_ddr4_dq(ddr4_c1_dq), + .c0_ddr4_dqs_t(ddr4_c1_dqs_t), + .c0_ddr4_dqs_c(ddr4_c1_dqs_c), + .c0_ddr4_odt(ddr4_c1_odt), + .c0_ddr4_parity(ddr4_c1_par), + .c0_ddr4_bg(ddr4_c1_bg), + .c0_ddr4_reset_n(ddr4_c1_reset_n), + .c0_ddr4_act_n(ddr4_c1_act_n), + .c0_ddr4_ck_t(ddr4_c1_ck_t), + .c0_ddr4_ck_c(ddr4_c1_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[1 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[1 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[1 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[1*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[1*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[1*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[1 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[1*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[1*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[1*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[1 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[1 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[1*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[1 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[1 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[1 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[1 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[1*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[1 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[1*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[1*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[1*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[1 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[1*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[1*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[1*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[1 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[1 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[1 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[1 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[1 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[1*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c1_adr = {17{1'bz}}; +assign ddr4_c1_ba = {2{1'bz}}; +assign ddr4_c1_bg = {2{1'bz}}; +assign ddr4_c1_cke = 1'bz; +assign ddr4_c1_cs_n = 1'bz; +assign ddr4_c1_act_n = 1'bz; +assign ddr4_c1_odt = 1'bz; +assign ddr4_c1_par = 1'bz; +assign ddr4_c1_reset_n = 1'b0; +assign ddr4_c1_dq = {72{1'bz}}; +assign ddr4_c1_dqs_t = {18{1'bz}}; +assign ddr4_c1_dqs_c = {18{1'bz}}; + +OBUFTDS ddr4_c1_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c1_ck_t), + .OB(ddr4_c1_ck_c) +); + +end + +if (DDR_ENABLE && DDR_CH > 2) begin + +ddr4_0 ddr4_c2_inst ( + .c0_sys_clk_p(clk_300mhz_2_p), + .c0_sys_clk_n(clk_300mhz_2_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[2 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c2_adr), + .c0_ddr4_ba(ddr4_c2_ba), + .c0_ddr4_cke(ddr4_c2_cke), + .c0_ddr4_cs_n(ddr4_c2_cs_n), + .c0_ddr4_dq(ddr4_c2_dq), + .c0_ddr4_dqs_t(ddr4_c2_dqs_t), + .c0_ddr4_dqs_c(ddr4_c2_dqs_c), + .c0_ddr4_odt(ddr4_c2_odt), + .c0_ddr4_parity(ddr4_c2_par), + .c0_ddr4_bg(ddr4_c2_bg), + .c0_ddr4_reset_n(ddr4_c2_reset_n), + .c0_ddr4_act_n(ddr4_c2_act_n), + .c0_ddr4_ck_t(ddr4_c2_ck_t), + .c0_ddr4_ck_c(ddr4_c2_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[2 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[2 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[2 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[2*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[2*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[2*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[2 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[2*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[2*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[2*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[2 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[2 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[2*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[2 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[2 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[2 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[2 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[2*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[2 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[2*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[2*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[2*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[2 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[2*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[2*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[2*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[2 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[2 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[2 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[2 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[2 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[2*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c2_adr = {17{1'bz}}; +assign ddr4_c2_ba = {2{1'bz}}; +assign ddr4_c2_bg = {2{1'bz}}; +assign ddr4_c2_cke = 1'bz; +assign ddr4_c2_cs_n = 1'bz; +assign ddr4_c2_act_n = 1'bz; +assign ddr4_c2_odt = 1'bz; +assign ddr4_c2_par = 1'bz; +assign ddr4_c2_reset_n = 1'b0; +assign ddr4_c2_dq = {72{1'bz}}; +assign ddr4_c2_dqs_t = {18{1'bz}}; +assign ddr4_c2_dqs_c = {18{1'bz}}; + +OBUFTDS ddr4_c2_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c2_ck_t), + .OB(ddr4_c2_ck_c) +); + +end + +if (DDR_ENABLE && DDR_CH > 3) begin + +ddr4_0 ddr4_c3_inst ( + .c0_sys_clk_p(clk_300mhz_3_p), + .c0_sys_clk_n(clk_300mhz_3_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[3 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c3_adr), + .c0_ddr4_ba(ddr4_c3_ba), + .c0_ddr4_cke(ddr4_c3_cke), + .c0_ddr4_cs_n(ddr4_c3_cs_n), + .c0_ddr4_dq(ddr4_c3_dq), + .c0_ddr4_dqs_t(ddr4_c3_dqs_t), + .c0_ddr4_dqs_c(ddr4_c3_dqs_c), + .c0_ddr4_odt(ddr4_c3_odt), + .c0_ddr4_parity(ddr4_c3_par), + .c0_ddr4_bg(ddr4_c3_bg), + .c0_ddr4_reset_n(ddr4_c3_reset_n), + .c0_ddr4_act_n(ddr4_c3_act_n), + .c0_ddr4_ck_t(ddr4_c3_ck_t), + .c0_ddr4_ck_c(ddr4_c3_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[3 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[3 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[3 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[3*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[3*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[3*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[3 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[3*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[3*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[3*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[3 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[3 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[3*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[3 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[3 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[3 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[3 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[3*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[3 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[3*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[3*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[3*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[3 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[3*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[3*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[3*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[3 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[3 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[3 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[3 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[3 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[3*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c3_adr = {17{1'bz}}; +assign ddr4_c3_ba = {2{1'bz}}; +assign ddr4_c3_bg = {2{1'bz}}; +assign ddr4_c3_cke = 1'bz; +assign ddr4_c3_cs_n = 1'bz; +assign ddr4_c3_act_n = 1'bz; +assign ddr4_c3_odt = 1'bz; +assign ddr4_c3_par = 1'bz; +assign ddr4_c3_reset_n = 1'b0; +assign ddr4_c3_dq = {72{1'bz}}; +assign ddr4_c3_dqs_t = {18{1'bz}}; +assign ddr4_c3_dqs_c = {18{1'bz}}; + +OBUFTDS ddr4_c3_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c3_ck_t), + .OB(ddr4_c3_ck_c) +); + +end + +endgenerate + fpga_core #( // FW and board IDs .FPGA_ID(FPGA_ID), @@ -1563,6 +2163,16 @@ fpga_core #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1868,6 +2478,52 @@ core_inst ( .qsfp1_intl(qsfp1_intl_int), .qsfp1_lpmode(qsfp1_lpmode), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + /* * QSPI flash */ diff --git a/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v index 57c7eebd6..ee697be04 100644 --- a/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v @@ -122,6 +122,16 @@ module fpga_core # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // RAM configuration + parameter DDR_CH = 4, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 34, + parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -429,6 +439,52 @@ module fpga_core # input wire qsfp1_intl, output wire qsfp1_lpmode, + /* + * DDR + */ + input wire [DDR_CH-1:0] ddr_clk, + input wire [DDR_CH-1:0] ddr_rst, + + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, + output wire [DDR_CH-1:0] m_axi_ddr_awlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, + output wire [DDR_CH-1:0] m_axi_ddr_awvalid, + input wire [DDR_CH-1:0] m_axi_ddr_awready, + output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, + output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, + output wire [DDR_CH-1:0] m_axi_ddr_wlast, + output wire [DDR_CH-1:0] m_axi_ddr_wvalid, + input wire [DDR_CH-1:0] m_axi_ddr_wready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, + input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, + input wire [DDR_CH-1:0] m_axi_ddr_bvalid, + output wire [DDR_CH-1:0] m_axi_ddr_bready, + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, + output wire [DDR_CH-1:0] m_axi_ddr_arlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, + output wire [DDR_CH-1:0] m_axi_ddr_arvalid, + input wire [DDR_CH-1:0] m_axi_ddr_arready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, + input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, + input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, + input wire [DDR_CH-1:0] m_axi_ddr_rlast, + input wire [DDR_CH-1:0] m_axi_ddr_rvalid, + output wire [DDR_CH-1:0] m_axi_ddr_rready, + + input wire [DDR_CH-1:0] ddr_status, + /* * QSPI flash */ @@ -1170,6 +1226,25 @@ mqnic_core_pcie_us #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .DDR_GROUP_SIZE(1), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_AWUSER_ENABLE(0), + .AXI_DDR_WUSER_ENABLE(0), + .AXI_DDR_BUSER_ENABLE(0), + .AXI_DDR_ARUSER_ENABLE(0), + .AXI_DDR_RUSER_ENABLE(0), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + .AXI_DDR_FIXED_BURST(0), + .AXI_DDR_WRAP_BURST(1), + .HBM_ENABLE(0), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1447,6 +1522,108 @@ core_inst ( .eth_rx_status(eth_rx_status), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awuser(), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wuser(), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_buser(0), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_aruser(), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_ruser(0), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + + /* + * HBM + */ + .hbm_clk(0), + .hbm_rst(0), + + .m_axi_hbm_awid(), + .m_axi_hbm_awaddr(), + .m_axi_hbm_awlen(), + .m_axi_hbm_awsize(), + .m_axi_hbm_awburst(), + .m_axi_hbm_awlock(), + .m_axi_hbm_awcache(), + .m_axi_hbm_awprot(), + .m_axi_hbm_awqos(), + .m_axi_hbm_awuser(), + .m_axi_hbm_awvalid(), + .m_axi_hbm_awready(0), + .m_axi_hbm_wdata(), + .m_axi_hbm_wstrb(), + .m_axi_hbm_wlast(), + .m_axi_hbm_wuser(), + .m_axi_hbm_wvalid(), + .m_axi_hbm_wready(0), + .m_axi_hbm_bid(0), + .m_axi_hbm_bresp(0), + .m_axi_hbm_buser(0), + .m_axi_hbm_bvalid(0), + .m_axi_hbm_bready(), + .m_axi_hbm_arid(), + .m_axi_hbm_araddr(), + .m_axi_hbm_arlen(), + .m_axi_hbm_arsize(), + .m_axi_hbm_arburst(), + .m_axi_hbm_arlock(), + .m_axi_hbm_arcache(), + .m_axi_hbm_arprot(), + .m_axi_hbm_arqos(), + .m_axi_hbm_aruser(), + .m_axi_hbm_arvalid(), + .m_axi_hbm_arready(0), + .m_axi_hbm_rid(0), + .m_axi_hbm_rdata(0), + .m_axi_hbm_rresp(0), + .m_axi_hbm_rlast(0), + .m_axi_hbm_ruser(0), + .m_axi_hbm_rvalid(0), + .m_axi_hbm_rready(), + + .hbm_status(0), + /* * Statistics input */ diff --git a/fpga/mqnic/AU280/fpga_100g/README.md b/fpga/mqnic/AU280/fpga_100g/README.md index 8154d21d6..6f4d1d0ea 100644 --- a/fpga/mqnic/AU280/fpga_100g/README.md +++ b/fpga/mqnic/AU280/fpga_100g/README.md @@ -7,6 +7,8 @@ This design targets the Xilinx Alveo U280 FPGA board. * FPGA: xcu280-fsvh2892-2L-e * MAC: Xilinx 100G CMAC * PHY: 100G CAUI-4 CMAC and internal GTY transceivers +* RAM: 32 GB DDR4 2400 (2x 2G x72 DIMM) +* HBM: 8GB HBM2 ## How to build diff --git a/fpga/mqnic/AU280/fpga_100g/fpga.xdc b/fpga/mqnic/AU280/fpga_100g/fpga.xdc index 39d2a829f..d89586559 100644 --- a/fpga/mqnic/AU280/fpga_100g/fpga.xdc +++ b/fpga/mqnic/AU280/fpga_100g/fpga.xdc @@ -18,14 +18,14 @@ set_operating_conditions -design_power_budget 160 # System clocks # 100 MHz (DDR4) -#set_property -dict {LOC BJ43 IOSTANDARD LVDS} [get_ports clk_100mhz_0_p] -#set_property -dict {LOC BJ44 IOSTANDARD LVDS} [get_ports clk_100mhz_0_n] -#create_clock -period 10 -name clk_100mhz_0 [get_ports clk_100mhz_0_p] +set_property -dict {LOC BJ43 IOSTANDARD LVDS} [get_ports clk_100mhz_0_p] +set_property -dict {LOC BJ44 IOSTANDARD LVDS} [get_ports clk_100mhz_0_n] +create_clock -period 10 -name clk_100mhz_0 [get_ports clk_100mhz_0_p] # 100 MHz (DDR4) -#set_property -dict {LOC BH6 IOSTANDARD LVDS} [get_ports clk_100mhz_1_p] -#set_property -dict {LOC BJ6 IOSTANDARD LVDS} [get_ports clk_100mhz_1_n] -#create_clock -period 10 -name clk_100mhz_1 [get_ports clk_100mhz_1_p] +set_property -dict {LOC BH6 IOSTANDARD LVDS} [get_ports clk_100mhz_1_p] +set_property -dict {LOC BJ6 IOSTANDARD LVDS} [get_ports clk_100mhz_1_n] +create_clock -period 10 -name clk_100mhz_1 [get_ports clk_100mhz_1_p] # 100 MHz #set_property -dict {LOC G31 IOSTANDARD LVDS} [get_ports clk_100mhz_2_p] @@ -225,3 +225,283 @@ create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_1_p] set_false_path -from [get_ports {pcie_reset_n}] set_input_delay 0 [get_ports {pcie_reset_n}] + +# DDR4 C0 +set_property -dict {LOC BF46 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}] +set_property -dict {LOC BG43 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}] +set_property -dict {LOC BK45 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}] +set_property -dict {LOC BF42 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}] +set_property -dict {LOC BL45 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}] +set_property -dict {LOC BF43 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}] +set_property -dict {LOC BG42 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}] +set_property -dict {LOC BL43 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}] +set_property -dict {LOC BK43 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}] +set_property -dict {LOC BM42 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}] +set_property -dict {LOC BG45 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}] +set_property -dict {LOC BD41 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}] +set_property -dict {LOC BL42 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}] +set_property -dict {LOC BE44 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}] +set_property -dict {LOC BE43 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}] +set_property -dict {LOC BL46 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}] +set_property -dict {LOC BH44 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}] +set_property -dict {LOC BH45 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}] +set_property -dict {LOC BM47 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}] +set_property -dict {LOC BF41 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}] +set_property -dict {LOC BE41 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}] +set_property -dict {LOC BH46 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c0_ck_t}] +set_property -dict {LOC BJ46 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c0_ck_c}] +set_property -dict {LOC BH42 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke}] +set_property -dict {LOC BK46 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n}] +set_property -dict {LOC BH41 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}] +set_property -dict {LOC BG44 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt}] +set_property -dict {LOC BF45 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}] +set_property -dict {LOC BG33 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_c0_reset_n}] + +set_property -dict {LOC BN32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}] +set_property -dict {LOC BP32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}] +set_property -dict {LOC BL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}] +set_property -dict {LOC BM30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}] +set_property -dict {LOC BP29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}] +set_property -dict {LOC BP28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}] +set_property -dict {LOC BP31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}] +set_property -dict {LOC BN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}] +set_property -dict {LOC BJ31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}] +set_property -dict {LOC BH31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}] +set_property -dict {LOC BF32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}] +set_property -dict {LOC BF33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}] +set_property -dict {LOC BH29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}] +set_property -dict {LOC BH30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}] +set_property -dict {LOC BF31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}] +set_property -dict {LOC BG32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}] +set_property -dict {LOC BK31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}] +set_property -dict {LOC BL31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}] +set_property -dict {LOC BK33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}] +set_property -dict {LOC BL33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}] +set_property -dict {LOC BL32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}] +set_property -dict {LOC BM33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}] +set_property -dict {LOC BN34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}] +set_property -dict {LOC BP34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}] +set_property -dict {LOC BH34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}] +set_property -dict {LOC BH35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}] +set_property -dict {LOC BF35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}] +set_property -dict {LOC BF36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}] +set_property -dict {LOC BJ33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}] +set_property -dict {LOC BJ34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}] +set_property -dict {LOC BG34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}] +set_property -dict {LOC BG35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}] +set_property -dict {LOC BM52 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}] +set_property -dict {LOC BL53 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}] +set_property -dict {LOC BL52 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}] +set_property -dict {LOC BL51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}] +set_property -dict {LOC BN50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}] +set_property -dict {LOC BN51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}] +set_property -dict {LOC BN49 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}] +set_property -dict {LOC BM48 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}] +set_property -dict {LOC BE50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}] +set_property -dict {LOC BE49 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}] +set_property -dict {LOC BE51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}] +set_property -dict {LOC BD51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}] +set_property -dict {LOC BF52 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}] +set_property -dict {LOC BF51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}] +set_property -dict {LOC BG50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}] +set_property -dict {LOC BF50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}] +set_property -dict {LOC BH50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}] +set_property -dict {LOC BJ51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}] +set_property -dict {LOC BH51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}] +set_property -dict {LOC BH49 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}] +set_property -dict {LOC BK50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}] +set_property -dict {LOC BK51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}] +set_property -dict {LOC BJ49 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}] +set_property -dict {LOC BJ48 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}] +set_property -dict {LOC BN44 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}] +set_property -dict {LOC BN45 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}] +set_property -dict {LOC BM44 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}] +set_property -dict {LOC BM45 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}] +set_property -dict {LOC BP43 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}] +set_property -dict {LOC BP44 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}] +set_property -dict {LOC BN47 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}] +set_property -dict {LOC BP47 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}] +set_property -dict {LOC BG54 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}] +set_property -dict {LOC BG53 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}] +set_property -dict {LOC BE53 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}] +set_property -dict {LOC BE54 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}] +set_property -dict {LOC BH52 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}] +set_property -dict {LOC BG52 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}] +set_property -dict {LOC BK54 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}] +set_property -dict {LOC BK53 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}] +set_property -dict {LOC BN29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}] +set_property -dict {LOC BN30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}] +set_property -dict {LOC BM28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}] +set_property -dict {LOC BM29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}] +set_property -dict {LOC BJ29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}] +set_property -dict {LOC BK30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}] +set_property -dict {LOC BG29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}] +set_property -dict {LOC BG30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}] +set_property -dict {LOC BL35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}] +set_property -dict {LOC BM35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}] +set_property -dict {LOC BM34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}] +set_property -dict {LOC BN35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}] +set_property -dict {LOC BK34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}] +set_property -dict {LOC BK35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}] +set_property -dict {LOC BH32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}] +set_property -dict {LOC BJ32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}] +set_property -dict {LOC BM49 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}] +set_property -dict {LOC BM50 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}] +set_property -dict {LOC BP48 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[9]}] +set_property -dict {LOC BP49 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[9]}] +set_property -dict {LOC BF47 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[10]}] +set_property -dict {LOC BF48 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[10]}] +set_property -dict {LOC BG48 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[11]}] +set_property -dict {LOC BG49 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[11]}] +set_property -dict {LOC BH47 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[12]}] +set_property -dict {LOC BJ47 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[12]}] +set_property -dict {LOC BK48 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[13]}] +set_property -dict {LOC BK49 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[13]}] +set_property -dict {LOC BN46 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[14]}] +set_property -dict {LOC BP46 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[14]}] +set_property -dict {LOC BN42 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[15]}] +set_property -dict {LOC BP42 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[15]}] +set_property -dict {LOC BH54 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[16]}] +set_property -dict {LOC BJ54 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[16]}] +set_property -dict {LOC BJ52 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[17]}] +set_property -dict {LOC BJ53 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[17]}] + +# DDR4 C1 +set_property -dict {LOC BF7 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}] +set_property -dict {LOC BK1 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}] +set_property -dict {LOC BF6 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}] +set_property -dict {LOC BF5 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}] +set_property -dict {LOC BE3 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}] +set_property -dict {LOC BE6 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}] +set_property -dict {LOC BE5 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}] +set_property -dict {LOC BG7 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}] +set_property -dict {LOC BJ1 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}] +set_property -dict {LOC BG2 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}] +set_property -dict {LOC BJ8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}] +set_property -dict {LOC BE4 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}] +set_property -dict {LOC BL2 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}] +set_property -dict {LOC BK5 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}] +set_property -dict {LOC BK8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}] +set_property -dict {LOC BJ4 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}] +set_property -dict {LOC BF8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}] +set_property -dict {LOC BG8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}] +set_property -dict {LOC BK4 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}] +set_property -dict {LOC BF3 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}] +set_property -dict {LOC BF2 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}] +set_property -dict {LOC BJ3 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c1_ck_t}] +set_property -dict {LOC BJ2 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c1_ck_c}] +set_property -dict {LOC BE1 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke}] +set_property -dict {LOC BL3 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n}] +set_property -dict {LOC BG3 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}] +set_property -dict {LOC BH2 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt}] +set_property -dict {LOC BH1 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}] +set_property -dict {LOC BH12 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_c1_reset_n}] + +set_property -dict {LOC A11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] +set_property -dict {LOC A10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] +set_property -dict {LOC A9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] +set_property -dict {LOC A8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] +set_property -dict {LOC B12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] +set_property -dict {LOC B10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] +set_property -dict {LOC C12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] +set_property -dict {LOC B11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] +set_property -dict {LOC E11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] +set_property -dict {LOC D11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] +set_property -dict {LOC E12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] +set_property -dict {LOC F11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] +set_property -dict {LOC F10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] +set_property -dict {LOC E9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] +set_property -dict {LOC F9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] +set_property -dict {LOC G11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] +set_property -dict {LOC H12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] +set_property -dict {LOC G13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] +set_property -dict {LOC H13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] +set_property -dict {LOC H14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] +set_property -dict {LOC J11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] +set_property -dict {LOC J12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] +set_property -dict {LOC J15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] +set_property -dict {LOC J14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] +set_property -dict {LOC A14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] +set_property -dict {LOC C15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] +set_property -dict {LOC A15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] +set_property -dict {LOC B15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] +set_property -dict {LOC F15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] +set_property -dict {LOC E14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] +set_property -dict {LOC F14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] +set_property -dict {LOC F13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] +set_property -dict {LOC BM3 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] +set_property -dict {LOC BM4 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] +set_property -dict {LOC BM5 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] +set_property -dict {LOC BL6 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] +set_property -dict {LOC BN4 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] +set_property -dict {LOC BN5 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] +set_property -dict {LOC BN6 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] +set_property -dict {LOC BN7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] +set_property -dict {LOC BJ9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] +set_property -dict {LOC BK9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] +set_property -dict {LOC BK10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] +set_property -dict {LOC BL10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] +set_property -dict {LOC BM9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] +set_property -dict {LOC BN9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] +set_property -dict {LOC BN10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] +set_property -dict {LOC BM10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] +set_property -dict {LOC BM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] +set_property -dict {LOC BM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] +set_property -dict {LOC BL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] +set_property -dict {LOC BM13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] +set_property -dict {LOC BN12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] +set_property -dict {LOC BM12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] +set_property -dict {LOC BP13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] +set_property -dict {LOC BP14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] +set_property -dict {LOC BJ13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] +set_property -dict {LOC BJ12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] +set_property -dict {LOC BH15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] +set_property -dict {LOC BH14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] +set_property -dict {LOC BK14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] +set_property -dict {LOC BK15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] +set_property -dict {LOC BL12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] +set_property -dict {LOC BL13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] +set_property -dict {LOC BE9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}] +set_property -dict {LOC BE10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}] +set_property -dict {LOC BF10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}] +set_property -dict {LOC BE11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}] +set_property -dict {LOC BG13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}] +set_property -dict {LOC BG12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}] +set_property -dict {LOC BG9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}] +set_property -dict {LOC BG10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}] +set_property -dict {LOC B13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] +set_property -dict {LOC A13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] +set_property -dict {LOC C10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] +set_property -dict {LOC C9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] +set_property -dict {LOC D10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] +set_property -dict {LOC D9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] +set_property -dict {LOC H10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] +set_property -dict {LOC G10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] +set_property -dict {LOC H15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] +set_property -dict {LOC G15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] +set_property -dict {LOC K14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] +set_property -dict {LOC K13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] +set_property -dict {LOC D15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] +set_property -dict {LOC D14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] +set_property -dict {LOC E13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] +set_property -dict {LOC D12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] +set_property -dict {LOC BL7 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}] +set_property -dict {LOC BM7 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}] +set_property -dict {LOC BP7 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}] +set_property -dict {LOC BP6 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}] +set_property -dict {LOC BL8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[10]}] +set_property -dict {LOC BM8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[10]}] +set_property -dict {LOC BP9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[11]}] +set_property -dict {LOC BP8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[11]}] +set_property -dict {LOC BN15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[12]}] +set_property -dict {LOC BN14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[12]}] +set_property -dict {LOC BP12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[13]}] +set_property -dict {LOC BP11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[13]}] +set_property -dict {LOC BJ14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[14]}] +set_property -dict {LOC BK13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[14]}] +set_property -dict {LOC BJ11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[15]}] +set_property -dict {LOC BK11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[15]}] +set_property -dict {LOC BF12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[16]}] +set_property -dict {LOC BF11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[16]}] +set_property -dict {LOC BH10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[17]}] +set_property -dict {LOC BH9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[17]}] diff --git a/fpga/mqnic/AU280/fpga_100g/fpga/Makefile b/fpga/mqnic/AU280/fpga_100g/fpga/Makefile index fedb334f5..a361c50b5 100644 --- a/fpga/mqnic/AU280/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/AU280/fpga_100g/fpga/Makefile @@ -117,12 +117,15 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += hbm.xdc # IP IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl IP_TCL_FILES += ip/cmac_usplus_0.tcl IP_TCL_FILES += ip/cmac_usplus_1.tcl IP_TCL_FILES += ip/cms.tcl +IP_TCL_FILES += ip/hbm_0.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl index 913ee7e3b..813e19316 100644 --- a/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/AU280/fpga_100g/fpga/config.tcl @@ -136,6 +136,17 @@ dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "131072" dict set params RX_RAM_SIZE "131072" + +# RAM configuration +dict set params DDR_CH "2" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" +dict set params HBM_CH "32" +dict set params HBM_ENABLE "1" +dict set params HBM_GROUP_SIZE "32" +dict set params AXI_HBM_ADDR_WIDTH "33" +dict set params AXI_HBM_MAX_BURST_LEN "256" # Application block configuration dict set params APP_ID "32'h00000000" @@ -187,6 +198,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie4c_uscale_plus_0] diff --git a/fpga/mqnic/AU280/fpga_100g/hbm.xdc b/fpga/mqnic/AU280/fpga_100g/hbm.xdc new file mode 100644 index 000000000..aa147b0a5 --- /dev/null +++ b/fpga/mqnic/AU280/fpga_100g/hbm.xdc @@ -0,0 +1,2 @@ +# force debug hub to use HBM APB clock to prevent CDC issues +connect_debug_port dbg_hub/clk [get_nets */APB_0_PCLK] diff --git a/fpga/mqnic/AU280/fpga_100g/ip/ddr4_0.tcl b/fpga/mqnic/AU280/fpga_100g/ip/ddr4_0.tcl new file mode 100644 index 000000000..12bd7aee2 --- /dev/null +++ b/fpga/mqnic/AU280/fpga_100g/ip/ddr4_0.tcl @@ -0,0 +1,18 @@ + +create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 + +set_property -dict [list \ + CONFIG.System_Clock {No_Buffer} \ + CONFIG.C0.DDR4_AxiSelection {true} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_AxiIDWidth {8} \ + CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ + CONFIG.C0.DDR4_TimePeriod {833} \ + CONFIG.C0.DDR4_InputClockPeriod {9996} \ + CONFIG.C0.DDR4_MemoryType {RDIMMs} \ + CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PZ-2G3} \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_CasLatency {17} \ + CONFIG.C0.DDR4_CasWriteLatency {12} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} +] [get_ips ddr4_0] diff --git a/fpga/mqnic/AU280/fpga_100g/ip/hbm_0.tcl b/fpga/mqnic/AU280/fpga_100g/ip/hbm_0.tcl new file mode 100644 index 000000000..a8cbc2874 --- /dev/null +++ b/fpga/mqnic/AU280/fpga_100g/ip/hbm_0.tcl @@ -0,0 +1,23 @@ + +create_ip -name hbm -vendor xilinx.com -library ip -module_name hbm_0 + +set_property -dict [list \ + CONFIG.USER_HBM_DENSITY {8GB} \ + CONFIG.USER_HBM_STACK {2} \ + CONFIG.USER_MC0_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC1_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC2_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC3_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC4_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC5_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC6_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC7_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC8_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC9_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC10_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC11_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC12_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC13_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC14_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC15_ENABLE_ECC_CORRECTION {true} +] [get_ips hbm_0] diff --git a/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v index e56a11831..5f26ff790 100644 --- a/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/AU280/fpga_100g/rtl/fpga.v @@ -109,6 +109,20 @@ module fpga # parameter TX_RAM_SIZE = 131072, parameter RX_RAM_SIZE = 131072, + // RAM configuration + parameter DDR_CH = 2, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 34, + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + parameter HBM_CH = 32, + parameter HBM_ENABLE = 1, + parameter HBM_GROUP_SIZE = 32, + parameter AXI_HBM_ADDR_WIDTH = 33, + parameter AXI_HBM_MAX_BURST_LEN = 256, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -173,6 +187,16 @@ module fpga # parameter STAT_ID_WIDTH = 12 ) ( + /* + * Clock and reset + */ + input wire clk_100mhz_0_p, + input wire clk_100mhz_0_n, + input wire clk_100mhz_1_p, + input wire clk_100mhz_1_n, + input wire clk_100mhz_2_p, + input wire clk_100mhz_2_n, + /* * GPIO */ @@ -239,7 +263,40 @@ module fpga # input wire qsfp1_mgt_refclk_1_p, input wire qsfp1_mgt_refclk_1_n, output wire qsfp1_refclk_oe_b, - output wire qsfp1_refclk_fs + output wire qsfp1_refclk_fs, + + /* + * DDR4 + */ + output wire [16:0] ddr4_c0_adr, + output wire [1:0] ddr4_c0_ba, + output wire [1:0] ddr4_c0_bg, + output wire ddr4_c0_ck_t, + output wire ddr4_c0_ck_c, + output wire ddr4_c0_cke, + output wire ddr4_c0_cs_n, + output wire ddr4_c0_act_n, + output wire ddr4_c0_odt, + output wire ddr4_c0_par, + output wire ddr4_c0_reset_n, + inout wire [71:0] ddr4_c0_dq, + inout wire [17:0] ddr4_c0_dqs_t, + inout wire [17:0] ddr4_c0_dqs_c, + + output wire [16:0] ddr4_c1_adr, + output wire [1:0] ddr4_c1_ba, + output wire [1:0] ddr4_c1_bg, + output wire ddr4_c1_ck_t, + output wire ddr4_c1_ck_c, + output wire ddr4_c1_cke, + output wire ddr4_c1_cs_n, + output wire ddr4_c1_act_n, + output wire ddr4_c1_odt, + output wire ddr4_c1_par, + output wire ddr4_c1_reset_n, + inout wire [71:0] ddr4_c1_dq, + inout wire [17:0] ddr4_c1_dqs_t, + inout wire [17:0] ddr4_c1_dqs_c ); // PTP configuration @@ -252,6 +309,12 @@ parameter PTP_SEPARATE_RX_CLOCK = 1; // Interface configuration parameter TX_TAG_WIDTH = 16; +// RAM configuration +parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8); +parameter AXI_HBM_DATA_WIDTH = 256; +parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8); +parameter AXI_HBM_ID_WIDTH = 6; + // Ethernet interface configuration parameter AXIS_ETH_DATA_WIDTH = 512; parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; @@ -369,9 +432,6 @@ sync_reset_125mhz_inst ( .out(rst_125mhz_int) ); -// GPIO -assign hbm_cattrip = 1'b0; - // Flash wire qspi_clk_int; wire [3:0] qspi_dq_int; @@ -581,6 +641,9 @@ wire [1:0] axil_cms_rresp_int; wire axil_cms_rvalid_int; wire axil_cms_rready_int; +wire [7:0] hbm_temp_1; +wire [7:0] hbm_temp_2; + axil_cdc #( .DATA_WIDTH(32), .ADDR_WIDTH(18) @@ -634,8 +697,8 @@ cms_wrapper cms_inst ( .aclk_ctrl_0(clk_50mhz_int), .aresetn_ctrl_0(~rst_50mhz_int), - .hbm_temp_1_0(7'd0), - .hbm_temp_2_0(7'd0), + .hbm_temp_1_0(hbm_temp_1), + .hbm_temp_2_0(hbm_temp_2), .interrupt_hbm_cattrip_0(hbm_cattrip), .interrupt_host_0(), .s_axi_ctrl_0_araddr(axil_cms_araddr_int), @@ -1786,6 +1849,1655 @@ sync_reset_ptp_rst_inst ( .out(ptp_rst) ); +// DDR4 +wire [DDR_CH-1:0] ddr_clk; +wire [DDR_CH-1:0] ddr_rst; + +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr; +wire [DDR_CH*8-1:0] m_axi_ddr_awlen; +wire [DDR_CH*3-1:0] m_axi_ddr_awsize; +wire [DDR_CH*2-1:0] m_axi_ddr_awburst; +wire [DDR_CH-1:0] m_axi_ddr_awlock; +wire [DDR_CH*4-1:0] m_axi_ddr_awcache; +wire [DDR_CH*3-1:0] m_axi_ddr_awprot; +wire [DDR_CH*4-1:0] m_axi_ddr_awqos; +wire [DDR_CH-1:0] m_axi_ddr_awvalid; +wire [DDR_CH-1:0] m_axi_ddr_awready; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata; +wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb; +wire [DDR_CH-1:0] m_axi_ddr_wlast; +wire [DDR_CH-1:0] m_axi_ddr_wvalid; +wire [DDR_CH-1:0] m_axi_ddr_wready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid; +wire [DDR_CH*2-1:0] m_axi_ddr_bresp; +wire [DDR_CH-1:0] m_axi_ddr_bvalid; +wire [DDR_CH-1:0] m_axi_ddr_bready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr; +wire [DDR_CH*8-1:0] m_axi_ddr_arlen; +wire [DDR_CH*3-1:0] m_axi_ddr_arsize; +wire [DDR_CH*2-1:0] m_axi_ddr_arburst; +wire [DDR_CH-1:0] m_axi_ddr_arlock; +wire [DDR_CH*4-1:0] m_axi_ddr_arcache; +wire [DDR_CH*3-1:0] m_axi_ddr_arprot; +wire [DDR_CH*4-1:0] m_axi_ddr_arqos; +wire [DDR_CH-1:0] m_axi_ddr_arvalid; +wire [DDR_CH-1:0] m_axi_ddr_arready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata; +wire [DDR_CH*2-1:0] m_axi_ddr_rresp; +wire [DDR_CH-1:0] m_axi_ddr_rlast; +wire [DDR_CH-1:0] m_axi_ddr_rvalid; +wire [DDR_CH-1:0] m_axi_ddr_rready; + +wire [DDR_CH-1:0] ddr_status; + +generate + +wire clk_100mhz_0_ibufg; + +IBUFGDS #( + .DIFF_TERM("FALSE"), + .IBUF_LOW_PWR("FALSE") +) +clk_100mhz_0_ibufg_inst ( + .O (clk_100mhz_0_ibufg), + .I (clk_100mhz_0_p), + .IB (clk_100mhz_0_n) +); + +if (DDR_ENABLE && DDR_CH > 0) begin + +ddr4_0 ddr4_c0_inst ( + .c0_sys_clk_i(clk_100mhz_0_ibufg), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[0 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c0_adr), + .c0_ddr4_ba(ddr4_c0_ba), + .c0_ddr4_cke(ddr4_c0_cke), + .c0_ddr4_cs_n(ddr4_c0_cs_n), + .c0_ddr4_dq(ddr4_c0_dq), + .c0_ddr4_dqs_t(ddr4_c0_dqs_t), + .c0_ddr4_dqs_c(ddr4_c0_dqs_c), + .c0_ddr4_odt(ddr4_c0_odt), + .c0_ddr4_parity(ddr4_c0_par), + .c0_ddr4_bg(ddr4_c0_bg), + .c0_ddr4_reset_n(ddr4_c0_reset_n), + .c0_ddr4_act_n(ddr4_c0_act_n), + .c0_ddr4_ck_t(ddr4_c0_ck_t), + .c0_ddr4_ck_c(ddr4_c0_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[0 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[0 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c0_adr = {17{1'bz}}; +assign ddr4_c0_ba = {2{1'bz}}; +assign ddr4_c0_bg = {2{1'bz}}; +assign ddr4_c0_cke = 1'bz; +assign ddr4_c0_cs_n = 1'bz; +assign ddr4_c0_act_n = 1'bz; +assign ddr4_c0_odt = 1'bz; +assign ddr4_c0_par = 1'bz; +assign ddr4_c0_reset_n = 1'b0; +assign ddr4_c0_dq = {72{1'bz}}; +assign ddr4_c0_dqs_t = {18{1'bz}}; +assign ddr4_c0_dqs_c = {18{1'bz}}; + +OBUFTDS ddr4_c0_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c0_ck_t), + .OB(ddr4_c0_ck_c) +); + +assign ddr_clk = 0; +assign ddr_rst = 0; + +assign m_axi_ddr_awready = 0; +assign m_axi_ddr_wready = 0; +assign m_axi_ddr_bid = 0; +assign m_axi_ddr_bresp = 0; +assign m_axi_ddr_bvalid = 0; +assign m_axi_ddr_arready = 0; +assign m_axi_ddr_rid = 0; +assign m_axi_ddr_rdata = 0; +assign m_axi_ddr_rresp = 0; +assign m_axi_ddr_rlast = 0; +assign m_axi_ddr_rvalid = 0; + +assign ddr_status = 0; + +end + +wire clk_100mhz_1_ibufg; + +IBUFGDS #( + .DIFF_TERM("FALSE"), + .IBUF_LOW_PWR("FALSE") +) +clk_100mhz_1_ibufg_inst ( + .O (clk_100mhz_1_ibufg), + .I (clk_100mhz_1_p), + .IB (clk_100mhz_1_n) +); + +if (DDR_ENABLE && DDR_CH > 1) begin + +ddr4_0 ddr4_c1_inst ( + .c0_sys_clk_i(clk_100mhz_1_ibufg), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[1 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c1_adr), + .c0_ddr4_ba(ddr4_c1_ba), + .c0_ddr4_cke(ddr4_c1_cke), + .c0_ddr4_cs_n(ddr4_c1_cs_n), + .c0_ddr4_dq(ddr4_c1_dq), + .c0_ddr4_dqs_t(ddr4_c1_dqs_t), + .c0_ddr4_dqs_c(ddr4_c1_dqs_c), + .c0_ddr4_odt(ddr4_c1_odt), + .c0_ddr4_parity(ddr4_c1_par), + .c0_ddr4_bg(ddr4_c1_bg), + .c0_ddr4_reset_n(ddr4_c1_reset_n), + .c0_ddr4_act_n(ddr4_c1_act_n), + .c0_ddr4_ck_t(ddr4_c1_ck_t), + .c0_ddr4_ck_c(ddr4_c1_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[1 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[1 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[1 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[1*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[1*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[1*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[1 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[1*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[1*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[1*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[1 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[1 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[1*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[1 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[1 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[1 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[1 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[1*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[1 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[1*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[1*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[1*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[1 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[1*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[1*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[1*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[1 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[1 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[1 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[1 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[1 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[1*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c1_adr = {17{1'bz}}; +assign ddr4_c1_ba = {2{1'bz}}; +assign ddr4_c1_bg = {2{1'bz}}; +assign ddr4_c1_cke = 1'bz; +assign ddr4_c1_cs_n = 1'bz; +assign ddr4_c1_act_n = 1'bz; +assign ddr4_c1_odt = 1'bz; +assign ddr4_c1_par = 1'bz; +assign ddr4_c1_reset_n = 1'b0; +assign ddr4_c1_dq = {72{1'bz}}; +assign ddr4_c1_dqs_t = {18{1'bz}}; +assign ddr4_c1_dqs_c = {18{1'bz}}; + +OBUFTDS ddr4_c1_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c1_ck_t), + .OB(ddr4_c1_ck_c) +); + +end + +endgenerate + +// HBM +wire [HBM_CH-1:0] hbm_clk; +wire [HBM_CH-1:0] hbm_rst; + +wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_awid; +wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_awaddr; +wire [HBM_CH*8-1:0] m_axi_hbm_awlen; +wire [HBM_CH*3-1:0] m_axi_hbm_awsize; +wire [HBM_CH*2-1:0] m_axi_hbm_awburst; +wire [HBM_CH-1:0] m_axi_hbm_awlock; +wire [HBM_CH*4-1:0] m_axi_hbm_awcache; +wire [HBM_CH*3-1:0] m_axi_hbm_awprot; +wire [HBM_CH*4-1:0] m_axi_hbm_awqos; +wire [HBM_CH-1:0] m_axi_hbm_awvalid; +wire [HBM_CH-1:0] m_axi_hbm_awready; +wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_wdata; +wire [HBM_CH*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_wstrb; +wire [HBM_CH-1:0] m_axi_hbm_wlast; +wire [HBM_CH-1:0] m_axi_hbm_wvalid; +wire [HBM_CH-1:0] m_axi_hbm_wready; +wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_bid; +wire [HBM_CH*2-1:0] m_axi_hbm_bresp; +wire [HBM_CH-1:0] m_axi_hbm_bvalid; +wire [HBM_CH-1:0] m_axi_hbm_bready; +wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_arid; +wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_araddr; +wire [HBM_CH*8-1:0] m_axi_hbm_arlen; +wire [HBM_CH*3-1:0] m_axi_hbm_arsize; +wire [HBM_CH*2-1:0] m_axi_hbm_arburst; +wire [HBM_CH-1:0] m_axi_hbm_arlock; +wire [HBM_CH*4-1:0] m_axi_hbm_arcache; +wire [HBM_CH*3-1:0] m_axi_hbm_arprot; +wire [HBM_CH*4-1:0] m_axi_hbm_arqos; +wire [HBM_CH-1:0] m_axi_hbm_arvalid; +wire [HBM_CH-1:0] m_axi_hbm_arready; +wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_rid; +wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_rdata; +wire [HBM_CH*2-1:0] m_axi_hbm_rresp; +wire [HBM_CH-1:0] m_axi_hbm_rlast; +wire [HBM_CH-1:0] m_axi_hbm_rvalid; +wire [HBM_CH-1:0] m_axi_hbm_rready; + +wire [HBM_CH-1:0] hbm_status; + +generate + +if (HBM_ENABLE) begin + +wire hbm_ref_clk; + +wire hbm_mmcm_rst; +wire hbm_mmcm_locked; +wire hbm_mmcm_clkfb; + +wire hbm_axi_clk_mmcm; +wire hbm_axi_clk; +wire hbm_axi_rst_int; +wire hbm_axi_rst; + +BUFG +hbm_ref_clk_bufg_inst ( + .I(clk_100mhz_0_ibufg), + .O(hbm_ref_clk) +); + +// HBM MMCM instance +// 100 MHz in, 450 MHz out +// PFD range: 10 MHz to 500 MHz +// VCO range: 800 MHz to 1600 MHz +// M = 9, D = 1 sets Fvco = 900 MHz +// Divide by 2 to get output frequency of 450 MHz +MMCME4_BASE #( + .BANDWIDTH("OPTIMIZED"), + .CLKOUT0_DIVIDE_F(2), + .CLKOUT0_DUTY_CYCLE(0.5), + .CLKOUT0_PHASE(0), + .CLKOUT1_DIVIDE(1), + .CLKOUT1_DUTY_CYCLE(0.5), + .CLKOUT1_PHASE(0), + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.5), + .CLKOUT2_PHASE(0), + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.5), + .CLKOUT3_PHASE(0), + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.5), + .CLKOUT4_PHASE(0), + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.5), + .CLKOUT5_PHASE(0), + .CLKOUT6_DIVIDE(1), + .CLKOUT6_DUTY_CYCLE(0.5), + .CLKOUT6_PHASE(0), + .CLKFBOUT_MULT_F(9), + .CLKFBOUT_PHASE(0), + .DIVCLK_DIVIDE(1), + .REF_JITTER1(0.010), + .CLKIN1_PERIOD(10.000), + .STARTUP_WAIT("FALSE"), + .CLKOUT4_CASCADE("FALSE") +) +hbm_mmcm_inst ( + .CLKIN1(clk_100mhz_0_ibufg), + .CLKFBIN(hbm_mmcm_clkfb), + .RST(hbm_mmcm_rst), + .PWRDWN(1'b0), + .CLKOUT0(hbm_axi_clk_mmcm), + .CLKOUT0B(), + .CLKOUT1(), + .CLKOUT1B(), + .CLKOUT2(), + .CLKOUT2B(), + .CLKOUT3(), + .CLKOUT3B(), + .CLKOUT4(), + .CLKOUT5(), + .CLKOUT6(), + .CLKFBOUT(hbm_mmcm_clkfb), + .CLKFBOUTB(), + .LOCKED(hbm_mmcm_locked) +); + +BUFG +hbm_axi_clk_bufg_inst ( + .I(hbm_axi_clk_mmcm), + .O(hbm_axi_clk) +); + +sync_reset #( + .N(4) +) +sync_reset_hbm_axi_inst ( + .clk(hbm_axi_clk), + .rst(~hbm_mmcm_locked), + .out(hbm_axi_rst_int) +); + +// extra register for hbm_axi_rst signal +(* shreg_extract = "no" *) +reg hbm_axi_rst_reg_1 = 1'b1; +(* shreg_extract = "no" *) +reg hbm_axi_rst_reg_2 = 1'b1; + +assign hbm_axi_rst = hbm_axi_rst_reg_2; + +always @(posedge hbm_axi_clk) begin + hbm_axi_rst_reg_1 <= hbm_axi_rst_int; + hbm_axi_rst_reg_2 <= hbm_axi_rst_reg_1; +end + +wire hbm_cattrip_1; +wire hbm_cattrip_2; + +assign hbm_cattrip = hbm_cattrip_1 | hbm_cattrip_2; + +assign hbm_clk = {HBM_CH{hbm_axi_clk}}; +assign hbm_rst = {HBM_CH{hbm_axi_rst}}; + +hbm_0 hbm_inst ( + .HBM_REF_CLK_0(hbm_ref_clk), + .HBM_REF_CLK_1(hbm_ref_clk), + + .APB_0_PWDATA(32'd0), + .APB_0_PADDR(22'd0), + .APB_0_PCLK(hbm_ref_clk), + .APB_0_PENABLE(1'b0), + .APB_0_PRESET_N(1'b1), + .APB_0_PSEL(1'b0), + .APB_0_PWRITE(1'b0), + .APB_0_PRDATA(), + .APB_0_PREADY(), + .APB_0_PSLVERR(), + .apb_complete_0(), + + .APB_1_PWDATA(32'd0), + .APB_1_PADDR(22'd0), + .APB_1_PCLK(hbm_ref_clk), + .APB_1_PENABLE(1'b0), + .APB_1_PRESET_N(1'b1), + .APB_1_PSEL(1'b0), + .APB_1_PWRITE(1'b0), + .APB_1_PRDATA(), + .APB_1_PREADY(), + .APB_1_PSLVERR(), + .apb_complete_1(), + + .AXI_00_ACLK(hbm_clk[0 +: 1]), + .AXI_00_ARESET_N(!hbm_rst[0 +: 1]), + + .AXI_00_ARADDR(m_axi_hbm_araddr[0*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_00_ARBURST(m_axi_hbm_arburst[0*2 +: 2]), + .AXI_00_ARID(m_axi_hbm_arid[0*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_00_ARLEN(m_axi_hbm_arlen[0*8 +: 8]), + .AXI_00_ARSIZE(m_axi_hbm_arsize[0*3 +: 3]), + .AXI_00_ARVALID(m_axi_hbm_arvalid[0 +: 1]), + .AXI_00_ARREADY(m_axi_hbm_arready[0 +: 1]), + .AXI_00_RDATA_PARITY(), + .AXI_00_RDATA(m_axi_hbm_rdata[0*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_00_RID(m_axi_hbm_rid[0 +: 1]), + .AXI_00_RLAST(m_axi_hbm_rlast[0 +: 1]), + .AXI_00_RRESP(m_axi_hbm_rresp[0*2 +: 2]), + .AXI_00_RVALID(m_axi_hbm_rvalid[0 +: 1]), + .AXI_00_RREADY(m_axi_hbm_rready[0 +: 1]), + .AXI_00_AWADDR(m_axi_hbm_awaddr[0*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_00_AWBURST(m_axi_hbm_awburst[0*2 +: 2]), + .AXI_00_AWID(m_axi_hbm_awid[0*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_00_AWLEN(m_axi_hbm_awlen[0*8 +: 8]), + .AXI_00_AWSIZE(m_axi_hbm_awsize[0*3 +: 3]), + .AXI_00_AWVALID(m_axi_hbm_awvalid[0 +: 1]), + .AXI_00_AWREADY(m_axi_hbm_awready[0 +: 1]), + .AXI_00_WDATA(m_axi_hbm_wdata[0*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_00_WLAST(m_axi_hbm_wlast[0 +: 1]), + .AXI_00_WSTRB(m_axi_hbm_wstrb[0*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_00_WDATA_PARITY(32'd0), + .AXI_00_WVALID(m_axi_hbm_wvalid[0 +: 1]), + .AXI_00_WREADY(m_axi_hbm_wready[0 +: 1]), + .AXI_00_BID(m_axi_hbm_bid[0*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_00_BRESP(m_axi_hbm_bresp[0*2 +: 2]), + .AXI_00_BVALID(m_axi_hbm_bvalid[0 +: 1]), + .AXI_00_BREADY(m_axi_hbm_bready[0 +: 1]), + + .AXI_01_ACLK(hbm_clk[1 +: 1]), + .AXI_01_ARESET_N(!hbm_rst[1 +: 1]), + + .AXI_01_ARADDR(m_axi_hbm_araddr[1*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_01_ARBURST(m_axi_hbm_arburst[1*2 +: 2]), + .AXI_01_ARID(m_axi_hbm_arid[1*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_01_ARLEN(m_axi_hbm_arlen[1*8 +: 8]), + .AXI_01_ARSIZE(m_axi_hbm_arsize[1*3 +: 3]), + .AXI_01_ARVALID(m_axi_hbm_arvalid[1 +: 1]), + .AXI_01_ARREADY(m_axi_hbm_arready[1 +: 1]), + .AXI_01_RDATA_PARITY(), + .AXI_01_RDATA(m_axi_hbm_rdata[1*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_01_RID(m_axi_hbm_rid[1 +: 1]), + .AXI_01_RLAST(m_axi_hbm_rlast[1 +: 1]), + .AXI_01_RRESP(m_axi_hbm_rresp[1*2 +: 2]), + .AXI_01_RVALID(m_axi_hbm_rvalid[1 +: 1]), + .AXI_01_RREADY(m_axi_hbm_rready[1 +: 1]), + .AXI_01_AWADDR(m_axi_hbm_awaddr[1*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_01_AWBURST(m_axi_hbm_awburst[1*2 +: 2]), + .AXI_01_AWID(m_axi_hbm_awid[1*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_01_AWLEN(m_axi_hbm_awlen[1*8 +: 8]), + .AXI_01_AWSIZE(m_axi_hbm_awsize[1*3 +: 3]), + .AXI_01_AWVALID(m_axi_hbm_awvalid[1 +: 1]), + .AXI_01_AWREADY(m_axi_hbm_awready[1 +: 1]), + .AXI_01_WDATA(m_axi_hbm_wdata[1*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_01_WLAST(m_axi_hbm_wlast[1 +: 1]), + .AXI_01_WSTRB(m_axi_hbm_wstrb[1*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_01_WDATA_PARITY(32'd0), + .AXI_01_WVALID(m_axi_hbm_wvalid[1 +: 1]), + .AXI_01_WREADY(m_axi_hbm_wready[1 +: 1]), + .AXI_01_BID(m_axi_hbm_bid[1*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_01_BRESP(m_axi_hbm_bresp[1*2 +: 2]), + .AXI_01_BVALID(m_axi_hbm_bvalid[1 +: 1]), + .AXI_01_BREADY(m_axi_hbm_bready[1 +: 1]), + + .AXI_02_ACLK(hbm_clk[2 +: 1]), + .AXI_02_ARESET_N(!hbm_rst[2 +: 1]), + + .AXI_02_ARADDR(m_axi_hbm_araddr[2*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_02_ARBURST(m_axi_hbm_arburst[2*2 +: 2]), + .AXI_02_ARID(m_axi_hbm_arid[2*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_02_ARLEN(m_axi_hbm_arlen[2*8 +: 8]), + .AXI_02_ARSIZE(m_axi_hbm_arsize[2*3 +: 3]), + .AXI_02_ARVALID(m_axi_hbm_arvalid[2 +: 1]), + .AXI_02_ARREADY(m_axi_hbm_arready[2 +: 1]), + .AXI_02_RDATA_PARITY(), + .AXI_02_RDATA(m_axi_hbm_rdata[2*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_02_RID(m_axi_hbm_rid[2 +: 1]), + .AXI_02_RLAST(m_axi_hbm_rlast[2 +: 1]), + .AXI_02_RRESP(m_axi_hbm_rresp[2*2 +: 2]), + .AXI_02_RVALID(m_axi_hbm_rvalid[2 +: 1]), + .AXI_02_RREADY(m_axi_hbm_rready[2 +: 1]), + .AXI_02_AWADDR(m_axi_hbm_awaddr[2*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_02_AWBURST(m_axi_hbm_awburst[2*2 +: 2]), + .AXI_02_AWID(m_axi_hbm_awid[2*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_02_AWLEN(m_axi_hbm_awlen[2*8 +: 8]), + .AXI_02_AWSIZE(m_axi_hbm_awsize[2*3 +: 3]), + .AXI_02_AWVALID(m_axi_hbm_awvalid[2 +: 1]), + .AXI_02_AWREADY(m_axi_hbm_awready[2 +: 1]), + .AXI_02_WDATA(m_axi_hbm_wdata[2*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_02_WLAST(m_axi_hbm_wlast[2 +: 1]), + .AXI_02_WSTRB(m_axi_hbm_wstrb[2*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_02_WDATA_PARITY(32'd0), + .AXI_02_WVALID(m_axi_hbm_wvalid[2 +: 1]), + .AXI_02_WREADY(m_axi_hbm_wready[2 +: 1]), + .AXI_02_BID(m_axi_hbm_bid[2*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_02_BRESP(m_axi_hbm_bresp[2*2 +: 2]), + .AXI_02_BVALID(m_axi_hbm_bvalid[2 +: 1]), + .AXI_02_BREADY(m_axi_hbm_bready[2 +: 1]), + + .AXI_03_ACLK(hbm_clk[3 +: 1]), + .AXI_03_ARESET_N(!hbm_rst[3 +: 1]), + + .AXI_03_ARADDR(m_axi_hbm_araddr[3*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_03_ARBURST(m_axi_hbm_arburst[3*2 +: 2]), + .AXI_03_ARID(m_axi_hbm_arid[3*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_03_ARLEN(m_axi_hbm_arlen[3*8 +: 8]), + .AXI_03_ARSIZE(m_axi_hbm_arsize[3*3 +: 3]), + .AXI_03_ARVALID(m_axi_hbm_arvalid[3 +: 1]), + .AXI_03_ARREADY(m_axi_hbm_arready[3 +: 1]), + .AXI_03_RDATA_PARITY(), + .AXI_03_RDATA(m_axi_hbm_rdata[3*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_03_RID(m_axi_hbm_rid[3 +: 1]), + .AXI_03_RLAST(m_axi_hbm_rlast[3 +: 1]), + .AXI_03_RRESP(m_axi_hbm_rresp[3*2 +: 2]), + .AXI_03_RVALID(m_axi_hbm_rvalid[3 +: 1]), + .AXI_03_RREADY(m_axi_hbm_rready[3 +: 1]), + .AXI_03_AWADDR(m_axi_hbm_awaddr[3*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_03_AWBURST(m_axi_hbm_awburst[3*2 +: 2]), + .AXI_03_AWID(m_axi_hbm_awid[3*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_03_AWLEN(m_axi_hbm_awlen[3*8 +: 8]), + .AXI_03_AWSIZE(m_axi_hbm_awsize[3*3 +: 3]), + .AXI_03_AWVALID(m_axi_hbm_awvalid[3 +: 1]), + .AXI_03_AWREADY(m_axi_hbm_awready[3 +: 1]), + .AXI_03_WDATA(m_axi_hbm_wdata[3*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_03_WLAST(m_axi_hbm_wlast[3 +: 1]), + .AXI_03_WSTRB(m_axi_hbm_wstrb[3*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_03_WDATA_PARITY(32'd0), + .AXI_03_WVALID(m_axi_hbm_wvalid[3 +: 1]), + .AXI_03_WREADY(m_axi_hbm_wready[3 +: 1]), + .AXI_03_BID(m_axi_hbm_bid[3*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_03_BRESP(m_axi_hbm_bresp[3*2 +: 2]), + .AXI_03_BVALID(m_axi_hbm_bvalid[3 +: 1]), + .AXI_03_BREADY(m_axi_hbm_bready[3 +: 1]), + + .AXI_04_ACLK(hbm_clk[4 +: 1]), + .AXI_04_ARESET_N(!hbm_rst[4 +: 1]), + + .AXI_04_ARADDR(m_axi_hbm_araddr[4*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_04_ARBURST(m_axi_hbm_arburst[4*2 +: 2]), + .AXI_04_ARID(m_axi_hbm_arid[4*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_04_ARLEN(m_axi_hbm_arlen[4*8 +: 8]), + .AXI_04_ARSIZE(m_axi_hbm_arsize[4*3 +: 3]), + .AXI_04_ARVALID(m_axi_hbm_arvalid[4 +: 1]), + .AXI_04_ARREADY(m_axi_hbm_arready[4 +: 1]), + .AXI_04_RDATA_PARITY(), + .AXI_04_RDATA(m_axi_hbm_rdata[4*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_04_RID(m_axi_hbm_rid[4 +: 1]), + .AXI_04_RLAST(m_axi_hbm_rlast[4 +: 1]), + .AXI_04_RRESP(m_axi_hbm_rresp[4*2 +: 2]), + .AXI_04_RVALID(m_axi_hbm_rvalid[4 +: 1]), + .AXI_04_RREADY(m_axi_hbm_rready[4 +: 1]), + .AXI_04_AWADDR(m_axi_hbm_awaddr[4*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_04_AWBURST(m_axi_hbm_awburst[4*2 +: 2]), + .AXI_04_AWID(m_axi_hbm_awid[4*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_04_AWLEN(m_axi_hbm_awlen[4*8 +: 8]), + .AXI_04_AWSIZE(m_axi_hbm_awsize[4*3 +: 3]), + .AXI_04_AWVALID(m_axi_hbm_awvalid[4 +: 1]), + .AXI_04_AWREADY(m_axi_hbm_awready[4 +: 1]), + .AXI_04_WDATA(m_axi_hbm_wdata[4*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_04_WLAST(m_axi_hbm_wlast[4 +: 1]), + .AXI_04_WSTRB(m_axi_hbm_wstrb[4*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_04_WDATA_PARITY(32'd0), + .AXI_04_WVALID(m_axi_hbm_wvalid[4 +: 1]), + .AXI_04_WREADY(m_axi_hbm_wready[4 +: 1]), + .AXI_04_BID(m_axi_hbm_bid[4*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_04_BRESP(m_axi_hbm_bresp[4*2 +: 2]), + .AXI_04_BVALID(m_axi_hbm_bvalid[4 +: 1]), + .AXI_04_BREADY(m_axi_hbm_bready[4 +: 1]), + + .AXI_05_ACLK(hbm_clk[5 +: 1]), + .AXI_05_ARESET_N(!hbm_rst[5 +: 1]), + + .AXI_05_ARADDR(m_axi_hbm_araddr[5*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_05_ARBURST(m_axi_hbm_arburst[5*2 +: 2]), + .AXI_05_ARID(m_axi_hbm_arid[5*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_05_ARLEN(m_axi_hbm_arlen[5*8 +: 8]), + .AXI_05_ARSIZE(m_axi_hbm_arsize[5*3 +: 3]), + .AXI_05_ARVALID(m_axi_hbm_arvalid[5 +: 1]), + .AXI_05_ARREADY(m_axi_hbm_arready[5 +: 1]), + .AXI_05_RDATA_PARITY(), + .AXI_05_RDATA(m_axi_hbm_rdata[5*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_05_RID(m_axi_hbm_rid[5 +: 1]), + .AXI_05_RLAST(m_axi_hbm_rlast[5 +: 1]), + .AXI_05_RRESP(m_axi_hbm_rresp[5*2 +: 2]), + .AXI_05_RVALID(m_axi_hbm_rvalid[5 +: 1]), + .AXI_05_RREADY(m_axi_hbm_rready[5 +: 1]), + .AXI_05_AWADDR(m_axi_hbm_awaddr[5*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_05_AWBURST(m_axi_hbm_awburst[5*2 +: 2]), + .AXI_05_AWID(m_axi_hbm_awid[5*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_05_AWLEN(m_axi_hbm_awlen[5*8 +: 8]), + .AXI_05_AWSIZE(m_axi_hbm_awsize[5*3 +: 3]), + .AXI_05_AWVALID(m_axi_hbm_awvalid[5 +: 1]), + .AXI_05_AWREADY(m_axi_hbm_awready[5 +: 1]), + .AXI_05_WDATA(m_axi_hbm_wdata[5*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_05_WLAST(m_axi_hbm_wlast[5 +: 1]), + .AXI_05_WSTRB(m_axi_hbm_wstrb[5*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_05_WDATA_PARITY(32'd0), + .AXI_05_WVALID(m_axi_hbm_wvalid[5 +: 1]), + .AXI_05_WREADY(m_axi_hbm_wready[5 +: 1]), + .AXI_05_BID(m_axi_hbm_bid[5*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_05_BRESP(m_axi_hbm_bresp[5*2 +: 2]), + .AXI_05_BVALID(m_axi_hbm_bvalid[5 +: 1]), + .AXI_05_BREADY(m_axi_hbm_bready[5 +: 1]), + + .AXI_06_ACLK(hbm_clk[6 +: 1]), + .AXI_06_ARESET_N(!hbm_rst[6 +: 1]), + + .AXI_06_ARADDR(m_axi_hbm_araddr[6*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_06_ARBURST(m_axi_hbm_arburst[6*2 +: 2]), + .AXI_06_ARID(m_axi_hbm_arid[6*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_06_ARLEN(m_axi_hbm_arlen[6*8 +: 8]), + .AXI_06_ARSIZE(m_axi_hbm_arsize[6*3 +: 3]), + .AXI_06_ARVALID(m_axi_hbm_arvalid[6 +: 1]), + .AXI_06_ARREADY(m_axi_hbm_arready[6 +: 1]), + .AXI_06_RDATA_PARITY(), + .AXI_06_RDATA(m_axi_hbm_rdata[6*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_06_RID(m_axi_hbm_rid[6 +: 1]), + .AXI_06_RLAST(m_axi_hbm_rlast[6 +: 1]), + .AXI_06_RRESP(m_axi_hbm_rresp[6*2 +: 2]), + .AXI_06_RVALID(m_axi_hbm_rvalid[6 +: 1]), + .AXI_06_RREADY(m_axi_hbm_rready[6 +: 1]), + .AXI_06_AWADDR(m_axi_hbm_awaddr[6*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_06_AWBURST(m_axi_hbm_awburst[6*2 +: 2]), + .AXI_06_AWID(m_axi_hbm_awid[6*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_06_AWLEN(m_axi_hbm_awlen[6*8 +: 8]), + .AXI_06_AWSIZE(m_axi_hbm_awsize[6*3 +: 3]), + .AXI_06_AWVALID(m_axi_hbm_awvalid[6 +: 1]), + .AXI_06_AWREADY(m_axi_hbm_awready[6 +: 1]), + .AXI_06_WDATA(m_axi_hbm_wdata[6*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_06_WLAST(m_axi_hbm_wlast[6 +: 1]), + .AXI_06_WSTRB(m_axi_hbm_wstrb[6*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_06_WDATA_PARITY(32'd0), + .AXI_06_WVALID(m_axi_hbm_wvalid[6 +: 1]), + .AXI_06_WREADY(m_axi_hbm_wready[6 +: 1]), + .AXI_06_BID(m_axi_hbm_bid[6*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_06_BRESP(m_axi_hbm_bresp[6*2 +: 2]), + .AXI_06_BVALID(m_axi_hbm_bvalid[6 +: 1]), + .AXI_06_BREADY(m_axi_hbm_bready[6 +: 1]), + + .AXI_07_ACLK(hbm_clk[7 +: 1]), + .AXI_07_ARESET_N(!hbm_rst[7 +: 1]), + + .AXI_07_ARADDR(m_axi_hbm_araddr[7*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_07_ARBURST(m_axi_hbm_arburst[7*2 +: 2]), + .AXI_07_ARID(m_axi_hbm_arid[7*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_07_ARLEN(m_axi_hbm_arlen[7*8 +: 8]), + .AXI_07_ARSIZE(m_axi_hbm_arsize[7*3 +: 3]), + .AXI_07_ARVALID(m_axi_hbm_arvalid[7 +: 1]), + .AXI_07_ARREADY(m_axi_hbm_arready[7 +: 1]), + .AXI_07_RDATA_PARITY(), + .AXI_07_RDATA(m_axi_hbm_rdata[7*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_07_RID(m_axi_hbm_rid[7 +: 1]), + .AXI_07_RLAST(m_axi_hbm_rlast[7 +: 1]), + .AXI_07_RRESP(m_axi_hbm_rresp[7*2 +: 2]), + .AXI_07_RVALID(m_axi_hbm_rvalid[7 +: 1]), + .AXI_07_RREADY(m_axi_hbm_rready[7 +: 1]), + .AXI_07_AWADDR(m_axi_hbm_awaddr[7*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_07_AWBURST(m_axi_hbm_awburst[7*2 +: 2]), + .AXI_07_AWID(m_axi_hbm_awid[7*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_07_AWLEN(m_axi_hbm_awlen[7*8 +: 8]), + .AXI_07_AWSIZE(m_axi_hbm_awsize[7*3 +: 3]), + .AXI_07_AWVALID(m_axi_hbm_awvalid[7 +: 1]), + .AXI_07_AWREADY(m_axi_hbm_awready[7 +: 1]), + .AXI_07_WDATA(m_axi_hbm_wdata[7*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_07_WLAST(m_axi_hbm_wlast[7 +: 1]), + .AXI_07_WSTRB(m_axi_hbm_wstrb[7*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_07_WDATA_PARITY(32'd0), + .AXI_07_WVALID(m_axi_hbm_wvalid[7 +: 1]), + .AXI_07_WREADY(m_axi_hbm_wready[7 +: 1]), + .AXI_07_BID(m_axi_hbm_bid[7*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_07_BRESP(m_axi_hbm_bresp[7*2 +: 2]), + .AXI_07_BVALID(m_axi_hbm_bvalid[7 +: 1]), + .AXI_07_BREADY(m_axi_hbm_bready[7 +: 1]), + + .AXI_08_ACLK(hbm_clk[8 +: 1]), + .AXI_08_ARESET_N(!hbm_rst[8 +: 1]), + + .AXI_08_ARADDR(m_axi_hbm_araddr[8*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_08_ARBURST(m_axi_hbm_arburst[8*2 +: 2]), + .AXI_08_ARID(m_axi_hbm_arid[8*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_08_ARLEN(m_axi_hbm_arlen[8*8 +: 8]), + .AXI_08_ARSIZE(m_axi_hbm_arsize[8*3 +: 3]), + .AXI_08_ARVALID(m_axi_hbm_arvalid[8 +: 1]), + .AXI_08_ARREADY(m_axi_hbm_arready[8 +: 1]), + .AXI_08_RDATA_PARITY(), + .AXI_08_RDATA(m_axi_hbm_rdata[8*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_08_RID(m_axi_hbm_rid[8 +: 1]), + .AXI_08_RLAST(m_axi_hbm_rlast[8 +: 1]), + .AXI_08_RRESP(m_axi_hbm_rresp[8*2 +: 2]), + .AXI_08_RVALID(m_axi_hbm_rvalid[8 +: 1]), + .AXI_08_RREADY(m_axi_hbm_rready[8 +: 1]), + .AXI_08_AWADDR(m_axi_hbm_awaddr[8*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_08_AWBURST(m_axi_hbm_awburst[8*2 +: 2]), + .AXI_08_AWID(m_axi_hbm_awid[8*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_08_AWLEN(m_axi_hbm_awlen[8*8 +: 8]), + .AXI_08_AWSIZE(m_axi_hbm_awsize[8*3 +: 3]), + .AXI_08_AWVALID(m_axi_hbm_awvalid[8 +: 1]), + .AXI_08_AWREADY(m_axi_hbm_awready[8 +: 1]), + .AXI_08_WDATA(m_axi_hbm_wdata[8*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_08_WLAST(m_axi_hbm_wlast[8 +: 1]), + .AXI_08_WSTRB(m_axi_hbm_wstrb[8*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_08_WDATA_PARITY(32'd0), + .AXI_08_WVALID(m_axi_hbm_wvalid[8 +: 1]), + .AXI_08_WREADY(m_axi_hbm_wready[8 +: 1]), + .AXI_08_BID(m_axi_hbm_bid[8*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_08_BRESP(m_axi_hbm_bresp[8*2 +: 2]), + .AXI_08_BVALID(m_axi_hbm_bvalid[8 +: 1]), + .AXI_08_BREADY(m_axi_hbm_bready[8 +: 1]), + + .AXI_09_ACLK(hbm_clk[9 +: 1]), + .AXI_09_ARESET_N(!hbm_rst[9 +: 1]), + + .AXI_09_ARADDR(m_axi_hbm_araddr[9*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_09_ARBURST(m_axi_hbm_arburst[9*2 +: 2]), + .AXI_09_ARID(m_axi_hbm_arid[9*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_09_ARLEN(m_axi_hbm_arlen[9*8 +: 8]), + .AXI_09_ARSIZE(m_axi_hbm_arsize[9*3 +: 3]), + .AXI_09_ARVALID(m_axi_hbm_arvalid[9 +: 1]), + .AXI_09_ARREADY(m_axi_hbm_arready[9 +: 1]), + .AXI_09_RDATA_PARITY(), + .AXI_09_RDATA(m_axi_hbm_rdata[9*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_09_RID(m_axi_hbm_rid[9 +: 1]), + .AXI_09_RLAST(m_axi_hbm_rlast[9 +: 1]), + .AXI_09_RRESP(m_axi_hbm_rresp[9*2 +: 2]), + .AXI_09_RVALID(m_axi_hbm_rvalid[9 +: 1]), + .AXI_09_RREADY(m_axi_hbm_rready[9 +: 1]), + .AXI_09_AWADDR(m_axi_hbm_awaddr[9*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_09_AWBURST(m_axi_hbm_awburst[9*2 +: 2]), + .AXI_09_AWID(m_axi_hbm_awid[9*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_09_AWLEN(m_axi_hbm_awlen[9*8 +: 8]), + .AXI_09_AWSIZE(m_axi_hbm_awsize[9*3 +: 3]), + .AXI_09_AWVALID(m_axi_hbm_awvalid[9 +: 1]), + .AXI_09_AWREADY(m_axi_hbm_awready[9 +: 1]), + .AXI_09_WDATA(m_axi_hbm_wdata[9*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_09_WLAST(m_axi_hbm_wlast[9 +: 1]), + .AXI_09_WSTRB(m_axi_hbm_wstrb[9*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_09_WDATA_PARITY(32'd0), + .AXI_09_WVALID(m_axi_hbm_wvalid[9 +: 1]), + .AXI_09_WREADY(m_axi_hbm_wready[9 +: 1]), + .AXI_09_BID(m_axi_hbm_bid[9*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_09_BRESP(m_axi_hbm_bresp[9*2 +: 2]), + .AXI_09_BVALID(m_axi_hbm_bvalid[9 +: 1]), + .AXI_09_BREADY(m_axi_hbm_bready[9 +: 1]), + + .AXI_10_ACLK(hbm_clk[10 +: 1]), + .AXI_10_ARESET_N(!hbm_rst[10 +: 1]), + + .AXI_10_ARADDR(m_axi_hbm_araddr[10*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_10_ARBURST(m_axi_hbm_arburst[10*2 +: 2]), + .AXI_10_ARID(m_axi_hbm_arid[10*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_10_ARLEN(m_axi_hbm_arlen[10*8 +: 8]), + .AXI_10_ARSIZE(m_axi_hbm_arsize[10*3 +: 3]), + .AXI_10_ARVALID(m_axi_hbm_arvalid[10 +: 1]), + .AXI_10_ARREADY(m_axi_hbm_arready[10 +: 1]), + .AXI_10_RDATA_PARITY(), + .AXI_10_RDATA(m_axi_hbm_rdata[10*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_10_RID(m_axi_hbm_rid[10 +: 1]), + .AXI_10_RLAST(m_axi_hbm_rlast[10 +: 1]), + .AXI_10_RRESP(m_axi_hbm_rresp[10*2 +: 2]), + .AXI_10_RVALID(m_axi_hbm_rvalid[10 +: 1]), + .AXI_10_RREADY(m_axi_hbm_rready[10 +: 1]), + .AXI_10_AWADDR(m_axi_hbm_awaddr[10*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_10_AWBURST(m_axi_hbm_awburst[10*2 +: 2]), + .AXI_10_AWID(m_axi_hbm_awid[10*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_10_AWLEN(m_axi_hbm_awlen[10*8 +: 8]), + .AXI_10_AWSIZE(m_axi_hbm_awsize[10*3 +: 3]), + .AXI_10_AWVALID(m_axi_hbm_awvalid[10 +: 1]), + .AXI_10_AWREADY(m_axi_hbm_awready[10 +: 1]), + .AXI_10_WDATA(m_axi_hbm_wdata[10*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_10_WLAST(m_axi_hbm_wlast[10 +: 1]), + .AXI_10_WSTRB(m_axi_hbm_wstrb[10*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_10_WDATA_PARITY(32'd0), + .AXI_10_WVALID(m_axi_hbm_wvalid[10 +: 1]), + .AXI_10_WREADY(m_axi_hbm_wready[10 +: 1]), + .AXI_10_BID(m_axi_hbm_bid[10*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_10_BRESP(m_axi_hbm_bresp[10*2 +: 2]), + .AXI_10_BVALID(m_axi_hbm_bvalid[10 +: 1]), + .AXI_10_BREADY(m_axi_hbm_bready[10 +: 1]), + + .AXI_11_ACLK(hbm_clk[11 +: 1]), + .AXI_11_ARESET_N(!hbm_rst[11 +: 1]), + + .AXI_11_ARADDR(m_axi_hbm_araddr[11*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_11_ARBURST(m_axi_hbm_arburst[11*2 +: 2]), + .AXI_11_ARID(m_axi_hbm_arid[11*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_11_ARLEN(m_axi_hbm_arlen[11*8 +: 8]), + .AXI_11_ARSIZE(m_axi_hbm_arsize[11*3 +: 3]), + .AXI_11_ARVALID(m_axi_hbm_arvalid[11 +: 1]), + .AXI_11_ARREADY(m_axi_hbm_arready[11 +: 1]), + .AXI_11_RDATA_PARITY(), + .AXI_11_RDATA(m_axi_hbm_rdata[11*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_11_RID(m_axi_hbm_rid[11 +: 1]), + .AXI_11_RLAST(m_axi_hbm_rlast[11 +: 1]), + .AXI_11_RRESP(m_axi_hbm_rresp[11*2 +: 2]), + .AXI_11_RVALID(m_axi_hbm_rvalid[11 +: 1]), + .AXI_11_RREADY(m_axi_hbm_rready[11 +: 1]), + .AXI_11_AWADDR(m_axi_hbm_awaddr[11*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_11_AWBURST(m_axi_hbm_awburst[11*2 +: 2]), + .AXI_11_AWID(m_axi_hbm_awid[11*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_11_AWLEN(m_axi_hbm_awlen[11*8 +: 8]), + .AXI_11_AWSIZE(m_axi_hbm_awsize[11*3 +: 3]), + .AXI_11_AWVALID(m_axi_hbm_awvalid[11 +: 1]), + .AXI_11_AWREADY(m_axi_hbm_awready[11 +: 1]), + .AXI_11_WDATA(m_axi_hbm_wdata[11*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_11_WLAST(m_axi_hbm_wlast[11 +: 1]), + .AXI_11_WSTRB(m_axi_hbm_wstrb[11*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_11_WDATA_PARITY(32'd0), + .AXI_11_WVALID(m_axi_hbm_wvalid[11 +: 1]), + .AXI_11_WREADY(m_axi_hbm_wready[11 +: 1]), + .AXI_11_BID(m_axi_hbm_bid[11*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_11_BRESP(m_axi_hbm_bresp[11*2 +: 2]), + .AXI_11_BVALID(m_axi_hbm_bvalid[11 +: 1]), + .AXI_11_BREADY(m_axi_hbm_bready[11 +: 1]), + + .AXI_12_ACLK(hbm_clk[12 +: 1]), + .AXI_12_ARESET_N(!hbm_rst[12 +: 1]), + + .AXI_12_ARADDR(m_axi_hbm_araddr[12*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_12_ARBURST(m_axi_hbm_arburst[12*2 +: 2]), + .AXI_12_ARID(m_axi_hbm_arid[12*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_12_ARLEN(m_axi_hbm_arlen[12*8 +: 8]), + .AXI_12_ARSIZE(m_axi_hbm_arsize[12*3 +: 3]), + .AXI_12_ARVALID(m_axi_hbm_arvalid[12 +: 1]), + .AXI_12_ARREADY(m_axi_hbm_arready[12 +: 1]), + .AXI_12_RDATA_PARITY(), + .AXI_12_RDATA(m_axi_hbm_rdata[12*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_12_RID(m_axi_hbm_rid[12 +: 1]), + .AXI_12_RLAST(m_axi_hbm_rlast[12 +: 1]), + .AXI_12_RRESP(m_axi_hbm_rresp[12*2 +: 2]), + .AXI_12_RVALID(m_axi_hbm_rvalid[12 +: 1]), + .AXI_12_RREADY(m_axi_hbm_rready[12 +: 1]), + .AXI_12_AWADDR(m_axi_hbm_awaddr[12*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_12_AWBURST(m_axi_hbm_awburst[12*2 +: 2]), + .AXI_12_AWID(m_axi_hbm_awid[12*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_12_AWLEN(m_axi_hbm_awlen[12*8 +: 8]), + .AXI_12_AWSIZE(m_axi_hbm_awsize[12*3 +: 3]), + .AXI_12_AWVALID(m_axi_hbm_awvalid[12 +: 1]), + .AXI_12_AWREADY(m_axi_hbm_awready[12 +: 1]), + .AXI_12_WDATA(m_axi_hbm_wdata[12*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_12_WLAST(m_axi_hbm_wlast[12 +: 1]), + .AXI_12_WSTRB(m_axi_hbm_wstrb[12*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_12_WDATA_PARITY(32'd0), + .AXI_12_WVALID(m_axi_hbm_wvalid[12 +: 1]), + .AXI_12_WREADY(m_axi_hbm_wready[12 +: 1]), + .AXI_12_BID(m_axi_hbm_bid[12*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_12_BRESP(m_axi_hbm_bresp[12*2 +: 2]), + .AXI_12_BVALID(m_axi_hbm_bvalid[12 +: 1]), + .AXI_12_BREADY(m_axi_hbm_bready[12 +: 1]), + + .AXI_13_ACLK(hbm_clk[13 +: 1]), + .AXI_13_ARESET_N(!hbm_rst[13 +: 1]), + + .AXI_13_ARADDR(m_axi_hbm_araddr[13*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_13_ARBURST(m_axi_hbm_arburst[13*2 +: 2]), + .AXI_13_ARID(m_axi_hbm_arid[13*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_13_ARLEN(m_axi_hbm_arlen[13*8 +: 8]), + .AXI_13_ARSIZE(m_axi_hbm_arsize[13*3 +: 3]), + .AXI_13_ARVALID(m_axi_hbm_arvalid[13 +: 1]), + .AXI_13_ARREADY(m_axi_hbm_arready[13 +: 1]), + .AXI_13_RDATA_PARITY(), + .AXI_13_RDATA(m_axi_hbm_rdata[13*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_13_RID(m_axi_hbm_rid[13 +: 1]), + .AXI_13_RLAST(m_axi_hbm_rlast[13 +: 1]), + .AXI_13_RRESP(m_axi_hbm_rresp[13*2 +: 2]), + .AXI_13_RVALID(m_axi_hbm_rvalid[13 +: 1]), + .AXI_13_RREADY(m_axi_hbm_rready[13 +: 1]), + .AXI_13_AWADDR(m_axi_hbm_awaddr[13*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_13_AWBURST(m_axi_hbm_awburst[13*2 +: 2]), + .AXI_13_AWID(m_axi_hbm_awid[13*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_13_AWLEN(m_axi_hbm_awlen[13*8 +: 8]), + .AXI_13_AWSIZE(m_axi_hbm_awsize[13*3 +: 3]), + .AXI_13_AWVALID(m_axi_hbm_awvalid[13 +: 1]), + .AXI_13_AWREADY(m_axi_hbm_awready[13 +: 1]), + .AXI_13_WDATA(m_axi_hbm_wdata[13*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_13_WLAST(m_axi_hbm_wlast[13 +: 1]), + .AXI_13_WSTRB(m_axi_hbm_wstrb[13*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_13_WDATA_PARITY(32'd0), + .AXI_13_WVALID(m_axi_hbm_wvalid[13 +: 1]), + .AXI_13_WREADY(m_axi_hbm_wready[13 +: 1]), + .AXI_13_BID(m_axi_hbm_bid[13*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_13_BRESP(m_axi_hbm_bresp[13*2 +: 2]), + .AXI_13_BVALID(m_axi_hbm_bvalid[13 +: 1]), + .AXI_13_BREADY(m_axi_hbm_bready[13 +: 1]), + + .AXI_14_ACLK(hbm_clk[14 +: 1]), + .AXI_14_ARESET_N(!hbm_rst[14 +: 1]), + + .AXI_14_ARADDR(m_axi_hbm_araddr[14*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_14_ARBURST(m_axi_hbm_arburst[14*2 +: 2]), + .AXI_14_ARID(m_axi_hbm_arid[14*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_14_ARLEN(m_axi_hbm_arlen[14*8 +: 8]), + .AXI_14_ARSIZE(m_axi_hbm_arsize[14*3 +: 3]), + .AXI_14_ARVALID(m_axi_hbm_arvalid[14 +: 1]), + .AXI_14_ARREADY(m_axi_hbm_arready[14 +: 1]), + .AXI_14_RDATA_PARITY(), + .AXI_14_RDATA(m_axi_hbm_rdata[14*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_14_RID(m_axi_hbm_rid[14 +: 1]), + .AXI_14_RLAST(m_axi_hbm_rlast[14 +: 1]), + .AXI_14_RRESP(m_axi_hbm_rresp[14*2 +: 2]), + .AXI_14_RVALID(m_axi_hbm_rvalid[14 +: 1]), + .AXI_14_RREADY(m_axi_hbm_rready[14 +: 1]), + .AXI_14_AWADDR(m_axi_hbm_awaddr[14*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_14_AWBURST(m_axi_hbm_awburst[14*2 +: 2]), + .AXI_14_AWID(m_axi_hbm_awid[14*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_14_AWLEN(m_axi_hbm_awlen[14*8 +: 8]), + .AXI_14_AWSIZE(m_axi_hbm_awsize[14*3 +: 3]), + .AXI_14_AWVALID(m_axi_hbm_awvalid[14 +: 1]), + .AXI_14_AWREADY(m_axi_hbm_awready[14 +: 1]), + .AXI_14_WDATA(m_axi_hbm_wdata[14*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_14_WLAST(m_axi_hbm_wlast[14 +: 1]), + .AXI_14_WSTRB(m_axi_hbm_wstrb[14*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_14_WDATA_PARITY(32'd0), + .AXI_14_WVALID(m_axi_hbm_wvalid[14 +: 1]), + .AXI_14_WREADY(m_axi_hbm_wready[14 +: 1]), + .AXI_14_BID(m_axi_hbm_bid[14*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_14_BRESP(m_axi_hbm_bresp[14*2 +: 2]), + .AXI_14_BVALID(m_axi_hbm_bvalid[14 +: 1]), + .AXI_14_BREADY(m_axi_hbm_bready[14 +: 1]), + + .AXI_15_ACLK(hbm_clk[15 +: 1]), + .AXI_15_ARESET_N(!hbm_rst[15 +: 1]), + + .AXI_15_ARADDR(m_axi_hbm_araddr[15*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_15_ARBURST(m_axi_hbm_arburst[15*2 +: 2]), + .AXI_15_ARID(m_axi_hbm_arid[15*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_15_ARLEN(m_axi_hbm_arlen[15*8 +: 8]), + .AXI_15_ARSIZE(m_axi_hbm_arsize[15*3 +: 3]), + .AXI_15_ARVALID(m_axi_hbm_arvalid[15 +: 1]), + .AXI_15_ARREADY(m_axi_hbm_arready[15 +: 1]), + .AXI_15_RDATA_PARITY(), + .AXI_15_RDATA(m_axi_hbm_rdata[15*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_15_RID(m_axi_hbm_rid[15 +: 1]), + .AXI_15_RLAST(m_axi_hbm_rlast[15 +: 1]), + .AXI_15_RRESP(m_axi_hbm_rresp[15*2 +: 2]), + .AXI_15_RVALID(m_axi_hbm_rvalid[15 +: 1]), + .AXI_15_RREADY(m_axi_hbm_rready[15 +: 1]), + .AXI_15_AWADDR(m_axi_hbm_awaddr[15*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_15_AWBURST(m_axi_hbm_awburst[15*2 +: 2]), + .AXI_15_AWID(m_axi_hbm_awid[15*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_15_AWLEN(m_axi_hbm_awlen[15*8 +: 8]), + .AXI_15_AWSIZE(m_axi_hbm_awsize[15*3 +: 3]), + .AXI_15_AWVALID(m_axi_hbm_awvalid[15 +: 1]), + .AXI_15_AWREADY(m_axi_hbm_awready[15 +: 1]), + .AXI_15_WDATA(m_axi_hbm_wdata[15*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_15_WLAST(m_axi_hbm_wlast[15 +: 1]), + .AXI_15_WSTRB(m_axi_hbm_wstrb[15*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_15_WDATA_PARITY(32'd0), + .AXI_15_WVALID(m_axi_hbm_wvalid[15 +: 1]), + .AXI_15_WREADY(m_axi_hbm_wready[15 +: 1]), + .AXI_15_BID(m_axi_hbm_bid[15*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_15_BRESP(m_axi_hbm_bresp[15*2 +: 2]), + .AXI_15_BVALID(m_axi_hbm_bvalid[15 +: 1]), + .AXI_15_BREADY(m_axi_hbm_bready[15 +: 1]), + + .AXI_16_ACLK(hbm_clk[16 +: 1]), + .AXI_16_ARESET_N(!hbm_rst[16 +: 1]), + + .AXI_16_ARADDR(m_axi_hbm_araddr[16*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_16_ARBURST(m_axi_hbm_arburst[16*2 +: 2]), + .AXI_16_ARID(m_axi_hbm_arid[16*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_16_ARLEN(m_axi_hbm_arlen[16*8 +: 8]), + .AXI_16_ARSIZE(m_axi_hbm_arsize[16*3 +: 3]), + .AXI_16_ARVALID(m_axi_hbm_arvalid[16 +: 1]), + .AXI_16_ARREADY(m_axi_hbm_arready[16 +: 1]), + .AXI_16_RDATA_PARITY(), + .AXI_16_RDATA(m_axi_hbm_rdata[16*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_16_RID(m_axi_hbm_rid[16 +: 1]), + .AXI_16_RLAST(m_axi_hbm_rlast[16 +: 1]), + .AXI_16_RRESP(m_axi_hbm_rresp[16*2 +: 2]), + .AXI_16_RVALID(m_axi_hbm_rvalid[16 +: 1]), + .AXI_16_RREADY(m_axi_hbm_rready[16 +: 1]), + .AXI_16_AWADDR(m_axi_hbm_awaddr[16*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_16_AWBURST(m_axi_hbm_awburst[16*2 +: 2]), + .AXI_16_AWID(m_axi_hbm_awid[16*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_16_AWLEN(m_axi_hbm_awlen[16*8 +: 8]), + .AXI_16_AWSIZE(m_axi_hbm_awsize[16*3 +: 3]), + .AXI_16_AWVALID(m_axi_hbm_awvalid[16 +: 1]), + .AXI_16_AWREADY(m_axi_hbm_awready[16 +: 1]), + .AXI_16_WDATA(m_axi_hbm_wdata[16*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_16_WLAST(m_axi_hbm_wlast[16 +: 1]), + .AXI_16_WSTRB(m_axi_hbm_wstrb[16*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_16_WDATA_PARITY(32'd0), + .AXI_16_WVALID(m_axi_hbm_wvalid[16 +: 1]), + .AXI_16_WREADY(m_axi_hbm_wready[16 +: 1]), + .AXI_16_BID(m_axi_hbm_bid[16*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_16_BRESP(m_axi_hbm_bresp[16*2 +: 2]), + .AXI_16_BVALID(m_axi_hbm_bvalid[16 +: 1]), + .AXI_16_BREADY(m_axi_hbm_bready[16 +: 1]), + + .AXI_17_ACLK(hbm_clk[17 +: 1]), + .AXI_17_ARESET_N(!hbm_rst[17 +: 1]), + + .AXI_17_ARADDR(m_axi_hbm_araddr[17*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_17_ARBURST(m_axi_hbm_arburst[17*2 +: 2]), + .AXI_17_ARID(m_axi_hbm_arid[17*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_17_ARLEN(m_axi_hbm_arlen[17*8 +: 8]), + .AXI_17_ARSIZE(m_axi_hbm_arsize[17*3 +: 3]), + .AXI_17_ARVALID(m_axi_hbm_arvalid[17 +: 1]), + .AXI_17_ARREADY(m_axi_hbm_arready[17 +: 1]), + .AXI_17_RDATA_PARITY(), + .AXI_17_RDATA(m_axi_hbm_rdata[17*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_17_RID(m_axi_hbm_rid[17 +: 1]), + .AXI_17_RLAST(m_axi_hbm_rlast[17 +: 1]), + .AXI_17_RRESP(m_axi_hbm_rresp[17*2 +: 2]), + .AXI_17_RVALID(m_axi_hbm_rvalid[17 +: 1]), + .AXI_17_RREADY(m_axi_hbm_rready[17 +: 1]), + .AXI_17_AWADDR(m_axi_hbm_awaddr[17*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_17_AWBURST(m_axi_hbm_awburst[17*2 +: 2]), + .AXI_17_AWID(m_axi_hbm_awid[17*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_17_AWLEN(m_axi_hbm_awlen[17*8 +: 8]), + .AXI_17_AWSIZE(m_axi_hbm_awsize[17*3 +: 3]), + .AXI_17_AWVALID(m_axi_hbm_awvalid[17 +: 1]), + .AXI_17_AWREADY(m_axi_hbm_awready[17 +: 1]), + .AXI_17_WDATA(m_axi_hbm_wdata[17*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_17_WLAST(m_axi_hbm_wlast[17 +: 1]), + .AXI_17_WSTRB(m_axi_hbm_wstrb[17*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_17_WDATA_PARITY(32'd0), + .AXI_17_WVALID(m_axi_hbm_wvalid[17 +: 1]), + .AXI_17_WREADY(m_axi_hbm_wready[17 +: 1]), + .AXI_17_BID(m_axi_hbm_bid[17*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_17_BRESP(m_axi_hbm_bresp[17*2 +: 2]), + .AXI_17_BVALID(m_axi_hbm_bvalid[17 +: 1]), + .AXI_17_BREADY(m_axi_hbm_bready[17 +: 1]), + + .AXI_18_ACLK(hbm_clk[18 +: 1]), + .AXI_18_ARESET_N(!hbm_rst[18 +: 1]), + + .AXI_18_ARADDR(m_axi_hbm_araddr[18*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_18_ARBURST(m_axi_hbm_arburst[18*2 +: 2]), + .AXI_18_ARID(m_axi_hbm_arid[18*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_18_ARLEN(m_axi_hbm_arlen[18*8 +: 8]), + .AXI_18_ARSIZE(m_axi_hbm_arsize[18*3 +: 3]), + .AXI_18_ARVALID(m_axi_hbm_arvalid[18 +: 1]), + .AXI_18_ARREADY(m_axi_hbm_arready[18 +: 1]), + .AXI_18_RDATA_PARITY(), + .AXI_18_RDATA(m_axi_hbm_rdata[18*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_18_RID(m_axi_hbm_rid[18 +: 1]), + .AXI_18_RLAST(m_axi_hbm_rlast[18 +: 1]), + .AXI_18_RRESP(m_axi_hbm_rresp[18*2 +: 2]), + .AXI_18_RVALID(m_axi_hbm_rvalid[18 +: 1]), + .AXI_18_RREADY(m_axi_hbm_rready[18 +: 1]), + .AXI_18_AWADDR(m_axi_hbm_awaddr[18*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_18_AWBURST(m_axi_hbm_awburst[18*2 +: 2]), + .AXI_18_AWID(m_axi_hbm_awid[18*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_18_AWLEN(m_axi_hbm_awlen[18*8 +: 8]), + .AXI_18_AWSIZE(m_axi_hbm_awsize[18*3 +: 3]), + .AXI_18_AWVALID(m_axi_hbm_awvalid[18 +: 1]), + .AXI_18_AWREADY(m_axi_hbm_awready[18 +: 1]), + .AXI_18_WDATA(m_axi_hbm_wdata[18*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_18_WLAST(m_axi_hbm_wlast[18 +: 1]), + .AXI_18_WSTRB(m_axi_hbm_wstrb[18*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_18_WDATA_PARITY(32'd0), + .AXI_18_WVALID(m_axi_hbm_wvalid[18 +: 1]), + .AXI_18_WREADY(m_axi_hbm_wready[18 +: 1]), + .AXI_18_BID(m_axi_hbm_bid[18*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_18_BRESP(m_axi_hbm_bresp[18*2 +: 2]), + .AXI_18_BVALID(m_axi_hbm_bvalid[18 +: 1]), + .AXI_18_BREADY(m_axi_hbm_bready[18 +: 1]), + + .AXI_19_ACLK(hbm_clk[19 +: 1]), + .AXI_19_ARESET_N(!hbm_rst[19 +: 1]), + + .AXI_19_ARADDR(m_axi_hbm_araddr[19*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_19_ARBURST(m_axi_hbm_arburst[19*2 +: 2]), + .AXI_19_ARID(m_axi_hbm_arid[19*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_19_ARLEN(m_axi_hbm_arlen[19*8 +: 8]), + .AXI_19_ARSIZE(m_axi_hbm_arsize[19*3 +: 3]), + .AXI_19_ARVALID(m_axi_hbm_arvalid[19 +: 1]), + .AXI_19_ARREADY(m_axi_hbm_arready[19 +: 1]), + .AXI_19_RDATA_PARITY(), + .AXI_19_RDATA(m_axi_hbm_rdata[19*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_19_RID(m_axi_hbm_rid[19 +: 1]), + .AXI_19_RLAST(m_axi_hbm_rlast[19 +: 1]), + .AXI_19_RRESP(m_axi_hbm_rresp[19*2 +: 2]), + .AXI_19_RVALID(m_axi_hbm_rvalid[19 +: 1]), + .AXI_19_RREADY(m_axi_hbm_rready[19 +: 1]), + .AXI_19_AWADDR(m_axi_hbm_awaddr[19*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_19_AWBURST(m_axi_hbm_awburst[19*2 +: 2]), + .AXI_19_AWID(m_axi_hbm_awid[19*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_19_AWLEN(m_axi_hbm_awlen[19*8 +: 8]), + .AXI_19_AWSIZE(m_axi_hbm_awsize[19*3 +: 3]), + .AXI_19_AWVALID(m_axi_hbm_awvalid[19 +: 1]), + .AXI_19_AWREADY(m_axi_hbm_awready[19 +: 1]), + .AXI_19_WDATA(m_axi_hbm_wdata[19*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_19_WLAST(m_axi_hbm_wlast[19 +: 1]), + .AXI_19_WSTRB(m_axi_hbm_wstrb[19*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_19_WDATA_PARITY(32'd0), + .AXI_19_WVALID(m_axi_hbm_wvalid[19 +: 1]), + .AXI_19_WREADY(m_axi_hbm_wready[19 +: 1]), + .AXI_19_BID(m_axi_hbm_bid[19*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_19_BRESP(m_axi_hbm_bresp[19*2 +: 2]), + .AXI_19_BVALID(m_axi_hbm_bvalid[19 +: 1]), + .AXI_19_BREADY(m_axi_hbm_bready[19 +: 1]), + + .AXI_20_ACLK(hbm_clk[20 +: 1]), + .AXI_20_ARESET_N(!hbm_rst[20 +: 1]), + + .AXI_20_ARADDR(m_axi_hbm_araddr[20*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_20_ARBURST(m_axi_hbm_arburst[20*2 +: 2]), + .AXI_20_ARID(m_axi_hbm_arid[20*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_20_ARLEN(m_axi_hbm_arlen[20*8 +: 8]), + .AXI_20_ARSIZE(m_axi_hbm_arsize[20*3 +: 3]), + .AXI_20_ARVALID(m_axi_hbm_arvalid[20 +: 1]), + .AXI_20_ARREADY(m_axi_hbm_arready[20 +: 1]), + .AXI_20_RDATA_PARITY(), + .AXI_20_RDATA(m_axi_hbm_rdata[20*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_20_RID(m_axi_hbm_rid[20 +: 1]), + .AXI_20_RLAST(m_axi_hbm_rlast[20 +: 1]), + .AXI_20_RRESP(m_axi_hbm_rresp[20*2 +: 2]), + .AXI_20_RVALID(m_axi_hbm_rvalid[20 +: 1]), + .AXI_20_RREADY(m_axi_hbm_rready[20 +: 1]), + .AXI_20_AWADDR(m_axi_hbm_awaddr[20*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_20_AWBURST(m_axi_hbm_awburst[20*2 +: 2]), + .AXI_20_AWID(m_axi_hbm_awid[20*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_20_AWLEN(m_axi_hbm_awlen[20*8 +: 8]), + .AXI_20_AWSIZE(m_axi_hbm_awsize[20*3 +: 3]), + .AXI_20_AWVALID(m_axi_hbm_awvalid[20 +: 1]), + .AXI_20_AWREADY(m_axi_hbm_awready[20 +: 1]), + .AXI_20_WDATA(m_axi_hbm_wdata[20*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_20_WLAST(m_axi_hbm_wlast[20 +: 1]), + .AXI_20_WSTRB(m_axi_hbm_wstrb[20*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_20_WDATA_PARITY(32'd0), + .AXI_20_WVALID(m_axi_hbm_wvalid[20 +: 1]), + .AXI_20_WREADY(m_axi_hbm_wready[20 +: 1]), + .AXI_20_BID(m_axi_hbm_bid[20*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_20_BRESP(m_axi_hbm_bresp[20*2 +: 2]), + .AXI_20_BVALID(m_axi_hbm_bvalid[20 +: 1]), + .AXI_20_BREADY(m_axi_hbm_bready[20 +: 1]), + + .AXI_21_ACLK(hbm_clk[21 +: 1]), + .AXI_21_ARESET_N(!hbm_rst[21 +: 1]), + + .AXI_21_ARADDR(m_axi_hbm_araddr[21*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_21_ARBURST(m_axi_hbm_arburst[21*2 +: 2]), + .AXI_21_ARID(m_axi_hbm_arid[21*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_21_ARLEN(m_axi_hbm_arlen[21*8 +: 8]), + .AXI_21_ARSIZE(m_axi_hbm_arsize[21*3 +: 3]), + .AXI_21_ARVALID(m_axi_hbm_arvalid[21 +: 1]), + .AXI_21_ARREADY(m_axi_hbm_arready[21 +: 1]), + .AXI_21_RDATA_PARITY(), + .AXI_21_RDATA(m_axi_hbm_rdata[21*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_21_RID(m_axi_hbm_rid[21 +: 1]), + .AXI_21_RLAST(m_axi_hbm_rlast[21 +: 1]), + .AXI_21_RRESP(m_axi_hbm_rresp[21*2 +: 2]), + .AXI_21_RVALID(m_axi_hbm_rvalid[21 +: 1]), + .AXI_21_RREADY(m_axi_hbm_rready[21 +: 1]), + .AXI_21_AWADDR(m_axi_hbm_awaddr[21*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_21_AWBURST(m_axi_hbm_awburst[21*2 +: 2]), + .AXI_21_AWID(m_axi_hbm_awid[21*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_21_AWLEN(m_axi_hbm_awlen[21*8 +: 8]), + .AXI_21_AWSIZE(m_axi_hbm_awsize[21*3 +: 3]), + .AXI_21_AWVALID(m_axi_hbm_awvalid[21 +: 1]), + .AXI_21_AWREADY(m_axi_hbm_awready[21 +: 1]), + .AXI_21_WDATA(m_axi_hbm_wdata[21*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_21_WLAST(m_axi_hbm_wlast[21 +: 1]), + .AXI_21_WSTRB(m_axi_hbm_wstrb[21*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_21_WDATA_PARITY(32'd0), + .AXI_21_WVALID(m_axi_hbm_wvalid[21 +: 1]), + .AXI_21_WREADY(m_axi_hbm_wready[21 +: 1]), + .AXI_21_BID(m_axi_hbm_bid[21*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_21_BRESP(m_axi_hbm_bresp[21*2 +: 2]), + .AXI_21_BVALID(m_axi_hbm_bvalid[21 +: 1]), + .AXI_21_BREADY(m_axi_hbm_bready[21 +: 1]), + + .AXI_22_ACLK(hbm_clk[22 +: 1]), + .AXI_22_ARESET_N(!hbm_rst[22 +: 1]), + + .AXI_22_ARADDR(m_axi_hbm_araddr[22*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_22_ARBURST(m_axi_hbm_arburst[22*2 +: 2]), + .AXI_22_ARID(m_axi_hbm_arid[22*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_22_ARLEN(m_axi_hbm_arlen[22*8 +: 8]), + .AXI_22_ARSIZE(m_axi_hbm_arsize[22*3 +: 3]), + .AXI_22_ARVALID(m_axi_hbm_arvalid[22 +: 1]), + .AXI_22_ARREADY(m_axi_hbm_arready[22 +: 1]), + .AXI_22_RDATA_PARITY(), + .AXI_22_RDATA(m_axi_hbm_rdata[22*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_22_RID(m_axi_hbm_rid[22 +: 1]), + .AXI_22_RLAST(m_axi_hbm_rlast[22 +: 1]), + .AXI_22_RRESP(m_axi_hbm_rresp[22*2 +: 2]), + .AXI_22_RVALID(m_axi_hbm_rvalid[22 +: 1]), + .AXI_22_RREADY(m_axi_hbm_rready[22 +: 1]), + .AXI_22_AWADDR(m_axi_hbm_awaddr[22*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_22_AWBURST(m_axi_hbm_awburst[22*2 +: 2]), + .AXI_22_AWID(m_axi_hbm_awid[22*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_22_AWLEN(m_axi_hbm_awlen[22*8 +: 8]), + .AXI_22_AWSIZE(m_axi_hbm_awsize[22*3 +: 3]), + .AXI_22_AWVALID(m_axi_hbm_awvalid[22 +: 1]), + .AXI_22_AWREADY(m_axi_hbm_awready[22 +: 1]), + .AXI_22_WDATA(m_axi_hbm_wdata[22*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_22_WLAST(m_axi_hbm_wlast[22 +: 1]), + .AXI_22_WSTRB(m_axi_hbm_wstrb[22*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_22_WDATA_PARITY(32'd0), + .AXI_22_WVALID(m_axi_hbm_wvalid[22 +: 1]), + .AXI_22_WREADY(m_axi_hbm_wready[22 +: 1]), + .AXI_22_BID(m_axi_hbm_bid[22*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_22_BRESP(m_axi_hbm_bresp[22*2 +: 2]), + .AXI_22_BVALID(m_axi_hbm_bvalid[22 +: 1]), + .AXI_22_BREADY(m_axi_hbm_bready[22 +: 1]), + + .AXI_23_ACLK(hbm_clk[23 +: 1]), + .AXI_23_ARESET_N(!hbm_rst[23 +: 1]), + + .AXI_23_ARADDR(m_axi_hbm_araddr[23*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_23_ARBURST(m_axi_hbm_arburst[23*2 +: 2]), + .AXI_23_ARID(m_axi_hbm_arid[23*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_23_ARLEN(m_axi_hbm_arlen[23*8 +: 8]), + .AXI_23_ARSIZE(m_axi_hbm_arsize[23*3 +: 3]), + .AXI_23_ARVALID(m_axi_hbm_arvalid[23 +: 1]), + .AXI_23_ARREADY(m_axi_hbm_arready[23 +: 1]), + .AXI_23_RDATA_PARITY(), + .AXI_23_RDATA(m_axi_hbm_rdata[23*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_23_RID(m_axi_hbm_rid[23 +: 1]), + .AXI_23_RLAST(m_axi_hbm_rlast[23 +: 1]), + .AXI_23_RRESP(m_axi_hbm_rresp[23*2 +: 2]), + .AXI_23_RVALID(m_axi_hbm_rvalid[23 +: 1]), + .AXI_23_RREADY(m_axi_hbm_rready[23 +: 1]), + .AXI_23_AWADDR(m_axi_hbm_awaddr[23*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_23_AWBURST(m_axi_hbm_awburst[23*2 +: 2]), + .AXI_23_AWID(m_axi_hbm_awid[23*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_23_AWLEN(m_axi_hbm_awlen[23*8 +: 8]), + .AXI_23_AWSIZE(m_axi_hbm_awsize[23*3 +: 3]), + .AXI_23_AWVALID(m_axi_hbm_awvalid[23 +: 1]), + .AXI_23_AWREADY(m_axi_hbm_awready[23 +: 1]), + .AXI_23_WDATA(m_axi_hbm_wdata[23*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_23_WLAST(m_axi_hbm_wlast[23 +: 1]), + .AXI_23_WSTRB(m_axi_hbm_wstrb[23*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_23_WDATA_PARITY(32'd0), + .AXI_23_WVALID(m_axi_hbm_wvalid[23 +: 1]), + .AXI_23_WREADY(m_axi_hbm_wready[23 +: 1]), + .AXI_23_BID(m_axi_hbm_bid[23*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_23_BRESP(m_axi_hbm_bresp[23*2 +: 2]), + .AXI_23_BVALID(m_axi_hbm_bvalid[23 +: 1]), + .AXI_23_BREADY(m_axi_hbm_bready[23 +: 1]), + + .AXI_24_ACLK(hbm_clk[24 +: 1]), + .AXI_24_ARESET_N(!hbm_rst[24 +: 1]), + + .AXI_24_ARADDR(m_axi_hbm_araddr[24*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_24_ARBURST(m_axi_hbm_arburst[24*2 +: 2]), + .AXI_24_ARID(m_axi_hbm_arid[24*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_24_ARLEN(m_axi_hbm_arlen[24*8 +: 8]), + .AXI_24_ARSIZE(m_axi_hbm_arsize[24*3 +: 3]), + .AXI_24_ARVALID(m_axi_hbm_arvalid[24 +: 1]), + .AXI_24_ARREADY(m_axi_hbm_arready[24 +: 1]), + .AXI_24_RDATA_PARITY(), + .AXI_24_RDATA(m_axi_hbm_rdata[24*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_24_RID(m_axi_hbm_rid[24 +: 1]), + .AXI_24_RLAST(m_axi_hbm_rlast[24 +: 1]), + .AXI_24_RRESP(m_axi_hbm_rresp[24*2 +: 2]), + .AXI_24_RVALID(m_axi_hbm_rvalid[24 +: 1]), + .AXI_24_RREADY(m_axi_hbm_rready[24 +: 1]), + .AXI_24_AWADDR(m_axi_hbm_awaddr[24*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_24_AWBURST(m_axi_hbm_awburst[24*2 +: 2]), + .AXI_24_AWID(m_axi_hbm_awid[24*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_24_AWLEN(m_axi_hbm_awlen[24*8 +: 8]), + .AXI_24_AWSIZE(m_axi_hbm_awsize[24*3 +: 3]), + .AXI_24_AWVALID(m_axi_hbm_awvalid[24 +: 1]), + .AXI_24_AWREADY(m_axi_hbm_awready[24 +: 1]), + .AXI_24_WDATA(m_axi_hbm_wdata[24*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_24_WLAST(m_axi_hbm_wlast[24 +: 1]), + .AXI_24_WSTRB(m_axi_hbm_wstrb[24*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_24_WDATA_PARITY(32'd0), + .AXI_24_WVALID(m_axi_hbm_wvalid[24 +: 1]), + .AXI_24_WREADY(m_axi_hbm_wready[24 +: 1]), + .AXI_24_BID(m_axi_hbm_bid[24*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_24_BRESP(m_axi_hbm_bresp[24*2 +: 2]), + .AXI_24_BVALID(m_axi_hbm_bvalid[24 +: 1]), + .AXI_24_BREADY(m_axi_hbm_bready[24 +: 1]), + + .AXI_25_ACLK(hbm_clk[25 +: 1]), + .AXI_25_ARESET_N(!hbm_rst[25 +: 1]), + + .AXI_25_ARADDR(m_axi_hbm_araddr[25*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_25_ARBURST(m_axi_hbm_arburst[25*2 +: 2]), + .AXI_25_ARID(m_axi_hbm_arid[25*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_25_ARLEN(m_axi_hbm_arlen[25*8 +: 8]), + .AXI_25_ARSIZE(m_axi_hbm_arsize[25*3 +: 3]), + .AXI_25_ARVALID(m_axi_hbm_arvalid[25 +: 1]), + .AXI_25_ARREADY(m_axi_hbm_arready[25 +: 1]), + .AXI_25_RDATA_PARITY(), + .AXI_25_RDATA(m_axi_hbm_rdata[25*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_25_RID(m_axi_hbm_rid[25 +: 1]), + .AXI_25_RLAST(m_axi_hbm_rlast[25 +: 1]), + .AXI_25_RRESP(m_axi_hbm_rresp[25*2 +: 2]), + .AXI_25_RVALID(m_axi_hbm_rvalid[25 +: 1]), + .AXI_25_RREADY(m_axi_hbm_rready[25 +: 1]), + .AXI_25_AWADDR(m_axi_hbm_awaddr[25*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_25_AWBURST(m_axi_hbm_awburst[25*2 +: 2]), + .AXI_25_AWID(m_axi_hbm_awid[25*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_25_AWLEN(m_axi_hbm_awlen[25*8 +: 8]), + .AXI_25_AWSIZE(m_axi_hbm_awsize[25*3 +: 3]), + .AXI_25_AWVALID(m_axi_hbm_awvalid[25 +: 1]), + .AXI_25_AWREADY(m_axi_hbm_awready[25 +: 1]), + .AXI_25_WDATA(m_axi_hbm_wdata[25*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_25_WLAST(m_axi_hbm_wlast[25 +: 1]), + .AXI_25_WSTRB(m_axi_hbm_wstrb[25*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_25_WDATA_PARITY(32'd0), + .AXI_25_WVALID(m_axi_hbm_wvalid[25 +: 1]), + .AXI_25_WREADY(m_axi_hbm_wready[25 +: 1]), + .AXI_25_BID(m_axi_hbm_bid[25*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_25_BRESP(m_axi_hbm_bresp[25*2 +: 2]), + .AXI_25_BVALID(m_axi_hbm_bvalid[25 +: 1]), + .AXI_25_BREADY(m_axi_hbm_bready[25 +: 1]), + + .AXI_26_ACLK(hbm_clk[26 +: 1]), + .AXI_26_ARESET_N(!hbm_rst[26 +: 1]), + + .AXI_26_ARADDR(m_axi_hbm_araddr[26*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_26_ARBURST(m_axi_hbm_arburst[26*2 +: 2]), + .AXI_26_ARID(m_axi_hbm_arid[26*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_26_ARLEN(m_axi_hbm_arlen[26*8 +: 8]), + .AXI_26_ARSIZE(m_axi_hbm_arsize[26*3 +: 3]), + .AXI_26_ARVALID(m_axi_hbm_arvalid[26 +: 1]), + .AXI_26_ARREADY(m_axi_hbm_arready[26 +: 1]), + .AXI_26_RDATA_PARITY(), + .AXI_26_RDATA(m_axi_hbm_rdata[26*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_26_RID(m_axi_hbm_rid[26 +: 1]), + .AXI_26_RLAST(m_axi_hbm_rlast[26 +: 1]), + .AXI_26_RRESP(m_axi_hbm_rresp[26*2 +: 2]), + .AXI_26_RVALID(m_axi_hbm_rvalid[26 +: 1]), + .AXI_26_RREADY(m_axi_hbm_rready[26 +: 1]), + .AXI_26_AWADDR(m_axi_hbm_awaddr[26*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_26_AWBURST(m_axi_hbm_awburst[26*2 +: 2]), + .AXI_26_AWID(m_axi_hbm_awid[26*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_26_AWLEN(m_axi_hbm_awlen[26*8 +: 8]), + .AXI_26_AWSIZE(m_axi_hbm_awsize[26*3 +: 3]), + .AXI_26_AWVALID(m_axi_hbm_awvalid[26 +: 1]), + .AXI_26_AWREADY(m_axi_hbm_awready[26 +: 1]), + .AXI_26_WDATA(m_axi_hbm_wdata[26*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_26_WLAST(m_axi_hbm_wlast[26 +: 1]), + .AXI_26_WSTRB(m_axi_hbm_wstrb[26*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_26_WDATA_PARITY(32'd0), + .AXI_26_WVALID(m_axi_hbm_wvalid[26 +: 1]), + .AXI_26_WREADY(m_axi_hbm_wready[26 +: 1]), + .AXI_26_BID(m_axi_hbm_bid[26*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_26_BRESP(m_axi_hbm_bresp[26*2 +: 2]), + .AXI_26_BVALID(m_axi_hbm_bvalid[26 +: 1]), + .AXI_26_BREADY(m_axi_hbm_bready[26 +: 1]), + + .AXI_27_ACLK(hbm_clk[27 +: 1]), + .AXI_27_ARESET_N(!hbm_rst[27 +: 1]), + + .AXI_27_ARADDR(m_axi_hbm_araddr[27*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_27_ARBURST(m_axi_hbm_arburst[27*2 +: 2]), + .AXI_27_ARID(m_axi_hbm_arid[27*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_27_ARLEN(m_axi_hbm_arlen[27*8 +: 8]), + .AXI_27_ARSIZE(m_axi_hbm_arsize[27*3 +: 3]), + .AXI_27_ARVALID(m_axi_hbm_arvalid[27 +: 1]), + .AXI_27_ARREADY(m_axi_hbm_arready[27 +: 1]), + .AXI_27_RDATA_PARITY(), + .AXI_27_RDATA(m_axi_hbm_rdata[27*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_27_RID(m_axi_hbm_rid[27 +: 1]), + .AXI_27_RLAST(m_axi_hbm_rlast[27 +: 1]), + .AXI_27_RRESP(m_axi_hbm_rresp[27*2 +: 2]), + .AXI_27_RVALID(m_axi_hbm_rvalid[27 +: 1]), + .AXI_27_RREADY(m_axi_hbm_rready[27 +: 1]), + .AXI_27_AWADDR(m_axi_hbm_awaddr[27*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_27_AWBURST(m_axi_hbm_awburst[27*2 +: 2]), + .AXI_27_AWID(m_axi_hbm_awid[27*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_27_AWLEN(m_axi_hbm_awlen[27*8 +: 8]), + .AXI_27_AWSIZE(m_axi_hbm_awsize[27*3 +: 3]), + .AXI_27_AWVALID(m_axi_hbm_awvalid[27 +: 1]), + .AXI_27_AWREADY(m_axi_hbm_awready[27 +: 1]), + .AXI_27_WDATA(m_axi_hbm_wdata[27*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_27_WLAST(m_axi_hbm_wlast[27 +: 1]), + .AXI_27_WSTRB(m_axi_hbm_wstrb[27*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_27_WDATA_PARITY(32'd0), + .AXI_27_WVALID(m_axi_hbm_wvalid[27 +: 1]), + .AXI_27_WREADY(m_axi_hbm_wready[27 +: 1]), + .AXI_27_BID(m_axi_hbm_bid[27*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_27_BRESP(m_axi_hbm_bresp[27*2 +: 2]), + .AXI_27_BVALID(m_axi_hbm_bvalid[27 +: 1]), + .AXI_27_BREADY(m_axi_hbm_bready[27 +: 1]), + + .AXI_28_ACLK(hbm_clk[28 +: 1]), + .AXI_28_ARESET_N(!hbm_rst[28 +: 1]), + + .AXI_28_ARADDR(m_axi_hbm_araddr[28*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_28_ARBURST(m_axi_hbm_arburst[28*2 +: 2]), + .AXI_28_ARID(m_axi_hbm_arid[28*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_28_ARLEN(m_axi_hbm_arlen[28*8 +: 8]), + .AXI_28_ARSIZE(m_axi_hbm_arsize[28*3 +: 3]), + .AXI_28_ARVALID(m_axi_hbm_arvalid[28 +: 1]), + .AXI_28_ARREADY(m_axi_hbm_arready[28 +: 1]), + .AXI_28_RDATA_PARITY(), + .AXI_28_RDATA(m_axi_hbm_rdata[28*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_28_RID(m_axi_hbm_rid[28 +: 1]), + .AXI_28_RLAST(m_axi_hbm_rlast[28 +: 1]), + .AXI_28_RRESP(m_axi_hbm_rresp[28*2 +: 2]), + .AXI_28_RVALID(m_axi_hbm_rvalid[28 +: 1]), + .AXI_28_RREADY(m_axi_hbm_rready[28 +: 1]), + .AXI_28_AWADDR(m_axi_hbm_awaddr[28*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_28_AWBURST(m_axi_hbm_awburst[28*2 +: 2]), + .AXI_28_AWID(m_axi_hbm_awid[28*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_28_AWLEN(m_axi_hbm_awlen[28*8 +: 8]), + .AXI_28_AWSIZE(m_axi_hbm_awsize[28*3 +: 3]), + .AXI_28_AWVALID(m_axi_hbm_awvalid[28 +: 1]), + .AXI_28_AWREADY(m_axi_hbm_awready[28 +: 1]), + .AXI_28_WDATA(m_axi_hbm_wdata[28*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_28_WLAST(m_axi_hbm_wlast[28 +: 1]), + .AXI_28_WSTRB(m_axi_hbm_wstrb[28*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_28_WDATA_PARITY(32'd0), + .AXI_28_WVALID(m_axi_hbm_wvalid[28 +: 1]), + .AXI_28_WREADY(m_axi_hbm_wready[28 +: 1]), + .AXI_28_BID(m_axi_hbm_bid[28*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_28_BRESP(m_axi_hbm_bresp[28*2 +: 2]), + .AXI_28_BVALID(m_axi_hbm_bvalid[28 +: 1]), + .AXI_28_BREADY(m_axi_hbm_bready[28 +: 1]), + + .AXI_29_ACLK(hbm_clk[29 +: 1]), + .AXI_29_ARESET_N(!hbm_rst[29 +: 1]), + + .AXI_29_ARADDR(m_axi_hbm_araddr[29*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_29_ARBURST(m_axi_hbm_arburst[29*2 +: 2]), + .AXI_29_ARID(m_axi_hbm_arid[29*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_29_ARLEN(m_axi_hbm_arlen[29*8 +: 8]), + .AXI_29_ARSIZE(m_axi_hbm_arsize[29*3 +: 3]), + .AXI_29_ARVALID(m_axi_hbm_arvalid[29 +: 1]), + .AXI_29_ARREADY(m_axi_hbm_arready[29 +: 1]), + .AXI_29_RDATA_PARITY(), + .AXI_29_RDATA(m_axi_hbm_rdata[29*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_29_RID(m_axi_hbm_rid[29 +: 1]), + .AXI_29_RLAST(m_axi_hbm_rlast[29 +: 1]), + .AXI_29_RRESP(m_axi_hbm_rresp[29*2 +: 2]), + .AXI_29_RVALID(m_axi_hbm_rvalid[29 +: 1]), + .AXI_29_RREADY(m_axi_hbm_rready[29 +: 1]), + .AXI_29_AWADDR(m_axi_hbm_awaddr[29*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_29_AWBURST(m_axi_hbm_awburst[29*2 +: 2]), + .AXI_29_AWID(m_axi_hbm_awid[29*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_29_AWLEN(m_axi_hbm_awlen[29*8 +: 8]), + .AXI_29_AWSIZE(m_axi_hbm_awsize[29*3 +: 3]), + .AXI_29_AWVALID(m_axi_hbm_awvalid[29 +: 1]), + .AXI_29_AWREADY(m_axi_hbm_awready[29 +: 1]), + .AXI_29_WDATA(m_axi_hbm_wdata[29*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_29_WLAST(m_axi_hbm_wlast[29 +: 1]), + .AXI_29_WSTRB(m_axi_hbm_wstrb[29*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_29_WDATA_PARITY(32'd0), + .AXI_29_WVALID(m_axi_hbm_wvalid[29 +: 1]), + .AXI_29_WREADY(m_axi_hbm_wready[29 +: 1]), + .AXI_29_BID(m_axi_hbm_bid[29*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_29_BRESP(m_axi_hbm_bresp[29*2 +: 2]), + .AXI_29_BVALID(m_axi_hbm_bvalid[29 +: 1]), + .AXI_29_BREADY(m_axi_hbm_bready[29 +: 1]), + + .AXI_30_ACLK(hbm_clk[30 +: 1]), + .AXI_30_ARESET_N(!hbm_rst[30 +: 1]), + + .AXI_30_ARADDR(m_axi_hbm_araddr[30*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_30_ARBURST(m_axi_hbm_arburst[30*2 +: 2]), + .AXI_30_ARID(m_axi_hbm_arid[30*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_30_ARLEN(m_axi_hbm_arlen[30*8 +: 8]), + .AXI_30_ARSIZE(m_axi_hbm_arsize[30*3 +: 3]), + .AXI_30_ARVALID(m_axi_hbm_arvalid[30 +: 1]), + .AXI_30_ARREADY(m_axi_hbm_arready[30 +: 1]), + .AXI_30_RDATA_PARITY(), + .AXI_30_RDATA(m_axi_hbm_rdata[30*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_30_RID(m_axi_hbm_rid[30 +: 1]), + .AXI_30_RLAST(m_axi_hbm_rlast[30 +: 1]), + .AXI_30_RRESP(m_axi_hbm_rresp[30*2 +: 2]), + .AXI_30_RVALID(m_axi_hbm_rvalid[30 +: 1]), + .AXI_30_RREADY(m_axi_hbm_rready[30 +: 1]), + .AXI_30_AWADDR(m_axi_hbm_awaddr[30*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_30_AWBURST(m_axi_hbm_awburst[30*2 +: 2]), + .AXI_30_AWID(m_axi_hbm_awid[30*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_30_AWLEN(m_axi_hbm_awlen[30*8 +: 8]), + .AXI_30_AWSIZE(m_axi_hbm_awsize[30*3 +: 3]), + .AXI_30_AWVALID(m_axi_hbm_awvalid[30 +: 1]), + .AXI_30_AWREADY(m_axi_hbm_awready[30 +: 1]), + .AXI_30_WDATA(m_axi_hbm_wdata[30*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_30_WLAST(m_axi_hbm_wlast[30 +: 1]), + .AXI_30_WSTRB(m_axi_hbm_wstrb[30*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_30_WDATA_PARITY(32'd0), + .AXI_30_WVALID(m_axi_hbm_wvalid[30 +: 1]), + .AXI_30_WREADY(m_axi_hbm_wready[30 +: 1]), + .AXI_30_BID(m_axi_hbm_bid[30*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_30_BRESP(m_axi_hbm_bresp[30*2 +: 2]), + .AXI_30_BVALID(m_axi_hbm_bvalid[30 +: 1]), + .AXI_30_BREADY(m_axi_hbm_bready[30 +: 1]), + + .AXI_31_ACLK(hbm_clk[31 +: 1]), + .AXI_31_ARESET_N(!hbm_rst[31 +: 1]), + + .AXI_31_ARADDR(m_axi_hbm_araddr[31*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_31_ARBURST(m_axi_hbm_arburst[31*2 +: 2]), + .AXI_31_ARID(m_axi_hbm_arid[31*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_31_ARLEN(m_axi_hbm_arlen[31*8 +: 8]), + .AXI_31_ARSIZE(m_axi_hbm_arsize[31*3 +: 3]), + .AXI_31_ARVALID(m_axi_hbm_arvalid[31 +: 1]), + .AXI_31_ARREADY(m_axi_hbm_arready[31 +: 1]), + .AXI_31_RDATA_PARITY(), + .AXI_31_RDATA(m_axi_hbm_rdata[31*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_31_RID(m_axi_hbm_rid[31 +: 1]), + .AXI_31_RLAST(m_axi_hbm_rlast[31 +: 1]), + .AXI_31_RRESP(m_axi_hbm_rresp[31*2 +: 2]), + .AXI_31_RVALID(m_axi_hbm_rvalid[31 +: 1]), + .AXI_31_RREADY(m_axi_hbm_rready[31 +: 1]), + .AXI_31_AWADDR(m_axi_hbm_awaddr[31*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_31_AWBURST(m_axi_hbm_awburst[31*2 +: 2]), + .AXI_31_AWID(m_axi_hbm_awid[31*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_31_AWLEN(m_axi_hbm_awlen[31*8 +: 8]), + .AXI_31_AWSIZE(m_axi_hbm_awsize[31*3 +: 3]), + .AXI_31_AWVALID(m_axi_hbm_awvalid[31 +: 1]), + .AXI_31_AWREADY(m_axi_hbm_awready[31 +: 1]), + .AXI_31_WDATA(m_axi_hbm_wdata[31*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_31_WLAST(m_axi_hbm_wlast[31 +: 1]), + .AXI_31_WSTRB(m_axi_hbm_wstrb[31*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_31_WDATA_PARITY(32'd0), + .AXI_31_WVALID(m_axi_hbm_wvalid[31 +: 1]), + .AXI_31_WREADY(m_axi_hbm_wready[31 +: 1]), + .AXI_31_BID(m_axi_hbm_bid[31*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_31_BRESP(m_axi_hbm_bresp[31*2 +: 2]), + .AXI_31_BVALID(m_axi_hbm_bvalid[31 +: 1]), + .AXI_31_BREADY(m_axi_hbm_bready[31 +: 1]), + + .DRAM_0_STAT_CATTRIP(hbm_cattrip_1), + .DRAM_0_STAT_TEMP(hbm_temp_1), + .DRAM_1_STAT_CATTRIP(hbm_cattrip_2), + .DRAM_1_STAT_TEMP(hbm_temp_2) +); + +assign hbm_status = {HBM_CH{1'b1}}; + +end else begin + +assign hbm_clk = 0; +assign hbm_rst = 0; + +assign m_axi_hbm_awready = 0; +assign m_axi_hbm_wready = 0; +assign m_axi_hbm_bid = 0; +assign m_axi_hbm_bresp = 0; +assign m_axi_hbm_bvalid = 0; +assign m_axi_hbm_arready = 0; +assign m_axi_hbm_rid = 0; +assign m_axi_hbm_rdata = 0; +assign m_axi_hbm_rresp = 0; +assign m_axi_hbm_rlast = 0; +assign m_axi_hbm_rvalid = 0; + +assign hbm_status = 0; + +end + +endgenerate + fpga_core #( // FW and board IDs .FPGA_ID(FPGA_ID), @@ -1860,6 +3572,24 @@ fpga_core #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + .HBM_CH(HBM_CH), + .HBM_ENABLE(HBM_ENABLE), + .HBM_GROUP_SIZE(HBM_GROUP_SIZE), + .AXI_HBM_DATA_WIDTH(AXI_HBM_DATA_WIDTH), + .AXI_HBM_ADDR_WIDTH(AXI_HBM_ADDR_WIDTH), + .AXI_HBM_STRB_WIDTH(AXI_HBM_STRB_WIDTH), + .AXI_HBM_ID_WIDTH(AXI_HBM_ID_WIDTH), + .AXI_HBM_MAX_BURST_LEN(AXI_HBM_MAX_BURST_LEN), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -2069,6 +3799,97 @@ core_inst ( .qsfp1_rx_ptp_time(qsfp1_rx_ptp_time_int), .qsfp1_rx_status(qsfp1_rx_status), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + + /* + * HBM + */ + .hbm_clk(hbm_clk), + .hbm_rst(hbm_rst), + .m_axi_hbm_awid(m_axi_hbm_awid), + .m_axi_hbm_awaddr(m_axi_hbm_awaddr), + .m_axi_hbm_awlen(m_axi_hbm_awlen), + .m_axi_hbm_awsize(m_axi_hbm_awsize), + .m_axi_hbm_awburst(m_axi_hbm_awburst), + .m_axi_hbm_awlock(m_axi_hbm_awlock), + .m_axi_hbm_awcache(m_axi_hbm_awcache), + .m_axi_hbm_awprot(m_axi_hbm_awprot), + .m_axi_hbm_awqos(m_axi_hbm_awqos), + .m_axi_hbm_awvalid(m_axi_hbm_awvalid), + .m_axi_hbm_awready(m_axi_hbm_awready), + .m_axi_hbm_wdata(m_axi_hbm_wdata), + .m_axi_hbm_wstrb(m_axi_hbm_wstrb), + .m_axi_hbm_wlast(m_axi_hbm_wlast), + .m_axi_hbm_wvalid(m_axi_hbm_wvalid), + .m_axi_hbm_wready(m_axi_hbm_wready), + .m_axi_hbm_bid(m_axi_hbm_bid), + .m_axi_hbm_bresp(m_axi_hbm_bresp), + .m_axi_hbm_bvalid(m_axi_hbm_bvalid), + .m_axi_hbm_bready(m_axi_hbm_bready), + .m_axi_hbm_arid(m_axi_hbm_arid), + .m_axi_hbm_araddr(m_axi_hbm_araddr), + .m_axi_hbm_arlen(m_axi_hbm_arlen), + .m_axi_hbm_arsize(m_axi_hbm_arsize), + .m_axi_hbm_arburst(m_axi_hbm_arburst), + .m_axi_hbm_arlock(m_axi_hbm_arlock), + .m_axi_hbm_arcache(m_axi_hbm_arcache), + .m_axi_hbm_arprot(m_axi_hbm_arprot), + .m_axi_hbm_arqos(m_axi_hbm_arqos), + .m_axi_hbm_arvalid(m_axi_hbm_arvalid), + .m_axi_hbm_arready(m_axi_hbm_arready), + .m_axi_hbm_rid(m_axi_hbm_rid), + .m_axi_hbm_rdata(m_axi_hbm_rdata), + .m_axi_hbm_rresp(m_axi_hbm_rresp), + .m_axi_hbm_rlast(m_axi_hbm_rlast), + .m_axi_hbm_rvalid(m_axi_hbm_rvalid), + .m_axi_hbm_rready(m_axi_hbm_rready), + + .hbm_status(hbm_status), + /* * QSPI flash */ diff --git a/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v index 20b0f3cc0..e7b2aecc6 100644 --- a/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v @@ -115,6 +115,24 @@ module fpga_core # parameter TX_RAM_SIZE = 131072, parameter RX_RAM_SIZE = 131072, + // RAM configuration + parameter DDR_CH = 2, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 34, + parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + parameter HBM_CH = 32, + parameter HBM_ENABLE = 1, + parameter HBM_GROUP_SIZE = 32, + parameter AXI_HBM_DATA_WIDTH = 256, + parameter AXI_HBM_ADDR_WIDTH = 33, + parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8), + parameter AXI_HBM_ID_WIDTH = 6, + parameter AXI_HBM_MAX_BURST_LEN = 256, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -336,6 +354,98 @@ module fpga_core # input wire qsfp1_rx_status, + /* + * DDR + */ + input wire [DDR_CH-1:0] ddr_clk, + input wire [DDR_CH-1:0] ddr_rst, + + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, + output wire [DDR_CH-1:0] m_axi_ddr_awlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, + output wire [DDR_CH-1:0] m_axi_ddr_awvalid, + input wire [DDR_CH-1:0] m_axi_ddr_awready, + output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, + output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, + output wire [DDR_CH-1:0] m_axi_ddr_wlast, + output wire [DDR_CH-1:0] m_axi_ddr_wvalid, + input wire [DDR_CH-1:0] m_axi_ddr_wready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, + input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, + input wire [DDR_CH-1:0] m_axi_ddr_bvalid, + output wire [DDR_CH-1:0] m_axi_ddr_bready, + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, + output wire [DDR_CH-1:0] m_axi_ddr_arlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, + output wire [DDR_CH-1:0] m_axi_ddr_arvalid, + input wire [DDR_CH-1:0] m_axi_ddr_arready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, + input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, + input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, + input wire [DDR_CH-1:0] m_axi_ddr_rlast, + input wire [DDR_CH-1:0] m_axi_ddr_rvalid, + output wire [DDR_CH-1:0] m_axi_ddr_rready, + + input wire [DDR_CH-1:0] ddr_status, + + /* + * HBM + */ + input wire [HBM_CH-1:0] hbm_clk, + input wire [HBM_CH-1:0] hbm_rst, + + output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_awid, + output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_awaddr, + output wire [HBM_CH*8-1:0] m_axi_hbm_awlen, + output wire [HBM_CH*3-1:0] m_axi_hbm_awsize, + output wire [HBM_CH*2-1:0] m_axi_hbm_awburst, + output wire [HBM_CH-1:0] m_axi_hbm_awlock, + output wire [HBM_CH*4-1:0] m_axi_hbm_awcache, + output wire [HBM_CH*3-1:0] m_axi_hbm_awprot, + output wire [HBM_CH*4-1:0] m_axi_hbm_awqos, + output wire [HBM_CH-1:0] m_axi_hbm_awvalid, + input wire [HBM_CH-1:0] m_axi_hbm_awready, + output wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_wdata, + output wire [HBM_CH*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_wstrb, + output wire [HBM_CH-1:0] m_axi_hbm_wlast, + output wire [HBM_CH-1:0] m_axi_hbm_wvalid, + input wire [HBM_CH-1:0] m_axi_hbm_wready, + input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_bid, + input wire [HBM_CH*2-1:0] m_axi_hbm_bresp, + input wire [HBM_CH-1:0] m_axi_hbm_bvalid, + output wire [HBM_CH-1:0] m_axi_hbm_bready, + output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_arid, + output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_araddr, + output wire [HBM_CH*8-1:0] m_axi_hbm_arlen, + output wire [HBM_CH*3-1:0] m_axi_hbm_arsize, + output wire [HBM_CH*2-1:0] m_axi_hbm_arburst, + output wire [HBM_CH-1:0] m_axi_hbm_arlock, + output wire [HBM_CH*4-1:0] m_axi_hbm_arcache, + output wire [HBM_CH*3-1:0] m_axi_hbm_arprot, + output wire [HBM_CH*4-1:0] m_axi_hbm_arqos, + output wire [HBM_CH-1:0] m_axi_hbm_arvalid, + input wire [HBM_CH-1:0] m_axi_hbm_arready, + input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_rid, + input wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_rdata, + input wire [HBM_CH*2-1:0] m_axi_hbm_rresp, + input wire [HBM_CH-1:0] m_axi_hbm_rlast, + input wire [HBM_CH-1:0] m_axi_hbm_rvalid, + output wire [HBM_CH-1:0] m_axi_hbm_rready, + + input wire [HBM_CH-1:0] hbm_status, + /* * QSPI flash */ @@ -792,6 +902,40 @@ mqnic_core_pcie_us #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .DDR_GROUP_SIZE(1), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_AWUSER_ENABLE(0), + .AXI_DDR_WUSER_ENABLE(0), + .AXI_DDR_BUSER_ENABLE(0), + .AXI_DDR_ARUSER_ENABLE(0), + .AXI_DDR_RUSER_ENABLE(0), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + .AXI_DDR_FIXED_BURST(0), + .AXI_DDR_WRAP_BURST(1), + .HBM_CH(HBM_CH), + .HBM_ENABLE(HBM_ENABLE), + .HBM_GROUP_SIZE(HBM_GROUP_SIZE), + .AXI_HBM_DATA_WIDTH(AXI_HBM_DATA_WIDTH), + .AXI_HBM_ADDR_WIDTH(AXI_HBM_ADDR_WIDTH), + .AXI_HBM_STRB_WIDTH(AXI_HBM_STRB_WIDTH), + .AXI_HBM_ID_WIDTH(AXI_HBM_ID_WIDTH), + .AXI_HBM_AWUSER_ENABLE(0), + .AXI_HBM_WUSER_ENABLE(0), + .AXI_HBM_BUSER_ENABLE(0), + .AXI_HBM_ARUSER_ENABLE(0), + .AXI_HBM_RUSER_ENABLE(0), + .AXI_HBM_MAX_BURST_LEN(AXI_HBM_MAX_BURST_LEN), + .AXI_HBM_NARROW_BURST(0), + .AXI_HBM_FIXED_BURST(0), + .AXI_HBM_WRAP_BURST(1), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1069,6 +1213,108 @@ core_inst ( .eth_rx_status(eth_rx_status), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awuser(), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wuser(), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_buser(0), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_aruser(), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_ruser(0), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + + /* + * HBM + */ + .hbm_clk(hbm_clk), + .hbm_rst(hbm_rst), + + .m_axi_hbm_awid(m_axi_hbm_awid), + .m_axi_hbm_awaddr(m_axi_hbm_awaddr), + .m_axi_hbm_awlen(m_axi_hbm_awlen), + .m_axi_hbm_awsize(m_axi_hbm_awsize), + .m_axi_hbm_awburst(m_axi_hbm_awburst), + .m_axi_hbm_awlock(m_axi_hbm_awlock), + .m_axi_hbm_awcache(m_axi_hbm_awcache), + .m_axi_hbm_awprot(m_axi_hbm_awprot), + .m_axi_hbm_awqos(m_axi_hbm_awqos), + .m_axi_hbm_awuser(), + .m_axi_hbm_awvalid(m_axi_hbm_awvalid), + .m_axi_hbm_awready(m_axi_hbm_awready), + .m_axi_hbm_wdata(m_axi_hbm_wdata), + .m_axi_hbm_wstrb(m_axi_hbm_wstrb), + .m_axi_hbm_wlast(m_axi_hbm_wlast), + .m_axi_hbm_wuser(), + .m_axi_hbm_wvalid(m_axi_hbm_wvalid), + .m_axi_hbm_wready(m_axi_hbm_wready), + .m_axi_hbm_bid(m_axi_hbm_bid), + .m_axi_hbm_bresp(m_axi_hbm_bresp), + .m_axi_hbm_buser(0), + .m_axi_hbm_bvalid(m_axi_hbm_bvalid), + .m_axi_hbm_bready(m_axi_hbm_bready), + .m_axi_hbm_arid(m_axi_hbm_arid), + .m_axi_hbm_araddr(m_axi_hbm_araddr), + .m_axi_hbm_arlen(m_axi_hbm_arlen), + .m_axi_hbm_arsize(m_axi_hbm_arsize), + .m_axi_hbm_arburst(m_axi_hbm_arburst), + .m_axi_hbm_arlock(m_axi_hbm_arlock), + .m_axi_hbm_arcache(m_axi_hbm_arcache), + .m_axi_hbm_arprot(m_axi_hbm_arprot), + .m_axi_hbm_arqos(m_axi_hbm_arqos), + .m_axi_hbm_aruser(), + .m_axi_hbm_arvalid(m_axi_hbm_arvalid), + .m_axi_hbm_arready(m_axi_hbm_arready), + .m_axi_hbm_rid(m_axi_hbm_rid), + .m_axi_hbm_rdata(m_axi_hbm_rdata), + .m_axi_hbm_rresp(m_axi_hbm_rresp), + .m_axi_hbm_rlast(m_axi_hbm_rlast), + .m_axi_hbm_ruser(0), + .m_axi_hbm_rvalid(m_axi_hbm_rvalid), + .m_axi_hbm_rready(m_axi_hbm_rready), + + .hbm_status(hbm_status), + /* * Statistics input */ diff --git a/fpga/mqnic/AU280/fpga_25g/README.md b/fpga/mqnic/AU280/fpga_25g/README.md index ef38c59c5..adf4580a5 100644 --- a/fpga/mqnic/AU280/fpga_25g/README.md +++ b/fpga/mqnic/AU280/fpga_25g/README.md @@ -6,6 +6,8 @@ This design targets the Xilinx Alveo U280 FPGA board. * FPGA: xcu280-fsvh2892-2L-e * PHY: 10G BASE-R PHY IP core and internal GTY transceivers +* RAM: 32 GB DDR4 2400 (2x 2G x72 DIMM) +* HBM: 8GB HBM2 ## How to build diff --git a/fpga/mqnic/AU280/fpga_25g/fpga.xdc b/fpga/mqnic/AU280/fpga_25g/fpga.xdc index a63b89942..ae028af3a 100644 --- a/fpga/mqnic/AU280/fpga_25g/fpga.xdc +++ b/fpga/mqnic/AU280/fpga_25g/fpga.xdc @@ -18,14 +18,14 @@ set_operating_conditions -design_power_budget 160 # System clocks # 100 MHz (DDR4) -#set_property -dict {LOC BJ43 IOSTANDARD LVDS} [get_ports clk_100mhz_0_p] -#set_property -dict {LOC BJ44 IOSTANDARD LVDS} [get_ports clk_100mhz_0_n] -#create_clock -period 10 -name clk_100mhz_0 [get_ports clk_100mhz_0_p] +set_property -dict {LOC BJ43 IOSTANDARD LVDS} [get_ports clk_100mhz_0_p] +set_property -dict {LOC BJ44 IOSTANDARD LVDS} [get_ports clk_100mhz_0_n] +create_clock -period 10 -name clk_100mhz_0 [get_ports clk_100mhz_0_p] # 100 MHz (DDR4) -#set_property -dict {LOC BH6 IOSTANDARD LVDS} [get_ports clk_100mhz_1_p] -#set_property -dict {LOC BJ6 IOSTANDARD LVDS} [get_ports clk_100mhz_1_n] -#create_clock -period 10 -name clk_100mhz_1 [get_ports clk_100mhz_1_p] +set_property -dict {LOC BH6 IOSTANDARD LVDS} [get_ports clk_100mhz_1_p] +set_property -dict {LOC BJ6 IOSTANDARD LVDS} [get_ports clk_100mhz_1_n] +create_clock -period 10 -name clk_100mhz_1 [get_ports clk_100mhz_1_p] # 100 MHz #set_property -dict {LOC G31 IOSTANDARD LVDS} [get_ports clk_100mhz_2_p] @@ -225,3 +225,283 @@ create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_1_p] set_false_path -from [get_ports {pcie_reset_n}] set_input_delay 0 [get_ports {pcie_reset_n}] + +# DDR4 C0 +set_property -dict {LOC BF46 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}] +set_property -dict {LOC BG43 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}] +set_property -dict {LOC BK45 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}] +set_property -dict {LOC BF42 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}] +set_property -dict {LOC BL45 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}] +set_property -dict {LOC BF43 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}] +set_property -dict {LOC BG42 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}] +set_property -dict {LOC BL43 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}] +set_property -dict {LOC BK43 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}] +set_property -dict {LOC BM42 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}] +set_property -dict {LOC BG45 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}] +set_property -dict {LOC BD41 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}] +set_property -dict {LOC BL42 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}] +set_property -dict {LOC BE44 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}] +set_property -dict {LOC BE43 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}] +set_property -dict {LOC BL46 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}] +set_property -dict {LOC BH44 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}] +set_property -dict {LOC BH45 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}] +set_property -dict {LOC BM47 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}] +set_property -dict {LOC BF41 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}] +set_property -dict {LOC BE41 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}] +set_property -dict {LOC BH46 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c0_ck_t}] +set_property -dict {LOC BJ46 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c0_ck_c}] +set_property -dict {LOC BH42 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke}] +set_property -dict {LOC BK46 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n}] +set_property -dict {LOC BH41 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}] +set_property -dict {LOC BG44 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt}] +set_property -dict {LOC BF45 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}] +set_property -dict {LOC BG33 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_c0_reset_n}] + +set_property -dict {LOC BN32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}] +set_property -dict {LOC BP32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}] +set_property -dict {LOC BL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}] +set_property -dict {LOC BM30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}] +set_property -dict {LOC BP29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}] +set_property -dict {LOC BP28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}] +set_property -dict {LOC BP31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}] +set_property -dict {LOC BN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}] +set_property -dict {LOC BJ31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}] +set_property -dict {LOC BH31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}] +set_property -dict {LOC BF32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}] +set_property -dict {LOC BF33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}] +set_property -dict {LOC BH29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}] +set_property -dict {LOC BH30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}] +set_property -dict {LOC BF31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}] +set_property -dict {LOC BG32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}] +set_property -dict {LOC BK31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}] +set_property -dict {LOC BL31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}] +set_property -dict {LOC BK33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}] +set_property -dict {LOC BL33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}] +set_property -dict {LOC BL32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}] +set_property -dict {LOC BM33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}] +set_property -dict {LOC BN34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}] +set_property -dict {LOC BP34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}] +set_property -dict {LOC BH34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}] +set_property -dict {LOC BH35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}] +set_property -dict {LOC BF35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}] +set_property -dict {LOC BF36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}] +set_property -dict {LOC BJ33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}] +set_property -dict {LOC BJ34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}] +set_property -dict {LOC BG34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}] +set_property -dict {LOC BG35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}] +set_property -dict {LOC BM52 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}] +set_property -dict {LOC BL53 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}] +set_property -dict {LOC BL52 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}] +set_property -dict {LOC BL51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}] +set_property -dict {LOC BN50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}] +set_property -dict {LOC BN51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}] +set_property -dict {LOC BN49 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}] +set_property -dict {LOC BM48 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}] +set_property -dict {LOC BE50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}] +set_property -dict {LOC BE49 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}] +set_property -dict {LOC BE51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}] +set_property -dict {LOC BD51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}] +set_property -dict {LOC BF52 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}] +set_property -dict {LOC BF51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}] +set_property -dict {LOC BG50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}] +set_property -dict {LOC BF50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}] +set_property -dict {LOC BH50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}] +set_property -dict {LOC BJ51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}] +set_property -dict {LOC BH51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}] +set_property -dict {LOC BH49 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}] +set_property -dict {LOC BK50 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}] +set_property -dict {LOC BK51 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}] +set_property -dict {LOC BJ49 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}] +set_property -dict {LOC BJ48 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}] +set_property -dict {LOC BN44 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}] +set_property -dict {LOC BN45 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}] +set_property -dict {LOC BM44 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}] +set_property -dict {LOC BM45 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}] +set_property -dict {LOC BP43 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}] +set_property -dict {LOC BP44 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}] +set_property -dict {LOC BN47 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}] +set_property -dict {LOC BP47 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}] +set_property -dict {LOC BG54 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}] +set_property -dict {LOC BG53 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}] +set_property -dict {LOC BE53 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}] +set_property -dict {LOC BE54 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}] +set_property -dict {LOC BH52 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}] +set_property -dict {LOC BG52 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}] +set_property -dict {LOC BK54 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}] +set_property -dict {LOC BK53 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}] +set_property -dict {LOC BN29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}] +set_property -dict {LOC BN30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}] +set_property -dict {LOC BM28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}] +set_property -dict {LOC BM29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}] +set_property -dict {LOC BJ29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}] +set_property -dict {LOC BK30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}] +set_property -dict {LOC BG29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}] +set_property -dict {LOC BG30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}] +set_property -dict {LOC BL35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}] +set_property -dict {LOC BM35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}] +set_property -dict {LOC BM34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}] +set_property -dict {LOC BN35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}] +set_property -dict {LOC BK34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}] +set_property -dict {LOC BK35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}] +set_property -dict {LOC BH32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}] +set_property -dict {LOC BJ32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}] +set_property -dict {LOC BM49 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}] +set_property -dict {LOC BM50 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}] +set_property -dict {LOC BP48 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[9]}] +set_property -dict {LOC BP49 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[9]}] +set_property -dict {LOC BF47 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[10]}] +set_property -dict {LOC BF48 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[10]}] +set_property -dict {LOC BG48 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[11]}] +set_property -dict {LOC BG49 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[11]}] +set_property -dict {LOC BH47 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[12]}] +set_property -dict {LOC BJ47 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[12]}] +set_property -dict {LOC BK48 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[13]}] +set_property -dict {LOC BK49 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[13]}] +set_property -dict {LOC BN46 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[14]}] +set_property -dict {LOC BP46 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[14]}] +set_property -dict {LOC BN42 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[15]}] +set_property -dict {LOC BP42 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[15]}] +set_property -dict {LOC BH54 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[16]}] +set_property -dict {LOC BJ54 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[16]}] +set_property -dict {LOC BJ52 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[17]}] +set_property -dict {LOC BJ53 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[17]}] + +# DDR4 C1 +set_property -dict {LOC BF7 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}] +set_property -dict {LOC BK1 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}] +set_property -dict {LOC BF6 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}] +set_property -dict {LOC BF5 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}] +set_property -dict {LOC BE3 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}] +set_property -dict {LOC BE6 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}] +set_property -dict {LOC BE5 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}] +set_property -dict {LOC BG7 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}] +set_property -dict {LOC BJ1 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}] +set_property -dict {LOC BG2 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}] +set_property -dict {LOC BJ8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}] +set_property -dict {LOC BE4 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}] +set_property -dict {LOC BL2 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}] +set_property -dict {LOC BK5 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}] +set_property -dict {LOC BK8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}] +set_property -dict {LOC BJ4 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}] +set_property -dict {LOC BF8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}] +set_property -dict {LOC BG8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}] +set_property -dict {LOC BK4 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}] +set_property -dict {LOC BF3 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}] +set_property -dict {LOC BF2 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}] +set_property -dict {LOC BJ3 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c1_ck_t}] +set_property -dict {LOC BJ2 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c1_ck_c}] +set_property -dict {LOC BE1 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke}] +set_property -dict {LOC BL3 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n}] +set_property -dict {LOC BG3 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}] +set_property -dict {LOC BH2 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt}] +set_property -dict {LOC BH1 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}] +set_property -dict {LOC BH12 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_c1_reset_n}] + +set_property -dict {LOC A11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] +set_property -dict {LOC A10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] +set_property -dict {LOC A9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] +set_property -dict {LOC A8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] +set_property -dict {LOC B12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] +set_property -dict {LOC B10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] +set_property -dict {LOC C12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] +set_property -dict {LOC B11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] +set_property -dict {LOC E11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] +set_property -dict {LOC D11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] +set_property -dict {LOC E12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] +set_property -dict {LOC F11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] +set_property -dict {LOC F10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] +set_property -dict {LOC E9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] +set_property -dict {LOC F9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] +set_property -dict {LOC G11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] +set_property -dict {LOC H12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] +set_property -dict {LOC G13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] +set_property -dict {LOC H13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] +set_property -dict {LOC H14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] +set_property -dict {LOC J11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] +set_property -dict {LOC J12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] +set_property -dict {LOC J15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] +set_property -dict {LOC J14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] +set_property -dict {LOC A14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] +set_property -dict {LOC C15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] +set_property -dict {LOC A15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] +set_property -dict {LOC B15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] +set_property -dict {LOC F15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] +set_property -dict {LOC E14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] +set_property -dict {LOC F14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] +set_property -dict {LOC F13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] +set_property -dict {LOC BM3 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] +set_property -dict {LOC BM4 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] +set_property -dict {LOC BM5 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] +set_property -dict {LOC BL6 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] +set_property -dict {LOC BN4 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] +set_property -dict {LOC BN5 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] +set_property -dict {LOC BN6 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] +set_property -dict {LOC BN7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] +set_property -dict {LOC BJ9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] +set_property -dict {LOC BK9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] +set_property -dict {LOC BK10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] +set_property -dict {LOC BL10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] +set_property -dict {LOC BM9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] +set_property -dict {LOC BN9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] +set_property -dict {LOC BN10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] +set_property -dict {LOC BM10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] +set_property -dict {LOC BM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] +set_property -dict {LOC BM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] +set_property -dict {LOC BL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] +set_property -dict {LOC BM13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] +set_property -dict {LOC BN12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] +set_property -dict {LOC BM12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] +set_property -dict {LOC BP13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] +set_property -dict {LOC BP14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] +set_property -dict {LOC BJ13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] +set_property -dict {LOC BJ12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] +set_property -dict {LOC BH15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] +set_property -dict {LOC BH14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] +set_property -dict {LOC BK14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] +set_property -dict {LOC BK15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] +set_property -dict {LOC BL12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] +set_property -dict {LOC BL13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] +set_property -dict {LOC BE9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}] +set_property -dict {LOC BE10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}] +set_property -dict {LOC BF10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}] +set_property -dict {LOC BE11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}] +set_property -dict {LOC BG13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}] +set_property -dict {LOC BG12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}] +set_property -dict {LOC BG9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}] +set_property -dict {LOC BG10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}] +set_property -dict {LOC B13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] +set_property -dict {LOC A13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] +set_property -dict {LOC C10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] +set_property -dict {LOC C9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] +set_property -dict {LOC D10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] +set_property -dict {LOC D9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] +set_property -dict {LOC H10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] +set_property -dict {LOC G10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] +set_property -dict {LOC H15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] +set_property -dict {LOC G15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] +set_property -dict {LOC K14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] +set_property -dict {LOC K13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] +set_property -dict {LOC D15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] +set_property -dict {LOC D14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] +set_property -dict {LOC E13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] +set_property -dict {LOC D12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] +set_property -dict {LOC BL7 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}] +set_property -dict {LOC BM7 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}] +set_property -dict {LOC BP7 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}] +set_property -dict {LOC BP6 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}] +set_property -dict {LOC BL8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[10]}] +set_property -dict {LOC BM8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[10]}] +set_property -dict {LOC BP9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[11]}] +set_property -dict {LOC BP8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[11]}] +set_property -dict {LOC BN15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[12]}] +set_property -dict {LOC BN14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[12]}] +set_property -dict {LOC BP12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[13]}] +set_property -dict {LOC BP11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[13]}] +set_property -dict {LOC BJ14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[14]}] +set_property -dict {LOC BK13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[14]}] +set_property -dict {LOC BJ11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[15]}] +set_property -dict {LOC BK11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[15]}] +set_property -dict {LOC BF12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[16]}] +set_property -dict {LOC BF11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[16]}] +set_property -dict {LOC BH10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[17]}] +set_property -dict {LOC BH9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[17]}] diff --git a/fpga/mqnic/AU280/fpga_25g/fpga/Makefile b/fpga/mqnic/AU280/fpga_25g/fpga/Makefile index bb5bfa142..2d4b56e1a 100644 --- a/fpga/mqnic/AU280/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/AU280/fpga_25g/fpga/Makefile @@ -138,11 +138,14 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl +XDC_FILES += hbm.xdc # IP IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl IP_TCL_FILES += ip/cms.tcl +IP_TCL_FILES += ip/hbm_0.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl index ab9b890da..1a1b373b8 100644 --- a/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/AU280/fpga_25g/fpga/config.tcl @@ -148,6 +148,17 @@ dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" dict set params RX_RAM_SIZE "131072" + +# RAM configuration +dict set params DDR_CH "2" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" +dict set params HBM_CH "32" +dict set params HBM_ENABLE "1" +dict set params HBM_GROUP_SIZE "32" +dict set params AXI_HBM_ADDR_WIDTH "33" +dict set params AXI_HBM_MAX_BURST_LEN "256" # Application block configuration dict set params APP_ID "32'h00000000" @@ -200,6 +211,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie4c_uscale_plus_0] diff --git a/fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile index bb5bfa142..2d4b56e1a 100644 --- a/fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile @@ -138,11 +138,14 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl +XDC_FILES += hbm.xdc # IP IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl IP_TCL_FILES += ip/cms.tcl +IP_TCL_FILES += ip/hbm_0.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl index 6c4dbeeb5..c372953d0 100644 --- a/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/AU280/fpga_25g/fpga_10g/config.tcl @@ -148,6 +148,17 @@ dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" dict set params RX_RAM_SIZE "32768" + +# RAM configuration +dict set params DDR_CH "2" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" +dict set params HBM_CH "32" +dict set params HBM_ENABLE "1" +dict set params HBM_GROUP_SIZE "32" +dict set params AXI_HBM_ADDR_WIDTH "33" +dict set params AXI_HBM_MAX_BURST_LEN "256" # Application block configuration dict set params APP_ID "32'h00000000" @@ -200,6 +211,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie4c_uscale_plus_0] diff --git a/fpga/mqnic/AU280/fpga_25g/hbm.xdc b/fpga/mqnic/AU280/fpga_25g/hbm.xdc new file mode 100644 index 000000000..aa147b0a5 --- /dev/null +++ b/fpga/mqnic/AU280/fpga_25g/hbm.xdc @@ -0,0 +1,2 @@ +# force debug hub to use HBM APB clock to prevent CDC issues +connect_debug_port dbg_hub/clk [get_nets */APB_0_PCLK] diff --git a/fpga/mqnic/AU280/fpga_25g/ip/ddr4_0.tcl b/fpga/mqnic/AU280/fpga_25g/ip/ddr4_0.tcl new file mode 100644 index 000000000..12bd7aee2 --- /dev/null +++ b/fpga/mqnic/AU280/fpga_25g/ip/ddr4_0.tcl @@ -0,0 +1,18 @@ + +create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 + +set_property -dict [list \ + CONFIG.System_Clock {No_Buffer} \ + CONFIG.C0.DDR4_AxiSelection {true} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_AxiIDWidth {8} \ + CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ + CONFIG.C0.DDR4_TimePeriod {833} \ + CONFIG.C0.DDR4_InputClockPeriod {9996} \ + CONFIG.C0.DDR4_MemoryType {RDIMMs} \ + CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PZ-2G3} \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_CasLatency {17} \ + CONFIG.C0.DDR4_CasWriteLatency {12} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} +] [get_ips ddr4_0] diff --git a/fpga/mqnic/AU280/fpga_25g/ip/hbm_0.tcl b/fpga/mqnic/AU280/fpga_25g/ip/hbm_0.tcl new file mode 100644 index 000000000..a8cbc2874 --- /dev/null +++ b/fpga/mqnic/AU280/fpga_25g/ip/hbm_0.tcl @@ -0,0 +1,23 @@ + +create_ip -name hbm -vendor xilinx.com -library ip -module_name hbm_0 + +set_property -dict [list \ + CONFIG.USER_HBM_DENSITY {8GB} \ + CONFIG.USER_HBM_STACK {2} \ + CONFIG.USER_MC0_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC1_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC2_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC3_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC4_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC5_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC6_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC7_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC8_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC9_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC10_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC11_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC12_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC13_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC14_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC15_ENABLE_ECC_CORRECTION {true} +] [get_ips hbm_0] diff --git a/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v index a2c62f4e7..82acfb468 100644 --- a/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/AU280/fpga_25g/rtl/fpga.v @@ -112,6 +112,20 @@ module fpga # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // RAM configuration + parameter DDR_CH = 2, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 34, + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + parameter HBM_CH = 32, + parameter HBM_ENABLE = 1, + parameter HBM_GROUP_SIZE = 32, + parameter AXI_HBM_ADDR_WIDTH = 33, + parameter AXI_HBM_MAX_BURST_LEN = 256, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -177,6 +191,16 @@ module fpga # parameter STAT_ID_WIDTH = 12 ) ( + /* + * Clock and reset + */ + input wire clk_100mhz_0_p, + input wire clk_100mhz_0_n, + input wire clk_100mhz_1_p, + input wire clk_100mhz_1_n, + input wire clk_100mhz_2_p, + input wire clk_100mhz_2_n, + /* * GPIO */ @@ -243,7 +267,40 @@ module fpga # input wire qsfp1_mgt_refclk_1_p, input wire qsfp1_mgt_refclk_1_n, output wire qsfp1_refclk_oe_b, - output wire qsfp1_refclk_fs + output wire qsfp1_refclk_fs, + + /* + * DDR4 + */ + output wire [16:0] ddr4_c0_adr, + output wire [1:0] ddr4_c0_ba, + output wire [1:0] ddr4_c0_bg, + output wire ddr4_c0_ck_t, + output wire ddr4_c0_ck_c, + output wire ddr4_c0_cke, + output wire ddr4_c0_cs_n, + output wire ddr4_c0_act_n, + output wire ddr4_c0_odt, + output wire ddr4_c0_par, + output wire ddr4_c0_reset_n, + inout wire [71:0] ddr4_c0_dq, + inout wire [17:0] ddr4_c0_dqs_t, + inout wire [17:0] ddr4_c0_dqs_c, + + output wire [16:0] ddr4_c1_adr, + output wire [1:0] ddr4_c1_ba, + output wire [1:0] ddr4_c1_bg, + output wire ddr4_c1_ck_t, + output wire ddr4_c1_ck_c, + output wire ddr4_c1_cke, + output wire ddr4_c1_cs_n, + output wire ddr4_c1_act_n, + output wire ddr4_c1_odt, + output wire ddr4_c1_par, + output wire ddr4_c1_reset_n, + inout wire [71:0] ddr4_c1_dq, + inout wire [17:0] ddr4_c1_dqs_t, + inout wire [17:0] ddr4_c1_dqs_c ); // PTP configuration @@ -257,6 +314,12 @@ parameter IF_PTP_PERIOD_FNS = 16'h6666; // Interface configuration parameter TX_TAG_WIDTH = 16; +// RAM configuration +parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8); +parameter AXI_HBM_DATA_WIDTH = 256; +parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8); +parameter AXI_HBM_ID_WIDTH = 6; + // Ethernet interface configuration parameter XGMII_DATA_WIDTH = 64; parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8; @@ -376,9 +439,6 @@ sync_reset_125mhz_inst ( .out(rst_125mhz_int) ); -// GPIO -assign hbm_cattrip = 1'b0; - // Flash wire qspi_clk_int; wire [3:0] qspi_dq_int; @@ -588,6 +648,9 @@ wire [1:0] axil_cms_rresp_int; wire axil_cms_rvalid_int; wire axil_cms_rready_int; +wire [7:0] hbm_temp_1; +wire [7:0] hbm_temp_2; + axil_cdc #( .DATA_WIDTH(32), .ADDR_WIDTH(18) @@ -641,8 +704,8 @@ cms_wrapper cms_inst ( .aclk_ctrl_0(clk_50mhz_int), .aresetn_ctrl_0(~rst_50mhz_int), - .hbm_temp_1_0(7'd0), - .hbm_temp_2_0(7'd0), + .hbm_temp_1_0(hbm_temp_1), + .hbm_temp_2_0(hbm_temp_2), .interrupt_hbm_cattrip_0(hbm_cattrip), .interrupt_host_0(), .s_axi_ctrl_0_araddr(axil_cms_araddr_int), @@ -1390,6 +1453,1655 @@ assign ptp_clk = qsfp0_mgt_refclk_1_bufg; assign ptp_rst = qsfp0_rst; assign ptp_sample_clk = clk_125mhz_int; +// DDR4 +wire [DDR_CH-1:0] ddr_clk; +wire [DDR_CH-1:0] ddr_rst; + +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr; +wire [DDR_CH*8-1:0] m_axi_ddr_awlen; +wire [DDR_CH*3-1:0] m_axi_ddr_awsize; +wire [DDR_CH*2-1:0] m_axi_ddr_awburst; +wire [DDR_CH-1:0] m_axi_ddr_awlock; +wire [DDR_CH*4-1:0] m_axi_ddr_awcache; +wire [DDR_CH*3-1:0] m_axi_ddr_awprot; +wire [DDR_CH*4-1:0] m_axi_ddr_awqos; +wire [DDR_CH-1:0] m_axi_ddr_awvalid; +wire [DDR_CH-1:0] m_axi_ddr_awready; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata; +wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb; +wire [DDR_CH-1:0] m_axi_ddr_wlast; +wire [DDR_CH-1:0] m_axi_ddr_wvalid; +wire [DDR_CH-1:0] m_axi_ddr_wready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid; +wire [DDR_CH*2-1:0] m_axi_ddr_bresp; +wire [DDR_CH-1:0] m_axi_ddr_bvalid; +wire [DDR_CH-1:0] m_axi_ddr_bready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr; +wire [DDR_CH*8-1:0] m_axi_ddr_arlen; +wire [DDR_CH*3-1:0] m_axi_ddr_arsize; +wire [DDR_CH*2-1:0] m_axi_ddr_arburst; +wire [DDR_CH-1:0] m_axi_ddr_arlock; +wire [DDR_CH*4-1:0] m_axi_ddr_arcache; +wire [DDR_CH*3-1:0] m_axi_ddr_arprot; +wire [DDR_CH*4-1:0] m_axi_ddr_arqos; +wire [DDR_CH-1:0] m_axi_ddr_arvalid; +wire [DDR_CH-1:0] m_axi_ddr_arready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata; +wire [DDR_CH*2-1:0] m_axi_ddr_rresp; +wire [DDR_CH-1:0] m_axi_ddr_rlast; +wire [DDR_CH-1:0] m_axi_ddr_rvalid; +wire [DDR_CH-1:0] m_axi_ddr_rready; + +wire [DDR_CH-1:0] ddr_status; + +generate + +wire clk_100mhz_0_ibufg; + +IBUFGDS #( + .DIFF_TERM("FALSE"), + .IBUF_LOW_PWR("FALSE") +) +clk_100mhz_0_ibufg_inst ( + .O (clk_100mhz_0_ibufg), + .I (clk_100mhz_0_p), + .IB (clk_100mhz_0_n) +); + +if (DDR_ENABLE && DDR_CH > 0) begin + +ddr4_0 ddr4_c0_inst ( + .c0_sys_clk_i(clk_100mhz_0_ibufg), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[0 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c0_adr), + .c0_ddr4_ba(ddr4_c0_ba), + .c0_ddr4_cke(ddr4_c0_cke), + .c0_ddr4_cs_n(ddr4_c0_cs_n), + .c0_ddr4_dq(ddr4_c0_dq), + .c0_ddr4_dqs_t(ddr4_c0_dqs_t), + .c0_ddr4_dqs_c(ddr4_c0_dqs_c), + .c0_ddr4_odt(ddr4_c0_odt), + .c0_ddr4_parity(ddr4_c0_par), + .c0_ddr4_bg(ddr4_c0_bg), + .c0_ddr4_reset_n(ddr4_c0_reset_n), + .c0_ddr4_act_n(ddr4_c0_act_n), + .c0_ddr4_ck_t(ddr4_c0_ck_t), + .c0_ddr4_ck_c(ddr4_c0_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[0 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[0 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c0_adr = {17{1'bz}}; +assign ddr4_c0_ba = {2{1'bz}}; +assign ddr4_c0_bg = {2{1'bz}}; +assign ddr4_c0_cke = 1'bz; +assign ddr4_c0_cs_n = 1'bz; +assign ddr4_c0_act_n = 1'bz; +assign ddr4_c0_odt = 1'bz; +assign ddr4_c0_par = 1'bz; +assign ddr4_c0_reset_n = 1'b0; +assign ddr4_c0_dq = {72{1'bz}}; +assign ddr4_c0_dqs_t = {18{1'bz}}; +assign ddr4_c0_dqs_c = {18{1'bz}}; + +OBUFTDS ddr4_c0_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c0_ck_t), + .OB(ddr4_c0_ck_c) +); + +assign ddr_clk = 0; +assign ddr_rst = 0; + +assign m_axi_ddr_awready = 0; +assign m_axi_ddr_wready = 0; +assign m_axi_ddr_bid = 0; +assign m_axi_ddr_bresp = 0; +assign m_axi_ddr_bvalid = 0; +assign m_axi_ddr_arready = 0; +assign m_axi_ddr_rid = 0; +assign m_axi_ddr_rdata = 0; +assign m_axi_ddr_rresp = 0; +assign m_axi_ddr_rlast = 0; +assign m_axi_ddr_rvalid = 0; + +assign ddr_status = 0; + +end + +wire clk_100mhz_1_ibufg; + +IBUFGDS #( + .DIFF_TERM("FALSE"), + .IBUF_LOW_PWR("FALSE") +) +clk_100mhz_1_ibufg_inst ( + .O (clk_100mhz_1_ibufg), + .I (clk_100mhz_1_p), + .IB (clk_100mhz_1_n) +); + +if (DDR_ENABLE && DDR_CH > 1) begin + +ddr4_0 ddr4_c1_inst ( + .c0_sys_clk_i(clk_100mhz_1_ibufg), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[1 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c1_adr), + .c0_ddr4_ba(ddr4_c1_ba), + .c0_ddr4_cke(ddr4_c1_cke), + .c0_ddr4_cs_n(ddr4_c1_cs_n), + .c0_ddr4_dq(ddr4_c1_dq), + .c0_ddr4_dqs_t(ddr4_c1_dqs_t), + .c0_ddr4_dqs_c(ddr4_c1_dqs_c), + .c0_ddr4_odt(ddr4_c1_odt), + .c0_ddr4_parity(ddr4_c1_par), + .c0_ddr4_bg(ddr4_c1_bg), + .c0_ddr4_reset_n(ddr4_c1_reset_n), + .c0_ddr4_act_n(ddr4_c1_act_n), + .c0_ddr4_ck_t(ddr4_c1_ck_t), + .c0_ddr4_ck_c(ddr4_c1_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[1 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[1 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[1 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[1*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[1*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[1*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[1 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[1*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[1*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[1*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[1 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[1 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[1*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[1 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[1 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[1 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[1 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[1*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[1 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[1*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[1*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[1*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[1 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[1*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[1*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[1*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[1 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[1 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[1 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[1 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[1 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[1*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c1_adr = {17{1'bz}}; +assign ddr4_c1_ba = {2{1'bz}}; +assign ddr4_c1_bg = {2{1'bz}}; +assign ddr4_c1_cke = 1'bz; +assign ddr4_c1_cs_n = 1'bz; +assign ddr4_c1_act_n = 1'bz; +assign ddr4_c1_odt = 1'bz; +assign ddr4_c1_par = 1'bz; +assign ddr4_c1_reset_n = 1'b0; +assign ddr4_c1_dq = {72{1'bz}}; +assign ddr4_c1_dqs_t = {18{1'bz}}; +assign ddr4_c1_dqs_c = {18{1'bz}}; + +OBUFTDS ddr4_c1_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c1_ck_t), + .OB(ddr4_c1_ck_c) +); + +end + +endgenerate + +// HBM +wire [HBM_CH-1:0] hbm_clk; +wire [HBM_CH-1:0] hbm_rst; + +wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_awid; +wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_awaddr; +wire [HBM_CH*8-1:0] m_axi_hbm_awlen; +wire [HBM_CH*3-1:0] m_axi_hbm_awsize; +wire [HBM_CH*2-1:0] m_axi_hbm_awburst; +wire [HBM_CH-1:0] m_axi_hbm_awlock; +wire [HBM_CH*4-1:0] m_axi_hbm_awcache; +wire [HBM_CH*3-1:0] m_axi_hbm_awprot; +wire [HBM_CH*4-1:0] m_axi_hbm_awqos; +wire [HBM_CH-1:0] m_axi_hbm_awvalid; +wire [HBM_CH-1:0] m_axi_hbm_awready; +wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_wdata; +wire [HBM_CH*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_wstrb; +wire [HBM_CH-1:0] m_axi_hbm_wlast; +wire [HBM_CH-1:0] m_axi_hbm_wvalid; +wire [HBM_CH-1:0] m_axi_hbm_wready; +wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_bid; +wire [HBM_CH*2-1:0] m_axi_hbm_bresp; +wire [HBM_CH-1:0] m_axi_hbm_bvalid; +wire [HBM_CH-1:0] m_axi_hbm_bready; +wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_arid; +wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_araddr; +wire [HBM_CH*8-1:0] m_axi_hbm_arlen; +wire [HBM_CH*3-1:0] m_axi_hbm_arsize; +wire [HBM_CH*2-1:0] m_axi_hbm_arburst; +wire [HBM_CH-1:0] m_axi_hbm_arlock; +wire [HBM_CH*4-1:0] m_axi_hbm_arcache; +wire [HBM_CH*3-1:0] m_axi_hbm_arprot; +wire [HBM_CH*4-1:0] m_axi_hbm_arqos; +wire [HBM_CH-1:0] m_axi_hbm_arvalid; +wire [HBM_CH-1:0] m_axi_hbm_arready; +wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_rid; +wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_rdata; +wire [HBM_CH*2-1:0] m_axi_hbm_rresp; +wire [HBM_CH-1:0] m_axi_hbm_rlast; +wire [HBM_CH-1:0] m_axi_hbm_rvalid; +wire [HBM_CH-1:0] m_axi_hbm_rready; + +wire [HBM_CH-1:0] hbm_status; + +generate + +if (HBM_ENABLE) begin + +wire hbm_ref_clk; + +wire hbm_mmcm_rst; +wire hbm_mmcm_locked; +wire hbm_mmcm_clkfb; + +wire hbm_axi_clk_mmcm; +wire hbm_axi_clk; +wire hbm_axi_rst_int; +wire hbm_axi_rst; + +BUFG +hbm_ref_clk_bufg_inst ( + .I(clk_100mhz_0_ibufg), + .O(hbm_ref_clk) +); + +// HBM MMCM instance +// 100 MHz in, 450 MHz out +// PFD range: 10 MHz to 500 MHz +// VCO range: 800 MHz to 1600 MHz +// M = 9, D = 1 sets Fvco = 900 MHz +// Divide by 2 to get output frequency of 450 MHz +MMCME4_BASE #( + .BANDWIDTH("OPTIMIZED"), + .CLKOUT0_DIVIDE_F(2), + .CLKOUT0_DUTY_CYCLE(0.5), + .CLKOUT0_PHASE(0), + .CLKOUT1_DIVIDE(1), + .CLKOUT1_DUTY_CYCLE(0.5), + .CLKOUT1_PHASE(0), + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.5), + .CLKOUT2_PHASE(0), + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.5), + .CLKOUT3_PHASE(0), + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.5), + .CLKOUT4_PHASE(0), + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.5), + .CLKOUT5_PHASE(0), + .CLKOUT6_DIVIDE(1), + .CLKOUT6_DUTY_CYCLE(0.5), + .CLKOUT6_PHASE(0), + .CLKFBOUT_MULT_F(9), + .CLKFBOUT_PHASE(0), + .DIVCLK_DIVIDE(1), + .REF_JITTER1(0.010), + .CLKIN1_PERIOD(10.000), + .STARTUP_WAIT("FALSE"), + .CLKOUT4_CASCADE("FALSE") +) +hbm_mmcm_inst ( + .CLKIN1(clk_100mhz_0_ibufg), + .CLKFBIN(hbm_mmcm_clkfb), + .RST(hbm_mmcm_rst), + .PWRDWN(1'b0), + .CLKOUT0(hbm_axi_clk_mmcm), + .CLKOUT0B(), + .CLKOUT1(), + .CLKOUT1B(), + .CLKOUT2(), + .CLKOUT2B(), + .CLKOUT3(), + .CLKOUT3B(), + .CLKOUT4(), + .CLKOUT5(), + .CLKOUT6(), + .CLKFBOUT(hbm_mmcm_clkfb), + .CLKFBOUTB(), + .LOCKED(hbm_mmcm_locked) +); + +BUFG +hbm_axi_clk_bufg_inst ( + .I(hbm_axi_clk_mmcm), + .O(hbm_axi_clk) +); + +sync_reset #( + .N(4) +) +sync_reset_hbm_axi_inst ( + .clk(hbm_axi_clk), + .rst(~hbm_mmcm_locked), + .out(hbm_axi_rst_int) +); + +// extra register for hbm_axi_rst signal +(* shreg_extract = "no" *) +reg hbm_axi_rst_reg_1 = 1'b1; +(* shreg_extract = "no" *) +reg hbm_axi_rst_reg_2 = 1'b1; + +assign hbm_axi_rst = hbm_axi_rst_reg_2; + +always @(posedge hbm_axi_clk) begin + hbm_axi_rst_reg_1 <= hbm_axi_rst_int; + hbm_axi_rst_reg_2 <= hbm_axi_rst_reg_1; +end + +wire hbm_cattrip_1; +wire hbm_cattrip_2; + +assign hbm_cattrip = hbm_cattrip_1 | hbm_cattrip_2; + +assign hbm_clk = {HBM_CH{hbm_axi_clk}}; +assign hbm_rst = {HBM_CH{hbm_axi_rst}}; + +hbm_0 hbm_inst ( + .HBM_REF_CLK_0(hbm_ref_clk), + .HBM_REF_CLK_1(hbm_ref_clk), + + .APB_0_PWDATA(32'd0), + .APB_0_PADDR(22'd0), + .APB_0_PCLK(hbm_ref_clk), + .APB_0_PENABLE(1'b0), + .APB_0_PRESET_N(1'b1), + .APB_0_PSEL(1'b0), + .APB_0_PWRITE(1'b0), + .APB_0_PRDATA(), + .APB_0_PREADY(), + .APB_0_PSLVERR(), + .apb_complete_0(), + + .APB_1_PWDATA(32'd0), + .APB_1_PADDR(22'd0), + .APB_1_PCLK(hbm_ref_clk), + .APB_1_PENABLE(1'b0), + .APB_1_PRESET_N(1'b1), + .APB_1_PSEL(1'b0), + .APB_1_PWRITE(1'b0), + .APB_1_PRDATA(), + .APB_1_PREADY(), + .APB_1_PSLVERR(), + .apb_complete_1(), + + .AXI_00_ACLK(hbm_clk[0 +: 1]), + .AXI_00_ARESET_N(!hbm_rst[0 +: 1]), + + .AXI_00_ARADDR(m_axi_hbm_araddr[0*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_00_ARBURST(m_axi_hbm_arburst[0*2 +: 2]), + .AXI_00_ARID(m_axi_hbm_arid[0*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_00_ARLEN(m_axi_hbm_arlen[0*8 +: 8]), + .AXI_00_ARSIZE(m_axi_hbm_arsize[0*3 +: 3]), + .AXI_00_ARVALID(m_axi_hbm_arvalid[0 +: 1]), + .AXI_00_ARREADY(m_axi_hbm_arready[0 +: 1]), + .AXI_00_RDATA_PARITY(), + .AXI_00_RDATA(m_axi_hbm_rdata[0*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_00_RID(m_axi_hbm_rid[0 +: 1]), + .AXI_00_RLAST(m_axi_hbm_rlast[0 +: 1]), + .AXI_00_RRESP(m_axi_hbm_rresp[0*2 +: 2]), + .AXI_00_RVALID(m_axi_hbm_rvalid[0 +: 1]), + .AXI_00_RREADY(m_axi_hbm_rready[0 +: 1]), + .AXI_00_AWADDR(m_axi_hbm_awaddr[0*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_00_AWBURST(m_axi_hbm_awburst[0*2 +: 2]), + .AXI_00_AWID(m_axi_hbm_awid[0*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_00_AWLEN(m_axi_hbm_awlen[0*8 +: 8]), + .AXI_00_AWSIZE(m_axi_hbm_awsize[0*3 +: 3]), + .AXI_00_AWVALID(m_axi_hbm_awvalid[0 +: 1]), + .AXI_00_AWREADY(m_axi_hbm_awready[0 +: 1]), + .AXI_00_WDATA(m_axi_hbm_wdata[0*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_00_WLAST(m_axi_hbm_wlast[0 +: 1]), + .AXI_00_WSTRB(m_axi_hbm_wstrb[0*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_00_WDATA_PARITY(32'd0), + .AXI_00_WVALID(m_axi_hbm_wvalid[0 +: 1]), + .AXI_00_WREADY(m_axi_hbm_wready[0 +: 1]), + .AXI_00_BID(m_axi_hbm_bid[0*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_00_BRESP(m_axi_hbm_bresp[0*2 +: 2]), + .AXI_00_BVALID(m_axi_hbm_bvalid[0 +: 1]), + .AXI_00_BREADY(m_axi_hbm_bready[0 +: 1]), + + .AXI_01_ACLK(hbm_clk[1 +: 1]), + .AXI_01_ARESET_N(!hbm_rst[1 +: 1]), + + .AXI_01_ARADDR(m_axi_hbm_araddr[1*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_01_ARBURST(m_axi_hbm_arburst[1*2 +: 2]), + .AXI_01_ARID(m_axi_hbm_arid[1*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_01_ARLEN(m_axi_hbm_arlen[1*8 +: 8]), + .AXI_01_ARSIZE(m_axi_hbm_arsize[1*3 +: 3]), + .AXI_01_ARVALID(m_axi_hbm_arvalid[1 +: 1]), + .AXI_01_ARREADY(m_axi_hbm_arready[1 +: 1]), + .AXI_01_RDATA_PARITY(), + .AXI_01_RDATA(m_axi_hbm_rdata[1*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_01_RID(m_axi_hbm_rid[1 +: 1]), + .AXI_01_RLAST(m_axi_hbm_rlast[1 +: 1]), + .AXI_01_RRESP(m_axi_hbm_rresp[1*2 +: 2]), + .AXI_01_RVALID(m_axi_hbm_rvalid[1 +: 1]), + .AXI_01_RREADY(m_axi_hbm_rready[1 +: 1]), + .AXI_01_AWADDR(m_axi_hbm_awaddr[1*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_01_AWBURST(m_axi_hbm_awburst[1*2 +: 2]), + .AXI_01_AWID(m_axi_hbm_awid[1*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_01_AWLEN(m_axi_hbm_awlen[1*8 +: 8]), + .AXI_01_AWSIZE(m_axi_hbm_awsize[1*3 +: 3]), + .AXI_01_AWVALID(m_axi_hbm_awvalid[1 +: 1]), + .AXI_01_AWREADY(m_axi_hbm_awready[1 +: 1]), + .AXI_01_WDATA(m_axi_hbm_wdata[1*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_01_WLAST(m_axi_hbm_wlast[1 +: 1]), + .AXI_01_WSTRB(m_axi_hbm_wstrb[1*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_01_WDATA_PARITY(32'd0), + .AXI_01_WVALID(m_axi_hbm_wvalid[1 +: 1]), + .AXI_01_WREADY(m_axi_hbm_wready[1 +: 1]), + .AXI_01_BID(m_axi_hbm_bid[1*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_01_BRESP(m_axi_hbm_bresp[1*2 +: 2]), + .AXI_01_BVALID(m_axi_hbm_bvalid[1 +: 1]), + .AXI_01_BREADY(m_axi_hbm_bready[1 +: 1]), + + .AXI_02_ACLK(hbm_clk[2 +: 1]), + .AXI_02_ARESET_N(!hbm_rst[2 +: 1]), + + .AXI_02_ARADDR(m_axi_hbm_araddr[2*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_02_ARBURST(m_axi_hbm_arburst[2*2 +: 2]), + .AXI_02_ARID(m_axi_hbm_arid[2*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_02_ARLEN(m_axi_hbm_arlen[2*8 +: 8]), + .AXI_02_ARSIZE(m_axi_hbm_arsize[2*3 +: 3]), + .AXI_02_ARVALID(m_axi_hbm_arvalid[2 +: 1]), + .AXI_02_ARREADY(m_axi_hbm_arready[2 +: 1]), + .AXI_02_RDATA_PARITY(), + .AXI_02_RDATA(m_axi_hbm_rdata[2*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_02_RID(m_axi_hbm_rid[2 +: 1]), + .AXI_02_RLAST(m_axi_hbm_rlast[2 +: 1]), + .AXI_02_RRESP(m_axi_hbm_rresp[2*2 +: 2]), + .AXI_02_RVALID(m_axi_hbm_rvalid[2 +: 1]), + .AXI_02_RREADY(m_axi_hbm_rready[2 +: 1]), + .AXI_02_AWADDR(m_axi_hbm_awaddr[2*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_02_AWBURST(m_axi_hbm_awburst[2*2 +: 2]), + .AXI_02_AWID(m_axi_hbm_awid[2*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_02_AWLEN(m_axi_hbm_awlen[2*8 +: 8]), + .AXI_02_AWSIZE(m_axi_hbm_awsize[2*3 +: 3]), + .AXI_02_AWVALID(m_axi_hbm_awvalid[2 +: 1]), + .AXI_02_AWREADY(m_axi_hbm_awready[2 +: 1]), + .AXI_02_WDATA(m_axi_hbm_wdata[2*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_02_WLAST(m_axi_hbm_wlast[2 +: 1]), + .AXI_02_WSTRB(m_axi_hbm_wstrb[2*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_02_WDATA_PARITY(32'd0), + .AXI_02_WVALID(m_axi_hbm_wvalid[2 +: 1]), + .AXI_02_WREADY(m_axi_hbm_wready[2 +: 1]), + .AXI_02_BID(m_axi_hbm_bid[2*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_02_BRESP(m_axi_hbm_bresp[2*2 +: 2]), + .AXI_02_BVALID(m_axi_hbm_bvalid[2 +: 1]), + .AXI_02_BREADY(m_axi_hbm_bready[2 +: 1]), + + .AXI_03_ACLK(hbm_clk[3 +: 1]), + .AXI_03_ARESET_N(!hbm_rst[3 +: 1]), + + .AXI_03_ARADDR(m_axi_hbm_araddr[3*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_03_ARBURST(m_axi_hbm_arburst[3*2 +: 2]), + .AXI_03_ARID(m_axi_hbm_arid[3*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_03_ARLEN(m_axi_hbm_arlen[3*8 +: 8]), + .AXI_03_ARSIZE(m_axi_hbm_arsize[3*3 +: 3]), + .AXI_03_ARVALID(m_axi_hbm_arvalid[3 +: 1]), + .AXI_03_ARREADY(m_axi_hbm_arready[3 +: 1]), + .AXI_03_RDATA_PARITY(), + .AXI_03_RDATA(m_axi_hbm_rdata[3*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_03_RID(m_axi_hbm_rid[3 +: 1]), + .AXI_03_RLAST(m_axi_hbm_rlast[3 +: 1]), + .AXI_03_RRESP(m_axi_hbm_rresp[3*2 +: 2]), + .AXI_03_RVALID(m_axi_hbm_rvalid[3 +: 1]), + .AXI_03_RREADY(m_axi_hbm_rready[3 +: 1]), + .AXI_03_AWADDR(m_axi_hbm_awaddr[3*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_03_AWBURST(m_axi_hbm_awburst[3*2 +: 2]), + .AXI_03_AWID(m_axi_hbm_awid[3*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_03_AWLEN(m_axi_hbm_awlen[3*8 +: 8]), + .AXI_03_AWSIZE(m_axi_hbm_awsize[3*3 +: 3]), + .AXI_03_AWVALID(m_axi_hbm_awvalid[3 +: 1]), + .AXI_03_AWREADY(m_axi_hbm_awready[3 +: 1]), + .AXI_03_WDATA(m_axi_hbm_wdata[3*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_03_WLAST(m_axi_hbm_wlast[3 +: 1]), + .AXI_03_WSTRB(m_axi_hbm_wstrb[3*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_03_WDATA_PARITY(32'd0), + .AXI_03_WVALID(m_axi_hbm_wvalid[3 +: 1]), + .AXI_03_WREADY(m_axi_hbm_wready[3 +: 1]), + .AXI_03_BID(m_axi_hbm_bid[3*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_03_BRESP(m_axi_hbm_bresp[3*2 +: 2]), + .AXI_03_BVALID(m_axi_hbm_bvalid[3 +: 1]), + .AXI_03_BREADY(m_axi_hbm_bready[3 +: 1]), + + .AXI_04_ACLK(hbm_clk[4 +: 1]), + .AXI_04_ARESET_N(!hbm_rst[4 +: 1]), + + .AXI_04_ARADDR(m_axi_hbm_araddr[4*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_04_ARBURST(m_axi_hbm_arburst[4*2 +: 2]), + .AXI_04_ARID(m_axi_hbm_arid[4*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_04_ARLEN(m_axi_hbm_arlen[4*8 +: 8]), + .AXI_04_ARSIZE(m_axi_hbm_arsize[4*3 +: 3]), + .AXI_04_ARVALID(m_axi_hbm_arvalid[4 +: 1]), + .AXI_04_ARREADY(m_axi_hbm_arready[4 +: 1]), + .AXI_04_RDATA_PARITY(), + .AXI_04_RDATA(m_axi_hbm_rdata[4*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_04_RID(m_axi_hbm_rid[4 +: 1]), + .AXI_04_RLAST(m_axi_hbm_rlast[4 +: 1]), + .AXI_04_RRESP(m_axi_hbm_rresp[4*2 +: 2]), + .AXI_04_RVALID(m_axi_hbm_rvalid[4 +: 1]), + .AXI_04_RREADY(m_axi_hbm_rready[4 +: 1]), + .AXI_04_AWADDR(m_axi_hbm_awaddr[4*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_04_AWBURST(m_axi_hbm_awburst[4*2 +: 2]), + .AXI_04_AWID(m_axi_hbm_awid[4*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_04_AWLEN(m_axi_hbm_awlen[4*8 +: 8]), + .AXI_04_AWSIZE(m_axi_hbm_awsize[4*3 +: 3]), + .AXI_04_AWVALID(m_axi_hbm_awvalid[4 +: 1]), + .AXI_04_AWREADY(m_axi_hbm_awready[4 +: 1]), + .AXI_04_WDATA(m_axi_hbm_wdata[4*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_04_WLAST(m_axi_hbm_wlast[4 +: 1]), + .AXI_04_WSTRB(m_axi_hbm_wstrb[4*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_04_WDATA_PARITY(32'd0), + .AXI_04_WVALID(m_axi_hbm_wvalid[4 +: 1]), + .AXI_04_WREADY(m_axi_hbm_wready[4 +: 1]), + .AXI_04_BID(m_axi_hbm_bid[4*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_04_BRESP(m_axi_hbm_bresp[4*2 +: 2]), + .AXI_04_BVALID(m_axi_hbm_bvalid[4 +: 1]), + .AXI_04_BREADY(m_axi_hbm_bready[4 +: 1]), + + .AXI_05_ACLK(hbm_clk[5 +: 1]), + .AXI_05_ARESET_N(!hbm_rst[5 +: 1]), + + .AXI_05_ARADDR(m_axi_hbm_araddr[5*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_05_ARBURST(m_axi_hbm_arburst[5*2 +: 2]), + .AXI_05_ARID(m_axi_hbm_arid[5*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_05_ARLEN(m_axi_hbm_arlen[5*8 +: 8]), + .AXI_05_ARSIZE(m_axi_hbm_arsize[5*3 +: 3]), + .AXI_05_ARVALID(m_axi_hbm_arvalid[5 +: 1]), + .AXI_05_ARREADY(m_axi_hbm_arready[5 +: 1]), + .AXI_05_RDATA_PARITY(), + .AXI_05_RDATA(m_axi_hbm_rdata[5*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_05_RID(m_axi_hbm_rid[5 +: 1]), + .AXI_05_RLAST(m_axi_hbm_rlast[5 +: 1]), + .AXI_05_RRESP(m_axi_hbm_rresp[5*2 +: 2]), + .AXI_05_RVALID(m_axi_hbm_rvalid[5 +: 1]), + .AXI_05_RREADY(m_axi_hbm_rready[5 +: 1]), + .AXI_05_AWADDR(m_axi_hbm_awaddr[5*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_05_AWBURST(m_axi_hbm_awburst[5*2 +: 2]), + .AXI_05_AWID(m_axi_hbm_awid[5*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_05_AWLEN(m_axi_hbm_awlen[5*8 +: 8]), + .AXI_05_AWSIZE(m_axi_hbm_awsize[5*3 +: 3]), + .AXI_05_AWVALID(m_axi_hbm_awvalid[5 +: 1]), + .AXI_05_AWREADY(m_axi_hbm_awready[5 +: 1]), + .AXI_05_WDATA(m_axi_hbm_wdata[5*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_05_WLAST(m_axi_hbm_wlast[5 +: 1]), + .AXI_05_WSTRB(m_axi_hbm_wstrb[5*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_05_WDATA_PARITY(32'd0), + .AXI_05_WVALID(m_axi_hbm_wvalid[5 +: 1]), + .AXI_05_WREADY(m_axi_hbm_wready[5 +: 1]), + .AXI_05_BID(m_axi_hbm_bid[5*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_05_BRESP(m_axi_hbm_bresp[5*2 +: 2]), + .AXI_05_BVALID(m_axi_hbm_bvalid[5 +: 1]), + .AXI_05_BREADY(m_axi_hbm_bready[5 +: 1]), + + .AXI_06_ACLK(hbm_clk[6 +: 1]), + .AXI_06_ARESET_N(!hbm_rst[6 +: 1]), + + .AXI_06_ARADDR(m_axi_hbm_araddr[6*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_06_ARBURST(m_axi_hbm_arburst[6*2 +: 2]), + .AXI_06_ARID(m_axi_hbm_arid[6*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_06_ARLEN(m_axi_hbm_arlen[6*8 +: 8]), + .AXI_06_ARSIZE(m_axi_hbm_arsize[6*3 +: 3]), + .AXI_06_ARVALID(m_axi_hbm_arvalid[6 +: 1]), + .AXI_06_ARREADY(m_axi_hbm_arready[6 +: 1]), + .AXI_06_RDATA_PARITY(), + .AXI_06_RDATA(m_axi_hbm_rdata[6*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_06_RID(m_axi_hbm_rid[6 +: 1]), + .AXI_06_RLAST(m_axi_hbm_rlast[6 +: 1]), + .AXI_06_RRESP(m_axi_hbm_rresp[6*2 +: 2]), + .AXI_06_RVALID(m_axi_hbm_rvalid[6 +: 1]), + .AXI_06_RREADY(m_axi_hbm_rready[6 +: 1]), + .AXI_06_AWADDR(m_axi_hbm_awaddr[6*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_06_AWBURST(m_axi_hbm_awburst[6*2 +: 2]), + .AXI_06_AWID(m_axi_hbm_awid[6*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_06_AWLEN(m_axi_hbm_awlen[6*8 +: 8]), + .AXI_06_AWSIZE(m_axi_hbm_awsize[6*3 +: 3]), + .AXI_06_AWVALID(m_axi_hbm_awvalid[6 +: 1]), + .AXI_06_AWREADY(m_axi_hbm_awready[6 +: 1]), + .AXI_06_WDATA(m_axi_hbm_wdata[6*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_06_WLAST(m_axi_hbm_wlast[6 +: 1]), + .AXI_06_WSTRB(m_axi_hbm_wstrb[6*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_06_WDATA_PARITY(32'd0), + .AXI_06_WVALID(m_axi_hbm_wvalid[6 +: 1]), + .AXI_06_WREADY(m_axi_hbm_wready[6 +: 1]), + .AXI_06_BID(m_axi_hbm_bid[6*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_06_BRESP(m_axi_hbm_bresp[6*2 +: 2]), + .AXI_06_BVALID(m_axi_hbm_bvalid[6 +: 1]), + .AXI_06_BREADY(m_axi_hbm_bready[6 +: 1]), + + .AXI_07_ACLK(hbm_clk[7 +: 1]), + .AXI_07_ARESET_N(!hbm_rst[7 +: 1]), + + .AXI_07_ARADDR(m_axi_hbm_araddr[7*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_07_ARBURST(m_axi_hbm_arburst[7*2 +: 2]), + .AXI_07_ARID(m_axi_hbm_arid[7*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_07_ARLEN(m_axi_hbm_arlen[7*8 +: 8]), + .AXI_07_ARSIZE(m_axi_hbm_arsize[7*3 +: 3]), + .AXI_07_ARVALID(m_axi_hbm_arvalid[7 +: 1]), + .AXI_07_ARREADY(m_axi_hbm_arready[7 +: 1]), + .AXI_07_RDATA_PARITY(), + .AXI_07_RDATA(m_axi_hbm_rdata[7*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_07_RID(m_axi_hbm_rid[7 +: 1]), + .AXI_07_RLAST(m_axi_hbm_rlast[7 +: 1]), + .AXI_07_RRESP(m_axi_hbm_rresp[7*2 +: 2]), + .AXI_07_RVALID(m_axi_hbm_rvalid[7 +: 1]), + .AXI_07_RREADY(m_axi_hbm_rready[7 +: 1]), + .AXI_07_AWADDR(m_axi_hbm_awaddr[7*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_07_AWBURST(m_axi_hbm_awburst[7*2 +: 2]), + .AXI_07_AWID(m_axi_hbm_awid[7*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_07_AWLEN(m_axi_hbm_awlen[7*8 +: 8]), + .AXI_07_AWSIZE(m_axi_hbm_awsize[7*3 +: 3]), + .AXI_07_AWVALID(m_axi_hbm_awvalid[7 +: 1]), + .AXI_07_AWREADY(m_axi_hbm_awready[7 +: 1]), + .AXI_07_WDATA(m_axi_hbm_wdata[7*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_07_WLAST(m_axi_hbm_wlast[7 +: 1]), + .AXI_07_WSTRB(m_axi_hbm_wstrb[7*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_07_WDATA_PARITY(32'd0), + .AXI_07_WVALID(m_axi_hbm_wvalid[7 +: 1]), + .AXI_07_WREADY(m_axi_hbm_wready[7 +: 1]), + .AXI_07_BID(m_axi_hbm_bid[7*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_07_BRESP(m_axi_hbm_bresp[7*2 +: 2]), + .AXI_07_BVALID(m_axi_hbm_bvalid[7 +: 1]), + .AXI_07_BREADY(m_axi_hbm_bready[7 +: 1]), + + .AXI_08_ACLK(hbm_clk[8 +: 1]), + .AXI_08_ARESET_N(!hbm_rst[8 +: 1]), + + .AXI_08_ARADDR(m_axi_hbm_araddr[8*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_08_ARBURST(m_axi_hbm_arburst[8*2 +: 2]), + .AXI_08_ARID(m_axi_hbm_arid[8*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_08_ARLEN(m_axi_hbm_arlen[8*8 +: 8]), + .AXI_08_ARSIZE(m_axi_hbm_arsize[8*3 +: 3]), + .AXI_08_ARVALID(m_axi_hbm_arvalid[8 +: 1]), + .AXI_08_ARREADY(m_axi_hbm_arready[8 +: 1]), + .AXI_08_RDATA_PARITY(), + .AXI_08_RDATA(m_axi_hbm_rdata[8*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_08_RID(m_axi_hbm_rid[8 +: 1]), + .AXI_08_RLAST(m_axi_hbm_rlast[8 +: 1]), + .AXI_08_RRESP(m_axi_hbm_rresp[8*2 +: 2]), + .AXI_08_RVALID(m_axi_hbm_rvalid[8 +: 1]), + .AXI_08_RREADY(m_axi_hbm_rready[8 +: 1]), + .AXI_08_AWADDR(m_axi_hbm_awaddr[8*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_08_AWBURST(m_axi_hbm_awburst[8*2 +: 2]), + .AXI_08_AWID(m_axi_hbm_awid[8*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_08_AWLEN(m_axi_hbm_awlen[8*8 +: 8]), + .AXI_08_AWSIZE(m_axi_hbm_awsize[8*3 +: 3]), + .AXI_08_AWVALID(m_axi_hbm_awvalid[8 +: 1]), + .AXI_08_AWREADY(m_axi_hbm_awready[8 +: 1]), + .AXI_08_WDATA(m_axi_hbm_wdata[8*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_08_WLAST(m_axi_hbm_wlast[8 +: 1]), + .AXI_08_WSTRB(m_axi_hbm_wstrb[8*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_08_WDATA_PARITY(32'd0), + .AXI_08_WVALID(m_axi_hbm_wvalid[8 +: 1]), + .AXI_08_WREADY(m_axi_hbm_wready[8 +: 1]), + .AXI_08_BID(m_axi_hbm_bid[8*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_08_BRESP(m_axi_hbm_bresp[8*2 +: 2]), + .AXI_08_BVALID(m_axi_hbm_bvalid[8 +: 1]), + .AXI_08_BREADY(m_axi_hbm_bready[8 +: 1]), + + .AXI_09_ACLK(hbm_clk[9 +: 1]), + .AXI_09_ARESET_N(!hbm_rst[9 +: 1]), + + .AXI_09_ARADDR(m_axi_hbm_araddr[9*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_09_ARBURST(m_axi_hbm_arburst[9*2 +: 2]), + .AXI_09_ARID(m_axi_hbm_arid[9*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_09_ARLEN(m_axi_hbm_arlen[9*8 +: 8]), + .AXI_09_ARSIZE(m_axi_hbm_arsize[9*3 +: 3]), + .AXI_09_ARVALID(m_axi_hbm_arvalid[9 +: 1]), + .AXI_09_ARREADY(m_axi_hbm_arready[9 +: 1]), + .AXI_09_RDATA_PARITY(), + .AXI_09_RDATA(m_axi_hbm_rdata[9*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_09_RID(m_axi_hbm_rid[9 +: 1]), + .AXI_09_RLAST(m_axi_hbm_rlast[9 +: 1]), + .AXI_09_RRESP(m_axi_hbm_rresp[9*2 +: 2]), + .AXI_09_RVALID(m_axi_hbm_rvalid[9 +: 1]), + .AXI_09_RREADY(m_axi_hbm_rready[9 +: 1]), + .AXI_09_AWADDR(m_axi_hbm_awaddr[9*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_09_AWBURST(m_axi_hbm_awburst[9*2 +: 2]), + .AXI_09_AWID(m_axi_hbm_awid[9*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_09_AWLEN(m_axi_hbm_awlen[9*8 +: 8]), + .AXI_09_AWSIZE(m_axi_hbm_awsize[9*3 +: 3]), + .AXI_09_AWVALID(m_axi_hbm_awvalid[9 +: 1]), + .AXI_09_AWREADY(m_axi_hbm_awready[9 +: 1]), + .AXI_09_WDATA(m_axi_hbm_wdata[9*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_09_WLAST(m_axi_hbm_wlast[9 +: 1]), + .AXI_09_WSTRB(m_axi_hbm_wstrb[9*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_09_WDATA_PARITY(32'd0), + .AXI_09_WVALID(m_axi_hbm_wvalid[9 +: 1]), + .AXI_09_WREADY(m_axi_hbm_wready[9 +: 1]), + .AXI_09_BID(m_axi_hbm_bid[9*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_09_BRESP(m_axi_hbm_bresp[9*2 +: 2]), + .AXI_09_BVALID(m_axi_hbm_bvalid[9 +: 1]), + .AXI_09_BREADY(m_axi_hbm_bready[9 +: 1]), + + .AXI_10_ACLK(hbm_clk[10 +: 1]), + .AXI_10_ARESET_N(!hbm_rst[10 +: 1]), + + .AXI_10_ARADDR(m_axi_hbm_araddr[10*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_10_ARBURST(m_axi_hbm_arburst[10*2 +: 2]), + .AXI_10_ARID(m_axi_hbm_arid[10*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_10_ARLEN(m_axi_hbm_arlen[10*8 +: 8]), + .AXI_10_ARSIZE(m_axi_hbm_arsize[10*3 +: 3]), + .AXI_10_ARVALID(m_axi_hbm_arvalid[10 +: 1]), + .AXI_10_ARREADY(m_axi_hbm_arready[10 +: 1]), + .AXI_10_RDATA_PARITY(), + .AXI_10_RDATA(m_axi_hbm_rdata[10*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_10_RID(m_axi_hbm_rid[10 +: 1]), + .AXI_10_RLAST(m_axi_hbm_rlast[10 +: 1]), + .AXI_10_RRESP(m_axi_hbm_rresp[10*2 +: 2]), + .AXI_10_RVALID(m_axi_hbm_rvalid[10 +: 1]), + .AXI_10_RREADY(m_axi_hbm_rready[10 +: 1]), + .AXI_10_AWADDR(m_axi_hbm_awaddr[10*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_10_AWBURST(m_axi_hbm_awburst[10*2 +: 2]), + .AXI_10_AWID(m_axi_hbm_awid[10*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_10_AWLEN(m_axi_hbm_awlen[10*8 +: 8]), + .AXI_10_AWSIZE(m_axi_hbm_awsize[10*3 +: 3]), + .AXI_10_AWVALID(m_axi_hbm_awvalid[10 +: 1]), + .AXI_10_AWREADY(m_axi_hbm_awready[10 +: 1]), + .AXI_10_WDATA(m_axi_hbm_wdata[10*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_10_WLAST(m_axi_hbm_wlast[10 +: 1]), + .AXI_10_WSTRB(m_axi_hbm_wstrb[10*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_10_WDATA_PARITY(32'd0), + .AXI_10_WVALID(m_axi_hbm_wvalid[10 +: 1]), + .AXI_10_WREADY(m_axi_hbm_wready[10 +: 1]), + .AXI_10_BID(m_axi_hbm_bid[10*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_10_BRESP(m_axi_hbm_bresp[10*2 +: 2]), + .AXI_10_BVALID(m_axi_hbm_bvalid[10 +: 1]), + .AXI_10_BREADY(m_axi_hbm_bready[10 +: 1]), + + .AXI_11_ACLK(hbm_clk[11 +: 1]), + .AXI_11_ARESET_N(!hbm_rst[11 +: 1]), + + .AXI_11_ARADDR(m_axi_hbm_araddr[11*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_11_ARBURST(m_axi_hbm_arburst[11*2 +: 2]), + .AXI_11_ARID(m_axi_hbm_arid[11*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_11_ARLEN(m_axi_hbm_arlen[11*8 +: 8]), + .AXI_11_ARSIZE(m_axi_hbm_arsize[11*3 +: 3]), + .AXI_11_ARVALID(m_axi_hbm_arvalid[11 +: 1]), + .AXI_11_ARREADY(m_axi_hbm_arready[11 +: 1]), + .AXI_11_RDATA_PARITY(), + .AXI_11_RDATA(m_axi_hbm_rdata[11*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_11_RID(m_axi_hbm_rid[11 +: 1]), + .AXI_11_RLAST(m_axi_hbm_rlast[11 +: 1]), + .AXI_11_RRESP(m_axi_hbm_rresp[11*2 +: 2]), + .AXI_11_RVALID(m_axi_hbm_rvalid[11 +: 1]), + .AXI_11_RREADY(m_axi_hbm_rready[11 +: 1]), + .AXI_11_AWADDR(m_axi_hbm_awaddr[11*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_11_AWBURST(m_axi_hbm_awburst[11*2 +: 2]), + .AXI_11_AWID(m_axi_hbm_awid[11*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_11_AWLEN(m_axi_hbm_awlen[11*8 +: 8]), + .AXI_11_AWSIZE(m_axi_hbm_awsize[11*3 +: 3]), + .AXI_11_AWVALID(m_axi_hbm_awvalid[11 +: 1]), + .AXI_11_AWREADY(m_axi_hbm_awready[11 +: 1]), + .AXI_11_WDATA(m_axi_hbm_wdata[11*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_11_WLAST(m_axi_hbm_wlast[11 +: 1]), + .AXI_11_WSTRB(m_axi_hbm_wstrb[11*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_11_WDATA_PARITY(32'd0), + .AXI_11_WVALID(m_axi_hbm_wvalid[11 +: 1]), + .AXI_11_WREADY(m_axi_hbm_wready[11 +: 1]), + .AXI_11_BID(m_axi_hbm_bid[11*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_11_BRESP(m_axi_hbm_bresp[11*2 +: 2]), + .AXI_11_BVALID(m_axi_hbm_bvalid[11 +: 1]), + .AXI_11_BREADY(m_axi_hbm_bready[11 +: 1]), + + .AXI_12_ACLK(hbm_clk[12 +: 1]), + .AXI_12_ARESET_N(!hbm_rst[12 +: 1]), + + .AXI_12_ARADDR(m_axi_hbm_araddr[12*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_12_ARBURST(m_axi_hbm_arburst[12*2 +: 2]), + .AXI_12_ARID(m_axi_hbm_arid[12*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_12_ARLEN(m_axi_hbm_arlen[12*8 +: 8]), + .AXI_12_ARSIZE(m_axi_hbm_arsize[12*3 +: 3]), + .AXI_12_ARVALID(m_axi_hbm_arvalid[12 +: 1]), + .AXI_12_ARREADY(m_axi_hbm_arready[12 +: 1]), + .AXI_12_RDATA_PARITY(), + .AXI_12_RDATA(m_axi_hbm_rdata[12*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_12_RID(m_axi_hbm_rid[12 +: 1]), + .AXI_12_RLAST(m_axi_hbm_rlast[12 +: 1]), + .AXI_12_RRESP(m_axi_hbm_rresp[12*2 +: 2]), + .AXI_12_RVALID(m_axi_hbm_rvalid[12 +: 1]), + .AXI_12_RREADY(m_axi_hbm_rready[12 +: 1]), + .AXI_12_AWADDR(m_axi_hbm_awaddr[12*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_12_AWBURST(m_axi_hbm_awburst[12*2 +: 2]), + .AXI_12_AWID(m_axi_hbm_awid[12*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_12_AWLEN(m_axi_hbm_awlen[12*8 +: 8]), + .AXI_12_AWSIZE(m_axi_hbm_awsize[12*3 +: 3]), + .AXI_12_AWVALID(m_axi_hbm_awvalid[12 +: 1]), + .AXI_12_AWREADY(m_axi_hbm_awready[12 +: 1]), + .AXI_12_WDATA(m_axi_hbm_wdata[12*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_12_WLAST(m_axi_hbm_wlast[12 +: 1]), + .AXI_12_WSTRB(m_axi_hbm_wstrb[12*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_12_WDATA_PARITY(32'd0), + .AXI_12_WVALID(m_axi_hbm_wvalid[12 +: 1]), + .AXI_12_WREADY(m_axi_hbm_wready[12 +: 1]), + .AXI_12_BID(m_axi_hbm_bid[12*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_12_BRESP(m_axi_hbm_bresp[12*2 +: 2]), + .AXI_12_BVALID(m_axi_hbm_bvalid[12 +: 1]), + .AXI_12_BREADY(m_axi_hbm_bready[12 +: 1]), + + .AXI_13_ACLK(hbm_clk[13 +: 1]), + .AXI_13_ARESET_N(!hbm_rst[13 +: 1]), + + .AXI_13_ARADDR(m_axi_hbm_araddr[13*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_13_ARBURST(m_axi_hbm_arburst[13*2 +: 2]), + .AXI_13_ARID(m_axi_hbm_arid[13*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_13_ARLEN(m_axi_hbm_arlen[13*8 +: 8]), + .AXI_13_ARSIZE(m_axi_hbm_arsize[13*3 +: 3]), + .AXI_13_ARVALID(m_axi_hbm_arvalid[13 +: 1]), + .AXI_13_ARREADY(m_axi_hbm_arready[13 +: 1]), + .AXI_13_RDATA_PARITY(), + .AXI_13_RDATA(m_axi_hbm_rdata[13*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_13_RID(m_axi_hbm_rid[13 +: 1]), + .AXI_13_RLAST(m_axi_hbm_rlast[13 +: 1]), + .AXI_13_RRESP(m_axi_hbm_rresp[13*2 +: 2]), + .AXI_13_RVALID(m_axi_hbm_rvalid[13 +: 1]), + .AXI_13_RREADY(m_axi_hbm_rready[13 +: 1]), + .AXI_13_AWADDR(m_axi_hbm_awaddr[13*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_13_AWBURST(m_axi_hbm_awburst[13*2 +: 2]), + .AXI_13_AWID(m_axi_hbm_awid[13*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_13_AWLEN(m_axi_hbm_awlen[13*8 +: 8]), + .AXI_13_AWSIZE(m_axi_hbm_awsize[13*3 +: 3]), + .AXI_13_AWVALID(m_axi_hbm_awvalid[13 +: 1]), + .AXI_13_AWREADY(m_axi_hbm_awready[13 +: 1]), + .AXI_13_WDATA(m_axi_hbm_wdata[13*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_13_WLAST(m_axi_hbm_wlast[13 +: 1]), + .AXI_13_WSTRB(m_axi_hbm_wstrb[13*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_13_WDATA_PARITY(32'd0), + .AXI_13_WVALID(m_axi_hbm_wvalid[13 +: 1]), + .AXI_13_WREADY(m_axi_hbm_wready[13 +: 1]), + .AXI_13_BID(m_axi_hbm_bid[13*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_13_BRESP(m_axi_hbm_bresp[13*2 +: 2]), + .AXI_13_BVALID(m_axi_hbm_bvalid[13 +: 1]), + .AXI_13_BREADY(m_axi_hbm_bready[13 +: 1]), + + .AXI_14_ACLK(hbm_clk[14 +: 1]), + .AXI_14_ARESET_N(!hbm_rst[14 +: 1]), + + .AXI_14_ARADDR(m_axi_hbm_araddr[14*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_14_ARBURST(m_axi_hbm_arburst[14*2 +: 2]), + .AXI_14_ARID(m_axi_hbm_arid[14*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_14_ARLEN(m_axi_hbm_arlen[14*8 +: 8]), + .AXI_14_ARSIZE(m_axi_hbm_arsize[14*3 +: 3]), + .AXI_14_ARVALID(m_axi_hbm_arvalid[14 +: 1]), + .AXI_14_ARREADY(m_axi_hbm_arready[14 +: 1]), + .AXI_14_RDATA_PARITY(), + .AXI_14_RDATA(m_axi_hbm_rdata[14*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_14_RID(m_axi_hbm_rid[14 +: 1]), + .AXI_14_RLAST(m_axi_hbm_rlast[14 +: 1]), + .AXI_14_RRESP(m_axi_hbm_rresp[14*2 +: 2]), + .AXI_14_RVALID(m_axi_hbm_rvalid[14 +: 1]), + .AXI_14_RREADY(m_axi_hbm_rready[14 +: 1]), + .AXI_14_AWADDR(m_axi_hbm_awaddr[14*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_14_AWBURST(m_axi_hbm_awburst[14*2 +: 2]), + .AXI_14_AWID(m_axi_hbm_awid[14*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_14_AWLEN(m_axi_hbm_awlen[14*8 +: 8]), + .AXI_14_AWSIZE(m_axi_hbm_awsize[14*3 +: 3]), + .AXI_14_AWVALID(m_axi_hbm_awvalid[14 +: 1]), + .AXI_14_AWREADY(m_axi_hbm_awready[14 +: 1]), + .AXI_14_WDATA(m_axi_hbm_wdata[14*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_14_WLAST(m_axi_hbm_wlast[14 +: 1]), + .AXI_14_WSTRB(m_axi_hbm_wstrb[14*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_14_WDATA_PARITY(32'd0), + .AXI_14_WVALID(m_axi_hbm_wvalid[14 +: 1]), + .AXI_14_WREADY(m_axi_hbm_wready[14 +: 1]), + .AXI_14_BID(m_axi_hbm_bid[14*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_14_BRESP(m_axi_hbm_bresp[14*2 +: 2]), + .AXI_14_BVALID(m_axi_hbm_bvalid[14 +: 1]), + .AXI_14_BREADY(m_axi_hbm_bready[14 +: 1]), + + .AXI_15_ACLK(hbm_clk[15 +: 1]), + .AXI_15_ARESET_N(!hbm_rst[15 +: 1]), + + .AXI_15_ARADDR(m_axi_hbm_araddr[15*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_15_ARBURST(m_axi_hbm_arburst[15*2 +: 2]), + .AXI_15_ARID(m_axi_hbm_arid[15*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_15_ARLEN(m_axi_hbm_arlen[15*8 +: 8]), + .AXI_15_ARSIZE(m_axi_hbm_arsize[15*3 +: 3]), + .AXI_15_ARVALID(m_axi_hbm_arvalid[15 +: 1]), + .AXI_15_ARREADY(m_axi_hbm_arready[15 +: 1]), + .AXI_15_RDATA_PARITY(), + .AXI_15_RDATA(m_axi_hbm_rdata[15*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_15_RID(m_axi_hbm_rid[15 +: 1]), + .AXI_15_RLAST(m_axi_hbm_rlast[15 +: 1]), + .AXI_15_RRESP(m_axi_hbm_rresp[15*2 +: 2]), + .AXI_15_RVALID(m_axi_hbm_rvalid[15 +: 1]), + .AXI_15_RREADY(m_axi_hbm_rready[15 +: 1]), + .AXI_15_AWADDR(m_axi_hbm_awaddr[15*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_15_AWBURST(m_axi_hbm_awburst[15*2 +: 2]), + .AXI_15_AWID(m_axi_hbm_awid[15*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_15_AWLEN(m_axi_hbm_awlen[15*8 +: 8]), + .AXI_15_AWSIZE(m_axi_hbm_awsize[15*3 +: 3]), + .AXI_15_AWVALID(m_axi_hbm_awvalid[15 +: 1]), + .AXI_15_AWREADY(m_axi_hbm_awready[15 +: 1]), + .AXI_15_WDATA(m_axi_hbm_wdata[15*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_15_WLAST(m_axi_hbm_wlast[15 +: 1]), + .AXI_15_WSTRB(m_axi_hbm_wstrb[15*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_15_WDATA_PARITY(32'd0), + .AXI_15_WVALID(m_axi_hbm_wvalid[15 +: 1]), + .AXI_15_WREADY(m_axi_hbm_wready[15 +: 1]), + .AXI_15_BID(m_axi_hbm_bid[15*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_15_BRESP(m_axi_hbm_bresp[15*2 +: 2]), + .AXI_15_BVALID(m_axi_hbm_bvalid[15 +: 1]), + .AXI_15_BREADY(m_axi_hbm_bready[15 +: 1]), + + .AXI_16_ACLK(hbm_clk[16 +: 1]), + .AXI_16_ARESET_N(!hbm_rst[16 +: 1]), + + .AXI_16_ARADDR(m_axi_hbm_araddr[16*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_16_ARBURST(m_axi_hbm_arburst[16*2 +: 2]), + .AXI_16_ARID(m_axi_hbm_arid[16*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_16_ARLEN(m_axi_hbm_arlen[16*8 +: 8]), + .AXI_16_ARSIZE(m_axi_hbm_arsize[16*3 +: 3]), + .AXI_16_ARVALID(m_axi_hbm_arvalid[16 +: 1]), + .AXI_16_ARREADY(m_axi_hbm_arready[16 +: 1]), + .AXI_16_RDATA_PARITY(), + .AXI_16_RDATA(m_axi_hbm_rdata[16*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_16_RID(m_axi_hbm_rid[16 +: 1]), + .AXI_16_RLAST(m_axi_hbm_rlast[16 +: 1]), + .AXI_16_RRESP(m_axi_hbm_rresp[16*2 +: 2]), + .AXI_16_RVALID(m_axi_hbm_rvalid[16 +: 1]), + .AXI_16_RREADY(m_axi_hbm_rready[16 +: 1]), + .AXI_16_AWADDR(m_axi_hbm_awaddr[16*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_16_AWBURST(m_axi_hbm_awburst[16*2 +: 2]), + .AXI_16_AWID(m_axi_hbm_awid[16*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_16_AWLEN(m_axi_hbm_awlen[16*8 +: 8]), + .AXI_16_AWSIZE(m_axi_hbm_awsize[16*3 +: 3]), + .AXI_16_AWVALID(m_axi_hbm_awvalid[16 +: 1]), + .AXI_16_AWREADY(m_axi_hbm_awready[16 +: 1]), + .AXI_16_WDATA(m_axi_hbm_wdata[16*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_16_WLAST(m_axi_hbm_wlast[16 +: 1]), + .AXI_16_WSTRB(m_axi_hbm_wstrb[16*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_16_WDATA_PARITY(32'd0), + .AXI_16_WVALID(m_axi_hbm_wvalid[16 +: 1]), + .AXI_16_WREADY(m_axi_hbm_wready[16 +: 1]), + .AXI_16_BID(m_axi_hbm_bid[16*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_16_BRESP(m_axi_hbm_bresp[16*2 +: 2]), + .AXI_16_BVALID(m_axi_hbm_bvalid[16 +: 1]), + .AXI_16_BREADY(m_axi_hbm_bready[16 +: 1]), + + .AXI_17_ACLK(hbm_clk[17 +: 1]), + .AXI_17_ARESET_N(!hbm_rst[17 +: 1]), + + .AXI_17_ARADDR(m_axi_hbm_araddr[17*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_17_ARBURST(m_axi_hbm_arburst[17*2 +: 2]), + .AXI_17_ARID(m_axi_hbm_arid[17*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_17_ARLEN(m_axi_hbm_arlen[17*8 +: 8]), + .AXI_17_ARSIZE(m_axi_hbm_arsize[17*3 +: 3]), + .AXI_17_ARVALID(m_axi_hbm_arvalid[17 +: 1]), + .AXI_17_ARREADY(m_axi_hbm_arready[17 +: 1]), + .AXI_17_RDATA_PARITY(), + .AXI_17_RDATA(m_axi_hbm_rdata[17*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_17_RID(m_axi_hbm_rid[17 +: 1]), + .AXI_17_RLAST(m_axi_hbm_rlast[17 +: 1]), + .AXI_17_RRESP(m_axi_hbm_rresp[17*2 +: 2]), + .AXI_17_RVALID(m_axi_hbm_rvalid[17 +: 1]), + .AXI_17_RREADY(m_axi_hbm_rready[17 +: 1]), + .AXI_17_AWADDR(m_axi_hbm_awaddr[17*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_17_AWBURST(m_axi_hbm_awburst[17*2 +: 2]), + .AXI_17_AWID(m_axi_hbm_awid[17*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_17_AWLEN(m_axi_hbm_awlen[17*8 +: 8]), + .AXI_17_AWSIZE(m_axi_hbm_awsize[17*3 +: 3]), + .AXI_17_AWVALID(m_axi_hbm_awvalid[17 +: 1]), + .AXI_17_AWREADY(m_axi_hbm_awready[17 +: 1]), + .AXI_17_WDATA(m_axi_hbm_wdata[17*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_17_WLAST(m_axi_hbm_wlast[17 +: 1]), + .AXI_17_WSTRB(m_axi_hbm_wstrb[17*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_17_WDATA_PARITY(32'd0), + .AXI_17_WVALID(m_axi_hbm_wvalid[17 +: 1]), + .AXI_17_WREADY(m_axi_hbm_wready[17 +: 1]), + .AXI_17_BID(m_axi_hbm_bid[17*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_17_BRESP(m_axi_hbm_bresp[17*2 +: 2]), + .AXI_17_BVALID(m_axi_hbm_bvalid[17 +: 1]), + .AXI_17_BREADY(m_axi_hbm_bready[17 +: 1]), + + .AXI_18_ACLK(hbm_clk[18 +: 1]), + .AXI_18_ARESET_N(!hbm_rst[18 +: 1]), + + .AXI_18_ARADDR(m_axi_hbm_araddr[18*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_18_ARBURST(m_axi_hbm_arburst[18*2 +: 2]), + .AXI_18_ARID(m_axi_hbm_arid[18*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_18_ARLEN(m_axi_hbm_arlen[18*8 +: 8]), + .AXI_18_ARSIZE(m_axi_hbm_arsize[18*3 +: 3]), + .AXI_18_ARVALID(m_axi_hbm_arvalid[18 +: 1]), + .AXI_18_ARREADY(m_axi_hbm_arready[18 +: 1]), + .AXI_18_RDATA_PARITY(), + .AXI_18_RDATA(m_axi_hbm_rdata[18*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_18_RID(m_axi_hbm_rid[18 +: 1]), + .AXI_18_RLAST(m_axi_hbm_rlast[18 +: 1]), + .AXI_18_RRESP(m_axi_hbm_rresp[18*2 +: 2]), + .AXI_18_RVALID(m_axi_hbm_rvalid[18 +: 1]), + .AXI_18_RREADY(m_axi_hbm_rready[18 +: 1]), + .AXI_18_AWADDR(m_axi_hbm_awaddr[18*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_18_AWBURST(m_axi_hbm_awburst[18*2 +: 2]), + .AXI_18_AWID(m_axi_hbm_awid[18*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_18_AWLEN(m_axi_hbm_awlen[18*8 +: 8]), + .AXI_18_AWSIZE(m_axi_hbm_awsize[18*3 +: 3]), + .AXI_18_AWVALID(m_axi_hbm_awvalid[18 +: 1]), + .AXI_18_AWREADY(m_axi_hbm_awready[18 +: 1]), + .AXI_18_WDATA(m_axi_hbm_wdata[18*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_18_WLAST(m_axi_hbm_wlast[18 +: 1]), + .AXI_18_WSTRB(m_axi_hbm_wstrb[18*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_18_WDATA_PARITY(32'd0), + .AXI_18_WVALID(m_axi_hbm_wvalid[18 +: 1]), + .AXI_18_WREADY(m_axi_hbm_wready[18 +: 1]), + .AXI_18_BID(m_axi_hbm_bid[18*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_18_BRESP(m_axi_hbm_bresp[18*2 +: 2]), + .AXI_18_BVALID(m_axi_hbm_bvalid[18 +: 1]), + .AXI_18_BREADY(m_axi_hbm_bready[18 +: 1]), + + .AXI_19_ACLK(hbm_clk[19 +: 1]), + .AXI_19_ARESET_N(!hbm_rst[19 +: 1]), + + .AXI_19_ARADDR(m_axi_hbm_araddr[19*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_19_ARBURST(m_axi_hbm_arburst[19*2 +: 2]), + .AXI_19_ARID(m_axi_hbm_arid[19*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_19_ARLEN(m_axi_hbm_arlen[19*8 +: 8]), + .AXI_19_ARSIZE(m_axi_hbm_arsize[19*3 +: 3]), + .AXI_19_ARVALID(m_axi_hbm_arvalid[19 +: 1]), + .AXI_19_ARREADY(m_axi_hbm_arready[19 +: 1]), + .AXI_19_RDATA_PARITY(), + .AXI_19_RDATA(m_axi_hbm_rdata[19*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_19_RID(m_axi_hbm_rid[19 +: 1]), + .AXI_19_RLAST(m_axi_hbm_rlast[19 +: 1]), + .AXI_19_RRESP(m_axi_hbm_rresp[19*2 +: 2]), + .AXI_19_RVALID(m_axi_hbm_rvalid[19 +: 1]), + .AXI_19_RREADY(m_axi_hbm_rready[19 +: 1]), + .AXI_19_AWADDR(m_axi_hbm_awaddr[19*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_19_AWBURST(m_axi_hbm_awburst[19*2 +: 2]), + .AXI_19_AWID(m_axi_hbm_awid[19*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_19_AWLEN(m_axi_hbm_awlen[19*8 +: 8]), + .AXI_19_AWSIZE(m_axi_hbm_awsize[19*3 +: 3]), + .AXI_19_AWVALID(m_axi_hbm_awvalid[19 +: 1]), + .AXI_19_AWREADY(m_axi_hbm_awready[19 +: 1]), + .AXI_19_WDATA(m_axi_hbm_wdata[19*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_19_WLAST(m_axi_hbm_wlast[19 +: 1]), + .AXI_19_WSTRB(m_axi_hbm_wstrb[19*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_19_WDATA_PARITY(32'd0), + .AXI_19_WVALID(m_axi_hbm_wvalid[19 +: 1]), + .AXI_19_WREADY(m_axi_hbm_wready[19 +: 1]), + .AXI_19_BID(m_axi_hbm_bid[19*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_19_BRESP(m_axi_hbm_bresp[19*2 +: 2]), + .AXI_19_BVALID(m_axi_hbm_bvalid[19 +: 1]), + .AXI_19_BREADY(m_axi_hbm_bready[19 +: 1]), + + .AXI_20_ACLK(hbm_clk[20 +: 1]), + .AXI_20_ARESET_N(!hbm_rst[20 +: 1]), + + .AXI_20_ARADDR(m_axi_hbm_araddr[20*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_20_ARBURST(m_axi_hbm_arburst[20*2 +: 2]), + .AXI_20_ARID(m_axi_hbm_arid[20*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_20_ARLEN(m_axi_hbm_arlen[20*8 +: 8]), + .AXI_20_ARSIZE(m_axi_hbm_arsize[20*3 +: 3]), + .AXI_20_ARVALID(m_axi_hbm_arvalid[20 +: 1]), + .AXI_20_ARREADY(m_axi_hbm_arready[20 +: 1]), + .AXI_20_RDATA_PARITY(), + .AXI_20_RDATA(m_axi_hbm_rdata[20*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_20_RID(m_axi_hbm_rid[20 +: 1]), + .AXI_20_RLAST(m_axi_hbm_rlast[20 +: 1]), + .AXI_20_RRESP(m_axi_hbm_rresp[20*2 +: 2]), + .AXI_20_RVALID(m_axi_hbm_rvalid[20 +: 1]), + .AXI_20_RREADY(m_axi_hbm_rready[20 +: 1]), + .AXI_20_AWADDR(m_axi_hbm_awaddr[20*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_20_AWBURST(m_axi_hbm_awburst[20*2 +: 2]), + .AXI_20_AWID(m_axi_hbm_awid[20*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_20_AWLEN(m_axi_hbm_awlen[20*8 +: 8]), + .AXI_20_AWSIZE(m_axi_hbm_awsize[20*3 +: 3]), + .AXI_20_AWVALID(m_axi_hbm_awvalid[20 +: 1]), + .AXI_20_AWREADY(m_axi_hbm_awready[20 +: 1]), + .AXI_20_WDATA(m_axi_hbm_wdata[20*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_20_WLAST(m_axi_hbm_wlast[20 +: 1]), + .AXI_20_WSTRB(m_axi_hbm_wstrb[20*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_20_WDATA_PARITY(32'd0), + .AXI_20_WVALID(m_axi_hbm_wvalid[20 +: 1]), + .AXI_20_WREADY(m_axi_hbm_wready[20 +: 1]), + .AXI_20_BID(m_axi_hbm_bid[20*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_20_BRESP(m_axi_hbm_bresp[20*2 +: 2]), + .AXI_20_BVALID(m_axi_hbm_bvalid[20 +: 1]), + .AXI_20_BREADY(m_axi_hbm_bready[20 +: 1]), + + .AXI_21_ACLK(hbm_clk[21 +: 1]), + .AXI_21_ARESET_N(!hbm_rst[21 +: 1]), + + .AXI_21_ARADDR(m_axi_hbm_araddr[21*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_21_ARBURST(m_axi_hbm_arburst[21*2 +: 2]), + .AXI_21_ARID(m_axi_hbm_arid[21*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_21_ARLEN(m_axi_hbm_arlen[21*8 +: 8]), + .AXI_21_ARSIZE(m_axi_hbm_arsize[21*3 +: 3]), + .AXI_21_ARVALID(m_axi_hbm_arvalid[21 +: 1]), + .AXI_21_ARREADY(m_axi_hbm_arready[21 +: 1]), + .AXI_21_RDATA_PARITY(), + .AXI_21_RDATA(m_axi_hbm_rdata[21*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_21_RID(m_axi_hbm_rid[21 +: 1]), + .AXI_21_RLAST(m_axi_hbm_rlast[21 +: 1]), + .AXI_21_RRESP(m_axi_hbm_rresp[21*2 +: 2]), + .AXI_21_RVALID(m_axi_hbm_rvalid[21 +: 1]), + .AXI_21_RREADY(m_axi_hbm_rready[21 +: 1]), + .AXI_21_AWADDR(m_axi_hbm_awaddr[21*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_21_AWBURST(m_axi_hbm_awburst[21*2 +: 2]), + .AXI_21_AWID(m_axi_hbm_awid[21*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_21_AWLEN(m_axi_hbm_awlen[21*8 +: 8]), + .AXI_21_AWSIZE(m_axi_hbm_awsize[21*3 +: 3]), + .AXI_21_AWVALID(m_axi_hbm_awvalid[21 +: 1]), + .AXI_21_AWREADY(m_axi_hbm_awready[21 +: 1]), + .AXI_21_WDATA(m_axi_hbm_wdata[21*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_21_WLAST(m_axi_hbm_wlast[21 +: 1]), + .AXI_21_WSTRB(m_axi_hbm_wstrb[21*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_21_WDATA_PARITY(32'd0), + .AXI_21_WVALID(m_axi_hbm_wvalid[21 +: 1]), + .AXI_21_WREADY(m_axi_hbm_wready[21 +: 1]), + .AXI_21_BID(m_axi_hbm_bid[21*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_21_BRESP(m_axi_hbm_bresp[21*2 +: 2]), + .AXI_21_BVALID(m_axi_hbm_bvalid[21 +: 1]), + .AXI_21_BREADY(m_axi_hbm_bready[21 +: 1]), + + .AXI_22_ACLK(hbm_clk[22 +: 1]), + .AXI_22_ARESET_N(!hbm_rst[22 +: 1]), + + .AXI_22_ARADDR(m_axi_hbm_araddr[22*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_22_ARBURST(m_axi_hbm_arburst[22*2 +: 2]), + .AXI_22_ARID(m_axi_hbm_arid[22*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_22_ARLEN(m_axi_hbm_arlen[22*8 +: 8]), + .AXI_22_ARSIZE(m_axi_hbm_arsize[22*3 +: 3]), + .AXI_22_ARVALID(m_axi_hbm_arvalid[22 +: 1]), + .AXI_22_ARREADY(m_axi_hbm_arready[22 +: 1]), + .AXI_22_RDATA_PARITY(), + .AXI_22_RDATA(m_axi_hbm_rdata[22*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_22_RID(m_axi_hbm_rid[22 +: 1]), + .AXI_22_RLAST(m_axi_hbm_rlast[22 +: 1]), + .AXI_22_RRESP(m_axi_hbm_rresp[22*2 +: 2]), + .AXI_22_RVALID(m_axi_hbm_rvalid[22 +: 1]), + .AXI_22_RREADY(m_axi_hbm_rready[22 +: 1]), + .AXI_22_AWADDR(m_axi_hbm_awaddr[22*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_22_AWBURST(m_axi_hbm_awburst[22*2 +: 2]), + .AXI_22_AWID(m_axi_hbm_awid[22*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_22_AWLEN(m_axi_hbm_awlen[22*8 +: 8]), + .AXI_22_AWSIZE(m_axi_hbm_awsize[22*3 +: 3]), + .AXI_22_AWVALID(m_axi_hbm_awvalid[22 +: 1]), + .AXI_22_AWREADY(m_axi_hbm_awready[22 +: 1]), + .AXI_22_WDATA(m_axi_hbm_wdata[22*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_22_WLAST(m_axi_hbm_wlast[22 +: 1]), + .AXI_22_WSTRB(m_axi_hbm_wstrb[22*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_22_WDATA_PARITY(32'd0), + .AXI_22_WVALID(m_axi_hbm_wvalid[22 +: 1]), + .AXI_22_WREADY(m_axi_hbm_wready[22 +: 1]), + .AXI_22_BID(m_axi_hbm_bid[22*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_22_BRESP(m_axi_hbm_bresp[22*2 +: 2]), + .AXI_22_BVALID(m_axi_hbm_bvalid[22 +: 1]), + .AXI_22_BREADY(m_axi_hbm_bready[22 +: 1]), + + .AXI_23_ACLK(hbm_clk[23 +: 1]), + .AXI_23_ARESET_N(!hbm_rst[23 +: 1]), + + .AXI_23_ARADDR(m_axi_hbm_araddr[23*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_23_ARBURST(m_axi_hbm_arburst[23*2 +: 2]), + .AXI_23_ARID(m_axi_hbm_arid[23*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_23_ARLEN(m_axi_hbm_arlen[23*8 +: 8]), + .AXI_23_ARSIZE(m_axi_hbm_arsize[23*3 +: 3]), + .AXI_23_ARVALID(m_axi_hbm_arvalid[23 +: 1]), + .AXI_23_ARREADY(m_axi_hbm_arready[23 +: 1]), + .AXI_23_RDATA_PARITY(), + .AXI_23_RDATA(m_axi_hbm_rdata[23*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_23_RID(m_axi_hbm_rid[23 +: 1]), + .AXI_23_RLAST(m_axi_hbm_rlast[23 +: 1]), + .AXI_23_RRESP(m_axi_hbm_rresp[23*2 +: 2]), + .AXI_23_RVALID(m_axi_hbm_rvalid[23 +: 1]), + .AXI_23_RREADY(m_axi_hbm_rready[23 +: 1]), + .AXI_23_AWADDR(m_axi_hbm_awaddr[23*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_23_AWBURST(m_axi_hbm_awburst[23*2 +: 2]), + .AXI_23_AWID(m_axi_hbm_awid[23*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_23_AWLEN(m_axi_hbm_awlen[23*8 +: 8]), + .AXI_23_AWSIZE(m_axi_hbm_awsize[23*3 +: 3]), + .AXI_23_AWVALID(m_axi_hbm_awvalid[23 +: 1]), + .AXI_23_AWREADY(m_axi_hbm_awready[23 +: 1]), + .AXI_23_WDATA(m_axi_hbm_wdata[23*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_23_WLAST(m_axi_hbm_wlast[23 +: 1]), + .AXI_23_WSTRB(m_axi_hbm_wstrb[23*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_23_WDATA_PARITY(32'd0), + .AXI_23_WVALID(m_axi_hbm_wvalid[23 +: 1]), + .AXI_23_WREADY(m_axi_hbm_wready[23 +: 1]), + .AXI_23_BID(m_axi_hbm_bid[23*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_23_BRESP(m_axi_hbm_bresp[23*2 +: 2]), + .AXI_23_BVALID(m_axi_hbm_bvalid[23 +: 1]), + .AXI_23_BREADY(m_axi_hbm_bready[23 +: 1]), + + .AXI_24_ACLK(hbm_clk[24 +: 1]), + .AXI_24_ARESET_N(!hbm_rst[24 +: 1]), + + .AXI_24_ARADDR(m_axi_hbm_araddr[24*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_24_ARBURST(m_axi_hbm_arburst[24*2 +: 2]), + .AXI_24_ARID(m_axi_hbm_arid[24*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_24_ARLEN(m_axi_hbm_arlen[24*8 +: 8]), + .AXI_24_ARSIZE(m_axi_hbm_arsize[24*3 +: 3]), + .AXI_24_ARVALID(m_axi_hbm_arvalid[24 +: 1]), + .AXI_24_ARREADY(m_axi_hbm_arready[24 +: 1]), + .AXI_24_RDATA_PARITY(), + .AXI_24_RDATA(m_axi_hbm_rdata[24*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_24_RID(m_axi_hbm_rid[24 +: 1]), + .AXI_24_RLAST(m_axi_hbm_rlast[24 +: 1]), + .AXI_24_RRESP(m_axi_hbm_rresp[24*2 +: 2]), + .AXI_24_RVALID(m_axi_hbm_rvalid[24 +: 1]), + .AXI_24_RREADY(m_axi_hbm_rready[24 +: 1]), + .AXI_24_AWADDR(m_axi_hbm_awaddr[24*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_24_AWBURST(m_axi_hbm_awburst[24*2 +: 2]), + .AXI_24_AWID(m_axi_hbm_awid[24*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_24_AWLEN(m_axi_hbm_awlen[24*8 +: 8]), + .AXI_24_AWSIZE(m_axi_hbm_awsize[24*3 +: 3]), + .AXI_24_AWVALID(m_axi_hbm_awvalid[24 +: 1]), + .AXI_24_AWREADY(m_axi_hbm_awready[24 +: 1]), + .AXI_24_WDATA(m_axi_hbm_wdata[24*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_24_WLAST(m_axi_hbm_wlast[24 +: 1]), + .AXI_24_WSTRB(m_axi_hbm_wstrb[24*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_24_WDATA_PARITY(32'd0), + .AXI_24_WVALID(m_axi_hbm_wvalid[24 +: 1]), + .AXI_24_WREADY(m_axi_hbm_wready[24 +: 1]), + .AXI_24_BID(m_axi_hbm_bid[24*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_24_BRESP(m_axi_hbm_bresp[24*2 +: 2]), + .AXI_24_BVALID(m_axi_hbm_bvalid[24 +: 1]), + .AXI_24_BREADY(m_axi_hbm_bready[24 +: 1]), + + .AXI_25_ACLK(hbm_clk[25 +: 1]), + .AXI_25_ARESET_N(!hbm_rst[25 +: 1]), + + .AXI_25_ARADDR(m_axi_hbm_araddr[25*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_25_ARBURST(m_axi_hbm_arburst[25*2 +: 2]), + .AXI_25_ARID(m_axi_hbm_arid[25*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_25_ARLEN(m_axi_hbm_arlen[25*8 +: 8]), + .AXI_25_ARSIZE(m_axi_hbm_arsize[25*3 +: 3]), + .AXI_25_ARVALID(m_axi_hbm_arvalid[25 +: 1]), + .AXI_25_ARREADY(m_axi_hbm_arready[25 +: 1]), + .AXI_25_RDATA_PARITY(), + .AXI_25_RDATA(m_axi_hbm_rdata[25*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_25_RID(m_axi_hbm_rid[25 +: 1]), + .AXI_25_RLAST(m_axi_hbm_rlast[25 +: 1]), + .AXI_25_RRESP(m_axi_hbm_rresp[25*2 +: 2]), + .AXI_25_RVALID(m_axi_hbm_rvalid[25 +: 1]), + .AXI_25_RREADY(m_axi_hbm_rready[25 +: 1]), + .AXI_25_AWADDR(m_axi_hbm_awaddr[25*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_25_AWBURST(m_axi_hbm_awburst[25*2 +: 2]), + .AXI_25_AWID(m_axi_hbm_awid[25*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_25_AWLEN(m_axi_hbm_awlen[25*8 +: 8]), + .AXI_25_AWSIZE(m_axi_hbm_awsize[25*3 +: 3]), + .AXI_25_AWVALID(m_axi_hbm_awvalid[25 +: 1]), + .AXI_25_AWREADY(m_axi_hbm_awready[25 +: 1]), + .AXI_25_WDATA(m_axi_hbm_wdata[25*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_25_WLAST(m_axi_hbm_wlast[25 +: 1]), + .AXI_25_WSTRB(m_axi_hbm_wstrb[25*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_25_WDATA_PARITY(32'd0), + .AXI_25_WVALID(m_axi_hbm_wvalid[25 +: 1]), + .AXI_25_WREADY(m_axi_hbm_wready[25 +: 1]), + .AXI_25_BID(m_axi_hbm_bid[25*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_25_BRESP(m_axi_hbm_bresp[25*2 +: 2]), + .AXI_25_BVALID(m_axi_hbm_bvalid[25 +: 1]), + .AXI_25_BREADY(m_axi_hbm_bready[25 +: 1]), + + .AXI_26_ACLK(hbm_clk[26 +: 1]), + .AXI_26_ARESET_N(!hbm_rst[26 +: 1]), + + .AXI_26_ARADDR(m_axi_hbm_araddr[26*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_26_ARBURST(m_axi_hbm_arburst[26*2 +: 2]), + .AXI_26_ARID(m_axi_hbm_arid[26*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_26_ARLEN(m_axi_hbm_arlen[26*8 +: 8]), + .AXI_26_ARSIZE(m_axi_hbm_arsize[26*3 +: 3]), + .AXI_26_ARVALID(m_axi_hbm_arvalid[26 +: 1]), + .AXI_26_ARREADY(m_axi_hbm_arready[26 +: 1]), + .AXI_26_RDATA_PARITY(), + .AXI_26_RDATA(m_axi_hbm_rdata[26*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_26_RID(m_axi_hbm_rid[26 +: 1]), + .AXI_26_RLAST(m_axi_hbm_rlast[26 +: 1]), + .AXI_26_RRESP(m_axi_hbm_rresp[26*2 +: 2]), + .AXI_26_RVALID(m_axi_hbm_rvalid[26 +: 1]), + .AXI_26_RREADY(m_axi_hbm_rready[26 +: 1]), + .AXI_26_AWADDR(m_axi_hbm_awaddr[26*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_26_AWBURST(m_axi_hbm_awburst[26*2 +: 2]), + .AXI_26_AWID(m_axi_hbm_awid[26*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_26_AWLEN(m_axi_hbm_awlen[26*8 +: 8]), + .AXI_26_AWSIZE(m_axi_hbm_awsize[26*3 +: 3]), + .AXI_26_AWVALID(m_axi_hbm_awvalid[26 +: 1]), + .AXI_26_AWREADY(m_axi_hbm_awready[26 +: 1]), + .AXI_26_WDATA(m_axi_hbm_wdata[26*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_26_WLAST(m_axi_hbm_wlast[26 +: 1]), + .AXI_26_WSTRB(m_axi_hbm_wstrb[26*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_26_WDATA_PARITY(32'd0), + .AXI_26_WVALID(m_axi_hbm_wvalid[26 +: 1]), + .AXI_26_WREADY(m_axi_hbm_wready[26 +: 1]), + .AXI_26_BID(m_axi_hbm_bid[26*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_26_BRESP(m_axi_hbm_bresp[26*2 +: 2]), + .AXI_26_BVALID(m_axi_hbm_bvalid[26 +: 1]), + .AXI_26_BREADY(m_axi_hbm_bready[26 +: 1]), + + .AXI_27_ACLK(hbm_clk[27 +: 1]), + .AXI_27_ARESET_N(!hbm_rst[27 +: 1]), + + .AXI_27_ARADDR(m_axi_hbm_araddr[27*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_27_ARBURST(m_axi_hbm_arburst[27*2 +: 2]), + .AXI_27_ARID(m_axi_hbm_arid[27*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_27_ARLEN(m_axi_hbm_arlen[27*8 +: 8]), + .AXI_27_ARSIZE(m_axi_hbm_arsize[27*3 +: 3]), + .AXI_27_ARVALID(m_axi_hbm_arvalid[27 +: 1]), + .AXI_27_ARREADY(m_axi_hbm_arready[27 +: 1]), + .AXI_27_RDATA_PARITY(), + .AXI_27_RDATA(m_axi_hbm_rdata[27*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_27_RID(m_axi_hbm_rid[27 +: 1]), + .AXI_27_RLAST(m_axi_hbm_rlast[27 +: 1]), + .AXI_27_RRESP(m_axi_hbm_rresp[27*2 +: 2]), + .AXI_27_RVALID(m_axi_hbm_rvalid[27 +: 1]), + .AXI_27_RREADY(m_axi_hbm_rready[27 +: 1]), + .AXI_27_AWADDR(m_axi_hbm_awaddr[27*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_27_AWBURST(m_axi_hbm_awburst[27*2 +: 2]), + .AXI_27_AWID(m_axi_hbm_awid[27*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_27_AWLEN(m_axi_hbm_awlen[27*8 +: 8]), + .AXI_27_AWSIZE(m_axi_hbm_awsize[27*3 +: 3]), + .AXI_27_AWVALID(m_axi_hbm_awvalid[27 +: 1]), + .AXI_27_AWREADY(m_axi_hbm_awready[27 +: 1]), + .AXI_27_WDATA(m_axi_hbm_wdata[27*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_27_WLAST(m_axi_hbm_wlast[27 +: 1]), + .AXI_27_WSTRB(m_axi_hbm_wstrb[27*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_27_WDATA_PARITY(32'd0), + .AXI_27_WVALID(m_axi_hbm_wvalid[27 +: 1]), + .AXI_27_WREADY(m_axi_hbm_wready[27 +: 1]), + .AXI_27_BID(m_axi_hbm_bid[27*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_27_BRESP(m_axi_hbm_bresp[27*2 +: 2]), + .AXI_27_BVALID(m_axi_hbm_bvalid[27 +: 1]), + .AXI_27_BREADY(m_axi_hbm_bready[27 +: 1]), + + .AXI_28_ACLK(hbm_clk[28 +: 1]), + .AXI_28_ARESET_N(!hbm_rst[28 +: 1]), + + .AXI_28_ARADDR(m_axi_hbm_araddr[28*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_28_ARBURST(m_axi_hbm_arburst[28*2 +: 2]), + .AXI_28_ARID(m_axi_hbm_arid[28*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_28_ARLEN(m_axi_hbm_arlen[28*8 +: 8]), + .AXI_28_ARSIZE(m_axi_hbm_arsize[28*3 +: 3]), + .AXI_28_ARVALID(m_axi_hbm_arvalid[28 +: 1]), + .AXI_28_ARREADY(m_axi_hbm_arready[28 +: 1]), + .AXI_28_RDATA_PARITY(), + .AXI_28_RDATA(m_axi_hbm_rdata[28*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_28_RID(m_axi_hbm_rid[28 +: 1]), + .AXI_28_RLAST(m_axi_hbm_rlast[28 +: 1]), + .AXI_28_RRESP(m_axi_hbm_rresp[28*2 +: 2]), + .AXI_28_RVALID(m_axi_hbm_rvalid[28 +: 1]), + .AXI_28_RREADY(m_axi_hbm_rready[28 +: 1]), + .AXI_28_AWADDR(m_axi_hbm_awaddr[28*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_28_AWBURST(m_axi_hbm_awburst[28*2 +: 2]), + .AXI_28_AWID(m_axi_hbm_awid[28*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_28_AWLEN(m_axi_hbm_awlen[28*8 +: 8]), + .AXI_28_AWSIZE(m_axi_hbm_awsize[28*3 +: 3]), + .AXI_28_AWVALID(m_axi_hbm_awvalid[28 +: 1]), + .AXI_28_AWREADY(m_axi_hbm_awready[28 +: 1]), + .AXI_28_WDATA(m_axi_hbm_wdata[28*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_28_WLAST(m_axi_hbm_wlast[28 +: 1]), + .AXI_28_WSTRB(m_axi_hbm_wstrb[28*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_28_WDATA_PARITY(32'd0), + .AXI_28_WVALID(m_axi_hbm_wvalid[28 +: 1]), + .AXI_28_WREADY(m_axi_hbm_wready[28 +: 1]), + .AXI_28_BID(m_axi_hbm_bid[28*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_28_BRESP(m_axi_hbm_bresp[28*2 +: 2]), + .AXI_28_BVALID(m_axi_hbm_bvalid[28 +: 1]), + .AXI_28_BREADY(m_axi_hbm_bready[28 +: 1]), + + .AXI_29_ACLK(hbm_clk[29 +: 1]), + .AXI_29_ARESET_N(!hbm_rst[29 +: 1]), + + .AXI_29_ARADDR(m_axi_hbm_araddr[29*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_29_ARBURST(m_axi_hbm_arburst[29*2 +: 2]), + .AXI_29_ARID(m_axi_hbm_arid[29*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_29_ARLEN(m_axi_hbm_arlen[29*8 +: 8]), + .AXI_29_ARSIZE(m_axi_hbm_arsize[29*3 +: 3]), + .AXI_29_ARVALID(m_axi_hbm_arvalid[29 +: 1]), + .AXI_29_ARREADY(m_axi_hbm_arready[29 +: 1]), + .AXI_29_RDATA_PARITY(), + .AXI_29_RDATA(m_axi_hbm_rdata[29*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_29_RID(m_axi_hbm_rid[29 +: 1]), + .AXI_29_RLAST(m_axi_hbm_rlast[29 +: 1]), + .AXI_29_RRESP(m_axi_hbm_rresp[29*2 +: 2]), + .AXI_29_RVALID(m_axi_hbm_rvalid[29 +: 1]), + .AXI_29_RREADY(m_axi_hbm_rready[29 +: 1]), + .AXI_29_AWADDR(m_axi_hbm_awaddr[29*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_29_AWBURST(m_axi_hbm_awburst[29*2 +: 2]), + .AXI_29_AWID(m_axi_hbm_awid[29*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_29_AWLEN(m_axi_hbm_awlen[29*8 +: 8]), + .AXI_29_AWSIZE(m_axi_hbm_awsize[29*3 +: 3]), + .AXI_29_AWVALID(m_axi_hbm_awvalid[29 +: 1]), + .AXI_29_AWREADY(m_axi_hbm_awready[29 +: 1]), + .AXI_29_WDATA(m_axi_hbm_wdata[29*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_29_WLAST(m_axi_hbm_wlast[29 +: 1]), + .AXI_29_WSTRB(m_axi_hbm_wstrb[29*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_29_WDATA_PARITY(32'd0), + .AXI_29_WVALID(m_axi_hbm_wvalid[29 +: 1]), + .AXI_29_WREADY(m_axi_hbm_wready[29 +: 1]), + .AXI_29_BID(m_axi_hbm_bid[29*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_29_BRESP(m_axi_hbm_bresp[29*2 +: 2]), + .AXI_29_BVALID(m_axi_hbm_bvalid[29 +: 1]), + .AXI_29_BREADY(m_axi_hbm_bready[29 +: 1]), + + .AXI_30_ACLK(hbm_clk[30 +: 1]), + .AXI_30_ARESET_N(!hbm_rst[30 +: 1]), + + .AXI_30_ARADDR(m_axi_hbm_araddr[30*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_30_ARBURST(m_axi_hbm_arburst[30*2 +: 2]), + .AXI_30_ARID(m_axi_hbm_arid[30*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_30_ARLEN(m_axi_hbm_arlen[30*8 +: 8]), + .AXI_30_ARSIZE(m_axi_hbm_arsize[30*3 +: 3]), + .AXI_30_ARVALID(m_axi_hbm_arvalid[30 +: 1]), + .AXI_30_ARREADY(m_axi_hbm_arready[30 +: 1]), + .AXI_30_RDATA_PARITY(), + .AXI_30_RDATA(m_axi_hbm_rdata[30*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_30_RID(m_axi_hbm_rid[30 +: 1]), + .AXI_30_RLAST(m_axi_hbm_rlast[30 +: 1]), + .AXI_30_RRESP(m_axi_hbm_rresp[30*2 +: 2]), + .AXI_30_RVALID(m_axi_hbm_rvalid[30 +: 1]), + .AXI_30_RREADY(m_axi_hbm_rready[30 +: 1]), + .AXI_30_AWADDR(m_axi_hbm_awaddr[30*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_30_AWBURST(m_axi_hbm_awburst[30*2 +: 2]), + .AXI_30_AWID(m_axi_hbm_awid[30*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_30_AWLEN(m_axi_hbm_awlen[30*8 +: 8]), + .AXI_30_AWSIZE(m_axi_hbm_awsize[30*3 +: 3]), + .AXI_30_AWVALID(m_axi_hbm_awvalid[30 +: 1]), + .AXI_30_AWREADY(m_axi_hbm_awready[30 +: 1]), + .AXI_30_WDATA(m_axi_hbm_wdata[30*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_30_WLAST(m_axi_hbm_wlast[30 +: 1]), + .AXI_30_WSTRB(m_axi_hbm_wstrb[30*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_30_WDATA_PARITY(32'd0), + .AXI_30_WVALID(m_axi_hbm_wvalid[30 +: 1]), + .AXI_30_WREADY(m_axi_hbm_wready[30 +: 1]), + .AXI_30_BID(m_axi_hbm_bid[30*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_30_BRESP(m_axi_hbm_bresp[30*2 +: 2]), + .AXI_30_BVALID(m_axi_hbm_bvalid[30 +: 1]), + .AXI_30_BREADY(m_axi_hbm_bready[30 +: 1]), + + .AXI_31_ACLK(hbm_clk[31 +: 1]), + .AXI_31_ARESET_N(!hbm_rst[31 +: 1]), + + .AXI_31_ARADDR(m_axi_hbm_araddr[31*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_31_ARBURST(m_axi_hbm_arburst[31*2 +: 2]), + .AXI_31_ARID(m_axi_hbm_arid[31*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_31_ARLEN(m_axi_hbm_arlen[31*8 +: 8]), + .AXI_31_ARSIZE(m_axi_hbm_arsize[31*3 +: 3]), + .AXI_31_ARVALID(m_axi_hbm_arvalid[31 +: 1]), + .AXI_31_ARREADY(m_axi_hbm_arready[31 +: 1]), + .AXI_31_RDATA_PARITY(), + .AXI_31_RDATA(m_axi_hbm_rdata[31*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_31_RID(m_axi_hbm_rid[31 +: 1]), + .AXI_31_RLAST(m_axi_hbm_rlast[31 +: 1]), + .AXI_31_RRESP(m_axi_hbm_rresp[31*2 +: 2]), + .AXI_31_RVALID(m_axi_hbm_rvalid[31 +: 1]), + .AXI_31_RREADY(m_axi_hbm_rready[31 +: 1]), + .AXI_31_AWADDR(m_axi_hbm_awaddr[31*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_31_AWBURST(m_axi_hbm_awburst[31*2 +: 2]), + .AXI_31_AWID(m_axi_hbm_awid[31*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_31_AWLEN(m_axi_hbm_awlen[31*8 +: 8]), + .AXI_31_AWSIZE(m_axi_hbm_awsize[31*3 +: 3]), + .AXI_31_AWVALID(m_axi_hbm_awvalid[31 +: 1]), + .AXI_31_AWREADY(m_axi_hbm_awready[31 +: 1]), + .AXI_31_WDATA(m_axi_hbm_wdata[31*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_31_WLAST(m_axi_hbm_wlast[31 +: 1]), + .AXI_31_WSTRB(m_axi_hbm_wstrb[31*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_31_WDATA_PARITY(32'd0), + .AXI_31_WVALID(m_axi_hbm_wvalid[31 +: 1]), + .AXI_31_WREADY(m_axi_hbm_wready[31 +: 1]), + .AXI_31_BID(m_axi_hbm_bid[31*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_31_BRESP(m_axi_hbm_bresp[31*2 +: 2]), + .AXI_31_BVALID(m_axi_hbm_bvalid[31 +: 1]), + .AXI_31_BREADY(m_axi_hbm_bready[31 +: 1]), + + .DRAM_0_STAT_CATTRIP(hbm_cattrip_1), + .DRAM_0_STAT_TEMP(hbm_temp_1), + .DRAM_1_STAT_CATTRIP(hbm_cattrip_2), + .DRAM_1_STAT_TEMP(hbm_temp_2) +); + +assign hbm_status = {HBM_CH{1'b1}}; + +end else begin + +assign hbm_clk = 0; +assign hbm_rst = 0; + +assign m_axi_hbm_awready = 0; +assign m_axi_hbm_wready = 0; +assign m_axi_hbm_bid = 0; +assign m_axi_hbm_bresp = 0; +assign m_axi_hbm_bvalid = 0; +assign m_axi_hbm_arready = 0; +assign m_axi_hbm_rid = 0; +assign m_axi_hbm_rdata = 0; +assign m_axi_hbm_rresp = 0; +assign m_axi_hbm_rlast = 0; +assign m_axi_hbm_rvalid = 0; + +assign hbm_status = 0; + +end + +endgenerate + fpga_core #( // FW and board IDs .FPGA_ID(FPGA_ID), @@ -1468,6 +3180,24 @@ fpga_core #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + .HBM_CH(HBM_CH), + .HBM_ENABLE(HBM_ENABLE), + .HBM_GROUP_SIZE(HBM_GROUP_SIZE), + .AXI_HBM_DATA_WIDTH(AXI_HBM_DATA_WIDTH), + .AXI_HBM_ADDR_WIDTH(AXI_HBM_ADDR_WIDTH), + .AXI_HBM_STRB_WIDTH(AXI_HBM_STRB_WIDTH), + .AXI_HBM_ID_WIDTH(AXI_HBM_ID_WIDTH), + .AXI_HBM_MAX_BURST_LEN(AXI_HBM_MAX_BURST_LEN), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1747,6 +3477,97 @@ core_inst ( .qsfp1_drp_do(qsfp1_drp_do), .qsfp1_drp_rdy(qsfp1_drp_rdy), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + + /* + * HBM + */ + .hbm_clk(hbm_clk), + .hbm_rst(hbm_rst), + .m_axi_hbm_awid(m_axi_hbm_awid), + .m_axi_hbm_awaddr(m_axi_hbm_awaddr), + .m_axi_hbm_awlen(m_axi_hbm_awlen), + .m_axi_hbm_awsize(m_axi_hbm_awsize), + .m_axi_hbm_awburst(m_axi_hbm_awburst), + .m_axi_hbm_awlock(m_axi_hbm_awlock), + .m_axi_hbm_awcache(m_axi_hbm_awcache), + .m_axi_hbm_awprot(m_axi_hbm_awprot), + .m_axi_hbm_awqos(m_axi_hbm_awqos), + .m_axi_hbm_awvalid(m_axi_hbm_awvalid), + .m_axi_hbm_awready(m_axi_hbm_awready), + .m_axi_hbm_wdata(m_axi_hbm_wdata), + .m_axi_hbm_wstrb(m_axi_hbm_wstrb), + .m_axi_hbm_wlast(m_axi_hbm_wlast), + .m_axi_hbm_wvalid(m_axi_hbm_wvalid), + .m_axi_hbm_wready(m_axi_hbm_wready), + .m_axi_hbm_bid(m_axi_hbm_bid), + .m_axi_hbm_bresp(m_axi_hbm_bresp), + .m_axi_hbm_bvalid(m_axi_hbm_bvalid), + .m_axi_hbm_bready(m_axi_hbm_bready), + .m_axi_hbm_arid(m_axi_hbm_arid), + .m_axi_hbm_araddr(m_axi_hbm_araddr), + .m_axi_hbm_arlen(m_axi_hbm_arlen), + .m_axi_hbm_arsize(m_axi_hbm_arsize), + .m_axi_hbm_arburst(m_axi_hbm_arburst), + .m_axi_hbm_arlock(m_axi_hbm_arlock), + .m_axi_hbm_arcache(m_axi_hbm_arcache), + .m_axi_hbm_arprot(m_axi_hbm_arprot), + .m_axi_hbm_arqos(m_axi_hbm_arqos), + .m_axi_hbm_arvalid(m_axi_hbm_arvalid), + .m_axi_hbm_arready(m_axi_hbm_arready), + .m_axi_hbm_rid(m_axi_hbm_rid), + .m_axi_hbm_rdata(m_axi_hbm_rdata), + .m_axi_hbm_rresp(m_axi_hbm_rresp), + .m_axi_hbm_rlast(m_axi_hbm_rlast), + .m_axi_hbm_rvalid(m_axi_hbm_rvalid), + .m_axi_hbm_rready(m_axi_hbm_rready), + + .hbm_status(hbm_status), + /* * QSPI flash */ diff --git a/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v index 8150d0708..097e915cf 100644 --- a/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v @@ -122,6 +122,24 @@ module fpga_core # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // RAM configuration + parameter DDR_CH = 2, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 34, + parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + parameter HBM_CH = 32, + parameter HBM_ENABLE = 1, + parameter HBM_GROUP_SIZE = 32, + parameter AXI_HBM_DATA_WIDTH = 256, + parameter AXI_HBM_ADDR_WIDTH = 33, + parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8), + parameter AXI_HBM_ID_WIDTH = 6, + parameter AXI_HBM_MAX_BURST_LEN = 256, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -401,6 +419,98 @@ module fpga_core # input wire [15:0] qsfp1_drp_do, input wire qsfp1_drp_rdy, + /* + * DDR + */ + input wire [DDR_CH-1:0] ddr_clk, + input wire [DDR_CH-1:0] ddr_rst, + + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, + output wire [DDR_CH-1:0] m_axi_ddr_awlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, + output wire [DDR_CH-1:0] m_axi_ddr_awvalid, + input wire [DDR_CH-1:0] m_axi_ddr_awready, + output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, + output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, + output wire [DDR_CH-1:0] m_axi_ddr_wlast, + output wire [DDR_CH-1:0] m_axi_ddr_wvalid, + input wire [DDR_CH-1:0] m_axi_ddr_wready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, + input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, + input wire [DDR_CH-1:0] m_axi_ddr_bvalid, + output wire [DDR_CH-1:0] m_axi_ddr_bready, + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, + output wire [DDR_CH-1:0] m_axi_ddr_arlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, + output wire [DDR_CH-1:0] m_axi_ddr_arvalid, + input wire [DDR_CH-1:0] m_axi_ddr_arready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, + input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, + input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, + input wire [DDR_CH-1:0] m_axi_ddr_rlast, + input wire [DDR_CH-1:0] m_axi_ddr_rvalid, + output wire [DDR_CH-1:0] m_axi_ddr_rready, + + input wire [DDR_CH-1:0] ddr_status, + + /* + * HBM + */ + input wire [HBM_CH-1:0] hbm_clk, + input wire [HBM_CH-1:0] hbm_rst, + + output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_awid, + output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_awaddr, + output wire [HBM_CH*8-1:0] m_axi_hbm_awlen, + output wire [HBM_CH*3-1:0] m_axi_hbm_awsize, + output wire [HBM_CH*2-1:0] m_axi_hbm_awburst, + output wire [HBM_CH-1:0] m_axi_hbm_awlock, + output wire [HBM_CH*4-1:0] m_axi_hbm_awcache, + output wire [HBM_CH*3-1:0] m_axi_hbm_awprot, + output wire [HBM_CH*4-1:0] m_axi_hbm_awqos, + output wire [HBM_CH-1:0] m_axi_hbm_awvalid, + input wire [HBM_CH-1:0] m_axi_hbm_awready, + output wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_wdata, + output wire [HBM_CH*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_wstrb, + output wire [HBM_CH-1:0] m_axi_hbm_wlast, + output wire [HBM_CH-1:0] m_axi_hbm_wvalid, + input wire [HBM_CH-1:0] m_axi_hbm_wready, + input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_bid, + input wire [HBM_CH*2-1:0] m_axi_hbm_bresp, + input wire [HBM_CH-1:0] m_axi_hbm_bvalid, + output wire [HBM_CH-1:0] m_axi_hbm_bready, + output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_arid, + output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_araddr, + output wire [HBM_CH*8-1:0] m_axi_hbm_arlen, + output wire [HBM_CH*3-1:0] m_axi_hbm_arsize, + output wire [HBM_CH*2-1:0] m_axi_hbm_arburst, + output wire [HBM_CH-1:0] m_axi_hbm_arlock, + output wire [HBM_CH*4-1:0] m_axi_hbm_arcache, + output wire [HBM_CH*3-1:0] m_axi_hbm_arprot, + output wire [HBM_CH*4-1:0] m_axi_hbm_arqos, + output wire [HBM_CH-1:0] m_axi_hbm_arvalid, + input wire [HBM_CH-1:0] m_axi_hbm_arready, + input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_rid, + input wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_rdata, + input wire [HBM_CH*2-1:0] m_axi_hbm_rresp, + input wire [HBM_CH-1:0] m_axi_hbm_rlast, + input wire [HBM_CH-1:0] m_axi_hbm_rvalid, + output wire [HBM_CH-1:0] m_axi_hbm_rready, + + input wire [HBM_CH-1:0] hbm_status, + /* * QSPI flash */ @@ -1059,6 +1169,40 @@ mqnic_core_pcie_us #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .DDR_GROUP_SIZE(1), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_AWUSER_ENABLE(0), + .AXI_DDR_WUSER_ENABLE(0), + .AXI_DDR_BUSER_ENABLE(0), + .AXI_DDR_ARUSER_ENABLE(0), + .AXI_DDR_RUSER_ENABLE(0), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + .AXI_DDR_FIXED_BURST(0), + .AXI_DDR_WRAP_BURST(1), + .HBM_CH(HBM_CH), + .HBM_ENABLE(HBM_ENABLE), + .HBM_GROUP_SIZE(HBM_GROUP_SIZE), + .AXI_HBM_DATA_WIDTH(AXI_HBM_DATA_WIDTH), + .AXI_HBM_ADDR_WIDTH(AXI_HBM_ADDR_WIDTH), + .AXI_HBM_STRB_WIDTH(AXI_HBM_STRB_WIDTH), + .AXI_HBM_ID_WIDTH(AXI_HBM_ID_WIDTH), + .AXI_HBM_AWUSER_ENABLE(0), + .AXI_HBM_WUSER_ENABLE(0), + .AXI_HBM_BUSER_ENABLE(0), + .AXI_HBM_ARUSER_ENABLE(0), + .AXI_HBM_RUSER_ENABLE(0), + .AXI_HBM_MAX_BURST_LEN(AXI_HBM_MAX_BURST_LEN), + .AXI_HBM_NARROW_BURST(0), + .AXI_HBM_FIXED_BURST(0), + .AXI_HBM_WRAP_BURST(1), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1336,6 +1480,108 @@ core_inst ( .eth_rx_status(eth_rx_status), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awuser(), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wuser(), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_buser(0), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_aruser(), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_ruser(0), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + + /* + * HBM + */ + .hbm_clk(hbm_clk), + .hbm_rst(hbm_rst), + + .m_axi_hbm_awid(m_axi_hbm_awid), + .m_axi_hbm_awaddr(m_axi_hbm_awaddr), + .m_axi_hbm_awlen(m_axi_hbm_awlen), + .m_axi_hbm_awsize(m_axi_hbm_awsize), + .m_axi_hbm_awburst(m_axi_hbm_awburst), + .m_axi_hbm_awlock(m_axi_hbm_awlock), + .m_axi_hbm_awcache(m_axi_hbm_awcache), + .m_axi_hbm_awprot(m_axi_hbm_awprot), + .m_axi_hbm_awqos(m_axi_hbm_awqos), + .m_axi_hbm_awuser(), + .m_axi_hbm_awvalid(m_axi_hbm_awvalid), + .m_axi_hbm_awready(m_axi_hbm_awready), + .m_axi_hbm_wdata(m_axi_hbm_wdata), + .m_axi_hbm_wstrb(m_axi_hbm_wstrb), + .m_axi_hbm_wlast(m_axi_hbm_wlast), + .m_axi_hbm_wuser(), + .m_axi_hbm_wvalid(m_axi_hbm_wvalid), + .m_axi_hbm_wready(m_axi_hbm_wready), + .m_axi_hbm_bid(m_axi_hbm_bid), + .m_axi_hbm_bresp(m_axi_hbm_bresp), + .m_axi_hbm_buser(0), + .m_axi_hbm_bvalid(m_axi_hbm_bvalid), + .m_axi_hbm_bready(m_axi_hbm_bready), + .m_axi_hbm_arid(m_axi_hbm_arid), + .m_axi_hbm_araddr(m_axi_hbm_araddr), + .m_axi_hbm_arlen(m_axi_hbm_arlen), + .m_axi_hbm_arsize(m_axi_hbm_arsize), + .m_axi_hbm_arburst(m_axi_hbm_arburst), + .m_axi_hbm_arlock(m_axi_hbm_arlock), + .m_axi_hbm_arcache(m_axi_hbm_arcache), + .m_axi_hbm_arprot(m_axi_hbm_arprot), + .m_axi_hbm_arqos(m_axi_hbm_arqos), + .m_axi_hbm_aruser(), + .m_axi_hbm_arvalid(m_axi_hbm_arvalid), + .m_axi_hbm_arready(m_axi_hbm_arready), + .m_axi_hbm_rid(m_axi_hbm_rid), + .m_axi_hbm_rdata(m_axi_hbm_rdata), + .m_axi_hbm_rresp(m_axi_hbm_rresp), + .m_axi_hbm_rlast(m_axi_hbm_rlast), + .m_axi_hbm_ruser(0), + .m_axi_hbm_rvalid(m_axi_hbm_rvalid), + .m_axi_hbm_rready(m_axi_hbm_rready), + + .hbm_status(hbm_status), + /* * Statistics input */ diff --git a/fpga/mqnic/AU50/fpga_100g/README.md b/fpga/mqnic/AU50/fpga_100g/README.md index b3fea0b65..913783084 100644 --- a/fpga/mqnic/AU50/fpga_100g/README.md +++ b/fpga/mqnic/AU50/fpga_100g/README.md @@ -7,6 +7,7 @@ This design targets the Xilinx Alveo U50 FPGA board. * FPGA: xcu50-fsvh2104-2-e * MAC: Xilinx 100G CMAC * PHY: 100G CAUI-4 CMAC and internal GTY transceivers +* RAM: 8GB HBM2 ## How to build diff --git a/fpga/mqnic/AU50/fpga_100g/fpga.xdc b/fpga/mqnic/AU50/fpga_100g/fpga.xdc index b02e3f829..621a99f56 100644 --- a/fpga/mqnic/AU50/fpga_100g/fpga.xdc +++ b/fpga/mqnic/AU50/fpga_100g/fpga.xdc @@ -23,9 +23,9 @@ set_operating_conditions -design_power_budget 63 #create_clock -period 10 -name clk_100mhz_0 [get_ports clk_100mhz_0_p] # 100 MHz -#set_property -dict {LOC BB18 IOSTANDARD LVDS} [get_ports clk_100mhz_1_p] -#set_property -dict {LOC BC18 IOSTANDARD LVDS} [get_ports clk_100mhz_1_n] -#create_clock -period 10 -name clk_100mhz_1 [get_ports clk_100mhz_1_p] +set_property -dict {LOC BB18 IOSTANDARD LVDS} [get_ports clk_100mhz_1_p] +set_property -dict {LOC BC18 IOSTANDARD LVDS} [get_ports clk_100mhz_1_n] +create_clock -period 10 -name clk_100mhz_1 [get_ports clk_100mhz_1_p] # LEDs set_property -dict {LOC E18 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp_led_act] diff --git a/fpga/mqnic/AU50/fpga_100g/fpga/Makefile b/fpga/mqnic/AU50/fpga_100g/fpga/Makefile index edc4c334a..a3b21841d 100644 --- a/fpga/mqnic/AU50/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/AU50/fpga_100g/fpga/Makefile @@ -117,11 +117,13 @@ XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_port.tcl XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl +XDC_FILES += hbm.xdc # IP IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl IP_TCL_FILES += ip/cmac_usplus_0.tcl IP_TCL_FILES += ip/cms.tcl +IP_TCL_FILES += ip/hbm_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/AU50/fpga_100g/fpga/config.tcl b/fpga/mqnic/AU50/fpga_100g/fpga/config.tcl index 5ad3e79b4..641a00ff9 100644 --- a/fpga/mqnic/AU50/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/AU50/fpga_100g/fpga/config.tcl @@ -136,6 +136,13 @@ dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "131072" dict set params RX_RAM_SIZE "131072" + +# RAM configuration +dict set params HBM_CH "32" +dict set params HBM_ENABLE "1" +dict set params HBM_GROUP_SIZE "32" +dict set params AXI_HBM_ADDR_WIDTH "33" +dict set params AXI_HBM_MAX_BURST_LEN "256" # Application block configuration dict set params APP_ID "32'h00000000" diff --git a/fpga/mqnic/AU50/fpga_100g/hbm.xdc b/fpga/mqnic/AU50/fpga_100g/hbm.xdc new file mode 100644 index 000000000..aa147b0a5 --- /dev/null +++ b/fpga/mqnic/AU50/fpga_100g/hbm.xdc @@ -0,0 +1,2 @@ +# force debug hub to use HBM APB clock to prevent CDC issues +connect_debug_port dbg_hub/clk [get_nets */APB_0_PCLK] diff --git a/fpga/mqnic/AU50/fpga_100g/ip/hbm_0.tcl b/fpga/mqnic/AU50/fpga_100g/ip/hbm_0.tcl new file mode 100644 index 000000000..a8cbc2874 --- /dev/null +++ b/fpga/mqnic/AU50/fpga_100g/ip/hbm_0.tcl @@ -0,0 +1,23 @@ + +create_ip -name hbm -vendor xilinx.com -library ip -module_name hbm_0 + +set_property -dict [list \ + CONFIG.USER_HBM_DENSITY {8GB} \ + CONFIG.USER_HBM_STACK {2} \ + CONFIG.USER_MC0_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC1_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC2_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC3_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC4_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC5_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC6_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC7_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC8_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC9_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC10_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC11_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC12_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC13_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC14_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC15_ENABLE_ECC_CORRECTION {true} +] [get_ips hbm_0] diff --git a/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v b/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v index 10c6d41c7..19fc83f83 100644 --- a/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/AU50/fpga_100g/rtl/fpga.v @@ -109,6 +109,13 @@ module fpga # parameter TX_RAM_SIZE = 131072, parameter RX_RAM_SIZE = 131072, + // RAM configuration + parameter HBM_CH = 32, + parameter HBM_ENABLE = 1, + parameter HBM_GROUP_SIZE = 32, + parameter AXI_HBM_ADDR_WIDTH = 33, + parameter AXI_HBM_MAX_BURST_LEN = 256, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -173,6 +180,14 @@ module fpga # parameter STAT_ID_WIDTH = 12 ) ( + /* + * Clock and reset + */ + // input wire clk_100mhz_0_p, + // input wire clk_100mhz_0_n, + input wire clk_100mhz_1_p, + input wire clk_100mhz_1_n, + /* * GPIO */ @@ -230,6 +245,11 @@ parameter PTP_SEPARATE_RX_CLOCK = 1; // Interface configuration parameter TX_TAG_WIDTH = 16; +// RAM configuration +parameter AXI_HBM_DATA_WIDTH = 256; +parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8); +parameter AXI_HBM_ID_WIDTH = 6; + // Ethernet interface configuration parameter AXIS_ETH_DATA_WIDTH = 512; parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; @@ -347,9 +367,6 @@ sync_reset_125mhz_inst ( .out(rst_125mhz_int) ); -// GPIO -assign hbm_cattrip = 1'b0; - // Flash wire qspi_clk_int; wire [3:0] qspi_dq_int; @@ -559,6 +576,9 @@ wire [1:0] axil_cms_rresp_int; wire axil_cms_rvalid_int; wire axil_cms_rready_int; +wire [7:0] hbm_temp_1; +wire [7:0] hbm_temp_2; + axil_cdc #( .DATA_WIDTH(32), .ADDR_WIDTH(18) @@ -612,8 +632,8 @@ cms_wrapper cms_inst ( .aclk_ctrl_0(clk_50mhz_int), .aresetn_ctrl_0(~rst_50mhz_int), - .hbm_temp_1_0(7'd0), - .hbm_temp_2_0(7'd0), + .hbm_temp_1_0(hbm_temp_1), + .hbm_temp_2_0(hbm_temp_2), .interrupt_hbm_cattrip_0(hbm_cattrip), .interrupt_host_0(), .s_axi_ctrl_0_araddr(axil_cms_araddr_int), @@ -1351,6 +1371,1356 @@ sync_reset_ptp_rst_inst ( assign qsfp_led_stat_g = qsfp_rx_status; +// HBM +wire [HBM_CH-1:0] hbm_clk; +wire [HBM_CH-1:0] hbm_rst; + +wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_awid; +wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_awaddr; +wire [HBM_CH*8-1:0] m_axi_hbm_awlen; +wire [HBM_CH*3-1:0] m_axi_hbm_awsize; +wire [HBM_CH*2-1:0] m_axi_hbm_awburst; +wire [HBM_CH-1:0] m_axi_hbm_awlock; +wire [HBM_CH*4-1:0] m_axi_hbm_awcache; +wire [HBM_CH*3-1:0] m_axi_hbm_awprot; +wire [HBM_CH*4-1:0] m_axi_hbm_awqos; +wire [HBM_CH-1:0] m_axi_hbm_awvalid; +wire [HBM_CH-1:0] m_axi_hbm_awready; +wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_wdata; +wire [HBM_CH*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_wstrb; +wire [HBM_CH-1:0] m_axi_hbm_wlast; +wire [HBM_CH-1:0] m_axi_hbm_wvalid; +wire [HBM_CH-1:0] m_axi_hbm_wready; +wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_bid; +wire [HBM_CH*2-1:0] m_axi_hbm_bresp; +wire [HBM_CH-1:0] m_axi_hbm_bvalid; +wire [HBM_CH-1:0] m_axi_hbm_bready; +wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_arid; +wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_araddr; +wire [HBM_CH*8-1:0] m_axi_hbm_arlen; +wire [HBM_CH*3-1:0] m_axi_hbm_arsize; +wire [HBM_CH*2-1:0] m_axi_hbm_arburst; +wire [HBM_CH-1:0] m_axi_hbm_arlock; +wire [HBM_CH*4-1:0] m_axi_hbm_arcache; +wire [HBM_CH*3-1:0] m_axi_hbm_arprot; +wire [HBM_CH*4-1:0] m_axi_hbm_arqos; +wire [HBM_CH-1:0] m_axi_hbm_arvalid; +wire [HBM_CH-1:0] m_axi_hbm_arready; +wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_rid; +wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_rdata; +wire [HBM_CH*2-1:0] m_axi_hbm_rresp; +wire [HBM_CH-1:0] m_axi_hbm_rlast; +wire [HBM_CH-1:0] m_axi_hbm_rvalid; +wire [HBM_CH-1:0] m_axi_hbm_rready; + +wire [HBM_CH-1:0] hbm_status; + +wire clk_100mhz_1_ibufg; + +IBUFGDS #( + .DIFF_TERM("FALSE"), + .IBUF_LOW_PWR("FALSE") +) +clk_100mhz_1_ibufg_inst ( + .O (clk_100mhz_1_ibufg), + .I (clk_100mhz_1_p), + .IB (clk_100mhz_1_n) +); + +generate + +if (HBM_ENABLE) begin + +wire hbm_ref_clk; + +wire hbm_mmcm_rst; +wire hbm_mmcm_locked; +wire hbm_mmcm_clkfb; + +wire hbm_axi_clk_mmcm; +wire hbm_axi_clk; +wire hbm_axi_rst_int; +wire hbm_axi_rst; + +BUFG +hbm_ref_clk_bufg_inst ( + .I(clk_100mhz_1_ibufg), + .O(hbm_ref_clk) +); + +// HBM MMCM instance +// 100 MHz in, 450 MHz out +// PFD range: 10 MHz to 500 MHz +// VCO range: 800 MHz to 1600 MHz +// M = 9, D = 1 sets Fvco = 900 MHz +// Divide by 2 to get output frequency of 450 MHz +MMCME4_BASE #( + .BANDWIDTH("OPTIMIZED"), + .CLKOUT0_DIVIDE_F(2), + .CLKOUT0_DUTY_CYCLE(0.5), + .CLKOUT0_PHASE(0), + .CLKOUT1_DIVIDE(1), + .CLKOUT1_DUTY_CYCLE(0.5), + .CLKOUT1_PHASE(0), + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.5), + .CLKOUT2_PHASE(0), + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.5), + .CLKOUT3_PHASE(0), + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.5), + .CLKOUT4_PHASE(0), + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.5), + .CLKOUT5_PHASE(0), + .CLKOUT6_DIVIDE(1), + .CLKOUT6_DUTY_CYCLE(0.5), + .CLKOUT6_PHASE(0), + .CLKFBOUT_MULT_F(9), + .CLKFBOUT_PHASE(0), + .DIVCLK_DIVIDE(1), + .REF_JITTER1(0.010), + .CLKIN1_PERIOD(10.000), + .STARTUP_WAIT("FALSE"), + .CLKOUT4_CASCADE("FALSE") +) +hbm_mmcm_inst ( + .CLKIN1(clk_100mhz_1_ibufg), + .CLKFBIN(hbm_mmcm_clkfb), + .RST(hbm_mmcm_rst), + .PWRDWN(1'b0), + .CLKOUT0(hbm_axi_clk_mmcm), + .CLKOUT0B(), + .CLKOUT1(), + .CLKOUT1B(), + .CLKOUT2(), + .CLKOUT2B(), + .CLKOUT3(), + .CLKOUT3B(), + .CLKOUT4(), + .CLKOUT5(), + .CLKOUT6(), + .CLKFBOUT(hbm_mmcm_clkfb), + .CLKFBOUTB(), + .LOCKED(hbm_mmcm_locked) +); + +BUFG +hbm_axi_clk_bufg_inst ( + .I(hbm_axi_clk_mmcm), + .O(hbm_axi_clk) +); + +sync_reset #( + .N(4) +) +sync_reset_hbm_axi_inst ( + .clk(hbm_axi_clk), + .rst(~hbm_mmcm_locked), + .out(hbm_axi_rst_int) +); + +// extra register for hbm_axi_rst signal +(* shreg_extract = "no" *) +reg hbm_axi_rst_reg_1 = 1'b1; +(* shreg_extract = "no" *) +reg hbm_axi_rst_reg_2 = 1'b1; + +assign hbm_axi_rst = hbm_axi_rst_reg_2; + +always @(posedge hbm_axi_clk) begin + hbm_axi_rst_reg_1 <= hbm_axi_rst_int; + hbm_axi_rst_reg_2 <= hbm_axi_rst_reg_1; +end + +wire hbm_cattrip_1; +wire hbm_cattrip_2; + +assign hbm_cattrip = hbm_cattrip_1 | hbm_cattrip_2; + +assign hbm_clk = {HBM_CH{hbm_axi_clk}}; +assign hbm_rst = {HBM_CH{hbm_axi_rst}}; + +hbm_0 hbm_inst ( + .HBM_REF_CLK_0(hbm_ref_clk), + .HBM_REF_CLK_1(hbm_ref_clk), + + .APB_0_PWDATA(32'd0), + .APB_0_PADDR(22'd0), + .APB_0_PCLK(hbm_ref_clk), + .APB_0_PENABLE(1'b0), + .APB_0_PRESET_N(1'b1), + .APB_0_PSEL(1'b0), + .APB_0_PWRITE(1'b0), + .APB_0_PRDATA(), + .APB_0_PREADY(), + .APB_0_PSLVERR(), + .apb_complete_0(), + + .APB_1_PWDATA(32'd0), + .APB_1_PADDR(22'd0), + .APB_1_PCLK(hbm_ref_clk), + .APB_1_PENABLE(1'b0), + .APB_1_PRESET_N(1'b1), + .APB_1_PSEL(1'b0), + .APB_1_PWRITE(1'b0), + .APB_1_PRDATA(), + .APB_1_PREADY(), + .APB_1_PSLVERR(), + .apb_complete_1(), + + .AXI_00_ACLK(hbm_clk[0 +: 1]), + .AXI_00_ARESET_N(!hbm_rst[0 +: 1]), + + .AXI_00_ARADDR(m_axi_hbm_araddr[0*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_00_ARBURST(m_axi_hbm_arburst[0*2 +: 2]), + .AXI_00_ARID(m_axi_hbm_arid[0*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_00_ARLEN(m_axi_hbm_arlen[0*8 +: 8]), + .AXI_00_ARSIZE(m_axi_hbm_arsize[0*3 +: 3]), + .AXI_00_ARVALID(m_axi_hbm_arvalid[0 +: 1]), + .AXI_00_ARREADY(m_axi_hbm_arready[0 +: 1]), + .AXI_00_RDATA_PARITY(), + .AXI_00_RDATA(m_axi_hbm_rdata[0*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_00_RID(m_axi_hbm_rid[0 +: 1]), + .AXI_00_RLAST(m_axi_hbm_rlast[0 +: 1]), + .AXI_00_RRESP(m_axi_hbm_rresp[0*2 +: 2]), + .AXI_00_RVALID(m_axi_hbm_rvalid[0 +: 1]), + .AXI_00_RREADY(m_axi_hbm_rready[0 +: 1]), + .AXI_00_AWADDR(m_axi_hbm_awaddr[0*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_00_AWBURST(m_axi_hbm_awburst[0*2 +: 2]), + .AXI_00_AWID(m_axi_hbm_awid[0*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_00_AWLEN(m_axi_hbm_awlen[0*8 +: 8]), + .AXI_00_AWSIZE(m_axi_hbm_awsize[0*3 +: 3]), + .AXI_00_AWVALID(m_axi_hbm_awvalid[0 +: 1]), + .AXI_00_AWREADY(m_axi_hbm_awready[0 +: 1]), + .AXI_00_WDATA(m_axi_hbm_wdata[0*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_00_WLAST(m_axi_hbm_wlast[0 +: 1]), + .AXI_00_WSTRB(m_axi_hbm_wstrb[0*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_00_WDATA_PARITY(32'd0), + .AXI_00_WVALID(m_axi_hbm_wvalid[0 +: 1]), + .AXI_00_WREADY(m_axi_hbm_wready[0 +: 1]), + .AXI_00_BID(m_axi_hbm_bid[0*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_00_BRESP(m_axi_hbm_bresp[0*2 +: 2]), + .AXI_00_BVALID(m_axi_hbm_bvalid[0 +: 1]), + .AXI_00_BREADY(m_axi_hbm_bready[0 +: 1]), + + .AXI_01_ACLK(hbm_clk[1 +: 1]), + .AXI_01_ARESET_N(!hbm_rst[1 +: 1]), + + .AXI_01_ARADDR(m_axi_hbm_araddr[1*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_01_ARBURST(m_axi_hbm_arburst[1*2 +: 2]), + .AXI_01_ARID(m_axi_hbm_arid[1*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_01_ARLEN(m_axi_hbm_arlen[1*8 +: 8]), + .AXI_01_ARSIZE(m_axi_hbm_arsize[1*3 +: 3]), + .AXI_01_ARVALID(m_axi_hbm_arvalid[1 +: 1]), + .AXI_01_ARREADY(m_axi_hbm_arready[1 +: 1]), + .AXI_01_RDATA_PARITY(), + .AXI_01_RDATA(m_axi_hbm_rdata[1*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_01_RID(m_axi_hbm_rid[1 +: 1]), + .AXI_01_RLAST(m_axi_hbm_rlast[1 +: 1]), + .AXI_01_RRESP(m_axi_hbm_rresp[1*2 +: 2]), + .AXI_01_RVALID(m_axi_hbm_rvalid[1 +: 1]), + .AXI_01_RREADY(m_axi_hbm_rready[1 +: 1]), + .AXI_01_AWADDR(m_axi_hbm_awaddr[1*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_01_AWBURST(m_axi_hbm_awburst[1*2 +: 2]), + .AXI_01_AWID(m_axi_hbm_awid[1*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_01_AWLEN(m_axi_hbm_awlen[1*8 +: 8]), + .AXI_01_AWSIZE(m_axi_hbm_awsize[1*3 +: 3]), + .AXI_01_AWVALID(m_axi_hbm_awvalid[1 +: 1]), + .AXI_01_AWREADY(m_axi_hbm_awready[1 +: 1]), + .AXI_01_WDATA(m_axi_hbm_wdata[1*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_01_WLAST(m_axi_hbm_wlast[1 +: 1]), + .AXI_01_WSTRB(m_axi_hbm_wstrb[1*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_01_WDATA_PARITY(32'd0), + .AXI_01_WVALID(m_axi_hbm_wvalid[1 +: 1]), + .AXI_01_WREADY(m_axi_hbm_wready[1 +: 1]), + .AXI_01_BID(m_axi_hbm_bid[1*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_01_BRESP(m_axi_hbm_bresp[1*2 +: 2]), + .AXI_01_BVALID(m_axi_hbm_bvalid[1 +: 1]), + .AXI_01_BREADY(m_axi_hbm_bready[1 +: 1]), + + .AXI_02_ACLK(hbm_clk[2 +: 1]), + .AXI_02_ARESET_N(!hbm_rst[2 +: 1]), + + .AXI_02_ARADDR(m_axi_hbm_araddr[2*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_02_ARBURST(m_axi_hbm_arburst[2*2 +: 2]), + .AXI_02_ARID(m_axi_hbm_arid[2*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_02_ARLEN(m_axi_hbm_arlen[2*8 +: 8]), + .AXI_02_ARSIZE(m_axi_hbm_arsize[2*3 +: 3]), + .AXI_02_ARVALID(m_axi_hbm_arvalid[2 +: 1]), + .AXI_02_ARREADY(m_axi_hbm_arready[2 +: 1]), + .AXI_02_RDATA_PARITY(), + .AXI_02_RDATA(m_axi_hbm_rdata[2*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_02_RID(m_axi_hbm_rid[2 +: 1]), + .AXI_02_RLAST(m_axi_hbm_rlast[2 +: 1]), + .AXI_02_RRESP(m_axi_hbm_rresp[2*2 +: 2]), + .AXI_02_RVALID(m_axi_hbm_rvalid[2 +: 1]), + .AXI_02_RREADY(m_axi_hbm_rready[2 +: 1]), + .AXI_02_AWADDR(m_axi_hbm_awaddr[2*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_02_AWBURST(m_axi_hbm_awburst[2*2 +: 2]), + .AXI_02_AWID(m_axi_hbm_awid[2*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_02_AWLEN(m_axi_hbm_awlen[2*8 +: 8]), + .AXI_02_AWSIZE(m_axi_hbm_awsize[2*3 +: 3]), + .AXI_02_AWVALID(m_axi_hbm_awvalid[2 +: 1]), + .AXI_02_AWREADY(m_axi_hbm_awready[2 +: 1]), + .AXI_02_WDATA(m_axi_hbm_wdata[2*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_02_WLAST(m_axi_hbm_wlast[2 +: 1]), + .AXI_02_WSTRB(m_axi_hbm_wstrb[2*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_02_WDATA_PARITY(32'd0), + .AXI_02_WVALID(m_axi_hbm_wvalid[2 +: 1]), + .AXI_02_WREADY(m_axi_hbm_wready[2 +: 1]), + .AXI_02_BID(m_axi_hbm_bid[2*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_02_BRESP(m_axi_hbm_bresp[2*2 +: 2]), + .AXI_02_BVALID(m_axi_hbm_bvalid[2 +: 1]), + .AXI_02_BREADY(m_axi_hbm_bready[2 +: 1]), + + .AXI_03_ACLK(hbm_clk[3 +: 1]), + .AXI_03_ARESET_N(!hbm_rst[3 +: 1]), + + .AXI_03_ARADDR(m_axi_hbm_araddr[3*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_03_ARBURST(m_axi_hbm_arburst[3*2 +: 2]), + .AXI_03_ARID(m_axi_hbm_arid[3*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_03_ARLEN(m_axi_hbm_arlen[3*8 +: 8]), + .AXI_03_ARSIZE(m_axi_hbm_arsize[3*3 +: 3]), + .AXI_03_ARVALID(m_axi_hbm_arvalid[3 +: 1]), + .AXI_03_ARREADY(m_axi_hbm_arready[3 +: 1]), + .AXI_03_RDATA_PARITY(), + .AXI_03_RDATA(m_axi_hbm_rdata[3*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_03_RID(m_axi_hbm_rid[3 +: 1]), + .AXI_03_RLAST(m_axi_hbm_rlast[3 +: 1]), + .AXI_03_RRESP(m_axi_hbm_rresp[3*2 +: 2]), + .AXI_03_RVALID(m_axi_hbm_rvalid[3 +: 1]), + .AXI_03_RREADY(m_axi_hbm_rready[3 +: 1]), + .AXI_03_AWADDR(m_axi_hbm_awaddr[3*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_03_AWBURST(m_axi_hbm_awburst[3*2 +: 2]), + .AXI_03_AWID(m_axi_hbm_awid[3*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_03_AWLEN(m_axi_hbm_awlen[3*8 +: 8]), + .AXI_03_AWSIZE(m_axi_hbm_awsize[3*3 +: 3]), + .AXI_03_AWVALID(m_axi_hbm_awvalid[3 +: 1]), + .AXI_03_AWREADY(m_axi_hbm_awready[3 +: 1]), + .AXI_03_WDATA(m_axi_hbm_wdata[3*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_03_WLAST(m_axi_hbm_wlast[3 +: 1]), + .AXI_03_WSTRB(m_axi_hbm_wstrb[3*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_03_WDATA_PARITY(32'd0), + .AXI_03_WVALID(m_axi_hbm_wvalid[3 +: 1]), + .AXI_03_WREADY(m_axi_hbm_wready[3 +: 1]), + .AXI_03_BID(m_axi_hbm_bid[3*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_03_BRESP(m_axi_hbm_bresp[3*2 +: 2]), + .AXI_03_BVALID(m_axi_hbm_bvalid[3 +: 1]), + .AXI_03_BREADY(m_axi_hbm_bready[3 +: 1]), + + .AXI_04_ACLK(hbm_clk[4 +: 1]), + .AXI_04_ARESET_N(!hbm_rst[4 +: 1]), + + .AXI_04_ARADDR(m_axi_hbm_araddr[4*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_04_ARBURST(m_axi_hbm_arburst[4*2 +: 2]), + .AXI_04_ARID(m_axi_hbm_arid[4*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_04_ARLEN(m_axi_hbm_arlen[4*8 +: 8]), + .AXI_04_ARSIZE(m_axi_hbm_arsize[4*3 +: 3]), + .AXI_04_ARVALID(m_axi_hbm_arvalid[4 +: 1]), + .AXI_04_ARREADY(m_axi_hbm_arready[4 +: 1]), + .AXI_04_RDATA_PARITY(), + .AXI_04_RDATA(m_axi_hbm_rdata[4*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_04_RID(m_axi_hbm_rid[4 +: 1]), + .AXI_04_RLAST(m_axi_hbm_rlast[4 +: 1]), + .AXI_04_RRESP(m_axi_hbm_rresp[4*2 +: 2]), + .AXI_04_RVALID(m_axi_hbm_rvalid[4 +: 1]), + .AXI_04_RREADY(m_axi_hbm_rready[4 +: 1]), + .AXI_04_AWADDR(m_axi_hbm_awaddr[4*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_04_AWBURST(m_axi_hbm_awburst[4*2 +: 2]), + .AXI_04_AWID(m_axi_hbm_awid[4*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_04_AWLEN(m_axi_hbm_awlen[4*8 +: 8]), + .AXI_04_AWSIZE(m_axi_hbm_awsize[4*3 +: 3]), + .AXI_04_AWVALID(m_axi_hbm_awvalid[4 +: 1]), + .AXI_04_AWREADY(m_axi_hbm_awready[4 +: 1]), + .AXI_04_WDATA(m_axi_hbm_wdata[4*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_04_WLAST(m_axi_hbm_wlast[4 +: 1]), + .AXI_04_WSTRB(m_axi_hbm_wstrb[4*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_04_WDATA_PARITY(32'd0), + .AXI_04_WVALID(m_axi_hbm_wvalid[4 +: 1]), + .AXI_04_WREADY(m_axi_hbm_wready[4 +: 1]), + .AXI_04_BID(m_axi_hbm_bid[4*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_04_BRESP(m_axi_hbm_bresp[4*2 +: 2]), + .AXI_04_BVALID(m_axi_hbm_bvalid[4 +: 1]), + .AXI_04_BREADY(m_axi_hbm_bready[4 +: 1]), + + .AXI_05_ACLK(hbm_clk[5 +: 1]), + .AXI_05_ARESET_N(!hbm_rst[5 +: 1]), + + .AXI_05_ARADDR(m_axi_hbm_araddr[5*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_05_ARBURST(m_axi_hbm_arburst[5*2 +: 2]), + .AXI_05_ARID(m_axi_hbm_arid[5*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_05_ARLEN(m_axi_hbm_arlen[5*8 +: 8]), + .AXI_05_ARSIZE(m_axi_hbm_arsize[5*3 +: 3]), + .AXI_05_ARVALID(m_axi_hbm_arvalid[5 +: 1]), + .AXI_05_ARREADY(m_axi_hbm_arready[5 +: 1]), + .AXI_05_RDATA_PARITY(), + .AXI_05_RDATA(m_axi_hbm_rdata[5*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_05_RID(m_axi_hbm_rid[5 +: 1]), + .AXI_05_RLAST(m_axi_hbm_rlast[5 +: 1]), + .AXI_05_RRESP(m_axi_hbm_rresp[5*2 +: 2]), + .AXI_05_RVALID(m_axi_hbm_rvalid[5 +: 1]), + .AXI_05_RREADY(m_axi_hbm_rready[5 +: 1]), + .AXI_05_AWADDR(m_axi_hbm_awaddr[5*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_05_AWBURST(m_axi_hbm_awburst[5*2 +: 2]), + .AXI_05_AWID(m_axi_hbm_awid[5*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_05_AWLEN(m_axi_hbm_awlen[5*8 +: 8]), + .AXI_05_AWSIZE(m_axi_hbm_awsize[5*3 +: 3]), + .AXI_05_AWVALID(m_axi_hbm_awvalid[5 +: 1]), + .AXI_05_AWREADY(m_axi_hbm_awready[5 +: 1]), + .AXI_05_WDATA(m_axi_hbm_wdata[5*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_05_WLAST(m_axi_hbm_wlast[5 +: 1]), + .AXI_05_WSTRB(m_axi_hbm_wstrb[5*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_05_WDATA_PARITY(32'd0), + .AXI_05_WVALID(m_axi_hbm_wvalid[5 +: 1]), + .AXI_05_WREADY(m_axi_hbm_wready[5 +: 1]), + .AXI_05_BID(m_axi_hbm_bid[5*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_05_BRESP(m_axi_hbm_bresp[5*2 +: 2]), + .AXI_05_BVALID(m_axi_hbm_bvalid[5 +: 1]), + .AXI_05_BREADY(m_axi_hbm_bready[5 +: 1]), + + .AXI_06_ACLK(hbm_clk[6 +: 1]), + .AXI_06_ARESET_N(!hbm_rst[6 +: 1]), + + .AXI_06_ARADDR(m_axi_hbm_araddr[6*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_06_ARBURST(m_axi_hbm_arburst[6*2 +: 2]), + .AXI_06_ARID(m_axi_hbm_arid[6*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_06_ARLEN(m_axi_hbm_arlen[6*8 +: 8]), + .AXI_06_ARSIZE(m_axi_hbm_arsize[6*3 +: 3]), + .AXI_06_ARVALID(m_axi_hbm_arvalid[6 +: 1]), + .AXI_06_ARREADY(m_axi_hbm_arready[6 +: 1]), + .AXI_06_RDATA_PARITY(), + .AXI_06_RDATA(m_axi_hbm_rdata[6*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_06_RID(m_axi_hbm_rid[6 +: 1]), + .AXI_06_RLAST(m_axi_hbm_rlast[6 +: 1]), + .AXI_06_RRESP(m_axi_hbm_rresp[6*2 +: 2]), + .AXI_06_RVALID(m_axi_hbm_rvalid[6 +: 1]), + .AXI_06_RREADY(m_axi_hbm_rready[6 +: 1]), + .AXI_06_AWADDR(m_axi_hbm_awaddr[6*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_06_AWBURST(m_axi_hbm_awburst[6*2 +: 2]), + .AXI_06_AWID(m_axi_hbm_awid[6*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_06_AWLEN(m_axi_hbm_awlen[6*8 +: 8]), + .AXI_06_AWSIZE(m_axi_hbm_awsize[6*3 +: 3]), + .AXI_06_AWVALID(m_axi_hbm_awvalid[6 +: 1]), + .AXI_06_AWREADY(m_axi_hbm_awready[6 +: 1]), + .AXI_06_WDATA(m_axi_hbm_wdata[6*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_06_WLAST(m_axi_hbm_wlast[6 +: 1]), + .AXI_06_WSTRB(m_axi_hbm_wstrb[6*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_06_WDATA_PARITY(32'd0), + .AXI_06_WVALID(m_axi_hbm_wvalid[6 +: 1]), + .AXI_06_WREADY(m_axi_hbm_wready[6 +: 1]), + .AXI_06_BID(m_axi_hbm_bid[6*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_06_BRESP(m_axi_hbm_bresp[6*2 +: 2]), + .AXI_06_BVALID(m_axi_hbm_bvalid[6 +: 1]), + .AXI_06_BREADY(m_axi_hbm_bready[6 +: 1]), + + .AXI_07_ACLK(hbm_clk[7 +: 1]), + .AXI_07_ARESET_N(!hbm_rst[7 +: 1]), + + .AXI_07_ARADDR(m_axi_hbm_araddr[7*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_07_ARBURST(m_axi_hbm_arburst[7*2 +: 2]), + .AXI_07_ARID(m_axi_hbm_arid[7*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_07_ARLEN(m_axi_hbm_arlen[7*8 +: 8]), + .AXI_07_ARSIZE(m_axi_hbm_arsize[7*3 +: 3]), + .AXI_07_ARVALID(m_axi_hbm_arvalid[7 +: 1]), + .AXI_07_ARREADY(m_axi_hbm_arready[7 +: 1]), + .AXI_07_RDATA_PARITY(), + .AXI_07_RDATA(m_axi_hbm_rdata[7*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_07_RID(m_axi_hbm_rid[7 +: 1]), + .AXI_07_RLAST(m_axi_hbm_rlast[7 +: 1]), + .AXI_07_RRESP(m_axi_hbm_rresp[7*2 +: 2]), + .AXI_07_RVALID(m_axi_hbm_rvalid[7 +: 1]), + .AXI_07_RREADY(m_axi_hbm_rready[7 +: 1]), + .AXI_07_AWADDR(m_axi_hbm_awaddr[7*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_07_AWBURST(m_axi_hbm_awburst[7*2 +: 2]), + .AXI_07_AWID(m_axi_hbm_awid[7*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_07_AWLEN(m_axi_hbm_awlen[7*8 +: 8]), + .AXI_07_AWSIZE(m_axi_hbm_awsize[7*3 +: 3]), + .AXI_07_AWVALID(m_axi_hbm_awvalid[7 +: 1]), + .AXI_07_AWREADY(m_axi_hbm_awready[7 +: 1]), + .AXI_07_WDATA(m_axi_hbm_wdata[7*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_07_WLAST(m_axi_hbm_wlast[7 +: 1]), + .AXI_07_WSTRB(m_axi_hbm_wstrb[7*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_07_WDATA_PARITY(32'd0), + .AXI_07_WVALID(m_axi_hbm_wvalid[7 +: 1]), + .AXI_07_WREADY(m_axi_hbm_wready[7 +: 1]), + .AXI_07_BID(m_axi_hbm_bid[7*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_07_BRESP(m_axi_hbm_bresp[7*2 +: 2]), + .AXI_07_BVALID(m_axi_hbm_bvalid[7 +: 1]), + .AXI_07_BREADY(m_axi_hbm_bready[7 +: 1]), + + .AXI_08_ACLK(hbm_clk[8 +: 1]), + .AXI_08_ARESET_N(!hbm_rst[8 +: 1]), + + .AXI_08_ARADDR(m_axi_hbm_araddr[8*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_08_ARBURST(m_axi_hbm_arburst[8*2 +: 2]), + .AXI_08_ARID(m_axi_hbm_arid[8*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_08_ARLEN(m_axi_hbm_arlen[8*8 +: 8]), + .AXI_08_ARSIZE(m_axi_hbm_arsize[8*3 +: 3]), + .AXI_08_ARVALID(m_axi_hbm_arvalid[8 +: 1]), + .AXI_08_ARREADY(m_axi_hbm_arready[8 +: 1]), + .AXI_08_RDATA_PARITY(), + .AXI_08_RDATA(m_axi_hbm_rdata[8*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_08_RID(m_axi_hbm_rid[8 +: 1]), + .AXI_08_RLAST(m_axi_hbm_rlast[8 +: 1]), + .AXI_08_RRESP(m_axi_hbm_rresp[8*2 +: 2]), + .AXI_08_RVALID(m_axi_hbm_rvalid[8 +: 1]), + .AXI_08_RREADY(m_axi_hbm_rready[8 +: 1]), + .AXI_08_AWADDR(m_axi_hbm_awaddr[8*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_08_AWBURST(m_axi_hbm_awburst[8*2 +: 2]), + .AXI_08_AWID(m_axi_hbm_awid[8*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_08_AWLEN(m_axi_hbm_awlen[8*8 +: 8]), + .AXI_08_AWSIZE(m_axi_hbm_awsize[8*3 +: 3]), + .AXI_08_AWVALID(m_axi_hbm_awvalid[8 +: 1]), + .AXI_08_AWREADY(m_axi_hbm_awready[8 +: 1]), + .AXI_08_WDATA(m_axi_hbm_wdata[8*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_08_WLAST(m_axi_hbm_wlast[8 +: 1]), + .AXI_08_WSTRB(m_axi_hbm_wstrb[8*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_08_WDATA_PARITY(32'd0), + .AXI_08_WVALID(m_axi_hbm_wvalid[8 +: 1]), + .AXI_08_WREADY(m_axi_hbm_wready[8 +: 1]), + .AXI_08_BID(m_axi_hbm_bid[8*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_08_BRESP(m_axi_hbm_bresp[8*2 +: 2]), + .AXI_08_BVALID(m_axi_hbm_bvalid[8 +: 1]), + .AXI_08_BREADY(m_axi_hbm_bready[8 +: 1]), + + .AXI_09_ACLK(hbm_clk[9 +: 1]), + .AXI_09_ARESET_N(!hbm_rst[9 +: 1]), + + .AXI_09_ARADDR(m_axi_hbm_araddr[9*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_09_ARBURST(m_axi_hbm_arburst[9*2 +: 2]), + .AXI_09_ARID(m_axi_hbm_arid[9*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_09_ARLEN(m_axi_hbm_arlen[9*8 +: 8]), + .AXI_09_ARSIZE(m_axi_hbm_arsize[9*3 +: 3]), + .AXI_09_ARVALID(m_axi_hbm_arvalid[9 +: 1]), + .AXI_09_ARREADY(m_axi_hbm_arready[9 +: 1]), + .AXI_09_RDATA_PARITY(), + .AXI_09_RDATA(m_axi_hbm_rdata[9*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_09_RID(m_axi_hbm_rid[9 +: 1]), + .AXI_09_RLAST(m_axi_hbm_rlast[9 +: 1]), + .AXI_09_RRESP(m_axi_hbm_rresp[9*2 +: 2]), + .AXI_09_RVALID(m_axi_hbm_rvalid[9 +: 1]), + .AXI_09_RREADY(m_axi_hbm_rready[9 +: 1]), + .AXI_09_AWADDR(m_axi_hbm_awaddr[9*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_09_AWBURST(m_axi_hbm_awburst[9*2 +: 2]), + .AXI_09_AWID(m_axi_hbm_awid[9*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_09_AWLEN(m_axi_hbm_awlen[9*8 +: 8]), + .AXI_09_AWSIZE(m_axi_hbm_awsize[9*3 +: 3]), + .AXI_09_AWVALID(m_axi_hbm_awvalid[9 +: 1]), + .AXI_09_AWREADY(m_axi_hbm_awready[9 +: 1]), + .AXI_09_WDATA(m_axi_hbm_wdata[9*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_09_WLAST(m_axi_hbm_wlast[9 +: 1]), + .AXI_09_WSTRB(m_axi_hbm_wstrb[9*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_09_WDATA_PARITY(32'd0), + .AXI_09_WVALID(m_axi_hbm_wvalid[9 +: 1]), + .AXI_09_WREADY(m_axi_hbm_wready[9 +: 1]), + .AXI_09_BID(m_axi_hbm_bid[9*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_09_BRESP(m_axi_hbm_bresp[9*2 +: 2]), + .AXI_09_BVALID(m_axi_hbm_bvalid[9 +: 1]), + .AXI_09_BREADY(m_axi_hbm_bready[9 +: 1]), + + .AXI_10_ACLK(hbm_clk[10 +: 1]), + .AXI_10_ARESET_N(!hbm_rst[10 +: 1]), + + .AXI_10_ARADDR(m_axi_hbm_araddr[10*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_10_ARBURST(m_axi_hbm_arburst[10*2 +: 2]), + .AXI_10_ARID(m_axi_hbm_arid[10*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_10_ARLEN(m_axi_hbm_arlen[10*8 +: 8]), + .AXI_10_ARSIZE(m_axi_hbm_arsize[10*3 +: 3]), + .AXI_10_ARVALID(m_axi_hbm_arvalid[10 +: 1]), + .AXI_10_ARREADY(m_axi_hbm_arready[10 +: 1]), + .AXI_10_RDATA_PARITY(), + .AXI_10_RDATA(m_axi_hbm_rdata[10*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_10_RID(m_axi_hbm_rid[10 +: 1]), + .AXI_10_RLAST(m_axi_hbm_rlast[10 +: 1]), + .AXI_10_RRESP(m_axi_hbm_rresp[10*2 +: 2]), + .AXI_10_RVALID(m_axi_hbm_rvalid[10 +: 1]), + .AXI_10_RREADY(m_axi_hbm_rready[10 +: 1]), + .AXI_10_AWADDR(m_axi_hbm_awaddr[10*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_10_AWBURST(m_axi_hbm_awburst[10*2 +: 2]), + .AXI_10_AWID(m_axi_hbm_awid[10*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_10_AWLEN(m_axi_hbm_awlen[10*8 +: 8]), + .AXI_10_AWSIZE(m_axi_hbm_awsize[10*3 +: 3]), + .AXI_10_AWVALID(m_axi_hbm_awvalid[10 +: 1]), + .AXI_10_AWREADY(m_axi_hbm_awready[10 +: 1]), + .AXI_10_WDATA(m_axi_hbm_wdata[10*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_10_WLAST(m_axi_hbm_wlast[10 +: 1]), + .AXI_10_WSTRB(m_axi_hbm_wstrb[10*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_10_WDATA_PARITY(32'd0), + .AXI_10_WVALID(m_axi_hbm_wvalid[10 +: 1]), + .AXI_10_WREADY(m_axi_hbm_wready[10 +: 1]), + .AXI_10_BID(m_axi_hbm_bid[10*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_10_BRESP(m_axi_hbm_bresp[10*2 +: 2]), + .AXI_10_BVALID(m_axi_hbm_bvalid[10 +: 1]), + .AXI_10_BREADY(m_axi_hbm_bready[10 +: 1]), + + .AXI_11_ACLK(hbm_clk[11 +: 1]), + .AXI_11_ARESET_N(!hbm_rst[11 +: 1]), + + .AXI_11_ARADDR(m_axi_hbm_araddr[11*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_11_ARBURST(m_axi_hbm_arburst[11*2 +: 2]), + .AXI_11_ARID(m_axi_hbm_arid[11*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_11_ARLEN(m_axi_hbm_arlen[11*8 +: 8]), + .AXI_11_ARSIZE(m_axi_hbm_arsize[11*3 +: 3]), + .AXI_11_ARVALID(m_axi_hbm_arvalid[11 +: 1]), + .AXI_11_ARREADY(m_axi_hbm_arready[11 +: 1]), + .AXI_11_RDATA_PARITY(), + .AXI_11_RDATA(m_axi_hbm_rdata[11*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_11_RID(m_axi_hbm_rid[11 +: 1]), + .AXI_11_RLAST(m_axi_hbm_rlast[11 +: 1]), + .AXI_11_RRESP(m_axi_hbm_rresp[11*2 +: 2]), + .AXI_11_RVALID(m_axi_hbm_rvalid[11 +: 1]), + .AXI_11_RREADY(m_axi_hbm_rready[11 +: 1]), + .AXI_11_AWADDR(m_axi_hbm_awaddr[11*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_11_AWBURST(m_axi_hbm_awburst[11*2 +: 2]), + .AXI_11_AWID(m_axi_hbm_awid[11*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_11_AWLEN(m_axi_hbm_awlen[11*8 +: 8]), + .AXI_11_AWSIZE(m_axi_hbm_awsize[11*3 +: 3]), + .AXI_11_AWVALID(m_axi_hbm_awvalid[11 +: 1]), + .AXI_11_AWREADY(m_axi_hbm_awready[11 +: 1]), + .AXI_11_WDATA(m_axi_hbm_wdata[11*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_11_WLAST(m_axi_hbm_wlast[11 +: 1]), + .AXI_11_WSTRB(m_axi_hbm_wstrb[11*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_11_WDATA_PARITY(32'd0), + .AXI_11_WVALID(m_axi_hbm_wvalid[11 +: 1]), + .AXI_11_WREADY(m_axi_hbm_wready[11 +: 1]), + .AXI_11_BID(m_axi_hbm_bid[11*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_11_BRESP(m_axi_hbm_bresp[11*2 +: 2]), + .AXI_11_BVALID(m_axi_hbm_bvalid[11 +: 1]), + .AXI_11_BREADY(m_axi_hbm_bready[11 +: 1]), + + .AXI_12_ACLK(hbm_clk[12 +: 1]), + .AXI_12_ARESET_N(!hbm_rst[12 +: 1]), + + .AXI_12_ARADDR(m_axi_hbm_araddr[12*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_12_ARBURST(m_axi_hbm_arburst[12*2 +: 2]), + .AXI_12_ARID(m_axi_hbm_arid[12*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_12_ARLEN(m_axi_hbm_arlen[12*8 +: 8]), + .AXI_12_ARSIZE(m_axi_hbm_arsize[12*3 +: 3]), + .AXI_12_ARVALID(m_axi_hbm_arvalid[12 +: 1]), + .AXI_12_ARREADY(m_axi_hbm_arready[12 +: 1]), + .AXI_12_RDATA_PARITY(), + .AXI_12_RDATA(m_axi_hbm_rdata[12*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_12_RID(m_axi_hbm_rid[12 +: 1]), + .AXI_12_RLAST(m_axi_hbm_rlast[12 +: 1]), + .AXI_12_RRESP(m_axi_hbm_rresp[12*2 +: 2]), + .AXI_12_RVALID(m_axi_hbm_rvalid[12 +: 1]), + .AXI_12_RREADY(m_axi_hbm_rready[12 +: 1]), + .AXI_12_AWADDR(m_axi_hbm_awaddr[12*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_12_AWBURST(m_axi_hbm_awburst[12*2 +: 2]), + .AXI_12_AWID(m_axi_hbm_awid[12*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_12_AWLEN(m_axi_hbm_awlen[12*8 +: 8]), + .AXI_12_AWSIZE(m_axi_hbm_awsize[12*3 +: 3]), + .AXI_12_AWVALID(m_axi_hbm_awvalid[12 +: 1]), + .AXI_12_AWREADY(m_axi_hbm_awready[12 +: 1]), + .AXI_12_WDATA(m_axi_hbm_wdata[12*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_12_WLAST(m_axi_hbm_wlast[12 +: 1]), + .AXI_12_WSTRB(m_axi_hbm_wstrb[12*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_12_WDATA_PARITY(32'd0), + .AXI_12_WVALID(m_axi_hbm_wvalid[12 +: 1]), + .AXI_12_WREADY(m_axi_hbm_wready[12 +: 1]), + .AXI_12_BID(m_axi_hbm_bid[12*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_12_BRESP(m_axi_hbm_bresp[12*2 +: 2]), + .AXI_12_BVALID(m_axi_hbm_bvalid[12 +: 1]), + .AXI_12_BREADY(m_axi_hbm_bready[12 +: 1]), + + .AXI_13_ACLK(hbm_clk[13 +: 1]), + .AXI_13_ARESET_N(!hbm_rst[13 +: 1]), + + .AXI_13_ARADDR(m_axi_hbm_araddr[13*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_13_ARBURST(m_axi_hbm_arburst[13*2 +: 2]), + .AXI_13_ARID(m_axi_hbm_arid[13*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_13_ARLEN(m_axi_hbm_arlen[13*8 +: 8]), + .AXI_13_ARSIZE(m_axi_hbm_arsize[13*3 +: 3]), + .AXI_13_ARVALID(m_axi_hbm_arvalid[13 +: 1]), + .AXI_13_ARREADY(m_axi_hbm_arready[13 +: 1]), + .AXI_13_RDATA_PARITY(), + .AXI_13_RDATA(m_axi_hbm_rdata[13*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_13_RID(m_axi_hbm_rid[13 +: 1]), + .AXI_13_RLAST(m_axi_hbm_rlast[13 +: 1]), + .AXI_13_RRESP(m_axi_hbm_rresp[13*2 +: 2]), + .AXI_13_RVALID(m_axi_hbm_rvalid[13 +: 1]), + .AXI_13_RREADY(m_axi_hbm_rready[13 +: 1]), + .AXI_13_AWADDR(m_axi_hbm_awaddr[13*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_13_AWBURST(m_axi_hbm_awburst[13*2 +: 2]), + .AXI_13_AWID(m_axi_hbm_awid[13*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_13_AWLEN(m_axi_hbm_awlen[13*8 +: 8]), + .AXI_13_AWSIZE(m_axi_hbm_awsize[13*3 +: 3]), + .AXI_13_AWVALID(m_axi_hbm_awvalid[13 +: 1]), + .AXI_13_AWREADY(m_axi_hbm_awready[13 +: 1]), + .AXI_13_WDATA(m_axi_hbm_wdata[13*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_13_WLAST(m_axi_hbm_wlast[13 +: 1]), + .AXI_13_WSTRB(m_axi_hbm_wstrb[13*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_13_WDATA_PARITY(32'd0), + .AXI_13_WVALID(m_axi_hbm_wvalid[13 +: 1]), + .AXI_13_WREADY(m_axi_hbm_wready[13 +: 1]), + .AXI_13_BID(m_axi_hbm_bid[13*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_13_BRESP(m_axi_hbm_bresp[13*2 +: 2]), + .AXI_13_BVALID(m_axi_hbm_bvalid[13 +: 1]), + .AXI_13_BREADY(m_axi_hbm_bready[13 +: 1]), + + .AXI_14_ACLK(hbm_clk[14 +: 1]), + .AXI_14_ARESET_N(!hbm_rst[14 +: 1]), + + .AXI_14_ARADDR(m_axi_hbm_araddr[14*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_14_ARBURST(m_axi_hbm_arburst[14*2 +: 2]), + .AXI_14_ARID(m_axi_hbm_arid[14*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_14_ARLEN(m_axi_hbm_arlen[14*8 +: 8]), + .AXI_14_ARSIZE(m_axi_hbm_arsize[14*3 +: 3]), + .AXI_14_ARVALID(m_axi_hbm_arvalid[14 +: 1]), + .AXI_14_ARREADY(m_axi_hbm_arready[14 +: 1]), + .AXI_14_RDATA_PARITY(), + .AXI_14_RDATA(m_axi_hbm_rdata[14*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_14_RID(m_axi_hbm_rid[14 +: 1]), + .AXI_14_RLAST(m_axi_hbm_rlast[14 +: 1]), + .AXI_14_RRESP(m_axi_hbm_rresp[14*2 +: 2]), + .AXI_14_RVALID(m_axi_hbm_rvalid[14 +: 1]), + .AXI_14_RREADY(m_axi_hbm_rready[14 +: 1]), + .AXI_14_AWADDR(m_axi_hbm_awaddr[14*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_14_AWBURST(m_axi_hbm_awburst[14*2 +: 2]), + .AXI_14_AWID(m_axi_hbm_awid[14*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_14_AWLEN(m_axi_hbm_awlen[14*8 +: 8]), + .AXI_14_AWSIZE(m_axi_hbm_awsize[14*3 +: 3]), + .AXI_14_AWVALID(m_axi_hbm_awvalid[14 +: 1]), + .AXI_14_AWREADY(m_axi_hbm_awready[14 +: 1]), + .AXI_14_WDATA(m_axi_hbm_wdata[14*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_14_WLAST(m_axi_hbm_wlast[14 +: 1]), + .AXI_14_WSTRB(m_axi_hbm_wstrb[14*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_14_WDATA_PARITY(32'd0), + .AXI_14_WVALID(m_axi_hbm_wvalid[14 +: 1]), + .AXI_14_WREADY(m_axi_hbm_wready[14 +: 1]), + .AXI_14_BID(m_axi_hbm_bid[14*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_14_BRESP(m_axi_hbm_bresp[14*2 +: 2]), + .AXI_14_BVALID(m_axi_hbm_bvalid[14 +: 1]), + .AXI_14_BREADY(m_axi_hbm_bready[14 +: 1]), + + .AXI_15_ACLK(hbm_clk[15 +: 1]), + .AXI_15_ARESET_N(!hbm_rst[15 +: 1]), + + .AXI_15_ARADDR(m_axi_hbm_araddr[15*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_15_ARBURST(m_axi_hbm_arburst[15*2 +: 2]), + .AXI_15_ARID(m_axi_hbm_arid[15*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_15_ARLEN(m_axi_hbm_arlen[15*8 +: 8]), + .AXI_15_ARSIZE(m_axi_hbm_arsize[15*3 +: 3]), + .AXI_15_ARVALID(m_axi_hbm_arvalid[15 +: 1]), + .AXI_15_ARREADY(m_axi_hbm_arready[15 +: 1]), + .AXI_15_RDATA_PARITY(), + .AXI_15_RDATA(m_axi_hbm_rdata[15*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_15_RID(m_axi_hbm_rid[15 +: 1]), + .AXI_15_RLAST(m_axi_hbm_rlast[15 +: 1]), + .AXI_15_RRESP(m_axi_hbm_rresp[15*2 +: 2]), + .AXI_15_RVALID(m_axi_hbm_rvalid[15 +: 1]), + .AXI_15_RREADY(m_axi_hbm_rready[15 +: 1]), + .AXI_15_AWADDR(m_axi_hbm_awaddr[15*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_15_AWBURST(m_axi_hbm_awburst[15*2 +: 2]), + .AXI_15_AWID(m_axi_hbm_awid[15*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_15_AWLEN(m_axi_hbm_awlen[15*8 +: 8]), + .AXI_15_AWSIZE(m_axi_hbm_awsize[15*3 +: 3]), + .AXI_15_AWVALID(m_axi_hbm_awvalid[15 +: 1]), + .AXI_15_AWREADY(m_axi_hbm_awready[15 +: 1]), + .AXI_15_WDATA(m_axi_hbm_wdata[15*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_15_WLAST(m_axi_hbm_wlast[15 +: 1]), + .AXI_15_WSTRB(m_axi_hbm_wstrb[15*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_15_WDATA_PARITY(32'd0), + .AXI_15_WVALID(m_axi_hbm_wvalid[15 +: 1]), + .AXI_15_WREADY(m_axi_hbm_wready[15 +: 1]), + .AXI_15_BID(m_axi_hbm_bid[15*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_15_BRESP(m_axi_hbm_bresp[15*2 +: 2]), + .AXI_15_BVALID(m_axi_hbm_bvalid[15 +: 1]), + .AXI_15_BREADY(m_axi_hbm_bready[15 +: 1]), + + .AXI_16_ACLK(hbm_clk[16 +: 1]), + .AXI_16_ARESET_N(!hbm_rst[16 +: 1]), + + .AXI_16_ARADDR(m_axi_hbm_araddr[16*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_16_ARBURST(m_axi_hbm_arburst[16*2 +: 2]), + .AXI_16_ARID(m_axi_hbm_arid[16*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_16_ARLEN(m_axi_hbm_arlen[16*8 +: 8]), + .AXI_16_ARSIZE(m_axi_hbm_arsize[16*3 +: 3]), + .AXI_16_ARVALID(m_axi_hbm_arvalid[16 +: 1]), + .AXI_16_ARREADY(m_axi_hbm_arready[16 +: 1]), + .AXI_16_RDATA_PARITY(), + .AXI_16_RDATA(m_axi_hbm_rdata[16*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_16_RID(m_axi_hbm_rid[16 +: 1]), + .AXI_16_RLAST(m_axi_hbm_rlast[16 +: 1]), + .AXI_16_RRESP(m_axi_hbm_rresp[16*2 +: 2]), + .AXI_16_RVALID(m_axi_hbm_rvalid[16 +: 1]), + .AXI_16_RREADY(m_axi_hbm_rready[16 +: 1]), + .AXI_16_AWADDR(m_axi_hbm_awaddr[16*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_16_AWBURST(m_axi_hbm_awburst[16*2 +: 2]), + .AXI_16_AWID(m_axi_hbm_awid[16*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_16_AWLEN(m_axi_hbm_awlen[16*8 +: 8]), + .AXI_16_AWSIZE(m_axi_hbm_awsize[16*3 +: 3]), + .AXI_16_AWVALID(m_axi_hbm_awvalid[16 +: 1]), + .AXI_16_AWREADY(m_axi_hbm_awready[16 +: 1]), + .AXI_16_WDATA(m_axi_hbm_wdata[16*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_16_WLAST(m_axi_hbm_wlast[16 +: 1]), + .AXI_16_WSTRB(m_axi_hbm_wstrb[16*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_16_WDATA_PARITY(32'd0), + .AXI_16_WVALID(m_axi_hbm_wvalid[16 +: 1]), + .AXI_16_WREADY(m_axi_hbm_wready[16 +: 1]), + .AXI_16_BID(m_axi_hbm_bid[16*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_16_BRESP(m_axi_hbm_bresp[16*2 +: 2]), + .AXI_16_BVALID(m_axi_hbm_bvalid[16 +: 1]), + .AXI_16_BREADY(m_axi_hbm_bready[16 +: 1]), + + .AXI_17_ACLK(hbm_clk[17 +: 1]), + .AXI_17_ARESET_N(!hbm_rst[17 +: 1]), + + .AXI_17_ARADDR(m_axi_hbm_araddr[17*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_17_ARBURST(m_axi_hbm_arburst[17*2 +: 2]), + .AXI_17_ARID(m_axi_hbm_arid[17*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_17_ARLEN(m_axi_hbm_arlen[17*8 +: 8]), + .AXI_17_ARSIZE(m_axi_hbm_arsize[17*3 +: 3]), + .AXI_17_ARVALID(m_axi_hbm_arvalid[17 +: 1]), + .AXI_17_ARREADY(m_axi_hbm_arready[17 +: 1]), + .AXI_17_RDATA_PARITY(), + .AXI_17_RDATA(m_axi_hbm_rdata[17*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_17_RID(m_axi_hbm_rid[17 +: 1]), + .AXI_17_RLAST(m_axi_hbm_rlast[17 +: 1]), + .AXI_17_RRESP(m_axi_hbm_rresp[17*2 +: 2]), + .AXI_17_RVALID(m_axi_hbm_rvalid[17 +: 1]), + .AXI_17_RREADY(m_axi_hbm_rready[17 +: 1]), + .AXI_17_AWADDR(m_axi_hbm_awaddr[17*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_17_AWBURST(m_axi_hbm_awburst[17*2 +: 2]), + .AXI_17_AWID(m_axi_hbm_awid[17*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_17_AWLEN(m_axi_hbm_awlen[17*8 +: 8]), + .AXI_17_AWSIZE(m_axi_hbm_awsize[17*3 +: 3]), + .AXI_17_AWVALID(m_axi_hbm_awvalid[17 +: 1]), + .AXI_17_AWREADY(m_axi_hbm_awready[17 +: 1]), + .AXI_17_WDATA(m_axi_hbm_wdata[17*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_17_WLAST(m_axi_hbm_wlast[17 +: 1]), + .AXI_17_WSTRB(m_axi_hbm_wstrb[17*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_17_WDATA_PARITY(32'd0), + .AXI_17_WVALID(m_axi_hbm_wvalid[17 +: 1]), + .AXI_17_WREADY(m_axi_hbm_wready[17 +: 1]), + .AXI_17_BID(m_axi_hbm_bid[17*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_17_BRESP(m_axi_hbm_bresp[17*2 +: 2]), + .AXI_17_BVALID(m_axi_hbm_bvalid[17 +: 1]), + .AXI_17_BREADY(m_axi_hbm_bready[17 +: 1]), + + .AXI_18_ACLK(hbm_clk[18 +: 1]), + .AXI_18_ARESET_N(!hbm_rst[18 +: 1]), + + .AXI_18_ARADDR(m_axi_hbm_araddr[18*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_18_ARBURST(m_axi_hbm_arburst[18*2 +: 2]), + .AXI_18_ARID(m_axi_hbm_arid[18*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_18_ARLEN(m_axi_hbm_arlen[18*8 +: 8]), + .AXI_18_ARSIZE(m_axi_hbm_arsize[18*3 +: 3]), + .AXI_18_ARVALID(m_axi_hbm_arvalid[18 +: 1]), + .AXI_18_ARREADY(m_axi_hbm_arready[18 +: 1]), + .AXI_18_RDATA_PARITY(), + .AXI_18_RDATA(m_axi_hbm_rdata[18*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_18_RID(m_axi_hbm_rid[18 +: 1]), + .AXI_18_RLAST(m_axi_hbm_rlast[18 +: 1]), + .AXI_18_RRESP(m_axi_hbm_rresp[18*2 +: 2]), + .AXI_18_RVALID(m_axi_hbm_rvalid[18 +: 1]), + .AXI_18_RREADY(m_axi_hbm_rready[18 +: 1]), + .AXI_18_AWADDR(m_axi_hbm_awaddr[18*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_18_AWBURST(m_axi_hbm_awburst[18*2 +: 2]), + .AXI_18_AWID(m_axi_hbm_awid[18*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_18_AWLEN(m_axi_hbm_awlen[18*8 +: 8]), + .AXI_18_AWSIZE(m_axi_hbm_awsize[18*3 +: 3]), + .AXI_18_AWVALID(m_axi_hbm_awvalid[18 +: 1]), + .AXI_18_AWREADY(m_axi_hbm_awready[18 +: 1]), + .AXI_18_WDATA(m_axi_hbm_wdata[18*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_18_WLAST(m_axi_hbm_wlast[18 +: 1]), + .AXI_18_WSTRB(m_axi_hbm_wstrb[18*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_18_WDATA_PARITY(32'd0), + .AXI_18_WVALID(m_axi_hbm_wvalid[18 +: 1]), + .AXI_18_WREADY(m_axi_hbm_wready[18 +: 1]), + .AXI_18_BID(m_axi_hbm_bid[18*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_18_BRESP(m_axi_hbm_bresp[18*2 +: 2]), + .AXI_18_BVALID(m_axi_hbm_bvalid[18 +: 1]), + .AXI_18_BREADY(m_axi_hbm_bready[18 +: 1]), + + .AXI_19_ACLK(hbm_clk[19 +: 1]), + .AXI_19_ARESET_N(!hbm_rst[19 +: 1]), + + .AXI_19_ARADDR(m_axi_hbm_araddr[19*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_19_ARBURST(m_axi_hbm_arburst[19*2 +: 2]), + .AXI_19_ARID(m_axi_hbm_arid[19*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_19_ARLEN(m_axi_hbm_arlen[19*8 +: 8]), + .AXI_19_ARSIZE(m_axi_hbm_arsize[19*3 +: 3]), + .AXI_19_ARVALID(m_axi_hbm_arvalid[19 +: 1]), + .AXI_19_ARREADY(m_axi_hbm_arready[19 +: 1]), + .AXI_19_RDATA_PARITY(), + .AXI_19_RDATA(m_axi_hbm_rdata[19*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_19_RID(m_axi_hbm_rid[19 +: 1]), + .AXI_19_RLAST(m_axi_hbm_rlast[19 +: 1]), + .AXI_19_RRESP(m_axi_hbm_rresp[19*2 +: 2]), + .AXI_19_RVALID(m_axi_hbm_rvalid[19 +: 1]), + .AXI_19_RREADY(m_axi_hbm_rready[19 +: 1]), + .AXI_19_AWADDR(m_axi_hbm_awaddr[19*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_19_AWBURST(m_axi_hbm_awburst[19*2 +: 2]), + .AXI_19_AWID(m_axi_hbm_awid[19*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_19_AWLEN(m_axi_hbm_awlen[19*8 +: 8]), + .AXI_19_AWSIZE(m_axi_hbm_awsize[19*3 +: 3]), + .AXI_19_AWVALID(m_axi_hbm_awvalid[19 +: 1]), + .AXI_19_AWREADY(m_axi_hbm_awready[19 +: 1]), + .AXI_19_WDATA(m_axi_hbm_wdata[19*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_19_WLAST(m_axi_hbm_wlast[19 +: 1]), + .AXI_19_WSTRB(m_axi_hbm_wstrb[19*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_19_WDATA_PARITY(32'd0), + .AXI_19_WVALID(m_axi_hbm_wvalid[19 +: 1]), + .AXI_19_WREADY(m_axi_hbm_wready[19 +: 1]), + .AXI_19_BID(m_axi_hbm_bid[19*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_19_BRESP(m_axi_hbm_bresp[19*2 +: 2]), + .AXI_19_BVALID(m_axi_hbm_bvalid[19 +: 1]), + .AXI_19_BREADY(m_axi_hbm_bready[19 +: 1]), + + .AXI_20_ACLK(hbm_clk[20 +: 1]), + .AXI_20_ARESET_N(!hbm_rst[20 +: 1]), + + .AXI_20_ARADDR(m_axi_hbm_araddr[20*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_20_ARBURST(m_axi_hbm_arburst[20*2 +: 2]), + .AXI_20_ARID(m_axi_hbm_arid[20*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_20_ARLEN(m_axi_hbm_arlen[20*8 +: 8]), + .AXI_20_ARSIZE(m_axi_hbm_arsize[20*3 +: 3]), + .AXI_20_ARVALID(m_axi_hbm_arvalid[20 +: 1]), + .AXI_20_ARREADY(m_axi_hbm_arready[20 +: 1]), + .AXI_20_RDATA_PARITY(), + .AXI_20_RDATA(m_axi_hbm_rdata[20*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_20_RID(m_axi_hbm_rid[20 +: 1]), + .AXI_20_RLAST(m_axi_hbm_rlast[20 +: 1]), + .AXI_20_RRESP(m_axi_hbm_rresp[20*2 +: 2]), + .AXI_20_RVALID(m_axi_hbm_rvalid[20 +: 1]), + .AXI_20_RREADY(m_axi_hbm_rready[20 +: 1]), + .AXI_20_AWADDR(m_axi_hbm_awaddr[20*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_20_AWBURST(m_axi_hbm_awburst[20*2 +: 2]), + .AXI_20_AWID(m_axi_hbm_awid[20*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_20_AWLEN(m_axi_hbm_awlen[20*8 +: 8]), + .AXI_20_AWSIZE(m_axi_hbm_awsize[20*3 +: 3]), + .AXI_20_AWVALID(m_axi_hbm_awvalid[20 +: 1]), + .AXI_20_AWREADY(m_axi_hbm_awready[20 +: 1]), + .AXI_20_WDATA(m_axi_hbm_wdata[20*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_20_WLAST(m_axi_hbm_wlast[20 +: 1]), + .AXI_20_WSTRB(m_axi_hbm_wstrb[20*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_20_WDATA_PARITY(32'd0), + .AXI_20_WVALID(m_axi_hbm_wvalid[20 +: 1]), + .AXI_20_WREADY(m_axi_hbm_wready[20 +: 1]), + .AXI_20_BID(m_axi_hbm_bid[20*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_20_BRESP(m_axi_hbm_bresp[20*2 +: 2]), + .AXI_20_BVALID(m_axi_hbm_bvalid[20 +: 1]), + .AXI_20_BREADY(m_axi_hbm_bready[20 +: 1]), + + .AXI_21_ACLK(hbm_clk[21 +: 1]), + .AXI_21_ARESET_N(!hbm_rst[21 +: 1]), + + .AXI_21_ARADDR(m_axi_hbm_araddr[21*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_21_ARBURST(m_axi_hbm_arburst[21*2 +: 2]), + .AXI_21_ARID(m_axi_hbm_arid[21*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_21_ARLEN(m_axi_hbm_arlen[21*8 +: 8]), + .AXI_21_ARSIZE(m_axi_hbm_arsize[21*3 +: 3]), + .AXI_21_ARVALID(m_axi_hbm_arvalid[21 +: 1]), + .AXI_21_ARREADY(m_axi_hbm_arready[21 +: 1]), + .AXI_21_RDATA_PARITY(), + .AXI_21_RDATA(m_axi_hbm_rdata[21*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_21_RID(m_axi_hbm_rid[21 +: 1]), + .AXI_21_RLAST(m_axi_hbm_rlast[21 +: 1]), + .AXI_21_RRESP(m_axi_hbm_rresp[21*2 +: 2]), + .AXI_21_RVALID(m_axi_hbm_rvalid[21 +: 1]), + .AXI_21_RREADY(m_axi_hbm_rready[21 +: 1]), + .AXI_21_AWADDR(m_axi_hbm_awaddr[21*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_21_AWBURST(m_axi_hbm_awburst[21*2 +: 2]), + .AXI_21_AWID(m_axi_hbm_awid[21*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_21_AWLEN(m_axi_hbm_awlen[21*8 +: 8]), + .AXI_21_AWSIZE(m_axi_hbm_awsize[21*3 +: 3]), + .AXI_21_AWVALID(m_axi_hbm_awvalid[21 +: 1]), + .AXI_21_AWREADY(m_axi_hbm_awready[21 +: 1]), + .AXI_21_WDATA(m_axi_hbm_wdata[21*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_21_WLAST(m_axi_hbm_wlast[21 +: 1]), + .AXI_21_WSTRB(m_axi_hbm_wstrb[21*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_21_WDATA_PARITY(32'd0), + .AXI_21_WVALID(m_axi_hbm_wvalid[21 +: 1]), + .AXI_21_WREADY(m_axi_hbm_wready[21 +: 1]), + .AXI_21_BID(m_axi_hbm_bid[21*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_21_BRESP(m_axi_hbm_bresp[21*2 +: 2]), + .AXI_21_BVALID(m_axi_hbm_bvalid[21 +: 1]), + .AXI_21_BREADY(m_axi_hbm_bready[21 +: 1]), + + .AXI_22_ACLK(hbm_clk[22 +: 1]), + .AXI_22_ARESET_N(!hbm_rst[22 +: 1]), + + .AXI_22_ARADDR(m_axi_hbm_araddr[22*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_22_ARBURST(m_axi_hbm_arburst[22*2 +: 2]), + .AXI_22_ARID(m_axi_hbm_arid[22*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_22_ARLEN(m_axi_hbm_arlen[22*8 +: 8]), + .AXI_22_ARSIZE(m_axi_hbm_arsize[22*3 +: 3]), + .AXI_22_ARVALID(m_axi_hbm_arvalid[22 +: 1]), + .AXI_22_ARREADY(m_axi_hbm_arready[22 +: 1]), + .AXI_22_RDATA_PARITY(), + .AXI_22_RDATA(m_axi_hbm_rdata[22*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_22_RID(m_axi_hbm_rid[22 +: 1]), + .AXI_22_RLAST(m_axi_hbm_rlast[22 +: 1]), + .AXI_22_RRESP(m_axi_hbm_rresp[22*2 +: 2]), + .AXI_22_RVALID(m_axi_hbm_rvalid[22 +: 1]), + .AXI_22_RREADY(m_axi_hbm_rready[22 +: 1]), + .AXI_22_AWADDR(m_axi_hbm_awaddr[22*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_22_AWBURST(m_axi_hbm_awburst[22*2 +: 2]), + .AXI_22_AWID(m_axi_hbm_awid[22*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_22_AWLEN(m_axi_hbm_awlen[22*8 +: 8]), + .AXI_22_AWSIZE(m_axi_hbm_awsize[22*3 +: 3]), + .AXI_22_AWVALID(m_axi_hbm_awvalid[22 +: 1]), + .AXI_22_AWREADY(m_axi_hbm_awready[22 +: 1]), + .AXI_22_WDATA(m_axi_hbm_wdata[22*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_22_WLAST(m_axi_hbm_wlast[22 +: 1]), + .AXI_22_WSTRB(m_axi_hbm_wstrb[22*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_22_WDATA_PARITY(32'd0), + .AXI_22_WVALID(m_axi_hbm_wvalid[22 +: 1]), + .AXI_22_WREADY(m_axi_hbm_wready[22 +: 1]), + .AXI_22_BID(m_axi_hbm_bid[22*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_22_BRESP(m_axi_hbm_bresp[22*2 +: 2]), + .AXI_22_BVALID(m_axi_hbm_bvalid[22 +: 1]), + .AXI_22_BREADY(m_axi_hbm_bready[22 +: 1]), + + .AXI_23_ACLK(hbm_clk[23 +: 1]), + .AXI_23_ARESET_N(!hbm_rst[23 +: 1]), + + .AXI_23_ARADDR(m_axi_hbm_araddr[23*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_23_ARBURST(m_axi_hbm_arburst[23*2 +: 2]), + .AXI_23_ARID(m_axi_hbm_arid[23*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_23_ARLEN(m_axi_hbm_arlen[23*8 +: 8]), + .AXI_23_ARSIZE(m_axi_hbm_arsize[23*3 +: 3]), + .AXI_23_ARVALID(m_axi_hbm_arvalid[23 +: 1]), + .AXI_23_ARREADY(m_axi_hbm_arready[23 +: 1]), + .AXI_23_RDATA_PARITY(), + .AXI_23_RDATA(m_axi_hbm_rdata[23*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_23_RID(m_axi_hbm_rid[23 +: 1]), + .AXI_23_RLAST(m_axi_hbm_rlast[23 +: 1]), + .AXI_23_RRESP(m_axi_hbm_rresp[23*2 +: 2]), + .AXI_23_RVALID(m_axi_hbm_rvalid[23 +: 1]), + .AXI_23_RREADY(m_axi_hbm_rready[23 +: 1]), + .AXI_23_AWADDR(m_axi_hbm_awaddr[23*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_23_AWBURST(m_axi_hbm_awburst[23*2 +: 2]), + .AXI_23_AWID(m_axi_hbm_awid[23*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_23_AWLEN(m_axi_hbm_awlen[23*8 +: 8]), + .AXI_23_AWSIZE(m_axi_hbm_awsize[23*3 +: 3]), + .AXI_23_AWVALID(m_axi_hbm_awvalid[23 +: 1]), + .AXI_23_AWREADY(m_axi_hbm_awready[23 +: 1]), + .AXI_23_WDATA(m_axi_hbm_wdata[23*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_23_WLAST(m_axi_hbm_wlast[23 +: 1]), + .AXI_23_WSTRB(m_axi_hbm_wstrb[23*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_23_WDATA_PARITY(32'd0), + .AXI_23_WVALID(m_axi_hbm_wvalid[23 +: 1]), + .AXI_23_WREADY(m_axi_hbm_wready[23 +: 1]), + .AXI_23_BID(m_axi_hbm_bid[23*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_23_BRESP(m_axi_hbm_bresp[23*2 +: 2]), + .AXI_23_BVALID(m_axi_hbm_bvalid[23 +: 1]), + .AXI_23_BREADY(m_axi_hbm_bready[23 +: 1]), + + .AXI_24_ACLK(hbm_clk[24 +: 1]), + .AXI_24_ARESET_N(!hbm_rst[24 +: 1]), + + .AXI_24_ARADDR(m_axi_hbm_araddr[24*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_24_ARBURST(m_axi_hbm_arburst[24*2 +: 2]), + .AXI_24_ARID(m_axi_hbm_arid[24*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_24_ARLEN(m_axi_hbm_arlen[24*8 +: 8]), + .AXI_24_ARSIZE(m_axi_hbm_arsize[24*3 +: 3]), + .AXI_24_ARVALID(m_axi_hbm_arvalid[24 +: 1]), + .AXI_24_ARREADY(m_axi_hbm_arready[24 +: 1]), + .AXI_24_RDATA_PARITY(), + .AXI_24_RDATA(m_axi_hbm_rdata[24*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_24_RID(m_axi_hbm_rid[24 +: 1]), + .AXI_24_RLAST(m_axi_hbm_rlast[24 +: 1]), + .AXI_24_RRESP(m_axi_hbm_rresp[24*2 +: 2]), + .AXI_24_RVALID(m_axi_hbm_rvalid[24 +: 1]), + .AXI_24_RREADY(m_axi_hbm_rready[24 +: 1]), + .AXI_24_AWADDR(m_axi_hbm_awaddr[24*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_24_AWBURST(m_axi_hbm_awburst[24*2 +: 2]), + .AXI_24_AWID(m_axi_hbm_awid[24*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_24_AWLEN(m_axi_hbm_awlen[24*8 +: 8]), + .AXI_24_AWSIZE(m_axi_hbm_awsize[24*3 +: 3]), + .AXI_24_AWVALID(m_axi_hbm_awvalid[24 +: 1]), + .AXI_24_AWREADY(m_axi_hbm_awready[24 +: 1]), + .AXI_24_WDATA(m_axi_hbm_wdata[24*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_24_WLAST(m_axi_hbm_wlast[24 +: 1]), + .AXI_24_WSTRB(m_axi_hbm_wstrb[24*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_24_WDATA_PARITY(32'd0), + .AXI_24_WVALID(m_axi_hbm_wvalid[24 +: 1]), + .AXI_24_WREADY(m_axi_hbm_wready[24 +: 1]), + .AXI_24_BID(m_axi_hbm_bid[24*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_24_BRESP(m_axi_hbm_bresp[24*2 +: 2]), + .AXI_24_BVALID(m_axi_hbm_bvalid[24 +: 1]), + .AXI_24_BREADY(m_axi_hbm_bready[24 +: 1]), + + .AXI_25_ACLK(hbm_clk[25 +: 1]), + .AXI_25_ARESET_N(!hbm_rst[25 +: 1]), + + .AXI_25_ARADDR(m_axi_hbm_araddr[25*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_25_ARBURST(m_axi_hbm_arburst[25*2 +: 2]), + .AXI_25_ARID(m_axi_hbm_arid[25*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_25_ARLEN(m_axi_hbm_arlen[25*8 +: 8]), + .AXI_25_ARSIZE(m_axi_hbm_arsize[25*3 +: 3]), + .AXI_25_ARVALID(m_axi_hbm_arvalid[25 +: 1]), + .AXI_25_ARREADY(m_axi_hbm_arready[25 +: 1]), + .AXI_25_RDATA_PARITY(), + .AXI_25_RDATA(m_axi_hbm_rdata[25*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_25_RID(m_axi_hbm_rid[25 +: 1]), + .AXI_25_RLAST(m_axi_hbm_rlast[25 +: 1]), + .AXI_25_RRESP(m_axi_hbm_rresp[25*2 +: 2]), + .AXI_25_RVALID(m_axi_hbm_rvalid[25 +: 1]), + .AXI_25_RREADY(m_axi_hbm_rready[25 +: 1]), + .AXI_25_AWADDR(m_axi_hbm_awaddr[25*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_25_AWBURST(m_axi_hbm_awburst[25*2 +: 2]), + .AXI_25_AWID(m_axi_hbm_awid[25*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_25_AWLEN(m_axi_hbm_awlen[25*8 +: 8]), + .AXI_25_AWSIZE(m_axi_hbm_awsize[25*3 +: 3]), + .AXI_25_AWVALID(m_axi_hbm_awvalid[25 +: 1]), + .AXI_25_AWREADY(m_axi_hbm_awready[25 +: 1]), + .AXI_25_WDATA(m_axi_hbm_wdata[25*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_25_WLAST(m_axi_hbm_wlast[25 +: 1]), + .AXI_25_WSTRB(m_axi_hbm_wstrb[25*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_25_WDATA_PARITY(32'd0), + .AXI_25_WVALID(m_axi_hbm_wvalid[25 +: 1]), + .AXI_25_WREADY(m_axi_hbm_wready[25 +: 1]), + .AXI_25_BID(m_axi_hbm_bid[25*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_25_BRESP(m_axi_hbm_bresp[25*2 +: 2]), + .AXI_25_BVALID(m_axi_hbm_bvalid[25 +: 1]), + .AXI_25_BREADY(m_axi_hbm_bready[25 +: 1]), + + .AXI_26_ACLK(hbm_clk[26 +: 1]), + .AXI_26_ARESET_N(!hbm_rst[26 +: 1]), + + .AXI_26_ARADDR(m_axi_hbm_araddr[26*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_26_ARBURST(m_axi_hbm_arburst[26*2 +: 2]), + .AXI_26_ARID(m_axi_hbm_arid[26*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_26_ARLEN(m_axi_hbm_arlen[26*8 +: 8]), + .AXI_26_ARSIZE(m_axi_hbm_arsize[26*3 +: 3]), + .AXI_26_ARVALID(m_axi_hbm_arvalid[26 +: 1]), + .AXI_26_ARREADY(m_axi_hbm_arready[26 +: 1]), + .AXI_26_RDATA_PARITY(), + .AXI_26_RDATA(m_axi_hbm_rdata[26*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_26_RID(m_axi_hbm_rid[26 +: 1]), + .AXI_26_RLAST(m_axi_hbm_rlast[26 +: 1]), + .AXI_26_RRESP(m_axi_hbm_rresp[26*2 +: 2]), + .AXI_26_RVALID(m_axi_hbm_rvalid[26 +: 1]), + .AXI_26_RREADY(m_axi_hbm_rready[26 +: 1]), + .AXI_26_AWADDR(m_axi_hbm_awaddr[26*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_26_AWBURST(m_axi_hbm_awburst[26*2 +: 2]), + .AXI_26_AWID(m_axi_hbm_awid[26*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_26_AWLEN(m_axi_hbm_awlen[26*8 +: 8]), + .AXI_26_AWSIZE(m_axi_hbm_awsize[26*3 +: 3]), + .AXI_26_AWVALID(m_axi_hbm_awvalid[26 +: 1]), + .AXI_26_AWREADY(m_axi_hbm_awready[26 +: 1]), + .AXI_26_WDATA(m_axi_hbm_wdata[26*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_26_WLAST(m_axi_hbm_wlast[26 +: 1]), + .AXI_26_WSTRB(m_axi_hbm_wstrb[26*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_26_WDATA_PARITY(32'd0), + .AXI_26_WVALID(m_axi_hbm_wvalid[26 +: 1]), + .AXI_26_WREADY(m_axi_hbm_wready[26 +: 1]), + .AXI_26_BID(m_axi_hbm_bid[26*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_26_BRESP(m_axi_hbm_bresp[26*2 +: 2]), + .AXI_26_BVALID(m_axi_hbm_bvalid[26 +: 1]), + .AXI_26_BREADY(m_axi_hbm_bready[26 +: 1]), + + .AXI_27_ACLK(hbm_clk[27 +: 1]), + .AXI_27_ARESET_N(!hbm_rst[27 +: 1]), + + .AXI_27_ARADDR(m_axi_hbm_araddr[27*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_27_ARBURST(m_axi_hbm_arburst[27*2 +: 2]), + .AXI_27_ARID(m_axi_hbm_arid[27*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_27_ARLEN(m_axi_hbm_arlen[27*8 +: 8]), + .AXI_27_ARSIZE(m_axi_hbm_arsize[27*3 +: 3]), + .AXI_27_ARVALID(m_axi_hbm_arvalid[27 +: 1]), + .AXI_27_ARREADY(m_axi_hbm_arready[27 +: 1]), + .AXI_27_RDATA_PARITY(), + .AXI_27_RDATA(m_axi_hbm_rdata[27*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_27_RID(m_axi_hbm_rid[27 +: 1]), + .AXI_27_RLAST(m_axi_hbm_rlast[27 +: 1]), + .AXI_27_RRESP(m_axi_hbm_rresp[27*2 +: 2]), + .AXI_27_RVALID(m_axi_hbm_rvalid[27 +: 1]), + .AXI_27_RREADY(m_axi_hbm_rready[27 +: 1]), + .AXI_27_AWADDR(m_axi_hbm_awaddr[27*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_27_AWBURST(m_axi_hbm_awburst[27*2 +: 2]), + .AXI_27_AWID(m_axi_hbm_awid[27*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_27_AWLEN(m_axi_hbm_awlen[27*8 +: 8]), + .AXI_27_AWSIZE(m_axi_hbm_awsize[27*3 +: 3]), + .AXI_27_AWVALID(m_axi_hbm_awvalid[27 +: 1]), + .AXI_27_AWREADY(m_axi_hbm_awready[27 +: 1]), + .AXI_27_WDATA(m_axi_hbm_wdata[27*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_27_WLAST(m_axi_hbm_wlast[27 +: 1]), + .AXI_27_WSTRB(m_axi_hbm_wstrb[27*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_27_WDATA_PARITY(32'd0), + .AXI_27_WVALID(m_axi_hbm_wvalid[27 +: 1]), + .AXI_27_WREADY(m_axi_hbm_wready[27 +: 1]), + .AXI_27_BID(m_axi_hbm_bid[27*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_27_BRESP(m_axi_hbm_bresp[27*2 +: 2]), + .AXI_27_BVALID(m_axi_hbm_bvalid[27 +: 1]), + .AXI_27_BREADY(m_axi_hbm_bready[27 +: 1]), + + .AXI_28_ACLK(hbm_clk[28 +: 1]), + .AXI_28_ARESET_N(!hbm_rst[28 +: 1]), + + .AXI_28_ARADDR(m_axi_hbm_araddr[28*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_28_ARBURST(m_axi_hbm_arburst[28*2 +: 2]), + .AXI_28_ARID(m_axi_hbm_arid[28*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_28_ARLEN(m_axi_hbm_arlen[28*8 +: 8]), + .AXI_28_ARSIZE(m_axi_hbm_arsize[28*3 +: 3]), + .AXI_28_ARVALID(m_axi_hbm_arvalid[28 +: 1]), + .AXI_28_ARREADY(m_axi_hbm_arready[28 +: 1]), + .AXI_28_RDATA_PARITY(), + .AXI_28_RDATA(m_axi_hbm_rdata[28*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_28_RID(m_axi_hbm_rid[28 +: 1]), + .AXI_28_RLAST(m_axi_hbm_rlast[28 +: 1]), + .AXI_28_RRESP(m_axi_hbm_rresp[28*2 +: 2]), + .AXI_28_RVALID(m_axi_hbm_rvalid[28 +: 1]), + .AXI_28_RREADY(m_axi_hbm_rready[28 +: 1]), + .AXI_28_AWADDR(m_axi_hbm_awaddr[28*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_28_AWBURST(m_axi_hbm_awburst[28*2 +: 2]), + .AXI_28_AWID(m_axi_hbm_awid[28*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_28_AWLEN(m_axi_hbm_awlen[28*8 +: 8]), + .AXI_28_AWSIZE(m_axi_hbm_awsize[28*3 +: 3]), + .AXI_28_AWVALID(m_axi_hbm_awvalid[28 +: 1]), + .AXI_28_AWREADY(m_axi_hbm_awready[28 +: 1]), + .AXI_28_WDATA(m_axi_hbm_wdata[28*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_28_WLAST(m_axi_hbm_wlast[28 +: 1]), + .AXI_28_WSTRB(m_axi_hbm_wstrb[28*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_28_WDATA_PARITY(32'd0), + .AXI_28_WVALID(m_axi_hbm_wvalid[28 +: 1]), + .AXI_28_WREADY(m_axi_hbm_wready[28 +: 1]), + .AXI_28_BID(m_axi_hbm_bid[28*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_28_BRESP(m_axi_hbm_bresp[28*2 +: 2]), + .AXI_28_BVALID(m_axi_hbm_bvalid[28 +: 1]), + .AXI_28_BREADY(m_axi_hbm_bready[28 +: 1]), + + .AXI_29_ACLK(hbm_clk[29 +: 1]), + .AXI_29_ARESET_N(!hbm_rst[29 +: 1]), + + .AXI_29_ARADDR(m_axi_hbm_araddr[29*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_29_ARBURST(m_axi_hbm_arburst[29*2 +: 2]), + .AXI_29_ARID(m_axi_hbm_arid[29*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_29_ARLEN(m_axi_hbm_arlen[29*8 +: 8]), + .AXI_29_ARSIZE(m_axi_hbm_arsize[29*3 +: 3]), + .AXI_29_ARVALID(m_axi_hbm_arvalid[29 +: 1]), + .AXI_29_ARREADY(m_axi_hbm_arready[29 +: 1]), + .AXI_29_RDATA_PARITY(), + .AXI_29_RDATA(m_axi_hbm_rdata[29*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_29_RID(m_axi_hbm_rid[29 +: 1]), + .AXI_29_RLAST(m_axi_hbm_rlast[29 +: 1]), + .AXI_29_RRESP(m_axi_hbm_rresp[29*2 +: 2]), + .AXI_29_RVALID(m_axi_hbm_rvalid[29 +: 1]), + .AXI_29_RREADY(m_axi_hbm_rready[29 +: 1]), + .AXI_29_AWADDR(m_axi_hbm_awaddr[29*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_29_AWBURST(m_axi_hbm_awburst[29*2 +: 2]), + .AXI_29_AWID(m_axi_hbm_awid[29*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_29_AWLEN(m_axi_hbm_awlen[29*8 +: 8]), + .AXI_29_AWSIZE(m_axi_hbm_awsize[29*3 +: 3]), + .AXI_29_AWVALID(m_axi_hbm_awvalid[29 +: 1]), + .AXI_29_AWREADY(m_axi_hbm_awready[29 +: 1]), + .AXI_29_WDATA(m_axi_hbm_wdata[29*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_29_WLAST(m_axi_hbm_wlast[29 +: 1]), + .AXI_29_WSTRB(m_axi_hbm_wstrb[29*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_29_WDATA_PARITY(32'd0), + .AXI_29_WVALID(m_axi_hbm_wvalid[29 +: 1]), + .AXI_29_WREADY(m_axi_hbm_wready[29 +: 1]), + .AXI_29_BID(m_axi_hbm_bid[29*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_29_BRESP(m_axi_hbm_bresp[29*2 +: 2]), + .AXI_29_BVALID(m_axi_hbm_bvalid[29 +: 1]), + .AXI_29_BREADY(m_axi_hbm_bready[29 +: 1]), + + .AXI_30_ACLK(hbm_clk[30 +: 1]), + .AXI_30_ARESET_N(!hbm_rst[30 +: 1]), + + .AXI_30_ARADDR(m_axi_hbm_araddr[30*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_30_ARBURST(m_axi_hbm_arburst[30*2 +: 2]), + .AXI_30_ARID(m_axi_hbm_arid[30*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_30_ARLEN(m_axi_hbm_arlen[30*8 +: 8]), + .AXI_30_ARSIZE(m_axi_hbm_arsize[30*3 +: 3]), + .AXI_30_ARVALID(m_axi_hbm_arvalid[30 +: 1]), + .AXI_30_ARREADY(m_axi_hbm_arready[30 +: 1]), + .AXI_30_RDATA_PARITY(), + .AXI_30_RDATA(m_axi_hbm_rdata[30*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_30_RID(m_axi_hbm_rid[30 +: 1]), + .AXI_30_RLAST(m_axi_hbm_rlast[30 +: 1]), + .AXI_30_RRESP(m_axi_hbm_rresp[30*2 +: 2]), + .AXI_30_RVALID(m_axi_hbm_rvalid[30 +: 1]), + .AXI_30_RREADY(m_axi_hbm_rready[30 +: 1]), + .AXI_30_AWADDR(m_axi_hbm_awaddr[30*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_30_AWBURST(m_axi_hbm_awburst[30*2 +: 2]), + .AXI_30_AWID(m_axi_hbm_awid[30*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_30_AWLEN(m_axi_hbm_awlen[30*8 +: 8]), + .AXI_30_AWSIZE(m_axi_hbm_awsize[30*3 +: 3]), + .AXI_30_AWVALID(m_axi_hbm_awvalid[30 +: 1]), + .AXI_30_AWREADY(m_axi_hbm_awready[30 +: 1]), + .AXI_30_WDATA(m_axi_hbm_wdata[30*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_30_WLAST(m_axi_hbm_wlast[30 +: 1]), + .AXI_30_WSTRB(m_axi_hbm_wstrb[30*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_30_WDATA_PARITY(32'd0), + .AXI_30_WVALID(m_axi_hbm_wvalid[30 +: 1]), + .AXI_30_WREADY(m_axi_hbm_wready[30 +: 1]), + .AXI_30_BID(m_axi_hbm_bid[30*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_30_BRESP(m_axi_hbm_bresp[30*2 +: 2]), + .AXI_30_BVALID(m_axi_hbm_bvalid[30 +: 1]), + .AXI_30_BREADY(m_axi_hbm_bready[30 +: 1]), + + .AXI_31_ACLK(hbm_clk[31 +: 1]), + .AXI_31_ARESET_N(!hbm_rst[31 +: 1]), + + .AXI_31_ARADDR(m_axi_hbm_araddr[31*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_31_ARBURST(m_axi_hbm_arburst[31*2 +: 2]), + .AXI_31_ARID(m_axi_hbm_arid[31*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_31_ARLEN(m_axi_hbm_arlen[31*8 +: 8]), + .AXI_31_ARSIZE(m_axi_hbm_arsize[31*3 +: 3]), + .AXI_31_ARVALID(m_axi_hbm_arvalid[31 +: 1]), + .AXI_31_ARREADY(m_axi_hbm_arready[31 +: 1]), + .AXI_31_RDATA_PARITY(), + .AXI_31_RDATA(m_axi_hbm_rdata[31*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_31_RID(m_axi_hbm_rid[31 +: 1]), + .AXI_31_RLAST(m_axi_hbm_rlast[31 +: 1]), + .AXI_31_RRESP(m_axi_hbm_rresp[31*2 +: 2]), + .AXI_31_RVALID(m_axi_hbm_rvalid[31 +: 1]), + .AXI_31_RREADY(m_axi_hbm_rready[31 +: 1]), + .AXI_31_AWADDR(m_axi_hbm_awaddr[31*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_31_AWBURST(m_axi_hbm_awburst[31*2 +: 2]), + .AXI_31_AWID(m_axi_hbm_awid[31*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_31_AWLEN(m_axi_hbm_awlen[31*8 +: 8]), + .AXI_31_AWSIZE(m_axi_hbm_awsize[31*3 +: 3]), + .AXI_31_AWVALID(m_axi_hbm_awvalid[31 +: 1]), + .AXI_31_AWREADY(m_axi_hbm_awready[31 +: 1]), + .AXI_31_WDATA(m_axi_hbm_wdata[31*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_31_WLAST(m_axi_hbm_wlast[31 +: 1]), + .AXI_31_WSTRB(m_axi_hbm_wstrb[31*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_31_WDATA_PARITY(32'd0), + .AXI_31_WVALID(m_axi_hbm_wvalid[31 +: 1]), + .AXI_31_WREADY(m_axi_hbm_wready[31 +: 1]), + .AXI_31_BID(m_axi_hbm_bid[31*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_31_BRESP(m_axi_hbm_bresp[31*2 +: 2]), + .AXI_31_BVALID(m_axi_hbm_bvalid[31 +: 1]), + .AXI_31_BREADY(m_axi_hbm_bready[31 +: 1]), + + .DRAM_0_STAT_CATTRIP(hbm_cattrip_1), + .DRAM_0_STAT_TEMP(hbm_temp_1), + .DRAM_1_STAT_CATTRIP(hbm_cattrip_2), + .DRAM_1_STAT_TEMP(hbm_temp_2) +); + +assign hbm_status = {HBM_CH{1'b1}}; + +end else begin + +assign hbm_clk = 0; +assign hbm_rst = 0; + +assign m_axi_hbm_awready = 0; +assign m_axi_hbm_wready = 0; +assign m_axi_hbm_bid = 0; +assign m_axi_hbm_bresp = 0; +assign m_axi_hbm_bvalid = 0; +assign m_axi_hbm_arready = 0; +assign m_axi_hbm_rid = 0; +assign m_axi_hbm_rdata = 0; +assign m_axi_hbm_rresp = 0; +assign m_axi_hbm_rlast = 0; +assign m_axi_hbm_rvalid = 0; + +assign hbm_status = 0; + +end + +endgenerate + fpga_core #( // FW and board IDs .FPGA_ID(FPGA_ID), @@ -1425,6 +2795,16 @@ fpga_core #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .HBM_CH(HBM_CH), + .HBM_ENABLE(HBM_ENABLE), + .HBM_GROUP_SIZE(HBM_GROUP_SIZE), + .AXI_HBM_DATA_WIDTH(AXI_HBM_DATA_WIDTH), + .AXI_HBM_ADDR_WIDTH(AXI_HBM_ADDR_WIDTH), + .AXI_HBM_STRB_WIDTH(AXI_HBM_STRB_WIDTH), + .AXI_HBM_ID_WIDTH(AXI_HBM_ID_WIDTH), + .AXI_HBM_MAX_BURST_LEN(AXI_HBM_MAX_BURST_LEN), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1617,6 +2997,50 @@ core_inst ( .qsfp_rx_ptp_time(qsfp_rx_ptp_time_int), .qsfp_rx_status(qsfp_rx_status), + /* + * HBM + */ + .hbm_clk(hbm_clk), + .hbm_rst(hbm_rst), + + .m_axi_hbm_awid(m_axi_hbm_awid), + .m_axi_hbm_awaddr(m_axi_hbm_awaddr), + .m_axi_hbm_awlen(m_axi_hbm_awlen), + .m_axi_hbm_awsize(m_axi_hbm_awsize), + .m_axi_hbm_awburst(m_axi_hbm_awburst), + .m_axi_hbm_awlock(m_axi_hbm_awlock), + .m_axi_hbm_awcache(m_axi_hbm_awcache), + .m_axi_hbm_awprot(m_axi_hbm_awprot), + .m_axi_hbm_awqos(m_axi_hbm_awqos), + .m_axi_hbm_awvalid(m_axi_hbm_awvalid), + .m_axi_hbm_awready(m_axi_hbm_awready), + .m_axi_hbm_wdata(m_axi_hbm_wdata), + .m_axi_hbm_wstrb(m_axi_hbm_wstrb), + .m_axi_hbm_wlast(m_axi_hbm_wlast), + .m_axi_hbm_wvalid(m_axi_hbm_wvalid), + .m_axi_hbm_wready(m_axi_hbm_wready), + .m_axi_hbm_bid(m_axi_hbm_bid), + .m_axi_hbm_bresp(m_axi_hbm_bresp), + .m_axi_hbm_bvalid(m_axi_hbm_bvalid), + .m_axi_hbm_bready(m_axi_hbm_bready), + .m_axi_hbm_arid(m_axi_hbm_arid), + .m_axi_hbm_araddr(m_axi_hbm_araddr), + .m_axi_hbm_arlen(m_axi_hbm_arlen), + .m_axi_hbm_arsize(m_axi_hbm_arsize), + .m_axi_hbm_arburst(m_axi_hbm_arburst), + .m_axi_hbm_arlock(m_axi_hbm_arlock), + .m_axi_hbm_arcache(m_axi_hbm_arcache), + .m_axi_hbm_arprot(m_axi_hbm_arprot), + .m_axi_hbm_arqos(m_axi_hbm_arqos), + .m_axi_hbm_arvalid(m_axi_hbm_arvalid), + .m_axi_hbm_arready(m_axi_hbm_arready), + .m_axi_hbm_rid(m_axi_hbm_rid), + .m_axi_hbm_rdata(m_axi_hbm_rdata), + .m_axi_hbm_rresp(m_axi_hbm_rresp), + .m_axi_hbm_rlast(m_axi_hbm_rlast), + .m_axi_hbm_rvalid(m_axi_hbm_rvalid), + .m_axi_hbm_rready(m_axi_hbm_rready), + /* * QSPI flash */ diff --git a/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v index 017578a4f..85f2472e2 100644 --- a/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v @@ -115,6 +115,16 @@ module fpga_core # parameter TX_RAM_SIZE = 131072, parameter RX_RAM_SIZE = 131072, + // RAM configuration + parameter HBM_CH = 32, + parameter HBM_ENABLE = 1, + parameter HBM_GROUP_SIZE = 32, + parameter AXI_HBM_DATA_WIDTH = 256, + parameter AXI_HBM_ADDR_WIDTH = 33, + parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8), + parameter AXI_HBM_ID_WIDTH = 6, + parameter AXI_HBM_MAX_BURST_LEN = 256, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -313,6 +323,52 @@ module fpga_core # input wire qsfp_rx_status, + /* + * HBM + */ + input wire [HBM_CH-1:0] hbm_clk, + input wire [HBM_CH-1:0] hbm_rst, + + output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_awid, + output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_awaddr, + output wire [HBM_CH*8-1:0] m_axi_hbm_awlen, + output wire [HBM_CH*3-1:0] m_axi_hbm_awsize, + output wire [HBM_CH*2-1:0] m_axi_hbm_awburst, + output wire [HBM_CH-1:0] m_axi_hbm_awlock, + output wire [HBM_CH*4-1:0] m_axi_hbm_awcache, + output wire [HBM_CH*3-1:0] m_axi_hbm_awprot, + output wire [HBM_CH*4-1:0] m_axi_hbm_awqos, + output wire [HBM_CH-1:0] m_axi_hbm_awvalid, + input wire [HBM_CH-1:0] m_axi_hbm_awready, + output wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_wdata, + output wire [HBM_CH*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_wstrb, + output wire [HBM_CH-1:0] m_axi_hbm_wlast, + output wire [HBM_CH-1:0] m_axi_hbm_wvalid, + input wire [HBM_CH-1:0] m_axi_hbm_wready, + input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_bid, + input wire [HBM_CH*2-1:0] m_axi_hbm_bresp, + input wire [HBM_CH-1:0] m_axi_hbm_bvalid, + output wire [HBM_CH-1:0] m_axi_hbm_bready, + output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_arid, + output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_araddr, + output wire [HBM_CH*8-1:0] m_axi_hbm_arlen, + output wire [HBM_CH*3-1:0] m_axi_hbm_arsize, + output wire [HBM_CH*2-1:0] m_axi_hbm_arburst, + output wire [HBM_CH-1:0] m_axi_hbm_arlock, + output wire [HBM_CH*4-1:0] m_axi_hbm_arcache, + output wire [HBM_CH*3-1:0] m_axi_hbm_arprot, + output wire [HBM_CH*4-1:0] m_axi_hbm_arqos, + output wire [HBM_CH-1:0] m_axi_hbm_arvalid, + input wire [HBM_CH-1:0] m_axi_hbm_arready, + input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_rid, + input wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_rdata, + input wire [HBM_CH*2-1:0] m_axi_hbm_rresp, + input wire [HBM_CH-1:0] m_axi_hbm_rlast, + input wire [HBM_CH-1:0] m_axi_hbm_rvalid, + output wire [HBM_CH-1:0] m_axi_hbm_rready, + + input wire [HBM_CH-1:0] hbm_status, + /* * QSPI flash */ @@ -769,6 +825,25 @@ mqnic_core_pcie_us #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_ENABLE(0), + .HBM_CH(HBM_CH), + .HBM_ENABLE(HBM_ENABLE), + .HBM_GROUP_SIZE(HBM_GROUP_SIZE), + .AXI_HBM_DATA_WIDTH(AXI_HBM_DATA_WIDTH), + .AXI_HBM_ADDR_WIDTH(AXI_HBM_ADDR_WIDTH), + .AXI_HBM_STRB_WIDTH(AXI_HBM_STRB_WIDTH), + .AXI_HBM_ID_WIDTH(AXI_HBM_ID_WIDTH), + .AXI_HBM_AWUSER_ENABLE(0), + .AXI_HBM_WUSER_ENABLE(0), + .AXI_HBM_BUSER_ENABLE(0), + .AXI_HBM_ARUSER_ENABLE(0), + .AXI_HBM_RUSER_ENABLE(0), + .AXI_HBM_MAX_BURST_LEN(AXI_HBM_MAX_BURST_LEN), + .AXI_HBM_NARROW_BURST(0), + .AXI_HBM_FIXED_BURST(0), + .AXI_HBM_WRAP_BURST(1), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1046,6 +1121,108 @@ core_inst ( .eth_rx_status(eth_rx_status), + /* + * DDR + */ + .ddr_clk(0), + .ddr_rst(0), + + .m_axi_ddr_awid(), + .m_axi_ddr_awaddr(), + .m_axi_ddr_awlen(), + .m_axi_ddr_awsize(), + .m_axi_ddr_awburst(), + .m_axi_ddr_awlock(), + .m_axi_ddr_awcache(), + .m_axi_ddr_awprot(), + .m_axi_ddr_awqos(), + .m_axi_ddr_awuser(), + .m_axi_ddr_awvalid(), + .m_axi_ddr_awready(0), + .m_axi_ddr_wdata(), + .m_axi_ddr_wstrb(), + .m_axi_ddr_wlast(), + .m_axi_ddr_wuser(), + .m_axi_ddr_wvalid(), + .m_axi_ddr_wready(0), + .m_axi_ddr_bid(0), + .m_axi_ddr_bresp(0), + .m_axi_ddr_buser(0), + .m_axi_ddr_bvalid(0), + .m_axi_ddr_bready(), + .m_axi_ddr_arid(), + .m_axi_ddr_araddr(), + .m_axi_ddr_arlen(), + .m_axi_ddr_arsize(), + .m_axi_ddr_arburst(), + .m_axi_ddr_arlock(), + .m_axi_ddr_arcache(), + .m_axi_ddr_arprot(), + .m_axi_ddr_arqos(), + .m_axi_ddr_aruser(), + .m_axi_ddr_arvalid(), + .m_axi_ddr_arready(0), + .m_axi_ddr_rid(0), + .m_axi_ddr_rdata(0), + .m_axi_ddr_rresp(0), + .m_axi_ddr_rlast(0), + .m_axi_ddr_ruser(0), + .m_axi_ddr_rvalid(0), + .m_axi_ddr_rready(), + + .ddr_status(0), + + /* + * HBM + */ + .hbm_clk(hbm_clk), + .hbm_rst(hbm_rst), + + .m_axi_hbm_awid(m_axi_hbm_awid), + .m_axi_hbm_awaddr(m_axi_hbm_awaddr), + .m_axi_hbm_awlen(m_axi_hbm_awlen), + .m_axi_hbm_awsize(m_axi_hbm_awsize), + .m_axi_hbm_awburst(m_axi_hbm_awburst), + .m_axi_hbm_awlock(m_axi_hbm_awlock), + .m_axi_hbm_awcache(m_axi_hbm_awcache), + .m_axi_hbm_awprot(m_axi_hbm_awprot), + .m_axi_hbm_awqos(m_axi_hbm_awqos), + .m_axi_hbm_awuser(), + .m_axi_hbm_awvalid(m_axi_hbm_awvalid), + .m_axi_hbm_awready(m_axi_hbm_awready), + .m_axi_hbm_wdata(m_axi_hbm_wdata), + .m_axi_hbm_wstrb(m_axi_hbm_wstrb), + .m_axi_hbm_wlast(m_axi_hbm_wlast), + .m_axi_hbm_wuser(), + .m_axi_hbm_wvalid(m_axi_hbm_wvalid), + .m_axi_hbm_wready(m_axi_hbm_wready), + .m_axi_hbm_bid(m_axi_hbm_bid), + .m_axi_hbm_bresp(m_axi_hbm_bresp), + .m_axi_hbm_buser(0), + .m_axi_hbm_bvalid(m_axi_hbm_bvalid), + .m_axi_hbm_bready(m_axi_hbm_bready), + .m_axi_hbm_arid(m_axi_hbm_arid), + .m_axi_hbm_araddr(m_axi_hbm_araddr), + .m_axi_hbm_arlen(m_axi_hbm_arlen), + .m_axi_hbm_arsize(m_axi_hbm_arsize), + .m_axi_hbm_arburst(m_axi_hbm_arburst), + .m_axi_hbm_arlock(m_axi_hbm_arlock), + .m_axi_hbm_arcache(m_axi_hbm_arcache), + .m_axi_hbm_arprot(m_axi_hbm_arprot), + .m_axi_hbm_arqos(m_axi_hbm_arqos), + .m_axi_hbm_aruser(), + .m_axi_hbm_arvalid(m_axi_hbm_arvalid), + .m_axi_hbm_arready(m_axi_hbm_arready), + .m_axi_hbm_rid(m_axi_hbm_rid), + .m_axi_hbm_rdata(m_axi_hbm_rdata), + .m_axi_hbm_rresp(m_axi_hbm_rresp), + .m_axi_hbm_rlast(m_axi_hbm_rlast), + .m_axi_hbm_ruser(0), + .m_axi_hbm_rvalid(m_axi_hbm_rvalid), + .m_axi_hbm_rready(m_axi_hbm_rready), + + .hbm_status(hbm_status), + /* * Statistics input */ diff --git a/fpga/mqnic/AU50/fpga_25g/README.md b/fpga/mqnic/AU50/fpga_25g/README.md index ecaaa76f1..32d935004 100644 --- a/fpga/mqnic/AU50/fpga_25g/README.md +++ b/fpga/mqnic/AU50/fpga_25g/README.md @@ -6,6 +6,7 @@ This design targets the Xilinx Alveo U50 FPGA board. * FPGA: xcu50-fsvh2104-2-e * PHY: 10G BASE-R PHY IP core and internal GTY transceivers +* RAM: 8GB HBM2 ## How to build diff --git a/fpga/mqnic/AU50/fpga_25g/fpga.xdc b/fpga/mqnic/AU50/fpga_25g/fpga.xdc index 3d386e6d8..758a7360d 100644 --- a/fpga/mqnic/AU50/fpga_25g/fpga.xdc +++ b/fpga/mqnic/AU50/fpga_25g/fpga.xdc @@ -23,9 +23,9 @@ set_operating_conditions -design_power_budget 63 #create_clock -period 10 -name clk_100mhz_0 [get_ports clk_100mhz_0_p] # 100 MHz -#set_property -dict {LOC BB18 IOSTANDARD LVDS} [get_ports clk_100mhz_1_p] -#set_property -dict {LOC BC18 IOSTANDARD LVDS} [get_ports clk_100mhz_1_n] -#create_clock -period 10 -name clk_100mhz_1 [get_ports clk_100mhz_1_p] +set_property -dict {LOC BB18 IOSTANDARD LVDS} [get_ports clk_100mhz_1_p] +set_property -dict {LOC BC18 IOSTANDARD LVDS} [get_ports clk_100mhz_1_n] +create_clock -period 10 -name clk_100mhz_1 [get_ports clk_100mhz_1_p] # LEDs set_property -dict {LOC E18 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp_led_act] diff --git a/fpga/mqnic/AU50/fpga_25g/fpga/Makefile b/fpga/mqnic/AU50/fpga_25g/fpga/Makefile index f3f113c17..b19f66874 100644 --- a/fpga/mqnic/AU50/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/AU50/fpga_25g/fpga/Makefile @@ -138,11 +138,13 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl +XDC_FILES += hbm.xdc # IP IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl IP_TCL_FILES += ip/cms.tcl +IP_TCL_FILES += ip/hbm_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl b/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl index 5bffa3f7f..0dda5836b 100644 --- a/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/AU50/fpga_25g/fpga/config.tcl @@ -148,6 +148,13 @@ dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" dict set params RX_RAM_SIZE "131072" + +# RAM configuration +dict set params HBM_CH "32" +dict set params HBM_ENABLE "1" +dict set params HBM_GROUP_SIZE "32" +dict set params AXI_HBM_ADDR_WIDTH "33" +dict set params AXI_HBM_MAX_BURST_LEN "256" # Application block configuration dict set params APP_ID "32'h00000000" diff --git a/fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile index f3f113c17..b19f66874 100644 --- a/fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile @@ -138,11 +138,13 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl XDC_FILES += ../../../common/syn/vivado/rb_drp.tcl XDC_FILES += ../../../common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl +XDC_FILES += hbm.xdc # IP IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl IP_TCL_FILES += ip/cms.tcl +IP_TCL_FILES += ip/hbm_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl index 6f5194c8b..a9c4e90e9 100644 --- a/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/AU50/fpga_25g/fpga_10g/config.tcl @@ -148,6 +148,13 @@ dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" dict set params RX_RAM_SIZE "32768" + +# RAM configuration +dict set params HBM_CH "32" +dict set params HBM_ENABLE "1" +dict set params HBM_GROUP_SIZE "32" +dict set params AXI_HBM_ADDR_WIDTH "33" +dict set params AXI_HBM_MAX_BURST_LEN "256" # Application block configuration dict set params APP_ID "32'h00000000" diff --git a/fpga/mqnic/AU50/fpga_25g/hbm.xdc b/fpga/mqnic/AU50/fpga_25g/hbm.xdc new file mode 100644 index 000000000..aa147b0a5 --- /dev/null +++ b/fpga/mqnic/AU50/fpga_25g/hbm.xdc @@ -0,0 +1,2 @@ +# force debug hub to use HBM APB clock to prevent CDC issues +connect_debug_port dbg_hub/clk [get_nets */APB_0_PCLK] diff --git a/fpga/mqnic/AU50/fpga_25g/ip/hbm_0.tcl b/fpga/mqnic/AU50/fpga_25g/ip/hbm_0.tcl new file mode 100644 index 000000000..a8cbc2874 --- /dev/null +++ b/fpga/mqnic/AU50/fpga_25g/ip/hbm_0.tcl @@ -0,0 +1,23 @@ + +create_ip -name hbm -vendor xilinx.com -library ip -module_name hbm_0 + +set_property -dict [list \ + CONFIG.USER_HBM_DENSITY {8GB} \ + CONFIG.USER_HBM_STACK {2} \ + CONFIG.USER_MC0_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC1_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC2_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC3_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC4_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC5_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC6_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC7_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC8_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC9_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC10_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC11_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC12_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC13_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC14_ENABLE_ECC_CORRECTION {true} \ + CONFIG.USER_MC15_ENABLE_ECC_CORRECTION {true} +] [get_ips hbm_0] diff --git a/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v b/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v index 8a924f6ed..8639a2368 100644 --- a/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/AU50/fpga_25g/rtl/fpga.v @@ -115,6 +115,13 @@ module fpga # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // RAM configuration + parameter HBM_CH = 32, + parameter HBM_ENABLE = 1, + parameter HBM_GROUP_SIZE = 32, + parameter AXI_HBM_ADDR_WIDTH = 33, + parameter AXI_HBM_MAX_BURST_LEN = 256, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -180,6 +187,14 @@ module fpga # parameter STAT_ID_WIDTH = 12 ) ( + /* + * Clock and reset + */ + // input wire clk_100mhz_0_p, + // input wire clk_100mhz_0_n, + input wire clk_100mhz_1_p, + input wire clk_100mhz_1_n, + /* * GPIO */ @@ -238,6 +253,11 @@ parameter IF_PTP_PERIOD_FNS = 16'h6666; // Interface configuration parameter TX_TAG_WIDTH = 16; +// RAM configuration +parameter AXI_HBM_DATA_WIDTH = 256; +parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8); +parameter AXI_HBM_ID_WIDTH = 6; + // Ethernet interface configuration parameter XGMII_DATA_WIDTH = 64; parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8; @@ -357,9 +377,6 @@ sync_reset_125mhz_inst ( .out(rst_125mhz_int) ); -// GPIO -assign hbm_cattrip = 1'b0; - // Flash wire qspi_clk_int; wire [3:0] qspi_dq_int; @@ -569,6 +586,9 @@ wire [1:0] axil_cms_rresp_int; wire axil_cms_rvalid_int; wire axil_cms_rready_int; +wire [7:0] hbm_temp_1; +wire [7:0] hbm_temp_2; + axil_cdc #( .DATA_WIDTH(32), .ADDR_WIDTH(18) @@ -622,8 +642,8 @@ cms_wrapper cms_inst ( .aclk_ctrl_0(clk_50mhz_int), .aresetn_ctrl_0(~rst_50mhz_int), - .hbm_temp_1_0(7'd0), - .hbm_temp_2_0(7'd0), + .hbm_temp_1_0(hbm_temp_1), + .hbm_temp_2_0(hbm_temp_2), .interrupt_hbm_cattrip_0(hbm_cattrip), .interrupt_host_0(), .s_axi_ctrl_0_araddr(axil_cms_araddr_int), @@ -1152,6 +1172,1356 @@ assign ptp_clk = qsfp_mgt_refclk_0_bufg; assign ptp_rst = qsfp_rst; assign ptp_sample_clk = clk_125mhz_int; +// HBM +wire [HBM_CH-1:0] hbm_clk; +wire [HBM_CH-1:0] hbm_rst; + +wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_awid; +wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_awaddr; +wire [HBM_CH*8-1:0] m_axi_hbm_awlen; +wire [HBM_CH*3-1:0] m_axi_hbm_awsize; +wire [HBM_CH*2-1:0] m_axi_hbm_awburst; +wire [HBM_CH-1:0] m_axi_hbm_awlock; +wire [HBM_CH*4-1:0] m_axi_hbm_awcache; +wire [HBM_CH*3-1:0] m_axi_hbm_awprot; +wire [HBM_CH*4-1:0] m_axi_hbm_awqos; +wire [HBM_CH-1:0] m_axi_hbm_awvalid; +wire [HBM_CH-1:0] m_axi_hbm_awready; +wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_wdata; +wire [HBM_CH*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_wstrb; +wire [HBM_CH-1:0] m_axi_hbm_wlast; +wire [HBM_CH-1:0] m_axi_hbm_wvalid; +wire [HBM_CH-1:0] m_axi_hbm_wready; +wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_bid; +wire [HBM_CH*2-1:0] m_axi_hbm_bresp; +wire [HBM_CH-1:0] m_axi_hbm_bvalid; +wire [HBM_CH-1:0] m_axi_hbm_bready; +wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_arid; +wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_araddr; +wire [HBM_CH*8-1:0] m_axi_hbm_arlen; +wire [HBM_CH*3-1:0] m_axi_hbm_arsize; +wire [HBM_CH*2-1:0] m_axi_hbm_arburst; +wire [HBM_CH-1:0] m_axi_hbm_arlock; +wire [HBM_CH*4-1:0] m_axi_hbm_arcache; +wire [HBM_CH*3-1:0] m_axi_hbm_arprot; +wire [HBM_CH*4-1:0] m_axi_hbm_arqos; +wire [HBM_CH-1:0] m_axi_hbm_arvalid; +wire [HBM_CH-1:0] m_axi_hbm_arready; +wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_rid; +wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_rdata; +wire [HBM_CH*2-1:0] m_axi_hbm_rresp; +wire [HBM_CH-1:0] m_axi_hbm_rlast; +wire [HBM_CH-1:0] m_axi_hbm_rvalid; +wire [HBM_CH-1:0] m_axi_hbm_rready; + +wire [HBM_CH-1:0] hbm_status; + +wire clk_100mhz_1_ibufg; + +IBUFGDS #( + .DIFF_TERM("FALSE"), + .IBUF_LOW_PWR("FALSE") +) +clk_100mhz_1_ibufg_inst ( + .O (clk_100mhz_1_ibufg), + .I (clk_100mhz_1_p), + .IB (clk_100mhz_1_n) +); + +generate + +if (HBM_ENABLE) begin + +wire hbm_ref_clk; + +wire hbm_mmcm_rst; +wire hbm_mmcm_locked; +wire hbm_mmcm_clkfb; + +wire hbm_axi_clk_mmcm; +wire hbm_axi_clk; +wire hbm_axi_rst_int; +wire hbm_axi_rst; + +BUFG +hbm_ref_clk_bufg_inst ( + .I(clk_100mhz_1_ibufg), + .O(hbm_ref_clk) +); + +// HBM MMCM instance +// 100 MHz in, 450 MHz out +// PFD range: 10 MHz to 500 MHz +// VCO range: 800 MHz to 1600 MHz +// M = 9, D = 1 sets Fvco = 900 MHz +// Divide by 2 to get output frequency of 450 MHz +MMCME4_BASE #( + .BANDWIDTH("OPTIMIZED"), + .CLKOUT0_DIVIDE_F(2), + .CLKOUT0_DUTY_CYCLE(0.5), + .CLKOUT0_PHASE(0), + .CLKOUT1_DIVIDE(1), + .CLKOUT1_DUTY_CYCLE(0.5), + .CLKOUT1_PHASE(0), + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.5), + .CLKOUT2_PHASE(0), + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.5), + .CLKOUT3_PHASE(0), + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.5), + .CLKOUT4_PHASE(0), + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.5), + .CLKOUT5_PHASE(0), + .CLKOUT6_DIVIDE(1), + .CLKOUT6_DUTY_CYCLE(0.5), + .CLKOUT6_PHASE(0), + .CLKFBOUT_MULT_F(9), + .CLKFBOUT_PHASE(0), + .DIVCLK_DIVIDE(1), + .REF_JITTER1(0.010), + .CLKIN1_PERIOD(10.000), + .STARTUP_WAIT("FALSE"), + .CLKOUT4_CASCADE("FALSE") +) +hbm_mmcm_inst ( + .CLKIN1(clk_100mhz_1_ibufg), + .CLKFBIN(hbm_mmcm_clkfb), + .RST(hbm_mmcm_rst), + .PWRDWN(1'b0), + .CLKOUT0(hbm_axi_clk_mmcm), + .CLKOUT0B(), + .CLKOUT1(), + .CLKOUT1B(), + .CLKOUT2(), + .CLKOUT2B(), + .CLKOUT3(), + .CLKOUT3B(), + .CLKOUT4(), + .CLKOUT5(), + .CLKOUT6(), + .CLKFBOUT(hbm_mmcm_clkfb), + .CLKFBOUTB(), + .LOCKED(hbm_mmcm_locked) +); + +BUFG +hbm_axi_clk_bufg_inst ( + .I(hbm_axi_clk_mmcm), + .O(hbm_axi_clk) +); + +sync_reset #( + .N(4) +) +sync_reset_hbm_axi_inst ( + .clk(hbm_axi_clk), + .rst(~hbm_mmcm_locked), + .out(hbm_axi_rst_int) +); + +// extra register for hbm_axi_rst signal +(* shreg_extract = "no" *) +reg hbm_axi_rst_reg_1 = 1'b1; +(* shreg_extract = "no" *) +reg hbm_axi_rst_reg_2 = 1'b1; + +assign hbm_axi_rst = hbm_axi_rst_reg_2; + +always @(posedge hbm_axi_clk) begin + hbm_axi_rst_reg_1 <= hbm_axi_rst_int; + hbm_axi_rst_reg_2 <= hbm_axi_rst_reg_1; +end + +wire hbm_cattrip_1; +wire hbm_cattrip_2; + +assign hbm_cattrip = hbm_cattrip_1 | hbm_cattrip_2; + +assign hbm_clk = {HBM_CH{hbm_axi_clk}}; +assign hbm_rst = {HBM_CH{hbm_axi_rst}}; + +hbm_0 hbm_inst ( + .HBM_REF_CLK_0(hbm_ref_clk), + .HBM_REF_CLK_1(hbm_ref_clk), + + .APB_0_PWDATA(32'd0), + .APB_0_PADDR(22'd0), + .APB_0_PCLK(hbm_ref_clk), + .APB_0_PENABLE(1'b0), + .APB_0_PRESET_N(1'b1), + .APB_0_PSEL(1'b0), + .APB_0_PWRITE(1'b0), + .APB_0_PRDATA(), + .APB_0_PREADY(), + .APB_0_PSLVERR(), + .apb_complete_0(), + + .APB_1_PWDATA(32'd0), + .APB_1_PADDR(22'd0), + .APB_1_PCLK(hbm_ref_clk), + .APB_1_PENABLE(1'b0), + .APB_1_PRESET_N(1'b1), + .APB_1_PSEL(1'b0), + .APB_1_PWRITE(1'b0), + .APB_1_PRDATA(), + .APB_1_PREADY(), + .APB_1_PSLVERR(), + .apb_complete_1(), + + .AXI_00_ACLK(hbm_clk[0 +: 1]), + .AXI_00_ARESET_N(!hbm_rst[0 +: 1]), + + .AXI_00_ARADDR(m_axi_hbm_araddr[0*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_00_ARBURST(m_axi_hbm_arburst[0*2 +: 2]), + .AXI_00_ARID(m_axi_hbm_arid[0*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_00_ARLEN(m_axi_hbm_arlen[0*8 +: 8]), + .AXI_00_ARSIZE(m_axi_hbm_arsize[0*3 +: 3]), + .AXI_00_ARVALID(m_axi_hbm_arvalid[0 +: 1]), + .AXI_00_ARREADY(m_axi_hbm_arready[0 +: 1]), + .AXI_00_RDATA_PARITY(), + .AXI_00_RDATA(m_axi_hbm_rdata[0*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_00_RID(m_axi_hbm_rid[0 +: 1]), + .AXI_00_RLAST(m_axi_hbm_rlast[0 +: 1]), + .AXI_00_RRESP(m_axi_hbm_rresp[0*2 +: 2]), + .AXI_00_RVALID(m_axi_hbm_rvalid[0 +: 1]), + .AXI_00_RREADY(m_axi_hbm_rready[0 +: 1]), + .AXI_00_AWADDR(m_axi_hbm_awaddr[0*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_00_AWBURST(m_axi_hbm_awburst[0*2 +: 2]), + .AXI_00_AWID(m_axi_hbm_awid[0*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_00_AWLEN(m_axi_hbm_awlen[0*8 +: 8]), + .AXI_00_AWSIZE(m_axi_hbm_awsize[0*3 +: 3]), + .AXI_00_AWVALID(m_axi_hbm_awvalid[0 +: 1]), + .AXI_00_AWREADY(m_axi_hbm_awready[0 +: 1]), + .AXI_00_WDATA(m_axi_hbm_wdata[0*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_00_WLAST(m_axi_hbm_wlast[0 +: 1]), + .AXI_00_WSTRB(m_axi_hbm_wstrb[0*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_00_WDATA_PARITY(32'd0), + .AXI_00_WVALID(m_axi_hbm_wvalid[0 +: 1]), + .AXI_00_WREADY(m_axi_hbm_wready[0 +: 1]), + .AXI_00_BID(m_axi_hbm_bid[0*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_00_BRESP(m_axi_hbm_bresp[0*2 +: 2]), + .AXI_00_BVALID(m_axi_hbm_bvalid[0 +: 1]), + .AXI_00_BREADY(m_axi_hbm_bready[0 +: 1]), + + .AXI_01_ACLK(hbm_clk[1 +: 1]), + .AXI_01_ARESET_N(!hbm_rst[1 +: 1]), + + .AXI_01_ARADDR(m_axi_hbm_araddr[1*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_01_ARBURST(m_axi_hbm_arburst[1*2 +: 2]), + .AXI_01_ARID(m_axi_hbm_arid[1*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_01_ARLEN(m_axi_hbm_arlen[1*8 +: 8]), + .AXI_01_ARSIZE(m_axi_hbm_arsize[1*3 +: 3]), + .AXI_01_ARVALID(m_axi_hbm_arvalid[1 +: 1]), + .AXI_01_ARREADY(m_axi_hbm_arready[1 +: 1]), + .AXI_01_RDATA_PARITY(), + .AXI_01_RDATA(m_axi_hbm_rdata[1*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_01_RID(m_axi_hbm_rid[1 +: 1]), + .AXI_01_RLAST(m_axi_hbm_rlast[1 +: 1]), + .AXI_01_RRESP(m_axi_hbm_rresp[1*2 +: 2]), + .AXI_01_RVALID(m_axi_hbm_rvalid[1 +: 1]), + .AXI_01_RREADY(m_axi_hbm_rready[1 +: 1]), + .AXI_01_AWADDR(m_axi_hbm_awaddr[1*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_01_AWBURST(m_axi_hbm_awburst[1*2 +: 2]), + .AXI_01_AWID(m_axi_hbm_awid[1*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_01_AWLEN(m_axi_hbm_awlen[1*8 +: 8]), + .AXI_01_AWSIZE(m_axi_hbm_awsize[1*3 +: 3]), + .AXI_01_AWVALID(m_axi_hbm_awvalid[1 +: 1]), + .AXI_01_AWREADY(m_axi_hbm_awready[1 +: 1]), + .AXI_01_WDATA(m_axi_hbm_wdata[1*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_01_WLAST(m_axi_hbm_wlast[1 +: 1]), + .AXI_01_WSTRB(m_axi_hbm_wstrb[1*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_01_WDATA_PARITY(32'd0), + .AXI_01_WVALID(m_axi_hbm_wvalid[1 +: 1]), + .AXI_01_WREADY(m_axi_hbm_wready[1 +: 1]), + .AXI_01_BID(m_axi_hbm_bid[1*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_01_BRESP(m_axi_hbm_bresp[1*2 +: 2]), + .AXI_01_BVALID(m_axi_hbm_bvalid[1 +: 1]), + .AXI_01_BREADY(m_axi_hbm_bready[1 +: 1]), + + .AXI_02_ACLK(hbm_clk[2 +: 1]), + .AXI_02_ARESET_N(!hbm_rst[2 +: 1]), + + .AXI_02_ARADDR(m_axi_hbm_araddr[2*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_02_ARBURST(m_axi_hbm_arburst[2*2 +: 2]), + .AXI_02_ARID(m_axi_hbm_arid[2*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_02_ARLEN(m_axi_hbm_arlen[2*8 +: 8]), + .AXI_02_ARSIZE(m_axi_hbm_arsize[2*3 +: 3]), + .AXI_02_ARVALID(m_axi_hbm_arvalid[2 +: 1]), + .AXI_02_ARREADY(m_axi_hbm_arready[2 +: 1]), + .AXI_02_RDATA_PARITY(), + .AXI_02_RDATA(m_axi_hbm_rdata[2*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_02_RID(m_axi_hbm_rid[2 +: 1]), + .AXI_02_RLAST(m_axi_hbm_rlast[2 +: 1]), + .AXI_02_RRESP(m_axi_hbm_rresp[2*2 +: 2]), + .AXI_02_RVALID(m_axi_hbm_rvalid[2 +: 1]), + .AXI_02_RREADY(m_axi_hbm_rready[2 +: 1]), + .AXI_02_AWADDR(m_axi_hbm_awaddr[2*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_02_AWBURST(m_axi_hbm_awburst[2*2 +: 2]), + .AXI_02_AWID(m_axi_hbm_awid[2*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_02_AWLEN(m_axi_hbm_awlen[2*8 +: 8]), + .AXI_02_AWSIZE(m_axi_hbm_awsize[2*3 +: 3]), + .AXI_02_AWVALID(m_axi_hbm_awvalid[2 +: 1]), + .AXI_02_AWREADY(m_axi_hbm_awready[2 +: 1]), + .AXI_02_WDATA(m_axi_hbm_wdata[2*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_02_WLAST(m_axi_hbm_wlast[2 +: 1]), + .AXI_02_WSTRB(m_axi_hbm_wstrb[2*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_02_WDATA_PARITY(32'd0), + .AXI_02_WVALID(m_axi_hbm_wvalid[2 +: 1]), + .AXI_02_WREADY(m_axi_hbm_wready[2 +: 1]), + .AXI_02_BID(m_axi_hbm_bid[2*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_02_BRESP(m_axi_hbm_bresp[2*2 +: 2]), + .AXI_02_BVALID(m_axi_hbm_bvalid[2 +: 1]), + .AXI_02_BREADY(m_axi_hbm_bready[2 +: 1]), + + .AXI_03_ACLK(hbm_clk[3 +: 1]), + .AXI_03_ARESET_N(!hbm_rst[3 +: 1]), + + .AXI_03_ARADDR(m_axi_hbm_araddr[3*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_03_ARBURST(m_axi_hbm_arburst[3*2 +: 2]), + .AXI_03_ARID(m_axi_hbm_arid[3*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_03_ARLEN(m_axi_hbm_arlen[3*8 +: 8]), + .AXI_03_ARSIZE(m_axi_hbm_arsize[3*3 +: 3]), + .AXI_03_ARVALID(m_axi_hbm_arvalid[3 +: 1]), + .AXI_03_ARREADY(m_axi_hbm_arready[3 +: 1]), + .AXI_03_RDATA_PARITY(), + .AXI_03_RDATA(m_axi_hbm_rdata[3*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_03_RID(m_axi_hbm_rid[3 +: 1]), + .AXI_03_RLAST(m_axi_hbm_rlast[3 +: 1]), + .AXI_03_RRESP(m_axi_hbm_rresp[3*2 +: 2]), + .AXI_03_RVALID(m_axi_hbm_rvalid[3 +: 1]), + .AXI_03_RREADY(m_axi_hbm_rready[3 +: 1]), + .AXI_03_AWADDR(m_axi_hbm_awaddr[3*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_03_AWBURST(m_axi_hbm_awburst[3*2 +: 2]), + .AXI_03_AWID(m_axi_hbm_awid[3*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_03_AWLEN(m_axi_hbm_awlen[3*8 +: 8]), + .AXI_03_AWSIZE(m_axi_hbm_awsize[3*3 +: 3]), + .AXI_03_AWVALID(m_axi_hbm_awvalid[3 +: 1]), + .AXI_03_AWREADY(m_axi_hbm_awready[3 +: 1]), + .AXI_03_WDATA(m_axi_hbm_wdata[3*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_03_WLAST(m_axi_hbm_wlast[3 +: 1]), + .AXI_03_WSTRB(m_axi_hbm_wstrb[3*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_03_WDATA_PARITY(32'd0), + .AXI_03_WVALID(m_axi_hbm_wvalid[3 +: 1]), + .AXI_03_WREADY(m_axi_hbm_wready[3 +: 1]), + .AXI_03_BID(m_axi_hbm_bid[3*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_03_BRESP(m_axi_hbm_bresp[3*2 +: 2]), + .AXI_03_BVALID(m_axi_hbm_bvalid[3 +: 1]), + .AXI_03_BREADY(m_axi_hbm_bready[3 +: 1]), + + .AXI_04_ACLK(hbm_clk[4 +: 1]), + .AXI_04_ARESET_N(!hbm_rst[4 +: 1]), + + .AXI_04_ARADDR(m_axi_hbm_araddr[4*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_04_ARBURST(m_axi_hbm_arburst[4*2 +: 2]), + .AXI_04_ARID(m_axi_hbm_arid[4*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_04_ARLEN(m_axi_hbm_arlen[4*8 +: 8]), + .AXI_04_ARSIZE(m_axi_hbm_arsize[4*3 +: 3]), + .AXI_04_ARVALID(m_axi_hbm_arvalid[4 +: 1]), + .AXI_04_ARREADY(m_axi_hbm_arready[4 +: 1]), + .AXI_04_RDATA_PARITY(), + .AXI_04_RDATA(m_axi_hbm_rdata[4*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_04_RID(m_axi_hbm_rid[4 +: 1]), + .AXI_04_RLAST(m_axi_hbm_rlast[4 +: 1]), + .AXI_04_RRESP(m_axi_hbm_rresp[4*2 +: 2]), + .AXI_04_RVALID(m_axi_hbm_rvalid[4 +: 1]), + .AXI_04_RREADY(m_axi_hbm_rready[4 +: 1]), + .AXI_04_AWADDR(m_axi_hbm_awaddr[4*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_04_AWBURST(m_axi_hbm_awburst[4*2 +: 2]), + .AXI_04_AWID(m_axi_hbm_awid[4*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_04_AWLEN(m_axi_hbm_awlen[4*8 +: 8]), + .AXI_04_AWSIZE(m_axi_hbm_awsize[4*3 +: 3]), + .AXI_04_AWVALID(m_axi_hbm_awvalid[4 +: 1]), + .AXI_04_AWREADY(m_axi_hbm_awready[4 +: 1]), + .AXI_04_WDATA(m_axi_hbm_wdata[4*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_04_WLAST(m_axi_hbm_wlast[4 +: 1]), + .AXI_04_WSTRB(m_axi_hbm_wstrb[4*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_04_WDATA_PARITY(32'd0), + .AXI_04_WVALID(m_axi_hbm_wvalid[4 +: 1]), + .AXI_04_WREADY(m_axi_hbm_wready[4 +: 1]), + .AXI_04_BID(m_axi_hbm_bid[4*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_04_BRESP(m_axi_hbm_bresp[4*2 +: 2]), + .AXI_04_BVALID(m_axi_hbm_bvalid[4 +: 1]), + .AXI_04_BREADY(m_axi_hbm_bready[4 +: 1]), + + .AXI_05_ACLK(hbm_clk[5 +: 1]), + .AXI_05_ARESET_N(!hbm_rst[5 +: 1]), + + .AXI_05_ARADDR(m_axi_hbm_araddr[5*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_05_ARBURST(m_axi_hbm_arburst[5*2 +: 2]), + .AXI_05_ARID(m_axi_hbm_arid[5*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_05_ARLEN(m_axi_hbm_arlen[5*8 +: 8]), + .AXI_05_ARSIZE(m_axi_hbm_arsize[5*3 +: 3]), + .AXI_05_ARVALID(m_axi_hbm_arvalid[5 +: 1]), + .AXI_05_ARREADY(m_axi_hbm_arready[5 +: 1]), + .AXI_05_RDATA_PARITY(), + .AXI_05_RDATA(m_axi_hbm_rdata[5*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_05_RID(m_axi_hbm_rid[5 +: 1]), + .AXI_05_RLAST(m_axi_hbm_rlast[5 +: 1]), + .AXI_05_RRESP(m_axi_hbm_rresp[5*2 +: 2]), + .AXI_05_RVALID(m_axi_hbm_rvalid[5 +: 1]), + .AXI_05_RREADY(m_axi_hbm_rready[5 +: 1]), + .AXI_05_AWADDR(m_axi_hbm_awaddr[5*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_05_AWBURST(m_axi_hbm_awburst[5*2 +: 2]), + .AXI_05_AWID(m_axi_hbm_awid[5*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_05_AWLEN(m_axi_hbm_awlen[5*8 +: 8]), + .AXI_05_AWSIZE(m_axi_hbm_awsize[5*3 +: 3]), + .AXI_05_AWVALID(m_axi_hbm_awvalid[5 +: 1]), + .AXI_05_AWREADY(m_axi_hbm_awready[5 +: 1]), + .AXI_05_WDATA(m_axi_hbm_wdata[5*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_05_WLAST(m_axi_hbm_wlast[5 +: 1]), + .AXI_05_WSTRB(m_axi_hbm_wstrb[5*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_05_WDATA_PARITY(32'd0), + .AXI_05_WVALID(m_axi_hbm_wvalid[5 +: 1]), + .AXI_05_WREADY(m_axi_hbm_wready[5 +: 1]), + .AXI_05_BID(m_axi_hbm_bid[5*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_05_BRESP(m_axi_hbm_bresp[5*2 +: 2]), + .AXI_05_BVALID(m_axi_hbm_bvalid[5 +: 1]), + .AXI_05_BREADY(m_axi_hbm_bready[5 +: 1]), + + .AXI_06_ACLK(hbm_clk[6 +: 1]), + .AXI_06_ARESET_N(!hbm_rst[6 +: 1]), + + .AXI_06_ARADDR(m_axi_hbm_araddr[6*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_06_ARBURST(m_axi_hbm_arburst[6*2 +: 2]), + .AXI_06_ARID(m_axi_hbm_arid[6*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_06_ARLEN(m_axi_hbm_arlen[6*8 +: 8]), + .AXI_06_ARSIZE(m_axi_hbm_arsize[6*3 +: 3]), + .AXI_06_ARVALID(m_axi_hbm_arvalid[6 +: 1]), + .AXI_06_ARREADY(m_axi_hbm_arready[6 +: 1]), + .AXI_06_RDATA_PARITY(), + .AXI_06_RDATA(m_axi_hbm_rdata[6*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_06_RID(m_axi_hbm_rid[6 +: 1]), + .AXI_06_RLAST(m_axi_hbm_rlast[6 +: 1]), + .AXI_06_RRESP(m_axi_hbm_rresp[6*2 +: 2]), + .AXI_06_RVALID(m_axi_hbm_rvalid[6 +: 1]), + .AXI_06_RREADY(m_axi_hbm_rready[6 +: 1]), + .AXI_06_AWADDR(m_axi_hbm_awaddr[6*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_06_AWBURST(m_axi_hbm_awburst[6*2 +: 2]), + .AXI_06_AWID(m_axi_hbm_awid[6*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_06_AWLEN(m_axi_hbm_awlen[6*8 +: 8]), + .AXI_06_AWSIZE(m_axi_hbm_awsize[6*3 +: 3]), + .AXI_06_AWVALID(m_axi_hbm_awvalid[6 +: 1]), + .AXI_06_AWREADY(m_axi_hbm_awready[6 +: 1]), + .AXI_06_WDATA(m_axi_hbm_wdata[6*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_06_WLAST(m_axi_hbm_wlast[6 +: 1]), + .AXI_06_WSTRB(m_axi_hbm_wstrb[6*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_06_WDATA_PARITY(32'd0), + .AXI_06_WVALID(m_axi_hbm_wvalid[6 +: 1]), + .AXI_06_WREADY(m_axi_hbm_wready[6 +: 1]), + .AXI_06_BID(m_axi_hbm_bid[6*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_06_BRESP(m_axi_hbm_bresp[6*2 +: 2]), + .AXI_06_BVALID(m_axi_hbm_bvalid[6 +: 1]), + .AXI_06_BREADY(m_axi_hbm_bready[6 +: 1]), + + .AXI_07_ACLK(hbm_clk[7 +: 1]), + .AXI_07_ARESET_N(!hbm_rst[7 +: 1]), + + .AXI_07_ARADDR(m_axi_hbm_araddr[7*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_07_ARBURST(m_axi_hbm_arburst[7*2 +: 2]), + .AXI_07_ARID(m_axi_hbm_arid[7*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_07_ARLEN(m_axi_hbm_arlen[7*8 +: 8]), + .AXI_07_ARSIZE(m_axi_hbm_arsize[7*3 +: 3]), + .AXI_07_ARVALID(m_axi_hbm_arvalid[7 +: 1]), + .AXI_07_ARREADY(m_axi_hbm_arready[7 +: 1]), + .AXI_07_RDATA_PARITY(), + .AXI_07_RDATA(m_axi_hbm_rdata[7*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_07_RID(m_axi_hbm_rid[7 +: 1]), + .AXI_07_RLAST(m_axi_hbm_rlast[7 +: 1]), + .AXI_07_RRESP(m_axi_hbm_rresp[7*2 +: 2]), + .AXI_07_RVALID(m_axi_hbm_rvalid[7 +: 1]), + .AXI_07_RREADY(m_axi_hbm_rready[7 +: 1]), + .AXI_07_AWADDR(m_axi_hbm_awaddr[7*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_07_AWBURST(m_axi_hbm_awburst[7*2 +: 2]), + .AXI_07_AWID(m_axi_hbm_awid[7*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_07_AWLEN(m_axi_hbm_awlen[7*8 +: 8]), + .AXI_07_AWSIZE(m_axi_hbm_awsize[7*3 +: 3]), + .AXI_07_AWVALID(m_axi_hbm_awvalid[7 +: 1]), + .AXI_07_AWREADY(m_axi_hbm_awready[7 +: 1]), + .AXI_07_WDATA(m_axi_hbm_wdata[7*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_07_WLAST(m_axi_hbm_wlast[7 +: 1]), + .AXI_07_WSTRB(m_axi_hbm_wstrb[7*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_07_WDATA_PARITY(32'd0), + .AXI_07_WVALID(m_axi_hbm_wvalid[7 +: 1]), + .AXI_07_WREADY(m_axi_hbm_wready[7 +: 1]), + .AXI_07_BID(m_axi_hbm_bid[7*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_07_BRESP(m_axi_hbm_bresp[7*2 +: 2]), + .AXI_07_BVALID(m_axi_hbm_bvalid[7 +: 1]), + .AXI_07_BREADY(m_axi_hbm_bready[7 +: 1]), + + .AXI_08_ACLK(hbm_clk[8 +: 1]), + .AXI_08_ARESET_N(!hbm_rst[8 +: 1]), + + .AXI_08_ARADDR(m_axi_hbm_araddr[8*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_08_ARBURST(m_axi_hbm_arburst[8*2 +: 2]), + .AXI_08_ARID(m_axi_hbm_arid[8*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_08_ARLEN(m_axi_hbm_arlen[8*8 +: 8]), + .AXI_08_ARSIZE(m_axi_hbm_arsize[8*3 +: 3]), + .AXI_08_ARVALID(m_axi_hbm_arvalid[8 +: 1]), + .AXI_08_ARREADY(m_axi_hbm_arready[8 +: 1]), + .AXI_08_RDATA_PARITY(), + .AXI_08_RDATA(m_axi_hbm_rdata[8*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_08_RID(m_axi_hbm_rid[8 +: 1]), + .AXI_08_RLAST(m_axi_hbm_rlast[8 +: 1]), + .AXI_08_RRESP(m_axi_hbm_rresp[8*2 +: 2]), + .AXI_08_RVALID(m_axi_hbm_rvalid[8 +: 1]), + .AXI_08_RREADY(m_axi_hbm_rready[8 +: 1]), + .AXI_08_AWADDR(m_axi_hbm_awaddr[8*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_08_AWBURST(m_axi_hbm_awburst[8*2 +: 2]), + .AXI_08_AWID(m_axi_hbm_awid[8*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_08_AWLEN(m_axi_hbm_awlen[8*8 +: 8]), + .AXI_08_AWSIZE(m_axi_hbm_awsize[8*3 +: 3]), + .AXI_08_AWVALID(m_axi_hbm_awvalid[8 +: 1]), + .AXI_08_AWREADY(m_axi_hbm_awready[8 +: 1]), + .AXI_08_WDATA(m_axi_hbm_wdata[8*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_08_WLAST(m_axi_hbm_wlast[8 +: 1]), + .AXI_08_WSTRB(m_axi_hbm_wstrb[8*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_08_WDATA_PARITY(32'd0), + .AXI_08_WVALID(m_axi_hbm_wvalid[8 +: 1]), + .AXI_08_WREADY(m_axi_hbm_wready[8 +: 1]), + .AXI_08_BID(m_axi_hbm_bid[8*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_08_BRESP(m_axi_hbm_bresp[8*2 +: 2]), + .AXI_08_BVALID(m_axi_hbm_bvalid[8 +: 1]), + .AXI_08_BREADY(m_axi_hbm_bready[8 +: 1]), + + .AXI_09_ACLK(hbm_clk[9 +: 1]), + .AXI_09_ARESET_N(!hbm_rst[9 +: 1]), + + .AXI_09_ARADDR(m_axi_hbm_araddr[9*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_09_ARBURST(m_axi_hbm_arburst[9*2 +: 2]), + .AXI_09_ARID(m_axi_hbm_arid[9*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_09_ARLEN(m_axi_hbm_arlen[9*8 +: 8]), + .AXI_09_ARSIZE(m_axi_hbm_arsize[9*3 +: 3]), + .AXI_09_ARVALID(m_axi_hbm_arvalid[9 +: 1]), + .AXI_09_ARREADY(m_axi_hbm_arready[9 +: 1]), + .AXI_09_RDATA_PARITY(), + .AXI_09_RDATA(m_axi_hbm_rdata[9*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_09_RID(m_axi_hbm_rid[9 +: 1]), + .AXI_09_RLAST(m_axi_hbm_rlast[9 +: 1]), + .AXI_09_RRESP(m_axi_hbm_rresp[9*2 +: 2]), + .AXI_09_RVALID(m_axi_hbm_rvalid[9 +: 1]), + .AXI_09_RREADY(m_axi_hbm_rready[9 +: 1]), + .AXI_09_AWADDR(m_axi_hbm_awaddr[9*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_09_AWBURST(m_axi_hbm_awburst[9*2 +: 2]), + .AXI_09_AWID(m_axi_hbm_awid[9*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_09_AWLEN(m_axi_hbm_awlen[9*8 +: 8]), + .AXI_09_AWSIZE(m_axi_hbm_awsize[9*3 +: 3]), + .AXI_09_AWVALID(m_axi_hbm_awvalid[9 +: 1]), + .AXI_09_AWREADY(m_axi_hbm_awready[9 +: 1]), + .AXI_09_WDATA(m_axi_hbm_wdata[9*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_09_WLAST(m_axi_hbm_wlast[9 +: 1]), + .AXI_09_WSTRB(m_axi_hbm_wstrb[9*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_09_WDATA_PARITY(32'd0), + .AXI_09_WVALID(m_axi_hbm_wvalid[9 +: 1]), + .AXI_09_WREADY(m_axi_hbm_wready[9 +: 1]), + .AXI_09_BID(m_axi_hbm_bid[9*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_09_BRESP(m_axi_hbm_bresp[9*2 +: 2]), + .AXI_09_BVALID(m_axi_hbm_bvalid[9 +: 1]), + .AXI_09_BREADY(m_axi_hbm_bready[9 +: 1]), + + .AXI_10_ACLK(hbm_clk[10 +: 1]), + .AXI_10_ARESET_N(!hbm_rst[10 +: 1]), + + .AXI_10_ARADDR(m_axi_hbm_araddr[10*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_10_ARBURST(m_axi_hbm_arburst[10*2 +: 2]), + .AXI_10_ARID(m_axi_hbm_arid[10*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_10_ARLEN(m_axi_hbm_arlen[10*8 +: 8]), + .AXI_10_ARSIZE(m_axi_hbm_arsize[10*3 +: 3]), + .AXI_10_ARVALID(m_axi_hbm_arvalid[10 +: 1]), + .AXI_10_ARREADY(m_axi_hbm_arready[10 +: 1]), + .AXI_10_RDATA_PARITY(), + .AXI_10_RDATA(m_axi_hbm_rdata[10*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_10_RID(m_axi_hbm_rid[10 +: 1]), + .AXI_10_RLAST(m_axi_hbm_rlast[10 +: 1]), + .AXI_10_RRESP(m_axi_hbm_rresp[10*2 +: 2]), + .AXI_10_RVALID(m_axi_hbm_rvalid[10 +: 1]), + .AXI_10_RREADY(m_axi_hbm_rready[10 +: 1]), + .AXI_10_AWADDR(m_axi_hbm_awaddr[10*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_10_AWBURST(m_axi_hbm_awburst[10*2 +: 2]), + .AXI_10_AWID(m_axi_hbm_awid[10*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_10_AWLEN(m_axi_hbm_awlen[10*8 +: 8]), + .AXI_10_AWSIZE(m_axi_hbm_awsize[10*3 +: 3]), + .AXI_10_AWVALID(m_axi_hbm_awvalid[10 +: 1]), + .AXI_10_AWREADY(m_axi_hbm_awready[10 +: 1]), + .AXI_10_WDATA(m_axi_hbm_wdata[10*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_10_WLAST(m_axi_hbm_wlast[10 +: 1]), + .AXI_10_WSTRB(m_axi_hbm_wstrb[10*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_10_WDATA_PARITY(32'd0), + .AXI_10_WVALID(m_axi_hbm_wvalid[10 +: 1]), + .AXI_10_WREADY(m_axi_hbm_wready[10 +: 1]), + .AXI_10_BID(m_axi_hbm_bid[10*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_10_BRESP(m_axi_hbm_bresp[10*2 +: 2]), + .AXI_10_BVALID(m_axi_hbm_bvalid[10 +: 1]), + .AXI_10_BREADY(m_axi_hbm_bready[10 +: 1]), + + .AXI_11_ACLK(hbm_clk[11 +: 1]), + .AXI_11_ARESET_N(!hbm_rst[11 +: 1]), + + .AXI_11_ARADDR(m_axi_hbm_araddr[11*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_11_ARBURST(m_axi_hbm_arburst[11*2 +: 2]), + .AXI_11_ARID(m_axi_hbm_arid[11*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_11_ARLEN(m_axi_hbm_arlen[11*8 +: 8]), + .AXI_11_ARSIZE(m_axi_hbm_arsize[11*3 +: 3]), + .AXI_11_ARVALID(m_axi_hbm_arvalid[11 +: 1]), + .AXI_11_ARREADY(m_axi_hbm_arready[11 +: 1]), + .AXI_11_RDATA_PARITY(), + .AXI_11_RDATA(m_axi_hbm_rdata[11*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_11_RID(m_axi_hbm_rid[11 +: 1]), + .AXI_11_RLAST(m_axi_hbm_rlast[11 +: 1]), + .AXI_11_RRESP(m_axi_hbm_rresp[11*2 +: 2]), + .AXI_11_RVALID(m_axi_hbm_rvalid[11 +: 1]), + .AXI_11_RREADY(m_axi_hbm_rready[11 +: 1]), + .AXI_11_AWADDR(m_axi_hbm_awaddr[11*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_11_AWBURST(m_axi_hbm_awburst[11*2 +: 2]), + .AXI_11_AWID(m_axi_hbm_awid[11*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_11_AWLEN(m_axi_hbm_awlen[11*8 +: 8]), + .AXI_11_AWSIZE(m_axi_hbm_awsize[11*3 +: 3]), + .AXI_11_AWVALID(m_axi_hbm_awvalid[11 +: 1]), + .AXI_11_AWREADY(m_axi_hbm_awready[11 +: 1]), + .AXI_11_WDATA(m_axi_hbm_wdata[11*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_11_WLAST(m_axi_hbm_wlast[11 +: 1]), + .AXI_11_WSTRB(m_axi_hbm_wstrb[11*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_11_WDATA_PARITY(32'd0), + .AXI_11_WVALID(m_axi_hbm_wvalid[11 +: 1]), + .AXI_11_WREADY(m_axi_hbm_wready[11 +: 1]), + .AXI_11_BID(m_axi_hbm_bid[11*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_11_BRESP(m_axi_hbm_bresp[11*2 +: 2]), + .AXI_11_BVALID(m_axi_hbm_bvalid[11 +: 1]), + .AXI_11_BREADY(m_axi_hbm_bready[11 +: 1]), + + .AXI_12_ACLK(hbm_clk[12 +: 1]), + .AXI_12_ARESET_N(!hbm_rst[12 +: 1]), + + .AXI_12_ARADDR(m_axi_hbm_araddr[12*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_12_ARBURST(m_axi_hbm_arburst[12*2 +: 2]), + .AXI_12_ARID(m_axi_hbm_arid[12*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_12_ARLEN(m_axi_hbm_arlen[12*8 +: 8]), + .AXI_12_ARSIZE(m_axi_hbm_arsize[12*3 +: 3]), + .AXI_12_ARVALID(m_axi_hbm_arvalid[12 +: 1]), + .AXI_12_ARREADY(m_axi_hbm_arready[12 +: 1]), + .AXI_12_RDATA_PARITY(), + .AXI_12_RDATA(m_axi_hbm_rdata[12*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_12_RID(m_axi_hbm_rid[12 +: 1]), + .AXI_12_RLAST(m_axi_hbm_rlast[12 +: 1]), + .AXI_12_RRESP(m_axi_hbm_rresp[12*2 +: 2]), + .AXI_12_RVALID(m_axi_hbm_rvalid[12 +: 1]), + .AXI_12_RREADY(m_axi_hbm_rready[12 +: 1]), + .AXI_12_AWADDR(m_axi_hbm_awaddr[12*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_12_AWBURST(m_axi_hbm_awburst[12*2 +: 2]), + .AXI_12_AWID(m_axi_hbm_awid[12*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_12_AWLEN(m_axi_hbm_awlen[12*8 +: 8]), + .AXI_12_AWSIZE(m_axi_hbm_awsize[12*3 +: 3]), + .AXI_12_AWVALID(m_axi_hbm_awvalid[12 +: 1]), + .AXI_12_AWREADY(m_axi_hbm_awready[12 +: 1]), + .AXI_12_WDATA(m_axi_hbm_wdata[12*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_12_WLAST(m_axi_hbm_wlast[12 +: 1]), + .AXI_12_WSTRB(m_axi_hbm_wstrb[12*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_12_WDATA_PARITY(32'd0), + .AXI_12_WVALID(m_axi_hbm_wvalid[12 +: 1]), + .AXI_12_WREADY(m_axi_hbm_wready[12 +: 1]), + .AXI_12_BID(m_axi_hbm_bid[12*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_12_BRESP(m_axi_hbm_bresp[12*2 +: 2]), + .AXI_12_BVALID(m_axi_hbm_bvalid[12 +: 1]), + .AXI_12_BREADY(m_axi_hbm_bready[12 +: 1]), + + .AXI_13_ACLK(hbm_clk[13 +: 1]), + .AXI_13_ARESET_N(!hbm_rst[13 +: 1]), + + .AXI_13_ARADDR(m_axi_hbm_araddr[13*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_13_ARBURST(m_axi_hbm_arburst[13*2 +: 2]), + .AXI_13_ARID(m_axi_hbm_arid[13*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_13_ARLEN(m_axi_hbm_arlen[13*8 +: 8]), + .AXI_13_ARSIZE(m_axi_hbm_arsize[13*3 +: 3]), + .AXI_13_ARVALID(m_axi_hbm_arvalid[13 +: 1]), + .AXI_13_ARREADY(m_axi_hbm_arready[13 +: 1]), + .AXI_13_RDATA_PARITY(), + .AXI_13_RDATA(m_axi_hbm_rdata[13*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_13_RID(m_axi_hbm_rid[13 +: 1]), + .AXI_13_RLAST(m_axi_hbm_rlast[13 +: 1]), + .AXI_13_RRESP(m_axi_hbm_rresp[13*2 +: 2]), + .AXI_13_RVALID(m_axi_hbm_rvalid[13 +: 1]), + .AXI_13_RREADY(m_axi_hbm_rready[13 +: 1]), + .AXI_13_AWADDR(m_axi_hbm_awaddr[13*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_13_AWBURST(m_axi_hbm_awburst[13*2 +: 2]), + .AXI_13_AWID(m_axi_hbm_awid[13*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_13_AWLEN(m_axi_hbm_awlen[13*8 +: 8]), + .AXI_13_AWSIZE(m_axi_hbm_awsize[13*3 +: 3]), + .AXI_13_AWVALID(m_axi_hbm_awvalid[13 +: 1]), + .AXI_13_AWREADY(m_axi_hbm_awready[13 +: 1]), + .AXI_13_WDATA(m_axi_hbm_wdata[13*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_13_WLAST(m_axi_hbm_wlast[13 +: 1]), + .AXI_13_WSTRB(m_axi_hbm_wstrb[13*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_13_WDATA_PARITY(32'd0), + .AXI_13_WVALID(m_axi_hbm_wvalid[13 +: 1]), + .AXI_13_WREADY(m_axi_hbm_wready[13 +: 1]), + .AXI_13_BID(m_axi_hbm_bid[13*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_13_BRESP(m_axi_hbm_bresp[13*2 +: 2]), + .AXI_13_BVALID(m_axi_hbm_bvalid[13 +: 1]), + .AXI_13_BREADY(m_axi_hbm_bready[13 +: 1]), + + .AXI_14_ACLK(hbm_clk[14 +: 1]), + .AXI_14_ARESET_N(!hbm_rst[14 +: 1]), + + .AXI_14_ARADDR(m_axi_hbm_araddr[14*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_14_ARBURST(m_axi_hbm_arburst[14*2 +: 2]), + .AXI_14_ARID(m_axi_hbm_arid[14*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_14_ARLEN(m_axi_hbm_arlen[14*8 +: 8]), + .AXI_14_ARSIZE(m_axi_hbm_arsize[14*3 +: 3]), + .AXI_14_ARVALID(m_axi_hbm_arvalid[14 +: 1]), + .AXI_14_ARREADY(m_axi_hbm_arready[14 +: 1]), + .AXI_14_RDATA_PARITY(), + .AXI_14_RDATA(m_axi_hbm_rdata[14*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_14_RID(m_axi_hbm_rid[14 +: 1]), + .AXI_14_RLAST(m_axi_hbm_rlast[14 +: 1]), + .AXI_14_RRESP(m_axi_hbm_rresp[14*2 +: 2]), + .AXI_14_RVALID(m_axi_hbm_rvalid[14 +: 1]), + .AXI_14_RREADY(m_axi_hbm_rready[14 +: 1]), + .AXI_14_AWADDR(m_axi_hbm_awaddr[14*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_14_AWBURST(m_axi_hbm_awburst[14*2 +: 2]), + .AXI_14_AWID(m_axi_hbm_awid[14*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_14_AWLEN(m_axi_hbm_awlen[14*8 +: 8]), + .AXI_14_AWSIZE(m_axi_hbm_awsize[14*3 +: 3]), + .AXI_14_AWVALID(m_axi_hbm_awvalid[14 +: 1]), + .AXI_14_AWREADY(m_axi_hbm_awready[14 +: 1]), + .AXI_14_WDATA(m_axi_hbm_wdata[14*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_14_WLAST(m_axi_hbm_wlast[14 +: 1]), + .AXI_14_WSTRB(m_axi_hbm_wstrb[14*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_14_WDATA_PARITY(32'd0), + .AXI_14_WVALID(m_axi_hbm_wvalid[14 +: 1]), + .AXI_14_WREADY(m_axi_hbm_wready[14 +: 1]), + .AXI_14_BID(m_axi_hbm_bid[14*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_14_BRESP(m_axi_hbm_bresp[14*2 +: 2]), + .AXI_14_BVALID(m_axi_hbm_bvalid[14 +: 1]), + .AXI_14_BREADY(m_axi_hbm_bready[14 +: 1]), + + .AXI_15_ACLK(hbm_clk[15 +: 1]), + .AXI_15_ARESET_N(!hbm_rst[15 +: 1]), + + .AXI_15_ARADDR(m_axi_hbm_araddr[15*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_15_ARBURST(m_axi_hbm_arburst[15*2 +: 2]), + .AXI_15_ARID(m_axi_hbm_arid[15*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_15_ARLEN(m_axi_hbm_arlen[15*8 +: 8]), + .AXI_15_ARSIZE(m_axi_hbm_arsize[15*3 +: 3]), + .AXI_15_ARVALID(m_axi_hbm_arvalid[15 +: 1]), + .AXI_15_ARREADY(m_axi_hbm_arready[15 +: 1]), + .AXI_15_RDATA_PARITY(), + .AXI_15_RDATA(m_axi_hbm_rdata[15*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_15_RID(m_axi_hbm_rid[15 +: 1]), + .AXI_15_RLAST(m_axi_hbm_rlast[15 +: 1]), + .AXI_15_RRESP(m_axi_hbm_rresp[15*2 +: 2]), + .AXI_15_RVALID(m_axi_hbm_rvalid[15 +: 1]), + .AXI_15_RREADY(m_axi_hbm_rready[15 +: 1]), + .AXI_15_AWADDR(m_axi_hbm_awaddr[15*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_15_AWBURST(m_axi_hbm_awburst[15*2 +: 2]), + .AXI_15_AWID(m_axi_hbm_awid[15*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_15_AWLEN(m_axi_hbm_awlen[15*8 +: 8]), + .AXI_15_AWSIZE(m_axi_hbm_awsize[15*3 +: 3]), + .AXI_15_AWVALID(m_axi_hbm_awvalid[15 +: 1]), + .AXI_15_AWREADY(m_axi_hbm_awready[15 +: 1]), + .AXI_15_WDATA(m_axi_hbm_wdata[15*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_15_WLAST(m_axi_hbm_wlast[15 +: 1]), + .AXI_15_WSTRB(m_axi_hbm_wstrb[15*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_15_WDATA_PARITY(32'd0), + .AXI_15_WVALID(m_axi_hbm_wvalid[15 +: 1]), + .AXI_15_WREADY(m_axi_hbm_wready[15 +: 1]), + .AXI_15_BID(m_axi_hbm_bid[15*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_15_BRESP(m_axi_hbm_bresp[15*2 +: 2]), + .AXI_15_BVALID(m_axi_hbm_bvalid[15 +: 1]), + .AXI_15_BREADY(m_axi_hbm_bready[15 +: 1]), + + .AXI_16_ACLK(hbm_clk[16 +: 1]), + .AXI_16_ARESET_N(!hbm_rst[16 +: 1]), + + .AXI_16_ARADDR(m_axi_hbm_araddr[16*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_16_ARBURST(m_axi_hbm_arburst[16*2 +: 2]), + .AXI_16_ARID(m_axi_hbm_arid[16*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_16_ARLEN(m_axi_hbm_arlen[16*8 +: 8]), + .AXI_16_ARSIZE(m_axi_hbm_arsize[16*3 +: 3]), + .AXI_16_ARVALID(m_axi_hbm_arvalid[16 +: 1]), + .AXI_16_ARREADY(m_axi_hbm_arready[16 +: 1]), + .AXI_16_RDATA_PARITY(), + .AXI_16_RDATA(m_axi_hbm_rdata[16*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_16_RID(m_axi_hbm_rid[16 +: 1]), + .AXI_16_RLAST(m_axi_hbm_rlast[16 +: 1]), + .AXI_16_RRESP(m_axi_hbm_rresp[16*2 +: 2]), + .AXI_16_RVALID(m_axi_hbm_rvalid[16 +: 1]), + .AXI_16_RREADY(m_axi_hbm_rready[16 +: 1]), + .AXI_16_AWADDR(m_axi_hbm_awaddr[16*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_16_AWBURST(m_axi_hbm_awburst[16*2 +: 2]), + .AXI_16_AWID(m_axi_hbm_awid[16*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_16_AWLEN(m_axi_hbm_awlen[16*8 +: 8]), + .AXI_16_AWSIZE(m_axi_hbm_awsize[16*3 +: 3]), + .AXI_16_AWVALID(m_axi_hbm_awvalid[16 +: 1]), + .AXI_16_AWREADY(m_axi_hbm_awready[16 +: 1]), + .AXI_16_WDATA(m_axi_hbm_wdata[16*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_16_WLAST(m_axi_hbm_wlast[16 +: 1]), + .AXI_16_WSTRB(m_axi_hbm_wstrb[16*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_16_WDATA_PARITY(32'd0), + .AXI_16_WVALID(m_axi_hbm_wvalid[16 +: 1]), + .AXI_16_WREADY(m_axi_hbm_wready[16 +: 1]), + .AXI_16_BID(m_axi_hbm_bid[16*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_16_BRESP(m_axi_hbm_bresp[16*2 +: 2]), + .AXI_16_BVALID(m_axi_hbm_bvalid[16 +: 1]), + .AXI_16_BREADY(m_axi_hbm_bready[16 +: 1]), + + .AXI_17_ACLK(hbm_clk[17 +: 1]), + .AXI_17_ARESET_N(!hbm_rst[17 +: 1]), + + .AXI_17_ARADDR(m_axi_hbm_araddr[17*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_17_ARBURST(m_axi_hbm_arburst[17*2 +: 2]), + .AXI_17_ARID(m_axi_hbm_arid[17*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_17_ARLEN(m_axi_hbm_arlen[17*8 +: 8]), + .AXI_17_ARSIZE(m_axi_hbm_arsize[17*3 +: 3]), + .AXI_17_ARVALID(m_axi_hbm_arvalid[17 +: 1]), + .AXI_17_ARREADY(m_axi_hbm_arready[17 +: 1]), + .AXI_17_RDATA_PARITY(), + .AXI_17_RDATA(m_axi_hbm_rdata[17*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_17_RID(m_axi_hbm_rid[17 +: 1]), + .AXI_17_RLAST(m_axi_hbm_rlast[17 +: 1]), + .AXI_17_RRESP(m_axi_hbm_rresp[17*2 +: 2]), + .AXI_17_RVALID(m_axi_hbm_rvalid[17 +: 1]), + .AXI_17_RREADY(m_axi_hbm_rready[17 +: 1]), + .AXI_17_AWADDR(m_axi_hbm_awaddr[17*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_17_AWBURST(m_axi_hbm_awburst[17*2 +: 2]), + .AXI_17_AWID(m_axi_hbm_awid[17*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_17_AWLEN(m_axi_hbm_awlen[17*8 +: 8]), + .AXI_17_AWSIZE(m_axi_hbm_awsize[17*3 +: 3]), + .AXI_17_AWVALID(m_axi_hbm_awvalid[17 +: 1]), + .AXI_17_AWREADY(m_axi_hbm_awready[17 +: 1]), + .AXI_17_WDATA(m_axi_hbm_wdata[17*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_17_WLAST(m_axi_hbm_wlast[17 +: 1]), + .AXI_17_WSTRB(m_axi_hbm_wstrb[17*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_17_WDATA_PARITY(32'd0), + .AXI_17_WVALID(m_axi_hbm_wvalid[17 +: 1]), + .AXI_17_WREADY(m_axi_hbm_wready[17 +: 1]), + .AXI_17_BID(m_axi_hbm_bid[17*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_17_BRESP(m_axi_hbm_bresp[17*2 +: 2]), + .AXI_17_BVALID(m_axi_hbm_bvalid[17 +: 1]), + .AXI_17_BREADY(m_axi_hbm_bready[17 +: 1]), + + .AXI_18_ACLK(hbm_clk[18 +: 1]), + .AXI_18_ARESET_N(!hbm_rst[18 +: 1]), + + .AXI_18_ARADDR(m_axi_hbm_araddr[18*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_18_ARBURST(m_axi_hbm_arburst[18*2 +: 2]), + .AXI_18_ARID(m_axi_hbm_arid[18*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_18_ARLEN(m_axi_hbm_arlen[18*8 +: 8]), + .AXI_18_ARSIZE(m_axi_hbm_arsize[18*3 +: 3]), + .AXI_18_ARVALID(m_axi_hbm_arvalid[18 +: 1]), + .AXI_18_ARREADY(m_axi_hbm_arready[18 +: 1]), + .AXI_18_RDATA_PARITY(), + .AXI_18_RDATA(m_axi_hbm_rdata[18*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_18_RID(m_axi_hbm_rid[18 +: 1]), + .AXI_18_RLAST(m_axi_hbm_rlast[18 +: 1]), + .AXI_18_RRESP(m_axi_hbm_rresp[18*2 +: 2]), + .AXI_18_RVALID(m_axi_hbm_rvalid[18 +: 1]), + .AXI_18_RREADY(m_axi_hbm_rready[18 +: 1]), + .AXI_18_AWADDR(m_axi_hbm_awaddr[18*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_18_AWBURST(m_axi_hbm_awburst[18*2 +: 2]), + .AXI_18_AWID(m_axi_hbm_awid[18*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_18_AWLEN(m_axi_hbm_awlen[18*8 +: 8]), + .AXI_18_AWSIZE(m_axi_hbm_awsize[18*3 +: 3]), + .AXI_18_AWVALID(m_axi_hbm_awvalid[18 +: 1]), + .AXI_18_AWREADY(m_axi_hbm_awready[18 +: 1]), + .AXI_18_WDATA(m_axi_hbm_wdata[18*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_18_WLAST(m_axi_hbm_wlast[18 +: 1]), + .AXI_18_WSTRB(m_axi_hbm_wstrb[18*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_18_WDATA_PARITY(32'd0), + .AXI_18_WVALID(m_axi_hbm_wvalid[18 +: 1]), + .AXI_18_WREADY(m_axi_hbm_wready[18 +: 1]), + .AXI_18_BID(m_axi_hbm_bid[18*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_18_BRESP(m_axi_hbm_bresp[18*2 +: 2]), + .AXI_18_BVALID(m_axi_hbm_bvalid[18 +: 1]), + .AXI_18_BREADY(m_axi_hbm_bready[18 +: 1]), + + .AXI_19_ACLK(hbm_clk[19 +: 1]), + .AXI_19_ARESET_N(!hbm_rst[19 +: 1]), + + .AXI_19_ARADDR(m_axi_hbm_araddr[19*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_19_ARBURST(m_axi_hbm_arburst[19*2 +: 2]), + .AXI_19_ARID(m_axi_hbm_arid[19*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_19_ARLEN(m_axi_hbm_arlen[19*8 +: 8]), + .AXI_19_ARSIZE(m_axi_hbm_arsize[19*3 +: 3]), + .AXI_19_ARVALID(m_axi_hbm_arvalid[19 +: 1]), + .AXI_19_ARREADY(m_axi_hbm_arready[19 +: 1]), + .AXI_19_RDATA_PARITY(), + .AXI_19_RDATA(m_axi_hbm_rdata[19*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_19_RID(m_axi_hbm_rid[19 +: 1]), + .AXI_19_RLAST(m_axi_hbm_rlast[19 +: 1]), + .AXI_19_RRESP(m_axi_hbm_rresp[19*2 +: 2]), + .AXI_19_RVALID(m_axi_hbm_rvalid[19 +: 1]), + .AXI_19_RREADY(m_axi_hbm_rready[19 +: 1]), + .AXI_19_AWADDR(m_axi_hbm_awaddr[19*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_19_AWBURST(m_axi_hbm_awburst[19*2 +: 2]), + .AXI_19_AWID(m_axi_hbm_awid[19*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_19_AWLEN(m_axi_hbm_awlen[19*8 +: 8]), + .AXI_19_AWSIZE(m_axi_hbm_awsize[19*3 +: 3]), + .AXI_19_AWVALID(m_axi_hbm_awvalid[19 +: 1]), + .AXI_19_AWREADY(m_axi_hbm_awready[19 +: 1]), + .AXI_19_WDATA(m_axi_hbm_wdata[19*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_19_WLAST(m_axi_hbm_wlast[19 +: 1]), + .AXI_19_WSTRB(m_axi_hbm_wstrb[19*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_19_WDATA_PARITY(32'd0), + .AXI_19_WVALID(m_axi_hbm_wvalid[19 +: 1]), + .AXI_19_WREADY(m_axi_hbm_wready[19 +: 1]), + .AXI_19_BID(m_axi_hbm_bid[19*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_19_BRESP(m_axi_hbm_bresp[19*2 +: 2]), + .AXI_19_BVALID(m_axi_hbm_bvalid[19 +: 1]), + .AXI_19_BREADY(m_axi_hbm_bready[19 +: 1]), + + .AXI_20_ACLK(hbm_clk[20 +: 1]), + .AXI_20_ARESET_N(!hbm_rst[20 +: 1]), + + .AXI_20_ARADDR(m_axi_hbm_araddr[20*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_20_ARBURST(m_axi_hbm_arburst[20*2 +: 2]), + .AXI_20_ARID(m_axi_hbm_arid[20*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_20_ARLEN(m_axi_hbm_arlen[20*8 +: 8]), + .AXI_20_ARSIZE(m_axi_hbm_arsize[20*3 +: 3]), + .AXI_20_ARVALID(m_axi_hbm_arvalid[20 +: 1]), + .AXI_20_ARREADY(m_axi_hbm_arready[20 +: 1]), + .AXI_20_RDATA_PARITY(), + .AXI_20_RDATA(m_axi_hbm_rdata[20*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_20_RID(m_axi_hbm_rid[20 +: 1]), + .AXI_20_RLAST(m_axi_hbm_rlast[20 +: 1]), + .AXI_20_RRESP(m_axi_hbm_rresp[20*2 +: 2]), + .AXI_20_RVALID(m_axi_hbm_rvalid[20 +: 1]), + .AXI_20_RREADY(m_axi_hbm_rready[20 +: 1]), + .AXI_20_AWADDR(m_axi_hbm_awaddr[20*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_20_AWBURST(m_axi_hbm_awburst[20*2 +: 2]), + .AXI_20_AWID(m_axi_hbm_awid[20*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_20_AWLEN(m_axi_hbm_awlen[20*8 +: 8]), + .AXI_20_AWSIZE(m_axi_hbm_awsize[20*3 +: 3]), + .AXI_20_AWVALID(m_axi_hbm_awvalid[20 +: 1]), + .AXI_20_AWREADY(m_axi_hbm_awready[20 +: 1]), + .AXI_20_WDATA(m_axi_hbm_wdata[20*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_20_WLAST(m_axi_hbm_wlast[20 +: 1]), + .AXI_20_WSTRB(m_axi_hbm_wstrb[20*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_20_WDATA_PARITY(32'd0), + .AXI_20_WVALID(m_axi_hbm_wvalid[20 +: 1]), + .AXI_20_WREADY(m_axi_hbm_wready[20 +: 1]), + .AXI_20_BID(m_axi_hbm_bid[20*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_20_BRESP(m_axi_hbm_bresp[20*2 +: 2]), + .AXI_20_BVALID(m_axi_hbm_bvalid[20 +: 1]), + .AXI_20_BREADY(m_axi_hbm_bready[20 +: 1]), + + .AXI_21_ACLK(hbm_clk[21 +: 1]), + .AXI_21_ARESET_N(!hbm_rst[21 +: 1]), + + .AXI_21_ARADDR(m_axi_hbm_araddr[21*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_21_ARBURST(m_axi_hbm_arburst[21*2 +: 2]), + .AXI_21_ARID(m_axi_hbm_arid[21*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_21_ARLEN(m_axi_hbm_arlen[21*8 +: 8]), + .AXI_21_ARSIZE(m_axi_hbm_arsize[21*3 +: 3]), + .AXI_21_ARVALID(m_axi_hbm_arvalid[21 +: 1]), + .AXI_21_ARREADY(m_axi_hbm_arready[21 +: 1]), + .AXI_21_RDATA_PARITY(), + .AXI_21_RDATA(m_axi_hbm_rdata[21*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_21_RID(m_axi_hbm_rid[21 +: 1]), + .AXI_21_RLAST(m_axi_hbm_rlast[21 +: 1]), + .AXI_21_RRESP(m_axi_hbm_rresp[21*2 +: 2]), + .AXI_21_RVALID(m_axi_hbm_rvalid[21 +: 1]), + .AXI_21_RREADY(m_axi_hbm_rready[21 +: 1]), + .AXI_21_AWADDR(m_axi_hbm_awaddr[21*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_21_AWBURST(m_axi_hbm_awburst[21*2 +: 2]), + .AXI_21_AWID(m_axi_hbm_awid[21*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_21_AWLEN(m_axi_hbm_awlen[21*8 +: 8]), + .AXI_21_AWSIZE(m_axi_hbm_awsize[21*3 +: 3]), + .AXI_21_AWVALID(m_axi_hbm_awvalid[21 +: 1]), + .AXI_21_AWREADY(m_axi_hbm_awready[21 +: 1]), + .AXI_21_WDATA(m_axi_hbm_wdata[21*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_21_WLAST(m_axi_hbm_wlast[21 +: 1]), + .AXI_21_WSTRB(m_axi_hbm_wstrb[21*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_21_WDATA_PARITY(32'd0), + .AXI_21_WVALID(m_axi_hbm_wvalid[21 +: 1]), + .AXI_21_WREADY(m_axi_hbm_wready[21 +: 1]), + .AXI_21_BID(m_axi_hbm_bid[21*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_21_BRESP(m_axi_hbm_bresp[21*2 +: 2]), + .AXI_21_BVALID(m_axi_hbm_bvalid[21 +: 1]), + .AXI_21_BREADY(m_axi_hbm_bready[21 +: 1]), + + .AXI_22_ACLK(hbm_clk[22 +: 1]), + .AXI_22_ARESET_N(!hbm_rst[22 +: 1]), + + .AXI_22_ARADDR(m_axi_hbm_araddr[22*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_22_ARBURST(m_axi_hbm_arburst[22*2 +: 2]), + .AXI_22_ARID(m_axi_hbm_arid[22*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_22_ARLEN(m_axi_hbm_arlen[22*8 +: 8]), + .AXI_22_ARSIZE(m_axi_hbm_arsize[22*3 +: 3]), + .AXI_22_ARVALID(m_axi_hbm_arvalid[22 +: 1]), + .AXI_22_ARREADY(m_axi_hbm_arready[22 +: 1]), + .AXI_22_RDATA_PARITY(), + .AXI_22_RDATA(m_axi_hbm_rdata[22*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_22_RID(m_axi_hbm_rid[22 +: 1]), + .AXI_22_RLAST(m_axi_hbm_rlast[22 +: 1]), + .AXI_22_RRESP(m_axi_hbm_rresp[22*2 +: 2]), + .AXI_22_RVALID(m_axi_hbm_rvalid[22 +: 1]), + .AXI_22_RREADY(m_axi_hbm_rready[22 +: 1]), + .AXI_22_AWADDR(m_axi_hbm_awaddr[22*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_22_AWBURST(m_axi_hbm_awburst[22*2 +: 2]), + .AXI_22_AWID(m_axi_hbm_awid[22*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_22_AWLEN(m_axi_hbm_awlen[22*8 +: 8]), + .AXI_22_AWSIZE(m_axi_hbm_awsize[22*3 +: 3]), + .AXI_22_AWVALID(m_axi_hbm_awvalid[22 +: 1]), + .AXI_22_AWREADY(m_axi_hbm_awready[22 +: 1]), + .AXI_22_WDATA(m_axi_hbm_wdata[22*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_22_WLAST(m_axi_hbm_wlast[22 +: 1]), + .AXI_22_WSTRB(m_axi_hbm_wstrb[22*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_22_WDATA_PARITY(32'd0), + .AXI_22_WVALID(m_axi_hbm_wvalid[22 +: 1]), + .AXI_22_WREADY(m_axi_hbm_wready[22 +: 1]), + .AXI_22_BID(m_axi_hbm_bid[22*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_22_BRESP(m_axi_hbm_bresp[22*2 +: 2]), + .AXI_22_BVALID(m_axi_hbm_bvalid[22 +: 1]), + .AXI_22_BREADY(m_axi_hbm_bready[22 +: 1]), + + .AXI_23_ACLK(hbm_clk[23 +: 1]), + .AXI_23_ARESET_N(!hbm_rst[23 +: 1]), + + .AXI_23_ARADDR(m_axi_hbm_araddr[23*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_23_ARBURST(m_axi_hbm_arburst[23*2 +: 2]), + .AXI_23_ARID(m_axi_hbm_arid[23*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_23_ARLEN(m_axi_hbm_arlen[23*8 +: 8]), + .AXI_23_ARSIZE(m_axi_hbm_arsize[23*3 +: 3]), + .AXI_23_ARVALID(m_axi_hbm_arvalid[23 +: 1]), + .AXI_23_ARREADY(m_axi_hbm_arready[23 +: 1]), + .AXI_23_RDATA_PARITY(), + .AXI_23_RDATA(m_axi_hbm_rdata[23*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_23_RID(m_axi_hbm_rid[23 +: 1]), + .AXI_23_RLAST(m_axi_hbm_rlast[23 +: 1]), + .AXI_23_RRESP(m_axi_hbm_rresp[23*2 +: 2]), + .AXI_23_RVALID(m_axi_hbm_rvalid[23 +: 1]), + .AXI_23_RREADY(m_axi_hbm_rready[23 +: 1]), + .AXI_23_AWADDR(m_axi_hbm_awaddr[23*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_23_AWBURST(m_axi_hbm_awburst[23*2 +: 2]), + .AXI_23_AWID(m_axi_hbm_awid[23*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_23_AWLEN(m_axi_hbm_awlen[23*8 +: 8]), + .AXI_23_AWSIZE(m_axi_hbm_awsize[23*3 +: 3]), + .AXI_23_AWVALID(m_axi_hbm_awvalid[23 +: 1]), + .AXI_23_AWREADY(m_axi_hbm_awready[23 +: 1]), + .AXI_23_WDATA(m_axi_hbm_wdata[23*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_23_WLAST(m_axi_hbm_wlast[23 +: 1]), + .AXI_23_WSTRB(m_axi_hbm_wstrb[23*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_23_WDATA_PARITY(32'd0), + .AXI_23_WVALID(m_axi_hbm_wvalid[23 +: 1]), + .AXI_23_WREADY(m_axi_hbm_wready[23 +: 1]), + .AXI_23_BID(m_axi_hbm_bid[23*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_23_BRESP(m_axi_hbm_bresp[23*2 +: 2]), + .AXI_23_BVALID(m_axi_hbm_bvalid[23 +: 1]), + .AXI_23_BREADY(m_axi_hbm_bready[23 +: 1]), + + .AXI_24_ACLK(hbm_clk[24 +: 1]), + .AXI_24_ARESET_N(!hbm_rst[24 +: 1]), + + .AXI_24_ARADDR(m_axi_hbm_araddr[24*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_24_ARBURST(m_axi_hbm_arburst[24*2 +: 2]), + .AXI_24_ARID(m_axi_hbm_arid[24*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_24_ARLEN(m_axi_hbm_arlen[24*8 +: 8]), + .AXI_24_ARSIZE(m_axi_hbm_arsize[24*3 +: 3]), + .AXI_24_ARVALID(m_axi_hbm_arvalid[24 +: 1]), + .AXI_24_ARREADY(m_axi_hbm_arready[24 +: 1]), + .AXI_24_RDATA_PARITY(), + .AXI_24_RDATA(m_axi_hbm_rdata[24*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_24_RID(m_axi_hbm_rid[24 +: 1]), + .AXI_24_RLAST(m_axi_hbm_rlast[24 +: 1]), + .AXI_24_RRESP(m_axi_hbm_rresp[24*2 +: 2]), + .AXI_24_RVALID(m_axi_hbm_rvalid[24 +: 1]), + .AXI_24_RREADY(m_axi_hbm_rready[24 +: 1]), + .AXI_24_AWADDR(m_axi_hbm_awaddr[24*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_24_AWBURST(m_axi_hbm_awburst[24*2 +: 2]), + .AXI_24_AWID(m_axi_hbm_awid[24*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_24_AWLEN(m_axi_hbm_awlen[24*8 +: 8]), + .AXI_24_AWSIZE(m_axi_hbm_awsize[24*3 +: 3]), + .AXI_24_AWVALID(m_axi_hbm_awvalid[24 +: 1]), + .AXI_24_AWREADY(m_axi_hbm_awready[24 +: 1]), + .AXI_24_WDATA(m_axi_hbm_wdata[24*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_24_WLAST(m_axi_hbm_wlast[24 +: 1]), + .AXI_24_WSTRB(m_axi_hbm_wstrb[24*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_24_WDATA_PARITY(32'd0), + .AXI_24_WVALID(m_axi_hbm_wvalid[24 +: 1]), + .AXI_24_WREADY(m_axi_hbm_wready[24 +: 1]), + .AXI_24_BID(m_axi_hbm_bid[24*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_24_BRESP(m_axi_hbm_bresp[24*2 +: 2]), + .AXI_24_BVALID(m_axi_hbm_bvalid[24 +: 1]), + .AXI_24_BREADY(m_axi_hbm_bready[24 +: 1]), + + .AXI_25_ACLK(hbm_clk[25 +: 1]), + .AXI_25_ARESET_N(!hbm_rst[25 +: 1]), + + .AXI_25_ARADDR(m_axi_hbm_araddr[25*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_25_ARBURST(m_axi_hbm_arburst[25*2 +: 2]), + .AXI_25_ARID(m_axi_hbm_arid[25*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_25_ARLEN(m_axi_hbm_arlen[25*8 +: 8]), + .AXI_25_ARSIZE(m_axi_hbm_arsize[25*3 +: 3]), + .AXI_25_ARVALID(m_axi_hbm_arvalid[25 +: 1]), + .AXI_25_ARREADY(m_axi_hbm_arready[25 +: 1]), + .AXI_25_RDATA_PARITY(), + .AXI_25_RDATA(m_axi_hbm_rdata[25*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_25_RID(m_axi_hbm_rid[25 +: 1]), + .AXI_25_RLAST(m_axi_hbm_rlast[25 +: 1]), + .AXI_25_RRESP(m_axi_hbm_rresp[25*2 +: 2]), + .AXI_25_RVALID(m_axi_hbm_rvalid[25 +: 1]), + .AXI_25_RREADY(m_axi_hbm_rready[25 +: 1]), + .AXI_25_AWADDR(m_axi_hbm_awaddr[25*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_25_AWBURST(m_axi_hbm_awburst[25*2 +: 2]), + .AXI_25_AWID(m_axi_hbm_awid[25*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_25_AWLEN(m_axi_hbm_awlen[25*8 +: 8]), + .AXI_25_AWSIZE(m_axi_hbm_awsize[25*3 +: 3]), + .AXI_25_AWVALID(m_axi_hbm_awvalid[25 +: 1]), + .AXI_25_AWREADY(m_axi_hbm_awready[25 +: 1]), + .AXI_25_WDATA(m_axi_hbm_wdata[25*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_25_WLAST(m_axi_hbm_wlast[25 +: 1]), + .AXI_25_WSTRB(m_axi_hbm_wstrb[25*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_25_WDATA_PARITY(32'd0), + .AXI_25_WVALID(m_axi_hbm_wvalid[25 +: 1]), + .AXI_25_WREADY(m_axi_hbm_wready[25 +: 1]), + .AXI_25_BID(m_axi_hbm_bid[25*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_25_BRESP(m_axi_hbm_bresp[25*2 +: 2]), + .AXI_25_BVALID(m_axi_hbm_bvalid[25 +: 1]), + .AXI_25_BREADY(m_axi_hbm_bready[25 +: 1]), + + .AXI_26_ACLK(hbm_clk[26 +: 1]), + .AXI_26_ARESET_N(!hbm_rst[26 +: 1]), + + .AXI_26_ARADDR(m_axi_hbm_araddr[26*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_26_ARBURST(m_axi_hbm_arburst[26*2 +: 2]), + .AXI_26_ARID(m_axi_hbm_arid[26*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_26_ARLEN(m_axi_hbm_arlen[26*8 +: 8]), + .AXI_26_ARSIZE(m_axi_hbm_arsize[26*3 +: 3]), + .AXI_26_ARVALID(m_axi_hbm_arvalid[26 +: 1]), + .AXI_26_ARREADY(m_axi_hbm_arready[26 +: 1]), + .AXI_26_RDATA_PARITY(), + .AXI_26_RDATA(m_axi_hbm_rdata[26*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_26_RID(m_axi_hbm_rid[26 +: 1]), + .AXI_26_RLAST(m_axi_hbm_rlast[26 +: 1]), + .AXI_26_RRESP(m_axi_hbm_rresp[26*2 +: 2]), + .AXI_26_RVALID(m_axi_hbm_rvalid[26 +: 1]), + .AXI_26_RREADY(m_axi_hbm_rready[26 +: 1]), + .AXI_26_AWADDR(m_axi_hbm_awaddr[26*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_26_AWBURST(m_axi_hbm_awburst[26*2 +: 2]), + .AXI_26_AWID(m_axi_hbm_awid[26*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_26_AWLEN(m_axi_hbm_awlen[26*8 +: 8]), + .AXI_26_AWSIZE(m_axi_hbm_awsize[26*3 +: 3]), + .AXI_26_AWVALID(m_axi_hbm_awvalid[26 +: 1]), + .AXI_26_AWREADY(m_axi_hbm_awready[26 +: 1]), + .AXI_26_WDATA(m_axi_hbm_wdata[26*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_26_WLAST(m_axi_hbm_wlast[26 +: 1]), + .AXI_26_WSTRB(m_axi_hbm_wstrb[26*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_26_WDATA_PARITY(32'd0), + .AXI_26_WVALID(m_axi_hbm_wvalid[26 +: 1]), + .AXI_26_WREADY(m_axi_hbm_wready[26 +: 1]), + .AXI_26_BID(m_axi_hbm_bid[26*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_26_BRESP(m_axi_hbm_bresp[26*2 +: 2]), + .AXI_26_BVALID(m_axi_hbm_bvalid[26 +: 1]), + .AXI_26_BREADY(m_axi_hbm_bready[26 +: 1]), + + .AXI_27_ACLK(hbm_clk[27 +: 1]), + .AXI_27_ARESET_N(!hbm_rst[27 +: 1]), + + .AXI_27_ARADDR(m_axi_hbm_araddr[27*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_27_ARBURST(m_axi_hbm_arburst[27*2 +: 2]), + .AXI_27_ARID(m_axi_hbm_arid[27*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_27_ARLEN(m_axi_hbm_arlen[27*8 +: 8]), + .AXI_27_ARSIZE(m_axi_hbm_arsize[27*3 +: 3]), + .AXI_27_ARVALID(m_axi_hbm_arvalid[27 +: 1]), + .AXI_27_ARREADY(m_axi_hbm_arready[27 +: 1]), + .AXI_27_RDATA_PARITY(), + .AXI_27_RDATA(m_axi_hbm_rdata[27*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_27_RID(m_axi_hbm_rid[27 +: 1]), + .AXI_27_RLAST(m_axi_hbm_rlast[27 +: 1]), + .AXI_27_RRESP(m_axi_hbm_rresp[27*2 +: 2]), + .AXI_27_RVALID(m_axi_hbm_rvalid[27 +: 1]), + .AXI_27_RREADY(m_axi_hbm_rready[27 +: 1]), + .AXI_27_AWADDR(m_axi_hbm_awaddr[27*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_27_AWBURST(m_axi_hbm_awburst[27*2 +: 2]), + .AXI_27_AWID(m_axi_hbm_awid[27*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_27_AWLEN(m_axi_hbm_awlen[27*8 +: 8]), + .AXI_27_AWSIZE(m_axi_hbm_awsize[27*3 +: 3]), + .AXI_27_AWVALID(m_axi_hbm_awvalid[27 +: 1]), + .AXI_27_AWREADY(m_axi_hbm_awready[27 +: 1]), + .AXI_27_WDATA(m_axi_hbm_wdata[27*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_27_WLAST(m_axi_hbm_wlast[27 +: 1]), + .AXI_27_WSTRB(m_axi_hbm_wstrb[27*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_27_WDATA_PARITY(32'd0), + .AXI_27_WVALID(m_axi_hbm_wvalid[27 +: 1]), + .AXI_27_WREADY(m_axi_hbm_wready[27 +: 1]), + .AXI_27_BID(m_axi_hbm_bid[27*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_27_BRESP(m_axi_hbm_bresp[27*2 +: 2]), + .AXI_27_BVALID(m_axi_hbm_bvalid[27 +: 1]), + .AXI_27_BREADY(m_axi_hbm_bready[27 +: 1]), + + .AXI_28_ACLK(hbm_clk[28 +: 1]), + .AXI_28_ARESET_N(!hbm_rst[28 +: 1]), + + .AXI_28_ARADDR(m_axi_hbm_araddr[28*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_28_ARBURST(m_axi_hbm_arburst[28*2 +: 2]), + .AXI_28_ARID(m_axi_hbm_arid[28*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_28_ARLEN(m_axi_hbm_arlen[28*8 +: 8]), + .AXI_28_ARSIZE(m_axi_hbm_arsize[28*3 +: 3]), + .AXI_28_ARVALID(m_axi_hbm_arvalid[28 +: 1]), + .AXI_28_ARREADY(m_axi_hbm_arready[28 +: 1]), + .AXI_28_RDATA_PARITY(), + .AXI_28_RDATA(m_axi_hbm_rdata[28*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_28_RID(m_axi_hbm_rid[28 +: 1]), + .AXI_28_RLAST(m_axi_hbm_rlast[28 +: 1]), + .AXI_28_RRESP(m_axi_hbm_rresp[28*2 +: 2]), + .AXI_28_RVALID(m_axi_hbm_rvalid[28 +: 1]), + .AXI_28_RREADY(m_axi_hbm_rready[28 +: 1]), + .AXI_28_AWADDR(m_axi_hbm_awaddr[28*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_28_AWBURST(m_axi_hbm_awburst[28*2 +: 2]), + .AXI_28_AWID(m_axi_hbm_awid[28*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_28_AWLEN(m_axi_hbm_awlen[28*8 +: 8]), + .AXI_28_AWSIZE(m_axi_hbm_awsize[28*3 +: 3]), + .AXI_28_AWVALID(m_axi_hbm_awvalid[28 +: 1]), + .AXI_28_AWREADY(m_axi_hbm_awready[28 +: 1]), + .AXI_28_WDATA(m_axi_hbm_wdata[28*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_28_WLAST(m_axi_hbm_wlast[28 +: 1]), + .AXI_28_WSTRB(m_axi_hbm_wstrb[28*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_28_WDATA_PARITY(32'd0), + .AXI_28_WVALID(m_axi_hbm_wvalid[28 +: 1]), + .AXI_28_WREADY(m_axi_hbm_wready[28 +: 1]), + .AXI_28_BID(m_axi_hbm_bid[28*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_28_BRESP(m_axi_hbm_bresp[28*2 +: 2]), + .AXI_28_BVALID(m_axi_hbm_bvalid[28 +: 1]), + .AXI_28_BREADY(m_axi_hbm_bready[28 +: 1]), + + .AXI_29_ACLK(hbm_clk[29 +: 1]), + .AXI_29_ARESET_N(!hbm_rst[29 +: 1]), + + .AXI_29_ARADDR(m_axi_hbm_araddr[29*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_29_ARBURST(m_axi_hbm_arburst[29*2 +: 2]), + .AXI_29_ARID(m_axi_hbm_arid[29*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_29_ARLEN(m_axi_hbm_arlen[29*8 +: 8]), + .AXI_29_ARSIZE(m_axi_hbm_arsize[29*3 +: 3]), + .AXI_29_ARVALID(m_axi_hbm_arvalid[29 +: 1]), + .AXI_29_ARREADY(m_axi_hbm_arready[29 +: 1]), + .AXI_29_RDATA_PARITY(), + .AXI_29_RDATA(m_axi_hbm_rdata[29*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_29_RID(m_axi_hbm_rid[29 +: 1]), + .AXI_29_RLAST(m_axi_hbm_rlast[29 +: 1]), + .AXI_29_RRESP(m_axi_hbm_rresp[29*2 +: 2]), + .AXI_29_RVALID(m_axi_hbm_rvalid[29 +: 1]), + .AXI_29_RREADY(m_axi_hbm_rready[29 +: 1]), + .AXI_29_AWADDR(m_axi_hbm_awaddr[29*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_29_AWBURST(m_axi_hbm_awburst[29*2 +: 2]), + .AXI_29_AWID(m_axi_hbm_awid[29*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_29_AWLEN(m_axi_hbm_awlen[29*8 +: 8]), + .AXI_29_AWSIZE(m_axi_hbm_awsize[29*3 +: 3]), + .AXI_29_AWVALID(m_axi_hbm_awvalid[29 +: 1]), + .AXI_29_AWREADY(m_axi_hbm_awready[29 +: 1]), + .AXI_29_WDATA(m_axi_hbm_wdata[29*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_29_WLAST(m_axi_hbm_wlast[29 +: 1]), + .AXI_29_WSTRB(m_axi_hbm_wstrb[29*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_29_WDATA_PARITY(32'd0), + .AXI_29_WVALID(m_axi_hbm_wvalid[29 +: 1]), + .AXI_29_WREADY(m_axi_hbm_wready[29 +: 1]), + .AXI_29_BID(m_axi_hbm_bid[29*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_29_BRESP(m_axi_hbm_bresp[29*2 +: 2]), + .AXI_29_BVALID(m_axi_hbm_bvalid[29 +: 1]), + .AXI_29_BREADY(m_axi_hbm_bready[29 +: 1]), + + .AXI_30_ACLK(hbm_clk[30 +: 1]), + .AXI_30_ARESET_N(!hbm_rst[30 +: 1]), + + .AXI_30_ARADDR(m_axi_hbm_araddr[30*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_30_ARBURST(m_axi_hbm_arburst[30*2 +: 2]), + .AXI_30_ARID(m_axi_hbm_arid[30*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_30_ARLEN(m_axi_hbm_arlen[30*8 +: 8]), + .AXI_30_ARSIZE(m_axi_hbm_arsize[30*3 +: 3]), + .AXI_30_ARVALID(m_axi_hbm_arvalid[30 +: 1]), + .AXI_30_ARREADY(m_axi_hbm_arready[30 +: 1]), + .AXI_30_RDATA_PARITY(), + .AXI_30_RDATA(m_axi_hbm_rdata[30*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_30_RID(m_axi_hbm_rid[30 +: 1]), + .AXI_30_RLAST(m_axi_hbm_rlast[30 +: 1]), + .AXI_30_RRESP(m_axi_hbm_rresp[30*2 +: 2]), + .AXI_30_RVALID(m_axi_hbm_rvalid[30 +: 1]), + .AXI_30_RREADY(m_axi_hbm_rready[30 +: 1]), + .AXI_30_AWADDR(m_axi_hbm_awaddr[30*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_30_AWBURST(m_axi_hbm_awburst[30*2 +: 2]), + .AXI_30_AWID(m_axi_hbm_awid[30*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_30_AWLEN(m_axi_hbm_awlen[30*8 +: 8]), + .AXI_30_AWSIZE(m_axi_hbm_awsize[30*3 +: 3]), + .AXI_30_AWVALID(m_axi_hbm_awvalid[30 +: 1]), + .AXI_30_AWREADY(m_axi_hbm_awready[30 +: 1]), + .AXI_30_WDATA(m_axi_hbm_wdata[30*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_30_WLAST(m_axi_hbm_wlast[30 +: 1]), + .AXI_30_WSTRB(m_axi_hbm_wstrb[30*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_30_WDATA_PARITY(32'd0), + .AXI_30_WVALID(m_axi_hbm_wvalid[30 +: 1]), + .AXI_30_WREADY(m_axi_hbm_wready[30 +: 1]), + .AXI_30_BID(m_axi_hbm_bid[30*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_30_BRESP(m_axi_hbm_bresp[30*2 +: 2]), + .AXI_30_BVALID(m_axi_hbm_bvalid[30 +: 1]), + .AXI_30_BREADY(m_axi_hbm_bready[30 +: 1]), + + .AXI_31_ACLK(hbm_clk[31 +: 1]), + .AXI_31_ARESET_N(!hbm_rst[31 +: 1]), + + .AXI_31_ARADDR(m_axi_hbm_araddr[31*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_31_ARBURST(m_axi_hbm_arburst[31*2 +: 2]), + .AXI_31_ARID(m_axi_hbm_arid[31*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_31_ARLEN(m_axi_hbm_arlen[31*8 +: 8]), + .AXI_31_ARSIZE(m_axi_hbm_arsize[31*3 +: 3]), + .AXI_31_ARVALID(m_axi_hbm_arvalid[31 +: 1]), + .AXI_31_ARREADY(m_axi_hbm_arready[31 +: 1]), + .AXI_31_RDATA_PARITY(), + .AXI_31_RDATA(m_axi_hbm_rdata[31*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_31_RID(m_axi_hbm_rid[31 +: 1]), + .AXI_31_RLAST(m_axi_hbm_rlast[31 +: 1]), + .AXI_31_RRESP(m_axi_hbm_rresp[31*2 +: 2]), + .AXI_31_RVALID(m_axi_hbm_rvalid[31 +: 1]), + .AXI_31_RREADY(m_axi_hbm_rready[31 +: 1]), + .AXI_31_AWADDR(m_axi_hbm_awaddr[31*AXI_HBM_ADDR_WIDTH +: AXI_HBM_ADDR_WIDTH]), + .AXI_31_AWBURST(m_axi_hbm_awburst[31*2 +: 2]), + .AXI_31_AWID(m_axi_hbm_awid[31*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_31_AWLEN(m_axi_hbm_awlen[31*8 +: 8]), + .AXI_31_AWSIZE(m_axi_hbm_awsize[31*3 +: 3]), + .AXI_31_AWVALID(m_axi_hbm_awvalid[31 +: 1]), + .AXI_31_AWREADY(m_axi_hbm_awready[31 +: 1]), + .AXI_31_WDATA(m_axi_hbm_wdata[31*AXI_HBM_DATA_WIDTH +: AXI_HBM_DATA_WIDTH]), + .AXI_31_WLAST(m_axi_hbm_wlast[31 +: 1]), + .AXI_31_WSTRB(m_axi_hbm_wstrb[31*AXI_HBM_STRB_WIDTH +: AXI_HBM_STRB_WIDTH]), + .AXI_31_WDATA_PARITY(32'd0), + .AXI_31_WVALID(m_axi_hbm_wvalid[31 +: 1]), + .AXI_31_WREADY(m_axi_hbm_wready[31 +: 1]), + .AXI_31_BID(m_axi_hbm_bid[31*AXI_HBM_ID_WIDTH +: AXI_HBM_ID_WIDTH]), + .AXI_31_BRESP(m_axi_hbm_bresp[31*2 +: 2]), + .AXI_31_BVALID(m_axi_hbm_bvalid[31 +: 1]), + .AXI_31_BREADY(m_axi_hbm_bready[31 +: 1]), + + .DRAM_0_STAT_CATTRIP(hbm_cattrip_1), + .DRAM_0_STAT_TEMP(hbm_temp_1), + .DRAM_1_STAT_CATTRIP(hbm_cattrip_2), + .DRAM_1_STAT_TEMP(hbm_temp_2) +); + +assign hbm_status = {HBM_CH{1'b1}}; + +end else begin + +assign hbm_clk = 0; +assign hbm_rst = 0; + +assign m_axi_hbm_awready = 0; +assign m_axi_hbm_wready = 0; +assign m_axi_hbm_bid = 0; +assign m_axi_hbm_bresp = 0; +assign m_axi_hbm_bvalid = 0; +assign m_axi_hbm_arready = 0; +assign m_axi_hbm_rid = 0; +assign m_axi_hbm_rdata = 0; +assign m_axi_hbm_rresp = 0; +assign m_axi_hbm_rlast = 0; +assign m_axi_hbm_rvalid = 0; + +assign hbm_status = 0; + +end + +endgenerate + fpga_core #( // FW and board IDs .FPGA_ID(FPGA_ID), @@ -1228,6 +2598,16 @@ fpga_core #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .HBM_CH(HBM_CH), + .HBM_ENABLE(HBM_ENABLE), + .HBM_GROUP_SIZE(HBM_GROUP_SIZE), + .AXI_HBM_DATA_WIDTH(AXI_HBM_DATA_WIDTH), + .AXI_HBM_ADDR_WIDTH(AXI_HBM_ADDR_WIDTH), + .AXI_HBM_STRB_WIDTH(AXI_HBM_STRB_WIDTH), + .AXI_HBM_ID_WIDTH(AXI_HBM_ID_WIDTH), + .AXI_HBM_MAX_BURST_LEN(AXI_HBM_MAX_BURST_LEN), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1454,6 +2834,50 @@ core_inst ( .qsfp_drp_do(qsfp_drp_do), .qsfp_drp_rdy(qsfp_drp_rdy), + /* + * HBM + */ + .hbm_clk(hbm_clk), + .hbm_rst(hbm_rst), + + .m_axi_hbm_awid(m_axi_hbm_awid), + .m_axi_hbm_awaddr(m_axi_hbm_awaddr), + .m_axi_hbm_awlen(m_axi_hbm_awlen), + .m_axi_hbm_awsize(m_axi_hbm_awsize), + .m_axi_hbm_awburst(m_axi_hbm_awburst), + .m_axi_hbm_awlock(m_axi_hbm_awlock), + .m_axi_hbm_awcache(m_axi_hbm_awcache), + .m_axi_hbm_awprot(m_axi_hbm_awprot), + .m_axi_hbm_awqos(m_axi_hbm_awqos), + .m_axi_hbm_awvalid(m_axi_hbm_awvalid), + .m_axi_hbm_awready(m_axi_hbm_awready), + .m_axi_hbm_wdata(m_axi_hbm_wdata), + .m_axi_hbm_wstrb(m_axi_hbm_wstrb), + .m_axi_hbm_wlast(m_axi_hbm_wlast), + .m_axi_hbm_wvalid(m_axi_hbm_wvalid), + .m_axi_hbm_wready(m_axi_hbm_wready), + .m_axi_hbm_bid(m_axi_hbm_bid), + .m_axi_hbm_bresp(m_axi_hbm_bresp), + .m_axi_hbm_bvalid(m_axi_hbm_bvalid), + .m_axi_hbm_bready(m_axi_hbm_bready), + .m_axi_hbm_arid(m_axi_hbm_arid), + .m_axi_hbm_araddr(m_axi_hbm_araddr), + .m_axi_hbm_arlen(m_axi_hbm_arlen), + .m_axi_hbm_arsize(m_axi_hbm_arsize), + .m_axi_hbm_arburst(m_axi_hbm_arburst), + .m_axi_hbm_arlock(m_axi_hbm_arlock), + .m_axi_hbm_arcache(m_axi_hbm_arcache), + .m_axi_hbm_arprot(m_axi_hbm_arprot), + .m_axi_hbm_arqos(m_axi_hbm_arqos), + .m_axi_hbm_arvalid(m_axi_hbm_arvalid), + .m_axi_hbm_arready(m_axi_hbm_arready), + .m_axi_hbm_rid(m_axi_hbm_rid), + .m_axi_hbm_rdata(m_axi_hbm_rdata), + .m_axi_hbm_rresp(m_axi_hbm_rresp), + .m_axi_hbm_rlast(m_axi_hbm_rlast), + .m_axi_hbm_rvalid(m_axi_hbm_rvalid), + .m_axi_hbm_rready(m_axi_hbm_rready), + /* * QSPI flash */ diff --git a/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v index 940db81db..b33996265 100644 --- a/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v @@ -122,6 +122,16 @@ module fpga_core # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // RAM configuration + parameter HBM_CH = 32, + parameter HBM_ENABLE = 1, + parameter HBM_GROUP_SIZE = 32, + parameter AXI_HBM_DATA_WIDTH = 256, + parameter AXI_HBM_ADDR_WIDTH = 33, + parameter AXI_HBM_STRB_WIDTH = (AXI_HBM_DATA_WIDTH/8), + parameter AXI_HBM_ID_WIDTH = 6, + parameter AXI_HBM_MAX_BURST_LEN = 256, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -350,6 +360,52 @@ module fpga_core # input wire [15:0] qsfp_drp_do, input wire qsfp_drp_rdy, + /* + * HBM + */ + input wire [HBM_CH-1:0] hbm_clk, + input wire [HBM_CH-1:0] hbm_rst, + + output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_awid, + output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_awaddr, + output wire [HBM_CH*8-1:0] m_axi_hbm_awlen, + output wire [HBM_CH*3-1:0] m_axi_hbm_awsize, + output wire [HBM_CH*2-1:0] m_axi_hbm_awburst, + output wire [HBM_CH-1:0] m_axi_hbm_awlock, + output wire [HBM_CH*4-1:0] m_axi_hbm_awcache, + output wire [HBM_CH*3-1:0] m_axi_hbm_awprot, + output wire [HBM_CH*4-1:0] m_axi_hbm_awqos, + output wire [HBM_CH-1:0] m_axi_hbm_awvalid, + input wire [HBM_CH-1:0] m_axi_hbm_awready, + output wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_wdata, + output wire [HBM_CH*AXI_HBM_STRB_WIDTH-1:0] m_axi_hbm_wstrb, + output wire [HBM_CH-1:0] m_axi_hbm_wlast, + output wire [HBM_CH-1:0] m_axi_hbm_wvalid, + input wire [HBM_CH-1:0] m_axi_hbm_wready, + input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_bid, + input wire [HBM_CH*2-1:0] m_axi_hbm_bresp, + input wire [HBM_CH-1:0] m_axi_hbm_bvalid, + output wire [HBM_CH-1:0] m_axi_hbm_bready, + output wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_arid, + output wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] m_axi_hbm_araddr, + output wire [HBM_CH*8-1:0] m_axi_hbm_arlen, + output wire [HBM_CH*3-1:0] m_axi_hbm_arsize, + output wire [HBM_CH*2-1:0] m_axi_hbm_arburst, + output wire [HBM_CH-1:0] m_axi_hbm_arlock, + output wire [HBM_CH*4-1:0] m_axi_hbm_arcache, + output wire [HBM_CH*3-1:0] m_axi_hbm_arprot, + output wire [HBM_CH*4-1:0] m_axi_hbm_arqos, + output wire [HBM_CH-1:0] m_axi_hbm_arvalid, + input wire [HBM_CH-1:0] m_axi_hbm_arready, + input wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] m_axi_hbm_rid, + input wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] m_axi_hbm_rdata, + input wire [HBM_CH*2-1:0] m_axi_hbm_rresp, + input wire [HBM_CH-1:0] m_axi_hbm_rlast, + input wire [HBM_CH-1:0] m_axi_hbm_rvalid, + output wire [HBM_CH-1:0] m_axi_hbm_rready, + + input wire [HBM_CH-1:0] hbm_status, + /* * QSPI flash */ @@ -955,6 +1011,25 @@ mqnic_core_pcie_us #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_ENABLE(0), + .HBM_CH(HBM_CH), + .HBM_ENABLE(HBM_ENABLE), + .HBM_GROUP_SIZE(HBM_GROUP_SIZE), + .AXI_HBM_DATA_WIDTH(AXI_HBM_DATA_WIDTH), + .AXI_HBM_ADDR_WIDTH(AXI_HBM_ADDR_WIDTH), + .AXI_HBM_STRB_WIDTH(AXI_HBM_STRB_WIDTH), + .AXI_HBM_ID_WIDTH(AXI_HBM_ID_WIDTH), + .AXI_HBM_AWUSER_ENABLE(0), + .AXI_HBM_WUSER_ENABLE(0), + .AXI_HBM_BUSER_ENABLE(0), + .AXI_HBM_ARUSER_ENABLE(0), + .AXI_HBM_RUSER_ENABLE(0), + .AXI_HBM_MAX_BURST_LEN(AXI_HBM_MAX_BURST_LEN), + .AXI_HBM_NARROW_BURST(0), + .AXI_HBM_FIXED_BURST(0), + .AXI_HBM_WRAP_BURST(1), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1232,6 +1307,108 @@ core_inst ( .eth_rx_status(eth_rx_status), + /* + * DDR + */ + .ddr_clk(0), + .ddr_rst(0), + + .m_axi_ddr_awid(), + .m_axi_ddr_awaddr(), + .m_axi_ddr_awlen(), + .m_axi_ddr_awsize(), + .m_axi_ddr_awburst(), + .m_axi_ddr_awlock(), + .m_axi_ddr_awcache(), + .m_axi_ddr_awprot(), + .m_axi_ddr_awqos(), + .m_axi_ddr_awuser(), + .m_axi_ddr_awvalid(), + .m_axi_ddr_awready(0), + .m_axi_ddr_wdata(), + .m_axi_ddr_wstrb(), + .m_axi_ddr_wlast(), + .m_axi_ddr_wuser(), + .m_axi_ddr_wvalid(), + .m_axi_ddr_wready(0), + .m_axi_ddr_bid(0), + .m_axi_ddr_bresp(0), + .m_axi_ddr_buser(0), + .m_axi_ddr_bvalid(0), + .m_axi_ddr_bready(), + .m_axi_ddr_arid(), + .m_axi_ddr_araddr(), + .m_axi_ddr_arlen(), + .m_axi_ddr_arsize(), + .m_axi_ddr_arburst(), + .m_axi_ddr_arlock(), + .m_axi_ddr_arcache(), + .m_axi_ddr_arprot(), + .m_axi_ddr_arqos(), + .m_axi_ddr_aruser(), + .m_axi_ddr_arvalid(), + .m_axi_ddr_arready(0), + .m_axi_ddr_rid(0), + .m_axi_ddr_rdata(0), + .m_axi_ddr_rresp(0), + .m_axi_ddr_rlast(0), + .m_axi_ddr_ruser(0), + .m_axi_ddr_rvalid(0), + .m_axi_ddr_rready(), + + .ddr_status(0), + + /* + * HBM + */ + .hbm_clk(hbm_clk), + .hbm_rst(hbm_rst), + + .m_axi_hbm_awid(m_axi_hbm_awid), + .m_axi_hbm_awaddr(m_axi_hbm_awaddr), + .m_axi_hbm_awlen(m_axi_hbm_awlen), + .m_axi_hbm_awsize(m_axi_hbm_awsize), + .m_axi_hbm_awburst(m_axi_hbm_awburst), + .m_axi_hbm_awlock(m_axi_hbm_awlock), + .m_axi_hbm_awcache(m_axi_hbm_awcache), + .m_axi_hbm_awprot(m_axi_hbm_awprot), + .m_axi_hbm_awqos(m_axi_hbm_awqos), + .m_axi_hbm_awuser(), + .m_axi_hbm_awvalid(m_axi_hbm_awvalid), + .m_axi_hbm_awready(m_axi_hbm_awready), + .m_axi_hbm_wdata(m_axi_hbm_wdata), + .m_axi_hbm_wstrb(m_axi_hbm_wstrb), + .m_axi_hbm_wlast(m_axi_hbm_wlast), + .m_axi_hbm_wuser(), + .m_axi_hbm_wvalid(m_axi_hbm_wvalid), + .m_axi_hbm_wready(m_axi_hbm_wready), + .m_axi_hbm_bid(m_axi_hbm_bid), + .m_axi_hbm_bresp(m_axi_hbm_bresp), + .m_axi_hbm_buser(0), + .m_axi_hbm_bvalid(m_axi_hbm_bvalid), + .m_axi_hbm_bready(m_axi_hbm_bready), + .m_axi_hbm_arid(m_axi_hbm_arid), + .m_axi_hbm_araddr(m_axi_hbm_araddr), + .m_axi_hbm_arlen(m_axi_hbm_arlen), + .m_axi_hbm_arsize(m_axi_hbm_arsize), + .m_axi_hbm_arburst(m_axi_hbm_arburst), + .m_axi_hbm_arlock(m_axi_hbm_arlock), + .m_axi_hbm_arcache(m_axi_hbm_arcache), + .m_axi_hbm_arprot(m_axi_hbm_arprot), + .m_axi_hbm_arqos(m_axi_hbm_arqos), + .m_axi_hbm_aruser(), + .m_axi_hbm_arvalid(m_axi_hbm_arvalid), + .m_axi_hbm_arready(m_axi_hbm_arready), + .m_axi_hbm_rid(m_axi_hbm_rid), + .m_axi_hbm_rdata(m_axi_hbm_rdata), + .m_axi_hbm_rresp(m_axi_hbm_rresp), + .m_axi_hbm_rlast(m_axi_hbm_rlast), + .m_axi_hbm_ruser(0), + .m_axi_hbm_rvalid(m_axi_hbm_rvalid), + .m_axi_hbm_rready(m_axi_hbm_rready), + + .hbm_status(hbm_status), + /* * Statistics input */ diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v index b126f455e..e008a07f4 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/rtl/fpga_core.v @@ -812,6 +812,10 @@ mqnic_core_pcie_ptile #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_ENABLE(0), + .HBM_ENABLE(0), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1033,6 +1037,108 @@ core_inst ( .eth_rx_status(eth_rx_status), + /* + * DDR + */ + .ddr_clk(0), + .ddr_rst(0), + + .m_axi_ddr_awid(), + .m_axi_ddr_awaddr(), + .m_axi_ddr_awlen(), + .m_axi_ddr_awsize(), + .m_axi_ddr_awburst(), + .m_axi_ddr_awlock(), + .m_axi_ddr_awcache(), + .m_axi_ddr_awprot(), + .m_axi_ddr_awqos(), + .m_axi_ddr_awuser(), + .m_axi_ddr_awvalid(), + .m_axi_ddr_awready(0), + .m_axi_ddr_wdata(), + .m_axi_ddr_wstrb(), + .m_axi_ddr_wlast(), + .m_axi_ddr_wuser(), + .m_axi_ddr_wvalid(), + .m_axi_ddr_wready(0), + .m_axi_ddr_bid(0), + .m_axi_ddr_bresp(0), + .m_axi_ddr_buser(0), + .m_axi_ddr_bvalid(0), + .m_axi_ddr_bready(), + .m_axi_ddr_arid(), + .m_axi_ddr_araddr(), + .m_axi_ddr_arlen(), + .m_axi_ddr_arsize(), + .m_axi_ddr_arburst(), + .m_axi_ddr_arlock(), + .m_axi_ddr_arcache(), + .m_axi_ddr_arprot(), + .m_axi_ddr_arqos(), + .m_axi_ddr_aruser(), + .m_axi_ddr_arvalid(), + .m_axi_ddr_arready(0), + .m_axi_ddr_rid(0), + .m_axi_ddr_rdata(0), + .m_axi_ddr_rresp(0), + .m_axi_ddr_rlast(0), + .m_axi_ddr_ruser(0), + .m_axi_ddr_rvalid(0), + .m_axi_ddr_rready(), + + .ddr_status(0), + + /* + * HBM + */ + .hbm_clk(0), + .hbm_rst(0), + + .m_axi_hbm_awid(), + .m_axi_hbm_awaddr(), + .m_axi_hbm_awlen(), + .m_axi_hbm_awsize(), + .m_axi_hbm_awburst(), + .m_axi_hbm_awlock(), + .m_axi_hbm_awcache(), + .m_axi_hbm_awprot(), + .m_axi_hbm_awqos(), + .m_axi_hbm_awuser(), + .m_axi_hbm_awvalid(), + .m_axi_hbm_awready(0), + .m_axi_hbm_wdata(), + .m_axi_hbm_wstrb(), + .m_axi_hbm_wlast(), + .m_axi_hbm_wuser(), + .m_axi_hbm_wvalid(), + .m_axi_hbm_wready(0), + .m_axi_hbm_bid(0), + .m_axi_hbm_bresp(0), + .m_axi_hbm_buser(0), + .m_axi_hbm_bvalid(0), + .m_axi_hbm_bready(), + .m_axi_hbm_arid(), + .m_axi_hbm_araddr(), + .m_axi_hbm_arlen(), + .m_axi_hbm_arsize(), + .m_axi_hbm_arburst(), + .m_axi_hbm_arlock(), + .m_axi_hbm_arcache(), + .m_axi_hbm_arprot(), + .m_axi_hbm_arqos(), + .m_axi_hbm_aruser(), + .m_axi_hbm_arvalid(), + .m_axi_hbm_arready(0), + .m_axi_hbm_rid(0), + .m_axi_hbm_rdata(0), + .m_axi_hbm_rresp(0), + .m_axi_hbm_rlast(0), + .m_axi_hbm_ruser(0), + .m_axi_hbm_rvalid(0), + .m_axi_hbm_rready(), + + .hbm_status(0), + /* * Statistics input */ diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga_core.v index 01242d0c7..45abc2417 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/rtl/fpga_core.v @@ -1246,6 +1246,10 @@ mqnic_core_pcie_ptile #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_ENABLE(0), + .HBM_ENABLE(0), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1467,6 +1471,108 @@ core_inst ( .eth_rx_status(eth_rx_status), + /* + * DDR + */ + .ddr_clk(0), + .ddr_rst(0), + + .m_axi_ddr_awid(), + .m_axi_ddr_awaddr(), + .m_axi_ddr_awlen(), + .m_axi_ddr_awsize(), + .m_axi_ddr_awburst(), + .m_axi_ddr_awlock(), + .m_axi_ddr_awcache(), + .m_axi_ddr_awprot(), + .m_axi_ddr_awqos(), + .m_axi_ddr_awuser(), + .m_axi_ddr_awvalid(), + .m_axi_ddr_awready(0), + .m_axi_ddr_wdata(), + .m_axi_ddr_wstrb(), + .m_axi_ddr_wlast(), + .m_axi_ddr_wuser(), + .m_axi_ddr_wvalid(), + .m_axi_ddr_wready(0), + .m_axi_ddr_bid(0), + .m_axi_ddr_bresp(0), + .m_axi_ddr_buser(0), + .m_axi_ddr_bvalid(0), + .m_axi_ddr_bready(), + .m_axi_ddr_arid(), + .m_axi_ddr_araddr(), + .m_axi_ddr_arlen(), + .m_axi_ddr_arsize(), + .m_axi_ddr_arburst(), + .m_axi_ddr_arlock(), + .m_axi_ddr_arcache(), + .m_axi_ddr_arprot(), + .m_axi_ddr_arqos(), + .m_axi_ddr_aruser(), + .m_axi_ddr_arvalid(), + .m_axi_ddr_arready(0), + .m_axi_ddr_rid(0), + .m_axi_ddr_rdata(0), + .m_axi_ddr_rresp(0), + .m_axi_ddr_rlast(0), + .m_axi_ddr_ruser(0), + .m_axi_ddr_rvalid(0), + .m_axi_ddr_rready(), + + .ddr_status(0), + + /* + * HBM + */ + .hbm_clk(0), + .hbm_rst(0), + + .m_axi_hbm_awid(), + .m_axi_hbm_awaddr(), + .m_axi_hbm_awlen(), + .m_axi_hbm_awsize(), + .m_axi_hbm_awburst(), + .m_axi_hbm_awlock(), + .m_axi_hbm_awcache(), + .m_axi_hbm_awprot(), + .m_axi_hbm_awqos(), + .m_axi_hbm_awuser(), + .m_axi_hbm_awvalid(), + .m_axi_hbm_awready(0), + .m_axi_hbm_wdata(), + .m_axi_hbm_wstrb(), + .m_axi_hbm_wlast(), + .m_axi_hbm_wuser(), + .m_axi_hbm_wvalid(), + .m_axi_hbm_wready(0), + .m_axi_hbm_bid(0), + .m_axi_hbm_bresp(0), + .m_axi_hbm_buser(0), + .m_axi_hbm_bvalid(0), + .m_axi_hbm_bready(), + .m_axi_hbm_arid(), + .m_axi_hbm_araddr(), + .m_axi_hbm_arlen(), + .m_axi_hbm_arsize(), + .m_axi_hbm_arburst(), + .m_axi_hbm_arlock(), + .m_axi_hbm_arcache(), + .m_axi_hbm_arprot(), + .m_axi_hbm_arqos(), + .m_axi_hbm_aruser(), + .m_axi_hbm_arvalid(), + .m_axi_hbm_arready(0), + .m_axi_hbm_rid(0), + .m_axi_hbm_rdata(0), + .m_axi_hbm_rresp(0), + .m_axi_hbm_rlast(0), + .m_axi_hbm_ruser(0), + .m_axi_hbm_rvalid(0), + .m_axi_hbm_rready(), + + .hbm_status(0), + /* * Statistics input */ diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/README.md b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/README.md index c3c126de4..72298ffd5 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/README.md +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/README.md @@ -6,6 +6,7 @@ This design targets the Dini Group DNPCIe_40G_KU_LL_2QSFP FPGA board. * FPGA: xcku040-ffva1156-2-e * PHY: 10G BASE-R PHY IP core and internal GTH transceiver +* RAM: 4 GB DDR4 2400 (512M x72) ## How to build diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga.xdc b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga.xdc index 63b62dfe3..8745736d9 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga.xdc +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga.xdc @@ -315,150 +315,151 @@ set_false_path -from [get_ports {pcie_reset_n}] set_input_delay 0 [get_ports {pcie_reset_n}] # DDR4 -# U30 -#set_property -dict {LOC AD21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[0]}] ;# IO_L1P_T0L_N0_DBC_44 to U30.DM_DBI_n -#set_property -dict {LOC AF20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[0]}] ;# IO_L2P_T0L_N2_44 to U30.DQ[7:0] -#set_property -dict {LOC AG20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[1]}] ;# IO_L2N_T0L_N3_44 to U30.DQ[7:0] -#set_property -dict {LOC AD20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[2]}] ;# IO_L3P_T0L_N4_AD15P_44 to U30.DQ[7:0] -#set_property -dict {LOC AE20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[3]}] ;# IO_L3N_T0L_N5_AD15N_44 to U30.DQ[7:0] -#set_property -dict {LOC AG21 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr4_dqs_t[0]}] ;# IO_L4P_T0U_N6_DBC_AD7P_44 to U30.DQS_t -#set_property -dict {LOC AH21 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr4_dqs_c[0]}] ;# IO_L4N_T0U_N7_DBC_AD7N_44 to U30.DQS_c -#set_property -dict {LOC AE22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[4]}] ;# IO_L5P_T0U_N8_AD14P_44 to U30.DQ[7:0] -#set_property -dict {LOC AE23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[5]}] ;# IO_L5N_T0U_N9_AD14N_44 to U30.DQ[7:0] -#set_property -dict {LOC AF22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[6]}] ;# IO_L6P_T0U_N10_AD6P_44 to U30.DQ[7:0] -#set_property -dict {LOC AG22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[7]}] ;# IO_L6N_T0U_N11_AD6N_44 to U30.DQ[7:0] -# U31 -#set_property -dict {LOC AJ21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[1]}] ;# IO_L13P_T2L_N0_GC_QBC_44 to U31.DM_DBI_n -#set_property -dict {LOC AK22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[8]}] ;# IO_L14P_T2L_N2_GC_44 to U31.DQ[7:0] -#set_property -dict {LOC AK23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[9]}] ;# IO_L14N_T2L_N3_GC_44 to U31.DQ[7:0] -#set_property -dict {LOC AL20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[10]}] ;# IO_L15P_T2L_N4_AD11P_44 to U31.DQ[7:0] -#set_property -dict {LOC AM20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[11]}] ;# IO_L15N_T2L_N5_AD11N_44 to U31.DQ[7:0] -#set_property -dict {LOC AJ20 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr4_dqs_t[1]}] ;# IO_L16P_T2U_N6_QBC_AD3P_44 to U31.DQS_t -#set_property -dict {LOC AK20 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr4_dqs_c[1]}] ;# IO_L16N_T2U_N7_QBC_AD3N_44 to U31.DQS_c -#set_property -dict {LOC AL22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[12]}] ;# IO_L17P_T2U_N8_AD10P_44 to U31.DQ[7:0] -#set_property -dict {LOC AL23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[13]}] ;# IO_L17N_T2U_N9_AD10N_44 to U31.DQ[7:0] -#set_property -dict {LOC AL24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[14]}] ;# IO_L18P_T2U_N10_AD2P_44 to U31.DQ[7:0] -#set_property -dict {LOC AL25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[15]}] ;# IO_L18N_T2U_N11_AD2N_44 to U31.DQ[7:0] -# U32 -#set_property -dict {LOC AH26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[2]}] ;# IO_L1P_T0L_N0_DBC_46 to U32.DM_DBI_n -#set_property -dict {LOC AM26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[16]}] ;# IO_L2P_T0L_N2_46 to U32.DQ[7:0] -#set_property -dict {LOC AM27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[17]}] ;# IO_L2N_T0L_N3_46 to U32.DQ[7:0] -#set_property -dict {LOC AK26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[18]}] ;# IO_L3P_T0L_N4_AD15P_46 to U32.DQ[7:0] -#set_property -dict {LOC AK27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[19]}] ;# IO_L3N_T0L_N5_AD15N_46 to U32.DQ[7:0] -#set_property -dict {LOC AL27 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr4_dqs_t[2]}] ;# IO_L4P_T0U_N6_DBC_AD7P_46 to U32.DQS_t -#set_property -dict {LOC AL28 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr4_dqs_c[2]}] ;# IO_L4N_T0U_N7_DBC_AD7N_46 to U32.DQS_c -#set_property -dict {LOC AH27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[20]}] ;# IO_L5P_T0U_N8_AD14P_46 to U32.DQ[7:0] -#set_property -dict {LOC AH28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[21]}] ;# IO_L5N_T0U_N9_AD14N_46 to U32.DQ[7:0] -#set_property -dict {LOC AJ28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[22]}] ;# IO_L6P_T0U_N10_AD6P_46 to U32.DQ[7:0] -#set_property -dict {LOC AK28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[23]}] ;# IO_L6N_T0U_N11_AD6N_46 to U32.DQ[7:0] -# U33 -#set_property -dict {LOC AN26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[3]}] ;# IO_L7P_T1L_N0_QBC_AD13P_46 to U33.DM_DBI_n -#set_property -dict {LOC AP28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[24]}] ;# IO_L8P_T1L_N2_AD5P_46 to U33.DQ[7:0] -#set_property -dict {LOC AP29 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[25]}] ;# IO_L8N_T1L_N3_AD5N_46 to U33.DQ[7:0] -#set_property -dict {LOC AN27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[26]}] ;# IO_L9P_T1L_N4_AD12P_46 to U33.DQ[7:0] -#set_property -dict {LOC AN28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[27]}] ;# IO_L9N_T1L_N5_AD12N_46 to U33.DQ[7:0] -#set_property -dict {LOC AN29 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr4_dqs_t[3]}] ;# IO_L10P_T1U_N6_QBC_AD4P_46 to U33.DQS_t -#set_property -dict {LOC AP30 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr4_dqs_c[3]}] ;# IO_L10N_T1U_N7_QBC_AD4N_46 to U33.DQS_c -#set_property -dict {LOC AL29 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[28]}] ;# IO_L11P_T1U_N8_GC_46 to U33.DQ[7:0] -#set_property -dict {LOC AM29 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[29]}] ;# IO_L11N_T1U_N9_GC_46 to U33.DQ[7:0] -#set_property -dict {LOC AL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[30]}] ;# IO_L12P_T1U_N10_GC_46 to U33.DQ[7:0] -#set_property -dict {LOC AM30 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[31]}] ;# IO_L12N_T1U_N11_GC_46 to U33.DQ[7:0] -# U83 -#set_property -dict {LOC AN14 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[4]}] ;# IO_L1P_T0L_N0_DBC_45 to U83.DM_DBI_n -#set_property -dict {LOC AN19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[32]}] ;# IO_L2P_T0L_N2_45 to U83.DQ[7:0] -#set_property -dict {LOC AP18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[33]}] ;# IO_L2N_T0L_N3_45 to U83.DQ[7:0] -#set_property -dict {LOC AM17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[34]}] ;# IO_L3P_T0L_N4_AD15P_45 to U83.DQ[7:0] -#set_property -dict {LOC AN16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[35]}] ;# IO_L3N_T0L_N5_AD15N_45 to U83.DQ[7:0] -#set_property -dict {LOC AN18 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr4_dqs_t[4]}] ;# IO_L4P_T0U_N6_DBC_AD7P_45 to U83.DQS_t -#set_property -dict {LOC AN17 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr4_dqs_c[4]}] ;# IO_L4N_T0U_N7_DBC_AD7N_45 to U83.DQS_c -#set_property -dict {LOC AM16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[36]}] ;# IO_L5P_T0U_N8_AD14P_45 to U83.DQ[7:0] -#set_property -dict {LOC AM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[37]}] ;# IO_L5N_T0U_N9_AD14N_45 to U83.DQ[7:0] -#set_property -dict {LOC AP16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[38]}] ;# IO_L6P_T0U_N10_AD6P_45 to U83.DQ[7:0] -#set_property -dict {LOC AP15 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[39]}] ;# IO_L6N_T0U_N11_AD6N_45 to U83.DQ[7:0] -# U86 -#set_property -dict {LOC AM21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[5]}] ;# IO_L19P_T3L_N0_DBC_AD9P_44 to U86.DM_DBI_n -#set_property -dict {LOC AM22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[40]}] ;# IO_L20P_T3L_N2_AD1P_44 to U86.DQ[7:0] -#set_property -dict {LOC AN22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[41]}] ;# IO_L20N_T3L_N3_AD1N_44 to U86.DQ[7:0] -#set_property -dict {LOC AM24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[42]}] ;# IO_L21P_T3L_N4_AD8P_44 to U86.DQ[7:0] -#set_property -dict {LOC AN24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[43]}] ;# IO_L21N_T3L_N5_AD8N_44 to U86.DQ[7:0] -#set_property -dict {LOC AP20 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr4_dqs_t[5]}] ;# IO_L22P_T3U_N6_DBC_AD0P_44 to U86.DQS_t -#set_property -dict {LOC AP21 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr4_dqs_c[5]}] ;# IO_L22N_T3U_N7_DBC_AD0N_44 to U86.DQS_c -#set_property -dict {LOC AP24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[44]}] ;# IO_L23P_T3U_N8_44 to U86.DQ[7:0] -#set_property -dict {LOC AP25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[45]}] ;# IO_L23N_T3U_N9_44 to U86.DQ[7:0] -#set_property -dict {LOC AN23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[46]}] ;# IO_L24P_T3U_N10_44 to U86.DQ[7:0] -#set_property -dict {LOC AP23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[47]}] ;# IO_L24N_T3U_N11_44 to U86.DQ[7:0] -# U87 -#set_property -dict {LOC AE25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[6]}] ;# IO_L7P_T1L_N0_QBC_AD13P_44 to U87.DM_DBI_n -#set_property -dict {LOC AF23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[48]}] ;# IO_L8P_T1L_N2_AD5P_44 to U87.DQ[7:0] -#set_property -dict {LOC AF24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[49]}] ;# IO_L8N_T1L_N3_AD5N_44 to U87.DQ[7:0] -#set_property -dict {LOC AG24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[50]}] ;# IO_L9P_T1L_N4_AD12P_44 to U87.DQ[7:0] -#set_property -dict {LOC AG25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[51]}] ;# IO_L9N_T1L_N5_AD12N_44 to U87.DQ[7:0] -#set_property -dict {LOC AH24 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr4_dqs_t[6]}] ;# IO_L10P_T1U_N6_QBC_AD4P_44 to U87.DQS_t -#set_property -dict {LOC AJ25 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr4_dqs_c[6]}] ;# IO_L10N_T1U_N7_QBC_AD4N_44 to U87.DQS_c -#set_property -dict {LOC AJ23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[52]}] ;# IO_L11P_T1U_N8_GC_44 to U87.DQ[7:0] -#set_property -dict {LOC AJ24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[53]}] ;# IO_L11N_T1U_N9_GC_44 to U87.DQ[7:0] -#set_property -dict {LOC AH22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[54]}] ;# IO_L12P_T1U_N10_GC_44 to U87.DQ[7:0] -#set_property -dict {LOC AH23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[55]}] ;# IO_L12N_T1U_N11_GC_44 to U87.DQ[7:0] -# U88 -#set_property -dict {LOC AJ29 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[7]}] ;# IO_L13P_T2L_N0_GC_QBC_46 to U88.DM_DBI_n -#set_property -dict {LOC AK31 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[56]}] ;# IO_L14P_T2L_N2_GC_46 to U88.DQ[7:0] -#set_property -dict {LOC AK32 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[57]}] ;# IO_L14N_T2L_N3_GC_46 to U88.DQ[7:0] -#set_property -dict {LOC AJ30 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[58]}] ;# IO_L15P_T2L_N4_AD11P_46 to U88.DQ[7:0] -#set_property -dict {LOC AJ31 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[59]}] ;# IO_L15N_T2L_N5_AD11N_46 to U88.DQ[7:0] -#set_property -dict {LOC AH33 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr4_dqs_t[7]}] ;# IO_L16P_T2U_N6_QBC_AD3P_46 to U88.DQS_t -#set_property -dict {LOC AJ33 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr4_dqs_c[7]}] ;# IO_L16N_T2U_N7_QBC_AD3N_46 to U88.DQS_c -#set_property -dict {LOC AH31 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[60]}] ;# IO_L17P_T2U_N8_AD10P_46 to U88.DQ[7:0] -#set_property -dict {LOC AH32 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[61]}] ;# IO_L17N_T2U_N9_AD10N_46 to U88.DQ[7:0] -#set_property -dict {LOC AH34 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[62]}] ;# IO_L18P_T2U_N10_AD2P_46 to U88.DQ[7:0] -#set_property -dict {LOC AJ34 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[63]}] ;# IO_L18N_T2U_N11_AD2N_46 to U88.DQ[7:0] -# U89 -#set_property -dict {LOC AL32 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[8]}] ;# IO_L19P_T3L_N0_DBC_AD9P_46 to U89.DM_DBI_n -#set_property -dict {LOC AN33 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[64]}] ;# IO_L20P_T3L_N2_AD1P_46 to U89.DQ[7:0] -#set_property -dict {LOC AP33 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[65]}] ;# IO_L20N_T3L_N3_AD1N_46 to U89.DQ[7:0] -#set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[66]}] ;# IO_L21P_T3L_N4_AD8P_46 to U89.DQ[7:0] -#set_property -dict {LOC AP31 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[67]}] ;# IO_L21N_T3L_N5_AD8N_46 to U89.DQ[7:0] -#set_property -dict {LOC AN34 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr4_dqs_t[8]}] ;# IO_L22P_T3U_N6_DBC_AD0P_46 to U89.DQS_t -#set_property -dict {LOC AP34 IOSTANDARD DIFF_POD12_DCI} [get_ports {ddr4_dqs_c[8]}] ;# IO_L22N_T3U_N7_DBC_AD0N_46 to U89.DQS_c -#set_property -dict {LOC AM32 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[68]}] ;# IO_L23P_T3U_N8_46 to U89.DQ[7:0] -#set_property -dict {LOC AN32 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[69]}] ;# IO_L23N_T3U_N9_46 to U89.DQ[7:0] -#set_property -dict {LOC AL34 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[70]}] ;# IO_L24P_T3U_N10_46 to U89.DQ[7:0] -#set_property -dict {LOC AM34 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[71]}] ;# IO_L24N_T3U_N11_46 to U89.DQ[7:0] +# 9x MT40A512M8RH-083E # Control -#set_property -dict {LOC AG17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a[0]}] ;# IO_L15P_T2L_N4_AD11P_45 -#set_property -dict {LOC AH16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a[1]}] ;# IO_L14P_T2L_N2_GC_45 -#set_property -dict {LOC AF15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a[2]}] ;# IO_L20P_T3L_N2_AD1P_45 -#set_property -dict {LOC AJ16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a[3]}] ;# IO_L14N_T2L_N3_GC_45 -#set_property -dict {LOC AH19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a[4]}] ;# IO_L17N_T2U_N9_AD10N_45 -#set_property -dict {LOC AJ15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a[5]}] ;# IO_L16P_T2U_N6_QBC_AD3P_45 -#set_property -dict {LOC AE18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a[6]}] ;# IO_L21P_T3L_N4_AD8P_45 -#set_property -dict {LOC AG15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a[7]}] ;# IO_L18P_T2U_N10_AD2P_45 -#set_property -dict {LOC AD18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a[8]}] ;# IO_L19N_T3L_N1_DBC_AD9N_45 -#set_property -dict {LOC AF14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a[9]}] ;# IO_L20N_T3L_N3_AD1N_45 -#set_property -dict {LOC AJ18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a[10]}] ;# IO_L11P_T1U_N8_GC_45 -#set_property -dict {LOC AD19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a[11]}] ;# IO_L19P_T3L_N0_DBC_AD9P_45 -#set_property -dict {LOC AK16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a[12]}] ;# IO_L12N_T1U_N11_GC_45 -#set_property -dict {LOC AG16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a[13]}] ;# IO_L15N_T2L_N5_AD11N_45 -#set_property -dict {LOC AJ19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a[14]}] ;# IO_T1U_N12_45 -#set_property -dict {LOC AL17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a[15]}] ;# IO_L10N_T1U_N7_QBC_AD4N_45 -#set_property -dict {LOC AL14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a[16]}] ;# IO_L7P_T1L_N0_QBC_AD13P_45 -#set_property -dict {LOC AF18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_ba[0]}] ;# IO_L21N_T3L_N5_AD8N_45 -#set_property -dict {LOC AJ14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_ba[1]}] ;# IO_L16N_T2U_N7_QBC_AD3N_45 -#set_property -dict {LOC AG19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_bg[0]}] ;# IO_L17P_T2U_N8_AD10P_45 -#set_property -dict {LOC AK15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_bg[1]}] ;# IO_L9P_T1L_N4_AD12P_45 -#set_property -dict {LOC AE17 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_ck_t}] ;# IO_L23P_T3U_N8_45 -#set_property -dict {LOC AF17 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_ck_c}] ;# IO_L23N_T3U_N9_45 -#set_property -dict {LOC AL18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_cke}] ;# IO_L10P_T1U_N6_QBC_AD4P_45 -#set_property -dict {LOC AK17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_act_n}] ;# IO_L12P_T1U_N10_GC_45 -#set_property -dict {LOC AE16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_par}] ;# IO_L22P_T3U_N6_DBC_AD0P_45 -#set_property -dict {LOC AM19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_odt}] ;# IO_L8N_T1L_N3_AD5N_45 -#set_property -dict {LOC AL15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_cs_n}] ;# IO_L9N_T1L_N5_AD12N_45 -#set_property -dict {LOC AD14 IOSTANDARD LVCMOS12 } [get_ports {ddr4_ten}] ;# IO_T3U_N12_45 -#set_property -dict {LOC AD15 IOSTANDARD LVCMOS12 } [get_ports {ddr4_alert_n}] ;# IO_L24N_T3U_N11_45 -#set_property -dict {LOC AD16 IOSTANDARD LVCMOS12 } [get_ports {ddr4_reset_n}] ;# IO_L24P_T3U_N10_45 +set_property -dict {LOC AG17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[0]}] ;# IO_L15P_T2L_N4_AD11P_45 +set_property -dict {LOC AH16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[1]}] ;# IO_L14P_T2L_N2_GC_45 +set_property -dict {LOC AF15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[2]}] ;# IO_L20P_T3L_N2_AD1P_45 +set_property -dict {LOC AJ16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[3]}] ;# IO_L14N_T2L_N3_GC_45 +set_property -dict {LOC AH19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[4]}] ;# IO_L17N_T2U_N9_AD10N_45 +set_property -dict {LOC AJ15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[5]}] ;# IO_L16P_T2U_N6_QBC_AD3P_45 +set_property -dict {LOC AE18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[6]}] ;# IO_L21P_T3L_N4_AD8P_45 +set_property -dict {LOC AG15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[7]}] ;# IO_L18P_T2U_N10_AD2P_45 +set_property -dict {LOC AD18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[8]}] ;# IO_L19N_T3L_N1_DBC_AD9N_45 +set_property -dict {LOC AF14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[9]}] ;# IO_L20N_T3L_N3_AD1N_45 +set_property -dict {LOC AJ18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[10]}] ;# IO_L11P_T1U_N8_GC_45 +set_property -dict {LOC AD19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[11]}] ;# IO_L19P_T3L_N0_DBC_AD9P_45 +set_property -dict {LOC AK16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[12]}] ;# IO_L12N_T1U_N11_GC_45 +set_property -dict {LOC AG16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[13]}] ;# IO_L15N_T2L_N5_AD11N_45 +set_property -dict {LOC AJ19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[14]}] ;# IO_T1U_N12_45 +set_property -dict {LOC AL17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[15]}] ;# IO_L10N_T1U_N7_QBC_AD4N_45 +set_property -dict {LOC AL14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[16]}] ;# IO_L7P_T1L_N0_QBC_AD13P_45 +set_property -dict {LOC AF18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_ba[0]}] ;# IO_L21N_T3L_N5_AD8N_45 +set_property -dict {LOC AJ14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_ba[1]}] ;# IO_L16N_T2U_N7_QBC_AD3N_45 +set_property -dict {LOC AG19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_bg[0]}] ;# IO_L17P_T2U_N8_AD10P_45 +set_property -dict {LOC AK15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_bg[1]}] ;# IO_L9P_T1L_N4_AD12P_45 +set_property -dict {LOC AE17 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_ck_t}] ;# IO_L23P_T3U_N8_45 +set_property -dict {LOC AF17 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_ck_c}] ;# IO_L23N_T3U_N9_45 +set_property -dict {LOC AL18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_cke}] ;# IO_L10P_T1U_N6_QBC_AD4P_45 +set_property -dict {LOC AL15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_cs_n}] ;# IO_L9N_T1L_N5_AD12N_45 +set_property -dict {LOC AK17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_act_n}] ;# IO_L12P_T1U_N10_GC_45 +set_property -dict {LOC AM19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_odt}] ;# IO_L8N_T1L_N3_AD5N_45 +set_property -dict {LOC AE16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_par}] ;# IO_L22P_T3U_N6_DBC_AD0P_45 +set_property -dict {LOC AD16 IOSTANDARD LVCMOS12 } [get_ports {ddr4_reset_n}] ;# IO_L24P_T3U_N10_45 +set_property -dict {LOC AD15 IOSTANDARD LVCMOS12 } [get_ports {ddr4_alert_n}] ;# IO_L24N_T3U_N11_45 +set_property -dict {LOC AD14 IOSTANDARD LVCMOS12 } [get_ports {ddr4_ten}] ;# IO_T3U_N12_45 +# U30 +set_property -dict {LOC AD21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[0]}] ;# IO_L1P_T0L_N0_DBC_44 to U30.DM_DBI_n +set_property -dict {LOC AF20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[0]}] ;# IO_L2P_T0L_N2_44 to U30.DQ[7:0] +set_property -dict {LOC AG20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[1]}] ;# IO_L2N_T0L_N3_44 to U30.DQ[7:0] +set_property -dict {LOC AD20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[2]}] ;# IO_L3P_T0L_N4_AD15P_44 to U30.DQ[7:0] +set_property -dict {LOC AE20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[3]}] ;# IO_L3N_T0L_N5_AD15N_44 to U30.DQ[7:0] +set_property -dict {LOC AG21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[0]}] ;# IO_L4P_T0U_N6_DBC_AD7P_44 to U30.DQS_t +set_property -dict {LOC AH21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[0]}] ;# IO_L4N_T0U_N7_DBC_AD7N_44 to U30.DQS_c +set_property -dict {LOC AE22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[4]}] ;# IO_L5P_T0U_N8_AD14P_44 to U30.DQ[7:0] +set_property -dict {LOC AE23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[5]}] ;# IO_L5N_T0U_N9_AD14N_44 to U30.DQ[7:0] +set_property -dict {LOC AF22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[6]}] ;# IO_L6P_T0U_N10_AD6P_44 to U30.DQ[7:0] +set_property -dict {LOC AG22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[7]}] ;# IO_L6N_T0U_N11_AD6N_44 to U30.DQ[7:0] +# U31 +set_property -dict {LOC AJ21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[1]}] ;# IO_L13P_T2L_N0_GC_QBC_44 to U31.DM_DBI_n +set_property -dict {LOC AK22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[8]}] ;# IO_L14P_T2L_N2_GC_44 to U31.DQ[7:0] +set_property -dict {LOC AK23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[9]}] ;# IO_L14N_T2L_N3_GC_44 to U31.DQ[7:0] +set_property -dict {LOC AL20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[10]}] ;# IO_L15P_T2L_N4_AD11P_44 to U31.DQ[7:0] +set_property -dict {LOC AM20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[11]}] ;# IO_L15N_T2L_N5_AD11N_44 to U31.DQ[7:0] +set_property -dict {LOC AJ20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[1]}] ;# IO_L16P_T2U_N6_QBC_AD3P_44 to U31.DQS_t +set_property -dict {LOC AK20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[1]}] ;# IO_L16N_T2U_N7_QBC_AD3N_44 to U31.DQS_c +set_property -dict {LOC AL22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[12]}] ;# IO_L17P_T2U_N8_AD10P_44 to U31.DQ[7:0] +set_property -dict {LOC AL23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[13]}] ;# IO_L17N_T2U_N9_AD10N_44 to U31.DQ[7:0] +set_property -dict {LOC AL24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[14]}] ;# IO_L18P_T2U_N10_AD2P_44 to U31.DQ[7:0] +set_property -dict {LOC AL25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[15]}] ;# IO_L18N_T2U_N11_AD2N_44 to U31.DQ[7:0] +# U32 +set_property -dict {LOC AH26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[2]}] ;# IO_L1P_T0L_N0_DBC_46 to U32.DM_DBI_n +set_property -dict {LOC AM26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[16]}] ;# IO_L2P_T0L_N2_46 to U32.DQ[7:0] +set_property -dict {LOC AM27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[17]}] ;# IO_L2N_T0L_N3_46 to U32.DQ[7:0] +set_property -dict {LOC AK26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[18]}] ;# IO_L3P_T0L_N4_AD15P_46 to U32.DQ[7:0] +set_property -dict {LOC AK27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[19]}] ;# IO_L3N_T0L_N5_AD15N_46 to U32.DQ[7:0] +set_property -dict {LOC AL27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[2]}] ;# IO_L4P_T0U_N6_DBC_AD7P_46 to U32.DQS_t +set_property -dict {LOC AL28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[2]}] ;# IO_L4N_T0U_N7_DBC_AD7N_46 to U32.DQS_c +set_property -dict {LOC AH27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[20]}] ;# IO_L5P_T0U_N8_AD14P_46 to U32.DQ[7:0] +set_property -dict {LOC AH28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[21]}] ;# IO_L5N_T0U_N9_AD14N_46 to U32.DQ[7:0] +set_property -dict {LOC AJ28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[22]}] ;# IO_L6P_T0U_N10_AD6P_46 to U32.DQ[7:0] +set_property -dict {LOC AK28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[23]}] ;# IO_L6N_T0U_N11_AD6N_46 to U32.DQ[7:0] +# U33 +set_property -dict {LOC AN26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[3]}] ;# IO_L7P_T1L_N0_QBC_AD13P_46 to U33.DM_DBI_n +set_property -dict {LOC AP28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[24]}] ;# IO_L8P_T1L_N2_AD5P_46 to U33.DQ[7:0] +set_property -dict {LOC AP29 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[25]}] ;# IO_L8N_T1L_N3_AD5N_46 to U33.DQ[7:0] +set_property -dict {LOC AN27 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[26]}] ;# IO_L9P_T1L_N4_AD12P_46 to U33.DQ[7:0] +set_property -dict {LOC AN28 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[27]}] ;# IO_L9N_T1L_N5_AD12N_46 to U33.DQ[7:0] +set_property -dict {LOC AN29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[3]}] ;# IO_L10P_T1U_N6_QBC_AD4P_46 to U33.DQS_t +set_property -dict {LOC AP30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[3]}] ;# IO_L10N_T1U_N7_QBC_AD4N_46 to U33.DQS_c +set_property -dict {LOC AL29 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[28]}] ;# IO_L11P_T1U_N8_GC_46 to U33.DQ[7:0] +set_property -dict {LOC AM29 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[29]}] ;# IO_L11N_T1U_N9_GC_46 to U33.DQ[7:0] +set_property -dict {LOC AL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[30]}] ;# IO_L12P_T1U_N10_GC_46 to U33.DQ[7:0] +set_property -dict {LOC AM30 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[31]}] ;# IO_L12N_T1U_N11_GC_46 to U33.DQ[7:0] +# U83 +set_property -dict {LOC AN14 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[4]}] ;# IO_L1P_T0L_N0_DBC_45 to U83.DM_DBI_n +set_property -dict {LOC AN19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[32]}] ;# IO_L2P_T0L_N2_45 to U83.DQ[7:0] +set_property -dict {LOC AP18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[33]}] ;# IO_L2N_T0L_N3_45 to U83.DQ[7:0] +set_property -dict {LOC AM17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[34]}] ;# IO_L3P_T0L_N4_AD15P_45 to U83.DQ[7:0] +set_property -dict {LOC AN16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[35]}] ;# IO_L3N_T0L_N5_AD15N_45 to U83.DQ[7:0] +set_property -dict {LOC AN18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[4]}] ;# IO_L4P_T0U_N6_DBC_AD7P_45 to U83.DQS_t +set_property -dict {LOC AN17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[4]}] ;# IO_L4N_T0U_N7_DBC_AD7N_45 to U83.DQS_c +set_property -dict {LOC AM16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[36]}] ;# IO_L5P_T0U_N8_AD14P_45 to U83.DQ[7:0] +set_property -dict {LOC AM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[37]}] ;# IO_L5N_T0U_N9_AD14N_45 to U83.DQ[7:0] +set_property -dict {LOC AP16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[38]}] ;# IO_L6P_T0U_N10_AD6P_45 to U83.DQ[7:0] +set_property -dict {LOC AP15 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[39]}] ;# IO_L6N_T0U_N11_AD6N_45 to U83.DQ[7:0] +# U86 +set_property -dict {LOC AM21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[5]}] ;# IO_L19P_T3L_N0_DBC_AD9P_44 to U86.DM_DBI_n +set_property -dict {LOC AM22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[40]}] ;# IO_L20P_T3L_N2_AD1P_44 to U86.DQ[7:0] +set_property -dict {LOC AN22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[41]}] ;# IO_L20N_T3L_N3_AD1N_44 to U86.DQ[7:0] +set_property -dict {LOC AM24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[42]}] ;# IO_L21P_T3L_N4_AD8P_44 to U86.DQ[7:0] +set_property -dict {LOC AN24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[43]}] ;# IO_L21N_T3L_N5_AD8N_44 to U86.DQ[7:0] +set_property -dict {LOC AP20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[5]}] ;# IO_L22P_T3U_N6_DBC_AD0P_44 to U86.DQS_t +set_property -dict {LOC AP21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[5]}] ;# IO_L22N_T3U_N7_DBC_AD0N_44 to U86.DQS_c +set_property -dict {LOC AP24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[44]}] ;# IO_L23P_T3U_N8_44 to U86.DQ[7:0] +set_property -dict {LOC AP25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[45]}] ;# IO_L23N_T3U_N9_44 to U86.DQ[7:0] +set_property -dict {LOC AN23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[46]}] ;# IO_L24P_T3U_N10_44 to U86.DQ[7:0] +set_property -dict {LOC AP23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[47]}] ;# IO_L24N_T3U_N11_44 to U86.DQ[7:0] +# U87 +set_property -dict {LOC AE25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[6]}] ;# IO_L7P_T1L_N0_QBC_AD13P_44 to U87.DM_DBI_n +set_property -dict {LOC AF23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[48]}] ;# IO_L8P_T1L_N2_AD5P_44 to U87.DQ[7:0] +set_property -dict {LOC AF24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[49]}] ;# IO_L8N_T1L_N3_AD5N_44 to U87.DQ[7:0] +set_property -dict {LOC AG24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[50]}] ;# IO_L9P_T1L_N4_AD12P_44 to U87.DQ[7:0] +set_property -dict {LOC AG25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[51]}] ;# IO_L9N_T1L_N5_AD12N_44 to U87.DQ[7:0] +set_property -dict {LOC AH24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[6]}] ;# IO_L10P_T1U_N6_QBC_AD4P_44 to U87.DQS_t +set_property -dict {LOC AJ25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[6]}] ;# IO_L10N_T1U_N7_QBC_AD4N_44 to U87.DQS_c +set_property -dict {LOC AJ23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[52]}] ;# IO_L11P_T1U_N8_GC_44 to U87.DQ[7:0] +set_property -dict {LOC AJ24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[53]}] ;# IO_L11N_T1U_N9_GC_44 to U87.DQ[7:0] +set_property -dict {LOC AH22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[54]}] ;# IO_L12P_T1U_N10_GC_44 to U87.DQ[7:0] +set_property -dict {LOC AH23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[55]}] ;# IO_L12N_T1U_N11_GC_44 to U87.DQ[7:0] +# U88 +set_property -dict {LOC AJ29 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[7]}] ;# IO_L13P_T2L_N0_GC_QBC_46 to U88.DM_DBI_n +set_property -dict {LOC AK31 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[56]}] ;# IO_L14P_T2L_N2_GC_46 to U88.DQ[7:0] +set_property -dict {LOC AK32 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[57]}] ;# IO_L14N_T2L_N3_GC_46 to U88.DQ[7:0] +set_property -dict {LOC AJ30 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[58]}] ;# IO_L15P_T2L_N4_AD11P_46 to U88.DQ[7:0] +set_property -dict {LOC AJ31 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[59]}] ;# IO_L15N_T2L_N5_AD11N_46 to U88.DQ[7:0] +set_property -dict {LOC AH33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[7]}] ;# IO_L16P_T2U_N6_QBC_AD3P_46 to U88.DQS_t +set_property -dict {LOC AJ33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[7]}] ;# IO_L16N_T2U_N7_QBC_AD3N_46 to U88.DQS_c +set_property -dict {LOC AH31 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[60]}] ;# IO_L17P_T2U_N8_AD10P_46 to U88.DQ[7:0] +set_property -dict {LOC AH32 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[61]}] ;# IO_L17N_T2U_N9_AD10N_46 to U88.DQ[7:0] +set_property -dict {LOC AH34 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[62]}] ;# IO_L18P_T2U_N10_AD2P_46 to U88.DQ[7:0] +set_property -dict {LOC AJ34 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[63]}] ;# IO_L18N_T2U_N11_AD2N_46 to U88.DQ[7:0] +# U89 +set_property -dict {LOC AL32 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[8]}] ;# IO_L19P_T3L_N0_DBC_AD9P_46 to U89.DM_DBI_n +set_property -dict {LOC AN33 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[64]}] ;# IO_L20P_T3L_N2_AD1P_46 to U89.DQ[7:0] +set_property -dict {LOC AP33 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[65]}] ;# IO_L20N_T3L_N3_AD1N_46 to U89.DQ[7:0] +set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[66]}] ;# IO_L21P_T3L_N4_AD8P_46 to U89.DQ[7:0] +set_property -dict {LOC AP31 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[67]}] ;# IO_L21N_T3L_N5_AD8N_46 to U89.DQ[7:0] +set_property -dict {LOC AN34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[8]}] ;# IO_L22P_T3U_N6_DBC_AD0P_46 to U89.DQS_t +set_property -dict {LOC AP34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[8]}] ;# IO_L22N_T3U_N7_DBC_AD0N_46 to U89.DQS_c +set_property -dict {LOC AM32 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[68]}] ;# IO_L23P_T3U_N8_46 to U89.DQ[7:0] +set_property -dict {LOC AN32 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[69]}] ;# IO_L23N_T3U_N9_46 to U89.DQ[7:0] +set_property -dict {LOC AL34 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[70]}] ;# IO_L24P_T3U_N10_46 to U89.DQ[7:0] +set_property -dict {LOC AM34 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[71]}] ;# IO_L24N_T3U_N11_46 to U89.DQ[7:0] # 200 MHz DDR4 clock (Si598 FCA000126G) (Y6) -#set_property -dict {LOC AH18 IOSTANDARD LVDS} [get_ports clk_ddr4_p] ;# from Y6.4 -#set_property -dict {LOC AH17 IOSTANDARD LVDS} [get_ports clk_ddr4_n] ;# from Y6.5 +set_property -dict {LOC AH18 IOSTANDARD LVDS} [get_ports clk_ddr4_p] ;# from Y6.4 +set_property -dict {LOC AH17 IOSTANDARD LVDS} [get_ports clk_ddr4_n] ;# from Y6.5 #create_clock -period 5.000 -name clk_ddr4 [get_ports clk_ddr4_p] #set_property -dict {LOC AG12 IOSTANDARD LVCMOS25 SLEW SLOW DRIVE 12 PULLUP true} [get_ports clk_ddr4_i2c_scl] diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile index 69fc05d9d..42219130f 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile @@ -137,6 +137,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie3_ultrascale_0.tcl IP_TCL_FILES += ip/eth_xcvr_gth.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl index e192b94b0..9b573de3e 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/config.tcl @@ -139,6 +139,12 @@ dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" dict set params RX_RAM_SIZE "32768" + +# RAM configuration +dict set params DDR_CH "1" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" # Application block configuration dict set params APP_ID "32'h00000000" @@ -190,6 +196,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "10" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie3_ultrascale_0] diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile index 3a334eb71..dbc8591f7 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile @@ -137,6 +137,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie3_ultrascale_0.tcl IP_TCL_FILES += ip/eth_xcvr_gth.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl index bae242832..195c136c3 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/config.tcl @@ -139,6 +139,12 @@ dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" dict set params RX_RAM_SIZE "32768" + +# RAM configuration +dict set params DDR_CH "1" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" # Application block configuration dict set params APP_ID "32'h00000000" @@ -190,6 +196,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "10" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie3_ultrascale_0] diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/ip/ddr4_0.tcl b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/ip/ddr4_0.tcl new file mode 100644 index 000000000..484797d5c --- /dev/null +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/ip/ddr4_0.tcl @@ -0,0 +1,19 @@ + +create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 + +set_property -dict [list \ + CONFIG.C0.DDR4_AxiSelection {true} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_AxiIDWidth {8} \ + CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ + CONFIG.C0.DDR4_TimePeriod {833} \ + CONFIG.C0.DDR4_InputClockPeriod {4998} \ + CONFIG.C0.DDR4_MemoryType {Components} \ + CONFIG.C0.DDR4_MemoryPart {MT40A512M8HX-083} \ + CONFIG.C0.DDR4_DataWidth {72} \ + CONFIG.C0.DDR4_DataMask {NO_DM_NO_DBI} \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_CasLatency {16} \ + CONFIG.C0.DDR4_CasWriteLatency {12} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} +] [get_ips ddr4_0] diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v index 456cbf8f5..5554a5d02 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v @@ -112,6 +112,15 @@ module fpga # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // RAM configuration + parameter DDR_CH = 1, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 32, + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -177,6 +186,12 @@ module fpga # parameter STAT_ID_WIDTH = 12 ) ( + /* + * Clock + */ + input wire clk_ddr4_p, + input wire clk_ddr4_n, + /* * GPIO */ @@ -260,6 +275,27 @@ module fpga # inout wire eeprom_i2c_scl, inout wire eeprom_i2c_sda, + /* + * DDR4 + */ + output wire [16:0] ddr4_adr, + output wire [1:0] ddr4_ba, + output wire [1:0] ddr4_bg, + output wire ddr4_ck_t, + output wire ddr4_ck_c, + output wire ddr4_cke, + output wire ddr4_cs_n, + output wire ddr4_act_n, + output wire ddr4_odt, + output wire ddr4_par, + input wire ddr4_alert_n, + output wire ddr4_reset_n, + output wire ddr4_ten, + inout wire [71:0] ddr4_dq, + inout wire [8:0] ddr4_dqs_t, + inout wire [8:0] ddr4_dqs_c, + inout wire [8:0] ddr4_dm_dbi_n, + /* * BPI Flash */ @@ -282,6 +318,9 @@ parameter IF_PTP_PERIOD_FNS = 16'h6666; // Interface configuration parameter TX_TAG_WIDTH = 16; +// RAM configuration +parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8); + // Ethernet interface configuration parameter XGMII_DATA_WIDTH = 64; parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8; @@ -1340,6 +1379,186 @@ assign user_led[2] = qsfp0_rx_status_3; assign user_led[3] = qsfp0_rx_status_4; assign user_led[7:4] = user_led_int[7:4]; +// DDR4 +wire [DDR_CH-1:0] ddr_clk; +wire [DDR_CH-1:0] ddr_rst; + +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr; +wire [DDR_CH*8-1:0] m_axi_ddr_awlen; +wire [DDR_CH*3-1:0] m_axi_ddr_awsize; +wire [DDR_CH*2-1:0] m_axi_ddr_awburst; +wire [DDR_CH-1:0] m_axi_ddr_awlock; +wire [DDR_CH*4-1:0] m_axi_ddr_awcache; +wire [DDR_CH*3-1:0] m_axi_ddr_awprot; +wire [DDR_CH*4-1:0] m_axi_ddr_awqos; +wire [DDR_CH-1:0] m_axi_ddr_awvalid; +wire [DDR_CH-1:0] m_axi_ddr_awready; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata; +wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb; +wire [DDR_CH-1:0] m_axi_ddr_wlast; +wire [DDR_CH-1:0] m_axi_ddr_wvalid; +wire [DDR_CH-1:0] m_axi_ddr_wready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid; +wire [DDR_CH*2-1:0] m_axi_ddr_bresp; +wire [DDR_CH-1:0] m_axi_ddr_bvalid; +wire [DDR_CH-1:0] m_axi_ddr_bready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr; +wire [DDR_CH*8-1:0] m_axi_ddr_arlen; +wire [DDR_CH*3-1:0] m_axi_ddr_arsize; +wire [DDR_CH*2-1:0] m_axi_ddr_arburst; +wire [DDR_CH-1:0] m_axi_ddr_arlock; +wire [DDR_CH*4-1:0] m_axi_ddr_arcache; +wire [DDR_CH*3-1:0] m_axi_ddr_arprot; +wire [DDR_CH*4-1:0] m_axi_ddr_arqos; +wire [DDR_CH-1:0] m_axi_ddr_arvalid; +wire [DDR_CH-1:0] m_axi_ddr_arready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata; +wire [DDR_CH*2-1:0] m_axi_ddr_rresp; +wire [DDR_CH-1:0] m_axi_ddr_rlast; +wire [DDR_CH-1:0] m_axi_ddr_rvalid; +wire [DDR_CH-1:0] m_axi_ddr_rready; + +wire [DDR_CH-1:0] ddr_status; + +generate + +if (DDR_ENABLE && DDR_CH > 0) begin + +ddr4_0 ddr4_inst ( + .c0_sys_clk_p(clk_ddr4_p), + .c0_sys_clk_n(clk_ddr4_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[0 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_adr), + .c0_ddr4_ba(ddr4_ba), + .c0_ddr4_cke(ddr4_cke), + .c0_ddr4_cs_n(ddr4_cs_n), + .c0_ddr4_dq(ddr4_dq), + .c0_ddr4_dqs_t(ddr4_dqs_t), + .c0_ddr4_dqs_c(ddr4_dqs_c), + .c0_ddr4_dm_dbi_n(ddr4_dm_dbi_n), + .c0_ddr4_odt(ddr4_odt), + .c0_ddr4_bg(ddr4_bg), + .c0_ddr4_reset_n(ddr4_reset_n), + .c0_ddr4_act_n(ddr4_act_n), + .c0_ddr4_ck_t(ddr4_ck_t), + .c0_ddr4_ck_c(ddr4_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[0 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[0 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_adr = {17{1'bz}}; +assign ddr4_ba = {2{1'bz}}; +assign ddr4_bg = {1{1'bz}}; +assign ddr4_cke = 1'bz; +assign ddr4_cs_n = 1'bz; +assign ddr4_act_n = 1'bz; +assign ddr4_odt = 1'bz; +assign ddr4_reset_n = 1'b0; +assign ddr4_dq = {72{1'bz}}; +assign ddr4_dqs_t = {9{1'bz}}; +assign ddr4_dqs_c = {9{1'bz}}; +assign ddr4_dm_dbi_n = {9{1'bz}}; + +OBUFTDS ddr4_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_ck_t), + .OB(ddr4_ck_c) +); + +assign ddr_clk = 0; +assign ddr_rst = 0; + +assign m_axi_ddr_awready = 0; +assign m_axi_ddr_wready = 0; +assign m_axi_ddr_bid = 0; +assign m_axi_ddr_bresp = 0; +assign m_axi_ddr_bvalid = 0; +assign m_axi_ddr_arready = 0; +assign m_axi_ddr_rid = 0; +assign m_axi_ddr_rdata = 0; +assign m_axi_ddr_rresp = 0; +assign m_axi_ddr_rlast = 0; +assign m_axi_ddr_rvalid = 0; + +assign ddr_status = 0; + +end + +assign ddr4_par = 1'b0; +assign ddr4_ten = 1'b0; + +endgenerate + fpga_core #( // FW and board IDs .FPGA_ID(FPGA_ID), @@ -1416,6 +1635,16 @@ fpga_core #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1733,6 +1962,52 @@ core_inst ( .eeprom_i2c_sda_o(eeprom_i2c_sda_o), .eeprom_i2c_sda_t(eeprom_i2c_sda_t), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + /* * BPI flash */ diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v index ba09e3678..09a0734b2 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v @@ -122,6 +122,16 @@ module fpga_core # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // RAM configuration + parameter DDR_CH = 1, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 32, + parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -441,6 +451,52 @@ module fpga_core # output wire eeprom_i2c_sda_o, output wire eeprom_i2c_sda_t, + /* + * DDR + */ + input wire [DDR_CH-1:0] ddr_clk, + input wire [DDR_CH-1:0] ddr_rst, + + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, + output wire [DDR_CH-1:0] m_axi_ddr_awlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, + output wire [DDR_CH-1:0] m_axi_ddr_awvalid, + input wire [DDR_CH-1:0] m_axi_ddr_awready, + output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, + output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, + output wire [DDR_CH-1:0] m_axi_ddr_wlast, + output wire [DDR_CH-1:0] m_axi_ddr_wvalid, + input wire [DDR_CH-1:0] m_axi_ddr_wready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, + input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, + input wire [DDR_CH-1:0] m_axi_ddr_bvalid, + output wire [DDR_CH-1:0] m_axi_ddr_bready, + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, + output wire [DDR_CH-1:0] m_axi_ddr_arlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, + output wire [DDR_CH-1:0] m_axi_ddr_arvalid, + input wire [DDR_CH-1:0] m_axi_ddr_arready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, + input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, + input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, + input wire [DDR_CH-1:0] m_axi_ddr_rlast, + input wire [DDR_CH-1:0] m_axi_ddr_rvalid, + output wire [DDR_CH-1:0] m_axi_ddr_rready, + + input wire [DDR_CH-1:0] ddr_status, + /* * BPI Flash */ @@ -1189,6 +1245,25 @@ mqnic_core_pcie_us #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .DDR_GROUP_SIZE(1), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_AWUSER_ENABLE(0), + .AXI_DDR_WUSER_ENABLE(0), + .AXI_DDR_BUSER_ENABLE(0), + .AXI_DDR_ARUSER_ENABLE(0), + .AXI_DDR_RUSER_ENABLE(0), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + .AXI_DDR_FIXED_BURST(0), + .AXI_DDR_WRAP_BURST(1), + .HBM_ENABLE(0), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1466,6 +1541,108 @@ core_inst ( .eth_rx_status(eth_rx_status), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awuser(), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wuser(), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_buser(0), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_aruser(), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_ruser(0), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + + /* + * HBM + */ + .hbm_clk(0), + .hbm_rst(0), + + .m_axi_hbm_awid(), + .m_axi_hbm_awaddr(), + .m_axi_hbm_awlen(), + .m_axi_hbm_awsize(), + .m_axi_hbm_awburst(), + .m_axi_hbm_awlock(), + .m_axi_hbm_awcache(), + .m_axi_hbm_awprot(), + .m_axi_hbm_awqos(), + .m_axi_hbm_awuser(), + .m_axi_hbm_awvalid(), + .m_axi_hbm_awready(0), + .m_axi_hbm_wdata(), + .m_axi_hbm_wstrb(), + .m_axi_hbm_wlast(), + .m_axi_hbm_wuser(), + .m_axi_hbm_wvalid(), + .m_axi_hbm_wready(0), + .m_axi_hbm_bid(0), + .m_axi_hbm_bresp(0), + .m_axi_hbm_buser(0), + .m_axi_hbm_bvalid(0), + .m_axi_hbm_bready(), + .m_axi_hbm_arid(), + .m_axi_hbm_araddr(), + .m_axi_hbm_arlen(), + .m_axi_hbm_arsize(), + .m_axi_hbm_arburst(), + .m_axi_hbm_arlock(), + .m_axi_hbm_arcache(), + .m_axi_hbm_arprot(), + .m_axi_hbm_arqos(), + .m_axi_hbm_aruser(), + .m_axi_hbm_arvalid(), + .m_axi_hbm_arready(0), + .m_axi_hbm_rid(0), + .m_axi_hbm_rdata(0), + .m_axi_hbm_rresp(0), + .m_axi_hbm_rlast(0), + .m_axi_hbm_ruser(0), + .m_axi_hbm_rvalid(0), + .m_axi_hbm_rready(), + + .hbm_status(0), + /* * Statistics input */ diff --git a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v index 00179feeb..09f294605 100644 --- a/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v @@ -791,6 +791,10 @@ mqnic_core_pcie_us #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_ENABLE(0), + .HBM_ENABLE(0), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1068,6 +1072,108 @@ core_inst ( .eth_rx_status(eth_rx_status), + /* + * DDR + */ + .ddr_clk(0), + .ddr_rst(0), + + .m_axi_ddr_awid(), + .m_axi_ddr_awaddr(), + .m_axi_ddr_awlen(), + .m_axi_ddr_awsize(), + .m_axi_ddr_awburst(), + .m_axi_ddr_awlock(), + .m_axi_ddr_awcache(), + .m_axi_ddr_awprot(), + .m_axi_ddr_awqos(), + .m_axi_ddr_awuser(), + .m_axi_ddr_awvalid(), + .m_axi_ddr_awready(0), + .m_axi_ddr_wdata(), + .m_axi_ddr_wstrb(), + .m_axi_ddr_wlast(), + .m_axi_ddr_wuser(), + .m_axi_ddr_wvalid(), + .m_axi_ddr_wready(0), + .m_axi_ddr_bid(0), + .m_axi_ddr_bresp(0), + .m_axi_ddr_buser(0), + .m_axi_ddr_bvalid(0), + .m_axi_ddr_bready(), + .m_axi_ddr_arid(), + .m_axi_ddr_araddr(), + .m_axi_ddr_arlen(), + .m_axi_ddr_arsize(), + .m_axi_ddr_arburst(), + .m_axi_ddr_arlock(), + .m_axi_ddr_arcache(), + .m_axi_ddr_arprot(), + .m_axi_ddr_arqos(), + .m_axi_ddr_aruser(), + .m_axi_ddr_arvalid(), + .m_axi_ddr_arready(0), + .m_axi_ddr_rid(0), + .m_axi_ddr_rdata(0), + .m_axi_ddr_rresp(0), + .m_axi_ddr_rlast(0), + .m_axi_ddr_ruser(0), + .m_axi_ddr_rvalid(0), + .m_axi_ddr_rready(), + + .ddr_status(0), + + /* + * HBM + */ + .hbm_clk(0), + .hbm_rst(0), + + .m_axi_hbm_awid(), + .m_axi_hbm_awaddr(), + .m_axi_hbm_awlen(), + .m_axi_hbm_awsize(), + .m_axi_hbm_awburst(), + .m_axi_hbm_awlock(), + .m_axi_hbm_awcache(), + .m_axi_hbm_awprot(), + .m_axi_hbm_awqos(), + .m_axi_hbm_awuser(), + .m_axi_hbm_awvalid(), + .m_axi_hbm_awready(0), + .m_axi_hbm_wdata(), + .m_axi_hbm_wstrb(), + .m_axi_hbm_wlast(), + .m_axi_hbm_wuser(), + .m_axi_hbm_wvalid(), + .m_axi_hbm_wready(0), + .m_axi_hbm_bid(0), + .m_axi_hbm_bresp(0), + .m_axi_hbm_buser(0), + .m_axi_hbm_bvalid(0), + .m_axi_hbm_bready(), + .m_axi_hbm_arid(), + .m_axi_hbm_araddr(), + .m_axi_hbm_arlen(), + .m_axi_hbm_arsize(), + .m_axi_hbm_arburst(), + .m_axi_hbm_arlock(), + .m_axi_hbm_arcache(), + .m_axi_hbm_arprot(), + .m_axi_hbm_arqos(), + .m_axi_hbm_aruser(), + .m_axi_hbm_arvalid(), + .m_axi_hbm_arready(0), + .m_axi_hbm_rid(0), + .m_axi_hbm_rdata(0), + .m_axi_hbm_rresp(0), + .m_axi_hbm_rlast(0), + .m_axi_hbm_ruser(0), + .m_axi_hbm_rvalid(0), + .m_axi_hbm_rready(), + + .hbm_status(0), + /* * Statistics input */ diff --git a/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v b/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v index f54c45f25..306bae16b 100644 --- a/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v @@ -945,6 +945,10 @@ mqnic_core_pcie_us #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_ENABLE(0), + .HBM_ENABLE(0), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1222,6 +1226,108 @@ core_inst ( .eth_rx_status(eth_rx_status), + /* + * DDR + */ + .ddr_clk(0), + .ddr_rst(0), + + .m_axi_ddr_awid(), + .m_axi_ddr_awaddr(), + .m_axi_ddr_awlen(), + .m_axi_ddr_awsize(), + .m_axi_ddr_awburst(), + .m_axi_ddr_awlock(), + .m_axi_ddr_awcache(), + .m_axi_ddr_awprot(), + .m_axi_ddr_awqos(), + .m_axi_ddr_awuser(), + .m_axi_ddr_awvalid(), + .m_axi_ddr_awready(0), + .m_axi_ddr_wdata(), + .m_axi_ddr_wstrb(), + .m_axi_ddr_wlast(), + .m_axi_ddr_wuser(), + .m_axi_ddr_wvalid(), + .m_axi_ddr_wready(0), + .m_axi_ddr_bid(0), + .m_axi_ddr_bresp(0), + .m_axi_ddr_buser(0), + .m_axi_ddr_bvalid(0), + .m_axi_ddr_bready(), + .m_axi_ddr_arid(), + .m_axi_ddr_araddr(), + .m_axi_ddr_arlen(), + .m_axi_ddr_arsize(), + .m_axi_ddr_arburst(), + .m_axi_ddr_arlock(), + .m_axi_ddr_arcache(), + .m_axi_ddr_arprot(), + .m_axi_ddr_arqos(), + .m_axi_ddr_aruser(), + .m_axi_ddr_arvalid(), + .m_axi_ddr_arready(0), + .m_axi_ddr_rid(0), + .m_axi_ddr_rdata(0), + .m_axi_ddr_rresp(0), + .m_axi_ddr_rlast(0), + .m_axi_ddr_ruser(0), + .m_axi_ddr_rvalid(0), + .m_axi_ddr_rready(), + + .ddr_status(0), + + /* + * HBM + */ + .hbm_clk(0), + .hbm_rst(0), + + .m_axi_hbm_awid(), + .m_axi_hbm_awaddr(), + .m_axi_hbm_awlen(), + .m_axi_hbm_awsize(), + .m_axi_hbm_awburst(), + .m_axi_hbm_awlock(), + .m_axi_hbm_awcache(), + .m_axi_hbm_awprot(), + .m_axi_hbm_awqos(), + .m_axi_hbm_awuser(), + .m_axi_hbm_awvalid(), + .m_axi_hbm_awready(0), + .m_axi_hbm_wdata(), + .m_axi_hbm_wstrb(), + .m_axi_hbm_wlast(), + .m_axi_hbm_wuser(), + .m_axi_hbm_wvalid(), + .m_axi_hbm_wready(0), + .m_axi_hbm_bid(0), + .m_axi_hbm_bresp(0), + .m_axi_hbm_buser(0), + .m_axi_hbm_bvalid(0), + .m_axi_hbm_bready(), + .m_axi_hbm_arid(), + .m_axi_hbm_araddr(), + .m_axi_hbm_arlen(), + .m_axi_hbm_arsize(), + .m_axi_hbm_arburst(), + .m_axi_hbm_arlock(), + .m_axi_hbm_arcache(), + .m_axi_hbm_arprot(), + .m_axi_hbm_arqos(), + .m_axi_hbm_aruser(), + .m_axi_hbm_arvalid(), + .m_axi_hbm_arready(0), + .m_axi_hbm_rid(0), + .m_axi_hbm_rdata(0), + .m_axi_hbm_rresp(0), + .m_axi_hbm_rlast(0), + .m_axi_hbm_ruser(0), + .m_axi_hbm_rvalid(0), + .m_axi_hbm_rready(), + + .hbm_status(0), + /* * Statistics input */ diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/README.md b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/README.md index 34902be91..aa71eac55 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/README.md +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/README.md @@ -6,6 +6,7 @@ This design targets the Cisco Nexus K3P-Q FPGA board. * FPGA: xcku3p-ffvb676-2-e * PHY: 25G BASE-R PHY IP core and internal GTY transceiver +* RAM: 8 GB DDR4 (1G x72) ## How to build diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga.xdc b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga.xdc index 9ac631919..b56243f51 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga.xdc +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga.xdc @@ -174,6 +174,142 @@ set_input_delay 0 [get_ports {pcie_reset_n}] # 100 MHz MGT reference clock create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_refclk_p] +# DDR4 +# 9x MT40A1G8SA-075 +set_property -dict {LOC W24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[0]}] +set_property -dict {LOC U24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[1]}] +set_property -dict {LOC AA24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[2]}] +set_property -dict {LOC T24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[3]}] +set_property -dict {LOC Y22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[4]}] +set_property -dict {LOC V23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[5]}] +set_property -dict {LOC Y25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[6]}] +set_property -dict {LOC V24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[7]}] +set_property -dict {LOC W23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[8]}] +set_property -dict {LOC Y26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[9]}] +set_property -dict {LOC V21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[10]}] +set_property -dict {LOC W25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[11]}] +set_property -dict {LOC AA23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[12]}] +set_property -dict {LOC W26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[13]}] +set_property -dict {LOC U21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[14]}] +set_property -dict {LOC T22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[15]}] +set_property -dict {LOC T20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[16]}] +set_property -dict {LOC V22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_ba[0]}] +set_property -dict {LOC T23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_ba[1]}] +set_property -dict {LOC Y23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_bg[0]}] +set_property -dict {LOC P24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_bg[1]}] +set_property -dict {LOC U19 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_ck_t}] +set_property -dict {LOC V19 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_ck_c}] +set_property -dict {LOC W19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_cke}] +set_property -dict {LOC N24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_cs_n}] +set_property -dict {LOC W20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_act_n}] +set_property -dict {LOC U20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_odt}] +set_property -dict {LOC R25 IOSTANDARD LVCMOS12 } [get_ports {ddr4_reset_n}] + +set_property -dict {LOC L20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[0]}] +set_property -dict {LOC M20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[1]}] +set_property -dict {LOC J21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[2]}] +set_property -dict {LOC M21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[3]}] +set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[4]}] +set_property -dict {LOC J19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[5]}] +set_property -dict {LOC K20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[6]}] +set_property -dict {LOC J20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[7]}] +set_property -dict {LOC K23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[8]}] +set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[9]}] +set_property -dict {LOC M25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[10]}] +set_property -dict {LOC K26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[11]}] +set_property -dict {LOC J23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[12]}] +set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[13]}] +set_property -dict {LOC M26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[14]}] +set_property -dict {LOC K25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[15]}] +set_property -dict {LOC H23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[16]}] +set_property -dict {LOC G26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[17]}] +set_property -dict {LOC J26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[18]}] +set_property -dict {LOC H24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[19]}] +set_property -dict {LOC H21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[20]}] +set_property -dict {LOC H22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[21]}] +set_property -dict {LOC J25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[22]}] +set_property -dict {LOC H26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[23]}] +set_property -dict {LOC E23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[24]}] +set_property -dict {LOC D24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[25]}] +set_property -dict {LOC D25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[26]}] +set_property -dict {LOC B25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[27]}] +set_property -dict {LOC D26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[28]}] +set_property -dict {LOC F23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[29]}] +set_property -dict {LOC C26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[30]}] +set_property -dict {LOC B26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[31]}] +set_property -dict {LOC AF25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[32]}] +set_property -dict {LOC AC24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[33]}] +set_property -dict {LOC AD25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[34]}] +set_property -dict {LOC AD24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[35]}] +set_property -dict {LOC AF24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[36]}] +set_property -dict {LOC AB25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[37]}] +set_property -dict {LOC AB24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[38]}] +set_property -dict {LOC AB26 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[39]}] +set_property -dict {LOC AD21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[40]}] +set_property -dict {LOC AD23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[41]}] +set_property -dict {LOC AC21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[42]}] +set_property -dict {LOC AC23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[43]}] +set_property -dict {LOC AE21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[44]}] +set_property -dict {LOC AB21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[45]}] +set_property -dict {LOC AC22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[46]}] +set_property -dict {LOC AE23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[47]}] +set_property -dict {LOC AD16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[48]}] +set_property -dict {LOC AD19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[49]}] +set_property -dict {LOC AF17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[50]}] +set_property -dict {LOC AF19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[51]}] +set_property -dict {LOC AE16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[52]}] +set_property -dict {LOC AC19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[53]}] +set_property -dict {LOC AE17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[54]}] +set_property -dict {LOC AF18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[55]}] +set_property -dict {LOC AA19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[56]}] +set_property -dict {LOC Y17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[57]}] +set_property -dict {LOC AA20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[58]}] +set_property -dict {LOC AA17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[59]}] +set_property -dict {LOC AB19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[60]}] +set_property -dict {LOC Y18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[61]}] +set_property -dict {LOC AB20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[62]}] +set_property -dict {LOC AA18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[63]}] +set_property -dict {LOC H16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[64]}] +set_property -dict {LOC E15 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[65]}] +set_property -dict {LOC C16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[66]}] +set_property -dict {LOC D16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[67]}] +set_property -dict {LOC H17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[68]}] +set_property -dict {LOC G16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[69]}] +set_property -dict {LOC G17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[70]}] +set_property -dict {LOC D15 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[71]}] +set_property -dict {LOC M19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[0]}] +set_property -dict {LOC L19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[0]}] +set_property -dict {LOC L24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[1]}] +set_property -dict {LOC L25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[1]}] +set_property -dict {LOC F24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[2]}] +set_property -dict {LOC F25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[2]}] +set_property -dict {LOC D23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[3]}] +set_property -dict {LOC C24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[3]}] +set_property -dict {LOC AC26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[4]}] +set_property -dict {LOC AD26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[4]}] +set_property -dict {LOC AA22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[5]}] +set_property -dict {LOC AB22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[5]}] +set_property -dict {LOC AC18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[6]}] +set_property -dict {LOC AD18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[6]}] +set_property -dict {LOC AB17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[7]}] +set_property -dict {LOC AC17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[7]}] +set_property -dict {LOC E16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[8]}] +set_property -dict {LOC E17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[8]}] +set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[0]}] +set_property -dict {LOC L22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[1]}] +set_property -dict {LOC G24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[2]}] +set_property -dict {LOC E25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[3]}] +set_property -dict {LOC AE25 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[4]}] +set_property -dict {LOC AE22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[5]}] +set_property -dict {LOC AD20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[6]}] +set_property -dict {LOC Y20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[7]}] +set_property -dict {LOC G15 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[8]}] + +# 161.1328125 MHz DDR4 clock +set_property -dict {LOC T25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports clk_ddr4_p] +set_property -dict {LOC U25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports clk_ddr4_n] +#create_clock -period 6.206 -name clk_ddr4 [get_ports clk_ddr4_p] + # QSPI flash set_property -dict {LOC H11 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_clk}] set_property -dict {LOC H9 IOSTANDARD LVCMOS18 DRIVE 16} [get_ports {qspi_dq[0]}] diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile index b9fefc250..96758c53e 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile @@ -137,6 +137,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl index c209677b3..116d2f22b 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/config.tcl @@ -148,6 +148,12 @@ dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" dict set params RX_RAM_SIZE "131072" + +# RAM configuration +dict set params DDR_CH "1" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" # Application block configuration dict set params APP_ID "32'h00000000" @@ -200,6 +206,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile index b9fefc250..96758c53e 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile @@ -137,6 +137,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl index 735b75d6c..5a03ff521 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/config.tcl @@ -148,6 +148,12 @@ dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" dict set params RX_RAM_SIZE "32768" + +# RAM configuration +dict set params DDR_CH "1" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" # Application block configuration dict set params APP_ID "32'h00000000" @@ -200,6 +206,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/ip/ddr4_0.tcl b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/ip/ddr4_0.tcl new file mode 100644 index 000000000..68d38aa71 --- /dev/null +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/ip/ddr4_0.tcl @@ -0,0 +1,19 @@ + +create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 + +set_property -dict [list \ + CONFIG.C0.DDR4_AxiSelection {true} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_AxiIDWidth {8} \ + CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ + CONFIG.C0.DDR4_TimePeriod {825} \ + CONFIG.C0.DDR4_InputClockPeriod {6187} \ + CONFIG.C0.DDR4_MemoryType {Components} \ + CONFIG.C0.DDR4_MemoryPart {MT40A1G8SA-075} \ + CONFIG.C0.DDR4_DataWidth {72} \ + CONFIG.C0.DDR4_DataMask {NO_DM_NO_DBI} \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_CasLatency {19} \ + CONFIG.C0.DDR4_CasWriteLatency {14} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} +] [get_ips ddr4_0] diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v index 40c9e6d4c..d3a3b299d 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v @@ -112,6 +112,15 @@ module fpga # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // RAM configuration + parameter DDR_CH = 1, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 33, + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -177,6 +186,12 @@ module fpga # parameter STAT_ID_WIDTH = 12 ) ( + /* + * Clock + */ + input wire clk_ddr4_p, + input wire clk_ddr4_n, + /* * GPIO */ @@ -264,7 +279,25 @@ module fpga # output wire qspi_clk, inout wire [3:0] qspi_dq, output wire qspi_0_cs, - output wire qspi_1_cs + output wire qspi_1_cs, + + /* + * DDR4 + */ + output wire [16:0] ddr4_adr, + output wire [1:0] ddr4_ba, + output wire [1:0] ddr4_bg, + output wire [0:0] ddr4_ck_t, + output wire [0:0] ddr4_ck_c, + output wire [0:0] ddr4_cke, + output wire [0:0] ddr4_cs_n, + output wire ddr4_act_n, + output wire [0:0] ddr4_odt, + output wire ddr4_reset_n, + inout wire [71:0] ddr4_dq, + inout wire [8:0] ddr4_dqs_t, + inout wire [8:0] ddr4_dqs_c, + inout wire [8:0] ddr4_dm_dbi_n ); // PTP configuration @@ -278,6 +311,9 @@ parameter IF_PTP_PERIOD_FNS = 16'h8F5C; // Interface configuration parameter TX_TAG_WIDTH = 16; +// RAM configuration +parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8); + // Ethernet interface configuration parameter XGMII_DATA_WIDTH = 64; parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8; @@ -1271,6 +1307,183 @@ assign ptp_sample_clk = clk_125mhz_int; assign qsfp_0_led_green = qsfp_0_rx_status_0; assign qsfp_1_led_green = qsfp_1_rx_status_0; +// DDR4 +wire [DDR_CH-1:0] ddr_clk; +wire [DDR_CH-1:0] ddr_rst; + +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr; +wire [DDR_CH*8-1:0] m_axi_ddr_awlen; +wire [DDR_CH*3-1:0] m_axi_ddr_awsize; +wire [DDR_CH*2-1:0] m_axi_ddr_awburst; +wire [DDR_CH-1:0] m_axi_ddr_awlock; +wire [DDR_CH*4-1:0] m_axi_ddr_awcache; +wire [DDR_CH*3-1:0] m_axi_ddr_awprot; +wire [DDR_CH*4-1:0] m_axi_ddr_awqos; +wire [DDR_CH-1:0] m_axi_ddr_awvalid; +wire [DDR_CH-1:0] m_axi_ddr_awready; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata; +wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb; +wire [DDR_CH-1:0] m_axi_ddr_wlast; +wire [DDR_CH-1:0] m_axi_ddr_wvalid; +wire [DDR_CH-1:0] m_axi_ddr_wready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid; +wire [DDR_CH*2-1:0] m_axi_ddr_bresp; +wire [DDR_CH-1:0] m_axi_ddr_bvalid; +wire [DDR_CH-1:0] m_axi_ddr_bready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr; +wire [DDR_CH*8-1:0] m_axi_ddr_arlen; +wire [DDR_CH*3-1:0] m_axi_ddr_arsize; +wire [DDR_CH*2-1:0] m_axi_ddr_arburst; +wire [DDR_CH-1:0] m_axi_ddr_arlock; +wire [DDR_CH*4-1:0] m_axi_ddr_arcache; +wire [DDR_CH*3-1:0] m_axi_ddr_arprot; +wire [DDR_CH*4-1:0] m_axi_ddr_arqos; +wire [DDR_CH-1:0] m_axi_ddr_arvalid; +wire [DDR_CH-1:0] m_axi_ddr_arready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata; +wire [DDR_CH*2-1:0] m_axi_ddr_rresp; +wire [DDR_CH-1:0] m_axi_ddr_rlast; +wire [DDR_CH-1:0] m_axi_ddr_rvalid; +wire [DDR_CH-1:0] m_axi_ddr_rready; + +wire [DDR_CH-1:0] ddr_status; + +generate + +if (DDR_ENABLE && DDR_CH > 0) begin + +ddr4_0 ddr4_inst ( + .c0_sys_clk_p(clk_ddr4_p), + .c0_sys_clk_n(clk_ddr4_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[0 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_adr), + .c0_ddr4_ba(ddr4_ba), + .c0_ddr4_cke(ddr4_cke), + .c0_ddr4_cs_n(ddr4_cs_n), + .c0_ddr4_dq(ddr4_dq), + .c0_ddr4_dqs_t(ddr4_dqs_t), + .c0_ddr4_dqs_c(ddr4_dqs_c), + .c0_ddr4_dm_dbi_n(ddr4_dm_dbi_n), + .c0_ddr4_odt(ddr4_odt), + .c0_ddr4_bg(ddr4_bg), + .c0_ddr4_reset_n(ddr4_reset_n), + .c0_ddr4_act_n(ddr4_act_n), + .c0_ddr4_ck_t(ddr4_ck_t), + .c0_ddr4_ck_c(ddr4_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[0 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[0 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_adr = {17{1'bz}}; +assign ddr4_ba = {2{1'bz}}; +assign ddr4_bg = {1{1'bz}}; +assign ddr4_cke = 1'bz; +assign ddr4_cs_n = 1'bz; +assign ddr4_act_n = 1'bz; +assign ddr4_odt = 1'bz; +assign ddr4_reset_n = 1'b0; +assign ddr4_dq = {72{1'bz}}; +assign ddr4_dqs_t = {9{1'bz}}; +assign ddr4_dqs_c = {9{1'bz}}; +assign ddr4_dm_dbi_n = {9{1'bz}}; + +OBUFTDS ddr4_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_ck_t), + .OB(ddr4_ck_c) +); + +assign ddr_clk = 0; +assign ddr_rst = 0; + +assign m_axi_ddr_awready = 0; +assign m_axi_ddr_wready = 0; +assign m_axi_ddr_bid = 0; +assign m_axi_ddr_bresp = 0; +assign m_axi_ddr_bvalid = 0; +assign m_axi_ddr_arready = 0; +assign m_axi_ddr_rid = 0; +assign m_axi_ddr_rdata = 0; +assign m_axi_ddr_rresp = 0; +assign m_axi_ddr_rlast = 0; +assign m_axi_ddr_rvalid = 0; + +assign ddr_status = 0; + +end + +endgenerate + fpga_core #( // FW and board IDs .FPGA_ID(FPGA_ID), @@ -1347,6 +1560,16 @@ fpga_core #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1672,6 +1895,52 @@ core_inst ( .eeprom_i2c_sda_o(eeprom_i2c_sda_o), .eeprom_i2c_sda_t(eeprom_i2c_sda_t), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + /* * QSPI flash */ diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v index 1994d4d74..e99729e9c 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v @@ -122,6 +122,16 @@ module fpga_core # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // RAM configuration + parameter DDR_CH = 1, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 33, + parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -450,6 +460,52 @@ module fpga_core # output wire eeprom_i2c_sda_o, output wire eeprom_i2c_sda_t, + /* + * DDR + */ + input wire [DDR_CH-1:0] ddr_clk, + input wire [DDR_CH-1:0] ddr_rst, + + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, + output wire [DDR_CH-1:0] m_axi_ddr_awlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, + output wire [DDR_CH-1:0] m_axi_ddr_awvalid, + input wire [DDR_CH-1:0] m_axi_ddr_awready, + output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, + output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, + output wire [DDR_CH-1:0] m_axi_ddr_wlast, + output wire [DDR_CH-1:0] m_axi_ddr_wvalid, + input wire [DDR_CH-1:0] m_axi_ddr_wready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, + input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, + input wire [DDR_CH-1:0] m_axi_ddr_bvalid, + output wire [DDR_CH-1:0] m_axi_ddr_bready, + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, + output wire [DDR_CH-1:0] m_axi_ddr_arlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, + output wire [DDR_CH-1:0] m_axi_ddr_arvalid, + input wire [DDR_CH-1:0] m_axi_ddr_arready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, + input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, + input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, + input wire [DDR_CH-1:0] m_axi_ddr_rlast, + input wire [DDR_CH-1:0] m_axi_ddr_rvalid, + output wire [DDR_CH-1:0] m_axi_ddr_rready, + + input wire [DDR_CH-1:0] ddr_status, + /* * QSPI flash */ @@ -1225,6 +1281,25 @@ mqnic_core_pcie_us #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .DDR_GROUP_SIZE(1), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_AWUSER_ENABLE(0), + .AXI_DDR_WUSER_ENABLE(0), + .AXI_DDR_BUSER_ENABLE(0), + .AXI_DDR_ARUSER_ENABLE(0), + .AXI_DDR_RUSER_ENABLE(0), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + .AXI_DDR_FIXED_BURST(0), + .AXI_DDR_WRAP_BURST(1), + .HBM_ENABLE(0), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1502,6 +1577,108 @@ core_inst ( .eth_rx_status(eth_rx_status), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awuser(), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wuser(), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_buser(0), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_aruser(), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_ruser(0), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + + /* + * HBM + */ + .hbm_clk(0), + .hbm_rst(0), + + .m_axi_hbm_awid(), + .m_axi_hbm_awaddr(), + .m_axi_hbm_awlen(), + .m_axi_hbm_awsize(), + .m_axi_hbm_awburst(), + .m_axi_hbm_awlock(), + .m_axi_hbm_awcache(), + .m_axi_hbm_awprot(), + .m_axi_hbm_awqos(), + .m_axi_hbm_awuser(), + .m_axi_hbm_awvalid(), + .m_axi_hbm_awready(0), + .m_axi_hbm_wdata(), + .m_axi_hbm_wstrb(), + .m_axi_hbm_wlast(), + .m_axi_hbm_wuser(), + .m_axi_hbm_wvalid(), + .m_axi_hbm_wready(0), + .m_axi_hbm_bid(0), + .m_axi_hbm_bresp(0), + .m_axi_hbm_buser(0), + .m_axi_hbm_bvalid(0), + .m_axi_hbm_bready(), + .m_axi_hbm_arid(), + .m_axi_hbm_araddr(), + .m_axi_hbm_arlen(), + .m_axi_hbm_arsize(), + .m_axi_hbm_arburst(), + .m_axi_hbm_arlock(), + .m_axi_hbm_arcache(), + .m_axi_hbm_arprot(), + .m_axi_hbm_arqos(), + .m_axi_hbm_aruser(), + .m_axi_hbm_arvalid(), + .m_axi_hbm_arready(0), + .m_axi_hbm_rid(0), + .m_axi_hbm_rdata(0), + .m_axi_hbm_rresp(0), + .m_axi_hbm_rlast(0), + .m_axi_hbm_ruser(0), + .m_axi_hbm_rvalid(0), + .m_axi_hbm_rready(), + + .hbm_status(0), + /* * Statistics input */ diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v index bc933faa5..d1c0fd707 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v @@ -1043,6 +1043,10 @@ mqnic_core_pcie_us #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_ENABLE(0), + .HBM_ENABLE(0), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1320,6 +1324,108 @@ core_inst ( .eth_rx_status(eth_rx_status), + /* + * DDR + */ + .ddr_clk(0), + .ddr_rst(0), + + .m_axi_ddr_awid(), + .m_axi_ddr_awaddr(), + .m_axi_ddr_awlen(), + .m_axi_ddr_awsize(), + .m_axi_ddr_awburst(), + .m_axi_ddr_awlock(), + .m_axi_ddr_awcache(), + .m_axi_ddr_awprot(), + .m_axi_ddr_awqos(), + .m_axi_ddr_awuser(), + .m_axi_ddr_awvalid(), + .m_axi_ddr_awready(0), + .m_axi_ddr_wdata(), + .m_axi_ddr_wstrb(), + .m_axi_ddr_wlast(), + .m_axi_ddr_wuser(), + .m_axi_ddr_wvalid(), + .m_axi_ddr_wready(0), + .m_axi_ddr_bid(0), + .m_axi_ddr_bresp(0), + .m_axi_ddr_buser(0), + .m_axi_ddr_bvalid(0), + .m_axi_ddr_bready(), + .m_axi_ddr_arid(), + .m_axi_ddr_araddr(), + .m_axi_ddr_arlen(), + .m_axi_ddr_arsize(), + .m_axi_ddr_arburst(), + .m_axi_ddr_arlock(), + .m_axi_ddr_arcache(), + .m_axi_ddr_arprot(), + .m_axi_ddr_arqos(), + .m_axi_ddr_aruser(), + .m_axi_ddr_arvalid(), + .m_axi_ddr_arready(0), + .m_axi_ddr_rid(0), + .m_axi_ddr_rdata(0), + .m_axi_ddr_rresp(0), + .m_axi_ddr_rlast(0), + .m_axi_ddr_ruser(0), + .m_axi_ddr_rvalid(0), + .m_axi_ddr_rready(), + + .ddr_status(0), + + /* + * HBM + */ + .hbm_clk(0), + .hbm_rst(0), + + .m_axi_hbm_awid(), + .m_axi_hbm_awaddr(), + .m_axi_hbm_awlen(), + .m_axi_hbm_awsize(), + .m_axi_hbm_awburst(), + .m_axi_hbm_awlock(), + .m_axi_hbm_awcache(), + .m_axi_hbm_awprot(), + .m_axi_hbm_awqos(), + .m_axi_hbm_awuser(), + .m_axi_hbm_awvalid(), + .m_axi_hbm_awready(0), + .m_axi_hbm_wdata(), + .m_axi_hbm_wstrb(), + .m_axi_hbm_wlast(), + .m_axi_hbm_wuser(), + .m_axi_hbm_wvalid(), + .m_axi_hbm_wready(0), + .m_axi_hbm_bid(0), + .m_axi_hbm_bresp(0), + .m_axi_hbm_buser(0), + .m_axi_hbm_bvalid(0), + .m_axi_hbm_bready(), + .m_axi_hbm_arid(), + .m_axi_hbm_araddr(), + .m_axi_hbm_arlen(), + .m_axi_hbm_arsize(), + .m_axi_hbm_arburst(), + .m_axi_hbm_arlock(), + .m_axi_hbm_arcache(), + .m_axi_hbm_arprot(), + .m_axi_hbm_arqos(), + .m_axi_hbm_aruser(), + .m_axi_hbm_arvalid(), + .m_axi_hbm_arready(0), + .m_axi_hbm_rid(0), + .m_axi_hbm_rdata(0), + .m_axi_hbm_rresp(0), + .m_axi_hbm_rlast(0), + .m_axi_hbm_ruser(0), + .m_axi_hbm_rvalid(0), + .m_axi_hbm_rready(), + + .hbm_status(0), + /* * Statistics input */ diff --git a/fpga/mqnic/S10DX_DK/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/S10DX_DK/fpga_25g/rtl/fpga_core.v index 5326291b4..2d7b268fe 100644 --- a/fpga/mqnic/S10DX_DK/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/S10DX_DK/fpga_25g/rtl/fpga_core.v @@ -972,6 +972,10 @@ mqnic_core_pcie_ptile #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_ENABLE(0), + .HBM_ENABLE(0), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1191,6 +1195,108 @@ core_inst ( .eth_rx_status(eth_rx_status), + /* + * DDR + */ + .ddr_clk(0), + .ddr_rst(0), + + .m_axi_ddr_awid(), + .m_axi_ddr_awaddr(), + .m_axi_ddr_awlen(), + .m_axi_ddr_awsize(), + .m_axi_ddr_awburst(), + .m_axi_ddr_awlock(), + .m_axi_ddr_awcache(), + .m_axi_ddr_awprot(), + .m_axi_ddr_awqos(), + .m_axi_ddr_awuser(), + .m_axi_ddr_awvalid(), + .m_axi_ddr_awready(0), + .m_axi_ddr_wdata(), + .m_axi_ddr_wstrb(), + .m_axi_ddr_wlast(), + .m_axi_ddr_wuser(), + .m_axi_ddr_wvalid(), + .m_axi_ddr_wready(0), + .m_axi_ddr_bid(0), + .m_axi_ddr_bresp(0), + .m_axi_ddr_buser(0), + .m_axi_ddr_bvalid(0), + .m_axi_ddr_bready(), + .m_axi_ddr_arid(), + .m_axi_ddr_araddr(), + .m_axi_ddr_arlen(), + .m_axi_ddr_arsize(), + .m_axi_ddr_arburst(), + .m_axi_ddr_arlock(), + .m_axi_ddr_arcache(), + .m_axi_ddr_arprot(), + .m_axi_ddr_arqos(), + .m_axi_ddr_aruser(), + .m_axi_ddr_arvalid(), + .m_axi_ddr_arready(0), + .m_axi_ddr_rid(0), + .m_axi_ddr_rdata(0), + .m_axi_ddr_rresp(0), + .m_axi_ddr_rlast(0), + .m_axi_ddr_ruser(0), + .m_axi_ddr_rvalid(0), + .m_axi_ddr_rready(), + + .ddr_status(0), + + /* + * HBM + */ + .hbm_clk(0), + .hbm_rst(0), + + .m_axi_hbm_awid(), + .m_axi_hbm_awaddr(), + .m_axi_hbm_awlen(), + .m_axi_hbm_awsize(), + .m_axi_hbm_awburst(), + .m_axi_hbm_awlock(), + .m_axi_hbm_awcache(), + .m_axi_hbm_awprot(), + .m_axi_hbm_awqos(), + .m_axi_hbm_awuser(), + .m_axi_hbm_awvalid(), + .m_axi_hbm_awready(0), + .m_axi_hbm_wdata(), + .m_axi_hbm_wstrb(), + .m_axi_hbm_wlast(), + .m_axi_hbm_wuser(), + .m_axi_hbm_wvalid(), + .m_axi_hbm_wready(0), + .m_axi_hbm_bid(0), + .m_axi_hbm_bresp(0), + .m_axi_hbm_buser(0), + .m_axi_hbm_bvalid(0), + .m_axi_hbm_bready(), + .m_axi_hbm_arid(), + .m_axi_hbm_araddr(), + .m_axi_hbm_arlen(), + .m_axi_hbm_arsize(), + .m_axi_hbm_arburst(), + .m_axi_hbm_arlock(), + .m_axi_hbm_arcache(), + .m_axi_hbm_arprot(), + .m_axi_hbm_arqos(), + .m_axi_hbm_aruser(), + .m_axi_hbm_arvalid(), + .m_axi_hbm_arready(0), + .m_axi_hbm_rid(0), + .m_axi_hbm_rdata(0), + .m_axi_hbm_rresp(0), + .m_axi_hbm_rlast(0), + .m_axi_hbm_ruser(0), + .m_axi_hbm_rvalid(0), + .m_axi_hbm_rready(), + + .hbm_status(0), + /* * Statistics input */ diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/S10MX_DK/fpga_25g/rtl/fpga_core.v index dc12dc3e4..90e037e47 100644 --- a/fpga/mqnic/S10MX_DK/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/S10MX_DK/fpga_25g/rtl/fpga_core.v @@ -900,6 +900,10 @@ mqnic_core_pcie_s10 #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_ENABLE(0), + .HBM_ENABLE(0), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1118,6 +1122,108 @@ core_inst ( .eth_rx_status(eth_rx_status), + /* + * DDR + */ + .ddr_clk(0), + .ddr_rst(0), + + .m_axi_ddr_awid(), + .m_axi_ddr_awaddr(), + .m_axi_ddr_awlen(), + .m_axi_ddr_awsize(), + .m_axi_ddr_awburst(), + .m_axi_ddr_awlock(), + .m_axi_ddr_awcache(), + .m_axi_ddr_awprot(), + .m_axi_ddr_awqos(), + .m_axi_ddr_awuser(), + .m_axi_ddr_awvalid(), + .m_axi_ddr_awready(0), + .m_axi_ddr_wdata(), + .m_axi_ddr_wstrb(), + .m_axi_ddr_wlast(), + .m_axi_ddr_wuser(), + .m_axi_ddr_wvalid(), + .m_axi_ddr_wready(0), + .m_axi_ddr_bid(0), + .m_axi_ddr_bresp(0), + .m_axi_ddr_buser(0), + .m_axi_ddr_bvalid(0), + .m_axi_ddr_bready(), + .m_axi_ddr_arid(), + .m_axi_ddr_araddr(), + .m_axi_ddr_arlen(), + .m_axi_ddr_arsize(), + .m_axi_ddr_arburst(), + .m_axi_ddr_arlock(), + .m_axi_ddr_arcache(), + .m_axi_ddr_arprot(), + .m_axi_ddr_arqos(), + .m_axi_ddr_aruser(), + .m_axi_ddr_arvalid(), + .m_axi_ddr_arready(0), + .m_axi_ddr_rid(0), + .m_axi_ddr_rdata(0), + .m_axi_ddr_rresp(0), + .m_axi_ddr_rlast(0), + .m_axi_ddr_ruser(0), + .m_axi_ddr_rvalid(0), + .m_axi_ddr_rready(), + + .ddr_status(0), + + /* + * HBM + */ + .hbm_clk(0), + .hbm_rst(0), + + .m_axi_hbm_awid(), + .m_axi_hbm_awaddr(), + .m_axi_hbm_awlen(), + .m_axi_hbm_awsize(), + .m_axi_hbm_awburst(), + .m_axi_hbm_awlock(), + .m_axi_hbm_awcache(), + .m_axi_hbm_awprot(), + .m_axi_hbm_awqos(), + .m_axi_hbm_awuser(), + .m_axi_hbm_awvalid(), + .m_axi_hbm_awready(0), + .m_axi_hbm_wdata(), + .m_axi_hbm_wstrb(), + .m_axi_hbm_wlast(), + .m_axi_hbm_wuser(), + .m_axi_hbm_wvalid(), + .m_axi_hbm_wready(0), + .m_axi_hbm_bid(0), + .m_axi_hbm_bresp(0), + .m_axi_hbm_buser(0), + .m_axi_hbm_bvalid(0), + .m_axi_hbm_bready(), + .m_axi_hbm_arid(), + .m_axi_hbm_araddr(), + .m_axi_hbm_arlen(), + .m_axi_hbm_arsize(), + .m_axi_hbm_arburst(), + .m_axi_hbm_arlock(), + .m_axi_hbm_arcache(), + .m_axi_hbm_arprot(), + .m_axi_hbm_arqos(), + .m_axi_hbm_aruser(), + .m_axi_hbm_arvalid(), + .m_axi_hbm_arready(0), + .m_axi_hbm_rid(0), + .m_axi_hbm_rdata(0), + .m_axi_hbm_rresp(0), + .m_axi_hbm_rlast(0), + .m_axi_hbm_ruser(0), + .m_axi_hbm_rvalid(0), + .m_axi_hbm_rready(), + + .hbm_status(0), + /* * Statistics input */ diff --git a/fpga/mqnic/VCU108/fpga_25g/README.md b/fpga/mqnic/VCU108/fpga_25g/README.md index a98333a04..61a6e297a 100644 --- a/fpga/mqnic/VCU108/fpga_25g/README.md +++ b/fpga/mqnic/VCU108/fpga_25g/README.md @@ -4,8 +4,9 @@ This design targets the Xilinx VCU108 FPGA board. -FPGA: xcvu095-ffva2104-2-e -PHY: 10G BASE-R PHY IP core and internal GTY transceiver +* FPGA: xcvu095-ffva2104-2-e +* PHY: 10G BASE-R PHY IP core and internal GTY transceiver +* RAM: 4 GB DDR4 2400 (2x 256M x80) ## How to build diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga.xdc b/fpga/mqnic/VCU108/fpga_25g/fpga.xdc index 0499384da..573376c51 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga.xdc +++ b/fpga/mqnic/VCU108/fpga_25g/fpga.xdc @@ -11,9 +11,13 @@ set_property CONFIG_MODE BPI16 [current_design] # System clocks # 300 MHz -#set_property -dict {LOC G31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_1_p] -#set_property -dict {LOC F31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_1_n] -#create_clock -period 3.333 -name clk_300mhz_1 [get_ports clk_300mhz_1_p] +set_property -dict {LOC G31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_1_p] +set_property -dict {LOC F31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_1_n] +create_clock -period 3.333 -name clk_300mhz_1 [get_ports clk_300mhz_1_p] + +# DDR ref clock sharing +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {name =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1 && name =~*ddr4_c1_inst*}] +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {name =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1 && name =~*ddr4_c2_inst*}] #set_property -dict {LOC G22 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_2_p] #set_property -dict {LOC G21 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_2_n] @@ -212,6 +216,300 @@ create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_mgt_refclk_p] set_false_path -from [get_ports {pcie_reset_n}] set_input_delay 0 [get_ports {pcie_reset_n}] +# DDR4 C1 +# 5x MT40A256M16GE-075E +set_property -dict {LOC C30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}] +set_property -dict {LOC D32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}] +set_property -dict {LOC B30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}] +set_property -dict {LOC C33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}] +set_property -dict {LOC E32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}] +set_property -dict {LOC A29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}] +set_property -dict {LOC C29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}] +set_property -dict {LOC E29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}] +set_property -dict {LOC A30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}] +set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}] +set_property -dict {LOC A31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}] +set_property -dict {LOC A33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}] +set_property -dict {LOC F29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}] +set_property -dict {LOC B32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}] +set_property -dict {LOC D29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}] +set_property -dict {LOC B31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}] +set_property -dict {LOC B33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}] +set_property -dict {LOC G30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}] +set_property -dict {LOC F30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}] +set_property -dict {LOC F33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}] +set_property -dict {LOC E31 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t}] +set_property -dict {LOC D31 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c}] +set_property -dict {LOC K29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke}] +set_property -dict {LOC D30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n}] +set_property -dict {LOC E33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}] +set_property -dict {LOC J31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt}] +set_property -dict {LOC R29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}] +set_property -dict {LOC M28 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}] +set_property -dict {LOC J40 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_alert_n}] + +set_property -dict {LOC J37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] ;# U60.G2 DQL0 +set_property -dict {LOC H40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] ;# U60.F7 DQL1 +set_property -dict {LOC F38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] ;# U60.H3 DQL2 +set_property -dict {LOC H39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] ;# U60.H7 DQL3 +set_property -dict {LOC K37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] ;# U60.H2 DQL4 +set_property -dict {LOC G40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] ;# U60.H8 DQL5 +set_property -dict {LOC F39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] ;# U60.J3 DQL6 +set_property -dict {LOC F40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] ;# U60.J7 DQL7 +set_property -dict {LOC F36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] ;# U60.A3 DQU0 +set_property -dict {LOC J36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] ;# U60.B8 DQU1 +set_property -dict {LOC F35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] ;# U60.C3 DQU2 +set_property -dict {LOC J35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] ;# U60.C7 DQU3 +set_property -dict {LOC G37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] ;# U60.C2 DQU4 +set_property -dict {LOC H35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] ;# U60.C8 DQU5 +set_property -dict {LOC G36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] ;# U60.D3 DQU6 +set_property -dict {LOC H37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] ;# U60.D7 DQU7 +set_property -dict {LOC H38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] ;# U60.G3 DQSL_T +set_property -dict {LOC G38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] ;# U60.F3 DQSL_C +set_property -dict {LOC H34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] ;# U60.B7 DQSU_T +set_property -dict {LOC G35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] ;# U60.A7 DQSU_C +set_property -dict {LOC J39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[0]}] ;# U60.E7 DML_B/DBIL_B +set_property -dict {LOC F34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[1]}] ;# U60.E2 DMU_B/DBIU_B + +set_property -dict {LOC C39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] ;# U61.G2 DQL0 +set_property -dict {LOC A38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] ;# U61.F7 DQL1 +set_property -dict {LOC B40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] ;# U61.H3 DQL2 +set_property -dict {LOC D40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] ;# U61.H7 DQL3 +set_property -dict {LOC E38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] ;# U61.H2 DQL4 +set_property -dict {LOC B38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] ;# U61.H8 DQL5 +set_property -dict {LOC E37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] ;# U61.J3 DQL6 +set_property -dict {LOC C40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] ;# U61.J7 DQL7 +set_property -dict {LOC C34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] ;# U61.A3 DQU0 +set_property -dict {LOC A34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] ;# U61.B8 DQU1 +set_property -dict {LOC D34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] ;# U61.C3 DQU2 +set_property -dict {LOC A35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] ;# U61.C7 DQU3 +set_property -dict {LOC A36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] ;# U61.C2 DQU4 +set_property -dict {LOC C35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] ;# U61.C8 DQU5 +set_property -dict {LOC B35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] ;# U61.D3 DQU6 +set_property -dict {LOC D35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] ;# U61.D7 DQU7 +set_property -dict {LOC A39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] ;# U61.G3 DQSL_T +set_property -dict {LOC A40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] ;# U61.F3 DQSL_C +set_property -dict {LOC B36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] ;# U61.B7 DQSU_T +set_property -dict {LOC B37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] ;# U61.A7 DQSU_C +set_property -dict {LOC E39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[2]}] ;# U61.E7 DML_B/DBIL_B +set_property -dict {LOC D37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[3]}] ;# U61.E2 DMU_B/DBIU_B + +set_property -dict {LOC N27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] ;# U62.G2 DQL0 +set_property -dict {LOC R27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] ;# U62.F7 DQL1 +set_property -dict {LOC N24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] ;# U62.H3 DQL2 +set_property -dict {LOC R24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] ;# U62.H7 DQL3 +set_property -dict {LOC P24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] ;# U62.H2 DQL4 +set_property -dict {LOC P26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] ;# U62.H8 DQL5 +set_property -dict {LOC P27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] ;# U62.J3 DQL6 +set_property -dict {LOC T24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] ;# U62.J7 DQL7 +set_property -dict {LOC K27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] ;# U62.A3 DQU0 +set_property -dict {LOC L26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] ;# U62.B8 DQU1 +set_property -dict {LOC J27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] ;# U62.C3 DQU2 +set_property -dict {LOC K28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] ;# U62.C7 DQU3 +set_property -dict {LOC K26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] ;# U62.C2 DQU4 +set_property -dict {LOC M25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] ;# U62.C8 DQU5 +set_property -dict {LOC J26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] ;# U62.D3 DQU6 +set_property -dict {LOC L28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] ;# U62.D7 DQU7 +set_property -dict {LOC P25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] ;# U62.G3 DQSL_T +set_property -dict {LOC N25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] ;# U62.F3 DQSL_C +set_property -dict {LOC L24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] ;# U62.B7 DQSU_T +set_property -dict {LOC L25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] ;# U62.A7 DQSU_C +set_property -dict {LOC T26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[4]}] ;# U62.E7 DML_B/DBIL_B +set_property -dict {LOC M27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[5]}] ;# U62.E2 DMU_B/DBIU_B + +set_property -dict {LOC E27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] ;# U63.G2 DQL0 +set_property -dict {LOC E28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] ;# U63.F7 DQL1 +set_property -dict {LOC E26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] ;# U63.H3 DQL2 +set_property -dict {LOC H27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] ;# U63.H7 DQL3 +set_property -dict {LOC F25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] ;# U63.H2 DQL4 +set_property -dict {LOC F28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] ;# U63.H8 DQL5 +set_property -dict {LOC G25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] ;# U63.J3 DQL6 +set_property -dict {LOC G27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] ;# U63.J7 DQL7 +set_property -dict {LOC B28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] ;# U63.A3 DQU0 +set_property -dict {LOC A28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] ;# U63.B8 DQU1 +set_property -dict {LOC B25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] ;# U63.C3 DQU2 +set_property -dict {LOC B27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] ;# U63.C7 DQU3 +set_property -dict {LOC D25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] ;# U63.C2 DQU4 +set_property -dict {LOC C27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] ;# U63.C8 DQU5 +set_property -dict {LOC C25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] ;# U63.D3 DQU6 +set_property -dict {LOC D26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] ;# U63.D7 DQU7 +set_property -dict {LOC H28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] ;# U63.G3 DQSL_T +set_property -dict {LOC G28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] ;# U63.F3 DQSL_C +set_property -dict {LOC B26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] ;# U63.B7 DQSU_T +set_property -dict {LOC A26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] ;# U63.A7 DQSU_C +set_property -dict {LOC G26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[6]}] ;# U63.E7 DML_B/DBIL_B +set_property -dict {LOC D27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[7]}] ;# U63.E2 DMU_B/DBIU_B + +set_property -dict {LOC N29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}] ;# U64.G2 DQL0 +set_property -dict {LOC M31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}] ;# U64.F7 DQL1 +set_property -dict {LOC P29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}] ;# U64.H3 DQL2 +set_property -dict {LOC L29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}] ;# U64.H7 DQL3 +set_property -dict {LOC P30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}] ;# U64.H2 DQL4 +set_property -dict {LOC N28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}] ;# U64.H8 DQL5 +set_property -dict {LOC L31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}] ;# U64.J3 DQL6 +set_property -dict {LOC L30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}] ;# U64.J7 DQL7 +# set_property -dict {LOC H30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[72]}] ;# U64.A3 DQU0 +# set_property -dict {LOC J32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[73]}] ;# U64.B8 DQU1 +# set_property -dict {LOC H29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[74]}] ;# U64.C3 DQU2 +# set_property -dict {LOC H32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[75]}] ;# U64.C7 DQU3 +# set_property -dict {LOC J29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[76]}] ;# U64.C2 DQU4 +# set_property -dict {LOC K32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[77]}] ;# U64.C8 DQU5 +# set_property -dict {LOC J30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[78]}] ;# U64.D3 DQU6 +# set_property -dict {LOC G32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[79]}] ;# U64.D7 DQU7 +set_property -dict {LOC N30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}] ;# U64.G3 DQSL_T +set_property -dict {LOC M30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}] ;# U64.F3 DQSL_C +# set_property -dict {LOC H33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}] ;# U64.B7 DQSU_T +# set_property -dict {LOC G33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}] ;# U64.A7 DQSU_C +set_property -dict {LOC R28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[8]}] ;# U64.E7 DML_B/DBIL_B +# set_property -dict {LOC K31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[9]}] ;# U64.E2 DMU_B/DBIU_B + +# DDR4 C2 +# 5x MT40A256M16GE-075E +set_property -dict {LOC AM27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[0]}] +set_property -dict {LOC AT25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[1]}] +set_property -dict {LOC AN25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[2]}] +set_property -dict {LOC AN26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[3]}] +set_property -dict {LOC AR25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[4]}] +set_property -dict {LOC AU28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[5]}] +set_property -dict {LOC AU27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[6]}] +set_property -dict {LOC AR28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[7]}] +set_property -dict {LOC AP25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[8]}] +set_property -dict {LOC AM26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[9]}] +set_property -dict {LOC AP26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[10]}] +set_property -dict {LOC AN28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[11]}] +set_property -dict {LOC AR27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[12]}] +set_property -dict {LOC AP28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[13]}] +set_property -dict {LOC AL27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[14]}] +set_property -dict {LOC AP27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[15]}] +set_property -dict {LOC AM28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[16]}] +set_property -dict {LOC AU26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[0]}] +set_property -dict {LOC AV26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[1]}] +set_property -dict {LOC AV28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[0]}] +set_property -dict {LOC AT26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t}] +set_property -dict {LOC AT27 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c}] +set_property -dict {LOC AY29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke}] +set_property -dict {LOC AW26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n}] +set_property -dict {LOC AW28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_act_n}] +set_property -dict {LOC BB29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt}] +set_property -dict {LOC BF29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_par}] +set_property -dict {LOC BF40 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_reset_n}] +set_property -dict {LOC AV25 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_alert_n}] + +set_property -dict {LOC BE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[0]}] ;# U135.G2 DQL0 +set_property -dict {LOC BE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[1]}] ;# U135.F7 DQL1 +set_property -dict {LOC BD30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[2]}] ;# U135.H3 DQL2 +set_property -dict {LOC BD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[3]}] ;# U135.H7 DQL3 +set_property -dict {LOC BD31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[4]}] ;# U135.H2 DQL4 +set_property -dict {LOC BC33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[5]}] ;# U135.H8 DQL5 +set_property -dict {LOC BD32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[6]}] ;# U135.J3 DQL6 +set_property -dict {LOC BC31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[7]}] ;# U135.J7 DQL7 +set_property -dict {LOC BA31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[8]}] ;# U135.A3 DQU0 +set_property -dict {LOC AY33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[9]}] ;# U135.B8 DQU1 +set_property -dict {LOC BA30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[10]}] ;# U135.C3 DQU2 +set_property -dict {LOC AW31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[11]}] ;# U135.C7 DQU3 +set_property -dict {LOC AW32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[12]}] ;# U135.C2 DQU4 +set_property -dict {LOC BB33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[13]}] ;# U135.C8 DQU5 +set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[14]}] ;# U135.D3 DQU6 +set_property -dict {LOC BA32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[15]}] ;# U135.D7 DQU7 +set_property -dict {LOC BF30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[0]}] ;# U135.G3 DQSL_T +set_property -dict {LOC BF31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[0]}] ;# U135.F3 DQSL_C +set_property -dict {LOC AY34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[1]}] ;# U135.B7 DQSU_T +set_property -dict {LOC BA34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[1]}] ;# U135.A7 DQSU_C +set_property -dict {LOC BE32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[0]}] ;# U135.E7 DML_B/DBIL_B +set_property -dict {LOC BB31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[1]}] ;# U135.E2 DMU_B/DBIU_B + +set_property -dict {LOC AT31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[16]}] ;# U136.G2 DQL0 +set_property -dict {LOC AV31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[17]}] ;# U136.F7 DQL1 +set_property -dict {LOC AV30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[18]}] ;# U136.H3 DQL2 +set_property -dict {LOC AU33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[19]}] ;# U136.H7 DQL3 +set_property -dict {LOC AU31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[20]}] ;# U136.H2 DQL4 +set_property -dict {LOC AU32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[21]}] ;# U136.H8 DQL5 +set_property -dict {LOC AW30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[22]}] ;# U136.J3 DQL6 +set_property -dict {LOC AU34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[23]}] ;# U136.J7 DQL7 +set_property -dict {LOC AT29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[24]}] ;# U136.A3 DQU0 +set_property -dict {LOC AT34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[25]}] ;# U136.B8 DQU1 +set_property -dict {LOC AT30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[26]}] ;# U136.C3 DQU2 +set_property -dict {LOC AR33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[27]}] ;# U136.C7 DQU3 +set_property -dict {LOC AR30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[28]}] ;# U136.C2 DQU4 +set_property -dict {LOC AN30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[29]}] ;# U136.C8 DQU5 +set_property -dict {LOC AP30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[30]}] ;# U136.D3 DQU6 +set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[31]}] ;# U136.D7 DQU7 +set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[2]}] ;# U136.G3 DQSL_T +set_property -dict {LOC AV29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[2]}] ;# U136.F3 DQSL_C +set_property -dict {LOC AP31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[3]}] ;# U136.B7 DQSU_T +set_property -dict {LOC AP32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[3]}] ;# U136.A7 DQSU_C +set_property -dict {LOC AV33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[2]}] ;# U136.E7 DML_B/DBIL_B +set_property -dict {LOC AR32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[3]}] ;# U136.E2 DMU_B/DBIU_B + +set_property -dict {LOC BF34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[32]}] ;# U137.G2 DQL0 +set_property -dict {LOC BF36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[33]}] ;# U137.F7 DQL1 +set_property -dict {LOC BC35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[34]}] ;# U137.H3 DQL2 +set_property -dict {LOC BE37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[35]}] ;# U137.H7 DQL3 +set_property -dict {LOC BE34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[36]}] ;# U137.H2 DQL4 +set_property -dict {LOC BD36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[37]}] ;# U137.H8 DQL5 +set_property -dict {LOC BF37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[38]}] ;# U137.J3 DQL6 +set_property -dict {LOC BC36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[39]}] ;# U137.J7 DQL7 +set_property -dict {LOC BD37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[40]}] ;# U137.A3 DQU0 +set_property -dict {LOC BE38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[41]}] ;# U137.B8 DQU1 +set_property -dict {LOC BD38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[42]}] ;# U137.C3 DQU2 +set_property -dict {LOC BD40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[43]}] ;# U137.C7 DQU3 +set_property -dict {LOC BB38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[44]}] ;# U137.C2 DQU4 +set_property -dict {LOC BB39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[45]}] ;# U137.C8 DQU5 +set_property -dict {LOC BC39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[46]}] ;# U137.D3 DQU6 +set_property -dict {LOC BC38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[47]}] ;# U137.D7 DQU7 +set_property -dict {LOC BE35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[4]}] ;# U137.G3 DQSL_T +set_property -dict {LOC BF35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[4]}] ;# U137.F3 DQSL_C +set_property -dict {LOC BE39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[5]}] ;# U137.B7 DQSU_T +set_property -dict {LOC BF39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[5]}] ;# U137.A7 DQSU_C +set_property -dict {LOC BC34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[4]}] ;# U137.E7 DML_B/DBIL_B +set_property -dict {LOC BE40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[5]}] ;# U137.E2 DMU_B/DBIU_B + +set_property -dict {LOC AW40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[48]}] ;# U138.G2 DQL0 +set_property -dict {LOC BA40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[49]}] ;# U138.F7 DQL1 +set_property -dict {LOC AY39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[50]}] ;# U138.H3 DQL2 +set_property -dict {LOC AY38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[51]}] ;# U138.H7 DQL3 +set_property -dict {LOC AY40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[52]}] ;# U138.H2 DQL4 +set_property -dict {LOC BA39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[53]}] ;# U138.H8 DQL5 +set_property -dict {LOC BB36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[54]}] ;# U138.J3 DQL6 +set_property -dict {LOC BB37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[55]}] ;# U138.J7 DQL7 +set_property -dict {LOC AV38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[56]}] ;# U138.A3 DQU0 +set_property -dict {LOC AU38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[57]}] ;# U138.B8 DQU1 +set_property -dict {LOC AU39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[58]}] ;# U138.C3 DQU2 +set_property -dict {LOC AW35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[59]}] ;# U138.C7 DQU3 +set_property -dict {LOC AU40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[60]}] ;# U138.C2 DQU4 +set_property -dict {LOC AV40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[61]}] ;# U138.C8 DQU5 +set_property -dict {LOC AW36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[62]}] ;# U138.D3 DQU6 +set_property -dict {LOC AV39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[63]}] ;# U138.D7 DQU7 +set_property -dict {LOC BA35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[6]}] ;# U138.G3 DQSL_T +set_property -dict {LOC BA36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[6]}] ;# U138.F3 DQSL_C +set_property -dict {LOC AW37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[7]}] ;# U138.B7 DQSU_T +set_property -dict {LOC AW38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[7]}] ;# U138.A7 DQSU_C +set_property -dict {LOC AY37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[6]}] ;# U138.E7 DML_B/DBIL_B +set_property -dict {LOC AV35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[7]}] ;# U138.E2 DMU_B/DBIU_B + +set_property -dict {LOC BD25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[64]}] ;# U139.G2 DQL0 +set_property -dict {LOC BD26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[65]}] ;# U139.F7 DQL1 +set_property -dict {LOC BD27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[66]}] ;# U139.H3 DQL2 +set_property -dict {LOC BE27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[67]}] ;# U139.H7 DQL3 +set_property -dict {LOC BD28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[68]}] ;# U139.H2 DQL4 +set_property -dict {LOC BE28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[69]}] ;# U139.H8 DQL5 +set_property -dict {LOC BF26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[70]}] ;# U139.J3 DQL6 +set_property -dict {LOC BF27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[71]}] ;# U139.J7 DQL7 +# set_property -dict {LOC AY27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[72]}] ;# U139.A3 DQU0 +# set_property -dict {LOC BC26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[73]}] ;# U139.B8 DQU1 +# set_property -dict {LOC BA27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[74]}] ;# U139.C3 DQU2 +# set_property -dict {LOC BB28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[75]}] ;# U139.C7 DQU3 +# set_property -dict {LOC AY28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[76]}] ;# U139.C2 DQU4 +# set_property -dict {LOC BB27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[77]}] ;# U139.C8 DQU5 +# set_property -dict {LOC BC25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[78]}] ;# U139.D3 DQU6 +# set_property -dict {LOC BC28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[79]}] ;# U139.D7 DQU7 +set_property -dict {LOC BE25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[8]}] ;# U139.G3 DQSL_T +set_property -dict {LOC BF25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[8]}] ;# U139.F3 DQSL_C +# set_property -dict {LOC BA26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[9]}] ;# U139.B7 DQSU_T +# set_property -dict {LOC BB26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[9]}] ;# U139.A7 DQSU_C +set_property -dict {LOC BE29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[8]}] ;# U139.E7 DML_B/DBIL_B +# set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[9]}] ;# U139.E2 DMU_B/DBIU_B + # BPI flash set_property -dict {LOC AM19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[4]}] set_property -dict {LOC AM18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[5]}] diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga/Makefile b/fpga/mqnic/VCU108/fpga_25g/fpga/Makefile index 19d2e9abe..0f127246f 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/VCU108/fpga_25g/fpga/Makefile @@ -139,6 +139,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie3_ultrascale_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl b/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl index 6cc943b73..2dae67146 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/VCU108/fpga_25g/fpga/config.tcl @@ -148,6 +148,12 @@ dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" dict set params RX_RAM_SIZE "32768" + +# RAM configuration +dict set params DDR_CH "2" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" # Application block configuration dict set params APP_ID "32'h00000000" @@ -200,6 +206,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie3_ultrascale_0] diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/VCU108/fpga_25g/fpga_10g/Makefile index 19d2e9abe..0f127246f 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/VCU108/fpga_25g/fpga_10g/Makefile @@ -139,6 +139,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie3_ultrascale_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl index 1aa474d58..04cba5fa7 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/VCU108/fpga_25g/fpga_10g/config.tcl @@ -148,6 +148,12 @@ dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" dict set params RX_RAM_SIZE "32768" + +# RAM configuration +dict set params DDR_CH "2" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" # Application block configuration dict set params APP_ID "32'h00000000" @@ -200,6 +206,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie3_ultrascale_0] diff --git a/fpga/mqnic/VCU108/fpga_25g/ip/ddr4_0.tcl b/fpga/mqnic/VCU108/fpga_25g/ip/ddr4_0.tcl new file mode 100644 index 000000000..c38815c16 --- /dev/null +++ b/fpga/mqnic/VCU108/fpga_25g/ip/ddr4_0.tcl @@ -0,0 +1,20 @@ + +create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 + +set_property -dict [list \ + CONFIG.System_Clock {No_Buffer} \ + CONFIG.C0.DDR4_AxiSelection {true} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_AxiIDWidth {8} \ + CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ + CONFIG.C0.DDR4_TimePeriod {833} \ + CONFIG.C0.DDR4_InputClockPeriod {3332} \ + CONFIG.C0.DDR4_MemoryType {Components} \ + CONFIG.C0.DDR4_MemoryPart {MT40A256M16GE-075E} \ + CONFIG.C0.DDR4_DataWidth {72} \ + CONFIG.C0.DDR4_DataMask {NO_DM_NO_DBI} \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_CasLatency {17} \ + CONFIG.C0.DDR4_CasWriteLatency {12} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} +] [get_ips ddr4_0] diff --git a/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v index fdd403187..b78a50cee 100644 --- a/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v @@ -112,6 +112,15 @@ module fpga # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // RAM configuration + parameter DDR_CH = 2, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 31, + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -182,6 +191,8 @@ module fpga # */ input wire clk_125mhz_p, input wire clk_125mhz_n, + input wire clk_300mhz_1_p, + input wire clk_300mhz_1_n, /* * GPIO @@ -244,6 +255,43 @@ module fpga # input wire qsfp_intl, output wire qsfp_lpmode, + /* + * DDR4 + */ + output wire [16:0] ddr4_c1_adr, + output wire [1:0] ddr4_c1_ba, + output wire [0:0] ddr4_c1_bg, + output wire [0:0] ddr4_c1_ck_t, + output wire [0:0] ddr4_c1_ck_c, + output wire [0:0] ddr4_c1_cke, + output wire [0:0] ddr4_c1_cs_n, + output wire ddr4_c1_act_n, + output wire [0:0] ddr4_c1_odt, + output wire ddr4_c1_par, + input wire ddr4_c1_alert_n, + output wire ddr4_c1_reset_n, + inout wire [71:0] ddr4_c1_dq, + inout wire [8:0] ddr4_c1_dqs_t, + inout wire [8:0] ddr4_c1_dqs_c, + inout wire [8:0] ddr4_c1_dm_dbi_n, + + output wire [16:0] ddr4_c2_adr, + output wire [1:0] ddr4_c2_ba, + output wire [0:0] ddr4_c2_bg, + output wire [0:0] ddr4_c2_ck_t, + output wire [0:0] ddr4_c2_ck_c, + output wire [0:0] ddr4_c2_cke, + output wire [0:0] ddr4_c2_cs_n, + output wire ddr4_c2_act_n, + output wire [0:0] ddr4_c2_odt, + output wire ddr4_c2_par, + input wire ddr4_c2_alert_n, + output wire ddr4_c2_reset_n, + inout wire [71:0] ddr4_c2_dq, + inout wire [8:0] ddr4_c2_dqs_t, + inout wire [8:0] ddr4_c2_dqs_c, + inout wire [8:0] ddr4_c2_dm_dbi_n, + /* * BPI Flash */ @@ -267,6 +315,9 @@ parameter IF_PTP_PERIOD_FNS = 16'h6666; // Interface configuration parameter TX_TAG_WIDTH = 16; +// RAM configuration +parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8); + // Ethernet interface configuration parameter XGMII_DATA_WIDTH = 64; parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8; @@ -1116,6 +1167,316 @@ assign led[2] = qsfp_rx_block_lock_3; assign led[3] = qsfp_rx_block_lock_4; assign led[7:4] = led_int[7:4]; +// DDR4 +wire [DDR_CH-1:0] ddr_clk; +wire [DDR_CH-1:0] ddr_rst; + +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr; +wire [DDR_CH*8-1:0] m_axi_ddr_awlen; +wire [DDR_CH*3-1:0] m_axi_ddr_awsize; +wire [DDR_CH*2-1:0] m_axi_ddr_awburst; +wire [DDR_CH-1:0] m_axi_ddr_awlock; +wire [DDR_CH*4-1:0] m_axi_ddr_awcache; +wire [DDR_CH*3-1:0] m_axi_ddr_awprot; +wire [DDR_CH*4-1:0] m_axi_ddr_awqos; +wire [DDR_CH-1:0] m_axi_ddr_awvalid; +wire [DDR_CH-1:0] m_axi_ddr_awready; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata; +wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb; +wire [DDR_CH-1:0] m_axi_ddr_wlast; +wire [DDR_CH-1:0] m_axi_ddr_wvalid; +wire [DDR_CH-1:0] m_axi_ddr_wready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid; +wire [DDR_CH*2-1:0] m_axi_ddr_bresp; +wire [DDR_CH-1:0] m_axi_ddr_bvalid; +wire [DDR_CH-1:0] m_axi_ddr_bready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr; +wire [DDR_CH*8-1:0] m_axi_ddr_arlen; +wire [DDR_CH*3-1:0] m_axi_ddr_arsize; +wire [DDR_CH*2-1:0] m_axi_ddr_arburst; +wire [DDR_CH-1:0] m_axi_ddr_arlock; +wire [DDR_CH*4-1:0] m_axi_ddr_arcache; +wire [DDR_CH*3-1:0] m_axi_ddr_arprot; +wire [DDR_CH*4-1:0] m_axi_ddr_arqos; +wire [DDR_CH-1:0] m_axi_ddr_arvalid; +wire [DDR_CH-1:0] m_axi_ddr_arready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata; +wire [DDR_CH*2-1:0] m_axi_ddr_rresp; +wire [DDR_CH-1:0] m_axi_ddr_rlast; +wire [DDR_CH-1:0] m_axi_ddr_rvalid; +wire [DDR_CH-1:0] m_axi_ddr_rready; + +wire [DDR_CH-1:0] ddr_status; + +generate + +wire clk_300mhz_1_ibufg; +wire clk_300mhz_1; + +IBUFGDS #( + .DIFF_TERM("FALSE"), + .IBUF_LOW_PWR("FALSE") +) +clk_300mhz_1_ibufg_inst ( + .O (clk_300mhz_1_ibufg), + .I (clk_300mhz_1_p), + .IB (clk_300mhz_1_n) +); + +BUFG +clk_300mhz_1_bufg_inst ( + .I(clk_300mhz_1_ibufg), + .O(clk_300mhz_1) +); + +if (DDR_ENABLE && DDR_CH > 0) begin + +ddr4_0 ddr4_c1_inst ( + .c0_sys_clk_i(clk_300mhz_1), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[0 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c1_adr), + .c0_ddr4_ba(ddr4_c1_ba), + .c0_ddr4_cke(ddr4_c1_cke), + .c0_ddr4_cs_n(ddr4_c1_cs_n), + .c0_ddr4_dq(ddr4_c1_dq), + .c0_ddr4_dqs_t(ddr4_c1_dqs_t), + .c0_ddr4_dqs_c(ddr4_c1_dqs_c), + .c0_ddr4_dm_dbi_n(ddr4_c1_dm_dbi_n), + .c0_ddr4_odt(ddr4_c1_odt), + .c0_ddr4_bg(ddr4_c1_bg), + .c0_ddr4_reset_n(ddr4_c1_reset_n), + .c0_ddr4_act_n(ddr4_c1_act_n), + .c0_ddr4_ck_t(ddr4_c1_ck_t), + .c0_ddr4_ck_c(ddr4_c1_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[0 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[0 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c1_adr = {17{1'bz}}; +assign ddr4_c1_ba = {2{1'bz}}; +assign ddr4_c1_bg = {1{1'bz}}; +assign ddr4_c1_cke = 1'bz; +assign ddr4_c1_cs_n = 1'bz; +assign ddr4_c1_act_n = 1'bz; +assign ddr4_c1_odt = 1'bz; +assign ddr4_c1_reset_n = 1'b0; +assign ddr4_c1_dq = {72{1'bz}}; +assign ddr4_c1_dqs_t = {9{1'bz}}; +assign ddr4_c1_dqs_c = {9{1'bz}}; +assign ddr4_c1_dm_dbi_n = {9{1'bz}}; + +OBUFTDS ddr4_c1_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c1_ck_t), + .OB(ddr4_c1_ck_c) +); + +assign ddr_clk = 0; +assign ddr_rst = 0; + +assign m_axi_ddr_awready = 0; +assign m_axi_ddr_wready = 0; +assign m_axi_ddr_bid = 0; +assign m_axi_ddr_bresp = 0; +assign m_axi_ddr_bvalid = 0; +assign m_axi_ddr_arready = 0; +assign m_axi_ddr_rid = 0; +assign m_axi_ddr_rdata = 0; +assign m_axi_ddr_rresp = 0; +assign m_axi_ddr_rlast = 0; +assign m_axi_ddr_rvalid = 0; + +assign ddr_status = 0; + +end + +assign ddr4_c1_par = 1'b0; + +if (DDR_ENABLE && DDR_CH > 1) begin + +ddr4_0 ddr4_c2_inst ( + .c0_sys_clk_i(clk_300mhz_1), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[1 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c2_adr), + .c0_ddr4_ba(ddr4_c2_ba), + .c0_ddr4_cke(ddr4_c2_cke), + .c0_ddr4_cs_n(ddr4_c2_cs_n), + .c0_ddr4_dq(ddr4_c2_dq), + .c0_ddr4_dqs_t(ddr4_c2_dqs_t), + .c0_ddr4_dqs_c(ddr4_c2_dqs_c), + .c0_ddr4_dm_dbi_n(ddr4_c2_dm_dbi_n), + .c0_ddr4_odt(ddr4_c2_odt), + .c0_ddr4_bg(ddr4_c2_bg), + .c0_ddr4_reset_n(ddr4_c2_reset_n), + .c0_ddr4_act_n(ddr4_c2_act_n), + .c0_ddr4_ck_t(ddr4_c2_ck_t), + .c0_ddr4_ck_c(ddr4_c2_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[1 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[1 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[1 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[1*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[1*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[1*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[1 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[1*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[1*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[1*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[1 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[1 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[1*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[1 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[1 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[1 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[1 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[1*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[1 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[1*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[1*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[1*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[1 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[1*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[1*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[1*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[1 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[1 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[1 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[1 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[1 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[1*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c2_adr = {17{1'bz}}; +assign ddr4_c2_ba = {2{1'bz}}; +assign ddr4_c2_bg = {1{1'bz}}; +assign ddr4_c2_cke = 1'bz; +assign ddr4_c2_cs_n = 1'bz; +assign ddr4_c2_act_n = 1'bz; +assign ddr4_c2_odt = 1'bz; +assign ddr4_c2_reset_n = 1'b0; +assign ddr4_c2_dq = {72{1'bz}}; +assign ddr4_c2_dqs_t = {9{1'bz}}; +assign ddr4_c2_dqs_c = {9{1'bz}}; +assign ddr4_c2_dm_dbi_n = {9{1'bz}}; + +OBUFTDS ddr4_c2_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c2_ck_t), + .OB(ddr4_c2_ck_c) +); + +end + +assign ddr4_c2_par = 1'b0; + +endgenerate + fpga_core #( // FW and board IDs .FPGA_ID(FPGA_ID), @@ -1192,6 +1553,16 @@ fpga_core #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1435,6 +1806,52 @@ core_inst ( .qsfp_intl(qsfp_intl_int), .qsfp_lpmode(qsfp_lpmode), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + /* * BPI flash */ diff --git a/fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v index d4f19ef5a..5910e50ca 100644 --- a/fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v @@ -122,6 +122,16 @@ module fpga_core # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // RAM configuration + parameter DDR_CH = 2, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 31, + parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -367,6 +377,52 @@ module fpga_core # input wire qsfp_intl, output wire qsfp_lpmode, + /* + * DDR + */ + input wire [DDR_CH-1:0] ddr_clk, + input wire [DDR_CH-1:0] ddr_rst, + + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, + output wire [DDR_CH-1:0] m_axi_ddr_awlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, + output wire [DDR_CH-1:0] m_axi_ddr_awvalid, + input wire [DDR_CH-1:0] m_axi_ddr_awready, + output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, + output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, + output wire [DDR_CH-1:0] m_axi_ddr_wlast, + output wire [DDR_CH-1:0] m_axi_ddr_wvalid, + input wire [DDR_CH-1:0] m_axi_ddr_wready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, + input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, + input wire [DDR_CH-1:0] m_axi_ddr_bvalid, + output wire [DDR_CH-1:0] m_axi_ddr_bready, + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, + output wire [DDR_CH-1:0] m_axi_ddr_arlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, + output wire [DDR_CH-1:0] m_axi_ddr_arvalid, + input wire [DDR_CH-1:0] m_axi_ddr_arready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, + input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, + input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, + input wire [DDR_CH-1:0] m_axi_ddr_rlast, + input wire [DDR_CH-1:0] m_axi_ddr_rvalid, + output wire [DDR_CH-1:0] m_axi_ddr_rready, + + input wire [DDR_CH-1:0] ddr_status, + /* * BPI Flash */ @@ -995,6 +1051,25 @@ mqnic_core_pcie_us #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .DDR_GROUP_SIZE(1), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_AWUSER_ENABLE(0), + .AXI_DDR_WUSER_ENABLE(0), + .AXI_DDR_BUSER_ENABLE(0), + .AXI_DDR_ARUSER_ENABLE(0), + .AXI_DDR_RUSER_ENABLE(0), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + .AXI_DDR_FIXED_BURST(0), + .AXI_DDR_WRAP_BURST(1), + .HBM_ENABLE(0), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1272,6 +1347,108 @@ core_inst ( .eth_rx_status(eth_rx_status), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awuser(), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wuser(), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_buser(0), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_aruser(), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_ruser(0), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + + /* + * HBM + */ + .hbm_clk(0), + .hbm_rst(0), + + .m_axi_hbm_awid(), + .m_axi_hbm_awaddr(), + .m_axi_hbm_awlen(), + .m_axi_hbm_awsize(), + .m_axi_hbm_awburst(), + .m_axi_hbm_awlock(), + .m_axi_hbm_awcache(), + .m_axi_hbm_awprot(), + .m_axi_hbm_awqos(), + .m_axi_hbm_awuser(), + .m_axi_hbm_awvalid(), + .m_axi_hbm_awready(0), + .m_axi_hbm_wdata(), + .m_axi_hbm_wstrb(), + .m_axi_hbm_wlast(), + .m_axi_hbm_wuser(), + .m_axi_hbm_wvalid(), + .m_axi_hbm_wready(0), + .m_axi_hbm_bid(0), + .m_axi_hbm_bresp(0), + .m_axi_hbm_buser(0), + .m_axi_hbm_bvalid(0), + .m_axi_hbm_bready(), + .m_axi_hbm_arid(), + .m_axi_hbm_araddr(), + .m_axi_hbm_arlen(), + .m_axi_hbm_arsize(), + .m_axi_hbm_arburst(), + .m_axi_hbm_arlock(), + .m_axi_hbm_arcache(), + .m_axi_hbm_arprot(), + .m_axi_hbm_arqos(), + .m_axi_hbm_aruser(), + .m_axi_hbm_arvalid(), + .m_axi_hbm_arready(0), + .m_axi_hbm_rid(0), + .m_axi_hbm_rdata(0), + .m_axi_hbm_rresp(0), + .m_axi_hbm_rlast(0), + .m_axi_hbm_ruser(0), + .m_axi_hbm_rvalid(0), + .m_axi_hbm_rready(), + + .hbm_status(0), + /* * Statistics input */ diff --git a/fpga/mqnic/VCU118/fpga_100g/README.md b/fpga/mqnic/VCU118/fpga_100g/README.md index 74df717d0..a32ec31fc 100644 --- a/fpga/mqnic/VCU118/fpga_100g/README.md +++ b/fpga/mqnic/VCU118/fpga_100g/README.md @@ -7,6 +7,7 @@ This design targets the Xilinx VCU118 FPGA board. * FPGA: xcvu9p-flga2104-2L-e * MAC: Xilinx 100G CMAC * PHY: 100G CAUI-4 CMAC and internal GTY transceivers +* RAM: 4 GB DDR4 2666 (2x 256M x80) ## How to build diff --git a/fpga/mqnic/VCU118/fpga_100g/fpga.xdc b/fpga/mqnic/VCU118/fpga_100g/fpga.xdc index cf87c7917..811d71c8d 100644 --- a/fpga/mqnic/VCU118/fpga_100g/fpga.xdc +++ b/fpga/mqnic/VCU118/fpga_100g/fpga.xdc @@ -17,12 +17,12 @@ set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] #create_clock -period 3.333 -name clk_300mhz [get_ports clk_300mhz_p] # 250 MHz -#set_property -dict {LOC E12 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_1_p] -#set_property -dict {LOC D12 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_1_n] +set_property -dict {LOC E12 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_1_p] +set_property -dict {LOC D12 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_1_n] #create_clock -period 4 -name clk_250mhz_1 [get_ports clk_250mhz_1_p] -#set_property -dict {LOC AW26 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_2_p] -#set_property -dict {LOC AW27 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_2_n] +set_property -dict {LOC AW26 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_2_p] +set_property -dict {LOC AW27 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_2_n] #create_clock -period 4 -name clk_250mhz_2 [get_ports clk_250mhz_2_p] # 125 MHz @@ -289,6 +289,302 @@ create_clock -period 10 -name pcie_mgt_refclk_2 [get_ports pcie_refclk_2_p] set_false_path -from [get_ports {pcie_reset_n}] set_input_delay 0 [get_ports {pcie_reset_n}] +# DDR4 C1 +# 5x MT40A256M16GE-075E +set_property -dict {LOC D14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}] +set_property -dict {LOC B15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}] +set_property -dict {LOC B16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}] +set_property -dict {LOC C14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}] +set_property -dict {LOC C15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}] +set_property -dict {LOC A13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}] +set_property -dict {LOC A14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}] +set_property -dict {LOC A15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}] +set_property -dict {LOC A16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}] +set_property -dict {LOC B12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}] +set_property -dict {LOC C12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}] +set_property -dict {LOC B13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}] +set_property -dict {LOC C13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}] +set_property -dict {LOC D15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}] +set_property -dict {LOC H14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}] +set_property -dict {LOC H15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}] +set_property -dict {LOC F15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}] +set_property -dict {LOC G15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}] +set_property -dict {LOC G13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}] +set_property -dict {LOC H13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}] +set_property -dict {LOC F14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t}] +set_property -dict {LOC E14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c}] +set_property -dict {LOC A10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke}] +set_property -dict {LOC F13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n}] +set_property -dict {LOC E13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}] +set_property -dict {LOC C8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt}] +set_property -dict {LOC G10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}] +set_property -dict {LOC N20 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}] +set_property -dict {LOC R17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_alert_n}] +set_property -dict {LOC A20 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_ten}] + +set_property -dict {LOC F11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] ;# U60.G2 DQL0 +set_property -dict {LOC E11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] ;# U60.F7 DQL1 +set_property -dict {LOC F10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] ;# U60.H3 DQL2 +set_property -dict {LOC F9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] ;# U60.H7 DQL3 +set_property -dict {LOC H12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] ;# U60.H2 DQL4 +set_property -dict {LOC G12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] ;# U60.H8 DQL5 +set_property -dict {LOC E9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] ;# U60.J3 DQL6 +set_property -dict {LOC D9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] ;# U60.J7 DQL7 +set_property -dict {LOC R19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] ;# U60.A3 DQU0 +set_property -dict {LOC P19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] ;# U60.B8 DQU1 +set_property -dict {LOC M18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] ;# U60.C3 DQU2 +set_property -dict {LOC M17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] ;# U60.C7 DQU3 +set_property -dict {LOC N19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] ;# U60.C2 DQU4 +set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] ;# U60.C8 DQU5 +set_property -dict {LOC N17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] ;# U60.D3 DQU6 +set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] ;# U60.D7 DQU7 +set_property -dict {LOC D11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] ;# U60.G3 DQSL_T +set_property -dict {LOC D10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] ;# U60.F3 DQSL_C +set_property -dict {LOC P17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] ;# U60.B7 DQSU_T +set_property -dict {LOC P16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] ;# U60.A7 DQSU_C +set_property -dict {LOC G11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[0]}] ;# U60.E7 DML_B/DBIL_B +set_property -dict {LOC R18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[1]}] ;# U60.E2 DMU_B/DBIU_B + +set_property -dict {LOC L16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] ;# U61.G2 DQL0 +set_property -dict {LOC K16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] ;# U61.F7 DQL1 +set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] ;# U61.H3 DQL2 +set_property -dict {LOC K18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] ;# U61.H7 DQL3 +set_property -dict {LOC J17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] ;# U61.H2 DQL4 +set_property -dict {LOC H17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] ;# U61.H8 DQL5 +set_property -dict {LOC H19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] ;# U61.J3 DQL6 +set_property -dict {LOC H18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] ;# U61.J7 DQL7 +set_property -dict {LOC F19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] ;# U61.A3 DQU0 +set_property -dict {LOC F18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] ;# U61.B8 DQU1 +set_property -dict {LOC E19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] ;# U61.C3 DQU2 +set_property -dict {LOC E18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] ;# U61.C7 DQU3 +set_property -dict {LOC G20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] ;# U61.C2 DQU4 +set_property -dict {LOC F20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] ;# U61.C8 DQU5 +set_property -dict {LOC E17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] ;# U61.D3 DQU6 +set_property -dict {LOC D16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] ;# U61.D7 DQU7 +set_property -dict {LOC K19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] ;# U61.G3 DQSL_T +set_property -dict {LOC J19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] ;# U61.F3 DQSL_C +set_property -dict {LOC F16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] ;# U61.B7 DQSU_T +set_property -dict {LOC E16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] ;# U61.A7 DQSU_C +set_property -dict {LOC K17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[2]}] ;# U61.E7 DML_B/DBIL_B +set_property -dict {LOC G18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[3]}] ;# U61.E2 DMU_B/DBIU_B + +set_property -dict {LOC D17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] ;# U62.G2 DQL0 +set_property -dict {LOC C17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] ;# U62.F7 DQL1 +set_property -dict {LOC C19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] ;# U62.H3 DQL2 +set_property -dict {LOC C18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] ;# U62.H7 DQL3 +set_property -dict {LOC D20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] ;# U62.H2 DQL4 +set_property -dict {LOC D19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] ;# U62.H8 DQL5 +set_property -dict {LOC C20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] ;# U62.J3 DQL6 +set_property -dict {LOC B20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] ;# U62.J7 DQL7 +set_property -dict {LOC N23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] ;# U62.A3 DQU0 +set_property -dict {LOC M23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] ;# U62.B8 DQU1 +set_property -dict {LOC R21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] ;# U62.C3 DQU2 +set_property -dict {LOC P21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] ;# U62.C7 DQU3 +set_property -dict {LOC R22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] ;# U62.C2 DQU4 +set_property -dict {LOC P22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] ;# U62.C8 DQU5 +set_property -dict {LOC T23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] ;# U62.D3 DQU6 +set_property -dict {LOC R23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] ;# U62.D7 DQU7 +set_property -dict {LOC A19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] ;# U62.G3 DQSL_T +set_property -dict {LOC A18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] ;# U62.F3 DQSL_C +set_property -dict {LOC N22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] ;# U62.B7 DQSU_T +set_property -dict {LOC M22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] ;# U62.A7 DQSU_C +set_property -dict {LOC B18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[4]}] ;# U62.E7 DML_B/DBIL_B +set_property -dict {LOC P20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[5]}] ;# U62.E2 DMU_B/DBIU_B + +set_property -dict {LOC K24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] ;# U63.G2 DQL0 +set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] ;# U63.F7 DQL1 +set_property -dict {LOC M21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] ;# U63.H3 DQL2 +set_property -dict {LOC L21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] ;# U63.H7 DQL3 +set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] ;# U63.H2 DQL4 +set_property -dict {LOC J21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] ;# U63.H8 DQL5 +set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] ;# U63.J3 DQL6 +set_property -dict {LOC J22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] ;# U63.J7 DQL7 +set_property -dict {LOC H23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] ;# U63.A3 DQU0 +set_property -dict {LOC H22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] ;# U63.B8 DQU1 +set_property -dict {LOC E23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] ;# U63.C3 DQU2 +set_property -dict {LOC E22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] ;# U63.C7 DQU3 +set_property -dict {LOC F21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] ;# U63.C2 DQU4 +set_property -dict {LOC E21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] ;# U63.C8 DQU5 +set_property -dict {LOC F24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] ;# U63.D3 DQU6 +set_property -dict {LOC F23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] ;# U63.D7 DQU7 +set_property -dict {LOC M20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] ;# U63.G3 DQSL_T +set_property -dict {LOC L20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] ;# U63.F3 DQSL_C +set_property -dict {LOC H24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] ;# U63.B7 DQSU_T +set_property -dict {LOC G23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] ;# U63.A7 DQSU_C +set_property -dict {LOC L23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[6]}] ;# U63.E7 DML_B/DBIL_B +set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[7]}] ;# U63.E2 DMU_B/DBIU_B + +set_property -dict {LOC A24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}] ;# U64.G2 DQL0 +set_property -dict {LOC A23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}] ;# U64.F7 DQL1 +set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}] ;# U64.H3 DQL2 +set_property -dict {LOC C23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}] ;# U64.H7 DQL3 +set_property -dict {LOC B23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}] ;# U64.H2 DQL4 +set_property -dict {LOC B22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}] ;# U64.H8 DQL5 +set_property -dict {LOC B21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}] ;# U64.J3 DQL6 +set_property -dict {LOC A21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}] ;# U64.J7 DQL7 +# set_property -dict {LOC D7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[72]}] ;# U64.A3 DQU0 +# set_property -dict {LOC C7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[73]}] ;# U64.B8 DQU1 +# set_property -dict {LOC B8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[74]}] ;# U64.C3 DQU2 +# set_property -dict {LOC B7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[75]}] ;# U64.C7 DQU3 +# set_property -dict {LOC C10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[76]}] ;# U64.C2 DQU4 +# set_property -dict {LOC B10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[77]}] ;# U64.C8 DQU5 +# set_property -dict {LOC B11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[78]}] ;# U64.D3 DQU6 +# set_property -dict {LOC A11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[79]}] ;# U64.D7 DQU7 +set_property -dict {LOC D22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}] ;# U64.G3 DQSL_T +set_property -dict {LOC C22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}] ;# U64.F3 DQSL_C +# set_property -dict {LOC A9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}] ;# U64.B7 DQSU_T +# set_property -dict {LOC A8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}] ;# U64.A7 DQSU_C +set_property -dict {LOC E24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[8]}] ;# U64.E7 DML_B/DBIL_B +# set_property -dict {LOC C9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[9]}] ;# U64.E2 DMU_B/DBIU_B + +# DDR4 C2 +# 5x MT40A256M16GE-075E +set_property -dict {LOC AM27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[0]}] +set_property -dict {LOC AL27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[1]}] +set_property -dict {LOC AP26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[2]}] +set_property -dict {LOC AP25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[3]}] +set_property -dict {LOC AN28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[4]}] +set_property -dict {LOC AM28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[5]}] +set_property -dict {LOC AP28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[6]}] +set_property -dict {LOC AP27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[7]}] +set_property -dict {LOC AN26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[8]}] +set_property -dict {LOC AM26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[9]}] +set_property -dict {LOC AR28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[10]}] +set_property -dict {LOC AR27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[11]}] +set_property -dict {LOC AV25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[12]}] +set_property -dict {LOC AT25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[13]}] +set_property -dict {LOC AV28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[14]}] +set_property -dict {LOC AU26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[15]}] +set_property -dict {LOC AV26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[16]}] +set_property -dict {LOC AR25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[0]}] +set_property -dict {LOC AU28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[1]}] +set_property -dict {LOC AU27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[0]}] +set_property -dict {LOC AT26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t}] +set_property -dict {LOC AT27 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c}] +set_property -dict {LOC AW28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke}] +set_property -dict {LOC AY29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n}] +set_property -dict {LOC AN25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_act_n}] +set_property -dict {LOC BB29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt}] +set_property -dict {LOC BF29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_par}] +set_property -dict {LOC BD35 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_reset_n}] +set_property -dict {LOC AR29 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_alert_n}] +set_property -dict {LOC AY35 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_ten}] + +set_property -dict {LOC BD30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[0]}] ;# U135.G2 DQL0 +set_property -dict {LOC BE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[1]}] ;# U135.F7 DQL1 +set_property -dict {LOC BD32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[2]}] ;# U135.H3 DQL2 +set_property -dict {LOC BE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[3]}] ;# U135.H7 DQL3 +set_property -dict {LOC BC33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[4]}] ;# U135.H2 DQL4 +set_property -dict {LOC BD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[5]}] ;# U135.H8 DQL5 +set_property -dict {LOC BC31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[6]}] ;# U135.J3 DQL6 +set_property -dict {LOC BD31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[7]}] ;# U135.J7 DQL7 +set_property -dict {LOC BA32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[8]}] ;# U135.A3 DQU0 +set_property -dict {LOC BB33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[9]}] ;# U135.B8 DQU1 +set_property -dict {LOC BA30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[10]}] ;# U135.C3 DQU2 +set_property -dict {LOC BA31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[11]}] ;# U135.C7 DQU3 +set_property -dict {LOC AW31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[12]}] ;# U135.C2 DQU4 +set_property -dict {LOC AW32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[13]}] ;# U135.C8 DQU5 +set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[14]}] ;# U135.D3 DQU6 +set_property -dict {LOC AY33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[15]}] ;# U135.D7 DQU7 +set_property -dict {LOC BF30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[0]}] ;# U135.G3 DQSL_T +set_property -dict {LOC BF31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[0]}] ;# U135.F3 DQSL_C +set_property -dict {LOC AY34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[1]}] ;# U135.B7 DQSU_T +set_property -dict {LOC BA34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[1]}] ;# U135.A7 DQSU_C +set_property -dict {LOC BE32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[0]}] ;# U135.E7 DML_B/DBIL_B +set_property -dict {LOC BB31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[1]}] ;# U135.E2 DMU_B/DBIU_B + +set_property -dict {LOC AV30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[16]}] ;# U136.G2 DQL0 +set_property -dict {LOC AW30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[17]}] ;# U136.F7 DQL1 +set_property -dict {LOC AU33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[18]}] ;# U136.H3 DQL2 +set_property -dict {LOC AU34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[19]}] ;# U136.H7 DQL3 +set_property -dict {LOC AT31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[20]}] ;# U136.H2 DQL4 +set_property -dict {LOC AU32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[21]}] ;# U136.H8 DQL5 +set_property -dict {LOC AU31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[22]}] ;# U136.J3 DQL6 +set_property -dict {LOC AV31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[23]}] ;# U136.J7 DQL7 +set_property -dict {LOC AR33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[24]}] ;# U136.A3 DQU0 +set_property -dict {LOC AT34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[25]}] ;# U136.B8 DQU1 +set_property -dict {LOC AT29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[26]}] ;# U136.C3 DQU2 +set_property -dict {LOC AT30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[27]}] ;# U136.C7 DQU3 +set_property -dict {LOC AP30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[28]}] ;# U136.C2 DQU4 +set_property -dict {LOC AR30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[29]}] ;# U136.C8 DQU5 +set_property -dict {LOC AN30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[30]}] ;# U136.D3 DQU6 +set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[31]}] ;# U136.D7 DQU7 +set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[2]}] ;# U136.G3 DQSL_T +set_property -dict {LOC AV29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[2]}] ;# U136.F3 DQSL_C +set_property -dict {LOC AP31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[3]}] ;# U136.B7 DQSU_T +set_property -dict {LOC AP32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[3]}] ;# U136.A7 DQSU_C +set_property -dict {LOC AV33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[2]}] ;# U136.E7 DML_B/DBIL_B +set_property -dict {LOC AR32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[3]}] ;# U136.E2 DMU_B/DBIU_B + +set_property -dict {LOC BE34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[32]}] ;# U137.G2 DQL0 +set_property -dict {LOC BF34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[33]}] ;# U137.F7 DQL1 +set_property -dict {LOC BC35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[34]}] ;# U137.H3 DQL2 +set_property -dict {LOC BC36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[35]}] ;# U137.H7 DQL3 +set_property -dict {LOC BD36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[36]}] ;# U137.H2 DQL4 +set_property -dict {LOC BE37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[37]}] ;# U137.H8 DQL5 +set_property -dict {LOC BF36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[38]}] ;# U137.J3 DQL6 +set_property -dict {LOC BF37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[39]}] ;# U137.J7 DQL7 +set_property -dict {LOC BD37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[40]}] ;# U137.A3 DQU0 +set_property -dict {LOC BE38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[41]}] ;# U137.B8 DQU1 +set_property -dict {LOC BC39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[42]}] ;# U137.C3 DQU2 +set_property -dict {LOC BD40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[43]}] ;# U137.C7 DQU3 +set_property -dict {LOC BB38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[44]}] ;# U137.C2 DQU4 +set_property -dict {LOC BB39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[45]}] ;# U137.C8 DQU5 +set_property -dict {LOC BC38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[46]}] ;# U137.D3 DQU6 +set_property -dict {LOC BD38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[47]}] ;# U137.D7 DQU7 +set_property -dict {LOC BE35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[4]}] ;# U137.G3 DQSL_T +set_property -dict {LOC BF35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[4]}] ;# U137.F3 DQSL_C +set_property -dict {LOC BE39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[5]}] ;# U137.B7 DQSU_T +set_property -dict {LOC BF39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[5]}] ;# U137.A7 DQSU_C +set_property -dict {LOC BC34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[4]}] ;# U137.E7 DML_B/DBIL_B +set_property -dict {LOC BE40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[5]}] ;# U137.E2 DMU_B/DBIU_B + +set_property -dict {LOC BB36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[48]}] ;# U138.G2 DQL0 +set_property -dict {LOC BB37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[49]}] ;# U138.F7 DQL1 +set_property -dict {LOC BA39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[50]}] ;# U138.H3 DQL2 +set_property -dict {LOC BA40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[51]}] ;# U138.H7 DQL3 +set_property -dict {LOC AW40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[52]}] ;# U138.H2 DQL4 +set_property -dict {LOC AY40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[53]}] ;# U138.H8 DQL5 +set_property -dict {LOC AY38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[54]}] ;# U138.J3 DQL6 +set_property -dict {LOC AY39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[55]}] ;# U138.J7 DQL7 +set_property -dict {LOC AW35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[56]}] ;# U138.A3 DQU0 +set_property -dict {LOC AW36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[57]}] ;# U138.B8 DQU1 +set_property -dict {LOC AU40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[58]}] ;# U138.C3 DQU2 +set_property -dict {LOC AV40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[59]}] ;# U138.C7 DQU3 +set_property -dict {LOC AU38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[60]}] ;# U138.C2 DQU4 +set_property -dict {LOC AU39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[61]}] ;# U138.C8 DQU5 +set_property -dict {LOC AV38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[62]}] ;# U138.D3 DQU6 +set_property -dict {LOC AV39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[63]}] ;# U138.D7 DQU7 +set_property -dict {LOC BA35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[6]}] ;# U138.G3 DQSL_T +set_property -dict {LOC BA36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[6]}] ;# U138.F3 DQSL_C +set_property -dict {LOC AW37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[7]}] ;# U138.B7 DQSU_T +set_property -dict {LOC AW38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[7]}] ;# U138.A7 DQSU_C +set_property -dict {LOC AY37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[6]}] ;# U138.E7 DML_B/DBIL_B +set_property -dict {LOC AV35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[7]}] ;# U138.E2 DMU_B/DBIU_B + +set_property -dict {LOC BF26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[64]}] ;# U139.G2 DQL0 +set_property -dict {LOC BF27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[65]}] ;# U139.F7 DQL1 +set_property -dict {LOC BD28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[66]}] ;# U139.H3 DQL2 +set_property -dict {LOC BE28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[67]}] ;# U139.H7 DQL3 +set_property -dict {LOC BD27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[68]}] ;# U139.H2 DQL4 +set_property -dict {LOC BE27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[69]}] ;# U139.H8 DQL5 +set_property -dict {LOC BD25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[70]}] ;# U139.J3 DQL6 +set_property -dict {LOC BD26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[71]}] ;# U139.J7 DQL7 +# set_property -dict {LOC BC25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[72]}] ;# U139.A3 DQU0 +# set_property -dict {LOC BC26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[73]}] ;# U139.B8 DQU1 +# set_property -dict {LOC BB28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[74]}] ;# U139.C3 DQU2 +# set_property -dict {LOC BC28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[75]}] ;# U139.C7 DQU3 +# set_property -dict {LOC AY27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[76]}] ;# U139.C2 DQU4 +# set_property -dict {LOC AY28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[77]}] ;# U139.C8 DQU5 +# set_property -dict {LOC BA27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[78]}] ;# U139.D3 DQU6 +# set_property -dict {LOC BB27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[79]}] ;# U139.D7 DQU7 +set_property -dict {LOC BE25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[8]}] ;# U139.G3 DQSL_T +set_property -dict {LOC BF25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[8]}] ;# U139.F3 DQSL_C +# set_property -dict {LOC BA26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[9]}] ;# U139.B7 DQSU_T +# set_property -dict {LOC BB26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[9]}] ;# U139.A7 DQSU_C +set_property -dict {LOC BE29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[8]}] ;# U139.E7 DML_B/DBIL_B +# set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[9]}] ;# U139.E2 DMU_B/DBIU_B + # QSPI flash set_property -dict {LOC AM19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[0]}] set_property -dict {LOC AM18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[1]}] diff --git a/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile b/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile index 738aade00..099b76790 100644 --- a/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile @@ -119,6 +119,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/cmac_usplus_0.tcl IP_TCL_FILES += ip/cmac_usplus_1.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl b/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl index 00cec4d1c..f909a9235 100644 --- a/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/VCU118/fpga_100g/fpga/config.tcl @@ -136,6 +136,12 @@ dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "131072" dict set params RX_RAM_SIZE "131072" + +# RAM configuration +dict set params DDR_CH "2" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" # Application block configuration dict set params APP_ID "32'h00000000" @@ -187,6 +193,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/VCU118/fpga_100g/ip/ddr4_0.tcl b/fpga/mqnic/VCU118/fpga_100g/ip/ddr4_0.tcl new file mode 100644 index 000000000..cff759015 --- /dev/null +++ b/fpga/mqnic/VCU118/fpga_100g/ip/ddr4_0.tcl @@ -0,0 +1,19 @@ + +create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 + +set_property -dict [list \ + CONFIG.C0.DDR4_AxiSelection {true} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_AxiIDWidth {8} \ + CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ + CONFIG.C0.DDR4_TimePeriod {750} \ + CONFIG.C0.DDR4_InputClockPeriod {4000} \ + CONFIG.C0.DDR4_MemoryType {Components} \ + CONFIG.C0.DDR4_MemoryPart {MT40A256M16GE-075E} \ + CONFIG.C0.DDR4_DataWidth {72} \ + CONFIG.C0.DDR4_DataMask {NO_DM_NO_DBI} \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_CasLatency {18} \ + CONFIG.C0.DDR4_CasWriteLatency {14} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} +] [get_ips ddr4_0] diff --git a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v index 9a7e3e12c..251357016 100644 --- a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v @@ -109,6 +109,15 @@ module fpga # parameter TX_RAM_SIZE = 131072, parameter RX_RAM_SIZE = 131072, + // RAM configuration + parameter DDR_CH = 2, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 31, + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -178,6 +187,10 @@ module fpga # */ input wire clk_125mhz_p, input wire clk_125mhz_n, + input wire clk_250mhz_1_p, + input wire clk_250mhz_1_n, + input wire clk_250mhz_2_p, + input wire clk_250mhz_2_n, /* * GPIO @@ -270,6 +283,45 @@ module fpga # input wire qsfp2_intl, output wire qsfp2_lpmode, + /* + * DDR4 + */ + output wire [16:0] ddr4_c1_adr, + output wire [1:0] ddr4_c1_ba, + output wire [0:0] ddr4_c1_bg, + output wire ddr4_c1_ck_t, + output wire ddr4_c1_ck_c, + output wire ddr4_c1_cke, + output wire ddr4_c1_cs_n, + output wire ddr4_c1_act_n, + output wire ddr4_c1_odt, + output wire ddr4_c1_par, + input wire ddr4_c1_alert_n, + output wire ddr4_c1_reset_n, + output wire ddr4_c1_ten, + inout wire [71:0] ddr4_c1_dq, + inout wire [8:0] ddr4_c1_dqs_t, + inout wire [8:0] ddr4_c1_dqs_c, + inout wire [8:0] ddr4_c1_dm_dbi_n, + + output wire [16:0] ddr4_c2_adr, + output wire [1:0] ddr4_c2_ba, + output wire [0:0] ddr4_c2_bg, + output wire ddr4_c2_ck_t, + output wire ddr4_c2_ck_c, + output wire ddr4_c2_cke, + output wire ddr4_c2_cs_n, + output wire ddr4_c2_act_n, + output wire ddr4_c2_odt, + output wire ddr4_c2_par, + input wire ddr4_c2_alert_n, + output wire ddr4_c2_reset_n, + output wire ddr4_c2_ten, + inout wire [71:0] ddr4_c2_dq, + inout wire [8:0] ddr4_c2_dqs_t, + inout wire [8:0] ddr4_c2_dqs_c, + inout wire [8:0] ddr4_c2_dm_dbi_n, + /* * QSPI */ @@ -287,6 +339,9 @@ parameter PTP_SEPARATE_RX_CLOCK = 1; // Interface configuration parameter TX_TAG_WIDTH = 16; +// RAM configuration +parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8); + // Ethernet interface configuration parameter AXIS_ETH_DATA_WIDTH = 512; parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; @@ -1746,6 +1801,301 @@ assign led[0] = qsfp1_rx_status; assign led[1] = qsfp2_rx_status; assign led[7:2] = led_int[7:2]; +// DDR4 +wire [DDR_CH-1:0] ddr_clk; +wire [DDR_CH-1:0] ddr_rst; + +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr; +wire [DDR_CH*8-1:0] m_axi_ddr_awlen; +wire [DDR_CH*3-1:0] m_axi_ddr_awsize; +wire [DDR_CH*2-1:0] m_axi_ddr_awburst; +wire [DDR_CH-1:0] m_axi_ddr_awlock; +wire [DDR_CH*4-1:0] m_axi_ddr_awcache; +wire [DDR_CH*3-1:0] m_axi_ddr_awprot; +wire [DDR_CH*4-1:0] m_axi_ddr_awqos; +wire [DDR_CH-1:0] m_axi_ddr_awvalid; +wire [DDR_CH-1:0] m_axi_ddr_awready; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata; +wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb; +wire [DDR_CH-1:0] m_axi_ddr_wlast; +wire [DDR_CH-1:0] m_axi_ddr_wvalid; +wire [DDR_CH-1:0] m_axi_ddr_wready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid; +wire [DDR_CH*2-1:0] m_axi_ddr_bresp; +wire [DDR_CH-1:0] m_axi_ddr_bvalid; +wire [DDR_CH-1:0] m_axi_ddr_bready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr; +wire [DDR_CH*8-1:0] m_axi_ddr_arlen; +wire [DDR_CH*3-1:0] m_axi_ddr_arsize; +wire [DDR_CH*2-1:0] m_axi_ddr_arburst; +wire [DDR_CH-1:0] m_axi_ddr_arlock; +wire [DDR_CH*4-1:0] m_axi_ddr_arcache; +wire [DDR_CH*3-1:0] m_axi_ddr_arprot; +wire [DDR_CH*4-1:0] m_axi_ddr_arqos; +wire [DDR_CH-1:0] m_axi_ddr_arvalid; +wire [DDR_CH-1:0] m_axi_ddr_arready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata; +wire [DDR_CH*2-1:0] m_axi_ddr_rresp; +wire [DDR_CH-1:0] m_axi_ddr_rlast; +wire [DDR_CH-1:0] m_axi_ddr_rvalid; +wire [DDR_CH-1:0] m_axi_ddr_rready; + +wire [DDR_CH-1:0] ddr_status; + +generate + +if (DDR_ENABLE && DDR_CH > 0) begin + +ddr4_0 ddr4_c1_inst ( + .c0_sys_clk_p(clk_250mhz_1_p), + .c0_sys_clk_n(clk_250mhz_1_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[0 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c1_adr), + .c0_ddr4_ba(ddr4_c1_ba), + .c0_ddr4_cke(ddr4_c1_cke), + .c0_ddr4_cs_n(ddr4_c1_cs_n), + .c0_ddr4_dq(ddr4_c1_dq), + .c0_ddr4_dqs_t(ddr4_c1_dqs_t), + .c0_ddr4_dqs_c(ddr4_c1_dqs_c), + .c0_ddr4_dm_dbi_n(ddr4_c1_dm_dbi_n), + .c0_ddr4_odt(ddr4_c1_odt), + .c0_ddr4_bg(ddr4_c1_bg), + .c0_ddr4_reset_n(ddr4_c1_reset_n), + .c0_ddr4_act_n(ddr4_c1_act_n), + .c0_ddr4_ck_t(ddr4_c1_ck_t), + .c0_ddr4_ck_c(ddr4_c1_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[0 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[0 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c1_adr = {17{1'bz}}; +assign ddr4_c1_ba = {2{1'bz}}; +assign ddr4_c1_bg = {1{1'bz}}; +assign ddr4_c1_cke = 1'bz; +assign ddr4_c1_cs_n = 1'bz; +assign ddr4_c1_act_n = 1'bz; +assign ddr4_c1_odt = 1'bz; +assign ddr4_c1_reset_n = 1'b0; +assign ddr4_c1_dq = {72{1'bz}}; +assign ddr4_c1_dqs_t = {9{1'bz}}; +assign ddr4_c1_dqs_c = {9{1'bz}}; +assign ddr4_c1_dm_dbi_n = {9{1'bz}}; + +OBUFTDS ddr4_c1_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c1_ck_t), + .OB(ddr4_c1_ck_c) +); + +assign ddr_clk = 0; +assign ddr_rst = 0; + +assign m_axi_ddr_awready = 0; +assign m_axi_ddr_wready = 0; +assign m_axi_ddr_bid = 0; +assign m_axi_ddr_bresp = 0; +assign m_axi_ddr_bvalid = 0; +assign m_axi_ddr_arready = 0; +assign m_axi_ddr_rid = 0; +assign m_axi_ddr_rdata = 0; +assign m_axi_ddr_rresp = 0; +assign m_axi_ddr_rlast = 0; +assign m_axi_ddr_rvalid = 0; + +assign ddr_status = 0; + +end + +assign ddr4_c1_par = 1'b0; +assign ddr4_c1_ten = 1'b0; + +if (DDR_ENABLE && DDR_CH > 1) begin + +ddr4_0 ddr4_c2_inst ( + .c0_sys_clk_p(clk_250mhz_2_p), + .c0_sys_clk_n(clk_250mhz_2_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[1 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c2_adr), + .c0_ddr4_ba(ddr4_c2_ba), + .c0_ddr4_cke(ddr4_c2_cke), + .c0_ddr4_cs_n(ddr4_c2_cs_n), + .c0_ddr4_dq(ddr4_c2_dq), + .c0_ddr4_dqs_t(ddr4_c2_dqs_t), + .c0_ddr4_dqs_c(ddr4_c2_dqs_c), + .c0_ddr4_dm_dbi_n(ddr4_c2_dm_dbi_n), + .c0_ddr4_odt(ddr4_c2_odt), + .c0_ddr4_bg(ddr4_c2_bg), + .c0_ddr4_reset_n(ddr4_c2_reset_n), + .c0_ddr4_act_n(ddr4_c2_act_n), + .c0_ddr4_ck_t(ddr4_c2_ck_t), + .c0_ddr4_ck_c(ddr4_c2_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[1 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[1 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[1 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[1*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[1*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[1*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[1 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[1*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[1*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[1*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[1 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[1 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[1*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[1 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[1 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[1 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[1 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[1*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[1 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[1*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[1*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[1*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[1 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[1*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[1*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[1*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[1 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[1 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[1 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[1 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[1 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[1*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c2_adr = {17{1'bz}}; +assign ddr4_c2_ba = {2{1'bz}}; +assign ddr4_c2_bg = {1{1'bz}}; +assign ddr4_c2_cke = 1'bz; +assign ddr4_c2_cs_n = 1'bz; +assign ddr4_c2_act_n = 1'bz; +assign ddr4_c2_odt = 1'bz; +assign ddr4_c2_reset_n = 1'b0; +assign ddr4_c2_dq = {72{1'bz}}; +assign ddr4_c2_dqs_t = {9{1'bz}}; +assign ddr4_c2_dqs_c = {9{1'bz}}; +assign ddr4_c2_dm_dbi_n = {9{1'bz}}; + +OBUFTDS ddr4_c2_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c2_ck_t), + .OB(ddr4_c2_ck_c) +); + +end + +assign ddr4_c2_par = 1'b0; +assign ddr4_c2_ten = 1'b0; + +endgenerate + fpga_core #( // FW and board IDs .FPGA_ID(FPGA_ID), @@ -1820,6 +2170,16 @@ fpga_core #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -2062,6 +2422,52 @@ core_inst ( .qsfp2_intl(qsfp2_intl_int), .qsfp2_lpmode(qsfp2_lpmode), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + /* * QSPI flash */ diff --git a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v index dffdba871..5a81f72fa 100644 --- a/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v @@ -115,6 +115,16 @@ module fpga_core # parameter TX_RAM_SIZE = 131072, parameter RX_RAM_SIZE = 131072, + // RAM configuration + parameter DDR_CH = 2, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 31, + parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -371,6 +381,52 @@ module fpga_core # input wire qsfp2_intl, output wire qsfp2_lpmode, + /* + * DDR + */ + input wire [DDR_CH-1:0] ddr_clk, + input wire [DDR_CH-1:0] ddr_rst, + + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, + output wire [DDR_CH-1:0] m_axi_ddr_awlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, + output wire [DDR_CH-1:0] m_axi_ddr_awvalid, + input wire [DDR_CH-1:0] m_axi_ddr_awready, + output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, + output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, + output wire [DDR_CH-1:0] m_axi_ddr_wlast, + output wire [DDR_CH-1:0] m_axi_ddr_wvalid, + input wire [DDR_CH-1:0] m_axi_ddr_wready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, + input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, + input wire [DDR_CH-1:0] m_axi_ddr_bvalid, + output wire [DDR_CH-1:0] m_axi_ddr_bready, + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, + output wire [DDR_CH-1:0] m_axi_ddr_arlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, + output wire [DDR_CH-1:0] m_axi_ddr_arvalid, + input wire [DDR_CH-1:0] m_axi_ddr_arready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, + input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, + input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, + input wire [DDR_CH-1:0] m_axi_ddr_rlast, + input wire [DDR_CH-1:0] m_axi_ddr_rvalid, + output wire [DDR_CH-1:0] m_axi_ddr_rready, + + input wire [DDR_CH-1:0] ddr_status, + /* * QSPI flash */ @@ -871,6 +927,25 @@ mqnic_core_pcie_us #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .DDR_GROUP_SIZE(1), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_AWUSER_ENABLE(0), + .AXI_DDR_WUSER_ENABLE(0), + .AXI_DDR_BUSER_ENABLE(0), + .AXI_DDR_ARUSER_ENABLE(0), + .AXI_DDR_RUSER_ENABLE(0), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + .AXI_DDR_FIXED_BURST(0), + .AXI_DDR_WRAP_BURST(1), + .HBM_ENABLE(0), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1148,6 +1223,108 @@ core_inst ( .eth_rx_status(eth_rx_status), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awuser(), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wuser(), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_buser(0), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_aruser(), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_ruser(0), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + + /* + * HBM + */ + .hbm_clk(0), + .hbm_rst(0), + + .m_axi_hbm_awid(), + .m_axi_hbm_awaddr(), + .m_axi_hbm_awlen(), + .m_axi_hbm_awsize(), + .m_axi_hbm_awburst(), + .m_axi_hbm_awlock(), + .m_axi_hbm_awcache(), + .m_axi_hbm_awprot(), + .m_axi_hbm_awqos(), + .m_axi_hbm_awuser(), + .m_axi_hbm_awvalid(), + .m_axi_hbm_awready(0), + .m_axi_hbm_wdata(), + .m_axi_hbm_wstrb(), + .m_axi_hbm_wlast(), + .m_axi_hbm_wuser(), + .m_axi_hbm_wvalid(), + .m_axi_hbm_wready(0), + .m_axi_hbm_bid(0), + .m_axi_hbm_bresp(0), + .m_axi_hbm_buser(0), + .m_axi_hbm_bvalid(0), + .m_axi_hbm_bready(), + .m_axi_hbm_arid(), + .m_axi_hbm_araddr(), + .m_axi_hbm_arlen(), + .m_axi_hbm_arsize(), + .m_axi_hbm_arburst(), + .m_axi_hbm_arlock(), + .m_axi_hbm_arcache(), + .m_axi_hbm_arprot(), + .m_axi_hbm_arqos(), + .m_axi_hbm_aruser(), + .m_axi_hbm_arvalid(), + .m_axi_hbm_arready(0), + .m_axi_hbm_rid(0), + .m_axi_hbm_rdata(0), + .m_axi_hbm_rresp(0), + .m_axi_hbm_rlast(0), + .m_axi_hbm_ruser(0), + .m_axi_hbm_rvalid(0), + .m_axi_hbm_rready(), + + .hbm_status(0), + /* * Statistics input */ diff --git a/fpga/mqnic/VCU118/fpga_25g/README.md b/fpga/mqnic/VCU118/fpga_25g/README.md index 2a6bf9ff4..e4f314d3d 100644 --- a/fpga/mqnic/VCU118/fpga_25g/README.md +++ b/fpga/mqnic/VCU118/fpga_25g/README.md @@ -4,8 +4,9 @@ This design targets the Xilinx VCU118 FPGA board. -FPGA: xcvu9p-flga2104-2L-e -PHY: 10G BASE-R PHY IP core and internal GTY transceiver +* FPGA: xcvu9p-flga2104-2L-e +* PHY: 10G BASE-R PHY IP core and internal GTY transceiver +* RAM: 4 GB DDR4 2666 (2x 256M x80) ## How to build diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga.xdc b/fpga/mqnic/VCU118/fpga_25g/fpga.xdc index 66f5514ef..1178e3b33 100644 --- a/fpga/mqnic/VCU118/fpga_25g/fpga.xdc +++ b/fpga/mqnic/VCU118/fpga_25g/fpga.xdc @@ -17,12 +17,12 @@ set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design] #create_clock -period 3.333 -name clk_300mhz [get_ports clk_300mhz_p] # 250 MHz -#set_property -dict {LOC E12 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_1_p] -#set_property -dict {LOC D12 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_1_n] +set_property -dict {LOC E12 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_1_p] +set_property -dict {LOC D12 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_1_n] #create_clock -period 4 -name clk_250mhz_1 [get_ports clk_250mhz_1_p] -#set_property -dict {LOC AW26 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_2_p] -#set_property -dict {LOC AW27 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_2_n] +set_property -dict {LOC AW26 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_2_p] +set_property -dict {LOC AW27 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_2_n] #create_clock -period 4 -name clk_250mhz_2 [get_ports clk_250mhz_2_p] # 125 MHz @@ -289,6 +289,302 @@ create_clock -period 10 -name pcie_mgt_refclk_2 [get_ports pcie_refclk_2_p] set_false_path -from [get_ports {pcie_reset_n}] set_input_delay 0 [get_ports {pcie_reset_n}] +# DDR4 C1 +# 5x MT40A256M16GE-075E +set_property -dict {LOC D14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}] +set_property -dict {LOC B15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}] +set_property -dict {LOC B16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}] +set_property -dict {LOC C14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}] +set_property -dict {LOC C15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}] +set_property -dict {LOC A13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}] +set_property -dict {LOC A14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}] +set_property -dict {LOC A15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}] +set_property -dict {LOC A16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}] +set_property -dict {LOC B12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}] +set_property -dict {LOC C12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}] +set_property -dict {LOC B13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}] +set_property -dict {LOC C13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}] +set_property -dict {LOC D15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}] +set_property -dict {LOC H14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}] +set_property -dict {LOC H15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}] +set_property -dict {LOC F15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}] +set_property -dict {LOC G15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}] +set_property -dict {LOC G13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}] +set_property -dict {LOC H13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}] +set_property -dict {LOC F14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t}] +set_property -dict {LOC E14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c}] +set_property -dict {LOC A10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke}] +set_property -dict {LOC F13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n}] +set_property -dict {LOC E13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}] +set_property -dict {LOC C8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt}] +set_property -dict {LOC G10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}] +set_property -dict {LOC N20 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}] +set_property -dict {LOC R17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_alert_n}] +set_property -dict {LOC A20 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_ten}] + +set_property -dict {LOC F11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] ;# U60.G2 DQL0 +set_property -dict {LOC E11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] ;# U60.F7 DQL1 +set_property -dict {LOC F10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] ;# U60.H3 DQL2 +set_property -dict {LOC F9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] ;# U60.H7 DQL3 +set_property -dict {LOC H12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] ;# U60.H2 DQL4 +set_property -dict {LOC G12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] ;# U60.H8 DQL5 +set_property -dict {LOC E9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] ;# U60.J3 DQL6 +set_property -dict {LOC D9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] ;# U60.J7 DQL7 +set_property -dict {LOC R19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] ;# U60.A3 DQU0 +set_property -dict {LOC P19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] ;# U60.B8 DQU1 +set_property -dict {LOC M18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] ;# U60.C3 DQU2 +set_property -dict {LOC M17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] ;# U60.C7 DQU3 +set_property -dict {LOC N19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] ;# U60.C2 DQU4 +set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] ;# U60.C8 DQU5 +set_property -dict {LOC N17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] ;# U60.D3 DQU6 +set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] ;# U60.D7 DQU7 +set_property -dict {LOC D11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] ;# U60.G3 DQSL_T +set_property -dict {LOC D10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] ;# U60.F3 DQSL_C +set_property -dict {LOC P17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] ;# U60.B7 DQSU_T +set_property -dict {LOC P16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] ;# U60.A7 DQSU_C +set_property -dict {LOC G11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[0]}] ;# U60.E7 DML_B/DBIL_B +set_property -dict {LOC R18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[1]}] ;# U60.E2 DMU_B/DBIU_B + +set_property -dict {LOC L16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] ;# U61.G2 DQL0 +set_property -dict {LOC K16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] ;# U61.F7 DQL1 +set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] ;# U61.H3 DQL2 +set_property -dict {LOC K18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] ;# U61.H7 DQL3 +set_property -dict {LOC J17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] ;# U61.H2 DQL4 +set_property -dict {LOC H17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] ;# U61.H8 DQL5 +set_property -dict {LOC H19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] ;# U61.J3 DQL6 +set_property -dict {LOC H18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] ;# U61.J7 DQL7 +set_property -dict {LOC F19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] ;# U61.A3 DQU0 +set_property -dict {LOC F18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] ;# U61.B8 DQU1 +set_property -dict {LOC E19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] ;# U61.C3 DQU2 +set_property -dict {LOC E18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] ;# U61.C7 DQU3 +set_property -dict {LOC G20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] ;# U61.C2 DQU4 +set_property -dict {LOC F20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] ;# U61.C8 DQU5 +set_property -dict {LOC E17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] ;# U61.D3 DQU6 +set_property -dict {LOC D16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] ;# U61.D7 DQU7 +set_property -dict {LOC K19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] ;# U61.G3 DQSL_T +set_property -dict {LOC J19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] ;# U61.F3 DQSL_C +set_property -dict {LOC F16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] ;# U61.B7 DQSU_T +set_property -dict {LOC E16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] ;# U61.A7 DQSU_C +set_property -dict {LOC K17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[2]}] ;# U61.E7 DML_B/DBIL_B +set_property -dict {LOC G18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[3]}] ;# U61.E2 DMU_B/DBIU_B + +set_property -dict {LOC D17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] ;# U62.G2 DQL0 +set_property -dict {LOC C17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] ;# U62.F7 DQL1 +set_property -dict {LOC C19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] ;# U62.H3 DQL2 +set_property -dict {LOC C18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] ;# U62.H7 DQL3 +set_property -dict {LOC D20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] ;# U62.H2 DQL4 +set_property -dict {LOC D19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] ;# U62.H8 DQL5 +set_property -dict {LOC C20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] ;# U62.J3 DQL6 +set_property -dict {LOC B20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] ;# U62.J7 DQL7 +set_property -dict {LOC N23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] ;# U62.A3 DQU0 +set_property -dict {LOC M23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] ;# U62.B8 DQU1 +set_property -dict {LOC R21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] ;# U62.C3 DQU2 +set_property -dict {LOC P21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] ;# U62.C7 DQU3 +set_property -dict {LOC R22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] ;# U62.C2 DQU4 +set_property -dict {LOC P22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] ;# U62.C8 DQU5 +set_property -dict {LOC T23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] ;# U62.D3 DQU6 +set_property -dict {LOC R23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] ;# U62.D7 DQU7 +set_property -dict {LOC A19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] ;# U62.G3 DQSL_T +set_property -dict {LOC A18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] ;# U62.F3 DQSL_C +set_property -dict {LOC N22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] ;# U62.B7 DQSU_T +set_property -dict {LOC M22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] ;# U62.A7 DQSU_C +set_property -dict {LOC B18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[4]}] ;# U62.E7 DML_B/DBIL_B +set_property -dict {LOC P20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[5]}] ;# U62.E2 DMU_B/DBIU_B + +set_property -dict {LOC K24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] ;# U63.G2 DQL0 +set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] ;# U63.F7 DQL1 +set_property -dict {LOC M21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] ;# U63.H3 DQL2 +set_property -dict {LOC L21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] ;# U63.H7 DQL3 +set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] ;# U63.H2 DQL4 +set_property -dict {LOC J21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] ;# U63.H8 DQL5 +set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] ;# U63.J3 DQL6 +set_property -dict {LOC J22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] ;# U63.J7 DQL7 +set_property -dict {LOC H23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] ;# U63.A3 DQU0 +set_property -dict {LOC H22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] ;# U63.B8 DQU1 +set_property -dict {LOC E23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] ;# U63.C3 DQU2 +set_property -dict {LOC E22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] ;# U63.C7 DQU3 +set_property -dict {LOC F21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] ;# U63.C2 DQU4 +set_property -dict {LOC E21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] ;# U63.C8 DQU5 +set_property -dict {LOC F24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] ;# U63.D3 DQU6 +set_property -dict {LOC F23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] ;# U63.D7 DQU7 +set_property -dict {LOC M20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] ;# U63.G3 DQSL_T +set_property -dict {LOC L20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] ;# U63.F3 DQSL_C +set_property -dict {LOC H24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] ;# U63.B7 DQSU_T +set_property -dict {LOC G23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] ;# U63.A7 DQSU_C +set_property -dict {LOC L23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[6]}] ;# U63.E7 DML_B/DBIL_B +set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[7]}] ;# U63.E2 DMU_B/DBIU_B + +set_property -dict {LOC A24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}] ;# U64.G2 DQL0 +set_property -dict {LOC A23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}] ;# U64.F7 DQL1 +set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}] ;# U64.H3 DQL2 +set_property -dict {LOC C23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}] ;# U64.H7 DQL3 +set_property -dict {LOC B23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}] ;# U64.H2 DQL4 +set_property -dict {LOC B22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}] ;# U64.H8 DQL5 +set_property -dict {LOC B21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}] ;# U64.J3 DQL6 +set_property -dict {LOC A21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}] ;# U64.J7 DQL7 +# set_property -dict {LOC D7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[72]}] ;# U64.A3 DQU0 +# set_property -dict {LOC C7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[73]}] ;# U64.B8 DQU1 +# set_property -dict {LOC B8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[74]}] ;# U64.C3 DQU2 +# set_property -dict {LOC B7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[75]}] ;# U64.C7 DQU3 +# set_property -dict {LOC C10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[76]}] ;# U64.C2 DQU4 +# set_property -dict {LOC B10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[77]}] ;# U64.C8 DQU5 +# set_property -dict {LOC B11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[78]}] ;# U64.D3 DQU6 +# set_property -dict {LOC A11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[79]}] ;# U64.D7 DQU7 +set_property -dict {LOC D22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}] ;# U64.G3 DQSL_T +set_property -dict {LOC C22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}] ;# U64.F3 DQSL_C +# set_property -dict {LOC A9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}] ;# U64.B7 DQSU_T +# set_property -dict {LOC A8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}] ;# U64.A7 DQSU_C +set_property -dict {LOC E24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[8]}] ;# U64.E7 DML_B/DBIL_B +# set_property -dict {LOC C9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[9]}] ;# U64.E2 DMU_B/DBIU_B + +# DDR4 C2 +# 5x MT40A256M16GE-075E +set_property -dict {LOC AM27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[0]}] +set_property -dict {LOC AL27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[1]}] +set_property -dict {LOC AP26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[2]}] +set_property -dict {LOC AP25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[3]}] +set_property -dict {LOC AN28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[4]}] +set_property -dict {LOC AM28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[5]}] +set_property -dict {LOC AP28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[6]}] +set_property -dict {LOC AP27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[7]}] +set_property -dict {LOC AN26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[8]}] +set_property -dict {LOC AM26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[9]}] +set_property -dict {LOC AR28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[10]}] +set_property -dict {LOC AR27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[11]}] +set_property -dict {LOC AV25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[12]}] +set_property -dict {LOC AT25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[13]}] +set_property -dict {LOC AV28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[14]}] +set_property -dict {LOC AU26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[15]}] +set_property -dict {LOC AV26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[16]}] +set_property -dict {LOC AR25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[0]}] +set_property -dict {LOC AU28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[1]}] +set_property -dict {LOC AU27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[0]}] +set_property -dict {LOC AT26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t}] +set_property -dict {LOC AT27 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c}] +set_property -dict {LOC AW28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke}] +set_property -dict {LOC AY29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n}] +set_property -dict {LOC AN25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_act_n}] +set_property -dict {LOC BB29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt}] +set_property -dict {LOC BF29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_par}] +set_property -dict {LOC BD35 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_reset_n}] +set_property -dict {LOC AR29 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_alert_n}] +set_property -dict {LOC AY35 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_ten}] + +set_property -dict {LOC BD30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[0]}] ;# U135.G2 DQL0 +set_property -dict {LOC BE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[1]}] ;# U135.F7 DQL1 +set_property -dict {LOC BD32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[2]}] ;# U135.H3 DQL2 +set_property -dict {LOC BE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[3]}] ;# U135.H7 DQL3 +set_property -dict {LOC BC33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[4]}] ;# U135.H2 DQL4 +set_property -dict {LOC BD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[5]}] ;# U135.H8 DQL5 +set_property -dict {LOC BC31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[6]}] ;# U135.J3 DQL6 +set_property -dict {LOC BD31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[7]}] ;# U135.J7 DQL7 +set_property -dict {LOC BA32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[8]}] ;# U135.A3 DQU0 +set_property -dict {LOC BB33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[9]}] ;# U135.B8 DQU1 +set_property -dict {LOC BA30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[10]}] ;# U135.C3 DQU2 +set_property -dict {LOC BA31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[11]}] ;# U135.C7 DQU3 +set_property -dict {LOC AW31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[12]}] ;# U135.C2 DQU4 +set_property -dict {LOC AW32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[13]}] ;# U135.C8 DQU5 +set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[14]}] ;# U135.D3 DQU6 +set_property -dict {LOC AY33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[15]}] ;# U135.D7 DQU7 +set_property -dict {LOC BF30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[0]}] ;# U135.G3 DQSL_T +set_property -dict {LOC BF31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[0]}] ;# U135.F3 DQSL_C +set_property -dict {LOC AY34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[1]}] ;# U135.B7 DQSU_T +set_property -dict {LOC BA34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[1]}] ;# U135.A7 DQSU_C +set_property -dict {LOC BE32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[0]}] ;# U135.E7 DML_B/DBIL_B +set_property -dict {LOC BB31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[1]}] ;# U135.E2 DMU_B/DBIU_B + +set_property -dict {LOC AV30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[16]}] ;# U136.G2 DQL0 +set_property -dict {LOC AW30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[17]}] ;# U136.F7 DQL1 +set_property -dict {LOC AU33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[18]}] ;# U136.H3 DQL2 +set_property -dict {LOC AU34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[19]}] ;# U136.H7 DQL3 +set_property -dict {LOC AT31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[20]}] ;# U136.H2 DQL4 +set_property -dict {LOC AU32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[21]}] ;# U136.H8 DQL5 +set_property -dict {LOC AU31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[22]}] ;# U136.J3 DQL6 +set_property -dict {LOC AV31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[23]}] ;# U136.J7 DQL7 +set_property -dict {LOC AR33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[24]}] ;# U136.A3 DQU0 +set_property -dict {LOC AT34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[25]}] ;# U136.B8 DQU1 +set_property -dict {LOC AT29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[26]}] ;# U136.C3 DQU2 +set_property -dict {LOC AT30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[27]}] ;# U136.C7 DQU3 +set_property -dict {LOC AP30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[28]}] ;# U136.C2 DQU4 +set_property -dict {LOC AR30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[29]}] ;# U136.C8 DQU5 +set_property -dict {LOC AN30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[30]}] ;# U136.D3 DQU6 +set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[31]}] ;# U136.D7 DQU7 +set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[2]}] ;# U136.G3 DQSL_T +set_property -dict {LOC AV29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[2]}] ;# U136.F3 DQSL_C +set_property -dict {LOC AP31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[3]}] ;# U136.B7 DQSU_T +set_property -dict {LOC AP32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[3]}] ;# U136.A7 DQSU_C +set_property -dict {LOC AV33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[2]}] ;# U136.E7 DML_B/DBIL_B +set_property -dict {LOC AR32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[3]}] ;# U136.E2 DMU_B/DBIU_B + +set_property -dict {LOC BE34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[32]}] ;# U137.G2 DQL0 +set_property -dict {LOC BF34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[33]}] ;# U137.F7 DQL1 +set_property -dict {LOC BC35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[34]}] ;# U137.H3 DQL2 +set_property -dict {LOC BC36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[35]}] ;# U137.H7 DQL3 +set_property -dict {LOC BD36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[36]}] ;# U137.H2 DQL4 +set_property -dict {LOC BE37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[37]}] ;# U137.H8 DQL5 +set_property -dict {LOC BF36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[38]}] ;# U137.J3 DQL6 +set_property -dict {LOC BF37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[39]}] ;# U137.J7 DQL7 +set_property -dict {LOC BD37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[40]}] ;# U137.A3 DQU0 +set_property -dict {LOC BE38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[41]}] ;# U137.B8 DQU1 +set_property -dict {LOC BC39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[42]}] ;# U137.C3 DQU2 +set_property -dict {LOC BD40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[43]}] ;# U137.C7 DQU3 +set_property -dict {LOC BB38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[44]}] ;# U137.C2 DQU4 +set_property -dict {LOC BB39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[45]}] ;# U137.C8 DQU5 +set_property -dict {LOC BC38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[46]}] ;# U137.D3 DQU6 +set_property -dict {LOC BD38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[47]}] ;# U137.D7 DQU7 +set_property -dict {LOC BE35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[4]}] ;# U137.G3 DQSL_T +set_property -dict {LOC BF35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[4]}] ;# U137.F3 DQSL_C +set_property -dict {LOC BE39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[5]}] ;# U137.B7 DQSU_T +set_property -dict {LOC BF39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[5]}] ;# U137.A7 DQSU_C +set_property -dict {LOC BC34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[4]}] ;# U137.E7 DML_B/DBIL_B +set_property -dict {LOC BE40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[5]}] ;# U137.E2 DMU_B/DBIU_B + +set_property -dict {LOC BB36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[48]}] ;# U138.G2 DQL0 +set_property -dict {LOC BB37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[49]}] ;# U138.F7 DQL1 +set_property -dict {LOC BA39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[50]}] ;# U138.H3 DQL2 +set_property -dict {LOC BA40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[51]}] ;# U138.H7 DQL3 +set_property -dict {LOC AW40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[52]}] ;# U138.H2 DQL4 +set_property -dict {LOC AY40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[53]}] ;# U138.H8 DQL5 +set_property -dict {LOC AY38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[54]}] ;# U138.J3 DQL6 +set_property -dict {LOC AY39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[55]}] ;# U138.J7 DQL7 +set_property -dict {LOC AW35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[56]}] ;# U138.A3 DQU0 +set_property -dict {LOC AW36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[57]}] ;# U138.B8 DQU1 +set_property -dict {LOC AU40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[58]}] ;# U138.C3 DQU2 +set_property -dict {LOC AV40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[59]}] ;# U138.C7 DQU3 +set_property -dict {LOC AU38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[60]}] ;# U138.C2 DQU4 +set_property -dict {LOC AU39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[61]}] ;# U138.C8 DQU5 +set_property -dict {LOC AV38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[62]}] ;# U138.D3 DQU6 +set_property -dict {LOC AV39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[63]}] ;# U138.D7 DQU7 +set_property -dict {LOC BA35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[6]}] ;# U138.G3 DQSL_T +set_property -dict {LOC BA36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[6]}] ;# U138.F3 DQSL_C +set_property -dict {LOC AW37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[7]}] ;# U138.B7 DQSU_T +set_property -dict {LOC AW38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[7]}] ;# U138.A7 DQSU_C +set_property -dict {LOC AY37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[6]}] ;# U138.E7 DML_B/DBIL_B +set_property -dict {LOC AV35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[7]}] ;# U138.E2 DMU_B/DBIU_B + +set_property -dict {LOC BF26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[64]}] ;# U139.G2 DQL0 +set_property -dict {LOC BF27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[65]}] ;# U139.F7 DQL1 +set_property -dict {LOC BD28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[66]}] ;# U139.H3 DQL2 +set_property -dict {LOC BE28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[67]}] ;# U139.H7 DQL3 +set_property -dict {LOC BD27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[68]}] ;# U139.H2 DQL4 +set_property -dict {LOC BE27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[69]}] ;# U139.H8 DQL5 +set_property -dict {LOC BD25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[70]}] ;# U139.J3 DQL6 +set_property -dict {LOC BD26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[71]}] ;# U139.J7 DQL7 +# set_property -dict {LOC BC25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[72]}] ;# U139.A3 DQU0 +# set_property -dict {LOC BC26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[73]}] ;# U139.B8 DQU1 +# set_property -dict {LOC BB28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[74]}] ;# U139.C3 DQU2 +# set_property -dict {LOC BC28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[75]}] ;# U139.C7 DQU3 +# set_property -dict {LOC AY27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[76]}] ;# U139.C2 DQU4 +# set_property -dict {LOC AY28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[77]}] ;# U139.C8 DQU5 +# set_property -dict {LOC BA27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[78]}] ;# U139.D3 DQU6 +# set_property -dict {LOC BB27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[79]}] ;# U139.D7 DQU7 +set_property -dict {LOC BE25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[8]}] ;# U139.G3 DQSL_T +set_property -dict {LOC BF25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[8]}] ;# U139.F3 DQSL_C +# set_property -dict {LOC BA26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[9]}] ;# U139.B7 DQSU_T +# set_property -dict {LOC BB26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[9]}] ;# U139.A7 DQSU_C +set_property -dict {LOC BE29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[8]}] ;# U139.E7 DML_B/DBIL_B +# set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[9]}] ;# U139.E2 DMU_B/DBIU_B + # QSPI flash set_property -dict {LOC AM19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[0]}] set_property -dict {LOC AM18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[1]}] diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile b/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile index fc8cef49d..9cceffb8c 100644 --- a/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile @@ -139,6 +139,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl b/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl index 284b765bc..9124de325 100644 --- a/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/VCU118/fpga_25g/fpga/config.tcl @@ -148,6 +148,12 @@ dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" dict set params RX_RAM_SIZE "131072" + +# RAM configuration +dict set params DDR_CH "2" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" # Application block configuration dict set params APP_ID "32'h00000000" @@ -200,6 +206,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile index fc8cef49d..9cceffb8c 100644 --- a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile @@ -139,6 +139,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl index 08a8177ea..782d4ea7c 100644 --- a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/config.tcl @@ -148,6 +148,12 @@ dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" dict set params RX_RAM_SIZE "32768" + +# RAM configuration +dict set params DDR_CH "2" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" # Application block configuration dict set params APP_ID "32'h00000000" @@ -200,6 +206,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/VCU118/fpga_25g/ip/ddr4_0.tcl b/fpga/mqnic/VCU118/fpga_25g/ip/ddr4_0.tcl new file mode 100644 index 000000000..cff759015 --- /dev/null +++ b/fpga/mqnic/VCU118/fpga_25g/ip/ddr4_0.tcl @@ -0,0 +1,19 @@ + +create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 + +set_property -dict [list \ + CONFIG.C0.DDR4_AxiSelection {true} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_AxiIDWidth {8} \ + CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ + CONFIG.C0.DDR4_TimePeriod {750} \ + CONFIG.C0.DDR4_InputClockPeriod {4000} \ + CONFIG.C0.DDR4_MemoryType {Components} \ + CONFIG.C0.DDR4_MemoryPart {MT40A256M16GE-075E} \ + CONFIG.C0.DDR4_DataWidth {72} \ + CONFIG.C0.DDR4_DataMask {NO_DM_NO_DBI} \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_CasLatency {18} \ + CONFIG.C0.DDR4_CasWriteLatency {14} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} +] [get_ips ddr4_0] diff --git a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v index b52d01045..30f60177f 100644 --- a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v @@ -112,6 +112,15 @@ module fpga # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // RAM configuration + parameter DDR_CH = 2, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 31, + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -182,6 +191,10 @@ module fpga # */ input wire clk_125mhz_p, input wire clk_125mhz_n, + input wire clk_250mhz_1_p, + input wire clk_250mhz_1_n, + input wire clk_250mhz_2_p, + input wire clk_250mhz_2_n, /* * GPIO @@ -274,6 +287,45 @@ module fpga # input wire qsfp2_intl, output wire qsfp2_lpmode, + /* + * DDR4 + */ + output wire [16:0] ddr4_c1_adr, + output wire [1:0] ddr4_c1_ba, + output wire [0:0] ddr4_c1_bg, + output wire ddr4_c1_ck_t, + output wire ddr4_c1_ck_c, + output wire ddr4_c1_cke, + output wire ddr4_c1_cs_n, + output wire ddr4_c1_act_n, + output wire ddr4_c1_odt, + output wire ddr4_c1_par, + input wire ddr4_c1_alert_n, + output wire ddr4_c1_reset_n, + output wire ddr4_c1_ten, + inout wire [71:0] ddr4_c1_dq, + inout wire [8:0] ddr4_c1_dqs_t, + inout wire [8:0] ddr4_c1_dqs_c, + inout wire [8:0] ddr4_c1_dm_dbi_n, + + output wire [16:0] ddr4_c2_adr, + output wire [1:0] ddr4_c2_ba, + output wire [0:0] ddr4_c2_bg, + output wire ddr4_c2_ck_t, + output wire ddr4_c2_ck_c, + output wire ddr4_c2_cke, + output wire ddr4_c2_cs_n, + output wire ddr4_c2_act_n, + output wire ddr4_c2_odt, + output wire ddr4_c2_par, + input wire ddr4_c2_alert_n, + output wire ddr4_c2_reset_n, + output wire ddr4_c2_ten, + inout wire [71:0] ddr4_c2_dq, + inout wire [8:0] ddr4_c2_dqs_t, + inout wire [8:0] ddr4_c2_dqs_c, + inout wire [8:0] ddr4_c2_dm_dbi_n, + /* * QSPI */ @@ -292,6 +344,9 @@ parameter IF_PTP_PERIOD_FNS = 16'h6666; // Interface configuration parameter TX_TAG_WIDTH = 16; +// RAM configuration +parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8); + // Ethernet interface configuration parameter XGMII_DATA_WIDTH = 64; parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8; @@ -1343,6 +1398,301 @@ assign ptp_clk = qsfp1_mgt_refclk_0_bufg; assign ptp_rst = qsfp1_rst; assign ptp_sample_clk = clk_125mhz_int; +// DDR4 +wire [DDR_CH-1:0] ddr_clk; +wire [DDR_CH-1:0] ddr_rst; + +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr; +wire [DDR_CH*8-1:0] m_axi_ddr_awlen; +wire [DDR_CH*3-1:0] m_axi_ddr_awsize; +wire [DDR_CH*2-1:0] m_axi_ddr_awburst; +wire [DDR_CH-1:0] m_axi_ddr_awlock; +wire [DDR_CH*4-1:0] m_axi_ddr_awcache; +wire [DDR_CH*3-1:0] m_axi_ddr_awprot; +wire [DDR_CH*4-1:0] m_axi_ddr_awqos; +wire [DDR_CH-1:0] m_axi_ddr_awvalid; +wire [DDR_CH-1:0] m_axi_ddr_awready; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata; +wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb; +wire [DDR_CH-1:0] m_axi_ddr_wlast; +wire [DDR_CH-1:0] m_axi_ddr_wvalid; +wire [DDR_CH-1:0] m_axi_ddr_wready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid; +wire [DDR_CH*2-1:0] m_axi_ddr_bresp; +wire [DDR_CH-1:0] m_axi_ddr_bvalid; +wire [DDR_CH-1:0] m_axi_ddr_bready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr; +wire [DDR_CH*8-1:0] m_axi_ddr_arlen; +wire [DDR_CH*3-1:0] m_axi_ddr_arsize; +wire [DDR_CH*2-1:0] m_axi_ddr_arburst; +wire [DDR_CH-1:0] m_axi_ddr_arlock; +wire [DDR_CH*4-1:0] m_axi_ddr_arcache; +wire [DDR_CH*3-1:0] m_axi_ddr_arprot; +wire [DDR_CH*4-1:0] m_axi_ddr_arqos; +wire [DDR_CH-1:0] m_axi_ddr_arvalid; +wire [DDR_CH-1:0] m_axi_ddr_arready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata; +wire [DDR_CH*2-1:0] m_axi_ddr_rresp; +wire [DDR_CH-1:0] m_axi_ddr_rlast; +wire [DDR_CH-1:0] m_axi_ddr_rvalid; +wire [DDR_CH-1:0] m_axi_ddr_rready; + +wire [DDR_CH-1:0] ddr_status; + +generate + +if (DDR_ENABLE && DDR_CH > 0) begin + +ddr4_0 ddr4_c1_inst ( + .c0_sys_clk_p(clk_250mhz_1_p), + .c0_sys_clk_n(clk_250mhz_1_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[0 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c1_adr), + .c0_ddr4_ba(ddr4_c1_ba), + .c0_ddr4_cke(ddr4_c1_cke), + .c0_ddr4_cs_n(ddr4_c1_cs_n), + .c0_ddr4_dq(ddr4_c1_dq), + .c0_ddr4_dqs_t(ddr4_c1_dqs_t), + .c0_ddr4_dqs_c(ddr4_c1_dqs_c), + .c0_ddr4_dm_dbi_n(ddr4_c1_dm_dbi_n), + .c0_ddr4_odt(ddr4_c1_odt), + .c0_ddr4_bg(ddr4_c1_bg), + .c0_ddr4_reset_n(ddr4_c1_reset_n), + .c0_ddr4_act_n(ddr4_c1_act_n), + .c0_ddr4_ck_t(ddr4_c1_ck_t), + .c0_ddr4_ck_c(ddr4_c1_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[0 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[0 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c1_adr = {17{1'bz}}; +assign ddr4_c1_ba = {2{1'bz}}; +assign ddr4_c1_bg = {1{1'bz}}; +assign ddr4_c1_cke = 1'bz; +assign ddr4_c1_cs_n = 1'bz; +assign ddr4_c1_act_n = 1'bz; +assign ddr4_c1_odt = 1'bz; +assign ddr4_c1_reset_n = 1'b0; +assign ddr4_c1_dq = {72{1'bz}}; +assign ddr4_c1_dqs_t = {9{1'bz}}; +assign ddr4_c1_dqs_c = {9{1'bz}}; +assign ddr4_c1_dm_dbi_n = {9{1'bz}}; + +OBUFTDS ddr4_c1_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c1_ck_t), + .OB(ddr4_c1_ck_c) +); + +assign ddr_clk = 0; +assign ddr_rst = 0; + +assign m_axi_ddr_awready = 0; +assign m_axi_ddr_wready = 0; +assign m_axi_ddr_bid = 0; +assign m_axi_ddr_bresp = 0; +assign m_axi_ddr_bvalid = 0; +assign m_axi_ddr_arready = 0; +assign m_axi_ddr_rid = 0; +assign m_axi_ddr_rdata = 0; +assign m_axi_ddr_rresp = 0; +assign m_axi_ddr_rlast = 0; +assign m_axi_ddr_rvalid = 0; + +assign ddr_status = 0; + +end + +assign ddr4_c1_par = 1'b0; +assign ddr4_c1_ten = 1'b0; + +if (DDR_ENABLE && DDR_CH > 1) begin + +ddr4_0 ddr4_c2_inst ( + .c0_sys_clk_p(clk_250mhz_2_p), + .c0_sys_clk_n(clk_250mhz_2_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[1 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c2_adr), + .c0_ddr4_ba(ddr4_c2_ba), + .c0_ddr4_cke(ddr4_c2_cke), + .c0_ddr4_cs_n(ddr4_c2_cs_n), + .c0_ddr4_dq(ddr4_c2_dq), + .c0_ddr4_dqs_t(ddr4_c2_dqs_t), + .c0_ddr4_dqs_c(ddr4_c2_dqs_c), + .c0_ddr4_dm_dbi_n(ddr4_c2_dm_dbi_n), + .c0_ddr4_odt(ddr4_c2_odt), + .c0_ddr4_bg(ddr4_c2_bg), + .c0_ddr4_reset_n(ddr4_c2_reset_n), + .c0_ddr4_act_n(ddr4_c2_act_n), + .c0_ddr4_ck_t(ddr4_c2_ck_t), + .c0_ddr4_ck_c(ddr4_c2_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[1 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[1 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[1 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[1*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[1*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[1*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[1 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[1*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[1*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[1*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[1 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[1 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[1*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[1 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[1 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[1 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[1 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[1*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[1 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[1*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[1*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[1*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[1 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[1*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[1*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[1*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[1 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[1 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[1 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[1 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[1 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[1*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c2_adr = {17{1'bz}}; +assign ddr4_c2_ba = {2{1'bz}}; +assign ddr4_c2_bg = {1{1'bz}}; +assign ddr4_c2_cke = 1'bz; +assign ddr4_c2_cs_n = 1'bz; +assign ddr4_c2_act_n = 1'bz; +assign ddr4_c2_odt = 1'bz; +assign ddr4_c2_reset_n = 1'b0; +assign ddr4_c2_dq = {72{1'bz}}; +assign ddr4_c2_dqs_t = {9{1'bz}}; +assign ddr4_c2_dqs_c = {9{1'bz}}; +assign ddr4_c2_dm_dbi_n = {9{1'bz}}; + +OBUFTDS ddr4_c2_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c2_ck_t), + .OB(ddr4_c2_ck_c) +); + +end + +assign ddr4_c2_par = 1'b0; +assign ddr4_c2_ten = 1'b0; + +endgenerate + fpga_core #( // FW and board IDs .FPGA_ID(FPGA_ID), @@ -1419,6 +1769,16 @@ fpga_core #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1731,6 +2091,52 @@ core_inst ( .qsfp2_intl(qsfp2_intl_int), .qsfp2_lpmode(qsfp2_lpmode), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + /* * QSPI flash */ diff --git a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v index 53e497d4d..7c2ebe33f 100644 --- a/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v @@ -122,6 +122,16 @@ module fpga_core # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // RAM configuration + parameter DDR_CH = 2, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 31, + parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -436,6 +446,52 @@ module fpga_core # input wire qsfp2_intl, output wire qsfp2_lpmode, + /* + * DDR + */ + input wire [DDR_CH-1:0] ddr_clk, + input wire [DDR_CH-1:0] ddr_rst, + + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, + output wire [DDR_CH-1:0] m_axi_ddr_awlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, + output wire [DDR_CH-1:0] m_axi_ddr_awvalid, + input wire [DDR_CH-1:0] m_axi_ddr_awready, + output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, + output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, + output wire [DDR_CH-1:0] m_axi_ddr_wlast, + output wire [DDR_CH-1:0] m_axi_ddr_wvalid, + input wire [DDR_CH-1:0] m_axi_ddr_wready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, + input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, + input wire [DDR_CH-1:0] m_axi_ddr_bvalid, + output wire [DDR_CH-1:0] m_axi_ddr_bready, + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, + output wire [DDR_CH-1:0] m_axi_ddr_arlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, + output wire [DDR_CH-1:0] m_axi_ddr_arvalid, + input wire [DDR_CH-1:0] m_axi_ddr_arready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, + input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, + input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, + input wire [DDR_CH-1:0] m_axi_ddr_rlast, + input wire [DDR_CH-1:0] m_axi_ddr_rvalid, + output wire [DDR_CH-1:0] m_axi_ddr_rready, + + input wire [DDR_CH-1:0] ddr_status, + /* * QSPI flash */ @@ -1138,6 +1194,25 @@ mqnic_core_pcie_us #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .DDR_GROUP_SIZE(1), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_AWUSER_ENABLE(0), + .AXI_DDR_WUSER_ENABLE(0), + .AXI_DDR_BUSER_ENABLE(0), + .AXI_DDR_ARUSER_ENABLE(0), + .AXI_DDR_RUSER_ENABLE(0), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + .AXI_DDR_FIXED_BURST(0), + .AXI_DDR_WRAP_BURST(1), + .HBM_ENABLE(0), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1415,6 +1490,108 @@ core_inst ( .eth_rx_status(eth_rx_status), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awuser(), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wuser(), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_buser(0), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_aruser(), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_ruser(0), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + + /* + * HBM + */ + .hbm_clk(0), + .hbm_rst(0), + + .m_axi_hbm_awid(), + .m_axi_hbm_awaddr(), + .m_axi_hbm_awlen(), + .m_axi_hbm_awsize(), + .m_axi_hbm_awburst(), + .m_axi_hbm_awlock(), + .m_axi_hbm_awcache(), + .m_axi_hbm_awprot(), + .m_axi_hbm_awqos(), + .m_axi_hbm_awuser(), + .m_axi_hbm_awvalid(), + .m_axi_hbm_awready(0), + .m_axi_hbm_wdata(), + .m_axi_hbm_wstrb(), + .m_axi_hbm_wlast(), + .m_axi_hbm_wuser(), + .m_axi_hbm_wvalid(), + .m_axi_hbm_wready(0), + .m_axi_hbm_bid(0), + .m_axi_hbm_bresp(0), + .m_axi_hbm_buser(0), + .m_axi_hbm_bvalid(0), + .m_axi_hbm_bready(), + .m_axi_hbm_arid(), + .m_axi_hbm_araddr(), + .m_axi_hbm_arlen(), + .m_axi_hbm_arsize(), + .m_axi_hbm_arburst(), + .m_axi_hbm_arlock(), + .m_axi_hbm_arcache(), + .m_axi_hbm_arprot(), + .m_axi_hbm_arqos(), + .m_axi_hbm_aruser(), + .m_axi_hbm_arvalid(), + .m_axi_hbm_arready(0), + .m_axi_hbm_rid(0), + .m_axi_hbm_rdata(0), + .m_axi_hbm_rresp(0), + .m_axi_hbm_rlast(0), + .m_axi_hbm_ruser(0), + .m_axi_hbm_rvalid(0), + .m_axi_hbm_rready(), + + .hbm_status(0), + /* * Statistics input */ diff --git a/fpga/mqnic/VCU1525/fpga_100g/README.md b/fpga/mqnic/VCU1525/fpga_100g/README.md index 4169b1b2c..786efae5e 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/README.md +++ b/fpga/mqnic/VCU1525/fpga_100g/README.md @@ -7,6 +7,7 @@ This design targets the Xilinx VCU1525 FPGA board. * FPGA: xcvu9p-fsgd2104-2L-e * MAC: Xilinx 100G CMAC * PHY: 100G CAUI-4 CMAC and internal GTY transceivers +* RAM: 64 GB DDR4 2400 (4x 2G x72 DIMM) ## How to build diff --git a/fpga/mqnic/VCU1525/fpga_100g/fpga.xdc b/fpga/mqnic/VCU1525/fpga_100g/fpga.xdc index a487ed9b4..61a523239 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/fpga.xdc +++ b/fpga/mqnic/VCU1525/fpga_100g/fpga.xdc @@ -15,23 +15,23 @@ set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] # System clocks # 300 MHz (DDR 0) -#set_property -dict {LOC AY37 IOSTANDARD LVDS} [get_ports clk_300mhz_0_p] -#set_property -dict {LOC AY38 IOSTANDARD LVDS} [get_ports clk_300mhz_0_n] +set_property -dict {LOC AY37 IOSTANDARD LVDS} [get_ports clk_300mhz_0_p] +set_property -dict {LOC AY38 IOSTANDARD LVDS} [get_ports clk_300mhz_0_n] #create_clock -period 3.333 -name clk_300mhz_0 [get_ports clk_300mhz_0_p] # 300 MHz (DDR 1) -#set_property -dict {LOC AW20 IOSTANDARD LVDS} [get_ports clk_300mhz_1_p] -#set_property -dict {LOC AW19 IOSTANDARD LVDS} [get_ports clk_300mhz_1_n] +set_property -dict {LOC AW20 IOSTANDARD LVDS} [get_ports clk_300mhz_1_p] +set_property -dict {LOC AW19 IOSTANDARD LVDS} [get_ports clk_300mhz_1_n] #create_clock -period 3.333 -name clk_300mhz_1 [get_ports clk_300mhz_1_p] # 300 MHz (DDR 2) -#set_property -dict {LOC F32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_p] -#set_property -dict {LOC E32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_n] +set_property -dict {LOC F32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_p] +set_property -dict {LOC E32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_n] #create_clock -period 3.333 -name clk_300mhz_2 [get_ports clk_300mhz_2_p] # 300 MHz (DDR 3) -#set_property -dict {LOC J16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_p] -#set_property -dict {LOC H16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_n] +set_property -dict {LOC J16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_p] +set_property -dict {LOC H16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_n] #create_clock -period 3.333 -name clk_300mhz_3 [get_ports clk_300mhz_3_p] # SI570 user clock @@ -242,3 +242,591 @@ create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_p] set_false_path -from [get_ports {pcie_reset_n}] set_input_delay 0 [get_ports {pcie_reset_n}] + +# DDR4 C0 +set_property -dict {LOC AT36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}] +set_property -dict {LOC AV36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}] +set_property -dict {LOC AV37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}] +set_property -dict {LOC AW35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}] +set_property -dict {LOC AW36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}] +set_property -dict {LOC AY36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}] +set_property -dict {LOC AY35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}] +set_property -dict {LOC BA40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}] +set_property -dict {LOC BA37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}] +set_property -dict {LOC BB37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}] +set_property -dict {LOC AR35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}] +set_property -dict {LOC BA39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}] +set_property -dict {LOC BB40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}] +set_property -dict {LOC AN36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}] +set_property -dict {LOC AP35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}] +set_property -dict {LOC AP36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}] +set_property -dict {LOC AR36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}] +set_property -dict {LOC AT35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}] +set_property -dict {LOC AT34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}] +set_property -dict {LOC BC37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}] +set_property -dict {LOC BC39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}] +set_property -dict {LOC AV38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t[0]}] +set_property -dict {LOC AW38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c[0]}] +#set_property -dict {LOC AU34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t[1]}] +#set_property -dict {LOC AU35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c[1]}] +set_property -dict {LOC BC38 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[0]}] +#set_property -dict {LOC BC40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[1]}] +set_property -dict {LOC AR33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[0]}] +#set_property -dict {LOC AP33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[1]}] +#set_property -dict {LOC AN33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[2]}] +#set_property -dict {LOC AM34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[3]}] +set_property -dict {LOC BB39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}] +set_property -dict {LOC AP34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[0]}] +#set_property -dict {LOC AN34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[1]}] +set_property -dict {LOC AU36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}] +set_property -dict {LOC AU31 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_reset_n}] + +set_property -dict {LOC AW28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}] +set_property -dict {LOC AW29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}] +set_property -dict {LOC BA28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}] +set_property -dict {LOC BA27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}] +set_property -dict {LOC BB29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}] +set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}] +set_property -dict {LOC BC27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}] +set_property -dict {LOC BB27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}] +set_property -dict {LOC BE28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}] +set_property -dict {LOC BF28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}] +set_property -dict {LOC BE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}] +set_property -dict {LOC BD30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}] +set_property -dict {LOC BF27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}] +set_property -dict {LOC BE27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}] +set_property -dict {LOC BF30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}] +set_property -dict {LOC BF29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}] +set_property -dict {LOC BB31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}] +set_property -dict {LOC BB32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}] +set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}] +set_property -dict {LOC AY33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}] +set_property -dict {LOC BC32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}] +set_property -dict {LOC BC33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}] +set_property -dict {LOC BB34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}] +set_property -dict {LOC BC34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}] +set_property -dict {LOC AV31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}] +set_property -dict {LOC AV32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}] +set_property -dict {LOC AV34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}] +set_property -dict {LOC AW34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}] +set_property -dict {LOC AW31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}] +set_property -dict {LOC AY31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}] +set_property -dict {LOC BA35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}] +set_property -dict {LOC BA34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}] +set_property -dict {LOC AL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}] +set_property -dict {LOC AM30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}] +set_property -dict {LOC AU32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}] +set_property -dict {LOC AT32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}] +set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}] +set_property -dict {LOC AN32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}] +set_property -dict {LOC AR32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}] +set_property -dict {LOC AR31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}] +set_property -dict {LOC AP29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}] +set_property -dict {LOC AP28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}] +set_property -dict {LOC AN27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}] +set_property -dict {LOC AM27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}] +set_property -dict {LOC AN29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}] +set_property -dict {LOC AM29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}] +set_property -dict {LOC AR27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}] +set_property -dict {LOC AR28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}] +set_property -dict {LOC AT28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}] +set_property -dict {LOC AV27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}] +set_property -dict {LOC AU27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}] +set_property -dict {LOC AT27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}] +set_property -dict {LOC AV29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}] +set_property -dict {LOC AY30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}] +set_property -dict {LOC AW30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}] +set_property -dict {LOC AV28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}] +set_property -dict {LOC BD34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}] +set_property -dict {LOC BD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}] +set_property -dict {LOC BE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}] +set_property -dict {LOC BD35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}] +set_property -dict {LOC BF32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}] +set_property -dict {LOC BF33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}] +set_property -dict {LOC BF34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}] +set_property -dict {LOC BF35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}] +set_property -dict {LOC BD40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}] +set_property -dict {LOC BD39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}] +set_property -dict {LOC BF43 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}] +set_property -dict {LOC BF42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}] +set_property -dict {LOC BF37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}] +set_property -dict {LOC BE37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}] +set_property -dict {LOC BE40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}] +set_property -dict {LOC BF41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}] +set_property -dict {LOC BA30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}] +set_property -dict {LOC BB30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}] +set_property -dict {LOC BB26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}] +set_property -dict {LOC BC26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}] +set_property -dict {LOC BD28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}] +set_property -dict {LOC BD29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}] +set_property -dict {LOC BD26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}] +set_property -dict {LOC BE26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}] +set_property -dict {LOC BB35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}] +set_property -dict {LOC BB36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}] +set_property -dict {LOC BC31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}] +set_property -dict {LOC BD31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}] +set_property -dict {LOC AV33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}] +set_property -dict {LOC AW33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}] +set_property -dict {LOC BA32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}] +set_property -dict {LOC BA33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}] +set_property -dict {LOC AM31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}] +set_property -dict {LOC AM32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}] +set_property -dict {LOC AP30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[9]}] +set_property -dict {LOC AP31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[9]}] +set_property -dict {LOC AL28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[10]}] +set_property -dict {LOC AL29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[10]}] +set_property -dict {LOC AR30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[11]}] +set_property -dict {LOC AT30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[11]}] +set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[12]}] +set_property -dict {LOC AU30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[12]}] +set_property -dict {LOC AY27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[13]}] +set_property -dict {LOC AY28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[13]}] +set_property -dict {LOC BE35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[14]}] +set_property -dict {LOC BE36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[14]}] +set_property -dict {LOC BE31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[15]}] +set_property -dict {LOC BE32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[15]}] +set_property -dict {LOC BE38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[16]}] +set_property -dict {LOC BF38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[16]}] +set_property -dict {LOC BF39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[17]}] +set_property -dict {LOC BF40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[17]}] + +# DDR4 C1 +set_property -dict {LOC AN24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}] +set_property -dict {LOC AT24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}] +set_property -dict {LOC AW24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}] +set_property -dict {LOC AN26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}] +set_property -dict {LOC AY22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}] +set_property -dict {LOC AY23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}] +set_property -dict {LOC AV24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}] +set_property -dict {LOC BA22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}] +set_property -dict {LOC AY25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}] +set_property -dict {LOC BA23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}] +set_property -dict {LOC AM26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}] +set_property -dict {LOC BA25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}] +set_property -dict {LOC BB22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}] +set_property -dict {LOC AL24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}] +set_property -dict {LOC AL25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}] +set_property -dict {LOC AM25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}] +set_property -dict {LOC AN23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}] +set_property -dict {LOC AU24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}] +set_property -dict {LOC AP26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}] +set_property -dict {LOC BC22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}] +set_property -dict {LOC AW26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}] +set_property -dict {LOC AT25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t[0]}] +set_property -dict {LOC AU25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c[0]}] +#set_property -dict {LOC AU26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t[1]}] +#set_property -dict {LOC AV26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c[1]}] +set_property -dict {LOC BB25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[0]}] +#set_property -dict {LOC BB24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[1]}] +set_property -dict {LOC AV23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[0]}] +#set_property -dict {LOC AP25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[1]}] +#set_property -dict {LOC AR23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[2]}] +#set_property -dict {LOC AP23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[3]}] +set_property -dict {LOC AW25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}] +set_property -dict {LOC AW23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[0]}] +#set_property -dict {LOC AP24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[1]}] +set_property -dict {LOC AT23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}] +set_property -dict {LOC AR17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}] + +set_property -dict {LOC BD9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] +set_property -dict {LOC BD7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] +set_property -dict {LOC BC7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] +set_property -dict {LOC BD8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] +set_property -dict {LOC BD10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] +set_property -dict {LOC BE10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] +set_property -dict {LOC BE7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] +set_property -dict {LOC BF7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] +set_property -dict {LOC AU13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] +set_property -dict {LOC AV13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] +set_property -dict {LOC AW13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] +set_property -dict {LOC AW14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] +set_property -dict {LOC AU14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] +set_property -dict {LOC AY11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] +set_property -dict {LOC AV14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] +set_property -dict {LOC BA11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] +set_property -dict {LOC BA12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] +set_property -dict {LOC BB12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] +set_property -dict {LOC BA13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] +set_property -dict {LOC BA14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] +set_property -dict {LOC BC9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] +set_property -dict {LOC BB9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] +set_property -dict {LOC BA7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] +set_property -dict {LOC BA8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] +set_property -dict {LOC AN13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] +set_property -dict {LOC AR13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] +set_property -dict {LOC AM13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] +set_property -dict {LOC AP13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] +set_property -dict {LOC AM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] +set_property -dict {LOC AR15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] +set_property -dict {LOC AL14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] +set_property -dict {LOC AT15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] +set_property -dict {LOC BE13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] +set_property -dict {LOC BD14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] +set_property -dict {LOC BF12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] +set_property -dict {LOC BD13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] +set_property -dict {LOC BD15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] +set_property -dict {LOC BD16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] +set_property -dict {LOC BF14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] +set_property -dict {LOC BF13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] +set_property -dict {LOC AY17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] +set_property -dict {LOC BA17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] +set_property -dict {LOC AY18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] +set_property -dict {LOC BA18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] +set_property -dict {LOC BA15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] +set_property -dict {LOC BB15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] +set_property -dict {LOC BC11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] +set_property -dict {LOC BD11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] +set_property -dict {LOC AV16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] +set_property -dict {LOC AV17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] +set_property -dict {LOC AU16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] +set_property -dict {LOC AU17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] +set_property -dict {LOC BB17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] +set_property -dict {LOC BB16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] +set_property -dict {LOC AT18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] +set_property -dict {LOC AT17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] +set_property -dict {LOC AM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] +set_property -dict {LOC AL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] +set_property -dict {LOC AN17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] +set_property -dict {LOC AN16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] +set_property -dict {LOC AR18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] +set_property -dict {LOC AP18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] +set_property -dict {LOC AL17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] +set_property -dict {LOC AL16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] +set_property -dict {LOC BF25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}] +set_property -dict {LOC BF24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}] +set_property -dict {LOC BD25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}] +set_property -dict {LOC BE25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}] +set_property -dict {LOC BD23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}] +set_property -dict {LOC BC23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}] +set_property -dict {LOC BF23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}] +set_property -dict {LOC BE23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}] +set_property -dict {LOC BF10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] +set_property -dict {LOC BF9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] +set_property -dict {LOC BE8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] +set_property -dict {LOC BF8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] +set_property -dict {LOC AW15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] +set_property -dict {LOC AY15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] +set_property -dict {LOC AY13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] +set_property -dict {LOC AY12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] +set_property -dict {LOC BB11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] +set_property -dict {LOC BB10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] +set_property -dict {LOC BA10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] +set_property -dict {LOC BA9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] +set_property -dict {LOC AT14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] +set_property -dict {LOC AT13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] +set_property -dict {LOC AN14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] +set_property -dict {LOC AP14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] +set_property -dict {LOC BE12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}] +set_property -dict {LOC BE11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}] +set_property -dict {LOC BE15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}] +set_property -dict {LOC BF15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}] +set_property -dict {LOC BC13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[10]}] +set_property -dict {LOC BC12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[10]}] +set_property -dict {LOC BB14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[11]}] +set_property -dict {LOC BC14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[11]}] +set_property -dict {LOC AV18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[12]}] +set_property -dict {LOC AW18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[12]}] +set_property -dict {LOC AW16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[13]}] +set_property -dict {LOC AY16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[13]}] +set_property -dict {LOC AP16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[14]}] +set_property -dict {LOC AR16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[14]}] +set_property -dict {LOC AM17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[15]}] +set_property -dict {LOC AM16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[15]}] +set_property -dict {LOC BC24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[16]}] +set_property -dict {LOC BD24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[16]}] +set_property -dict {LOC BE22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[17]}] +set_property -dict {LOC BF22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[17]}] + +# DDR4 C2 +set_property -dict {LOC L29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[0]}] +set_property -dict {LOC A33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[1]}] +set_property -dict {LOC C33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[2]}] +set_property -dict {LOC J29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[3]}] +set_property -dict {LOC H31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[4]}] +set_property -dict {LOC G31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[5]}] +set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[6]}] +set_property -dict {LOC B32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[7]}] +set_property -dict {LOC A32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[8]}] +set_property -dict {LOC D31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[9]}] +set_property -dict {LOC A34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[10]}] +set_property -dict {LOC E31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[11]}] +set_property -dict {LOC M30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[12]}] +set_property -dict {LOC F33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[13]}] +set_property -dict {LOC A35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[14]}] +set_property -dict {LOC G32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[15]}] +set_property -dict {LOC K30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[16]}] +set_property -dict {LOC D33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[0]}] +set_property -dict {LOC B36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[1]}] +set_property -dict {LOC C31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[0]}] +set_property -dict {LOC J30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[1]}] +set_property -dict {LOC C34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t[0]}] +set_property -dict {LOC B34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c[0]}] +#set_property -dict {LOC D34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t[1]}] +#set_property -dict {LOC D35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c[1]}] +set_property -dict {LOC G30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[0]}] +#set_property -dict {LOC E30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[1]}] +set_property -dict {LOC B35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[0]}] +#set_property -dict {LOC J31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[1]}] +#set_property -dict {LOC L30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[2]}] +#set_property -dict {LOC K31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[3]}] +set_property -dict {LOC B31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_act_n}] +set_property -dict {LOC E33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[0]}] +#set_property -dict {LOC F34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[1]}] +set_property -dict {LOC M29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_par}] +set_property -dict {LOC D36 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_reset_n}] + +set_property -dict {LOC R25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[0]}] +set_property -dict {LOC P25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[1]}] +set_property -dict {LOC M25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[2]}] +set_property -dict {LOC L25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[3]}] +set_property -dict {LOC P26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[4]}] +set_property -dict {LOC R26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[5]}] +set_property -dict {LOC N27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[6]}] +set_property -dict {LOC N28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[7]}] +set_property -dict {LOC J28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[8]}] +set_property -dict {LOC H29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[9]}] +set_property -dict {LOC H28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[10]}] +set_property -dict {LOC G29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[11]}] +set_property -dict {LOC K25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[12]}] +set_property -dict {LOC L27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[13]}] +set_property -dict {LOC K26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[14]}] +set_property -dict {LOC K27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[15]}] +set_property -dict {LOC F27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[16]}] +set_property -dict {LOC E27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[17]}] +set_property -dict {LOC E28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[18]}] +set_property -dict {LOC D28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[19]}] +set_property -dict {LOC G27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[20]}] +set_property -dict {LOC G26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[21]}] +set_property -dict {LOC F28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[22]}] +set_property -dict {LOC F29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[23]}] +set_property -dict {LOC D26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[24]}] +set_property -dict {LOC C26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[25]}] +set_property -dict {LOC B27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[26]}] +set_property -dict {LOC B26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[27]}] +set_property -dict {LOC A29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[28]}] +set_property -dict {LOC A30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[29]}] +set_property -dict {LOC C27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[30]}] +set_property -dict {LOC C28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[31]}] +set_property -dict {LOC F35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[32]}] +set_property -dict {LOC E38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[33]}] +set_property -dict {LOC D38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[34]}] +set_property -dict {LOC E35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[35]}] +set_property -dict {LOC E36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[36]}] +set_property -dict {LOC E37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[37]}] +set_property -dict {LOC F38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[38]}] +set_property -dict {LOC G38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[39]}] +set_property -dict {LOC P30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[40]}] +set_property -dict {LOC R30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[41]}] +set_property -dict {LOC P29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[42]}] +set_property -dict {LOC N29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[43]}] +set_property -dict {LOC L32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[44]}] +set_property -dict {LOC M32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[45]}] +set_property -dict {LOC P31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[46]}] +set_property -dict {LOC N32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[47]}] +set_property -dict {LOC J35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[48]}] +set_property -dict {LOC K35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[49]}] +set_property -dict {LOC L33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[50]}] +set_property -dict {LOC K33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[51]}] +set_property -dict {LOC J34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[52]}] +set_property -dict {LOC J33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[53]}] +set_property -dict {LOC N34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[54]}] +set_property -dict {LOC P34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[55]}] +set_property -dict {LOC H36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[56]}] +set_property -dict {LOC G36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[57]}] +set_property -dict {LOC H37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[58]}] +set_property -dict {LOC J36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[59]}] +set_property -dict {LOC K37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[60]}] +set_property -dict {LOC K38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[61]}] +set_property -dict {LOC G35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[62]}] +set_property -dict {LOC G34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[63]}] +set_property -dict {LOC C36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[64]}] +set_property -dict {LOC B37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[65]}] +set_property -dict {LOC A37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[66]}] +set_property -dict {LOC A38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[67]}] +set_property -dict {LOC C39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[68]}] +set_property -dict {LOC D39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[69]}] +set_property -dict {LOC A40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[70]}] +set_property -dict {LOC B40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[71]}] +set_property -dict {LOC N26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[0]}] +set_property -dict {LOC M26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[0]}] +set_property -dict {LOC R28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[1]}] +set_property -dict {LOC P28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[1]}] +set_property -dict {LOC J25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[2]}] +set_property -dict {LOC J26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[2]}] +set_property -dict {LOC M27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[3]}] +set_property -dict {LOC L28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[3]}] +set_property -dict {LOC D29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[4]}] +set_property -dict {LOC D30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[4]}] +set_property -dict {LOC H26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[5]}] +set_property -dict {LOC H27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[5]}] +set_property -dict {LOC A27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[6]}] +set_property -dict {LOC A28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[6]}] +set_property -dict {LOC C29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[7]}] +set_property -dict {LOC B29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[7]}] +set_property -dict {LOC E39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[8]}] +set_property -dict {LOC E40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[8]}] +set_property -dict {LOC G37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[9]}] +set_property -dict {LOC F37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[9]}] +set_property -dict {LOC N31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[10]}] +set_property -dict {LOC M31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[10]}] +set_property -dict {LOC T30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[11]}] +set_property -dict {LOC R31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[11]}] +set_property -dict {LOC L35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[12]}] +set_property -dict {LOC L36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[12]}] +set_property -dict {LOC M34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[13]}] +set_property -dict {LOC L34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[13]}] +set_property -dict {LOC J38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[14]}] +set_property -dict {LOC H38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[14]}] +set_property -dict {LOC H33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[15]}] +set_property -dict {LOC H34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[15]}] +set_property -dict {LOC B39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[16]}] +set_property -dict {LOC A39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[16]}] +set_property -dict {LOC C37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[17]}] +set_property -dict {LOC C38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[17]}] + +# DDR4 C3 +set_property -dict {LOC K15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[0]}] +set_property -dict {LOC B15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[1]}] +set_property -dict {LOC F14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[2]}] +set_property -dict {LOC A15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[3]}] +set_property -dict {LOC C14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[4]}] +set_property -dict {LOC A14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[5]}] +set_property -dict {LOC B14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[6]}] +set_property -dict {LOC E13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[7]}] +set_property -dict {LOC F13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[8]}] +set_property -dict {LOC A13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[9]}] +set_property -dict {LOC D14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[10]}] +set_property -dict {LOC C13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[11]}] +set_property -dict {LOC B13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[12]}] +set_property -dict {LOC K16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[13]}] +set_property -dict {LOC D15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[14]}] +set_property -dict {LOC E15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[15]}] +set_property -dict {LOC F15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[16]}] +set_property -dict {LOC J15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[0]}] +set_property -dict {LOC H14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[1]}] +set_property -dict {LOC D13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[0]}] +set_property -dict {LOC J13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[1]}] +set_property -dict {LOC L14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t[0]}] +set_property -dict {LOC L13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c[0]}] +#set_property -dict {LOC G14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t[1]}] +#set_property -dict {LOC G13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c[1]}] +set_property -dict {LOC K13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[0]}] +#set_property -dict {LOC L15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[1]}] +set_property -dict {LOC B16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[0]}] +#set_property -dict {LOC D16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[1]}] +#set_property -dict {LOC M14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[2]}] +#set_property -dict {LOC M13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[3]}] +set_property -dict {LOC H13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_act_n}] +set_property -dict {LOC C16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[0]}] +#set_property -dict {LOC E16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[1]}] +set_property -dict {LOC J14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_par}] +set_property -dict {LOC D21 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c3_reset_n}] + +set_property -dict {LOC P24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[0]}] +set_property -dict {LOC N24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[1]}] +set_property -dict {LOC T24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[2]}] +set_property -dict {LOC R23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[3]}] +set_property -dict {LOC N23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[4]}] +set_property -dict {LOC P21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[5]}] +set_property -dict {LOC P23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[6]}] +set_property -dict {LOC R21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[7]}] +set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[8]}] +set_property -dict {LOC J23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[9]}] +set_property -dict {LOC H24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[10]}] +set_property -dict {LOC G24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[11]}] +set_property -dict {LOC L24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[12]}] +set_property -dict {LOC L23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[13]}] +set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[14]}] +set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[15]}] +set_property -dict {LOC G20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[16]}] +set_property -dict {LOC H17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[17]}] +set_property -dict {LOC F19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[18]}] +set_property -dict {LOC G17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[19]}] +set_property -dict {LOC J20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[20]}] +set_property -dict {LOC L19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[21]}] +set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[22]}] +set_property -dict {LOC J19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[23]}] +set_property -dict {LOC M19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[24]}] +set_property -dict {LOC M20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[25]}] +set_property -dict {LOC R18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[26]}] +set_property -dict {LOC R17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[27]}] +set_property -dict {LOC R20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[28]}] +set_property -dict {LOC T20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[29]}] +set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[30]}] +set_property -dict {LOC N19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[31]}] +set_property -dict {LOC A23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[32]}] +set_property -dict {LOC A22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[33]}] +set_property -dict {LOC B24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[34]}] +set_property -dict {LOC B25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[35]}] +set_property -dict {LOC B22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[36]}] +set_property -dict {LOC C22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[37]}] +set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[38]}] +set_property -dict {LOC C23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[39]}] +set_property -dict {LOC C19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[40]}] +set_property -dict {LOC C18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[41]}] +set_property -dict {LOC C21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[42]}] +set_property -dict {LOC B21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[43]}] +set_property -dict {LOC A18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[44]}] +set_property -dict {LOC A17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[45]}] +set_property -dict {LOC A20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[46]}] +set_property -dict {LOC B20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[47]}] +set_property -dict {LOC E17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[48]}] +set_property -dict {LOC F20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[49]}] +set_property -dict {LOC E18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[50]}] +set_property -dict {LOC E20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[51]}] +set_property -dict {LOC D19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[52]}] +set_property -dict {LOC D20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[53]}] +set_property -dict {LOC H18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[54]}] +set_property -dict {LOC J18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[55]}] +set_property -dict {LOC F22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[56]}] +set_property -dict {LOC E22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[57]}] +set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[58]}] +set_property -dict {LOC G21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[59]}] +set_property -dict {LOC F24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[60]}] +set_property -dict {LOC E25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[61]}] +set_property -dict {LOC F25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[62]}] +set_property -dict {LOC G25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[63]}] +set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[64]}] +set_property -dict {LOC N16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[65]}] +set_property -dict {LOC N13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[66]}] +set_property -dict {LOC N14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[67]}] +set_property -dict {LOC T15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[68]}] +set_property -dict {LOC R15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[69]}] +set_property -dict {LOC P13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[70]}] +set_property -dict {LOC P14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[71]}] +set_property -dict {LOC T22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[0]}] +set_property -dict {LOC R22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[0]}] +set_property -dict {LOC N22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[1]}] +set_property -dict {LOC N21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[1]}] +set_property -dict {LOC J21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[2]}] +set_property -dict {LOC H21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[2]}] +set_property -dict {LOC M22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[3]}] +set_property -dict {LOC L22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[3]}] +set_property -dict {LOC L20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[4]}] +set_property -dict {LOC K20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[4]}] +set_property -dict {LOC K18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[5]}] +set_property -dict {LOC K17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[5]}] +set_property -dict {LOC P19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[6]}] +set_property -dict {LOC P18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[6]}] +set_property -dict {LOC N17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[7]}] +set_property -dict {LOC M17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[7]}] +set_property -dict {LOC A25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[8]}] +set_property -dict {LOC A24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[8]}] +set_property -dict {LOC D24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[9]}] +set_property -dict {LOC D23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[9]}] +set_property -dict {LOC C17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[10]}] +set_property -dict {LOC B17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[10]}] +set_property -dict {LOC B19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[11]}] +set_property -dict {LOC A19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[11]}] +set_property -dict {LOC F18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[12]}] +set_property -dict {LOC F17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[12]}] +set_property -dict {LOC H19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[13]}] +set_property -dict {LOC G19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[13]}] +set_property -dict {LOC F23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[14]}] +set_property -dict {LOC E23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[14]}] +set_property -dict {LOC H23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[15]}] +set_property -dict {LOC H22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[15]}] +set_property -dict {LOC R16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[16]}] +set_property -dict {LOC P15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[16]}] +set_property -dict {LOC T13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[17]}] +set_property -dict {LOC R13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[17]}] diff --git a/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile b/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile index 1d46ca2a2..cc9c6f502 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile @@ -120,6 +120,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/cmac_usplus_0.tcl IP_TCL_FILES += ip/cmac_usplus_1.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl b/fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl index 686875baf..d25cc59be 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/VCU1525/fpga_100g/fpga/config.tcl @@ -136,6 +136,12 @@ dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "131072" dict set params RX_RAM_SIZE "131072" + +# RAM configuration +dict set params DDR_CH "4" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" # Application block configuration dict set params APP_ID "32'h00000000" @@ -187,6 +193,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/VCU1525/fpga_100g/ip/ddr4_0.tcl b/fpga/mqnic/VCU1525/fpga_100g/ip/ddr4_0.tcl new file mode 100644 index 000000000..27252f502 --- /dev/null +++ b/fpga/mqnic/VCU1525/fpga_100g/ip/ddr4_0.tcl @@ -0,0 +1,17 @@ + +create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 + +set_property -dict [list \ + CONFIG.C0.DDR4_AxiSelection {true} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_AxiIDWidth {8} \ + CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ + CONFIG.C0.DDR4_TimePeriod {833} \ + CONFIG.C0.DDR4_InputClockPeriod {3332} \ + CONFIG.C0.DDR4_MemoryType {RDIMMs} \ + CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PZ-2G3} \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_CasLatency {17} \ + CONFIG.C0.DDR4_CasWriteLatency {12} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} +] [get_ips ddr4_0] diff --git a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v index 1a89821dc..30d5e35c6 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v @@ -109,6 +109,15 @@ module fpga # parameter TX_RAM_SIZE = 131072, parameter RX_RAM_SIZE = 131072, + // RAM configuration + parameter DDR_CH = 4, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 34, + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -173,6 +182,18 @@ module fpga # parameter STAT_ID_WIDTH = 12 ) ( + /* + * Clock and reset + */ + input wire clk_300mhz_0_p, + input wire clk_300mhz_0_n, + input wire clk_300mhz_1_p, + input wire clk_300mhz_1_n, + input wire clk_300mhz_2_p, + input wire clk_300mhz_2_n, + input wire clk_300mhz_3_p, + input wire clk_300mhz_3_n, + /* * GPIO */ @@ -253,7 +274,70 @@ module fpga # input wire qsfp1_intl, output wire qsfp1_lpmode, output wire qsfp1_refclk_reset, - output wire [1:0] qsfp1_fs + output wire [1:0] qsfp1_fs, + + /* + * DDR4 + */ + output wire [16:0] ddr4_c0_adr, + output wire [1:0] ddr4_c0_ba, + output wire [1:0] ddr4_c0_bg, + output wire [0:0] ddr4_c0_ck_t, + output wire [0:0] ddr4_c0_ck_c, + output wire [0:0] ddr4_c0_cke, + output wire [0:0] ddr4_c0_cs_n, + output wire ddr4_c0_act_n, + output wire [0:0] ddr4_c0_odt, + output wire ddr4_c0_par, + output wire ddr4_c0_reset_n, + inout wire [71:0] ddr4_c0_dq, + inout wire [17:0] ddr4_c0_dqs_t, + inout wire [17:0] ddr4_c0_dqs_c, + + output wire [16:0] ddr4_c1_adr, + output wire [1:0] ddr4_c1_ba, + output wire [1:0] ddr4_c1_bg, + output wire [0:0] ddr4_c1_ck_t, + output wire [0:0] ddr4_c1_ck_c, + output wire [0:0] ddr4_c1_cke, + output wire [0:0] ddr4_c1_cs_n, + output wire ddr4_c1_act_n, + output wire [0:0] ddr4_c1_odt, + output wire ddr4_c1_par, + output wire ddr4_c1_reset_n, + inout wire [71:0] ddr4_c1_dq, + inout wire [17:0] ddr4_c1_dqs_t, + inout wire [17:0] ddr4_c1_dqs_c, + + output wire [16:0] ddr4_c2_adr, + output wire [1:0] ddr4_c2_ba, + output wire [1:0] ddr4_c2_bg, + output wire [0:0] ddr4_c2_ck_t, + output wire [0:0] ddr4_c2_ck_c, + output wire [0:0] ddr4_c2_cke, + output wire [0:0] ddr4_c2_cs_n, + output wire ddr4_c2_act_n, + output wire [0:0] ddr4_c2_odt, + output wire ddr4_c2_par, + output wire ddr4_c2_reset_n, + inout wire [71:0] ddr4_c2_dq, + inout wire [17:0] ddr4_c2_dqs_t, + inout wire [17:0] ddr4_c2_dqs_c, + + output wire [16:0] ddr4_c3_adr, + output wire [1:0] ddr4_c3_ba, + output wire [1:0] ddr4_c3_bg, + output wire [0:0] ddr4_c3_ck_t, + output wire [0:0] ddr4_c3_ck_c, + output wire [0:0] ddr4_c3_cke, + output wire [0:0] ddr4_c3_cs_n, + output wire ddr4_c3_act_n, + output wire [0:0] ddr4_c3_odt, + output wire ddr4_c3_par, + output wire ddr4_c3_reset_n, + inout wire [71:0] ddr4_c3_dq, + inout wire [17:0] ddr4_c3_dqs_t, + inout wire [17:0] ddr4_c3_dqs_c ); // PTP configuration @@ -266,6 +350,9 @@ parameter PTP_SEPARATE_RX_CLOCK = 1; // Interface configuration parameter TX_TAG_WIDTH = 16; +// RAM configuration +parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8); + // Ethernet interface configuration parameter AXIS_ETH_DATA_WIDTH = 512; parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; @@ -1734,6 +1821,519 @@ assign led[0] = led_int[0]; // red assign led[1] = qsfp1_rx_status; // yellow assign led[2] = qsfp0_rx_status; // green +// DDR4 +wire [DDR_CH-1:0] ddr_clk; +wire [DDR_CH-1:0] ddr_rst; + +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr; +wire [DDR_CH*8-1:0] m_axi_ddr_awlen; +wire [DDR_CH*3-1:0] m_axi_ddr_awsize; +wire [DDR_CH*2-1:0] m_axi_ddr_awburst; +wire [DDR_CH-1:0] m_axi_ddr_awlock; +wire [DDR_CH*4-1:0] m_axi_ddr_awcache; +wire [DDR_CH*3-1:0] m_axi_ddr_awprot; +wire [DDR_CH*4-1:0] m_axi_ddr_awqos; +wire [DDR_CH-1:0] m_axi_ddr_awvalid; +wire [DDR_CH-1:0] m_axi_ddr_awready; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata; +wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb; +wire [DDR_CH-1:0] m_axi_ddr_wlast; +wire [DDR_CH-1:0] m_axi_ddr_wvalid; +wire [DDR_CH-1:0] m_axi_ddr_wready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid; +wire [DDR_CH*2-1:0] m_axi_ddr_bresp; +wire [DDR_CH-1:0] m_axi_ddr_bvalid; +wire [DDR_CH-1:0] m_axi_ddr_bready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr; +wire [DDR_CH*8-1:0] m_axi_ddr_arlen; +wire [DDR_CH*3-1:0] m_axi_ddr_arsize; +wire [DDR_CH*2-1:0] m_axi_ddr_arburst; +wire [DDR_CH-1:0] m_axi_ddr_arlock; +wire [DDR_CH*4-1:0] m_axi_ddr_arcache; +wire [DDR_CH*3-1:0] m_axi_ddr_arprot; +wire [DDR_CH*4-1:0] m_axi_ddr_arqos; +wire [DDR_CH-1:0] m_axi_ddr_arvalid; +wire [DDR_CH-1:0] m_axi_ddr_arready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata; +wire [DDR_CH*2-1:0] m_axi_ddr_rresp; +wire [DDR_CH-1:0] m_axi_ddr_rlast; +wire [DDR_CH-1:0] m_axi_ddr_rvalid; +wire [DDR_CH-1:0] m_axi_ddr_rready; + +wire [DDR_CH-1:0] ddr_status; + +generate + +if (DDR_ENABLE && DDR_CH > 0) begin + +ddr4_0 ddr4_c0_inst ( + .c0_sys_clk_p(clk_300mhz_0_p), + .c0_sys_clk_n(clk_300mhz_0_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[0 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c0_adr), + .c0_ddr4_ba(ddr4_c0_ba), + .c0_ddr4_cke(ddr4_c0_cke), + .c0_ddr4_cs_n(ddr4_c0_cs_n), + .c0_ddr4_dq(ddr4_c0_dq), + .c0_ddr4_dqs_t(ddr4_c0_dqs_t), + .c0_ddr4_dqs_c(ddr4_c0_dqs_c), + .c0_ddr4_odt(ddr4_c0_odt), + .c0_ddr4_parity(ddr4_c0_par), + .c0_ddr4_bg(ddr4_c0_bg), + .c0_ddr4_reset_n(ddr4_c0_reset_n), + .c0_ddr4_act_n(ddr4_c0_act_n), + .c0_ddr4_ck_t(ddr4_c0_ck_t), + .c0_ddr4_ck_c(ddr4_c0_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[0 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[0 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c0_adr = {17{1'bz}}; +assign ddr4_c0_ba = {2{1'bz}}; +assign ddr4_c0_bg = {2{1'bz}}; +assign ddr4_c0_cke = 1'bz; +assign ddr4_c0_cs_n = 1'bz; +assign ddr4_c0_act_n = 1'bz; +assign ddr4_c0_odt = 1'bz; +assign ddr4_c0_par = 1'bz; +assign ddr4_c0_reset_n = 1'b0; +assign ddr4_c0_dq = {72{1'bz}}; +assign ddr4_c0_dqs_t = {18{1'bz}}; +assign ddr4_c0_dqs_c = {18{1'bz}}; + +OBUFTDS ddr4_c0_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c0_ck_t), + .OB(ddr4_c0_ck_c) +); + +assign ddr_clk = 0; +assign ddr_rst = 0; + +assign m_axi_ddr_awready = 0; +assign m_axi_ddr_wready = 0; +assign m_axi_ddr_bid = 0; +assign m_axi_ddr_bresp = 0; +assign m_axi_ddr_bvalid = 0; +assign m_axi_ddr_arready = 0; +assign m_axi_ddr_rid = 0; +assign m_axi_ddr_rdata = 0; +assign m_axi_ddr_rresp = 0; +assign m_axi_ddr_rlast = 0; +assign m_axi_ddr_rvalid = 0; + +assign ddr_status = 0; + +end + +if (DDR_ENABLE && DDR_CH > 1) begin + +ddr4_0 ddr4_c1_inst ( + .c0_sys_clk_p(clk_300mhz_1_p), + .c0_sys_clk_n(clk_300mhz_1_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[1 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c1_adr), + .c0_ddr4_ba(ddr4_c1_ba), + .c0_ddr4_cke(ddr4_c1_cke), + .c0_ddr4_cs_n(ddr4_c1_cs_n), + .c0_ddr4_dq(ddr4_c1_dq), + .c0_ddr4_dqs_t(ddr4_c1_dqs_t), + .c0_ddr4_dqs_c(ddr4_c1_dqs_c), + .c0_ddr4_odt(ddr4_c1_odt), + .c0_ddr4_parity(ddr4_c1_par), + .c0_ddr4_bg(ddr4_c1_bg), + .c0_ddr4_reset_n(ddr4_c1_reset_n), + .c0_ddr4_act_n(ddr4_c1_act_n), + .c0_ddr4_ck_t(ddr4_c1_ck_t), + .c0_ddr4_ck_c(ddr4_c1_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[1 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[1 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[1 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[1*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[1*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[1*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[1 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[1*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[1*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[1*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[1 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[1 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[1*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[1 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[1 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[1 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[1 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[1*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[1 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[1*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[1*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[1*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[1 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[1*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[1*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[1*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[1 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[1 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[1 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[1 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[1 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[1*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c1_adr = {17{1'bz}}; +assign ddr4_c1_ba = {2{1'bz}}; +assign ddr4_c1_bg = {2{1'bz}}; +assign ddr4_c1_cke = 1'bz; +assign ddr4_c1_cs_n = 1'bz; +assign ddr4_c1_act_n = 1'bz; +assign ddr4_c1_odt = 1'bz; +assign ddr4_c1_par = 1'bz; +assign ddr4_c1_reset_n = 1'b0; +assign ddr4_c1_dq = {72{1'bz}}; +assign ddr4_c1_dqs_t = {18{1'bz}}; +assign ddr4_c1_dqs_c = {18{1'bz}}; + +OBUFTDS ddr4_c1_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c1_ck_t), + .OB(ddr4_c1_ck_c) +); + +end + +if (DDR_ENABLE && DDR_CH > 2) begin + +ddr4_0 ddr4_c2_inst ( + .c0_sys_clk_p(clk_300mhz_2_p), + .c0_sys_clk_n(clk_300mhz_2_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[2 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c2_adr), + .c0_ddr4_ba(ddr4_c2_ba), + .c0_ddr4_cke(ddr4_c2_cke), + .c0_ddr4_cs_n(ddr4_c2_cs_n), + .c0_ddr4_dq(ddr4_c2_dq), + .c0_ddr4_dqs_t(ddr4_c2_dqs_t), + .c0_ddr4_dqs_c(ddr4_c2_dqs_c), + .c0_ddr4_odt(ddr4_c2_odt), + .c0_ddr4_parity(ddr4_c2_par), + .c0_ddr4_bg(ddr4_c2_bg), + .c0_ddr4_reset_n(ddr4_c2_reset_n), + .c0_ddr4_act_n(ddr4_c2_act_n), + .c0_ddr4_ck_t(ddr4_c2_ck_t), + .c0_ddr4_ck_c(ddr4_c2_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[2 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[2 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[2 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[2*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[2*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[2*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[2 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[2*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[2*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[2*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[2 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[2 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[2*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[2 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[2 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[2 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[2 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[2*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[2 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[2*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[2*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[2*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[2 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[2*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[2*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[2*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[2 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[2 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[2 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[2 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[2 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[2*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c2_adr = {17{1'bz}}; +assign ddr4_c2_ba = {2{1'bz}}; +assign ddr4_c2_bg = {2{1'bz}}; +assign ddr4_c2_cke = 1'bz; +assign ddr4_c2_cs_n = 1'bz; +assign ddr4_c2_act_n = 1'bz; +assign ddr4_c2_odt = 1'bz; +assign ddr4_c2_par = 1'bz; +assign ddr4_c2_reset_n = 1'b0; +assign ddr4_c2_dq = {72{1'bz}}; +assign ddr4_c2_dqs_t = {18{1'bz}}; +assign ddr4_c2_dqs_c = {18{1'bz}}; + +OBUFTDS ddr4_c2_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c2_ck_t), + .OB(ddr4_c2_ck_c) +); + +end + +if (DDR_ENABLE && DDR_CH > 3) begin + +ddr4_0 ddr4_c3_inst ( + .c0_sys_clk_p(clk_300mhz_3_p), + .c0_sys_clk_n(clk_300mhz_3_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[3 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c3_adr), + .c0_ddr4_ba(ddr4_c3_ba), + .c0_ddr4_cke(ddr4_c3_cke), + .c0_ddr4_cs_n(ddr4_c3_cs_n), + .c0_ddr4_dq(ddr4_c3_dq), + .c0_ddr4_dqs_t(ddr4_c3_dqs_t), + .c0_ddr4_dqs_c(ddr4_c3_dqs_c), + .c0_ddr4_odt(ddr4_c3_odt), + .c0_ddr4_parity(ddr4_c3_par), + .c0_ddr4_bg(ddr4_c3_bg), + .c0_ddr4_reset_n(ddr4_c3_reset_n), + .c0_ddr4_act_n(ddr4_c3_act_n), + .c0_ddr4_ck_t(ddr4_c3_ck_t), + .c0_ddr4_ck_c(ddr4_c3_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[3 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[3 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[3 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[3*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[3*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[3*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[3 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[3*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[3*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[3*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[3 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[3 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[3*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[3 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[3 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[3 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[3 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[3*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[3 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[3*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[3*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[3*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[3 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[3*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[3*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[3*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[3 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[3 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[3 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[3 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[3 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[3*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c3_adr = {17{1'bz}}; +assign ddr4_c3_ba = {2{1'bz}}; +assign ddr4_c3_bg = {2{1'bz}}; +assign ddr4_c3_cke = 1'bz; +assign ddr4_c3_cs_n = 1'bz; +assign ddr4_c3_act_n = 1'bz; +assign ddr4_c3_odt = 1'bz; +assign ddr4_c3_par = 1'bz; +assign ddr4_c3_reset_n = 1'b0; +assign ddr4_c3_dq = {72{1'bz}}; +assign ddr4_c3_dqs_t = {18{1'bz}}; +assign ddr4_c3_dqs_c = {18{1'bz}}; + +OBUFTDS ddr4_c3_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c3_ck_t), + .OB(ddr4_c3_ck_c) +); + +end + +endgenerate + fpga_core #( // FW and board IDs .FPGA_ID(FPGA_ID), @@ -1808,6 +2408,16 @@ fpga_core #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -2045,6 +2655,52 @@ core_inst ( .qsfp1_intl(qsfp1_intl_int), .qsfp1_lpmode(qsfp1_lpmode), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + /* * QSPI flash */ diff --git a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v index 2c7407447..31d680816 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v @@ -115,6 +115,16 @@ module fpga_core # parameter TX_RAM_SIZE = 131072, parameter RX_RAM_SIZE = 131072, + // RAM configuration + parameter DDR_CH = 4, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 34, + parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -364,6 +374,52 @@ module fpga_core # input wire qsfp1_intl, output wire qsfp1_lpmode, + /* + * DDR + */ + input wire [DDR_CH-1:0] ddr_clk, + input wire [DDR_CH-1:0] ddr_rst, + + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, + output wire [DDR_CH-1:0] m_axi_ddr_awlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, + output wire [DDR_CH-1:0] m_axi_ddr_awvalid, + input wire [DDR_CH-1:0] m_axi_ddr_awready, + output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, + output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, + output wire [DDR_CH-1:0] m_axi_ddr_wlast, + output wire [DDR_CH-1:0] m_axi_ddr_wvalid, + input wire [DDR_CH-1:0] m_axi_ddr_wready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, + input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, + input wire [DDR_CH-1:0] m_axi_ddr_bvalid, + output wire [DDR_CH-1:0] m_axi_ddr_bready, + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, + output wire [DDR_CH-1:0] m_axi_ddr_arlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, + output wire [DDR_CH-1:0] m_axi_ddr_arvalid, + input wire [DDR_CH-1:0] m_axi_ddr_arready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, + input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, + input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, + input wire [DDR_CH-1:0] m_axi_ddr_rlast, + input wire [DDR_CH-1:0] m_axi_ddr_rvalid, + output wire [DDR_CH-1:0] m_axi_ddr_rready, + + input wire [DDR_CH-1:0] ddr_status, + /* * QSPI flash */ @@ -826,6 +882,25 @@ mqnic_core_pcie_us #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .DDR_GROUP_SIZE(1), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_AWUSER_ENABLE(0), + .AXI_DDR_WUSER_ENABLE(0), + .AXI_DDR_BUSER_ENABLE(0), + .AXI_DDR_ARUSER_ENABLE(0), + .AXI_DDR_RUSER_ENABLE(0), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + .AXI_DDR_FIXED_BURST(0), + .AXI_DDR_WRAP_BURST(1), + .HBM_ENABLE(0), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1103,6 +1178,108 @@ core_inst ( .eth_rx_status(eth_rx_status), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awuser(), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wuser(), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_buser(0), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_aruser(), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_ruser(0), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + + /* + * HBM + */ + .hbm_clk(0), + .hbm_rst(0), + + .m_axi_hbm_awid(), + .m_axi_hbm_awaddr(), + .m_axi_hbm_awlen(), + .m_axi_hbm_awsize(), + .m_axi_hbm_awburst(), + .m_axi_hbm_awlock(), + .m_axi_hbm_awcache(), + .m_axi_hbm_awprot(), + .m_axi_hbm_awqos(), + .m_axi_hbm_awuser(), + .m_axi_hbm_awvalid(), + .m_axi_hbm_awready(0), + .m_axi_hbm_wdata(), + .m_axi_hbm_wstrb(), + .m_axi_hbm_wlast(), + .m_axi_hbm_wuser(), + .m_axi_hbm_wvalid(), + .m_axi_hbm_wready(0), + .m_axi_hbm_bid(0), + .m_axi_hbm_bresp(0), + .m_axi_hbm_buser(0), + .m_axi_hbm_bvalid(0), + .m_axi_hbm_bready(), + .m_axi_hbm_arid(), + .m_axi_hbm_araddr(), + .m_axi_hbm_arlen(), + .m_axi_hbm_arsize(), + .m_axi_hbm_arburst(), + .m_axi_hbm_arlock(), + .m_axi_hbm_arcache(), + .m_axi_hbm_arprot(), + .m_axi_hbm_arqos(), + .m_axi_hbm_aruser(), + .m_axi_hbm_arvalid(), + .m_axi_hbm_arready(0), + .m_axi_hbm_rid(0), + .m_axi_hbm_rdata(0), + .m_axi_hbm_rresp(0), + .m_axi_hbm_rlast(0), + .m_axi_hbm_ruser(0), + .m_axi_hbm_rvalid(0), + .m_axi_hbm_rready(), + + .hbm_status(0), + /* * Statistics input */ diff --git a/fpga/mqnic/VCU1525/fpga_25g/README.md b/fpga/mqnic/VCU1525/fpga_25g/README.md index a667d5342..953c323ea 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/README.md +++ b/fpga/mqnic/VCU1525/fpga_25g/README.md @@ -4,8 +4,9 @@ This design targets the Xilinx VCU1525 FPGA board. -FPGA: xcvu9p-fsgd2104-2L-e -PHY: 10G BASE-R PHY IP core and internal GTY transceiver +* FPGA: xcvu9p-fsgd2104-2L-e +* PHY: 10G BASE-R PHY IP core and internal GTY transceiver +* RAM: 64 GB DDR4 2400 (4x 2G x72 DIMM) ## How to build diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga.xdc b/fpga/mqnic/VCU1525/fpga_25g/fpga.xdc index 90da67206..9dec0b9c5 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/fpga.xdc +++ b/fpga/mqnic/VCU1525/fpga_25g/fpga.xdc @@ -15,23 +15,23 @@ set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] # System clocks # 300 MHz (DDR 0) -#set_property -dict {LOC AY37 IOSTANDARD LVDS} [get_ports clk_300mhz_0_p] -#set_property -dict {LOC AY38 IOSTANDARD LVDS} [get_ports clk_300mhz_0_n] +set_property -dict {LOC AY37 IOSTANDARD LVDS} [get_ports clk_300mhz_0_p] +set_property -dict {LOC AY38 IOSTANDARD LVDS} [get_ports clk_300mhz_0_n] #create_clock -period 3.333 -name clk_300mhz_0 [get_ports clk_300mhz_0_p] # 300 MHz (DDR 1) -#set_property -dict {LOC AW20 IOSTANDARD LVDS} [get_ports clk_300mhz_1_p] -#set_property -dict {LOC AW19 IOSTANDARD LVDS} [get_ports clk_300mhz_1_n] +set_property -dict {LOC AW20 IOSTANDARD LVDS} [get_ports clk_300mhz_1_p] +set_property -dict {LOC AW19 IOSTANDARD LVDS} [get_ports clk_300mhz_1_n] #create_clock -period 3.333 -name clk_300mhz_1 [get_ports clk_300mhz_1_p] # 300 MHz (DDR 2) -#set_property -dict {LOC F32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_p] -#set_property -dict {LOC E32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_n] +set_property -dict {LOC F32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_p] +set_property -dict {LOC E32 IOSTANDARD LVDS} [get_ports clk_300mhz_2_n] #create_clock -period 3.333 -name clk_300mhz_2 [get_ports clk_300mhz_2_p] # 300 MHz (DDR 3) -#set_property -dict {LOC J16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_p] -#set_property -dict {LOC H16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_n] +set_property -dict {LOC J16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_p] +set_property -dict {LOC H16 IOSTANDARD LVDS} [get_ports clk_300mhz_3_n] #create_clock -period 3.333 -name clk_300mhz_3 [get_ports clk_300mhz_3_p] # SI570 user clock @@ -242,3 +242,591 @@ create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_p] set_false_path -from [get_ports {pcie_reset_n}] set_input_delay 0 [get_ports {pcie_reset_n}] + +# DDR4 C0 +set_property -dict {LOC AT36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}] +set_property -dict {LOC AV36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}] +set_property -dict {LOC AV37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}] +set_property -dict {LOC AW35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}] +set_property -dict {LOC AW36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}] +set_property -dict {LOC AY36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}] +set_property -dict {LOC AY35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}] +set_property -dict {LOC BA40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}] +set_property -dict {LOC BA37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}] +set_property -dict {LOC BB37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}] +set_property -dict {LOC AR35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}] +set_property -dict {LOC BA39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}] +set_property -dict {LOC BB40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}] +set_property -dict {LOC AN36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}] +set_property -dict {LOC AP35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}] +set_property -dict {LOC AP36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}] +set_property -dict {LOC AR36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}] +set_property -dict {LOC AT35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}] +set_property -dict {LOC AT34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}] +set_property -dict {LOC BC37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}] +set_property -dict {LOC BC39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}] +set_property -dict {LOC AV38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t[0]}] +set_property -dict {LOC AW38 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c[0]}] +#set_property -dict {LOC AU34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t[1]}] +#set_property -dict {LOC AU35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c[1]}] +set_property -dict {LOC BC38 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[0]}] +#set_property -dict {LOC BC40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[1]}] +set_property -dict {LOC AR33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[0]}] +#set_property -dict {LOC AP33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[1]}] +#set_property -dict {LOC AN33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[2]}] +#set_property -dict {LOC AM34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[3]}] +set_property -dict {LOC BB39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}] +set_property -dict {LOC AP34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[0]}] +#set_property -dict {LOC AN34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[1]}] +set_property -dict {LOC AU36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}] +set_property -dict {LOC AU31 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_reset_n}] + +set_property -dict {LOC AW28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}] +set_property -dict {LOC AW29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}] +set_property -dict {LOC BA28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}] +set_property -dict {LOC BA27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}] +set_property -dict {LOC BB29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}] +set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}] +set_property -dict {LOC BC27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}] +set_property -dict {LOC BB27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}] +set_property -dict {LOC BE28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}] +set_property -dict {LOC BF28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}] +set_property -dict {LOC BE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}] +set_property -dict {LOC BD30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}] +set_property -dict {LOC BF27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}] +set_property -dict {LOC BE27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}] +set_property -dict {LOC BF30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}] +set_property -dict {LOC BF29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}] +set_property -dict {LOC BB31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}] +set_property -dict {LOC BB32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}] +set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}] +set_property -dict {LOC AY33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}] +set_property -dict {LOC BC32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}] +set_property -dict {LOC BC33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}] +set_property -dict {LOC BB34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}] +set_property -dict {LOC BC34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}] +set_property -dict {LOC AV31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}] +set_property -dict {LOC AV32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}] +set_property -dict {LOC AV34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}] +set_property -dict {LOC AW34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}] +set_property -dict {LOC AW31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}] +set_property -dict {LOC AY31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}] +set_property -dict {LOC BA35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}] +set_property -dict {LOC BA34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}] +set_property -dict {LOC AL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}] +set_property -dict {LOC AM30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}] +set_property -dict {LOC AU32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}] +set_property -dict {LOC AT32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}] +set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}] +set_property -dict {LOC AN32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}] +set_property -dict {LOC AR32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}] +set_property -dict {LOC AR31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}] +set_property -dict {LOC AP29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}] +set_property -dict {LOC AP28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}] +set_property -dict {LOC AN27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}] +set_property -dict {LOC AM27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}] +set_property -dict {LOC AN29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}] +set_property -dict {LOC AM29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}] +set_property -dict {LOC AR27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}] +set_property -dict {LOC AR28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}] +set_property -dict {LOC AT28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}] +set_property -dict {LOC AV27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}] +set_property -dict {LOC AU27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}] +set_property -dict {LOC AT27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}] +set_property -dict {LOC AV29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}] +set_property -dict {LOC AY30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}] +set_property -dict {LOC AW30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}] +set_property -dict {LOC AV28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}] +set_property -dict {LOC BD34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}] +set_property -dict {LOC BD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}] +set_property -dict {LOC BE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}] +set_property -dict {LOC BD35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}] +set_property -dict {LOC BF32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}] +set_property -dict {LOC BF33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}] +set_property -dict {LOC BF34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}] +set_property -dict {LOC BF35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}] +set_property -dict {LOC BD40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}] +set_property -dict {LOC BD39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}] +set_property -dict {LOC BF43 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}] +set_property -dict {LOC BF42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}] +set_property -dict {LOC BF37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}] +set_property -dict {LOC BE37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}] +set_property -dict {LOC BE40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}] +set_property -dict {LOC BF41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}] +set_property -dict {LOC BA30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}] +set_property -dict {LOC BB30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}] +set_property -dict {LOC BB26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}] +set_property -dict {LOC BC26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}] +set_property -dict {LOC BD28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}] +set_property -dict {LOC BD29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}] +set_property -dict {LOC BD26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}] +set_property -dict {LOC BE26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}] +set_property -dict {LOC BB35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}] +set_property -dict {LOC BB36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}] +set_property -dict {LOC BC31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}] +set_property -dict {LOC BD31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}] +set_property -dict {LOC AV33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}] +set_property -dict {LOC AW33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}] +set_property -dict {LOC BA32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}] +set_property -dict {LOC BA33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}] +set_property -dict {LOC AM31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}] +set_property -dict {LOC AM32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}] +set_property -dict {LOC AP30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[9]}] +set_property -dict {LOC AP31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[9]}] +set_property -dict {LOC AL28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[10]}] +set_property -dict {LOC AL29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[10]}] +set_property -dict {LOC AR30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[11]}] +set_property -dict {LOC AT30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[11]}] +set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[12]}] +set_property -dict {LOC AU30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[12]}] +set_property -dict {LOC AY27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[13]}] +set_property -dict {LOC AY28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[13]}] +set_property -dict {LOC BE35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[14]}] +set_property -dict {LOC BE36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[14]}] +set_property -dict {LOC BE31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[15]}] +set_property -dict {LOC BE32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[15]}] +set_property -dict {LOC BE38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[16]}] +set_property -dict {LOC BF38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[16]}] +set_property -dict {LOC BF39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[17]}] +set_property -dict {LOC BF40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[17]}] + +# DDR4 C1 +set_property -dict {LOC AN24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}] +set_property -dict {LOC AT24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}] +set_property -dict {LOC AW24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}] +set_property -dict {LOC AN26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}] +set_property -dict {LOC AY22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}] +set_property -dict {LOC AY23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}] +set_property -dict {LOC AV24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}] +set_property -dict {LOC BA22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}] +set_property -dict {LOC AY25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}] +set_property -dict {LOC BA23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}] +set_property -dict {LOC AM26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}] +set_property -dict {LOC BA25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}] +set_property -dict {LOC BB22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}] +set_property -dict {LOC AL24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}] +set_property -dict {LOC AL25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}] +set_property -dict {LOC AM25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}] +set_property -dict {LOC AN23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}] +set_property -dict {LOC AU24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}] +set_property -dict {LOC AP26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}] +set_property -dict {LOC BC22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}] +set_property -dict {LOC AW26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}] +set_property -dict {LOC AT25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t[0]}] +set_property -dict {LOC AU25 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c[0]}] +#set_property -dict {LOC AU26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t[1]}] +#set_property -dict {LOC AV26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c[1]}] +set_property -dict {LOC BB25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[0]}] +#set_property -dict {LOC BB24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[1]}] +set_property -dict {LOC AV23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[0]}] +#set_property -dict {LOC AP25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[1]}] +#set_property -dict {LOC AR23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[2]}] +#set_property -dict {LOC AP23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[3]}] +set_property -dict {LOC AW25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}] +set_property -dict {LOC AW23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[0]}] +#set_property -dict {LOC AP24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[1]}] +set_property -dict {LOC AT23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}] +set_property -dict {LOC AR17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}] + +set_property -dict {LOC BD9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] +set_property -dict {LOC BD7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] +set_property -dict {LOC BC7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] +set_property -dict {LOC BD8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] +set_property -dict {LOC BD10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] +set_property -dict {LOC BE10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] +set_property -dict {LOC BE7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] +set_property -dict {LOC BF7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] +set_property -dict {LOC AU13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] +set_property -dict {LOC AV13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] +set_property -dict {LOC AW13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] +set_property -dict {LOC AW14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] +set_property -dict {LOC AU14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] +set_property -dict {LOC AY11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] +set_property -dict {LOC AV14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] +set_property -dict {LOC BA11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] +set_property -dict {LOC BA12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] +set_property -dict {LOC BB12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] +set_property -dict {LOC BA13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] +set_property -dict {LOC BA14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] +set_property -dict {LOC BC9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] +set_property -dict {LOC BB9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] +set_property -dict {LOC BA7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] +set_property -dict {LOC BA8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] +set_property -dict {LOC AN13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] +set_property -dict {LOC AR13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] +set_property -dict {LOC AM13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] +set_property -dict {LOC AP13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] +set_property -dict {LOC AM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] +set_property -dict {LOC AR15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] +set_property -dict {LOC AL14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] +set_property -dict {LOC AT15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] +set_property -dict {LOC BE13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] +set_property -dict {LOC BD14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] +set_property -dict {LOC BF12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] +set_property -dict {LOC BD13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] +set_property -dict {LOC BD15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] +set_property -dict {LOC BD16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] +set_property -dict {LOC BF14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] +set_property -dict {LOC BF13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] +set_property -dict {LOC AY17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] +set_property -dict {LOC BA17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] +set_property -dict {LOC AY18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] +set_property -dict {LOC BA18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] +set_property -dict {LOC BA15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] +set_property -dict {LOC BB15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] +set_property -dict {LOC BC11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] +set_property -dict {LOC BD11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] +set_property -dict {LOC AV16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] +set_property -dict {LOC AV17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] +set_property -dict {LOC AU16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] +set_property -dict {LOC AU17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] +set_property -dict {LOC BB17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] +set_property -dict {LOC BB16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] +set_property -dict {LOC AT18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] +set_property -dict {LOC AT17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] +set_property -dict {LOC AM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] +set_property -dict {LOC AL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] +set_property -dict {LOC AN17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] +set_property -dict {LOC AN16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] +set_property -dict {LOC AR18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] +set_property -dict {LOC AP18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] +set_property -dict {LOC AL17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] +set_property -dict {LOC AL16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] +set_property -dict {LOC BF25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}] +set_property -dict {LOC BF24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}] +set_property -dict {LOC BD25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}] +set_property -dict {LOC BE25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}] +set_property -dict {LOC BD23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}] +set_property -dict {LOC BC23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}] +set_property -dict {LOC BF23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}] +set_property -dict {LOC BE23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}] +set_property -dict {LOC BF10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] +set_property -dict {LOC BF9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] +set_property -dict {LOC BE8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] +set_property -dict {LOC BF8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] +set_property -dict {LOC AW15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] +set_property -dict {LOC AY15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] +set_property -dict {LOC AY13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] +set_property -dict {LOC AY12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] +set_property -dict {LOC BB11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] +set_property -dict {LOC BB10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] +set_property -dict {LOC BA10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] +set_property -dict {LOC BA9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] +set_property -dict {LOC AT14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] +set_property -dict {LOC AT13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] +set_property -dict {LOC AN14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] +set_property -dict {LOC AP14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] +set_property -dict {LOC BE12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}] +set_property -dict {LOC BE11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}] +set_property -dict {LOC BE15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}] +set_property -dict {LOC BF15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}] +set_property -dict {LOC BC13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[10]}] +set_property -dict {LOC BC12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[10]}] +set_property -dict {LOC BB14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[11]}] +set_property -dict {LOC BC14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[11]}] +set_property -dict {LOC AV18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[12]}] +set_property -dict {LOC AW18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[12]}] +set_property -dict {LOC AW16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[13]}] +set_property -dict {LOC AY16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[13]}] +set_property -dict {LOC AP16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[14]}] +set_property -dict {LOC AR16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[14]}] +set_property -dict {LOC AM17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[15]}] +set_property -dict {LOC AM16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[15]}] +set_property -dict {LOC BC24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[16]}] +set_property -dict {LOC BD24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[16]}] +set_property -dict {LOC BE22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[17]}] +set_property -dict {LOC BF22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[17]}] + +# DDR4 C2 +set_property -dict {LOC L29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[0]}] +set_property -dict {LOC A33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[1]}] +set_property -dict {LOC C33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[2]}] +set_property -dict {LOC J29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[3]}] +set_property -dict {LOC H31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[4]}] +set_property -dict {LOC G31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[5]}] +set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[6]}] +set_property -dict {LOC B32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[7]}] +set_property -dict {LOC A32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[8]}] +set_property -dict {LOC D31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[9]}] +set_property -dict {LOC A34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[10]}] +set_property -dict {LOC E31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[11]}] +set_property -dict {LOC M30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[12]}] +set_property -dict {LOC F33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[13]}] +set_property -dict {LOC A35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[14]}] +set_property -dict {LOC G32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[15]}] +set_property -dict {LOC K30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[16]}] +set_property -dict {LOC D33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[0]}] +set_property -dict {LOC B36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[1]}] +set_property -dict {LOC C31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[0]}] +set_property -dict {LOC J30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[1]}] +set_property -dict {LOC C34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t[0]}] +set_property -dict {LOC B34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c[0]}] +#set_property -dict {LOC D34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t[1]}] +#set_property -dict {LOC D35 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c[1]}] +set_property -dict {LOC G30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[0]}] +#set_property -dict {LOC E30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[1]}] +set_property -dict {LOC B35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[0]}] +#set_property -dict {LOC J31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[1]}] +#set_property -dict {LOC L30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[2]}] +#set_property -dict {LOC K31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[3]}] +set_property -dict {LOC B31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_act_n}] +set_property -dict {LOC E33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[0]}] +#set_property -dict {LOC F34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[1]}] +set_property -dict {LOC M29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_par}] +set_property -dict {LOC D36 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_reset_n}] + +set_property -dict {LOC R25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[0]}] +set_property -dict {LOC P25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[1]}] +set_property -dict {LOC M25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[2]}] +set_property -dict {LOC L25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[3]}] +set_property -dict {LOC P26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[4]}] +set_property -dict {LOC R26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[5]}] +set_property -dict {LOC N27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[6]}] +set_property -dict {LOC N28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[7]}] +set_property -dict {LOC J28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[8]}] +set_property -dict {LOC H29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[9]}] +set_property -dict {LOC H28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[10]}] +set_property -dict {LOC G29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[11]}] +set_property -dict {LOC K25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[12]}] +set_property -dict {LOC L27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[13]}] +set_property -dict {LOC K26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[14]}] +set_property -dict {LOC K27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[15]}] +set_property -dict {LOC F27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[16]}] +set_property -dict {LOC E27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[17]}] +set_property -dict {LOC E28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[18]}] +set_property -dict {LOC D28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[19]}] +set_property -dict {LOC G27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[20]}] +set_property -dict {LOC G26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[21]}] +set_property -dict {LOC F28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[22]}] +set_property -dict {LOC F29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[23]}] +set_property -dict {LOC D26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[24]}] +set_property -dict {LOC C26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[25]}] +set_property -dict {LOC B27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[26]}] +set_property -dict {LOC B26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[27]}] +set_property -dict {LOC A29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[28]}] +set_property -dict {LOC A30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[29]}] +set_property -dict {LOC C27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[30]}] +set_property -dict {LOC C28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[31]}] +set_property -dict {LOC F35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[32]}] +set_property -dict {LOC E38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[33]}] +set_property -dict {LOC D38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[34]}] +set_property -dict {LOC E35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[35]}] +set_property -dict {LOC E36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[36]}] +set_property -dict {LOC E37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[37]}] +set_property -dict {LOC F38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[38]}] +set_property -dict {LOC G38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[39]}] +set_property -dict {LOC P30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[40]}] +set_property -dict {LOC R30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[41]}] +set_property -dict {LOC P29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[42]}] +set_property -dict {LOC N29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[43]}] +set_property -dict {LOC L32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[44]}] +set_property -dict {LOC M32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[45]}] +set_property -dict {LOC P31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[46]}] +set_property -dict {LOC N32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[47]}] +set_property -dict {LOC J35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[48]}] +set_property -dict {LOC K35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[49]}] +set_property -dict {LOC L33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[50]}] +set_property -dict {LOC K33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[51]}] +set_property -dict {LOC J34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[52]}] +set_property -dict {LOC J33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[53]}] +set_property -dict {LOC N34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[54]}] +set_property -dict {LOC P34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[55]}] +set_property -dict {LOC H36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[56]}] +set_property -dict {LOC G36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[57]}] +set_property -dict {LOC H37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[58]}] +set_property -dict {LOC J36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[59]}] +set_property -dict {LOC K37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[60]}] +set_property -dict {LOC K38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[61]}] +set_property -dict {LOC G35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[62]}] +set_property -dict {LOC G34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[63]}] +set_property -dict {LOC C36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[64]}] +set_property -dict {LOC B37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[65]}] +set_property -dict {LOC A37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[66]}] +set_property -dict {LOC A38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[67]}] +set_property -dict {LOC C39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[68]}] +set_property -dict {LOC D39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[69]}] +set_property -dict {LOC A40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[70]}] +set_property -dict {LOC B40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[71]}] +set_property -dict {LOC N26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[0]}] +set_property -dict {LOC M26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[0]}] +set_property -dict {LOC R28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[1]}] +set_property -dict {LOC P28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[1]}] +set_property -dict {LOC J25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[2]}] +set_property -dict {LOC J26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[2]}] +set_property -dict {LOC M27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[3]}] +set_property -dict {LOC L28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[3]}] +set_property -dict {LOC D29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[4]}] +set_property -dict {LOC D30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[4]}] +set_property -dict {LOC H26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[5]}] +set_property -dict {LOC H27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[5]}] +set_property -dict {LOC A27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[6]}] +set_property -dict {LOC A28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[6]}] +set_property -dict {LOC C29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[7]}] +set_property -dict {LOC B29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[7]}] +set_property -dict {LOC E39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[8]}] +set_property -dict {LOC E40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[8]}] +set_property -dict {LOC G37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[9]}] +set_property -dict {LOC F37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[9]}] +set_property -dict {LOC N31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[10]}] +set_property -dict {LOC M31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[10]}] +set_property -dict {LOC T30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[11]}] +set_property -dict {LOC R31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[11]}] +set_property -dict {LOC L35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[12]}] +set_property -dict {LOC L36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[12]}] +set_property -dict {LOC M34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[13]}] +set_property -dict {LOC L34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[13]}] +set_property -dict {LOC J38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[14]}] +set_property -dict {LOC H38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[14]}] +set_property -dict {LOC H33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[15]}] +set_property -dict {LOC H34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[15]}] +set_property -dict {LOC B39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[16]}] +set_property -dict {LOC A39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[16]}] +set_property -dict {LOC C37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[17]}] +set_property -dict {LOC C38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[17]}] + +# DDR4 C3 +set_property -dict {LOC K15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[0]}] +set_property -dict {LOC B15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[1]}] +set_property -dict {LOC F14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[2]}] +set_property -dict {LOC A15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[3]}] +set_property -dict {LOC C14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[4]}] +set_property -dict {LOC A14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[5]}] +set_property -dict {LOC B14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[6]}] +set_property -dict {LOC E13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[7]}] +set_property -dict {LOC F13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[8]}] +set_property -dict {LOC A13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[9]}] +set_property -dict {LOC D14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[10]}] +set_property -dict {LOC C13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[11]}] +set_property -dict {LOC B13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[12]}] +set_property -dict {LOC K16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[13]}] +set_property -dict {LOC D15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[14]}] +set_property -dict {LOC E15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[15]}] +set_property -dict {LOC F15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[16]}] +set_property -dict {LOC J15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[0]}] +set_property -dict {LOC H14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[1]}] +set_property -dict {LOC D13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[0]}] +set_property -dict {LOC J13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[1]}] +set_property -dict {LOC L14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t[0]}] +set_property -dict {LOC L13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c[0]}] +#set_property -dict {LOC G14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t[1]}] +#set_property -dict {LOC G13 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c[1]}] +set_property -dict {LOC K13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[0]}] +#set_property -dict {LOC L15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[1]}] +set_property -dict {LOC B16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[0]}] +#set_property -dict {LOC D16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[1]}] +#set_property -dict {LOC M14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[2]}] +#set_property -dict {LOC M13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[3]}] +set_property -dict {LOC H13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_act_n}] +set_property -dict {LOC C16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[0]}] +#set_property -dict {LOC E16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[1]}] +set_property -dict {LOC J14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_par}] +set_property -dict {LOC D21 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c3_reset_n}] + +set_property -dict {LOC P24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[0]}] +set_property -dict {LOC N24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[1]}] +set_property -dict {LOC T24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[2]}] +set_property -dict {LOC R23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[3]}] +set_property -dict {LOC N23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[4]}] +set_property -dict {LOC P21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[5]}] +set_property -dict {LOC P23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[6]}] +set_property -dict {LOC R21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[7]}] +set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[8]}] +set_property -dict {LOC J23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[9]}] +set_property -dict {LOC H24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[10]}] +set_property -dict {LOC G24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[11]}] +set_property -dict {LOC L24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[12]}] +set_property -dict {LOC L23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[13]}] +set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[14]}] +set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[15]}] +set_property -dict {LOC G20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[16]}] +set_property -dict {LOC H17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[17]}] +set_property -dict {LOC F19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[18]}] +set_property -dict {LOC G17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[19]}] +set_property -dict {LOC J20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[20]}] +set_property -dict {LOC L19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[21]}] +set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[22]}] +set_property -dict {LOC J19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[23]}] +set_property -dict {LOC M19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[24]}] +set_property -dict {LOC M20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[25]}] +set_property -dict {LOC R18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[26]}] +set_property -dict {LOC R17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[27]}] +set_property -dict {LOC R20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[28]}] +set_property -dict {LOC T20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[29]}] +set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[30]}] +set_property -dict {LOC N19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[31]}] +set_property -dict {LOC A23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[32]}] +set_property -dict {LOC A22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[33]}] +set_property -dict {LOC B24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[34]}] +set_property -dict {LOC B25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[35]}] +set_property -dict {LOC B22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[36]}] +set_property -dict {LOC C22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[37]}] +set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[38]}] +set_property -dict {LOC C23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[39]}] +set_property -dict {LOC C19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[40]}] +set_property -dict {LOC C18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[41]}] +set_property -dict {LOC C21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[42]}] +set_property -dict {LOC B21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[43]}] +set_property -dict {LOC A18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[44]}] +set_property -dict {LOC A17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[45]}] +set_property -dict {LOC A20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[46]}] +set_property -dict {LOC B20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[47]}] +set_property -dict {LOC E17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[48]}] +set_property -dict {LOC F20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[49]}] +set_property -dict {LOC E18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[50]}] +set_property -dict {LOC E20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[51]}] +set_property -dict {LOC D19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[52]}] +set_property -dict {LOC D20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[53]}] +set_property -dict {LOC H18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[54]}] +set_property -dict {LOC J18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[55]}] +set_property -dict {LOC F22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[56]}] +set_property -dict {LOC E22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[57]}] +set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[58]}] +set_property -dict {LOC G21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[59]}] +set_property -dict {LOC F24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[60]}] +set_property -dict {LOC E25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[61]}] +set_property -dict {LOC F25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[62]}] +set_property -dict {LOC G25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[63]}] +set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[64]}] +set_property -dict {LOC N16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[65]}] +set_property -dict {LOC N13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[66]}] +set_property -dict {LOC N14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[67]}] +set_property -dict {LOC T15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[68]}] +set_property -dict {LOC R15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[69]}] +set_property -dict {LOC P13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[70]}] +set_property -dict {LOC P14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[71]}] +set_property -dict {LOC T22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[0]}] +set_property -dict {LOC R22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[0]}] +set_property -dict {LOC N22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[1]}] +set_property -dict {LOC N21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[1]}] +set_property -dict {LOC J21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[2]}] +set_property -dict {LOC H21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[2]}] +set_property -dict {LOC M22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[3]}] +set_property -dict {LOC L22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[3]}] +set_property -dict {LOC L20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[4]}] +set_property -dict {LOC K20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[4]}] +set_property -dict {LOC K18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[5]}] +set_property -dict {LOC K17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[5]}] +set_property -dict {LOC P19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[6]}] +set_property -dict {LOC P18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[6]}] +set_property -dict {LOC N17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[7]}] +set_property -dict {LOC M17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[7]}] +set_property -dict {LOC A25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[8]}] +set_property -dict {LOC A24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[8]}] +set_property -dict {LOC D24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[9]}] +set_property -dict {LOC D23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[9]}] +set_property -dict {LOC C17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[10]}] +set_property -dict {LOC B17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[10]}] +set_property -dict {LOC B19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[11]}] +set_property -dict {LOC A19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[11]}] +set_property -dict {LOC F18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[12]}] +set_property -dict {LOC F17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[12]}] +set_property -dict {LOC H19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[13]}] +set_property -dict {LOC G19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[13]}] +set_property -dict {LOC F23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[14]}] +set_property -dict {LOC E23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[14]}] +set_property -dict {LOC H23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[15]}] +set_property -dict {LOC H22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[15]}] +set_property -dict {LOC R16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[16]}] +set_property -dict {LOC P15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[16]}] +set_property -dict {LOC T13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[17]}] +set_property -dict {LOC R13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[17]}] diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile b/fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile index 1ea7629c8..9fe016fa7 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile @@ -140,6 +140,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl b/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl index 064601017..e4f635640 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/VCU1525/fpga_25g/fpga/config.tcl @@ -148,6 +148,12 @@ dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" dict set params RX_RAM_SIZE "131072" + +# RAM configuration +dict set params DDR_CH "4" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" # Application block configuration dict set params APP_ID "32'h00000000" @@ -200,6 +206,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile index 1ea7629c8..9fe016fa7 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile @@ -140,6 +140,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl index 9822704b5..37e8a700f 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/config.tcl @@ -148,6 +148,12 @@ dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" dict set params RX_RAM_SIZE "32768" + +# RAM configuration +dict set params DDR_CH "4" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" # Application block configuration dict set params APP_ID "32'h00000000" @@ -200,6 +206,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/VCU1525/fpga_25g/ip/ddr4_0.tcl b/fpga/mqnic/VCU1525/fpga_25g/ip/ddr4_0.tcl new file mode 100644 index 000000000..27252f502 --- /dev/null +++ b/fpga/mqnic/VCU1525/fpga_25g/ip/ddr4_0.tcl @@ -0,0 +1,17 @@ + +create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 + +set_property -dict [list \ + CONFIG.C0.DDR4_AxiSelection {true} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_AxiIDWidth {8} \ + CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ + CONFIG.C0.DDR4_TimePeriod {833} \ + CONFIG.C0.DDR4_InputClockPeriod {3332} \ + CONFIG.C0.DDR4_MemoryType {RDIMMs} \ + CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PZ-2G3} \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_CasLatency {17} \ + CONFIG.C0.DDR4_CasWriteLatency {12} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} +] [get_ips ddr4_0] diff --git a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v index 30264bc82..68804b8b5 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v @@ -112,6 +112,15 @@ module fpga # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // RAM configuration + parameter DDR_CH = 4, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 34, + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -177,6 +186,18 @@ module fpga # parameter STAT_ID_WIDTH = 12 ) ( + /* + * Clock and reset + */ + input wire clk_300mhz_0_p, + input wire clk_300mhz_0_n, + input wire clk_300mhz_1_p, + input wire clk_300mhz_1_n, + input wire clk_300mhz_2_p, + input wire clk_300mhz_2_n, + input wire clk_300mhz_3_p, + input wire clk_300mhz_3_n, + /* * GPIO */ @@ -257,7 +278,70 @@ module fpga # input wire qsfp1_intl, output wire qsfp1_lpmode, output wire qsfp1_refclk_reset, - output wire [1:0] qsfp1_fs + output wire [1:0] qsfp1_fs, + + /* + * DDR4 + */ + output wire [16:0] ddr4_c0_adr, + output wire [1:0] ddr4_c0_ba, + output wire [1:0] ddr4_c0_bg, + output wire [0:0] ddr4_c0_ck_t, + output wire [0:0] ddr4_c0_ck_c, + output wire [0:0] ddr4_c0_cke, + output wire [0:0] ddr4_c0_cs_n, + output wire ddr4_c0_act_n, + output wire [0:0] ddr4_c0_odt, + output wire ddr4_c0_par, + output wire ddr4_c0_reset_n, + inout wire [71:0] ddr4_c0_dq, + inout wire [17:0] ddr4_c0_dqs_t, + inout wire [17:0] ddr4_c0_dqs_c, + + output wire [16:0] ddr4_c1_adr, + output wire [1:0] ddr4_c1_ba, + output wire [1:0] ddr4_c1_bg, + output wire [0:0] ddr4_c1_ck_t, + output wire [0:0] ddr4_c1_ck_c, + output wire [0:0] ddr4_c1_cke, + output wire [0:0] ddr4_c1_cs_n, + output wire ddr4_c1_act_n, + output wire [0:0] ddr4_c1_odt, + output wire ddr4_c1_par, + output wire ddr4_c1_reset_n, + inout wire [71:0] ddr4_c1_dq, + inout wire [17:0] ddr4_c1_dqs_t, + inout wire [17:0] ddr4_c1_dqs_c, + + output wire [16:0] ddr4_c2_adr, + output wire [1:0] ddr4_c2_ba, + output wire [1:0] ddr4_c2_bg, + output wire [0:0] ddr4_c2_ck_t, + output wire [0:0] ddr4_c2_ck_c, + output wire [0:0] ddr4_c2_cke, + output wire [0:0] ddr4_c2_cs_n, + output wire ddr4_c2_act_n, + output wire [0:0] ddr4_c2_odt, + output wire ddr4_c2_par, + output wire ddr4_c2_reset_n, + inout wire [71:0] ddr4_c2_dq, + inout wire [17:0] ddr4_c2_dqs_t, + inout wire [17:0] ddr4_c2_dqs_c, + + output wire [16:0] ddr4_c3_adr, + output wire [1:0] ddr4_c3_ba, + output wire [1:0] ddr4_c3_bg, + output wire [0:0] ddr4_c3_ck_t, + output wire [0:0] ddr4_c3_ck_c, + output wire [0:0] ddr4_c3_cke, + output wire [0:0] ddr4_c3_cs_n, + output wire ddr4_c3_act_n, + output wire [0:0] ddr4_c3_odt, + output wire ddr4_c3_par, + output wire ddr4_c3_reset_n, + inout wire [71:0] ddr4_c3_dq, + inout wire [17:0] ddr4_c3_dqs_t, + inout wire [17:0] ddr4_c3_dqs_c ); // PTP configuration @@ -271,6 +355,9 @@ parameter IF_PTP_PERIOD_FNS = 16'h6666; // Interface configuration parameter TX_TAG_WIDTH = 16; +// RAM configuration +parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8); + // Ethernet interface configuration parameter XGMII_DATA_WIDTH = 64; parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8; @@ -1332,6 +1419,519 @@ assign ptp_clk = qsfp0_mgt_refclk_1_bufg; assign ptp_rst = qsfp0_rst; assign ptp_sample_clk = clk_125mhz_int; +// DDR4 +wire [DDR_CH-1:0] ddr_clk; +wire [DDR_CH-1:0] ddr_rst; + +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr; +wire [DDR_CH*8-1:0] m_axi_ddr_awlen; +wire [DDR_CH*3-1:0] m_axi_ddr_awsize; +wire [DDR_CH*2-1:0] m_axi_ddr_awburst; +wire [DDR_CH-1:0] m_axi_ddr_awlock; +wire [DDR_CH*4-1:0] m_axi_ddr_awcache; +wire [DDR_CH*3-1:0] m_axi_ddr_awprot; +wire [DDR_CH*4-1:0] m_axi_ddr_awqos; +wire [DDR_CH-1:0] m_axi_ddr_awvalid; +wire [DDR_CH-1:0] m_axi_ddr_awready; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata; +wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb; +wire [DDR_CH-1:0] m_axi_ddr_wlast; +wire [DDR_CH-1:0] m_axi_ddr_wvalid; +wire [DDR_CH-1:0] m_axi_ddr_wready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid; +wire [DDR_CH*2-1:0] m_axi_ddr_bresp; +wire [DDR_CH-1:0] m_axi_ddr_bvalid; +wire [DDR_CH-1:0] m_axi_ddr_bready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr; +wire [DDR_CH*8-1:0] m_axi_ddr_arlen; +wire [DDR_CH*3-1:0] m_axi_ddr_arsize; +wire [DDR_CH*2-1:0] m_axi_ddr_arburst; +wire [DDR_CH-1:0] m_axi_ddr_arlock; +wire [DDR_CH*4-1:0] m_axi_ddr_arcache; +wire [DDR_CH*3-1:0] m_axi_ddr_arprot; +wire [DDR_CH*4-1:0] m_axi_ddr_arqos; +wire [DDR_CH-1:0] m_axi_ddr_arvalid; +wire [DDR_CH-1:0] m_axi_ddr_arready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata; +wire [DDR_CH*2-1:0] m_axi_ddr_rresp; +wire [DDR_CH-1:0] m_axi_ddr_rlast; +wire [DDR_CH-1:0] m_axi_ddr_rvalid; +wire [DDR_CH-1:0] m_axi_ddr_rready; + +wire [DDR_CH-1:0] ddr_status; + +generate + +if (DDR_ENABLE && DDR_CH > 0) begin + +ddr4_0 ddr4_c0_inst ( + .c0_sys_clk_p(clk_300mhz_0_p), + .c0_sys_clk_n(clk_300mhz_0_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[0 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c0_adr), + .c0_ddr4_ba(ddr4_c0_ba), + .c0_ddr4_cke(ddr4_c0_cke), + .c0_ddr4_cs_n(ddr4_c0_cs_n), + .c0_ddr4_dq(ddr4_c0_dq), + .c0_ddr4_dqs_t(ddr4_c0_dqs_t), + .c0_ddr4_dqs_c(ddr4_c0_dqs_c), + .c0_ddr4_odt(ddr4_c0_odt), + .c0_ddr4_parity(ddr4_c0_par), + .c0_ddr4_bg(ddr4_c0_bg), + .c0_ddr4_reset_n(ddr4_c0_reset_n), + .c0_ddr4_act_n(ddr4_c0_act_n), + .c0_ddr4_ck_t(ddr4_c0_ck_t), + .c0_ddr4_ck_c(ddr4_c0_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[0 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[0 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c0_adr = {17{1'bz}}; +assign ddr4_c0_ba = {2{1'bz}}; +assign ddr4_c0_bg = {2{1'bz}}; +assign ddr4_c0_cke = 1'bz; +assign ddr4_c0_cs_n = 1'bz; +assign ddr4_c0_act_n = 1'bz; +assign ddr4_c0_odt = 1'bz; +assign ddr4_c0_par = 1'bz; +assign ddr4_c0_reset_n = 1'b0; +assign ddr4_c0_dq = {72{1'bz}}; +assign ddr4_c0_dqs_t = {18{1'bz}}; +assign ddr4_c0_dqs_c = {18{1'bz}}; + +OBUFTDS ddr4_c0_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c0_ck_t), + .OB(ddr4_c0_ck_c) +); + +assign ddr_clk = 0; +assign ddr_rst = 0; + +assign m_axi_ddr_awready = 0; +assign m_axi_ddr_wready = 0; +assign m_axi_ddr_bid = 0; +assign m_axi_ddr_bresp = 0; +assign m_axi_ddr_bvalid = 0; +assign m_axi_ddr_arready = 0; +assign m_axi_ddr_rid = 0; +assign m_axi_ddr_rdata = 0; +assign m_axi_ddr_rresp = 0; +assign m_axi_ddr_rlast = 0; +assign m_axi_ddr_rvalid = 0; + +assign ddr_status = 0; + +end + +if (DDR_ENABLE && DDR_CH > 1) begin + +ddr4_0 ddr4_c1_inst ( + .c0_sys_clk_p(clk_300mhz_1_p), + .c0_sys_clk_n(clk_300mhz_1_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[1 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c1_adr), + .c0_ddr4_ba(ddr4_c1_ba), + .c0_ddr4_cke(ddr4_c1_cke), + .c0_ddr4_cs_n(ddr4_c1_cs_n), + .c0_ddr4_dq(ddr4_c1_dq), + .c0_ddr4_dqs_t(ddr4_c1_dqs_t), + .c0_ddr4_dqs_c(ddr4_c1_dqs_c), + .c0_ddr4_odt(ddr4_c1_odt), + .c0_ddr4_parity(ddr4_c1_par), + .c0_ddr4_bg(ddr4_c1_bg), + .c0_ddr4_reset_n(ddr4_c1_reset_n), + .c0_ddr4_act_n(ddr4_c1_act_n), + .c0_ddr4_ck_t(ddr4_c1_ck_t), + .c0_ddr4_ck_c(ddr4_c1_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[1 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[1 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[1 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[1*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[1*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[1*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[1 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[1*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[1*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[1*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[1 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[1 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[1*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[1 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[1 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[1 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[1 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[1*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[1 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[1*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[1*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[1*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[1 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[1*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[1*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[1*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[1 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[1 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[1 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[1 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[1 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[1*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c1_adr = {17{1'bz}}; +assign ddr4_c1_ba = {2{1'bz}}; +assign ddr4_c1_bg = {2{1'bz}}; +assign ddr4_c1_cke = 1'bz; +assign ddr4_c1_cs_n = 1'bz; +assign ddr4_c1_act_n = 1'bz; +assign ddr4_c1_odt = 1'bz; +assign ddr4_c1_par = 1'bz; +assign ddr4_c1_reset_n = 1'b0; +assign ddr4_c1_dq = {72{1'bz}}; +assign ddr4_c1_dqs_t = {18{1'bz}}; +assign ddr4_c1_dqs_c = {18{1'bz}}; + +OBUFTDS ddr4_c1_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c1_ck_t), + .OB(ddr4_c1_ck_c) +); + +end + +if (DDR_ENABLE && DDR_CH > 2) begin + +ddr4_0 ddr4_c2_inst ( + .c0_sys_clk_p(clk_300mhz_2_p), + .c0_sys_clk_n(clk_300mhz_2_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[2 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c2_adr), + .c0_ddr4_ba(ddr4_c2_ba), + .c0_ddr4_cke(ddr4_c2_cke), + .c0_ddr4_cs_n(ddr4_c2_cs_n), + .c0_ddr4_dq(ddr4_c2_dq), + .c0_ddr4_dqs_t(ddr4_c2_dqs_t), + .c0_ddr4_dqs_c(ddr4_c2_dqs_c), + .c0_ddr4_odt(ddr4_c2_odt), + .c0_ddr4_parity(ddr4_c2_par), + .c0_ddr4_bg(ddr4_c2_bg), + .c0_ddr4_reset_n(ddr4_c2_reset_n), + .c0_ddr4_act_n(ddr4_c2_act_n), + .c0_ddr4_ck_t(ddr4_c2_ck_t), + .c0_ddr4_ck_c(ddr4_c2_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[2 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[2 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[2 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[2*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[2*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[2*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[2 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[2*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[2*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[2*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[2 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[2 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[2*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[2 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[2 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[2 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[2 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[2*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[2 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[2*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[2*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[2*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[2 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[2*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[2*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[2*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[2 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[2 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[2 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[2 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[2 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[2*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c2_adr = {17{1'bz}}; +assign ddr4_c2_ba = {2{1'bz}}; +assign ddr4_c2_bg = {2{1'bz}}; +assign ddr4_c2_cke = 1'bz; +assign ddr4_c2_cs_n = 1'bz; +assign ddr4_c2_act_n = 1'bz; +assign ddr4_c2_odt = 1'bz; +assign ddr4_c2_par = 1'bz; +assign ddr4_c2_reset_n = 1'b0; +assign ddr4_c2_dq = {72{1'bz}}; +assign ddr4_c2_dqs_t = {18{1'bz}}; +assign ddr4_c2_dqs_c = {18{1'bz}}; + +OBUFTDS ddr4_c2_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c2_ck_t), + .OB(ddr4_c2_ck_c) +); + +end + +if (DDR_ENABLE && DDR_CH > 3) begin + +ddr4_0 ddr4_c3_inst ( + .c0_sys_clk_p(clk_300mhz_3_p), + .c0_sys_clk_n(clk_300mhz_3_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[3 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c3_adr), + .c0_ddr4_ba(ddr4_c3_ba), + .c0_ddr4_cke(ddr4_c3_cke), + .c0_ddr4_cs_n(ddr4_c3_cs_n), + .c0_ddr4_dq(ddr4_c3_dq), + .c0_ddr4_dqs_t(ddr4_c3_dqs_t), + .c0_ddr4_dqs_c(ddr4_c3_dqs_c), + .c0_ddr4_odt(ddr4_c3_odt), + .c0_ddr4_parity(ddr4_c3_par), + .c0_ddr4_bg(ddr4_c3_bg), + .c0_ddr4_reset_n(ddr4_c3_reset_n), + .c0_ddr4_act_n(ddr4_c3_act_n), + .c0_ddr4_ck_t(ddr4_c3_ck_t), + .c0_ddr4_ck_c(ddr4_c3_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[3 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[3 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[3 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[3*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[3*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[3*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[3 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[3*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[3*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[3*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[3 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[3 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[3*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[3 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[3 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[3 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[3 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[3*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[3 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[3*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[3*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[3*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[3 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[3*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[3*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[3*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[3 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[3 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[3 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[3 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[3 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[3*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c3_adr = {17{1'bz}}; +assign ddr4_c3_ba = {2{1'bz}}; +assign ddr4_c3_bg = {2{1'bz}}; +assign ddr4_c3_cke = 1'bz; +assign ddr4_c3_cs_n = 1'bz; +assign ddr4_c3_act_n = 1'bz; +assign ddr4_c3_odt = 1'bz; +assign ddr4_c3_par = 1'bz; +assign ddr4_c3_reset_n = 1'b0; +assign ddr4_c3_dq = {72{1'bz}}; +assign ddr4_c3_dqs_t = {18{1'bz}}; +assign ddr4_c3_dqs_c = {18{1'bz}}; + +OBUFTDS ddr4_c3_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c3_ck_t), + .OB(ddr4_c3_ck_c) +); + +end + +endgenerate + fpga_core #( // FW and board IDs .FPGA_ID(FPGA_ID), @@ -1408,6 +2008,16 @@ fpga_core #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1713,6 +2323,52 @@ core_inst ( .qsfp1_intl(qsfp1_intl_int), .qsfp1_lpmode(qsfp1_lpmode), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + /* * QSPI flash */ diff --git a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v index f9b19d01c..749539699 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v @@ -122,6 +122,16 @@ module fpga_core # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // RAM configuration + parameter DDR_CH = 4, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 34, + parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -429,6 +439,52 @@ module fpga_core # input wire qsfp1_intl, output wire qsfp1_lpmode, + /* + * DDR + */ + input wire [DDR_CH-1:0] ddr_clk, + input wire [DDR_CH-1:0] ddr_rst, + + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, + output wire [DDR_CH-1:0] m_axi_ddr_awlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, + output wire [DDR_CH-1:0] m_axi_ddr_awvalid, + input wire [DDR_CH-1:0] m_axi_ddr_awready, + output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, + output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, + output wire [DDR_CH-1:0] m_axi_ddr_wlast, + output wire [DDR_CH-1:0] m_axi_ddr_wvalid, + input wire [DDR_CH-1:0] m_axi_ddr_wready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, + input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, + input wire [DDR_CH-1:0] m_axi_ddr_bvalid, + output wire [DDR_CH-1:0] m_axi_ddr_bready, + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, + output wire [DDR_CH-1:0] m_axi_ddr_arlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, + output wire [DDR_CH-1:0] m_axi_ddr_arvalid, + input wire [DDR_CH-1:0] m_axi_ddr_arready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, + input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, + input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, + input wire [DDR_CH-1:0] m_axi_ddr_rlast, + input wire [DDR_CH-1:0] m_axi_ddr_rvalid, + output wire [DDR_CH-1:0] m_axi_ddr_rready, + + input wire [DDR_CH-1:0] ddr_status, + /* * QSPI flash */ @@ -1093,6 +1149,25 @@ mqnic_core_pcie_us #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .DDR_GROUP_SIZE(1), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_AWUSER_ENABLE(0), + .AXI_DDR_WUSER_ENABLE(0), + .AXI_DDR_BUSER_ENABLE(0), + .AXI_DDR_ARUSER_ENABLE(0), + .AXI_DDR_RUSER_ENABLE(0), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + .AXI_DDR_FIXED_BURST(0), + .AXI_DDR_WRAP_BURST(1), + .HBM_ENABLE(0), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1370,6 +1445,108 @@ core_inst ( .eth_rx_status(eth_rx_status), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awuser(), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wuser(), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_buser(0), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_aruser(), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_ruser(0), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + + /* + * HBM + */ + .hbm_clk(0), + .hbm_rst(0), + + .m_axi_hbm_awid(), + .m_axi_hbm_awaddr(), + .m_axi_hbm_awlen(), + .m_axi_hbm_awsize(), + .m_axi_hbm_awburst(), + .m_axi_hbm_awlock(), + .m_axi_hbm_awcache(), + .m_axi_hbm_awprot(), + .m_axi_hbm_awqos(), + .m_axi_hbm_awuser(), + .m_axi_hbm_awvalid(), + .m_axi_hbm_awready(0), + .m_axi_hbm_wdata(), + .m_axi_hbm_wstrb(), + .m_axi_hbm_wlast(), + .m_axi_hbm_wuser(), + .m_axi_hbm_wvalid(), + .m_axi_hbm_wready(0), + .m_axi_hbm_bid(0), + .m_axi_hbm_bresp(0), + .m_axi_hbm_buser(0), + .m_axi_hbm_bvalid(0), + .m_axi_hbm_bready(), + .m_axi_hbm_arid(), + .m_axi_hbm_araddr(), + .m_axi_hbm_arlen(), + .m_axi_hbm_arsize(), + .m_axi_hbm_arburst(), + .m_axi_hbm_arlock(), + .m_axi_hbm_arcache(), + .m_axi_hbm_arprot(), + .m_axi_hbm_arqos(), + .m_axi_hbm_aruser(), + .m_axi_hbm_arvalid(), + .m_axi_hbm_arready(0), + .m_axi_hbm_rid(0), + .m_axi_hbm_rdata(0), + .m_axi_hbm_rresp(0), + .m_axi_hbm_rlast(0), + .m_axi_hbm_ruser(0), + .m_axi_hbm_rvalid(0), + .m_axi_hbm_rready(), + + .hbm_status(0), + /* * Statistics input */ diff --git a/fpga/mqnic/XUPP3R/fpga_100g/README.md b/fpga/mqnic/XUPP3R/fpga_100g/README.md index c00ed56e2..c2da8c52d 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/README.md +++ b/fpga/mqnic/XUPP3R/fpga_100g/README.md @@ -2,11 +2,12 @@ ## Introduction -This design targets the BittWare XUP-PR3 FPGA board. +This design targets the BittWare XUP-P3R FPGA board. * FPGA: xcvu9p-flgb2104-2-e * MAC: Xilinx 100G CMAC * PHY: 100G CAUI-4 CMAC and internal GTY transceivers +* RAM: 4x DDR4 DIMM ## How to build @@ -18,6 +19,6 @@ installed, otherwise the driver cannot be compiled. ## How to test -Run make program to program the XUP-PR3 board with Vivado. Then load the +Run make program to program the XUP-P3R board with Vivado. Then load the driver with insmod mqnic.ko. Check dmesg for output from driver initialization. diff --git a/fpga/mqnic/XUPP3R/fpga_100g/fpga.xdc b/fpga/mqnic/XUPP3R/fpga_100g/fpga.xdc index 658274940..addb346e9 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/fpga.xdc +++ b/fpga/mqnic/XUPP3R/fpga_100g/fpga.xdc @@ -29,23 +29,23 @@ create_clock -period 20.833 -name clk_48mhz [get_ports clk_48mhz] #create_clock -period 3.103 -name clk_b2 [get_ports clk_b2_p] # 100 MHz DDR4 module 1 clock from Si5338 A ch 0 -#set_property -dict {LOC AV18 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_1_p] -#set_property -dict {LOC AW18 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_1_n] +set_property -dict {LOC AV18 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_1_p] +set_property -dict {LOC AW18 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_1_n] #create_clock -period 10.000 -name clk_ddr_1 [get_ports clk_ddr_1_p] # 100 MHz DDR4 module 2 clock from Si5338 A ch 1 -#set_property -dict {LOC BB36 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_2_p] -#set_property -dict {LOC BC36 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_2_n] +set_property -dict {LOC BB36 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_2_p] +set_property -dict {LOC BC36 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_2_n] #create_clock -period 10.000 -name clk_ddr_2 [get_ports clk_ddr_2_p] # 100 MHz DDR4 module 3 clock from Si5338 A ch 2 -#set_property -dict {LOC E38 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_3_p] -#set_property -dict {LOC D38 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_3_n] +set_property -dict {LOC E38 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_3_p] +set_property -dict {LOC D38 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_3_n] #create_clock -period 10.000 -name clk_ddr_3 [get_ports clk_ddr_3_p] # 100 MHz DDR4 module 4 clock from Si5338 A ch 3 -#set_property -dict {LOC K18 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_4_p] -#set_property -dict {LOC J18 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_4_n] +set_property -dict {LOC K18 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_4_p] +set_property -dict {LOC J18 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_4_n] #create_clock -period 10.000 -name clk_ddr_4 [get_ports clk_ddr_4_p] # LEDs @@ -379,3 +379,599 @@ create_clock -period 10 -name pcie_mgt_refclk_0 [get_ports pcie_refclk_0_p] set_false_path -from [get_ports {pcie_reset_n}] set_input_delay 0 [get_ports {pcie_reset_n}] + +# DDR4 C0 +set_property -dict {LOC AT18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}] +set_property -dict {LOC AU17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}] +set_property -dict {LOC AP18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}] +set_property -dict {LOC AR18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}] +set_property -dict {LOC AP20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}] +set_property -dict {LOC AR20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}] +set_property -dict {LOC AU21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}] +set_property -dict {LOC AN18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}] +set_property -dict {LOC AN17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}] +set_property -dict {LOC AN19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}] +set_property -dict {LOC AP19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}] +set_property -dict {LOC AM16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}] +set_property -dict {LOC AN16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}] +set_property -dict {LOC AL19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}] +set_property -dict {LOC AM19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}] +set_property -dict {LOC AL20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}] +set_property -dict {LOC AM20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}] +# set_property -dict {LOC AP16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[17]}] +set_property -dict {LOC AT19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}] +set_property -dict {LOC AU19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}] +set_property -dict {LOC AT20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}] +set_property -dict {LOC AU20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}] +set_property -dict {LOC AR17 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c0_ck_t[0]}] +set_property -dict {LOC AT17 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c0_ck_c[0]}] +set_property -dict {LOC AY20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[0]}] +# set_property -dict {LOC AV21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[1]}] +set_property -dict {LOC BA18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[0]}] +# set_property -dict {LOC AW20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[1]}] +# set_property -dict {LOC BA17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[2]}] +# set_property -dict {LOC AY18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[3]}] +# set_property -dict {LOC AM17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_c[0]}] +# set_property -dict {LOC AU25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_c[1]}] +# set_property -dict {LOC AT14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_c[2]}] +set_property -dict {LOC AV17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}] +set_property -dict {LOC AW21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[0]}] +# set_property -dict {LOC AV19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[1]}] +set_property -dict {LOC AW19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}] +set_property -dict {LOC AY17 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_c0_reset_n}] + +set_property -dict {LOC AL28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}] +set_property -dict {LOC AL27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}] +set_property -dict {LOC AN27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}] +set_property -dict {LOC AM27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}] +set_property -dict {LOC AM25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}] +set_property -dict {LOC AL25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}] +set_property -dict {LOC AP28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}] +set_property -dict {LOC AN28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}] +set_property -dict {LOC AT28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}] +set_property -dict {LOC AR28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}] +set_property -dict {LOC AT27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}] +set_property -dict {LOC AR27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}] +set_property -dict {LOC AU27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}] +set_property -dict {LOC AU26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}] +set_property -dict {LOC AV28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}] +set_property -dict {LOC AV27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}] +set_property -dict {LOC AY28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}] +set_property -dict {LOC AW28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}] +set_property -dict {LOC AY27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}] +set_property -dict {LOC AY26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}] +set_property -dict {LOC BA28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}] +set_property -dict {LOC BA27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}] +set_property -dict {LOC BB27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}] +set_property -dict {LOC BB26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}] +set_property -dict {LOC BC27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}] +set_property -dict {LOC BC26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}] +set_property -dict {LOC BF25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}] +set_property -dict {LOC BE25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}] +set_property -dict {LOC BE28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}] +set_property -dict {LOC BD28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}] +set_property -dict {LOC BF27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}] +set_property -dict {LOC BE27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}] +set_property -dict {LOC AM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}] +set_property -dict {LOC AL14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}] +set_property -dict {LOC AM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}] +set_property -dict {LOC AL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}] +set_property -dict {LOC AN13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}] +set_property -dict {LOC AN14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}] +set_property -dict {LOC AP14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}] +set_property -dict {LOC AP15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}] +set_property -dict {LOC AV16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}] +set_property -dict {LOC AU16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}] +set_property -dict {LOC AU15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}] +set_property -dict {LOC AT15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}] +set_property -dict {LOC AV13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}] +set_property -dict {LOC AU13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}] +set_property -dict {LOC AW15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}] +set_property -dict {LOC AW16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}] +set_property -dict {LOC BA13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}] +set_property -dict {LOC AY13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}] +set_property -dict {LOC BA14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}] +set_property -dict {LOC BA15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}] +set_property -dict {LOC AY15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}] +set_property -dict {LOC AY16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}] +set_property -dict {LOC AY11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}] +set_property -dict {LOC AY12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}] +set_property -dict {LOC BC13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}] +set_property -dict {LOC BC14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}] +set_property -dict {LOC BD14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}] +set_property -dict {LOC BD15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}] +set_property -dict {LOC BE16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}] +set_property -dict {LOC BD16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}] +set_property -dict {LOC BF15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}] +set_property -dict {LOC BE15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}] +set_property -dict {LOC BC18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}] +set_property -dict {LOC BB19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}] +set_property -dict {LOC BC17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}] +set_property -dict {LOC BB17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}] +set_property -dict {LOC BE18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}] +set_property -dict {LOC BD18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}] +set_property -dict {LOC BF18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}] +set_property -dict {LOC BF19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}] +set_property -dict {LOC AM26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}] +set_property -dict {LOC AN26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}] +set_property -dict {LOC AP25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}] +set_property -dict {LOC AP26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}] +set_property -dict {LOC AR25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}] +set_property -dict {LOC AT25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}] +set_property -dict {LOC AV26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}] +set_property -dict {LOC AW26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}] +set_property -dict {LOC AW25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}] +set_property -dict {LOC AY25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}] +set_property -dict {LOC BA25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}] +set_property -dict {LOC BB25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}] +set_property -dict {LOC BD26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}] +set_property -dict {LOC BE26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}] +set_property -dict {LOC BF28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}] +set_property -dict {LOC BF29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}] +set_property -dict {LOC AP13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}] +set_property -dict {LOC AR13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}] +set_property -dict {LOC AR16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[9]}] +set_property -dict {LOC AR15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[9]}] +set_property -dict {LOC AU14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[10]}] +set_property -dict {LOC AV14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[10]}] +set_property -dict {LOC AW14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[11]}] +set_property -dict {LOC AW13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[11]}] +set_property -dict {LOC BB15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[12]}] +set_property -dict {LOC BB14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[12]}] +set_property -dict {LOC BA12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[13]}] +set_property -dict {LOC BB12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[13]}] +set_property -dict {LOC BD13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[14]}] +set_property -dict {LOC BE13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[14]}] +set_property -dict {LOC BF14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[15]}] +set_property -dict {LOC BF13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[15]}] +set_property -dict {LOC BC19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[16]}] +set_property -dict {LOC BD19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[16]}] +set_property -dict {LOC BE17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[17]}] +set_property -dict {LOC BF17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[17]}] + +# DDR4 C1 +set_property -dict {LOC AY33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}] +set_property -dict {LOC BA33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}] +set_property -dict {LOC AV34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}] +set_property -dict {LOC AW34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}] +set_property -dict {LOC AV33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}] +set_property -dict {LOC AW33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}] +set_property -dict {LOC AU34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}] +set_property -dict {LOC AT33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}] +set_property -dict {LOC AT34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}] +set_property -dict {LOC AP33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}] +set_property -dict {LOC AR33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}] +set_property -dict {LOC AN34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}] +set_property -dict {LOC AP34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}] +set_property -dict {LOC AL32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}] +set_property -dict {LOC AM32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}] +set_property -dict {LOC AL34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}] +set_property -dict {LOC AM34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}] +# set_property -dict {LOC AL33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[17]}] +set_property -dict {LOC BA34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}] +set_property -dict {LOC BB34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}] +set_property -dict {LOC AY35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}] +set_property -dict {LOC AY36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}] +set_property -dict {LOC AW35 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c1_ck_t[0]}] +set_property -dict {LOC AW36 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c1_ck_c[0]}] +set_property -dict {LOC BE36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[0]}] +# set_property -dict {LOC BB37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[1]}] +set_property -dict {LOC BE35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[0]}] +# set_property -dict {LOC BD36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[1]}] +# set_property -dict {LOC BD34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[2]}] +# set_property -dict {LOC BD35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[3]}] +# set_property -dict {LOC AN33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_c[0]}] +# set_property -dict {LOC AD30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_c[1]}] +# set_property -dict {LOC AT32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_c[2]}] +set_property -dict {LOC BF35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}] +set_property -dict {LOC BC37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[0]}] +# set_property -dict {LOC BA35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[1]}] +set_property -dict {LOC BB35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}] +set_property -dict {LOC BC34 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_c1_reset_n}] + +set_property -dict {LOC W34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] +set_property -dict {LOC W33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] +set_property -dict {LOC Y33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] +set_property -dict {LOC Y32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] +set_property -dict {LOC Y30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] +set_property -dict {LOC W30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] +set_property -dict {LOC AB34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] +set_property -dict {LOC AA34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] +set_property -dict {LOC AD34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] +set_property -dict {LOC AC34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] +set_property -dict {LOC AC33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] +set_property -dict {LOC AC32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] +set_property -dict {LOC AF30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] +set_property -dict {LOC AE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] +set_property -dict {LOC AE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] +set_property -dict {LOC AD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] +set_property -dict {LOC AF33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] +set_property -dict {LOC AF32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] +set_property -dict {LOC AG32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] +set_property -dict {LOC AG31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] +set_property -dict {LOC AG34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] +set_property -dict {LOC AF34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] +set_property -dict {LOC AJ33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] +set_property -dict {LOC AH33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] +set_property -dict {LOC AK31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] +set_property -dict {LOC AJ31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] +set_property -dict {LOC AG30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] +set_property -dict {LOC AG29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] +set_property -dict {LOC AJ30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] +set_property -dict {LOC AJ29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] +set_property -dict {LOC AK28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] +set_property -dict {LOC AJ28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] +set_property -dict {LOC AL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] +set_property -dict {LOC AL29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] +set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] +set_property -dict {LOC AM31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] +set_property -dict {LOC AP29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] +set_property -dict {LOC AN29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] +set_property -dict {LOC AR30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] +set_property -dict {LOC AP30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] +set_property -dict {LOC AT30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] +set_property -dict {LOC AT29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] +set_property -dict {LOC AU31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] +set_property -dict {LOC AU30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] +set_property -dict {LOC AV32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] +set_property -dict {LOC AU32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] +set_property -dict {LOC AW31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] +set_property -dict {LOC AV31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] +set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] +set_property -dict {LOC AY31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] +set_property -dict {LOC BA30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] +set_property -dict {LOC AY30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] +set_property -dict {LOC BB29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] +set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] +set_property -dict {LOC BB31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] +set_property -dict {LOC BB30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] +set_property -dict {LOC BD29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] +set_property -dict {LOC BC29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] +set_property -dict {LOC BE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] +set_property -dict {LOC BD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] +set_property -dict {LOC BF30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] +set_property -dict {LOC BE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] +set_property -dict {LOC BE32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] +set_property -dict {LOC BE31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] +set_property -dict {LOC BC38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}] +set_property -dict {LOC BB38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}] +set_property -dict {LOC BD39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}] +set_property -dict {LOC BC39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}] +set_property -dict {LOC BF37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}] +set_property -dict {LOC BE37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}] +set_property -dict {LOC BF38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}] +set_property -dict {LOC BE38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}] +set_property -dict {LOC W31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] +set_property -dict {LOC Y31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] +set_property -dict {LOC AA32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] +set_property -dict {LOC AA33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] +set_property -dict {LOC AC31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] +set_property -dict {LOC AD31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] +set_property -dict {LOC AE31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] +set_property -dict {LOC AE32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] +set_property -dict {LOC AH31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] +set_property -dict {LOC AH32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] +set_property -dict {LOC AH34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] +set_property -dict {LOC AJ34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] +set_property -dict {LOC AH28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] +set_property -dict {LOC AH29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] +set_property -dict {LOC AJ27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] +set_property -dict {LOC AK27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] +set_property -dict {LOC AM29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}] +set_property -dict {LOC AM30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}] +set_property -dict {LOC AP31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}] +set_property -dict {LOC AR31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}] +set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[10]}] +set_property -dict {LOC AV29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[10]}] +set_property -dict {LOC AW29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[11]}] +set_property -dict {LOC AW30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[11]}] +set_property -dict {LOC BA32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[12]}] +set_property -dict {LOC BB32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[12]}] +set_property -dict {LOC BC31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[13]}] +set_property -dict {LOC BC32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[13]}] +set_property -dict {LOC BD30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[14]}] +set_property -dict {LOC BD31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[14]}] +set_property -dict {LOC BF32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[15]}] +set_property -dict {LOC BF33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[15]}] +set_property -dict {LOC BD40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[16]}] +set_property -dict {LOC BE40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[16]}] +set_property -dict {LOC BF39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[17]}] +set_property -dict {LOC BF40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[17]}] + +# DDR4 C2 +set_property -dict {LOC A37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[0]}] +set_property -dict {LOC A38 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[1]}] +set_property -dict {LOC B35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[2]}] +set_property -dict {LOC A35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[3]}] +set_property -dict {LOC E35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[4]}] +set_property -dict {LOC D35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[5]}] +set_property -dict {LOC E37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[6]}] +set_property -dict {LOC B34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[7]}] +set_property -dict {LOC A34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[8]}] +set_property -dict {LOC D34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[9]}] +set_property -dict {LOC C34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[10]}] +set_property -dict {LOC D33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[11]}] +set_property -dict {LOC C33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[12]}] +set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[13]}] +set_property -dict {LOC B32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[14]}] +set_property -dict {LOC D31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[15]}] +set_property -dict {LOC C31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[16]}] +# set_property -dict {LOC B31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[17]}] +set_property -dict {LOC C36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[0]}] +set_property -dict {LOC C37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[1]}] +set_property -dict {LOC E36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[0]}] +set_property -dict {LOC D36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[1]}] +set_property -dict {LOC B36 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c2_ck_t[0]}] +set_property -dict {LOC B37 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c2_ck_c[0]}] +set_property -dict {LOC A40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[0]}] +# set_property -dict {LOC B39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[1]}] +set_property -dict {LOC D39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[0]}] +# set_property -dict {LOC B40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[1]}] +# set_property -dict {LOC D40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[2]}] +# set_property -dict {LOC E39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[3]}] +# set_property -dict {LOC A33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_c[0]}] +# set_property -dict {LOC K34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_c[1]}] +# set_property -dict {LOC E26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_c[2]}] +set_property -dict {LOC F38 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_act_n}] +set_property -dict {LOC A39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[0]}] +# set_property -dict {LOC C38 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[1]}] +set_property -dict {LOC C39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_par}] +set_property -dict {LOC E40 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_c2_reset_n}] + +set_property -dict {LOC E33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[0]}] +set_property -dict {LOC F33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[1]}] +set_property -dict {LOC E32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[2]}] +set_property -dict {LOC F32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[3]}] +set_property -dict {LOC G32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[4]}] +set_property -dict {LOC H32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[5]}] +set_property -dict {LOC G31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[6]}] +set_property -dict {LOC H31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[7]}] +set_property -dict {LOC K33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[8]}] +set_property -dict {LOC L33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[9]}] +set_property -dict {LOC J31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[10]}] +set_property -dict {LOC K31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[11]}] +set_property -dict {LOC L30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[12]}] +set_property -dict {LOC M30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[13]}] +set_property -dict {LOC K32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[14]}] +set_property -dict {LOC L32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[15]}] +set_property -dict {LOC N33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[16]}] +set_property -dict {LOC N32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[17]}] +set_property -dict {LOC N31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[18]}] +set_property -dict {LOC P31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[19]}] +set_property -dict {LOC N34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[20]}] +set_property -dict {LOC P34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[21]}] +set_property -dict {LOC R32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[22]}] +set_property -dict {LOC R31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[23]}] +set_property -dict {LOC T30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[24]}] +set_property -dict {LOC U30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[25]}] +set_property -dict {LOC U31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[26]}] +set_property -dict {LOC V31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[27]}] +set_property -dict {LOC T32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[28]}] +set_property -dict {LOC U32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[29]}] +set_property -dict {LOC R33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[30]}] +set_property -dict {LOC T33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[31]}] +set_property -dict {LOC A30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[32]}] +set_property -dict {LOC B30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[33]}] +set_property -dict {LOC A29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[34]}] +set_property -dict {LOC B29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[35]}] +set_property -dict {LOC D30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[36]}] +set_property -dict {LOC E30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[37]}] +set_property -dict {LOC C29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[38]}] +set_property -dict {LOC D29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[39]}] +set_property -dict {LOC D28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[40]}] +set_property -dict {LOC E28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[41]}] +set_property -dict {LOC E27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[42]}] +set_property -dict {LOC F27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[43]}] +set_property -dict {LOC G29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[44]}] +set_property -dict {LOC H29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[45]}] +set_property -dict {LOC G27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[46]}] +set_property -dict {LOC G26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[47]}] +set_property -dict {LOC J29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[48]}] +set_property -dict {LOC J28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[49]}] +set_property -dict {LOC H28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[50]}] +set_property -dict {LOC H27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[51]}] +set_property -dict {LOC L27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[52]}] +set_property -dict {LOC M27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[53]}] +set_property -dict {LOC K28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[54]}] +set_property -dict {LOC L28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[55]}] +set_property -dict {LOC N26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[56]}] +set_property -dict {LOC P26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[57]}] +set_property -dict {LOC N28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[58]}] +set_property -dict {LOC P28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[59]}] +set_property -dict {LOC R26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[60]}] +set_property -dict {LOC T26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[61]}] +set_property -dict {LOC R27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[62]}] +set_property -dict {LOC T27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[63]}] +set_property -dict {LOC F35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[64]}] +set_property -dict {LOC F34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[65]}] +set_property -dict {LOC G34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[66]}] +set_property -dict {LOC H34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[67]}] +set_property -dict {LOC J36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[68]}] +set_property -dict {LOC J35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[69]}] +set_property -dict {LOC F37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[70]}] +set_property -dict {LOC G37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[71]}] +set_property -dict {LOC J33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[0]}] +set_property -dict {LOC H33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[0]}] +set_property -dict {LOC G30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[1]}] +set_property -dict {LOC F30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[1]}] +set_property -dict {LOC K30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[2]}] +set_property -dict {LOC J30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[2]}] +set_property -dict {LOC M31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[3]}] +set_property -dict {LOC M32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[3]}] +set_property -dict {LOC M34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[4]}] +set_property -dict {LOC L34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[4]}] +set_property -dict {LOC R30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[5]}] +set_property -dict {LOC P30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[5]}] +set_property -dict {LOC V32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[6]}] +set_property -dict {LOC V33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[6]}] +set_property -dict {LOC U34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[7]}] +set_property -dict {LOC T34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[7]}] +set_property -dict {LOC A27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[8]}] +set_property -dict {LOC A28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[8]}] +set_property -dict {LOC C27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[9]}] +set_property -dict {LOC B27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[9]}] +set_property -dict {LOC F28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[10]}] +set_property -dict {LOC F29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[10]}] +set_property -dict {LOC J26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[11]}] +set_property -dict {LOC H26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[11]}] +set_property -dict {LOC K26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[12]}] +set_property -dict {LOC K27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[12]}] +set_property -dict {LOC M29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[13]}] +set_property -dict {LOC L29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[13]}] +set_property -dict {LOC P29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[14]}] +set_property -dict {LOC N29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[14]}] +set_property -dict {LOC T28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[15]}] +set_property -dict {LOC R28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[15]}] +set_property -dict {LOC H36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[16]}] +set_property -dict {LOC G36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[16]}] +set_property -dict {LOC H37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[17]}] +set_property -dict {LOC H38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[17]}] + +# DDR4 C3 +set_property -dict {LOC F20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[0]}] +set_property -dict {LOC F19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[1]}] +set_property -dict {LOC E21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[2]}] +set_property -dict {LOC E20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[3]}] +set_property -dict {LOC F18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[4]}] +set_property -dict {LOC F17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[5]}] +set_property -dict {LOC G21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[6]}] +set_property -dict {LOC D19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[7]}] +set_property -dict {LOC C19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[8]}] +set_property -dict {LOC D21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[9]}] +set_property -dict {LOC D20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[10]}] +set_property -dict {LOC C21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[11]}] +set_property -dict {LOC B21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[12]}] +set_property -dict {LOC B19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[13]}] +set_property -dict {LOC A19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[14]}] +set_property -dict {LOC B20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[15]}] +set_property -dict {LOC A20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[16]}] +# set_property -dict {LOC A18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[17]}] +set_property -dict {LOC H19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[0]}] +set_property -dict {LOC H18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[1]}] +set_property -dict {LOC G20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[0]}] +set_property -dict {LOC G19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[1]}] +set_property -dict {LOC E18 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c3_ck_t[0]}] +set_property -dict {LOC E17 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c3_ck_c[0]}] +set_property -dict {LOC K20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[0]}] +# set_property -dict {LOC J21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[1]}] +set_property -dict {LOC L18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[0]}] +# set_property -dict {LOC L20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[1]}] +# set_property -dict {LOC K17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[2]}] +# set_property -dict {LOC L19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[3]}] +# set_property -dict {LOC C18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_c[0]}] +# set_property -dict {LOC F25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_c[1]}] +# set_property -dict {LOC D14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_c[2]}] +set_property -dict {LOC K21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_act_n}] +set_property -dict {LOC H21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[0]}] +# set_property -dict {LOC J20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[1]}] +set_property -dict {LOC J19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_par}] +set_property -dict {LOC L17 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_c3_reset_n}] + +set_property -dict {LOC A25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[0]}] +set_property -dict {LOC B25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[1]}] +set_property -dict {LOC A24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[2]}] +set_property -dict {LOC B24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[3]}] +set_property -dict {LOC B26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[4]}] +set_property -dict {LOC C26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[5]}] +set_property -dict {LOC C23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[6]}] +set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[7]}] +set_property -dict {LOC D25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[8]}] +set_property -dict {LOC E25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[9]}] +set_property -dict {LOC D23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[10]}] +set_property -dict {LOC D24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[11]}] +set_property -dict {LOC F22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[12]}] +set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[13]}] +set_property -dict {LOC F23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[14]}] +set_property -dict {LOC F24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[15]}] +set_property -dict {LOC H24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[16]}] +set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[17]}] +set_property -dict {LOC H23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[18]}] +set_property -dict {LOC J23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[19]}] +set_property -dict {LOC K23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[20]}] +set_property -dict {LOC L23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[21]}] +set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[22]}] +set_property -dict {LOC L22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[23]}] +set_property -dict {LOC P25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[24]}] +set_property -dict {LOC R25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[25]}] +set_property -dict {LOC M24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[26]}] +set_property -dict {LOC M25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[27]}] +set_property -dict {LOC N23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[28]}] +set_property -dict {LOC P23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[29]}] +set_property -dict {LOC M22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[30]}] +set_property -dict {LOC N22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[31]}] +set_property -dict {LOC A17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[32]}] +set_property -dict {LOC B17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[33]}] +set_property -dict {LOC B16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[34]}] +set_property -dict {LOC C16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[35]}] +set_property -dict {LOC A13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[36]}] +set_property -dict {LOC A14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[37]}] +set_property -dict {LOC B14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[38]}] +set_property -dict {LOC C14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[39]}] +set_property -dict {LOC D16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[40]}] +set_property -dict {LOC E16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[41]}] +set_property -dict {LOC D15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[42]}] +set_property -dict {LOC E15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[43]}] +set_property -dict {LOC E13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[44]}] +set_property -dict {LOC F13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[45]}] +set_property -dict {LOC F15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[46]}] +set_property -dict {LOC G15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[47]}] +set_property -dict {LOC J15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[48]}] +set_property -dict {LOC J16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[49]}] +set_property -dict {LOC H14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[50]}] +set_property -dict {LOC J14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[51]}] +set_property -dict {LOC H13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[52]}] +set_property -dict {LOC J13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[53]}] +set_property -dict {LOC K15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[54]}] +set_property -dict {LOC K16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[55]}] +set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[56]}] +set_property -dict {LOC N16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[57]}] +set_property -dict {LOC L14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[58]}] +set_property -dict {LOC M14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[59]}] +set_property -dict {LOC P15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[60]}] +set_property -dict {LOC R15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[61]}] +set_property -dict {LOC N14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[62]}] +set_property -dict {LOC P14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[63]}] +set_property -dict {LOC M21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[64]}] +set_property -dict {LOC N21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[65]}] +set_property -dict {LOC P20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[66]}] +set_property -dict {LOC R20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[67]}] +set_property -dict {LOC M19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[68]}] +set_property -dict {LOC M20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[69]}] +set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[70]}] +set_property -dict {LOC P18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[71]}] +set_property -dict {LOC A23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[0]}] +set_property -dict {LOC A22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[0]}] +set_property -dict {LOC C22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[1]}] +set_property -dict {LOC B22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[1]}] +set_property -dict {LOC E23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[2]}] +set_property -dict {LOC E22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[2]}] +set_property -dict {LOC G25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[3]}] +set_property -dict {LOC G24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[3]}] +set_property -dict {LOC K25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[4]}] +set_property -dict {LOC J25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[4]}] +set_property -dict {LOC L25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[5]}] +set_property -dict {LOC L24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[5]}] +set_property -dict {LOC P24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[6]}] +set_property -dict {LOC N24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[6]}] +set_property -dict {LOC R21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[7]}] +set_property -dict {LOC P21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[7]}] +set_property -dict {LOC B15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[8]}] +set_property -dict {LOC A15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[8]}] +set_property -dict {LOC D13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[9]}] +set_property -dict {LOC C13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[9]}] +set_property -dict {LOC G17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[10]}] +set_property -dict {LOC G16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[10]}] +set_property -dict {LOC G14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[11]}] +set_property -dict {LOC F14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[11]}] +set_property -dict {LOC H17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[12]}] +set_property -dict {LOC H16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[12]}] +set_property -dict {LOC L13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[13]}] +set_property -dict {LOC K13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[13]}] +set_property -dict {LOC R16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[14]}] +set_property -dict {LOC P16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[14]}] +set_property -dict {LOC P13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[15]}] +set_property -dict {LOC N13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[15]}] +set_property -dict {LOC P19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[16]}] +set_property -dict {LOC N19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[16]}] +set_property -dict {LOC N17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[17]}] +set_property -dict {LOC M17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[17]}] diff --git a/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile b/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile index 7a6cb9c32..40bea31a5 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile @@ -120,6 +120,7 @@ IP_TCL_FILES += ip/cmac_usplus_0.tcl IP_TCL_FILES += ip/cmac_usplus_1.tcl IP_TCL_FILES += ip/cmac_usplus_2.tcl IP_TCL_FILES += ip/cmac_usplus_3.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl b/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl index 92cdad8f3..a1e6b0d5c 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/XUPP3R/fpga_100g/fpga/config.tcl @@ -136,6 +136,12 @@ dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "131072" dict set params RX_RAM_SIZE "131072" + +# RAM configuration +dict set params DDR_CH "4" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" # Application block configuration dict set params APP_ID "32'h00000000" @@ -187,6 +193,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/XUPP3R/fpga_100g/ip/ddr4_0.tcl b/fpga/mqnic/XUPP3R/fpga_100g/ip/ddr4_0.tcl new file mode 100644 index 000000000..4ddb8395c --- /dev/null +++ b/fpga/mqnic/XUPP3R/fpga_100g/ip/ddr4_0.tcl @@ -0,0 +1,17 @@ + +create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 + +set_property -dict [list \ + CONFIG.C0.DDR4_AxiSelection {true} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_AxiIDWidth {8} \ + CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ + CONFIG.C0.DDR4_TimePeriod {833} \ + CONFIG.C0.DDR4_InputClockPeriod {9996} \ + CONFIG.C0.DDR4_MemoryType {RDIMMs} \ + CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PZ-2G3} \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_CasLatency {17} \ + CONFIG.C0.DDR4_CasWriteLatency {12} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} +] [get_ips ddr4_0] diff --git a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v index d36b28aac..076f82530 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v @@ -109,6 +109,15 @@ module fpga # parameter TX_RAM_SIZE = 131072, parameter RX_RAM_SIZE = 131072, + // RAM configuration + parameter DDR_CH = 4, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 34, + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -177,6 +186,14 @@ module fpga # * Clock: 48MHz */ input wire clk_48mhz, + input wire clk_ddr_1_p, + input wire clk_ddr_1_n, + input wire clk_ddr_2_p, + input wire clk_ddr_2_n, + input wire clk_ddr_3_p, + input wire clk_ddr_3_n, + input wire clk_ddr_4_p, + input wire clk_ddr_4_n, /* * GPIO @@ -331,7 +348,70 @@ module fpga # input wire qsfp3_intl, output wire qsfp3_lpmode, inout wire qsfp3_i2c_scl, - inout wire qsfp3_i2c_sda + inout wire qsfp3_i2c_sda, + + /* + * DDR4 + */ + output wire [16:0] ddr4_c0_adr, + output wire [1:0] ddr4_c0_ba, + output wire [1:0] ddr4_c0_bg, + output wire [0:0] ddr4_c0_ck_t, + output wire [0:0] ddr4_c0_ck_c, + output wire [0:0] ddr4_c0_cke, + output wire [0:0] ddr4_c0_cs_n, + output wire ddr4_c0_act_n, + output wire [0:0] ddr4_c0_odt, + output wire ddr4_c0_par, + output wire ddr4_c0_reset_n, + inout wire [71:0] ddr4_c0_dq, + inout wire [17:0] ddr4_c0_dqs_t, + inout wire [17:0] ddr4_c0_dqs_c, + + output wire [16:0] ddr4_c1_adr, + output wire [1:0] ddr4_c1_ba, + output wire [1:0] ddr4_c1_bg, + output wire [0:0] ddr4_c1_ck_t, + output wire [0:0] ddr4_c1_ck_c, + output wire [0:0] ddr4_c1_cke, + output wire [0:0] ddr4_c1_cs_n, + output wire ddr4_c1_act_n, + output wire [0:0] ddr4_c1_odt, + output wire ddr4_c1_par, + output wire ddr4_c1_reset_n, + inout wire [71:0] ddr4_c1_dq, + inout wire [17:0] ddr4_c1_dqs_t, + inout wire [17:0] ddr4_c1_dqs_c, + + output wire [16:0] ddr4_c2_adr, + output wire [1:0] ddr4_c2_ba, + output wire [1:0] ddr4_c2_bg, + output wire [0:0] ddr4_c2_ck_t, + output wire [0:0] ddr4_c2_ck_c, + output wire [0:0] ddr4_c2_cke, + output wire [0:0] ddr4_c2_cs_n, + output wire ddr4_c2_act_n, + output wire [0:0] ddr4_c2_odt, + output wire ddr4_c2_par, + output wire ddr4_c2_reset_n, + inout wire [71:0] ddr4_c2_dq, + inout wire [17:0] ddr4_c2_dqs_t, + inout wire [17:0] ddr4_c2_dqs_c, + + output wire [16:0] ddr4_c3_adr, + output wire [1:0] ddr4_c3_ba, + output wire [1:0] ddr4_c3_bg, + output wire [0:0] ddr4_c3_ck_t, + output wire [0:0] ddr4_c3_ck_c, + output wire [0:0] ddr4_c3_cke, + output wire [0:0] ddr4_c3_cs_n, + output wire ddr4_c3_act_n, + output wire [0:0] ddr4_c3_odt, + output wire ddr4_c3_par, + output wire ddr4_c3_reset_n, + inout wire [71:0] ddr4_c3_dq, + inout wire [17:0] ddr4_c3_dqs_t, + inout wire [17:0] ddr4_c3_dqs_c ); // PTP configuration @@ -344,6 +424,9 @@ parameter PTP_SEPARATE_RX_CLOCK = 1; // Interface configuration parameter TX_TAG_WIDTH = 16; +// RAM configuration +parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8); + // Ethernet interface configuration parameter AXIS_ETH_DATA_WIDTH = 512; parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; @@ -2669,6 +2752,519 @@ assign led[1] = !qsfp1_rx_status; assign led[2] = !qsfp2_rx_status; assign led[3] = led_int[3]; +// DDR4 +wire [DDR_CH-1:0] ddr_clk; +wire [DDR_CH-1:0] ddr_rst; + +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr; +wire [DDR_CH*8-1:0] m_axi_ddr_awlen; +wire [DDR_CH*3-1:0] m_axi_ddr_awsize; +wire [DDR_CH*2-1:0] m_axi_ddr_awburst; +wire [DDR_CH-1:0] m_axi_ddr_awlock; +wire [DDR_CH*4-1:0] m_axi_ddr_awcache; +wire [DDR_CH*3-1:0] m_axi_ddr_awprot; +wire [DDR_CH*4-1:0] m_axi_ddr_awqos; +wire [DDR_CH-1:0] m_axi_ddr_awvalid; +wire [DDR_CH-1:0] m_axi_ddr_awready; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata; +wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb; +wire [DDR_CH-1:0] m_axi_ddr_wlast; +wire [DDR_CH-1:0] m_axi_ddr_wvalid; +wire [DDR_CH-1:0] m_axi_ddr_wready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid; +wire [DDR_CH*2-1:0] m_axi_ddr_bresp; +wire [DDR_CH-1:0] m_axi_ddr_bvalid; +wire [DDR_CH-1:0] m_axi_ddr_bready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr; +wire [DDR_CH*8-1:0] m_axi_ddr_arlen; +wire [DDR_CH*3-1:0] m_axi_ddr_arsize; +wire [DDR_CH*2-1:0] m_axi_ddr_arburst; +wire [DDR_CH-1:0] m_axi_ddr_arlock; +wire [DDR_CH*4-1:0] m_axi_ddr_arcache; +wire [DDR_CH*3-1:0] m_axi_ddr_arprot; +wire [DDR_CH*4-1:0] m_axi_ddr_arqos; +wire [DDR_CH-1:0] m_axi_ddr_arvalid; +wire [DDR_CH-1:0] m_axi_ddr_arready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata; +wire [DDR_CH*2-1:0] m_axi_ddr_rresp; +wire [DDR_CH-1:0] m_axi_ddr_rlast; +wire [DDR_CH-1:0] m_axi_ddr_rvalid; +wire [DDR_CH-1:0] m_axi_ddr_rready; + +wire [DDR_CH-1:0] ddr_status; + +generate + +if (DDR_ENABLE && DDR_CH > 0) begin + +ddr4_0 ddr4_c0_inst ( + .c0_sys_clk_p(clk_ddr_1_p), + .c0_sys_clk_n(clk_ddr_1_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[0 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c0_adr), + .c0_ddr4_ba(ddr4_c0_ba), + .c0_ddr4_cke(ddr4_c0_cke), + .c0_ddr4_cs_n(ddr4_c0_cs_n), + .c0_ddr4_dq(ddr4_c0_dq), + .c0_ddr4_dqs_t(ddr4_c0_dqs_t), + .c0_ddr4_dqs_c(ddr4_c0_dqs_c), + .c0_ddr4_odt(ddr4_c0_odt), + .c0_ddr4_parity(ddr4_c0_par), + .c0_ddr4_bg(ddr4_c0_bg), + .c0_ddr4_reset_n(ddr4_c0_reset_n), + .c0_ddr4_act_n(ddr4_c0_act_n), + .c0_ddr4_ck_t(ddr4_c0_ck_t), + .c0_ddr4_ck_c(ddr4_c0_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[0 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[0 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c0_adr = {17{1'bz}}; +assign ddr4_c0_ba = {2{1'bz}}; +assign ddr4_c0_bg = {2{1'bz}}; +assign ddr4_c0_cke = 1'bz; +assign ddr4_c0_cs_n = 1'bz; +assign ddr4_c0_act_n = 1'bz; +assign ddr4_c0_odt = 1'bz; +assign ddr4_c0_par = 1'bz; +assign ddr4_c0_reset_n = 1'b0; +assign ddr4_c0_dq = {72{1'bz}}; +assign ddr4_c0_dqs_t = {18{1'bz}}; +assign ddr4_c0_dqs_c = {18{1'bz}}; + +OBUFTDS ddr4_c0_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c0_ck_t), + .OB(ddr4_c0_ck_c) +); + +assign ddr_clk = 0; +assign ddr_rst = 0; + +assign m_axi_ddr_awready = 0; +assign m_axi_ddr_wready = 0; +assign m_axi_ddr_bid = 0; +assign m_axi_ddr_bresp = 0; +assign m_axi_ddr_bvalid = 0; +assign m_axi_ddr_arready = 0; +assign m_axi_ddr_rid = 0; +assign m_axi_ddr_rdata = 0; +assign m_axi_ddr_rresp = 0; +assign m_axi_ddr_rlast = 0; +assign m_axi_ddr_rvalid = 0; + +assign ddr_status = 0; + +end + +if (DDR_ENABLE && DDR_CH > 1) begin + +ddr4_0 ddr4_c1_inst ( + .c0_sys_clk_p(clk_ddr_2_p), + .c0_sys_clk_n(clk_ddr_2_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[1 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c1_adr), + .c0_ddr4_ba(ddr4_c1_ba), + .c0_ddr4_cke(ddr4_c1_cke), + .c0_ddr4_cs_n(ddr4_c1_cs_n), + .c0_ddr4_dq(ddr4_c1_dq), + .c0_ddr4_dqs_t(ddr4_c1_dqs_t), + .c0_ddr4_dqs_c(ddr4_c1_dqs_c), + .c0_ddr4_odt(ddr4_c1_odt), + .c0_ddr4_parity(ddr4_c1_par), + .c0_ddr4_bg(ddr4_c1_bg), + .c0_ddr4_reset_n(ddr4_c1_reset_n), + .c0_ddr4_act_n(ddr4_c1_act_n), + .c0_ddr4_ck_t(ddr4_c1_ck_t), + .c0_ddr4_ck_c(ddr4_c1_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[1 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[1 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[1 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[1*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[1*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[1*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[1 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[1*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[1*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[1*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[1 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[1 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[1*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[1 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[1 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[1 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[1 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[1*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[1 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[1*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[1*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[1*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[1 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[1*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[1*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[1*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[1 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[1 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[1 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[1 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[1 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[1*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c1_adr = {17{1'bz}}; +assign ddr4_c1_ba = {2{1'bz}}; +assign ddr4_c1_bg = {2{1'bz}}; +assign ddr4_c1_cke = 1'bz; +assign ddr4_c1_cs_n = 1'bz; +assign ddr4_c1_act_n = 1'bz; +assign ddr4_c1_odt = 1'bz; +assign ddr4_c1_par = 1'bz; +assign ddr4_c1_reset_n = 1'b0; +assign ddr4_c1_dq = {72{1'bz}}; +assign ddr4_c1_dqs_t = {18{1'bz}}; +assign ddr4_c1_dqs_c = {18{1'bz}}; + +OBUFTDS ddr4_c1_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c1_ck_t), + .OB(ddr4_c1_ck_c) +); + +end + +if (DDR_ENABLE && DDR_CH > 2) begin + +ddr4_0 ddr4_c2_inst ( + .c0_sys_clk_p(clk_ddr_3_p), + .c0_sys_clk_n(clk_ddr_3_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[2 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c2_adr), + .c0_ddr4_ba(ddr4_c2_ba), + .c0_ddr4_cke(ddr4_c2_cke), + .c0_ddr4_cs_n(ddr4_c2_cs_n), + .c0_ddr4_dq(ddr4_c2_dq), + .c0_ddr4_dqs_t(ddr4_c2_dqs_t), + .c0_ddr4_dqs_c(ddr4_c2_dqs_c), + .c0_ddr4_odt(ddr4_c2_odt), + .c0_ddr4_parity(ddr4_c2_par), + .c0_ddr4_bg(ddr4_c2_bg), + .c0_ddr4_reset_n(ddr4_c2_reset_n), + .c0_ddr4_act_n(ddr4_c2_act_n), + .c0_ddr4_ck_t(ddr4_c2_ck_t), + .c0_ddr4_ck_c(ddr4_c2_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[2 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[2 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[2 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[2*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[2*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[2*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[2 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[2*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[2*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[2*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[2 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[2 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[2*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[2 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[2 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[2 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[2 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[2*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[2 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[2*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[2*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[2*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[2 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[2*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[2*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[2*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[2 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[2 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[2 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[2 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[2 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[2*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c2_adr = {17{1'bz}}; +assign ddr4_c2_ba = {2{1'bz}}; +assign ddr4_c2_bg = {2{1'bz}}; +assign ddr4_c2_cke = 1'bz; +assign ddr4_c2_cs_n = 1'bz; +assign ddr4_c2_act_n = 1'bz; +assign ddr4_c2_odt = 1'bz; +assign ddr4_c2_par = 1'bz; +assign ddr4_c2_reset_n = 1'b0; +assign ddr4_c2_dq = {72{1'bz}}; +assign ddr4_c2_dqs_t = {18{1'bz}}; +assign ddr4_c2_dqs_c = {18{1'bz}}; + +OBUFTDS ddr4_c2_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c2_ck_t), + .OB(ddr4_c2_ck_c) +); + +end + +if (DDR_ENABLE && DDR_CH > 3) begin + +ddr4_0 ddr4_c3_inst ( + .c0_sys_clk_p(clk_ddr_4_p), + .c0_sys_clk_n(clk_ddr_4_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[3 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c3_adr), + .c0_ddr4_ba(ddr4_c3_ba), + .c0_ddr4_cke(ddr4_c3_cke), + .c0_ddr4_cs_n(ddr4_c3_cs_n), + .c0_ddr4_dq(ddr4_c3_dq), + .c0_ddr4_dqs_t(ddr4_c3_dqs_t), + .c0_ddr4_dqs_c(ddr4_c3_dqs_c), + .c0_ddr4_odt(ddr4_c3_odt), + .c0_ddr4_parity(ddr4_c3_par), + .c0_ddr4_bg(ddr4_c3_bg), + .c0_ddr4_reset_n(ddr4_c3_reset_n), + .c0_ddr4_act_n(ddr4_c3_act_n), + .c0_ddr4_ck_t(ddr4_c3_ck_t), + .c0_ddr4_ck_c(ddr4_c3_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[3 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[3 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[3 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[3*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[3*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[3*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[3 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[3*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[3*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[3*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[3 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[3 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[3*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[3 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[3 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[3 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[3 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[3*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[3 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[3*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[3*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[3*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[3 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[3*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[3*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[3*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[3 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[3 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[3 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[3 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[3 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[3*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c3_adr = {17{1'bz}}; +assign ddr4_c3_ba = {2{1'bz}}; +assign ddr4_c3_bg = {2{1'bz}}; +assign ddr4_c3_cke = 1'bz; +assign ddr4_c3_cs_n = 1'bz; +assign ddr4_c3_act_n = 1'bz; +assign ddr4_c3_odt = 1'bz; +assign ddr4_c3_par = 1'bz; +assign ddr4_c3_reset_n = 1'b0; +assign ddr4_c3_dq = {72{1'bz}}; +assign ddr4_c3_dqs_t = {18{1'bz}}; +assign ddr4_c3_dqs_c = {18{1'bz}}; + +OBUFTDS ddr4_c3_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c3_ck_t), + .OB(ddr4_c3_ck_c) +); + +end + +endgenerate + fpga_core #( // FW and board IDs .FPGA_ID(FPGA_ID), @@ -2743,6 +3339,16 @@ fpga_core #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -3071,6 +3677,52 @@ core_inst ( .qsfp3_i2c_sda_o(qsfp3_i2c_sda_o), .qsfp3_i2c_sda_t(qsfp3_i2c_sda_t), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + /* * QSPI flash */ diff --git a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v index 547b78e4c..7a5f306c8 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v @@ -115,6 +115,16 @@ module fpga_core # parameter TX_RAM_SIZE = 131072, parameter RX_RAM_SIZE = 131072, + // RAM configuration + parameter DDR_CH = 4, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 34, + parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -459,6 +469,52 @@ module fpga_core # output wire qsfp3_i2c_sda_o, output wire qsfp3_i2c_sda_t, + /* + * DDR + */ + input wire [DDR_CH-1:0] ddr_clk, + input wire [DDR_CH-1:0] ddr_rst, + + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, + output wire [DDR_CH-1:0] m_axi_ddr_awlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, + output wire [DDR_CH-1:0] m_axi_ddr_awvalid, + input wire [DDR_CH-1:0] m_axi_ddr_awready, + output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, + output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, + output wire [DDR_CH-1:0] m_axi_ddr_wlast, + output wire [DDR_CH-1:0] m_axi_ddr_wvalid, + input wire [DDR_CH-1:0] m_axi_ddr_wready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, + input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, + input wire [DDR_CH-1:0] m_axi_ddr_bvalid, + output wire [DDR_CH-1:0] m_axi_ddr_bready, + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, + output wire [DDR_CH-1:0] m_axi_ddr_arlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, + output wire [DDR_CH-1:0] m_axi_ddr_arvalid, + input wire [DDR_CH-1:0] m_axi_ddr_arready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, + input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, + input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, + input wire [DDR_CH-1:0] m_axi_ddr_rlast, + input wire [DDR_CH-1:0] m_axi_ddr_rvalid, + output wire [DDR_CH-1:0] m_axi_ddr_rready, + + input wire [DDR_CH-1:0] ddr_status, + /* * QSPI flash */ @@ -1082,6 +1138,25 @@ mqnic_core_pcie_us #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .DDR_GROUP_SIZE(1), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_AWUSER_ENABLE(0), + .AXI_DDR_WUSER_ENABLE(0), + .AXI_DDR_BUSER_ENABLE(0), + .AXI_DDR_ARUSER_ENABLE(0), + .AXI_DDR_RUSER_ENABLE(0), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + .AXI_DDR_FIXED_BURST(0), + .AXI_DDR_WRAP_BURST(1), + .HBM_ENABLE(0), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1359,6 +1434,108 @@ core_inst ( .eth_rx_status(eth_rx_status), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awuser(), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wuser(), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_buser(0), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_aruser(), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_ruser(0), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + + /* + * HBM + */ + .hbm_clk(0), + .hbm_rst(0), + + .m_axi_hbm_awid(), + .m_axi_hbm_awaddr(), + .m_axi_hbm_awlen(), + .m_axi_hbm_awsize(), + .m_axi_hbm_awburst(), + .m_axi_hbm_awlock(), + .m_axi_hbm_awcache(), + .m_axi_hbm_awprot(), + .m_axi_hbm_awqos(), + .m_axi_hbm_awuser(), + .m_axi_hbm_awvalid(), + .m_axi_hbm_awready(0), + .m_axi_hbm_wdata(), + .m_axi_hbm_wstrb(), + .m_axi_hbm_wlast(), + .m_axi_hbm_wuser(), + .m_axi_hbm_wvalid(), + .m_axi_hbm_wready(0), + .m_axi_hbm_bid(0), + .m_axi_hbm_bresp(0), + .m_axi_hbm_buser(0), + .m_axi_hbm_bvalid(0), + .m_axi_hbm_bready(), + .m_axi_hbm_arid(), + .m_axi_hbm_araddr(), + .m_axi_hbm_arlen(), + .m_axi_hbm_arsize(), + .m_axi_hbm_arburst(), + .m_axi_hbm_arlock(), + .m_axi_hbm_arcache(), + .m_axi_hbm_arprot(), + .m_axi_hbm_arqos(), + .m_axi_hbm_aruser(), + .m_axi_hbm_arvalid(), + .m_axi_hbm_arready(0), + .m_axi_hbm_rid(0), + .m_axi_hbm_rdata(0), + .m_axi_hbm_rresp(0), + .m_axi_hbm_rlast(0), + .m_axi_hbm_ruser(0), + .m_axi_hbm_rvalid(0), + .m_axi_hbm_rready(), + + .hbm_status(0), + /* * Statistics input */ diff --git a/fpga/mqnic/XUPP3R/fpga_25g/README.md b/fpga/mqnic/XUPP3R/fpga_25g/README.md index fe66bf46c..8b91b12b4 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/README.md +++ b/fpga/mqnic/XUPP3R/fpga_25g/README.md @@ -6,6 +6,7 @@ This design targets the BittWare XUP-P3R FPGA board. * FPGA: xcvu9p-flgb2104-2-e * PHY: 10G BASE-R PHY IP core and internal GTY transceiver +* RAM: 4x DDR4 DIMM ## How to build diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga.xdc b/fpga/mqnic/XUPP3R/fpga_25g/fpga.xdc index 611b9d747..b03372f7f 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga.xdc +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga.xdc @@ -29,23 +29,23 @@ create_clock -period 20.833 -name clk_48mhz [get_ports clk_48mhz] #create_clock -period 3.103 -name clk_b2 [get_ports clk_b2_p] # 100 MHz DDR4 module 1 clock from Si5338 A ch 0 -#set_property -dict {LOC AV18 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_1_p] -#set_property -dict {LOC AW18 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_1_n] +set_property -dict {LOC AV18 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_1_p] +set_property -dict {LOC AW18 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_1_n] #create_clock -period 10.000 -name clk_ddr_1 [get_ports clk_ddr_1_p] # 100 MHz DDR4 module 2 clock from Si5338 A ch 1 -#set_property -dict {LOC BB36 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_2_p] -#set_property -dict {LOC BC36 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_2_n] +set_property -dict {LOC BB36 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_2_p] +set_property -dict {LOC BC36 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_2_n] #create_clock -period 10.000 -name clk_ddr_2 [get_ports clk_ddr_2_p] # 100 MHz DDR4 module 3 clock from Si5338 A ch 2 -#set_property -dict {LOC E38 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_3_p] -#set_property -dict {LOC D38 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_3_n] +set_property -dict {LOC E38 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_3_p] +set_property -dict {LOC D38 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_3_n] #create_clock -period 10.000 -name clk_ddr_3 [get_ports clk_ddr_3_p] # 100 MHz DDR4 module 4 clock from Si5338 A ch 3 -#set_property -dict {LOC K18 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_4_p] -#set_property -dict {LOC J18 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_4_n] +set_property -dict {LOC K18 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_4_p] +set_property -dict {LOC J18 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr_4_n] #create_clock -period 10.000 -name clk_ddr_4 [get_ports clk_ddr_4_p] # LEDs @@ -379,3 +379,599 @@ create_clock -period 10 -name pcie_mgt_refclk_0 [get_ports pcie_refclk_0_p] set_false_path -from [get_ports {pcie_reset_n}] set_input_delay 0 [get_ports {pcie_reset_n}] + +# DDR4 C0 +set_property -dict {LOC AT18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}] +set_property -dict {LOC AU17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}] +set_property -dict {LOC AP18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}] +set_property -dict {LOC AR18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}] +set_property -dict {LOC AP20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}] +set_property -dict {LOC AR20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}] +set_property -dict {LOC AU21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}] +set_property -dict {LOC AN18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}] +set_property -dict {LOC AN17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}] +set_property -dict {LOC AN19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}] +set_property -dict {LOC AP19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}] +set_property -dict {LOC AM16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}] +set_property -dict {LOC AN16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}] +set_property -dict {LOC AL19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}] +set_property -dict {LOC AM19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}] +set_property -dict {LOC AL20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}] +set_property -dict {LOC AM20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}] +# set_property -dict {LOC AP16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[17]}] +set_property -dict {LOC AT19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}] +set_property -dict {LOC AU19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}] +set_property -dict {LOC AT20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}] +set_property -dict {LOC AU20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}] +set_property -dict {LOC AR17 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c0_ck_t[0]}] +set_property -dict {LOC AT17 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c0_ck_c[0]}] +set_property -dict {LOC AY20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[0]}] +# set_property -dict {LOC AV21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke[1]}] +set_property -dict {LOC BA18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[0]}] +# set_property -dict {LOC AW20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[1]}] +# set_property -dict {LOC BA17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[2]}] +# set_property -dict {LOC AY18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n[3]}] +# set_property -dict {LOC AM17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_c[0]}] +# set_property -dict {LOC AU25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_c[1]}] +# set_property -dict {LOC AT14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_c[2]}] +set_property -dict {LOC AV17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}] +set_property -dict {LOC AW21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[0]}] +# set_property -dict {LOC AV19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt[1]}] +set_property -dict {LOC AW19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}] +set_property -dict {LOC AY17 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_c0_reset_n}] + +set_property -dict {LOC AL28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}] +set_property -dict {LOC AL27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}] +set_property -dict {LOC AN27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}] +set_property -dict {LOC AM27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}] +set_property -dict {LOC AM25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}] +set_property -dict {LOC AL25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}] +set_property -dict {LOC AP28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}] +set_property -dict {LOC AN28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}] +set_property -dict {LOC AT28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}] +set_property -dict {LOC AR28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}] +set_property -dict {LOC AT27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}] +set_property -dict {LOC AR27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}] +set_property -dict {LOC AU27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}] +set_property -dict {LOC AU26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}] +set_property -dict {LOC AV28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}] +set_property -dict {LOC AV27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}] +set_property -dict {LOC AY28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}] +set_property -dict {LOC AW28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}] +set_property -dict {LOC AY27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}] +set_property -dict {LOC AY26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}] +set_property -dict {LOC BA28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}] +set_property -dict {LOC BA27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}] +set_property -dict {LOC BB27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}] +set_property -dict {LOC BB26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}] +set_property -dict {LOC BC27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}] +set_property -dict {LOC BC26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}] +set_property -dict {LOC BF25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}] +set_property -dict {LOC BE25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}] +set_property -dict {LOC BE28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}] +set_property -dict {LOC BD28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}] +set_property -dict {LOC BF27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}] +set_property -dict {LOC BE27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}] +set_property -dict {LOC AM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}] +set_property -dict {LOC AL14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}] +set_property -dict {LOC AM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}] +set_property -dict {LOC AL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}] +set_property -dict {LOC AN13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}] +set_property -dict {LOC AN14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}] +set_property -dict {LOC AP14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}] +set_property -dict {LOC AP15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}] +set_property -dict {LOC AV16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}] +set_property -dict {LOC AU16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}] +set_property -dict {LOC AU15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}] +set_property -dict {LOC AT15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}] +set_property -dict {LOC AV13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}] +set_property -dict {LOC AU13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}] +set_property -dict {LOC AW15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}] +set_property -dict {LOC AW16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}] +set_property -dict {LOC BA13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}] +set_property -dict {LOC AY13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}] +set_property -dict {LOC BA14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}] +set_property -dict {LOC BA15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}] +set_property -dict {LOC AY15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}] +set_property -dict {LOC AY16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}] +set_property -dict {LOC AY11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}] +set_property -dict {LOC AY12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}] +set_property -dict {LOC BC13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}] +set_property -dict {LOC BC14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}] +set_property -dict {LOC BD14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}] +set_property -dict {LOC BD15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}] +set_property -dict {LOC BE16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}] +set_property -dict {LOC BD16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}] +set_property -dict {LOC BF15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}] +set_property -dict {LOC BE15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}] +set_property -dict {LOC BC18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}] +set_property -dict {LOC BB19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}] +set_property -dict {LOC BC17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}] +set_property -dict {LOC BB17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}] +set_property -dict {LOC BE18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}] +set_property -dict {LOC BD18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}] +set_property -dict {LOC BF18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}] +set_property -dict {LOC BF19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}] +set_property -dict {LOC AM26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}] +set_property -dict {LOC AN26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}] +set_property -dict {LOC AP25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}] +set_property -dict {LOC AP26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}] +set_property -dict {LOC AR25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}] +set_property -dict {LOC AT25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}] +set_property -dict {LOC AV26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}] +set_property -dict {LOC AW26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}] +set_property -dict {LOC AW25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}] +set_property -dict {LOC AY25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}] +set_property -dict {LOC BA25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}] +set_property -dict {LOC BB25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}] +set_property -dict {LOC BD26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}] +set_property -dict {LOC BE26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}] +set_property -dict {LOC BF28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}] +set_property -dict {LOC BF29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}] +set_property -dict {LOC AP13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}] +set_property -dict {LOC AR13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}] +set_property -dict {LOC AR16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[9]}] +set_property -dict {LOC AR15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[9]}] +set_property -dict {LOC AU14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[10]}] +set_property -dict {LOC AV14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[10]}] +set_property -dict {LOC AW14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[11]}] +set_property -dict {LOC AW13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[11]}] +set_property -dict {LOC BB15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[12]}] +set_property -dict {LOC BB14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[12]}] +set_property -dict {LOC BA12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[13]}] +set_property -dict {LOC BB12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[13]}] +set_property -dict {LOC BD13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[14]}] +set_property -dict {LOC BE13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[14]}] +set_property -dict {LOC BF14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[15]}] +set_property -dict {LOC BF13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[15]}] +set_property -dict {LOC BC19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[16]}] +set_property -dict {LOC BD19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[16]}] +set_property -dict {LOC BE17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[17]}] +set_property -dict {LOC BF17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[17]}] + +# DDR4 C1 +set_property -dict {LOC AY33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}] +set_property -dict {LOC BA33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}] +set_property -dict {LOC AV34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}] +set_property -dict {LOC AW34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}] +set_property -dict {LOC AV33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}] +set_property -dict {LOC AW33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}] +set_property -dict {LOC AU34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}] +set_property -dict {LOC AT33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}] +set_property -dict {LOC AT34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}] +set_property -dict {LOC AP33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}] +set_property -dict {LOC AR33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}] +set_property -dict {LOC AN34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}] +set_property -dict {LOC AP34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}] +set_property -dict {LOC AL32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}] +set_property -dict {LOC AM32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}] +set_property -dict {LOC AL34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}] +set_property -dict {LOC AM34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}] +# set_property -dict {LOC AL33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[17]}] +set_property -dict {LOC BA34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}] +set_property -dict {LOC BB34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}] +set_property -dict {LOC AY35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}] +set_property -dict {LOC AY36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}] +set_property -dict {LOC AW35 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c1_ck_t[0]}] +set_property -dict {LOC AW36 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c1_ck_c[0]}] +set_property -dict {LOC BE36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[0]}] +# set_property -dict {LOC BB37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke[1]}] +set_property -dict {LOC BE35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[0]}] +# set_property -dict {LOC BD36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[1]}] +# set_property -dict {LOC BD34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[2]}] +# set_property -dict {LOC BD35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n[3]}] +# set_property -dict {LOC AN33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_c[0]}] +# set_property -dict {LOC AD30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_c[1]}] +# set_property -dict {LOC AT32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_c[2]}] +set_property -dict {LOC BF35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}] +set_property -dict {LOC BC37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[0]}] +# set_property -dict {LOC BA35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt[1]}] +set_property -dict {LOC BB35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}] +set_property -dict {LOC BC34 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_c1_reset_n}] + +set_property -dict {LOC W34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] +set_property -dict {LOC W33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] +set_property -dict {LOC Y33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] +set_property -dict {LOC Y32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] +set_property -dict {LOC Y30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] +set_property -dict {LOC W30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] +set_property -dict {LOC AB34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] +set_property -dict {LOC AA34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] +set_property -dict {LOC AD34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] +set_property -dict {LOC AC34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] +set_property -dict {LOC AC33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] +set_property -dict {LOC AC32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] +set_property -dict {LOC AF30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] +set_property -dict {LOC AE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] +set_property -dict {LOC AE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] +set_property -dict {LOC AD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] +set_property -dict {LOC AF33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] +set_property -dict {LOC AF32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] +set_property -dict {LOC AG32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] +set_property -dict {LOC AG31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] +set_property -dict {LOC AG34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] +set_property -dict {LOC AF34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] +set_property -dict {LOC AJ33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] +set_property -dict {LOC AH33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] +set_property -dict {LOC AK31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] +set_property -dict {LOC AJ31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] +set_property -dict {LOC AG30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] +set_property -dict {LOC AG29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] +set_property -dict {LOC AJ30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] +set_property -dict {LOC AJ29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] +set_property -dict {LOC AK28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] +set_property -dict {LOC AJ28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] +set_property -dict {LOC AL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] +set_property -dict {LOC AL29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] +set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] +set_property -dict {LOC AM31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] +set_property -dict {LOC AP29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] +set_property -dict {LOC AN29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] +set_property -dict {LOC AR30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] +set_property -dict {LOC AP30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] +set_property -dict {LOC AT30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] +set_property -dict {LOC AT29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] +set_property -dict {LOC AU31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] +set_property -dict {LOC AU30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] +set_property -dict {LOC AV32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] +set_property -dict {LOC AU32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] +set_property -dict {LOC AW31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] +set_property -dict {LOC AV31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] +set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] +set_property -dict {LOC AY31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] +set_property -dict {LOC BA30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] +set_property -dict {LOC AY30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] +set_property -dict {LOC BB29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] +set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] +set_property -dict {LOC BB31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] +set_property -dict {LOC BB30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] +set_property -dict {LOC BD29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] +set_property -dict {LOC BC29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] +set_property -dict {LOC BE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] +set_property -dict {LOC BD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] +set_property -dict {LOC BF30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] +set_property -dict {LOC BE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] +set_property -dict {LOC BE32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] +set_property -dict {LOC BE31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] +set_property -dict {LOC BC38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}] +set_property -dict {LOC BB38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}] +set_property -dict {LOC BD39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}] +set_property -dict {LOC BC39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}] +set_property -dict {LOC BF37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}] +set_property -dict {LOC BE37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}] +set_property -dict {LOC BF38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}] +set_property -dict {LOC BE38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}] +set_property -dict {LOC W31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] +set_property -dict {LOC Y31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] +set_property -dict {LOC AA32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] +set_property -dict {LOC AA33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] +set_property -dict {LOC AC31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] +set_property -dict {LOC AD31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] +set_property -dict {LOC AE31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] +set_property -dict {LOC AE32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] +set_property -dict {LOC AH31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] +set_property -dict {LOC AH32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] +set_property -dict {LOC AH34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] +set_property -dict {LOC AJ34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] +set_property -dict {LOC AH28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] +set_property -dict {LOC AH29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] +set_property -dict {LOC AJ27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] +set_property -dict {LOC AK27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] +set_property -dict {LOC AM29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}] +set_property -dict {LOC AM30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}] +set_property -dict {LOC AP31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}] +set_property -dict {LOC AR31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}] +set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[10]}] +set_property -dict {LOC AV29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[10]}] +set_property -dict {LOC AW29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[11]}] +set_property -dict {LOC AW30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[11]}] +set_property -dict {LOC BA32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[12]}] +set_property -dict {LOC BB32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[12]}] +set_property -dict {LOC BC31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[13]}] +set_property -dict {LOC BC32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[13]}] +set_property -dict {LOC BD30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[14]}] +set_property -dict {LOC BD31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[14]}] +set_property -dict {LOC BF32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[15]}] +set_property -dict {LOC BF33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[15]}] +set_property -dict {LOC BD40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[16]}] +set_property -dict {LOC BE40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[16]}] +set_property -dict {LOC BF39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[17]}] +set_property -dict {LOC BF40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[17]}] + +# DDR4 C2 +set_property -dict {LOC A37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[0]}] +set_property -dict {LOC A38 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[1]}] +set_property -dict {LOC B35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[2]}] +set_property -dict {LOC A35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[3]}] +set_property -dict {LOC E35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[4]}] +set_property -dict {LOC D35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[5]}] +set_property -dict {LOC E37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[6]}] +set_property -dict {LOC B34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[7]}] +set_property -dict {LOC A34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[8]}] +set_property -dict {LOC D34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[9]}] +set_property -dict {LOC C34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[10]}] +set_property -dict {LOC D33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[11]}] +set_property -dict {LOC C33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[12]}] +set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[13]}] +set_property -dict {LOC B32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[14]}] +set_property -dict {LOC D31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[15]}] +set_property -dict {LOC C31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[16]}] +# set_property -dict {LOC B31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[17]}] +set_property -dict {LOC C36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[0]}] +set_property -dict {LOC C37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[1]}] +set_property -dict {LOC E36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[0]}] +set_property -dict {LOC D36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[1]}] +set_property -dict {LOC B36 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c2_ck_t[0]}] +set_property -dict {LOC B37 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c2_ck_c[0]}] +set_property -dict {LOC A40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[0]}] +# set_property -dict {LOC B39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke[1]}] +set_property -dict {LOC D39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[0]}] +# set_property -dict {LOC B40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[1]}] +# set_property -dict {LOC D40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[2]}] +# set_property -dict {LOC E39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n[3]}] +# set_property -dict {LOC A33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_c[0]}] +# set_property -dict {LOC K34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_c[1]}] +# set_property -dict {LOC E26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_c[2]}] +set_property -dict {LOC F38 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_act_n}] +set_property -dict {LOC A39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[0]}] +# set_property -dict {LOC C38 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt[1]}] +set_property -dict {LOC C39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_par}] +set_property -dict {LOC E40 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_c2_reset_n}] + +set_property -dict {LOC E33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[0]}] +set_property -dict {LOC F33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[1]}] +set_property -dict {LOC E32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[2]}] +set_property -dict {LOC F32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[3]}] +set_property -dict {LOC G32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[4]}] +set_property -dict {LOC H32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[5]}] +set_property -dict {LOC G31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[6]}] +set_property -dict {LOC H31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[7]}] +set_property -dict {LOC K33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[8]}] +set_property -dict {LOC L33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[9]}] +set_property -dict {LOC J31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[10]}] +set_property -dict {LOC K31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[11]}] +set_property -dict {LOC L30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[12]}] +set_property -dict {LOC M30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[13]}] +set_property -dict {LOC K32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[14]}] +set_property -dict {LOC L32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[15]}] +set_property -dict {LOC N33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[16]}] +set_property -dict {LOC N32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[17]}] +set_property -dict {LOC N31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[18]}] +set_property -dict {LOC P31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[19]}] +set_property -dict {LOC N34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[20]}] +set_property -dict {LOC P34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[21]}] +set_property -dict {LOC R32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[22]}] +set_property -dict {LOC R31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[23]}] +set_property -dict {LOC T30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[24]}] +set_property -dict {LOC U30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[25]}] +set_property -dict {LOC U31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[26]}] +set_property -dict {LOC V31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[27]}] +set_property -dict {LOC T32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[28]}] +set_property -dict {LOC U32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[29]}] +set_property -dict {LOC R33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[30]}] +set_property -dict {LOC T33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[31]}] +set_property -dict {LOC A30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[32]}] +set_property -dict {LOC B30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[33]}] +set_property -dict {LOC A29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[34]}] +set_property -dict {LOC B29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[35]}] +set_property -dict {LOC D30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[36]}] +set_property -dict {LOC E30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[37]}] +set_property -dict {LOC C29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[38]}] +set_property -dict {LOC D29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[39]}] +set_property -dict {LOC D28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[40]}] +set_property -dict {LOC E28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[41]}] +set_property -dict {LOC E27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[42]}] +set_property -dict {LOC F27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[43]}] +set_property -dict {LOC G29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[44]}] +set_property -dict {LOC H29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[45]}] +set_property -dict {LOC G27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[46]}] +set_property -dict {LOC G26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[47]}] +set_property -dict {LOC J29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[48]}] +set_property -dict {LOC J28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[49]}] +set_property -dict {LOC H28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[50]}] +set_property -dict {LOC H27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[51]}] +set_property -dict {LOC L27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[52]}] +set_property -dict {LOC M27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[53]}] +set_property -dict {LOC K28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[54]}] +set_property -dict {LOC L28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[55]}] +set_property -dict {LOC N26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[56]}] +set_property -dict {LOC P26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[57]}] +set_property -dict {LOC N28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[58]}] +set_property -dict {LOC P28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[59]}] +set_property -dict {LOC R26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[60]}] +set_property -dict {LOC T26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[61]}] +set_property -dict {LOC R27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[62]}] +set_property -dict {LOC T27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[63]}] +set_property -dict {LOC F35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[64]}] +set_property -dict {LOC F34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[65]}] +set_property -dict {LOC G34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[66]}] +set_property -dict {LOC H34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[67]}] +set_property -dict {LOC J36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[68]}] +set_property -dict {LOC J35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[69]}] +set_property -dict {LOC F37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[70]}] +set_property -dict {LOC G37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[71]}] +set_property -dict {LOC J33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[0]}] +set_property -dict {LOC H33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[0]}] +set_property -dict {LOC G30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[1]}] +set_property -dict {LOC F30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[1]}] +set_property -dict {LOC K30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[2]}] +set_property -dict {LOC J30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[2]}] +set_property -dict {LOC M31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[3]}] +set_property -dict {LOC M32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[3]}] +set_property -dict {LOC M34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[4]}] +set_property -dict {LOC L34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[4]}] +set_property -dict {LOC R30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[5]}] +set_property -dict {LOC P30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[5]}] +set_property -dict {LOC V32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[6]}] +set_property -dict {LOC V33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[6]}] +set_property -dict {LOC U34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[7]}] +set_property -dict {LOC T34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[7]}] +set_property -dict {LOC A27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[8]}] +set_property -dict {LOC A28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[8]}] +set_property -dict {LOC C27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[9]}] +set_property -dict {LOC B27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[9]}] +set_property -dict {LOC F28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[10]}] +set_property -dict {LOC F29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[10]}] +set_property -dict {LOC J26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[11]}] +set_property -dict {LOC H26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[11]}] +set_property -dict {LOC K26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[12]}] +set_property -dict {LOC K27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[12]}] +set_property -dict {LOC M29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[13]}] +set_property -dict {LOC L29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[13]}] +set_property -dict {LOC P29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[14]}] +set_property -dict {LOC N29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[14]}] +set_property -dict {LOC T28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[15]}] +set_property -dict {LOC R28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[15]}] +set_property -dict {LOC H36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[16]}] +set_property -dict {LOC G36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[16]}] +set_property -dict {LOC H37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[17]}] +set_property -dict {LOC H38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[17]}] + +# DDR4 C3 +set_property -dict {LOC F20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[0]}] +set_property -dict {LOC F19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[1]}] +set_property -dict {LOC E21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[2]}] +set_property -dict {LOC E20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[3]}] +set_property -dict {LOC F18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[4]}] +set_property -dict {LOC F17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[5]}] +set_property -dict {LOC G21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[6]}] +set_property -dict {LOC D19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[7]}] +set_property -dict {LOC C19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[8]}] +set_property -dict {LOC D21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[9]}] +set_property -dict {LOC D20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[10]}] +set_property -dict {LOC C21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[11]}] +set_property -dict {LOC B21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[12]}] +set_property -dict {LOC B19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[13]}] +set_property -dict {LOC A19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[14]}] +set_property -dict {LOC B20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[15]}] +set_property -dict {LOC A20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[16]}] +# set_property -dict {LOC A18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[17]}] +set_property -dict {LOC H19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[0]}] +set_property -dict {LOC H18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[1]}] +set_property -dict {LOC G20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[0]}] +set_property -dict {LOC G19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[1]}] +set_property -dict {LOC E18 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c3_ck_t[0]}] +set_property -dict {LOC E17 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_c3_ck_c[0]}] +set_property -dict {LOC K20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[0]}] +# set_property -dict {LOC J21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke[1]}] +set_property -dict {LOC L18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[0]}] +# set_property -dict {LOC L20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[1]}] +# set_property -dict {LOC K17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[2]}] +# set_property -dict {LOC L19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n[3]}] +# set_property -dict {LOC C18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_c[0]}] +# set_property -dict {LOC F25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_c[1]}] +# set_property -dict {LOC D14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_c[2]}] +set_property -dict {LOC K21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_act_n}] +set_property -dict {LOC H21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[0]}] +# set_property -dict {LOC J20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt[1]}] +set_property -dict {LOC J19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_par}] +set_property -dict {LOC L17 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_c3_reset_n}] + +set_property -dict {LOC A25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[0]}] +set_property -dict {LOC B25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[1]}] +set_property -dict {LOC A24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[2]}] +set_property -dict {LOC B24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[3]}] +set_property -dict {LOC B26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[4]}] +set_property -dict {LOC C26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[5]}] +set_property -dict {LOC C23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[6]}] +set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[7]}] +set_property -dict {LOC D25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[8]}] +set_property -dict {LOC E25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[9]}] +set_property -dict {LOC D23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[10]}] +set_property -dict {LOC D24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[11]}] +set_property -dict {LOC F22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[12]}] +set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[13]}] +set_property -dict {LOC F23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[14]}] +set_property -dict {LOC F24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[15]}] +set_property -dict {LOC H24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[16]}] +set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[17]}] +set_property -dict {LOC H23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[18]}] +set_property -dict {LOC J23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[19]}] +set_property -dict {LOC K23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[20]}] +set_property -dict {LOC L23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[21]}] +set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[22]}] +set_property -dict {LOC L22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[23]}] +set_property -dict {LOC P25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[24]}] +set_property -dict {LOC R25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[25]}] +set_property -dict {LOC M24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[26]}] +set_property -dict {LOC M25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[27]}] +set_property -dict {LOC N23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[28]}] +set_property -dict {LOC P23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[29]}] +set_property -dict {LOC M22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[30]}] +set_property -dict {LOC N22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[31]}] +set_property -dict {LOC A17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[32]}] +set_property -dict {LOC B17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[33]}] +set_property -dict {LOC B16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[34]}] +set_property -dict {LOC C16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[35]}] +set_property -dict {LOC A13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[36]}] +set_property -dict {LOC A14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[37]}] +set_property -dict {LOC B14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[38]}] +set_property -dict {LOC C14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[39]}] +set_property -dict {LOC D16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[40]}] +set_property -dict {LOC E16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[41]}] +set_property -dict {LOC D15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[42]}] +set_property -dict {LOC E15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[43]}] +set_property -dict {LOC E13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[44]}] +set_property -dict {LOC F13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[45]}] +set_property -dict {LOC F15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[46]}] +set_property -dict {LOC G15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[47]}] +set_property -dict {LOC J15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[48]}] +set_property -dict {LOC J16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[49]}] +set_property -dict {LOC H14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[50]}] +set_property -dict {LOC J14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[51]}] +set_property -dict {LOC H13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[52]}] +set_property -dict {LOC J13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[53]}] +set_property -dict {LOC K15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[54]}] +set_property -dict {LOC K16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[55]}] +set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[56]}] +set_property -dict {LOC N16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[57]}] +set_property -dict {LOC L14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[58]}] +set_property -dict {LOC M14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[59]}] +set_property -dict {LOC P15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[60]}] +set_property -dict {LOC R15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[61]}] +set_property -dict {LOC N14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[62]}] +set_property -dict {LOC P14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[63]}] +set_property -dict {LOC M21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[64]}] +set_property -dict {LOC N21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[65]}] +set_property -dict {LOC P20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[66]}] +set_property -dict {LOC R20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[67]}] +set_property -dict {LOC M19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[68]}] +set_property -dict {LOC M20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[69]}] +set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[70]}] +set_property -dict {LOC P18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[71]}] +set_property -dict {LOC A23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[0]}] +set_property -dict {LOC A22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[0]}] +set_property -dict {LOC C22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[1]}] +set_property -dict {LOC B22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[1]}] +set_property -dict {LOC E23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[2]}] +set_property -dict {LOC E22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[2]}] +set_property -dict {LOC G25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[3]}] +set_property -dict {LOC G24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[3]}] +set_property -dict {LOC K25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[4]}] +set_property -dict {LOC J25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[4]}] +set_property -dict {LOC L25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[5]}] +set_property -dict {LOC L24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[5]}] +set_property -dict {LOC P24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[6]}] +set_property -dict {LOC N24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[6]}] +set_property -dict {LOC R21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[7]}] +set_property -dict {LOC P21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[7]}] +set_property -dict {LOC B15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[8]}] +set_property -dict {LOC A15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[8]}] +set_property -dict {LOC D13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[9]}] +set_property -dict {LOC C13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[9]}] +set_property -dict {LOC G17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[10]}] +set_property -dict {LOC G16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[10]}] +set_property -dict {LOC G14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[11]}] +set_property -dict {LOC F14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[11]}] +set_property -dict {LOC H17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[12]}] +set_property -dict {LOC H16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[12]}] +set_property -dict {LOC L13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[13]}] +set_property -dict {LOC K13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[13]}] +set_property -dict {LOC R16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[14]}] +set_property -dict {LOC P16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[14]}] +set_property -dict {LOC P13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[15]}] +set_property -dict {LOC N13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[15]}] +set_property -dict {LOC P19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[16]}] +set_property -dict {LOC N19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[16]}] +set_property -dict {LOC N17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[17]}] +set_property -dict {LOC M17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[17]}] diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile index 0779d69a9..0e43bbeef 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile @@ -138,6 +138,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl b/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl index dd1520fae..88b8678b3 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga/config.tcl @@ -148,6 +148,12 @@ dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" dict set params RX_RAM_SIZE "131072" + +# RAM configuration +dict set params DDR_CH "4" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" # Application block configuration dict set params APP_ID "32'h00000000" @@ -200,6 +206,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile index 0779d69a9..0e43bbeef 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile @@ -138,6 +138,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl index fec4223cb..ebf31a7dd 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/config.tcl @@ -148,6 +148,12 @@ dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" dict set params RX_RAM_SIZE "32768" + +# RAM configuration +dict set params DDR_CH "4" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" # Application block configuration dict set params APP_ID "32'h00000000" @@ -200,6 +206,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/XUPP3R/fpga_25g/ip/ddr4_0.tcl b/fpga/mqnic/XUPP3R/fpga_25g/ip/ddr4_0.tcl new file mode 100644 index 000000000..4ddb8395c --- /dev/null +++ b/fpga/mqnic/XUPP3R/fpga_25g/ip/ddr4_0.tcl @@ -0,0 +1,17 @@ + +create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 + +set_property -dict [list \ + CONFIG.C0.DDR4_AxiSelection {true} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_AxiIDWidth {8} \ + CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ + CONFIG.C0.DDR4_TimePeriod {833} \ + CONFIG.C0.DDR4_InputClockPeriod {9996} \ + CONFIG.C0.DDR4_MemoryType {RDIMMs} \ + CONFIG.C0.DDR4_MemoryPart {MTA18ASF2G72PZ-2G3} \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_CasLatency {17} \ + CONFIG.C0.DDR4_CasWriteLatency {12} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} +] [get_ips ddr4_0] diff --git a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v index 8755bc9cf..b2727f5fd 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v @@ -112,6 +112,15 @@ module fpga # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // RAM configuration + parameter DDR_CH = 4, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 34, + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -181,6 +190,14 @@ module fpga # * Clock: 48MHz */ input wire clk_48mhz, + input wire clk_ddr_1_p, + input wire clk_ddr_1_n, + input wire clk_ddr_2_p, + input wire clk_ddr_2_n, + input wire clk_ddr_3_p, + input wire clk_ddr_3_n, + input wire clk_ddr_4_p, + input wire clk_ddr_4_n, /* * GPIO @@ -335,7 +352,70 @@ module fpga # input wire qsfp3_intl, output wire qsfp3_lpmode, inout wire qsfp3_i2c_scl, - inout wire qsfp3_i2c_sda + inout wire qsfp3_i2c_sda, + + /* + * DDR4 + */ + output wire [16:0] ddr4_c0_adr, + output wire [1:0] ddr4_c0_ba, + output wire [1:0] ddr4_c0_bg, + output wire [0:0] ddr4_c0_ck_t, + output wire [0:0] ddr4_c0_ck_c, + output wire [0:0] ddr4_c0_cke, + output wire [0:0] ddr4_c0_cs_n, + output wire ddr4_c0_act_n, + output wire [0:0] ddr4_c0_odt, + output wire ddr4_c0_par, + output wire ddr4_c0_reset_n, + inout wire [71:0] ddr4_c0_dq, + inout wire [17:0] ddr4_c0_dqs_t, + inout wire [17:0] ddr4_c0_dqs_c, + + output wire [16:0] ddr4_c1_adr, + output wire [1:0] ddr4_c1_ba, + output wire [1:0] ddr4_c1_bg, + output wire [0:0] ddr4_c1_ck_t, + output wire [0:0] ddr4_c1_ck_c, + output wire [0:0] ddr4_c1_cke, + output wire [0:0] ddr4_c1_cs_n, + output wire ddr4_c1_act_n, + output wire [0:0] ddr4_c1_odt, + output wire ddr4_c1_par, + output wire ddr4_c1_reset_n, + inout wire [71:0] ddr4_c1_dq, + inout wire [17:0] ddr4_c1_dqs_t, + inout wire [17:0] ddr4_c1_dqs_c, + + output wire [16:0] ddr4_c2_adr, + output wire [1:0] ddr4_c2_ba, + output wire [1:0] ddr4_c2_bg, + output wire [0:0] ddr4_c2_ck_t, + output wire [0:0] ddr4_c2_ck_c, + output wire [0:0] ddr4_c2_cke, + output wire [0:0] ddr4_c2_cs_n, + output wire ddr4_c2_act_n, + output wire [0:0] ddr4_c2_odt, + output wire ddr4_c2_par, + output wire ddr4_c2_reset_n, + inout wire [71:0] ddr4_c2_dq, + inout wire [17:0] ddr4_c2_dqs_t, + inout wire [17:0] ddr4_c2_dqs_c, + + output wire [16:0] ddr4_c3_adr, + output wire [1:0] ddr4_c3_ba, + output wire [1:0] ddr4_c3_bg, + output wire [0:0] ddr4_c3_ck_t, + output wire [0:0] ddr4_c3_ck_c, + output wire [0:0] ddr4_c3_cke, + output wire [0:0] ddr4_c3_cs_n, + output wire ddr4_c3_act_n, + output wire [0:0] ddr4_c3_odt, + output wire ddr4_c3_par, + output wire ddr4_c3_reset_n, + inout wire [71:0] ddr4_c3_dq, + inout wire [17:0] ddr4_c3_dqs_t, + inout wire [17:0] ddr4_c3_dqs_c ); // PTP configuration @@ -349,6 +429,9 @@ parameter IF_PTP_PERIOD_FNS = 16'h6666; // Interface configuration parameter TX_TAG_WIDTH = 16; +// RAM configuration +parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8); + // Ethernet interface configuration parameter XGMII_DATA_WIDTH = 64; parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8; @@ -1867,6 +1950,519 @@ assign ptp_clk = qsfp0_mgt_refclk_b0_bufg; assign ptp_rst = qsfp0_rst; assign ptp_sample_clk = clk_125mhz_int; +// DDR4 +wire [DDR_CH-1:0] ddr_clk; +wire [DDR_CH-1:0] ddr_rst; + +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr; +wire [DDR_CH*8-1:0] m_axi_ddr_awlen; +wire [DDR_CH*3-1:0] m_axi_ddr_awsize; +wire [DDR_CH*2-1:0] m_axi_ddr_awburst; +wire [DDR_CH-1:0] m_axi_ddr_awlock; +wire [DDR_CH*4-1:0] m_axi_ddr_awcache; +wire [DDR_CH*3-1:0] m_axi_ddr_awprot; +wire [DDR_CH*4-1:0] m_axi_ddr_awqos; +wire [DDR_CH-1:0] m_axi_ddr_awvalid; +wire [DDR_CH-1:0] m_axi_ddr_awready; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata; +wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb; +wire [DDR_CH-1:0] m_axi_ddr_wlast; +wire [DDR_CH-1:0] m_axi_ddr_wvalid; +wire [DDR_CH-1:0] m_axi_ddr_wready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid; +wire [DDR_CH*2-1:0] m_axi_ddr_bresp; +wire [DDR_CH-1:0] m_axi_ddr_bvalid; +wire [DDR_CH-1:0] m_axi_ddr_bready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr; +wire [DDR_CH*8-1:0] m_axi_ddr_arlen; +wire [DDR_CH*3-1:0] m_axi_ddr_arsize; +wire [DDR_CH*2-1:0] m_axi_ddr_arburst; +wire [DDR_CH-1:0] m_axi_ddr_arlock; +wire [DDR_CH*4-1:0] m_axi_ddr_arcache; +wire [DDR_CH*3-1:0] m_axi_ddr_arprot; +wire [DDR_CH*4-1:0] m_axi_ddr_arqos; +wire [DDR_CH-1:0] m_axi_ddr_arvalid; +wire [DDR_CH-1:0] m_axi_ddr_arready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata; +wire [DDR_CH*2-1:0] m_axi_ddr_rresp; +wire [DDR_CH-1:0] m_axi_ddr_rlast; +wire [DDR_CH-1:0] m_axi_ddr_rvalid; +wire [DDR_CH-1:0] m_axi_ddr_rready; + +wire [DDR_CH-1:0] ddr_status; + +generate + +if (DDR_ENABLE && DDR_CH > 0) begin + +ddr4_0 ddr4_c0_inst ( + .c0_sys_clk_p(clk_ddr_1_p), + .c0_sys_clk_n(clk_ddr_1_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[0 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c0_adr), + .c0_ddr4_ba(ddr4_c0_ba), + .c0_ddr4_cke(ddr4_c0_cke), + .c0_ddr4_cs_n(ddr4_c0_cs_n), + .c0_ddr4_dq(ddr4_c0_dq), + .c0_ddr4_dqs_t(ddr4_c0_dqs_t), + .c0_ddr4_dqs_c(ddr4_c0_dqs_c), + .c0_ddr4_odt(ddr4_c0_odt), + .c0_ddr4_parity(ddr4_c0_par), + .c0_ddr4_bg(ddr4_c0_bg), + .c0_ddr4_reset_n(ddr4_c0_reset_n), + .c0_ddr4_act_n(ddr4_c0_act_n), + .c0_ddr4_ck_t(ddr4_c0_ck_t), + .c0_ddr4_ck_c(ddr4_c0_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[0 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[0 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c0_adr = {17{1'bz}}; +assign ddr4_c0_ba = {2{1'bz}}; +assign ddr4_c0_bg = {2{1'bz}}; +assign ddr4_c0_cke = 1'bz; +assign ddr4_c0_cs_n = 1'bz; +assign ddr4_c0_act_n = 1'bz; +assign ddr4_c0_odt = 1'bz; +assign ddr4_c0_par = 1'bz; +assign ddr4_c0_reset_n = 1'b0; +assign ddr4_c0_dq = {72{1'bz}}; +assign ddr4_c0_dqs_t = {18{1'bz}}; +assign ddr4_c0_dqs_c = {18{1'bz}}; + +OBUFTDS ddr4_c0_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c0_ck_t), + .OB(ddr4_c0_ck_c) +); + +assign ddr_clk = 0; +assign ddr_rst = 0; + +assign m_axi_ddr_awready = 0; +assign m_axi_ddr_wready = 0; +assign m_axi_ddr_bid = 0; +assign m_axi_ddr_bresp = 0; +assign m_axi_ddr_bvalid = 0; +assign m_axi_ddr_arready = 0; +assign m_axi_ddr_rid = 0; +assign m_axi_ddr_rdata = 0; +assign m_axi_ddr_rresp = 0; +assign m_axi_ddr_rlast = 0; +assign m_axi_ddr_rvalid = 0; + +assign ddr_status = 0; + +end + +if (DDR_ENABLE && DDR_CH > 1) begin + +ddr4_0 ddr4_c1_inst ( + .c0_sys_clk_p(clk_ddr_2_p), + .c0_sys_clk_n(clk_ddr_2_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[1 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c1_adr), + .c0_ddr4_ba(ddr4_c1_ba), + .c0_ddr4_cke(ddr4_c1_cke), + .c0_ddr4_cs_n(ddr4_c1_cs_n), + .c0_ddr4_dq(ddr4_c1_dq), + .c0_ddr4_dqs_t(ddr4_c1_dqs_t), + .c0_ddr4_dqs_c(ddr4_c1_dqs_c), + .c0_ddr4_odt(ddr4_c1_odt), + .c0_ddr4_parity(ddr4_c1_par), + .c0_ddr4_bg(ddr4_c1_bg), + .c0_ddr4_reset_n(ddr4_c1_reset_n), + .c0_ddr4_act_n(ddr4_c1_act_n), + .c0_ddr4_ck_t(ddr4_c1_ck_t), + .c0_ddr4_ck_c(ddr4_c1_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[1 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[1 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[1 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[1*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[1*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[1*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[1 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[1*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[1*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[1*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[1 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[1 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[1*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[1 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[1 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[1 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[1 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[1*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[1 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[1*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[1*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[1*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[1 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[1*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[1*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[1*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[1 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[1 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[1 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[1 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[1 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[1*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c1_adr = {17{1'bz}}; +assign ddr4_c1_ba = {2{1'bz}}; +assign ddr4_c1_bg = {2{1'bz}}; +assign ddr4_c1_cke = 1'bz; +assign ddr4_c1_cs_n = 1'bz; +assign ddr4_c1_act_n = 1'bz; +assign ddr4_c1_odt = 1'bz; +assign ddr4_c1_par = 1'bz; +assign ddr4_c1_reset_n = 1'b0; +assign ddr4_c1_dq = {72{1'bz}}; +assign ddr4_c1_dqs_t = {18{1'bz}}; +assign ddr4_c1_dqs_c = {18{1'bz}}; + +OBUFTDS ddr4_c1_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c1_ck_t), + .OB(ddr4_c1_ck_c) +); + +end + +if (DDR_ENABLE && DDR_CH > 2) begin + +ddr4_0 ddr4_c2_inst ( + .c0_sys_clk_p(clk_ddr_3_p), + .c0_sys_clk_n(clk_ddr_3_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[2 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c2_adr), + .c0_ddr4_ba(ddr4_c2_ba), + .c0_ddr4_cke(ddr4_c2_cke), + .c0_ddr4_cs_n(ddr4_c2_cs_n), + .c0_ddr4_dq(ddr4_c2_dq), + .c0_ddr4_dqs_t(ddr4_c2_dqs_t), + .c0_ddr4_dqs_c(ddr4_c2_dqs_c), + .c0_ddr4_odt(ddr4_c2_odt), + .c0_ddr4_parity(ddr4_c2_par), + .c0_ddr4_bg(ddr4_c2_bg), + .c0_ddr4_reset_n(ddr4_c2_reset_n), + .c0_ddr4_act_n(ddr4_c2_act_n), + .c0_ddr4_ck_t(ddr4_c2_ck_t), + .c0_ddr4_ck_c(ddr4_c2_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[2 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[2 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[2 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[2*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[2*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[2*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[2 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[2*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[2*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[2*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[2 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[2 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[2*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[2 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[2 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[2 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[2 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[2*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[2 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[2*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[2*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[2*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[2 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[2*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[2*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[2*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[2 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[2 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[2 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[2 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[2 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[2*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c2_adr = {17{1'bz}}; +assign ddr4_c2_ba = {2{1'bz}}; +assign ddr4_c2_bg = {2{1'bz}}; +assign ddr4_c2_cke = 1'bz; +assign ddr4_c2_cs_n = 1'bz; +assign ddr4_c2_act_n = 1'bz; +assign ddr4_c2_odt = 1'bz; +assign ddr4_c2_par = 1'bz; +assign ddr4_c2_reset_n = 1'b0; +assign ddr4_c2_dq = {72{1'bz}}; +assign ddr4_c2_dqs_t = {18{1'bz}}; +assign ddr4_c2_dqs_c = {18{1'bz}}; + +OBUFTDS ddr4_c2_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c2_ck_t), + .OB(ddr4_c2_ck_c) +); + +end + +if (DDR_ENABLE && DDR_CH > 3) begin + +ddr4_0 ddr4_c3_inst ( + .c0_sys_clk_p(clk_ddr_4_p), + .c0_sys_clk_n(clk_ddr_4_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[3 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c3_adr), + .c0_ddr4_ba(ddr4_c3_ba), + .c0_ddr4_cke(ddr4_c3_cke), + .c0_ddr4_cs_n(ddr4_c3_cs_n), + .c0_ddr4_dq(ddr4_c3_dq), + .c0_ddr4_dqs_t(ddr4_c3_dqs_t), + .c0_ddr4_dqs_c(ddr4_c3_dqs_c), + .c0_ddr4_odt(ddr4_c3_odt), + .c0_ddr4_parity(ddr4_c3_par), + .c0_ddr4_bg(ddr4_c3_bg), + .c0_ddr4_reset_n(ddr4_c3_reset_n), + .c0_ddr4_act_n(ddr4_c3_act_n), + .c0_ddr4_ck_t(ddr4_c3_ck_t), + .c0_ddr4_ck_c(ddr4_c3_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[3 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[3 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[3 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[3*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[3*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[3*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[3 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[3*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[3*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[3*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[3 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[3 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[3*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[3 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[3 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[3 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[3 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[3*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[3 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[3*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[3*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[3*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[3 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[3*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[3*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[3*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[3 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[3 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[3 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[3 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[3 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[3*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c3_adr = {17{1'bz}}; +assign ddr4_c3_ba = {2{1'bz}}; +assign ddr4_c3_bg = {2{1'bz}}; +assign ddr4_c3_cke = 1'bz; +assign ddr4_c3_cs_n = 1'bz; +assign ddr4_c3_act_n = 1'bz; +assign ddr4_c3_odt = 1'bz; +assign ddr4_c3_par = 1'bz; +assign ddr4_c3_reset_n = 1'b0; +assign ddr4_c3_dq = {72{1'bz}}; +assign ddr4_c3_dqs_t = {18{1'bz}}; +assign ddr4_c3_dqs_c = {18{1'bz}}; + +OBUFTDS ddr4_c3_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c3_ck_t), + .OB(ddr4_c3_ck_c) +); + +end + +endgenerate + fpga_core #( // FW and board IDs .FPGA_ID(FPGA_ID), @@ -1943,6 +2539,16 @@ fpga_core #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -2399,6 +3005,52 @@ core_inst ( .qsfp3_i2c_sda_o(qsfp3_i2c_sda_o), .qsfp3_i2c_sda_t(qsfp3_i2c_sda_t), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + /* * QSPI flash */ diff --git a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v index 5c5de70f3..af8648c17 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v @@ -122,6 +122,16 @@ module fpga_core # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // RAM configuration + parameter DDR_CH = 4, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 34, + parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -580,6 +590,52 @@ module fpga_core # output wire qsfp3_i2c_sda_o, output wire qsfp3_i2c_sda_t, + /* + * DDR + */ + input wire [DDR_CH-1:0] ddr_clk, + input wire [DDR_CH-1:0] ddr_rst, + + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, + output wire [DDR_CH-1:0] m_axi_ddr_awlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, + output wire [DDR_CH-1:0] m_axi_ddr_awvalid, + input wire [DDR_CH-1:0] m_axi_ddr_awready, + output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, + output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, + output wire [DDR_CH-1:0] m_axi_ddr_wlast, + output wire [DDR_CH-1:0] m_axi_ddr_wvalid, + input wire [DDR_CH-1:0] m_axi_ddr_wready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, + input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, + input wire [DDR_CH-1:0] m_axi_ddr_bvalid, + output wire [DDR_CH-1:0] m_axi_ddr_bready, + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, + output wire [DDR_CH-1:0] m_axi_ddr_arlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, + output wire [DDR_CH-1:0] m_axi_ddr_arvalid, + input wire [DDR_CH-1:0] m_axi_ddr_arready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, + input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, + input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, + input wire [DDR_CH-1:0] m_axi_ddr_rlast, + input wire [DDR_CH-1:0] m_axi_ddr_rvalid, + output wire [DDR_CH-1:0] m_axi_ddr_rready, + + input wire [DDR_CH-1:0] ddr_status, + /* * QSPI flash */ @@ -1511,6 +1567,25 @@ mqnic_core_pcie_us #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .DDR_GROUP_SIZE(1), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_AWUSER_ENABLE(0), + .AXI_DDR_WUSER_ENABLE(0), + .AXI_DDR_BUSER_ENABLE(0), + .AXI_DDR_ARUSER_ENABLE(0), + .AXI_DDR_RUSER_ENABLE(0), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + .AXI_DDR_FIXED_BURST(0), + .AXI_DDR_WRAP_BURST(1), + .HBM_ENABLE(0), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1788,6 +1863,108 @@ core_inst ( .eth_rx_status(eth_rx_status), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awuser(), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wuser(), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_buser(0), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_aruser(), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_ruser(0), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + + /* + * HBM + */ + .hbm_clk(0), + .hbm_rst(0), + + .m_axi_hbm_awid(), + .m_axi_hbm_awaddr(), + .m_axi_hbm_awlen(), + .m_axi_hbm_awsize(), + .m_axi_hbm_awburst(), + .m_axi_hbm_awlock(), + .m_axi_hbm_awcache(), + .m_axi_hbm_awprot(), + .m_axi_hbm_awqos(), + .m_axi_hbm_awuser(), + .m_axi_hbm_awvalid(), + .m_axi_hbm_awready(0), + .m_axi_hbm_wdata(), + .m_axi_hbm_wstrb(), + .m_axi_hbm_wlast(), + .m_axi_hbm_wuser(), + .m_axi_hbm_wvalid(), + .m_axi_hbm_wready(0), + .m_axi_hbm_bid(0), + .m_axi_hbm_bresp(0), + .m_axi_hbm_buser(0), + .m_axi_hbm_bvalid(0), + .m_axi_hbm_bready(), + .m_axi_hbm_arid(), + .m_axi_hbm_araddr(), + .m_axi_hbm_arlen(), + .m_axi_hbm_arsize(), + .m_axi_hbm_arburst(), + .m_axi_hbm_arlock(), + .m_axi_hbm_arcache(), + .m_axi_hbm_arprot(), + .m_axi_hbm_arqos(), + .m_axi_hbm_aruser(), + .m_axi_hbm_arvalid(), + .m_axi_hbm_arready(0), + .m_axi_hbm_rid(0), + .m_axi_hbm_rdata(0), + .m_axi_hbm_rresp(0), + .m_axi_hbm_rlast(0), + .m_axi_hbm_ruser(0), + .m_axi_hbm_rvalid(0), + .m_axi_hbm_rready(), + + .hbm_status(0), + /* * Statistics input */ diff --git a/fpga/mqnic/ZCU102/fpga/README.md b/fpga/mqnic/ZCU102/fpga/README.md index 32e371f91..c932a13c6 100644 --- a/fpga/mqnic/ZCU102/fpga/README.md +++ b/fpga/mqnic/ZCU102/fpga/README.md @@ -5,8 +5,9 @@ This design targets the Xilinx ZCU102 FPGA board. The host system of the NIC is the Zynq US+ MPSoC. -FPGA: xczu9eg-ffvb1156-2-e -PHY: 10G BASE-R PHY IP core and internal GTH transceiver +* FPGA: xczu9eg-ffvb1156-2-e +* PHY: 10G BASE-R PHY IP core and internal GTH transceiver +* RAM: 512 MB DDR4 2400 (256M x16) ## How to build diff --git a/fpga/mqnic/ZCU102/fpga/fpga.xdc b/fpga/mqnic/ZCU102/fpga/fpga.xdc index 9c9abf58c..fcb1839f0 100644 --- a/fpga/mqnic/ZCU102/fpga/fpga.xdc +++ b/fpga/mqnic/ZCU102/fpga/fpga.xdc @@ -10,6 +10,11 @@ set_property -dict {LOC G21 IOSTANDARD LVDS_25} [get_ports clk_125mhz_p] set_property -dict {LOC F21 IOSTANDARD LVDS_25} [get_ports clk_125mhz_n] create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p] +# User Si570 (default 300 MHz) +set_property -dict {LOC AL8 IOSTANDARD DIFF_SSTL12} [get_ports clk_user_si570_p] +set_property -dict {LOC AL7 IOSTANDARD DIFF_SSTL12} [get_ports clk_user_si570_n] +#create_clock -period 3.333 -name clk_user_si570 [get_ports clk_user_si570_p] + # LEDs set_property -dict {LOC AG14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[0]}] set_property -dict {LOC AF13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 8} [get_ports {led[1]}] @@ -107,3 +112,57 @@ create_clock -period 6.400 -name sfp_mgt_refclk_0 [get_ports sfp_mgt_refclk_0_p] set_false_path -to [get_ports {sfp0_tx_disable_b sfp1_tx_disable_b sfp2_tx_disable_b sfp3_tx_disable_b}] set_output_delay 0 [get_ports {sfp0_tx_disable_b sfp1_tx_disable_b sfp2_tx_disable_b sfp3_tx_disable_b}] + +# DDR4 +# 1x MT40A256M16GE-075E +set_property -dict {LOC AM8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[0]}] +set_property -dict {LOC AM9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[1]}] +set_property -dict {LOC AP8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[2]}] +set_property -dict {LOC AN8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[3]}] +set_property -dict {LOC AK10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[4]}] +set_property -dict {LOC AJ10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[5]}] +set_property -dict {LOC AP9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[6]}] +set_property -dict {LOC AN9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[7]}] +set_property -dict {LOC AP10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[8]}] +set_property -dict {LOC AP11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[9]}] +set_property -dict {LOC AM10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[10]}] +set_property -dict {LOC AL10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[11]}] +set_property -dict {LOC AM11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[12]}] +set_property -dict {LOC AL11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[13]}] +set_property -dict {LOC AJ7 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[14]}] +set_property -dict {LOC AL5 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[15]}] +set_property -dict {LOC AJ9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[16]}] +set_property -dict {LOC AK12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_ba[0]}] +set_property -dict {LOC AJ12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_ba[1]}] +set_property -dict {LOC AK7 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_bg[0]}] +set_property -dict {LOC AN7 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_ck_t}] +set_property -dict {LOC AP7 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_ck_c}] +set_property -dict {LOC AM3 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_cke}] +set_property -dict {LOC AP2 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_cs_n}] +set_property -dict {LOC AK8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_act_n}] +set_property -dict {LOC AK9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_odt}] +set_property -dict {LOC AP1 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_par}] +set_property -dict {LOC AH9 IOSTANDARD LVCMOS12 } [get_ports {ddr4_reset_n}] + +set_property -dict {LOC AK4 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[0]}] ;# U2.G2 DQL0 +set_property -dict {LOC AK5 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[1]}] ;# U2.F7 DQL1 +set_property -dict {LOC AN4 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[2]}] ;# U2.H3 DQL2 +set_property -dict {LOC AM4 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[3]}] ;# U2.H7 DQL3 +set_property -dict {LOC AP4 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[4]}] ;# U2.H2 DQL4 +set_property -dict {LOC AP5 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[5]}] ;# U2.H8 DQL5 +set_property -dict {LOC AM5 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[6]}] ;# U2.J3 DQL6 +set_property -dict {LOC AM6 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[7]}] ;# U2.J7 DQL7 +set_property -dict {LOC AK2 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[8]}] ;# U2.A3 DQU0 +set_property -dict {LOC AK3 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[9]}] ;# U2.B8 DQU1 +set_property -dict {LOC AL1 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[10]}] ;# U2.C3 DQU2 +set_property -dict {LOC AK1 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[11]}] ;# U2.C7 DQU3 +set_property -dict {LOC AN1 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[12]}] ;# U2.C2 DQU4 +set_property -dict {LOC AM1 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[13]}] ;# U2.C8 DQU5 +set_property -dict {LOC AP3 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[14]}] ;# U2.D3 DQU6 +set_property -dict {LOC AN3 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[15]}] ;# U2.D7 DQU7 +set_property -dict {LOC AN6 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[0]}] ;# U2.G3 DQSL_T +set_property -dict {LOC AP6 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[0]}] ;# U2.F3 DQSL_C +set_property -dict {LOC AL3 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[1]}] ;# U2.B7 DQSU_T +set_property -dict {LOC AL2 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[1]}] ;# U2.A7 DQSU_C +set_property -dict {LOC AL6 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[0]}] ;# U2.E7 DML_B/DBIL_B +set_property -dict {LOC AN2 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[1]}] ;# U2.E2 DMU_B/DBIU_B diff --git a/fpga/mqnic/ZCU102/fpga/fpga/Makefile b/fpga/mqnic/ZCU102/fpga/fpga/Makefile index b04483282..4657ea844 100644 --- a/fpga/mqnic/ZCU102/fpga/fpga/Makefile +++ b/fpga/mqnic/ZCU102/fpga/fpga/Makefile @@ -119,6 +119,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/zynq_ps.tcl IP_TCL_FILES += ip/eth_xcvr_gth.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/ZCU102/fpga/fpga/config.tcl b/fpga/mqnic/ZCU102/fpga/fpga/config.tcl index 9998d9ee9..e3d79240d 100644 --- a/fpga/mqnic/ZCU102/fpga/fpga/config.tcl +++ b/fpga/mqnic/ZCU102/fpga/fpga/config.tcl @@ -132,6 +132,12 @@ dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" dict set params RX_RAM_SIZE "32768" +# RAM configuration +dict set params DDR_CH "1" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" + # Application block configuration dict set params APP_ID "32'h00000000" dict set params APP_ENABLE "0" @@ -193,6 +199,19 @@ dict set params STAT_AXI_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # apply parameters to top-level set param_list {} dict for {name value} $params { diff --git a/fpga/mqnic/ZCU102/fpga/ip/ddr4_0.tcl b/fpga/mqnic/ZCU102/fpga/ip/ddr4_0.tcl new file mode 100644 index 000000000..726b7d3a6 --- /dev/null +++ b/fpga/mqnic/ZCU102/fpga/ip/ddr4_0.tcl @@ -0,0 +1,19 @@ + +create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 + +set_property -dict [list \ + CONFIG.C0.DDR4_AxiSelection {true} \ + CONFIG.C0.DDR4_AxiDataWidth {128} \ + CONFIG.C0.DDR4_AxiIDWidth {8} \ + CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ + CONFIG.C0.DDR4_TimePeriod {833} \ + CONFIG.C0.DDR4_InputClockPeriod {3332} \ + CONFIG.C0.DDR4_MemoryType {Components} \ + CONFIG.C0.DDR4_MemoryPart {MT40A256M16GE-075E} \ + CONFIG.C0.DDR4_DataWidth {16} \ + CONFIG.C0.DDR4_DataMask {DM_NO_DBI} \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_CasLatency {17} \ + CONFIG.C0.DDR4_CasWriteLatency {12} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} +] [get_ips ddr4_0] diff --git a/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi index 31cb34c93..d900c3238 100644 --- a/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi +++ b/fpga/mqnic/ZCU102/fpga/ps/petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi @@ -72,6 +72,11 @@ }; }; +/* USER SI570 (U42) */ +&si570_1 { + clock-frequency = <300000000>; +}; + /* USER MGT SI570 (U56) */ &si570_2 { clock-frequency = <156250000>; diff --git a/fpga/mqnic/ZCU102/fpga/rtl/fpga.v b/fpga/mqnic/ZCU102/fpga/rtl/fpga.v index 430b0f963..15d0c9fef 100644 --- a/fpga/mqnic/ZCU102/fpga/rtl/fpga.v +++ b/fpga/mqnic/ZCU102/fpga/rtl/fpga.v @@ -112,6 +112,15 @@ module fpga # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // RAM configuration + parameter DDR_CH = 1, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 128, + parameter AXI_DDR_ADDR_WIDTH = 29, + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -171,6 +180,8 @@ module fpga # */ input wire clk_125mhz_p, input wire clk_125mhz_n, + input wire clk_user_si570_p, + input wire clk_user_si570_n, /* * GPIO @@ -207,7 +218,26 @@ module fpga # output wire sfp0_tx_disable_b, output wire sfp1_tx_disable_b, output wire sfp2_tx_disable_b, - output wire sfp3_tx_disable_b + output wire sfp3_tx_disable_b, + + /* + * DDR4 + */ + output wire [16:0] ddr4_adr, + output wire [1:0] ddr4_ba, + output wire [0:0] ddr4_bg, + output wire [0:0] ddr4_ck_t, + output wire [0:0] ddr4_ck_c, + output wire [0:0] ddr4_cke, + output wire [0:0] ddr4_cs_n, + output wire ddr4_act_n, + output wire [0:0] ddr4_odt, + output wire ddr4_par, + output wire ddr4_reset_n, + inout wire [15:0] ddr4_dq, + inout wire [1:0] ddr4_dqs_t, + inout wire [1:0] ddr4_dqs_c, + inout wire [1:0] ddr4_dm_dbi_n ); // PTP configuration @@ -221,6 +251,9 @@ parameter IF_PTP_PERIOD_FNS = 16'h6666; // Interface configuration parameter TX_TAG_WIDTH = 16; +// RAM configuration +parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8); + // Ethernet interface configuration parameter XGMII_DATA_WIDTH = 64; parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8; @@ -772,6 +805,165 @@ assign ptp_clk = sfp_mgt_refclk_0_bufg; assign ptp_rst = sfp_rst; assign ptp_sample_clk = clk_125mhz_int; +// DDR4 +wire [DDR_CH-1:0] ddr_clk; +wire [DDR_CH-1:0] ddr_rst; + +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr; +wire [DDR_CH*8-1:0] m_axi_ddr_awlen; +wire [DDR_CH*3-1:0] m_axi_ddr_awsize; +wire [DDR_CH*2-1:0] m_axi_ddr_awburst; +wire [DDR_CH-1:0] m_axi_ddr_awlock; +wire [DDR_CH*4-1:0] m_axi_ddr_awcache; +wire [DDR_CH*3-1:0] m_axi_ddr_awprot; +wire [DDR_CH*4-1:0] m_axi_ddr_awqos; +wire [DDR_CH-1:0] m_axi_ddr_awvalid; +wire [DDR_CH-1:0] m_axi_ddr_awready; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata; +wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb; +wire [DDR_CH-1:0] m_axi_ddr_wlast; +wire [DDR_CH-1:0] m_axi_ddr_wvalid; +wire [DDR_CH-1:0] m_axi_ddr_wready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid; +wire [DDR_CH*2-1:0] m_axi_ddr_bresp; +wire [DDR_CH-1:0] m_axi_ddr_bvalid; +wire [DDR_CH-1:0] m_axi_ddr_bready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr; +wire [DDR_CH*8-1:0] m_axi_ddr_arlen; +wire [DDR_CH*3-1:0] m_axi_ddr_arsize; +wire [DDR_CH*2-1:0] m_axi_ddr_arburst; +wire [DDR_CH-1:0] m_axi_ddr_arlock; +wire [DDR_CH*4-1:0] m_axi_ddr_arcache; +wire [DDR_CH*3-1:0] m_axi_ddr_arprot; +wire [DDR_CH*4-1:0] m_axi_ddr_arqos; +wire [DDR_CH-1:0] m_axi_ddr_arvalid; +wire [DDR_CH-1:0] m_axi_ddr_arready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata; +wire [DDR_CH*2-1:0] m_axi_ddr_rresp; +wire [DDR_CH-1:0] m_axi_ddr_rlast; +wire [DDR_CH-1:0] m_axi_ddr_rvalid; +wire [DDR_CH-1:0] m_axi_ddr_rready; + +wire [DDR_CH-1:0] ddr_status; + +generate + +if (DDR_ENABLE && DDR_CH > 0) begin + +ddr4_0 ddr4_inst ( + .c0_sys_clk_p(clk_user_si570_p), + .c0_sys_clk_n(clk_user_si570_n), + .sys_rst(zynq_pl_reset), + + .c0_init_calib_complete(ddr_status[0 +: 1]), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_adr), + .c0_ddr4_ba(ddr4_ba), + .c0_ddr4_cke(ddr4_cke), + .c0_ddr4_cs_n(ddr4_cs_n), + .c0_ddr4_dq(ddr4_dq), + .c0_ddr4_dqs_t(ddr4_dqs_t), + .c0_ddr4_dqs_c(ddr4_dqs_c), + .c0_ddr4_dm_dbi_n(ddr4_dm_dbi_n), + .c0_ddr4_odt(ddr4_odt), + .c0_ddr4_bg(ddr4_bg), + .c0_ddr4_reset_n(ddr4_reset_n), + .c0_ddr4_act_n(ddr4_act_n), + .c0_ddr4_ck_t(ddr4_ck_t), + .c0_ddr4_ck_c(ddr4_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[0 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[0 +: 1]), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_adr = {17{1'bz}}; +assign ddr4_ba = {2{1'bz}}; +assign ddr4_bg = {1{1'bz}}; +assign ddr4_cke = 1'bz; +assign ddr4_cs_n = 1'bz; +assign ddr4_act_n = 1'bz; +assign ddr4_odt = 1'bz; +assign ddr4_par = 1'bz; +assign ddr4_reset_n = 1'b0; +assign ddr4_dq = {16{1'bz}}; +assign ddr4_dqs_t = {2{1'bz}}; +assign ddr4_dqs_c = {2{1'bz}}; + +OBUFTDS ddr4_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_ck_t), + .OB(ddr4_ck_c) +); + +assign ddr_clk = 0; +assign ddr_rst = 0; + +assign m_axi_ddr_awready = 0; +assign m_axi_ddr_wready = 0; +assign m_axi_ddr_bid = 0; +assign m_axi_ddr_bresp = 0; +assign m_axi_ddr_bvalid = 0; +assign m_axi_ddr_arready = 0; +assign m_axi_ddr_rid = 0; +assign m_axi_ddr_rdata = 0; +assign m_axi_ddr_rresp = 0; +assign m_axi_ddr_rlast = 0; +assign m_axi_ddr_rvalid = 0; + +assign ddr_status = 0; + +end + +endgenerate + fpga_core #( // FW and board IDs .FPGA_ID(FPGA_ID), @@ -848,6 +1040,16 @@ fpga_core #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1087,7 +1289,53 @@ core_inst ( .sfp_drp_en(sfp_drp_en), .sfp_drp_we(sfp_drp_we), .sfp_drp_do(sfp_drp_do), - .sfp_drp_rdy(sfp_drp_rdy) + .sfp_drp_rdy(sfp_drp_rdy), + + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status) ); endmodule diff --git a/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v b/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v index 5910c3b85..1d08e6747 100644 --- a/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v +++ b/fpga/mqnic/ZCU102/fpga/rtl/fpga_core.v @@ -122,6 +122,16 @@ module fpga_core # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // RAM configuration + parameter DDR_CH = 1, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 128, + parameter AXI_DDR_ADDR_WIDTH = 29, + parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -363,7 +373,53 @@ module fpga_core # output wire sfp_drp_en, output wire sfp_drp_we, input wire [15:0] sfp_drp_do, - input wire sfp_drp_rdy + input wire sfp_drp_rdy, + + /* + * DDR + */ + input wire [DDR_CH-1:0] ddr_clk, + input wire [DDR_CH-1:0] ddr_rst, + + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, + output wire [DDR_CH-1:0] m_axi_ddr_awlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, + output wire [DDR_CH-1:0] m_axi_ddr_awvalid, + input wire [DDR_CH-1:0] m_axi_ddr_awready, + output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, + output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, + output wire [DDR_CH-1:0] m_axi_ddr_wlast, + output wire [DDR_CH-1:0] m_axi_ddr_wvalid, + input wire [DDR_CH-1:0] m_axi_ddr_wready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, + input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, + input wire [DDR_CH-1:0] m_axi_ddr_bvalid, + output wire [DDR_CH-1:0] m_axi_ddr_bready, + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, + output wire [DDR_CH-1:0] m_axi_ddr_arlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, + output wire [DDR_CH-1:0] m_axi_ddr_arvalid, + input wire [DDR_CH-1:0] m_axi_ddr_arready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, + input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, + input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, + input wire [DDR_CH-1:0] m_axi_ddr_rlast, + input wire [DDR_CH-1:0] m_axi_ddr_rvalid, + output wire [DDR_CH-1:0] m_axi_ddr_rready, + + input wire [DDR_CH-1:0] ddr_status ); parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF; @@ -858,6 +914,25 @@ mqnic_core_axi #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .DDR_GROUP_SIZE(1), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_AWUSER_ENABLE(0), + .AXI_DDR_WUSER_ENABLE(0), + .AXI_DDR_BUSER_ENABLE(0), + .AXI_DDR_ARUSER_ENABLE(0), + .AXI_DDR_RUSER_ENABLE(0), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + .AXI_DDR_FIXED_BURST(0), + .AXI_DDR_WRAP_BURST(1), + .HBM_ENABLE(0), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1112,6 +1187,108 @@ core_inst ( .rx_status(eth_rx_status), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awuser(), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wuser(), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_buser(0), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_aruser(), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_ruser(0), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + + /* + * HBM + */ + .hbm_clk(0), + .hbm_rst(0), + + .m_axi_hbm_awid(), + .m_axi_hbm_awaddr(), + .m_axi_hbm_awlen(), + .m_axi_hbm_awsize(), + .m_axi_hbm_awburst(), + .m_axi_hbm_awlock(), + .m_axi_hbm_awcache(), + .m_axi_hbm_awprot(), + .m_axi_hbm_awqos(), + .m_axi_hbm_awuser(), + .m_axi_hbm_awvalid(), + .m_axi_hbm_awready(0), + .m_axi_hbm_wdata(), + .m_axi_hbm_wstrb(), + .m_axi_hbm_wlast(), + .m_axi_hbm_wuser(), + .m_axi_hbm_wvalid(), + .m_axi_hbm_wready(0), + .m_axi_hbm_bid(0), + .m_axi_hbm_bresp(0), + .m_axi_hbm_buser(0), + .m_axi_hbm_bvalid(0), + .m_axi_hbm_bready(), + .m_axi_hbm_arid(), + .m_axi_hbm_araddr(), + .m_axi_hbm_arlen(), + .m_axi_hbm_arsize(), + .m_axi_hbm_arburst(), + .m_axi_hbm_arlock(), + .m_axi_hbm_arcache(), + .m_axi_hbm_arprot(), + .m_axi_hbm_arqos(), + .m_axi_hbm_aruser(), + .m_axi_hbm_arvalid(), + .m_axi_hbm_arready(0), + .m_axi_hbm_rid(0), + .m_axi_hbm_rdata(0), + .m_axi_hbm_rresp(0), + .m_axi_hbm_rlast(0), + .m_axi_hbm_ruser(0), + .m_axi_hbm_rvalid(0), + .m_axi_hbm_rready(), + + .hbm_status(0), + /* * Statistics input */ diff --git a/fpga/mqnic/ZCU106/fpga_pcie/README.md b/fpga/mqnic/ZCU106/fpga_pcie/README.md index bb5a8a22f..caf587be6 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/README.md +++ b/fpga/mqnic/ZCU106/fpga_pcie/README.md @@ -4,8 +4,9 @@ This design targets the Xilinx ZCU106 FPGA board. -FPGA: xczu7ev-ffvc1156-2-e -PHY: 10G BASE-R PHY IP core and internal GTH transceiver +* FPGA: xczu7ev-ffvc1156-2-e +* PHY: 10G BASE-R PHY IP core and internal GTH transceiver +* RAM: 2 GB DDR4 2400 (256M x64) ## How to build diff --git a/fpga/mqnic/ZCU106/fpga_pcie/fpga.xdc b/fpga/mqnic/ZCU106/fpga_pcie/fpga.xdc index c65a78e8b..ad37c4f63 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/fpga.xdc +++ b/fpga/mqnic/ZCU106/fpga_pcie/fpga.xdc @@ -10,6 +10,11 @@ set_property -dict {LOC H9 IOSTANDARD LVDS} [get_ports clk_125mhz_p] set_property -dict {LOC G9 IOSTANDARD LVDS} [get_ports clk_125mhz_n] create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p] +# User Si570 (default 300 MHz) +set_property -dict {LOC AH12 IOSTANDARD DIFF_SSTL12} [get_ports clk_user_si570_p] +set_property -dict {LOC AJ12 IOSTANDARD DIFF_SSTL12} [get_ports clk_user_si570_n] +#create_clock -period 3.333 -name clk_user_si570 [get_ports clk_user_si570_p] + # LEDs set_property -dict {LOC AL11 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}] set_property -dict {LOC AL13 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[1]}] @@ -125,4 +130,125 @@ create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_mgt_refclk_p] set_false_path -from [get_ports {pcie_reset_n}] set_input_delay 0 [get_ports {pcie_reset_n}] +# DDR4 +# 4x MT40A256M16GE-075E +set_property -dict {LOC AK9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[0]}] +set_property -dict {LOC AG11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[1]}] +set_property -dict {LOC AJ10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[2]}] +set_property -dict {LOC AL8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[3]}] +set_property -dict {LOC AK10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[4]}] +set_property -dict {LOC AH8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[5]}] +set_property -dict {LOC AJ9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[6]}] +set_property -dict {LOC AG8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[7]}] +set_property -dict {LOC AH9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[8]}] +set_property -dict {LOC AG10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[9]}] +set_property -dict {LOC AH13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[10]}] +set_property -dict {LOC AG9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[11]}] +set_property -dict {LOC AM13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[12]}] +set_property -dict {LOC AF8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[13]}] +set_property -dict {LOC AC12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[14]}] +set_property -dict {LOC AE12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[15]}] +set_property -dict {LOC AF11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[16]}] +set_property -dict {LOC AK8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_ba[0]}] +set_property -dict {LOC AL12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_ba[1]}] +set_property -dict {LOC AE14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_bg[0]}] +set_property -dict {LOC AH11 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_ck_t}] +set_property -dict {LOC AJ11 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_ck_c}] +set_property -dict {LOC AB13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_cke}] +set_property -dict {LOC AD12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_cs_n}] +set_property -dict {LOC AD14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_act_n}] +set_property -dict {LOC AF10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_odt}] +set_property -dict {LOC AC13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_par}] +set_property -dict {LOC AF12 IOSTANDARD LVCMOS12 } [get_ports {ddr4_reset_n}] +set_property -dict {LOC AF16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[0]}] ;# U101.G2 DQL0 +set_property -dict {LOC AF18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[1]}] ;# U101.F7 DQL1 +set_property -dict {LOC AG15 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[2]}] ;# U101.H3 DQL2 +set_property -dict {LOC AF17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[3]}] ;# U101.H7 DQL3 +set_property -dict {LOC AF15 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[4]}] ;# U101.H2 DQL4 +set_property -dict {LOC AG18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[5]}] ;# U101.H8 DQL5 +set_property -dict {LOC AG14 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[6]}] ;# U101.J3 DQL6 +set_property -dict {LOC AE17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[7]}] ;# U101.J7 DQL7 +set_property -dict {LOC AA14 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[8]}] ;# U101.A3 DQU0 +set_property -dict {LOC AC16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[9]}] ;# U101.B8 DQU1 +set_property -dict {LOC AB15 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[10]}] ;# U101.C3 DQU2 +set_property -dict {LOC AD16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[11]}] ;# U101.C7 DQU3 +set_property -dict {LOC AB16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[12]}] ;# U101.C2 DQU4 +set_property -dict {LOC AC17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[13]}] ;# U101.C8 DQU5 +set_property -dict {LOC AB14 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[14]}] ;# U101.D3 DQU6 +set_property -dict {LOC AD17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[15]}] ;# U101.D7 DQU7 +set_property -dict {LOC AH14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[0]}] ;# U101.G3 DQSL_T +set_property -dict {LOC AJ14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[0]}] ;# U101.F3 DQSL_C +set_property -dict {LOC AA16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[1]}] ;# U101.B7 DQSU_T +set_property -dict {LOC AA15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[1]}] ;# U101.A7 DQSU_C +set_property -dict {LOC AH18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[0]}] ;# U101.E7 DML_B/DBIL_B +set_property -dict {LOC AD15 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[1]}] ;# U101.E2 DMU_B/DBIU_B + +set_property -dict {LOC AJ16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[16]}] ;# U99.G2 DQL0 +set_property -dict {LOC AJ17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[17]}] ;# U99.F7 DQL1 +set_property -dict {LOC AL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[18]}] ;# U99.H3 DQL2 +set_property -dict {LOC AK17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[19]}] ;# U99.H7 DQL3 +set_property -dict {LOC AJ15 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[20]}] ;# U99.H2 DQL4 +set_property -dict {LOC AK18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[21]}] ;# U99.H8 DQL5 +set_property -dict {LOC AL16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[22]}] ;# U99.J3 DQL6 +set_property -dict {LOC AL18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[23]}] ;# U99.J7 DQL7 +set_property -dict {LOC AP13 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[24]}] ;# U99.A3 DQU0 +set_property -dict {LOC AP16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[25]}] ;# U99.B8 DQU1 +set_property -dict {LOC AP15 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[26]}] ;# U99.C3 DQU2 +set_property -dict {LOC AN16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[27]}] ;# U99.C7 DQU3 +set_property -dict {LOC AN13 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[28]}] ;# U99.C2 DQU4 +set_property -dict {LOC AM18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[29]}] ;# U99.C8 DQU5 +set_property -dict {LOC AN17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[30]}] ;# U99.D3 DQU6 +set_property -dict {LOC AN18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[31]}] ;# U99.D7 DQU7 +set_property -dict {LOC AK15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[2]}] ;# U99.G3 DQSL_T +set_property -dict {LOC AK14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[2]}] ;# U99.F3 DQSL_C +set_property -dict {LOC AM14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[3]}] ;# U99.B7 DQSU_T +set_property -dict {LOC AN14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[3]}] ;# U99.A7 DQSU_C +set_property -dict {LOC AM16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[2]}] ;# U99.E7 DML_B/DBIL_B +set_property -dict {LOC AP18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[3]}] ;# U99.E2 DMU_B/DBIU_B + +set_property -dict {LOC AB19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[32]}] ;# U100.G2 DQL0 +set_property -dict {LOC AD19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[33]}] ;# U100.F7 DQL1 +set_property -dict {LOC AC18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[34]}] ;# U100.H3 DQL2 +set_property -dict {LOC AC19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[35]}] ;# U100.H7 DQL3 +set_property -dict {LOC AA20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[36]}] ;# U100.H2 DQL4 +set_property -dict {LOC AE20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[37]}] ;# U100.H8 DQL5 +set_property -dict {LOC AA19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[38]}] ;# U100.J3 DQL6 +set_property -dict {LOC AD20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[39]}] ;# U100.J7 DQL7 +set_property -dict {LOC AF22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[40]}] ;# U100.A3 DQU0 +set_property -dict {LOC AH21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[41]}] ;# U100.B8 DQU1 +set_property -dict {LOC AG19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[42]}] ;# U100.C3 DQU2 +set_property -dict {LOC AG21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[43]}] ;# U100.C7 DQU3 +set_property -dict {LOC AE24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[44]}] ;# U100.C2 DQU4 +set_property -dict {LOC AG20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[45]}] ;# U100.C8 DQU5 +set_property -dict {LOC AE23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[46]}] ;# U100.D3 DQU6 +set_property -dict {LOC AF21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[47]}] ;# U100.D7 DQU7 +set_property -dict {LOC AA18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[4]}] ;# U100.G3 DQSL_T +set_property -dict {LOC AB18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[4]}] ;# U100.F3 DQSL_C +set_property -dict {LOC AF23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[5]}] ;# U100.B7 DQSU_T +set_property -dict {LOC AG23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[5]}] ;# U100.A7 DQSU_C +set_property -dict {LOC AE18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[4]}] ;# U100.E7 DML_B/DBIL_B +set_property -dict {LOC AH22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[5]}] ;# U100.E2 DMU_B/DBIU_B + +set_property -dict {LOC AL22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[48]}] ;# U2.G2 DQL0 +set_property -dict {LOC AJ22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[49]}] ;# U2.F7 DQL1 +set_property -dict {LOC AL23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[50]}] ;# U2.H3 DQL2 +set_property -dict {LOC AJ21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[51]}] ;# U2.H7 DQL3 +set_property -dict {LOC AK20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[52]}] ;# U2.H2 DQL4 +set_property -dict {LOC AJ19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[53]}] ;# U2.H8 DQL5 +set_property -dict {LOC AK19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[54]}] ;# U2.J3 DQL6 +set_property -dict {LOC AJ20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[55]}] ;# U2.J7 DQL7 +set_property -dict {LOC AP22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[56]}] ;# U2.A3 DQU0 +set_property -dict {LOC AN22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[57]}] ;# U2.B8 DQU1 +set_property -dict {LOC AP21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[58]}] ;# U2.C3 DQU2 +set_property -dict {LOC AP23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[59]}] ;# U2.C7 DQU3 +set_property -dict {LOC AM19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[60]}] ;# U2.C2 DQU4 +set_property -dict {LOC AM23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[61]}] ;# U2.C8 DQU5 +set_property -dict {LOC AN19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[62]}] ;# U2.D3 DQU6 +set_property -dict {LOC AN23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[63]}] ;# U2.D7 DQU7 +set_property -dict {LOC AK22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[6]}] ;# U2.G3 DQSL_T +set_property -dict {LOC AK23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[6]}] ;# U2.F3 DQSL_C +set_property -dict {LOC AM21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[7]}] ;# U2.B7 DQSU_T +set_property -dict {LOC AN21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[7]}] ;# U2.A7 DQSU_C +set_property -dict {LOC AL20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[6]}] ;# U2.E7 DML_B/DBIL_B +set_property -dict {LOC AP19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[7]}] ;# U2.E2 DMU_B/DBIU_B diff --git a/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile b/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile index 72002119e..acf2bfe22 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile +++ b/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile @@ -137,6 +137,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gth.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl b/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl index 752e8fe3f..8892be565 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl +++ b/fpga/mqnic/ZCU106/fpga_pcie/fpga/config.tcl @@ -139,6 +139,12 @@ dict set params MAX_TX_SIZE "9214" dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" dict set params RX_RAM_SIZE "32768" + +# RAM configuration +dict set params DDR_CH "1" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" # Application block configuration dict set params APP_ID "32'h00000000" @@ -190,6 +196,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/ZCU106/fpga_pcie/ip/ddr4_0.tcl b/fpga/mqnic/ZCU106/fpga_pcie/ip/ddr4_0.tcl new file mode 100644 index 000000000..e5a410924 --- /dev/null +++ b/fpga/mqnic/ZCU106/fpga_pcie/ip/ddr4_0.tcl @@ -0,0 +1,19 @@ + +create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 + +set_property -dict [list \ + CONFIG.C0.DDR4_AxiSelection {true} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_AxiIDWidth {8} \ + CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ + CONFIG.C0.DDR4_TimePeriod {833} \ + CONFIG.C0.DDR4_InputClockPeriod {3332} \ + CONFIG.C0.DDR4_MemoryType {Components} \ + CONFIG.C0.DDR4_MemoryPart {MT40A256M16GE-075E} \ + CONFIG.C0.DDR4_DataWidth {64} \ + CONFIG.C0.DDR4_DataMask {DM_NO_DBI} \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_CasLatency {17} \ + CONFIG.C0.DDR4_CasWriteLatency {12} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} +] [get_ips ddr4_0] diff --git a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v index ceced6f5e..cd3b80d56 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v +++ b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v @@ -112,6 +112,15 @@ module fpga # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // RAM configuration + parameter DDR_CH = 1, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 31, + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -181,6 +190,8 @@ module fpga # */ input wire clk_125mhz_p, input wire clk_125mhz_n, + input wire clk_user_si570_p, + input wire clk_user_si570_n, /* * GPIO @@ -224,7 +235,26 @@ module fpga # input wire sfp_mgt_refclk_0_p, input wire sfp_mgt_refclk_0_n, output wire sfp0_tx_disable_b, - output wire sfp1_tx_disable_b + output wire sfp1_tx_disable_b, + + /* + * DDR4 + */ + output wire [16:0] ddr4_adr, + output wire [1:0] ddr4_ba, + output wire [0:0] ddr4_bg, + output wire [0:0] ddr4_ck_t, + output wire [0:0] ddr4_ck_c, + output wire [0:0] ddr4_cke, + output wire [0:0] ddr4_cs_n, + output wire ddr4_act_n, + output wire [0:0] ddr4_odt, + output wire ddr4_par, + output wire ddr4_reset_n, + inout wire [63:0] ddr4_dq, + inout wire [7:0] ddr4_dqs_t, + inout wire [7:0] ddr4_dqs_c, + inout wire [7:0] ddr4_dm_dbi_n ); // PTP configuration @@ -238,6 +268,9 @@ parameter IF_PTP_PERIOD_FNS = 16'h6666; // Interface configuration parameter TX_TAG_WIDTH = 16; +// RAM configuration +parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8); + // Ethernet interface configuration parameter XGMII_DATA_WIDTH = 64; parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8; @@ -827,6 +860,165 @@ assign ptp_clk = sfp_mgt_refclk_0_bufg; assign ptp_rst = sfp_rst; assign ptp_sample_clk = clk_125mhz_int; +// DDR4 +wire [DDR_CH-1:0] ddr_clk; +wire [DDR_CH-1:0] ddr_rst; + +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr; +wire [DDR_CH*8-1:0] m_axi_ddr_awlen; +wire [DDR_CH*3-1:0] m_axi_ddr_awsize; +wire [DDR_CH*2-1:0] m_axi_ddr_awburst; +wire [DDR_CH-1:0] m_axi_ddr_awlock; +wire [DDR_CH*4-1:0] m_axi_ddr_awcache; +wire [DDR_CH*3-1:0] m_axi_ddr_awprot; +wire [DDR_CH*4-1:0] m_axi_ddr_awqos; +wire [DDR_CH-1:0] m_axi_ddr_awvalid; +wire [DDR_CH-1:0] m_axi_ddr_awready; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata; +wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb; +wire [DDR_CH-1:0] m_axi_ddr_wlast; +wire [DDR_CH-1:0] m_axi_ddr_wvalid; +wire [DDR_CH-1:0] m_axi_ddr_wready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid; +wire [DDR_CH*2-1:0] m_axi_ddr_bresp; +wire [DDR_CH-1:0] m_axi_ddr_bvalid; +wire [DDR_CH-1:0] m_axi_ddr_bready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr; +wire [DDR_CH*8-1:0] m_axi_ddr_arlen; +wire [DDR_CH*3-1:0] m_axi_ddr_arsize; +wire [DDR_CH*2-1:0] m_axi_ddr_arburst; +wire [DDR_CH-1:0] m_axi_ddr_arlock; +wire [DDR_CH*4-1:0] m_axi_ddr_arcache; +wire [DDR_CH*3-1:0] m_axi_ddr_arprot; +wire [DDR_CH*4-1:0] m_axi_ddr_arqos; +wire [DDR_CH-1:0] m_axi_ddr_arvalid; +wire [DDR_CH-1:0] m_axi_ddr_arready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata; +wire [DDR_CH*2-1:0] m_axi_ddr_rresp; +wire [DDR_CH-1:0] m_axi_ddr_rlast; +wire [DDR_CH-1:0] m_axi_ddr_rvalid; +wire [DDR_CH-1:0] m_axi_ddr_rready; + +wire [DDR_CH-1:0] ddr_status; + +generate + +if (DDR_ENABLE && DDR_CH > 0) begin + +ddr4_0 ddr4_inst ( + .c0_sys_clk_p(clk_user_si570_p), + .c0_sys_clk_n(clk_user_si570_n), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[0 +: 1]), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_adr), + .c0_ddr4_ba(ddr4_ba), + .c0_ddr4_cke(ddr4_cke), + .c0_ddr4_cs_n(ddr4_cs_n), + .c0_ddr4_dq(ddr4_dq), + .c0_ddr4_dqs_t(ddr4_dqs_t), + .c0_ddr4_dqs_c(ddr4_dqs_c), + .c0_ddr4_dm_dbi_n(ddr4_dm_dbi_n), + .c0_ddr4_odt(ddr4_odt), + .c0_ddr4_bg(ddr4_bg), + .c0_ddr4_reset_n(ddr4_reset_n), + .c0_ddr4_act_n(ddr4_act_n), + .c0_ddr4_ck_t(ddr4_ck_t), + .c0_ddr4_ck_c(ddr4_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[0 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[0 +: 1]), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_adr = {17{1'bz}}; +assign ddr4_ba = {2{1'bz}}; +assign ddr4_bg = {1{1'bz}}; +assign ddr4_cke = 1'bz; +assign ddr4_cs_n = 1'bz; +assign ddr4_act_n = 1'bz; +assign ddr4_odt = 1'bz; +assign ddr4_par = 1'bz; +assign ddr4_reset_n = 1'b0; +assign ddr4_dq = {64{1'bz}}; +assign ddr4_dqs_t = {8{1'bz}}; +assign ddr4_dqs_c = {8{1'bz}}; + +OBUFTDS ddr4_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_ck_t), + .OB(ddr4_ck_c) +); + +assign ddr_clk = 0; +assign ddr_rst = 0; + +assign m_axi_ddr_awready = 0; +assign m_axi_ddr_wready = 0; +assign m_axi_ddr_bid = 0; +assign m_axi_ddr_bresp = 0; +assign m_axi_ddr_bvalid = 0; +assign m_axi_ddr_arready = 0; +assign m_axi_ddr_rid = 0; +assign m_axi_ddr_rdata = 0; +assign m_axi_ddr_rresp = 0; +assign m_axi_ddr_rlast = 0; +assign m_axi_ddr_rvalid = 0; + +assign ddr_status = 0; + +end + +endgenerate + fpga_core #( // FW and board IDs .FPGA_ID(FPGA_ID), @@ -903,6 +1095,16 @@ fpga_core #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1116,7 +1318,53 @@ core_inst ( .sfp_drp_en(sfp_drp_en), .sfp_drp_we(sfp_drp_we), .sfp_drp_do(sfp_drp_do), - .sfp_drp_rdy(sfp_drp_rdy) + .sfp_drp_rdy(sfp_drp_rdy), + + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status) ); endmodule diff --git a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v index 2d6822928..551ec97fc 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v +++ b/fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v @@ -122,6 +122,16 @@ module fpga_core # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // RAM configuration + parameter DDR_CH = 1, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 31, + parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -341,7 +351,53 @@ module fpga_core # output wire sfp_drp_en, output wire sfp_drp_we, input wire [15:0] sfp_drp_do, - input wire sfp_drp_rdy + input wire sfp_drp_rdy, + + /* + * DDR + */ + input wire [DDR_CH-1:0] ddr_clk, + input wire [DDR_CH-1:0] ddr_rst, + + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, + output wire [DDR_CH-1:0] m_axi_ddr_awlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, + output wire [DDR_CH-1:0] m_axi_ddr_awvalid, + input wire [DDR_CH-1:0] m_axi_ddr_awready, + output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, + output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, + output wire [DDR_CH-1:0] m_axi_ddr_wlast, + output wire [DDR_CH-1:0] m_axi_ddr_wvalid, + input wire [DDR_CH-1:0] m_axi_ddr_wready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, + input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, + input wire [DDR_CH-1:0] m_axi_ddr_bvalid, + output wire [DDR_CH-1:0] m_axi_ddr_bready, + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, + output wire [DDR_CH-1:0] m_axi_ddr_arlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, + output wire [DDR_CH-1:0] m_axi_ddr_arvalid, + input wire [DDR_CH-1:0] m_axi_ddr_arready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, + input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, + input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, + input wire [DDR_CH-1:0] m_axi_ddr_rlast, + input wire [DDR_CH-1:0] m_axi_ddr_rvalid, + output wire [DDR_CH-1:0] m_axi_ddr_rready, + + input wire [DDR_CH-1:0] ddr_status ); parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF; @@ -853,6 +909,25 @@ mqnic_core_pcie_us #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .DDR_GROUP_SIZE(1), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_AWUSER_ENABLE(0), + .AXI_DDR_WUSER_ENABLE(0), + .AXI_DDR_BUSER_ENABLE(0), + .AXI_DDR_ARUSER_ENABLE(0), + .AXI_DDR_RUSER_ENABLE(0), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + .AXI_DDR_FIXED_BURST(0), + .AXI_DDR_WRAP_BURST(1), + .HBM_ENABLE(0), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1126,6 +1201,108 @@ core_inst ( .eth_rx_status(eth_rx_status), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awuser(), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wuser(), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_buser(0), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_aruser(), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_ruser(0), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + + /* + * HBM + */ + .hbm_clk(0), + .hbm_rst(0), + + .m_axi_hbm_awid(), + .m_axi_hbm_awaddr(), + .m_axi_hbm_awlen(), + .m_axi_hbm_awsize(), + .m_axi_hbm_awburst(), + .m_axi_hbm_awlock(), + .m_axi_hbm_awcache(), + .m_axi_hbm_awprot(), + .m_axi_hbm_awqos(), + .m_axi_hbm_awuser(), + .m_axi_hbm_awvalid(), + .m_axi_hbm_awready(0), + .m_axi_hbm_wdata(), + .m_axi_hbm_wstrb(), + .m_axi_hbm_wlast(), + .m_axi_hbm_wuser(), + .m_axi_hbm_wvalid(), + .m_axi_hbm_wready(0), + .m_axi_hbm_bid(0), + .m_axi_hbm_bresp(0), + .m_axi_hbm_buser(0), + .m_axi_hbm_bvalid(0), + .m_axi_hbm_bready(), + .m_axi_hbm_arid(), + .m_axi_hbm_araddr(), + .m_axi_hbm_arlen(), + .m_axi_hbm_arsize(), + .m_axi_hbm_arburst(), + .m_axi_hbm_arlock(), + .m_axi_hbm_arcache(), + .m_axi_hbm_arprot(), + .m_axi_hbm_arqos(), + .m_axi_hbm_aruser(), + .m_axi_hbm_arvalid(), + .m_axi_hbm_arready(0), + .m_axi_hbm_rid(0), + .m_axi_hbm_rdata(0), + .m_axi_hbm_rresp(0), + .m_axi_hbm_rlast(0), + .m_axi_hbm_ruser(0), + .m_axi_hbm_rvalid(0), + .m_axi_hbm_rready(), + + .hbm_status(0), + /* * Statistics input */ diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/README.md b/fpga/mqnic/ZCU106/fpga_zynqmp/README.md index d10c2aa8b..f3641abbd 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/README.md +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/README.md @@ -5,8 +5,9 @@ This design targets the Xilinx ZCU106 FPGA board. The host system of the NIC is the Zynq US+ MPSoC. -FPGA: xczu7ev-ffvc1156-2-e -PHY: 10G BASE-R PHY IP core and internal GTH transceiver +* FPGA: xczu7ev-ffvc1156-2-e +* PHY: 10G BASE-R PHY IP core and internal GTH transceiver +* RAM: 2 GB DDR4 2400 (256M x64) ## How to build diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga.xdc b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga.xdc index 279351e45..d355d2816 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga.xdc +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga.xdc @@ -10,6 +10,11 @@ set_property -dict {LOC H9 IOSTANDARD LVDS} [get_ports clk_125mhz_p] set_property -dict {LOC G9 IOSTANDARD LVDS} [get_ports clk_125mhz_n] create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p] +# User Si570 (default 300 MHz) +set_property -dict {LOC AH12 IOSTANDARD DIFF_SSTL12} [get_ports clk_user_si570_p] +set_property -dict {LOC AJ12 IOSTANDARD DIFF_SSTL12} [get_ports clk_user_si570_n] +#create_clock -period 3.333 -name clk_user_si570 [get_ports clk_user_si570_p] + # LEDs set_property -dict {LOC AL11 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}] set_property -dict {LOC AL13 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[1]}] @@ -86,3 +91,153 @@ create_clock -period 6.400 -name sfp_mgt_refclk_0 [get_ports sfp_mgt_refclk_0_p] set_false_path -to [get_ports {sfp0_tx_disable_b sfp1_tx_disable_b}] set_output_delay 0 [get_ports {sfp0_tx_disable_b sfp1_tx_disable_b}] + +# PCIe Interface +#set_property -dict {LOC AE2 } [get_ports {pcie_rx_p[0]}] ;# MGTHRXP3_224 GTHE4_CHANNEL_X0Y7 / GTHE4_COMMON_X0Y1 +#set_property -dict {LOC AE1 } [get_ports {pcie_rx_n[0]}] ;# MGTHRXN3_224 GTHE4_CHANNEL_X0Y7 / GTHE4_COMMON_X0Y1 +#set_property -dict {LOC AD4 } [get_ports {pcie_tx_p[0]}] ;# MGTHTXP3_224 GTHE4_CHANNEL_X0Y7 / GTHE4_COMMON_X0Y1 +#set_property -dict {LOC AD3 } [get_ports {pcie_tx_n[0]}] ;# MGTHTXN3_224 GTHE4_CHANNEL_X0Y7 / GTHE4_COMMON_X0Y1 +#set_property -dict {LOC AF4 } [get_ports {pcie_rx_p[1]}] ;# MGTHRXP2_224 GTHE4_CHANNEL_X0Y6 / GTHE4_COMMON_X0Y1 +#set_property -dict {LOC AF3 } [get_ports {pcie_rx_n[1]}] ;# MGTHRXN2_224 GTHE4_CHANNEL_X0Y6 / GTHE4_COMMON_X0Y1 +#set_property -dict {LOC AE6 } [get_ports {pcie_tx_p[1]}] ;# MGTHTXP2_224 GTHE4_CHANNEL_X0Y6 / GTHE4_COMMON_X0Y1 +#set_property -dict {LOC AE5 } [get_ports {pcie_tx_n[1]}] ;# MGTHTXN2_224 GTHE4_CHANNEL_X0Y6 / GTHE4_COMMON_X0Y1 +#set_property -dict {LOC AG2 } [get_ports {pcie_rx_p[2]}] ;# MGTHRXP1_224 GTHE4_CHANNEL_X0Y5 / GTHE4_COMMON_X0Y1 +#set_property -dict {LOC AG1 } [get_ports {pcie_rx_n[2]}] ;# MGTHRXN1_224 GTHE4_CHANNEL_X0Y5 / GTHE4_COMMON_X0Y1 +#set_property -dict {LOC AG6 } [get_ports {pcie_tx_p[2]}] ;# MGTHTXP1_224 GTHE4_CHANNEL_X0Y5 / GTHE4_COMMON_X0Y1 +#set_property -dict {LOC AG5 } [get_ports {pcie_tx_n[2]}] ;# MGTHTXN1_224 GTHE4_CHANNEL_X0Y5 / GTHE4_COMMON_X0Y1 +#set_property -dict {LOC AJ2 } [get_ports {pcie_rx_p[3]}] ;# MGTHRXP0_224 GTHE4_CHANNEL_X0Y4 / GTHE4_COMMON_X0Y1 +#set_property -dict {LOC AJ1 } [get_ports {pcie_rx_n[3]}] ;# MGTHRXN0_224 GTHE4_CHANNEL_X0Y4 / GTHE4_COMMON_X0Y1 +#set_property -dict {LOC AH4 } [get_ports {pcie_tx_p[3]}] ;# MGTHTXP0_224 GTHE4_CHANNEL_X0Y4 / GTHE4_COMMON_X0Y1 +#set_property -dict {LOC AH3 } [get_ports {pcie_tx_n[3]}] ;# MGTHTXN0_224 GTHE4_CHANNEL_X0Y4 / GTHE4_COMMON_X0Y1 +#set_property -dict {LOC AB8 } [get_ports pcie_mgt_refclk_p] ;# MGTREFCLK0P_224 +#set_property -dict {LOC AB7 } [get_ports pcie_mgt_refclk_n] ;# MGTREFCLK0N_224 +#set_property -dict {LOC L8 IOSTANDARD LVCMOS33 PULLUP true} [get_ports pcie_reset_n] + +# 100 MHz MGT reference clock +#create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_mgt_refclk_p] + +#set_false_path -from [get_ports {pcie_reset_n}] +#set_input_delay 0 [get_ports {pcie_reset_n}] + +# DDR4 +# 4x MT40A256M16GE-075E +set_property -dict {LOC AK9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[0]}] +set_property -dict {LOC AG11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[1]}] +set_property -dict {LOC AJ10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[2]}] +set_property -dict {LOC AL8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[3]}] +set_property -dict {LOC AK10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[4]}] +set_property -dict {LOC AH8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[5]}] +set_property -dict {LOC AJ9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[6]}] +set_property -dict {LOC AG8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[7]}] +set_property -dict {LOC AH9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[8]}] +set_property -dict {LOC AG10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[9]}] +set_property -dict {LOC AH13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[10]}] +set_property -dict {LOC AG9 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[11]}] +set_property -dict {LOC AM13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[12]}] +set_property -dict {LOC AF8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[13]}] +set_property -dict {LOC AC12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[14]}] +set_property -dict {LOC AE12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[15]}] +set_property -dict {LOC AF11 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_adr[16]}] +set_property -dict {LOC AK8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_ba[0]}] +set_property -dict {LOC AL12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_ba[1]}] +set_property -dict {LOC AE14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_bg[0]}] +set_property -dict {LOC AH11 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_ck_t}] +set_property -dict {LOC AJ11 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_ck_c}] +set_property -dict {LOC AB13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_cke}] +set_property -dict {LOC AD12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_cs_n}] +set_property -dict {LOC AD14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_act_n}] +set_property -dict {LOC AF10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_odt}] +set_property -dict {LOC AC13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_par}] +set_property -dict {LOC AF12 IOSTANDARD LVCMOS12 } [get_ports {ddr4_reset_n}] + +set_property -dict {LOC AF16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[0]}] ;# U101.G2 DQL0 +set_property -dict {LOC AF18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[1]}] ;# U101.F7 DQL1 +set_property -dict {LOC AG15 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[2]}] ;# U101.H3 DQL2 +set_property -dict {LOC AF17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[3]}] ;# U101.H7 DQL3 +set_property -dict {LOC AF15 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[4]}] ;# U101.H2 DQL4 +set_property -dict {LOC AG18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[5]}] ;# U101.H8 DQL5 +set_property -dict {LOC AG14 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[6]}] ;# U101.J3 DQL6 +set_property -dict {LOC AE17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[7]}] ;# U101.J7 DQL7 +set_property -dict {LOC AA14 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[8]}] ;# U101.A3 DQU0 +set_property -dict {LOC AC16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[9]}] ;# U101.B8 DQU1 +set_property -dict {LOC AB15 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[10]}] ;# U101.C3 DQU2 +set_property -dict {LOC AD16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[11]}] ;# U101.C7 DQU3 +set_property -dict {LOC AB16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[12]}] ;# U101.C2 DQU4 +set_property -dict {LOC AC17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[13]}] ;# U101.C8 DQU5 +set_property -dict {LOC AB14 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[14]}] ;# U101.D3 DQU6 +set_property -dict {LOC AD17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[15]}] ;# U101.D7 DQU7 +set_property -dict {LOC AH14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[0]}] ;# U101.G3 DQSL_T +set_property -dict {LOC AJ14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[0]}] ;# U101.F3 DQSL_C +set_property -dict {LOC AA16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[1]}] ;# U101.B7 DQSU_T +set_property -dict {LOC AA15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[1]}] ;# U101.A7 DQSU_C +set_property -dict {LOC AH18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[0]}] ;# U101.E7 DML_B/DBIL_B +set_property -dict {LOC AD15 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[1]}] ;# U101.E2 DMU_B/DBIU_B + +set_property -dict {LOC AJ16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[16]}] ;# U99.G2 DQL0 +set_property -dict {LOC AJ17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[17]}] ;# U99.F7 DQL1 +set_property -dict {LOC AL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[18]}] ;# U99.H3 DQL2 +set_property -dict {LOC AK17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[19]}] ;# U99.H7 DQL3 +set_property -dict {LOC AJ15 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[20]}] ;# U99.H2 DQL4 +set_property -dict {LOC AK18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[21]}] ;# U99.H8 DQL5 +set_property -dict {LOC AL16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[22]}] ;# U99.J3 DQL6 +set_property -dict {LOC AL18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[23]}] ;# U99.J7 DQL7 +set_property -dict {LOC AP13 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[24]}] ;# U99.A3 DQU0 +set_property -dict {LOC AP16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[25]}] ;# U99.B8 DQU1 +set_property -dict {LOC AP15 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[26]}] ;# U99.C3 DQU2 +set_property -dict {LOC AN16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[27]}] ;# U99.C7 DQU3 +set_property -dict {LOC AN13 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[28]}] ;# U99.C2 DQU4 +set_property -dict {LOC AM18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[29]}] ;# U99.C8 DQU5 +set_property -dict {LOC AN17 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[30]}] ;# U99.D3 DQU6 +set_property -dict {LOC AN18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[31]}] ;# U99.D7 DQU7 +set_property -dict {LOC AK15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[2]}] ;# U99.G3 DQSL_T +set_property -dict {LOC AK14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[2]}] ;# U99.F3 DQSL_C +set_property -dict {LOC AM14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[3]}] ;# U99.B7 DQSU_T +set_property -dict {LOC AN14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[3]}] ;# U99.A7 DQSU_C +set_property -dict {LOC AM16 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[2]}] ;# U99.E7 DML_B/DBIL_B +set_property -dict {LOC AP18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[3]}] ;# U99.E2 DMU_B/DBIU_B + +set_property -dict {LOC AB19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[32]}] ;# U100.G2 DQL0 +set_property -dict {LOC AD19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[33]}] ;# U100.F7 DQL1 +set_property -dict {LOC AC18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[34]}] ;# U100.H3 DQL2 +set_property -dict {LOC AC19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[35]}] ;# U100.H7 DQL3 +set_property -dict {LOC AA20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[36]}] ;# U100.H2 DQL4 +set_property -dict {LOC AE20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[37]}] ;# U100.H8 DQL5 +set_property -dict {LOC AA19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[38]}] ;# U100.J3 DQL6 +set_property -dict {LOC AD20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[39]}] ;# U100.J7 DQL7 +set_property -dict {LOC AF22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[40]}] ;# U100.A3 DQU0 +set_property -dict {LOC AH21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[41]}] ;# U100.B8 DQU1 +set_property -dict {LOC AG19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[42]}] ;# U100.C3 DQU2 +set_property -dict {LOC AG21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[43]}] ;# U100.C7 DQU3 +set_property -dict {LOC AE24 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[44]}] ;# U100.C2 DQU4 +set_property -dict {LOC AG20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[45]}] ;# U100.C8 DQU5 +set_property -dict {LOC AE23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[46]}] ;# U100.D3 DQU6 +set_property -dict {LOC AF21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[47]}] ;# U100.D7 DQU7 +set_property -dict {LOC AA18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[4]}] ;# U100.G3 DQSL_T +set_property -dict {LOC AB18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[4]}] ;# U100.F3 DQSL_C +set_property -dict {LOC AF23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[5]}] ;# U100.B7 DQSU_T +set_property -dict {LOC AG23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[5]}] ;# U100.A7 DQSU_C +set_property -dict {LOC AE18 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[4]}] ;# U100.E7 DML_B/DBIL_B +set_property -dict {LOC AH22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[5]}] ;# U100.E2 DMU_B/DBIU_B + +set_property -dict {LOC AL22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[48]}] ;# U2.G2 DQL0 +set_property -dict {LOC AJ22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[49]}] ;# U2.F7 DQL1 +set_property -dict {LOC AL23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[50]}] ;# U2.H3 DQL2 +set_property -dict {LOC AJ21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[51]}] ;# U2.H7 DQL3 +set_property -dict {LOC AK20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[52]}] ;# U2.H2 DQL4 +set_property -dict {LOC AJ19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[53]}] ;# U2.H8 DQL5 +set_property -dict {LOC AK19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[54]}] ;# U2.J3 DQL6 +set_property -dict {LOC AJ20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[55]}] ;# U2.J7 DQL7 +set_property -dict {LOC AP22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[56]}] ;# U2.A3 DQU0 +set_property -dict {LOC AN22 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[57]}] ;# U2.B8 DQU1 +set_property -dict {LOC AP21 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[58]}] ;# U2.C3 DQU2 +set_property -dict {LOC AP23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[59]}] ;# U2.C7 DQU3 +set_property -dict {LOC AM19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[60]}] ;# U2.C2 DQU4 +set_property -dict {LOC AM23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[61]}] ;# U2.C8 DQU5 +set_property -dict {LOC AN19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[62]}] ;# U2.D3 DQU6 +set_property -dict {LOC AN23 IOSTANDARD POD12_DCI } [get_ports {ddr4_dq[63]}] ;# U2.D7 DQU7 +set_property -dict {LOC AK22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[6]}] ;# U2.G3 DQSL_T +set_property -dict {LOC AK23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[6]}] ;# U2.F3 DQSL_C +set_property -dict {LOC AM21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_t[7]}] ;# U2.B7 DQSU_T +set_property -dict {LOC AN21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_dqs_c[7]}] ;# U2.A7 DQSU_C +set_property -dict {LOC AL20 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[6]}] ;# U2.E7 DML_B/DBIL_B +set_property -dict {LOC AP19 IOSTANDARD POD12_DCI } [get_ports {ddr4_dm_dbi_n[7]}] ;# U2.E2 DMU_B/DBIU_B diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile index bad0a6715..c69e19fc1 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile @@ -119,6 +119,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/zynq_ps.tcl IP_TCL_FILES += ip/eth_xcvr_gth.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl index 248dc68c4..87133e832 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl @@ -132,6 +132,12 @@ dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" dict set params RX_RAM_SIZE "32768" +# RAM configuration +dict set params DDR_CH "1" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" + # Application block configuration dict set params APP_ID "32'h00000000" dict set params APP_ENABLE "0" @@ -193,6 +199,19 @@ dict set params STAT_AXI_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # apply parameters to top-level set param_list {} dict for {name value} $params { diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/ip/ddr4_0.tcl b/fpga/mqnic/ZCU106/fpga_zynqmp/ip/ddr4_0.tcl new file mode 100644 index 000000000..e5a410924 --- /dev/null +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/ip/ddr4_0.tcl @@ -0,0 +1,19 @@ + +create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 + +set_property -dict [list \ + CONFIG.C0.DDR4_AxiSelection {true} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_AxiIDWidth {8} \ + CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ + CONFIG.C0.DDR4_TimePeriod {833} \ + CONFIG.C0.DDR4_InputClockPeriod {3332} \ + CONFIG.C0.DDR4_MemoryType {Components} \ + CONFIG.C0.DDR4_MemoryPart {MT40A256M16GE-075E} \ + CONFIG.C0.DDR4_DataWidth {64} \ + CONFIG.C0.DDR4_DataMask {DM_NO_DBI} \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_CasLatency {17} \ + CONFIG.C0.DDR4_CasWriteLatency {12} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} +] [get_ips ddr4_0] diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/ps/petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi b/fpga/mqnic/ZCU106/fpga_zynqmp/ps/petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi index c1ee9f77f..972ee550b 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/ps/petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/ps/petalinux/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi @@ -59,6 +59,11 @@ }; }; +/* USER SI570 (U42) */ +&si570_1 { + clock-frequency = <300000000>; +}; + /* USER MGT SI570 (U56) */ &si570_2 { clock-frequency = <156250000>; diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v index 73a77f368..31de649a0 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v @@ -112,6 +112,15 @@ module fpga # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // RAM configuration + parameter DDR_CH = 1, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 31, + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -171,6 +180,8 @@ module fpga # */ input wire clk_125mhz_p, input wire clk_125mhz_n, + input wire clk_user_si570_p, + input wire clk_user_si570_n, /* * GPIO @@ -197,7 +208,26 @@ module fpga # input wire sfp_mgt_refclk_0_p, input wire sfp_mgt_refclk_0_n, output wire sfp0_tx_disable_b, - output wire sfp1_tx_disable_b + output wire sfp1_tx_disable_b, + + /* + * DDR4 + */ + output wire [16:0] ddr4_adr, + output wire [1:0] ddr4_ba, + output wire [0:0] ddr4_bg, + output wire [0:0] ddr4_ck_t, + output wire [0:0] ddr4_ck_c, + output wire [0:0] ddr4_cke, + output wire [0:0] ddr4_cs_n, + output wire ddr4_act_n, + output wire [0:0] ddr4_odt, + output wire ddr4_par, + output wire ddr4_reset_n, + inout wire [63:0] ddr4_dq, + inout wire [7:0] ddr4_dqs_t, + inout wire [7:0] ddr4_dqs_c, + inout wire [7:0] ddr4_dm_dbi_n ); // PTP configuration @@ -211,6 +241,9 @@ parameter IF_PTP_PERIOD_FNS = 16'h6666; // Interface configuration parameter TX_TAG_WIDTH = 16; +// RAM configuration +parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8); + // Ethernet interface configuration parameter XGMII_DATA_WIDTH = 64; parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8; @@ -693,6 +726,165 @@ assign ptp_clk = sfp_mgt_refclk_0_bufg; assign ptp_rst = sfp_rst; assign ptp_sample_clk = clk_125mhz_int; +// DDR4 +wire [DDR_CH-1:0] ddr_clk; +wire [DDR_CH-1:0] ddr_rst; + +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr; +wire [DDR_CH*8-1:0] m_axi_ddr_awlen; +wire [DDR_CH*3-1:0] m_axi_ddr_awsize; +wire [DDR_CH*2-1:0] m_axi_ddr_awburst; +wire [DDR_CH-1:0] m_axi_ddr_awlock; +wire [DDR_CH*4-1:0] m_axi_ddr_awcache; +wire [DDR_CH*3-1:0] m_axi_ddr_awprot; +wire [DDR_CH*4-1:0] m_axi_ddr_awqos; +wire [DDR_CH-1:0] m_axi_ddr_awvalid; +wire [DDR_CH-1:0] m_axi_ddr_awready; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata; +wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb; +wire [DDR_CH-1:0] m_axi_ddr_wlast; +wire [DDR_CH-1:0] m_axi_ddr_wvalid; +wire [DDR_CH-1:0] m_axi_ddr_wready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid; +wire [DDR_CH*2-1:0] m_axi_ddr_bresp; +wire [DDR_CH-1:0] m_axi_ddr_bvalid; +wire [DDR_CH-1:0] m_axi_ddr_bready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr; +wire [DDR_CH*8-1:0] m_axi_ddr_arlen; +wire [DDR_CH*3-1:0] m_axi_ddr_arsize; +wire [DDR_CH*2-1:0] m_axi_ddr_arburst; +wire [DDR_CH-1:0] m_axi_ddr_arlock; +wire [DDR_CH*4-1:0] m_axi_ddr_arcache; +wire [DDR_CH*3-1:0] m_axi_ddr_arprot; +wire [DDR_CH*4-1:0] m_axi_ddr_arqos; +wire [DDR_CH-1:0] m_axi_ddr_arvalid; +wire [DDR_CH-1:0] m_axi_ddr_arready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata; +wire [DDR_CH*2-1:0] m_axi_ddr_rresp; +wire [DDR_CH-1:0] m_axi_ddr_rlast; +wire [DDR_CH-1:0] m_axi_ddr_rvalid; +wire [DDR_CH-1:0] m_axi_ddr_rready; + +wire [DDR_CH-1:0] ddr_status; + +generate + +if (DDR_ENABLE && DDR_CH > 0) begin + +ddr4_0 ddr4_inst ( + .c0_sys_clk_p(clk_user_si570_p), + .c0_sys_clk_n(clk_user_si570_n), + .sys_rst(zynq_pl_reset), + + .c0_init_calib_complete(ddr_status[0 +: 1]), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_adr), + .c0_ddr4_ba(ddr4_ba), + .c0_ddr4_cke(ddr4_cke), + .c0_ddr4_cs_n(ddr4_cs_n), + .c0_ddr4_dq(ddr4_dq), + .c0_ddr4_dqs_t(ddr4_dqs_t), + .c0_ddr4_dqs_c(ddr4_dqs_c), + .c0_ddr4_dm_dbi_n(ddr4_dm_dbi_n), + .c0_ddr4_odt(ddr4_odt), + .c0_ddr4_bg(ddr4_bg), + .c0_ddr4_reset_n(ddr4_reset_n), + .c0_ddr4_act_n(ddr4_act_n), + .c0_ddr4_ck_t(ddr4_ck_t), + .c0_ddr4_ck_c(ddr4_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[0 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[0 +: 1]), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_adr = {17{1'bz}}; +assign ddr4_ba = {2{1'bz}}; +assign ddr4_bg = {1{1'bz}}; +assign ddr4_cke = 1'bz; +assign ddr4_cs_n = 1'bz; +assign ddr4_act_n = 1'bz; +assign ddr4_odt = 1'bz; +assign ddr4_par = 1'bz; +assign ddr4_reset_n = 1'b0; +assign ddr4_dq = {64{1'bz}}; +assign ddr4_dqs_t = {8{1'bz}}; +assign ddr4_dqs_c = {8{1'bz}}; + +OBUFTDS ddr4_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_ck_t), + .OB(ddr4_ck_c) +); + +assign ddr_clk = 0; +assign ddr_rst = 0; + +assign m_axi_ddr_awready = 0; +assign m_axi_ddr_wready = 0; +assign m_axi_ddr_bid = 0; +assign m_axi_ddr_bresp = 0; +assign m_axi_ddr_bvalid = 0; +assign m_axi_ddr_arready = 0; +assign m_axi_ddr_rid = 0; +assign m_axi_ddr_rdata = 0; +assign m_axi_ddr_rresp = 0; +assign m_axi_ddr_rlast = 0; +assign m_axi_ddr_rvalid = 0; + +assign ddr_status = 0; + +end + +endgenerate + fpga_core #( // FW and board IDs .FPGA_ID(FPGA_ID), @@ -769,6 +961,16 @@ fpga_core #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -980,7 +1182,53 @@ core_inst ( .sfp_drp_en(sfp_drp_en), .sfp_drp_we(sfp_drp_we), .sfp_drp_do(sfp_drp_do), - .sfp_drp_rdy(sfp_drp_rdy) + .sfp_drp_rdy(sfp_drp_rdy), + + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status) ); endmodule diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v index d51c04a0f..86c4a1f6b 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v @@ -122,6 +122,16 @@ module fpga_core # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // RAM configuration + parameter DDR_CH = 1, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 31, + parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -335,7 +345,53 @@ module fpga_core # output wire sfp_drp_en, output wire sfp_drp_we, input wire [15:0] sfp_drp_do, - input wire sfp_drp_rdy + input wire sfp_drp_rdy, + + /* + * DDR + */ + input wire [DDR_CH-1:0] ddr_clk, + input wire [DDR_CH-1:0] ddr_rst, + + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, + output wire [DDR_CH-1:0] m_axi_ddr_awlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, + output wire [DDR_CH-1:0] m_axi_ddr_awvalid, + input wire [DDR_CH-1:0] m_axi_ddr_awready, + output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, + output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, + output wire [DDR_CH-1:0] m_axi_ddr_wlast, + output wire [DDR_CH-1:0] m_axi_ddr_wvalid, + input wire [DDR_CH-1:0] m_axi_ddr_wready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, + input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, + input wire [DDR_CH-1:0] m_axi_ddr_bvalid, + output wire [DDR_CH-1:0] m_axi_ddr_bready, + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, + output wire [DDR_CH-1:0] m_axi_ddr_arlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, + output wire [DDR_CH-1:0] m_axi_ddr_arvalid, + input wire [DDR_CH-1:0] m_axi_ddr_arready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, + input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, + input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, + input wire [DDR_CH-1:0] m_axi_ddr_rlast, + input wire [DDR_CH-1:0] m_axi_ddr_rvalid, + output wire [DDR_CH-1:0] m_axi_ddr_rready, + + input wire [DDR_CH-1:0] ddr_status ); parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF; @@ -812,6 +868,25 @@ mqnic_core_axi #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .DDR_GROUP_SIZE(1), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_AWUSER_ENABLE(0), + .AXI_DDR_WUSER_ENABLE(0), + .AXI_DDR_BUSER_ENABLE(0), + .AXI_DDR_ARUSER_ENABLE(0), + .AXI_DDR_RUSER_ENABLE(0), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + .AXI_DDR_FIXED_BURST(0), + .AXI_DDR_WRAP_BURST(1), + .HBM_ENABLE(0), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1066,6 +1141,108 @@ core_inst ( .rx_status(eth_rx_status), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awuser(), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wuser(), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_buser(0), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_aruser(), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_ruser(0), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + + /* + * HBM + */ + .hbm_clk(0), + .hbm_rst(0), + + .m_axi_hbm_awid(), + .m_axi_hbm_awaddr(), + .m_axi_hbm_awlen(), + .m_axi_hbm_awsize(), + .m_axi_hbm_awburst(), + .m_axi_hbm_awlock(), + .m_axi_hbm_awcache(), + .m_axi_hbm_awprot(), + .m_axi_hbm_awqos(), + .m_axi_hbm_awuser(), + .m_axi_hbm_awvalid(), + .m_axi_hbm_awready(0), + .m_axi_hbm_wdata(), + .m_axi_hbm_wstrb(), + .m_axi_hbm_wlast(), + .m_axi_hbm_wuser(), + .m_axi_hbm_wvalid(), + .m_axi_hbm_wready(0), + .m_axi_hbm_bid(0), + .m_axi_hbm_bresp(0), + .m_axi_hbm_buser(0), + .m_axi_hbm_bvalid(0), + .m_axi_hbm_bready(), + .m_axi_hbm_arid(), + .m_axi_hbm_araddr(), + .m_axi_hbm_arlen(), + .m_axi_hbm_arsize(), + .m_axi_hbm_arburst(), + .m_axi_hbm_arlock(), + .m_axi_hbm_arcache(), + .m_axi_hbm_arprot(), + .m_axi_hbm_arqos(), + .m_axi_hbm_aruser(), + .m_axi_hbm_arvalid(), + .m_axi_hbm_arready(0), + .m_axi_hbm_rid(0), + .m_axi_hbm_rdata(0), + .m_axi_hbm_rresp(0), + .m_axi_hbm_rlast(0), + .m_axi_hbm_ruser(0), + .m_axi_hbm_rvalid(0), + .m_axi_hbm_rready(), + + .hbm_status(0), + /* * Statistics input */ diff --git a/fpga/mqnic/fb2CG/fpga_100g/README.md b/fpga/mqnic/fb2CG/fpga_100g/README.md index 5a8a117c3..4104f7d2b 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/README.md +++ b/fpga/mqnic/fb2CG/fpga_100g/README.md @@ -7,6 +7,7 @@ This design targets the Silicom fb2CG@KU15P FPGA board. * FPGA: xcku15p-ffve1760-2-e * MAC: Xilinx 100G CMAC * PHY: 100G CAUI-4 CMAC and internal GTY transceivers +* RAM: 16GB DDR4 2666 (4x 512M x72) ## How to build diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga.xdc b/fpga/mqnic/fb2CG/fpga_100g/fpga.xdc index 451eebc0b..429977e4a 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga.xdc +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga.xdc @@ -23,14 +23,22 @@ create_clock -period 20.000 -name init_clk [get_ports init_clk] set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets init_clk_bufg] # DDR4 refclk1 -#set_property -dict {LOC AT32 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk1_p] -#set_property -dict {LOC AU32 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk1_n] -#create_clock -period 3.750 -name clk_ddr4_refclk1 [get_ports clk_ddr4_refclk1_p] +set_property -dict {LOC AT32 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk1_p] +set_property -dict {LOC AU32 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk1_n] +create_clock -period 3.750 -name clk_ddr4_refclk1 [get_ports clk_ddr4_refclk1_p] + +# DDR ref clock sharing +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {name =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1 && name =~*ddr4_c0_inst*}] +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {name =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1 && name =~*ddr4_c1_inst*}] # DDR4 refclk2 -#set_property -dict {LOC G29 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk2_p] -#set_property -dict {LOC G28 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk2_n] -#create_clock -period 3.750 -name clk_ddr4_refclk2 [get_ports clk_ddr4_refclk1_p] +set_property -dict {LOC G28 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk2_p] +set_property -dict {LOC G29 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk2_n] +create_clock -period 3.750 -name clk_ddr4_refclk2 [get_ports clk_ddr4_refclk2_p] + +# DDR ref clock sharing +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {name =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1 && name =~*ddr4_c2_inst*}] +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {name =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1 && name =~*ddr4_c3_inst*}] # LEDs set_property -dict {LOC C4 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports led_sreg_d] @@ -264,3 +272,539 @@ create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_refclk_p] set_false_path -from [get_ports {pcie_rst_n}] set_input_delay 0 [get_ports {pcie_rst_n}] + +# DDR4 C0 +# 5x K4A8G165WB-BCTD / MT40A512M16HA-075E +set_property -dict {LOC AY22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}] +set_property -dict {LOC AY23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}] +set_property -dict {LOC AV23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}] +set_property -dict {LOC AY24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}] +set_property -dict {LOC AK23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}] +set_property -dict {LOC AV21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}] +set_property -dict {LOC AV22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}] +set_property -dict {LOC AT24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}] +set_property -dict {LOC AW24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}] +set_property -dict {LOC AY21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}] +set_property -dict {LOC AT22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}] +set_property -dict {LOC AP23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}] +set_property -dict {LOC BA21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}] +set_property -dict {LOC AU24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}] +set_property -dict {LOC AL22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}] +set_property -dict {LOC BB22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}] +set_property -dict {LOC BB25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}] +set_property -dict {LOC AW21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}] +set_property -dict {LOC AW23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}] +set_property -dict {LOC BA22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}] +set_property -dict {LOC BB23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}] +set_property -dict {LOC BA24 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t}] +set_property -dict {LOC BB24 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c}] +set_property -dict {LOC AL21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke}] +set_property -dict {LOC BA25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n}] +set_property -dict {LOC AR21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}] +set_property -dict {LOC AT21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt}] +set_property -dict {LOC AK17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}] +set_property -dict {LOC BB20 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_reset_n}] +set_property -dict {LOC AV20 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_alert_n}] +set_property -dict {LOC AU20 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_ten}] + +set_property -dict {LOC AL17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}] +set_property -dict {LOC AJ16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}] +set_property -dict {LOC AK19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}] +set_property -dict {LOC AK16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}] +set_property -dict {LOC AL19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}] +set_property -dict {LOC AH16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}] +set_property -dict {LOC AM17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}] +set_property -dict {LOC AH17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}] +set_property -dict {LOC AL24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}] +set_property -dict {LOC AH21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}] +set_property -dict {LOC AK24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}] +set_property -dict {LOC AJ24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}] +set_property -dict {LOC AK21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}] +set_property -dict {LOC AH22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}] +set_property -dict {LOC AJ21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}] +set_property -dict {LOC AJ23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}] +set_property -dict {LOC BA14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}] +set_property -dict {LOC BB13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}] +set_property -dict {LOC AY13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}] +set_property -dict {LOC BB14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}] +set_property -dict {LOC AY14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}] +set_property -dict {LOC BB15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}] +set_property -dict {LOC BA15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}] +set_property -dict {LOC BB12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}] +set_property -dict {LOC AT15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}] +set_property -dict {LOC AW13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}] +set_property -dict {LOC AU15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}] +set_property -dict {LOC AU13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}] +set_property -dict {LOC AT16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}] +set_property -dict {LOC AW14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}] +set_property -dict {LOC AU14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}] +set_property -dict {LOC AV13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}] +set_property -dict {LOC BB18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}] +set_property -dict {LOC AY18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}] +set_property -dict {LOC BA19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}] +set_property -dict {LOC AW19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}] +set_property -dict {LOC BB17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}] +set_property -dict {LOC AW18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}] +set_property -dict {LOC BB19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}] +set_property -dict {LOC AY19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}] +set_property -dict {LOC AV17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}] +set_property -dict {LOC AT19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}] +set_property -dict {LOC AU18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}] +set_property -dict {LOC AU19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}] +set_property -dict {LOC AU17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}] +set_property -dict {LOC AR19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}] +set_property -dict {LOC AV18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}] +set_property -dict {LOC AR18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}] +set_property -dict {LOC AN16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}] +set_property -dict {LOC AM20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}] +set_property -dict {LOC AN18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}] +set_property -dict {LOC AN20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}] +set_property -dict {LOC AP16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}] +set_property -dict {LOC AL20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}] +set_property -dict {LOC AN17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}] +set_property -dict {LOC AP20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}] +set_property -dict {LOC AR23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}] +set_property -dict {LOC AM23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}] +set_property -dict {LOC AR24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}] +set_property -dict {LOC AM24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}] +set_property -dict {LOC AR22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}] +set_property -dict {LOC AN22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}] +set_property -dict {LOC AP24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}] +set_property -dict {LOC AM22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}] +set_property -dict {LOC AM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}] +set_property -dict {LOC AR12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}] +set_property -dict {LOC AP15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}] +set_property -dict {LOC AR13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}] +set_property -dict {LOC AM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}] +set_property -dict {LOC AT12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}] +set_property -dict {LOC AP14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}] +set_property -dict {LOC AP13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}] +set_property -dict {LOC AJ19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}] +set_property -dict {LOC AJ18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}] +set_property -dict {LOC AH20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}] +set_property -dict {LOC AJ20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}] +set_property -dict {LOC AY12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}] +set_property -dict {LOC BA12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}] +set_property -dict {LOC AU12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}] +set_property -dict {LOC AV12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}] +set_property -dict {LOC AY17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}] +set_property -dict {LOC BA17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}] +set_property -dict {LOC AR17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}] +set_property -dict {LOC AT17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}] +set_property -dict {LOC AM19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}] +set_property -dict {LOC AM18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}] +set_property -dict {LOC AN21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}] +set_property -dict {LOC AP21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}] +set_property -dict {LOC AN13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}] +set_property -dict {LOC AN12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}] +set_property -dict {LOC AK18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[0]}] +set_property -dict {LOC AK22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[1]}] +set_property -dict {LOC AY16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[2]}] +set_property -dict {LOC AV15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[3]}] +set_property -dict {LOC BA20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[4]}] +set_property -dict {LOC AT20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[5]}] +set_property -dict {LOC AP19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[6]}] +set_property -dict {LOC AN23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[7]}] +set_property -dict {LOC AR14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[8]}] + +# DDR4 C1 +# 5x K4A8G165WB-BCTD / MT40A512M16HA-075E +set_property -dict {LOC AT30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}] +set_property -dict {LOC AR29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}] +set_property -dict {LOC AP30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}] +set_property -dict {LOC AR32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}] +set_property -dict {LOC AU30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}] +set_property -dict {LOC AP28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}] +set_property -dict {LOC AW31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}] +set_property -dict {LOC AM30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}] +set_property -dict {LOC AR33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}] +set_property -dict {LOC AN28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}] +set_property -dict {LOC AV31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}] +set_property -dict {LOC AP29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}] +set_property -dict {LOC AR31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}] +set_property -dict {LOC AN30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}] +set_property -dict {LOC AN32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}] +set_property -dict {LOC AV32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}] +set_property -dict {LOC BA34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}] +set_property -dict {LOC AP34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}] +set_property -dict {LOC AT31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}] +set_property -dict {LOC AP33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}] +set_property -dict {LOC AV33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}] +set_property -dict {LOC AT34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t}] +set_property -dict {LOC AU34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c}] +set_property -dict {LOC AP31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke}] +set_property -dict {LOC AR34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n}] +set_property -dict {LOC AU33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}] +set_property -dict {LOC AN31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt}] +set_property -dict {LOC AW26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}] +set_property -dict {LOC AV25 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}] +set_property -dict {LOC BA31 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_alert_n}] +set_property -dict {LOC AT27 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_ten}] + +set_property -dict {LOC AV41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] +set_property -dict {LOC BB39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] +set_property -dict {LOC AY42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] +set_property -dict {LOC BA40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] +set_property -dict {LOC AV42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] +set_property -dict {LOC BA39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] +set_property -dict {LOC AW41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] +set_property -dict {LOC BB40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] +set_property -dict {LOC AV38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] +set_property -dict {LOC BA37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] +set_property -dict {LOC AW38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] +set_property -dict {LOC AV37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] +set_property -dict {LOC AU37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] +set_property -dict {LOC AW36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] +set_property -dict {LOC BB38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] +set_property -dict {LOC AV36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] +set_property -dict {LOC BB34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] +set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] +set_property -dict {LOC BB33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] +set_property -dict {LOC AY33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] +set_property -dict {LOC BA36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] +set_property -dict {LOC AW34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] +set_property -dict {LOC BB37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] +set_property -dict {LOC AW33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] +set_property -dict {LOC BA32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] +set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] +set_property -dict {LOC BB29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] +set_property -dict {LOC AY29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] +set_property -dict {LOC BB32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] +set_property -dict {LOC AW30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] +set_property -dict {LOC BB28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] +set_property -dict {LOC AW29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] +set_property -dict {LOC AY28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] +set_property -dict {LOC AV26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] +set_property -dict {LOC BA26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] +set_property -dict {LOC AV27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] +set_property -dict {LOC AW28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] +set_property -dict {LOC AV28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] +set_property -dict {LOC AY26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] +set_property -dict {LOC AY27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] +set_property -dict {LOC AU27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] +set_property -dict {LOC AP25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] +set_property -dict {LOC AR27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] +set_property -dict {LOC AP26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] +set_property -dict {LOC AU28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] +set_property -dict {LOC AN25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] +set_property -dict {LOC AR26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] +set_property -dict {LOC AR28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] +set_property -dict {LOC AM29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] +set_property -dict {LOC AK30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] +set_property -dict {LOC AL29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] +set_property -dict {LOC AH30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] +set_property -dict {LOC AM28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] +set_property -dict {LOC AJ30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] +set_property -dict {LOC AK29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] +set_property -dict {LOC AJ29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] +set_property -dict {LOC AL25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] +set_property -dict {LOC AH26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] +set_property -dict {LOC AL27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] +set_property -dict {LOC AJ25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] +set_property -dict {LOC AM27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] +set_property -dict {LOC AH27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] +set_property -dict {LOC AM25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] +set_property -dict {LOC AJ26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] +set_property -dict {LOC AK13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}] +set_property -dict {LOC AJ13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}] +set_property -dict {LOC AL14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}] +set_property -dict {LOC AH13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}] +set_property -dict {LOC AK14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}] +set_property -dict {LOC AH12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}] +set_property -dict {LOC AL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}] +set_property -dict {LOC AK12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}] +set_property -dict {LOC AY41 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] +set_property -dict {LOC BA41 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] +set_property -dict {LOC AY37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] +set_property -dict {LOC AY38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] +set_property -dict {LOC BA35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] +set_property -dict {LOC BB35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] +set_property -dict {LOC BA30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] +set_property -dict {LOC BB30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] +set_property -dict {LOC BA27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] +set_property -dict {LOC BB27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] +set_property -dict {LOC AT29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] +set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] +set_property -dict {LOC AJ28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] +set_property -dict {LOC AK28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] +set_property -dict {LOC AN26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] +set_property -dict {LOC AN27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] +set_property -dict {LOC AJ15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}] +set_property -dict {LOC AJ14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}] +set_property -dict {LOC AW39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[0]}] +set_property -dict {LOC AU35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[1]}] +set_property -dict {LOC AY34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[2]}] +set_property -dict {LOC AY31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[3]}] +set_property -dict {LOC AU25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[4]}] +set_property -dict {LOC AT26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[5]}] +set_property -dict {LOC AL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[6]}] +set_property -dict {LOC AK26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[7]}] +set_property -dict {LOC AM13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[8]}] + +# DDR4 C2 +# 5x K4A8G165WB-BCTD / MT40A512M16HA-075E +set_property -dict {LOC J30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[0]}] +set_property -dict {LOC J29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[1]}] +set_property -dict {LOC G32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[2]}] +set_property -dict {LOC F31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[3]}] +set_property -dict {LOC H29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[4]}] +set_property -dict {LOC F28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[5]}] +set_property -dict {LOC J28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[6]}] +set_property -dict {LOC H32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[7]}] +set_property -dict {LOC L29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[8]}] +set_property -dict {LOC H31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[9]}] +set_property -dict {LOC F30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[10]}] +set_property -dict {LOC J32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[11]}] +set_property -dict {LOC B28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[12]}] +set_property -dict {LOC K32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[13]}] +set_property -dict {LOC F29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[14]}] +set_property -dict {LOC D29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[15]}] +set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[16]}] +set_property -dict {LOC G31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[0]}] +set_property -dict {LOC H30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[1]}] +set_property -dict {LOC E31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[0]}] +set_property -dict {LOC D30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[1]}] +set_property -dict {LOC E32 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t}] +set_property -dict {LOC D32 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c}] +set_property -dict {LOC E30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke}] +set_property -dict {LOC C31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n}] +set_property -dict {LOC E28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_act_n}] +set_property -dict {LOC D28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt}] +set_property -dict {LOC J18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_par}] +set_property -dict {LOC L19 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_reset_n}] +set_property -dict {LOC F19 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_alert_n}] +set_property -dict {LOC E15 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_ten}] + +set_property -dict {LOC G38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[0]}] +set_property -dict {LOC D42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[1]}] +set_property -dict {LOC F39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[2]}] +set_property -dict {LOC G41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[3]}] +set_property -dict {LOC F38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[4]}] +set_property -dict {LOC G42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[5]}] +set_property -dict {LOC G39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[6]}] +set_property -dict {LOC E42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[7]}] +set_property -dict {LOC C39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[8]}] +set_property -dict {LOC B41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[9]}] +set_property -dict {LOC B39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[10]}] +set_property -dict {LOC C41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[11]}] +set_property -dict {LOC B38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[12]}] +set_property -dict {LOC C42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[13]}] +set_property -dict {LOC A38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[14]}] +set_property -dict {LOC C40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[15]}] +set_property -dict {LOC AT36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[16]}] +set_property -dict {LOC AR38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[17]}] +set_property -dict {LOC AP36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[18]}] +set_property -dict {LOC AR37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[19]}] +set_property -dict {LOC AR36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[20]}] +set_property -dict {LOC AP39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[21]}] +set_property -dict {LOC AP37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[22]}] +set_property -dict {LOC AP40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[23]}] +set_property -dict {LOC N24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[24]}] +set_property -dict {LOC M26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[25]}] +set_property -dict {LOC N26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[26]}] +set_property -dict {LOC L25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[27]}] +set_property -dict {LOC N25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[28]}] +set_property -dict {LOC L26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[29]}] +set_property -dict {LOC M23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[30]}] +set_property -dict {LOC L23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[31]}] +set_property -dict {LOC AP41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[32]}] +set_property -dict {LOC AT41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[33]}] +set_property -dict {LOC AP42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[34]}] +set_property -dict {LOC AU40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[35]}] +set_property -dict {LOC AR41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[36]}] +set_property -dict {LOC AV40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[37]}] +set_property -dict {LOC AR42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[38]}] +set_property -dict {LOC AT40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[39]}] +set_property -dict {LOC K28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[40]}] +set_property -dict {LOC K31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[41]}] +set_property -dict {LOC P28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[42]}] +set_property -dict {LOC N28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[43]}] +set_property -dict {LOC M27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[44]}] +set_property -dict {LOC L31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[45]}] +set_property -dict {LOC N27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[46]}] +set_property -dict {LOC L28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[47]}] +set_property -dict {LOC D34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[48]}] +set_property -dict {LOC A34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[49]}] +set_property -dict {LOC C34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[50]}] +set_property -dict {LOC A35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[51]}] +set_property -dict {LOC C36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[52]}] +set_property -dict {LOC A36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[53]}] +set_property -dict {LOC C37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[54]}] +set_property -dict {LOC B34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[55]}] +set_property -dict {LOC B29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[56]}] +set_property -dict {LOC B33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[57]}] +set_property -dict {LOC A29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[58]}] +set_property -dict {LOC B32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[59]}] +set_property -dict {LOC A28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[60]}] +set_property -dict {LOC A33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[61]}] +set_property -dict {LOC C29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[62]}] +set_property -dict {LOC B31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[63]}] +set_property -dict {LOC E37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[64]}] +set_property -dict {LOC E36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[65]}] +set_property -dict {LOC F36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[66]}] +set_property -dict {LOC D37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[67]}] +set_property -dict {LOC E38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[68]}] +set_property -dict {LOC F33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[69]}] +set_property -dict {LOC G36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[70]}] +set_property -dict {LOC E33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[71]}] +set_property -dict {LOC F41 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[0]}] +set_property -dict {LOC E41 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[0]}] +set_property -dict {LOC A39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[1]}] +set_property -dict {LOC A40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[1]}] +set_property -dict {LOC AT37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[2]}] +set_property -dict {LOC AU38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[2]}] +set_property -dict {LOC M24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[3]}] +set_property -dict {LOC L24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[3]}] +set_property -dict {LOC AT42 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[4]}] +set_property -dict {LOC AU42 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[4]}] +set_property -dict {LOC L30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[5]}] +set_property -dict {LOC K30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[5]}] +set_property -dict {LOC B36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[6]}] +set_property -dict {LOC B37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[6]}] +set_property -dict {LOC A30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[7]}] +set_property -dict {LOC A31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[7]}] +set_property -dict {LOC F35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[8]}] +set_property -dict {LOC E35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[8]}] +set_property -dict {LOC G40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[0]}] +set_property -dict {LOC D39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[1]}] +set_property -dict {LOC AP38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[2]}] +set_property -dict {LOC P23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[3]}] +set_property -dict {LOC AT39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[4]}] +set_property -dict {LOC M28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[5]}] +set_property -dict {LOC D35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[6]}] +set_property -dict {LOC C30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[7]}] +set_property -dict {LOC G34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[8]}] + +# DDR4 C3 +# 5x K4A8G165WB-BCTD / MT40A512M16HA-075E +set_property -dict {LOC F23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[0]}] +set_property -dict {LOC G23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[1]}] +set_property -dict {LOC H24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[2]}] +set_property -dict {LOC F25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[3]}] +set_property -dict {LOC F26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[4]}] +set_property -dict {LOC F24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[5]}] +set_property -dict {LOC K26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[6]}] +set_property -dict {LOC G27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[7]}] +set_property -dict {LOC J27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[8]}] +set_property -dict {LOC G24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[9]}] +set_property -dict {LOC E25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[10]}] +set_property -dict {LOC H27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[11]}] +set_property -dict {LOC E23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[12]}] +set_property -dict {LOC G26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[13]}] +set_property -dict {LOC J23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[14]}] +set_property -dict {LOC D23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[15]}] +set_property -dict {LOC B27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[16]}] +set_property -dict {LOC J25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[0]}] +set_property -dict {LOC K25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[1]}] +set_property -dict {LOC J24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[0]}] +set_property -dict {LOC D25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[1]}] +set_property -dict {LOC E27 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t}] +set_property -dict {LOC D27 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c}] +set_property -dict {LOC E26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke}] +set_property -dict {LOC H25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n}] +set_property -dict {LOC D24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_act_n}] +set_property -dict {LOC B22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt}] +set_property -dict {LOC A14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_par}] +set_property -dict {LOC M16 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c3_reset_n}] +set_property -dict {LOC F20 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c3_alert_n}] +set_property -dict {LOC J17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c3_ten}] + +set_property -dict {LOC E18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[0]}] +set_property -dict {LOC G17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[1]}] +set_property -dict {LOC F16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[2]}] +set_property -dict {LOC G16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[3]}] +set_property -dict {LOC E16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[4]}] +set_property -dict {LOC H17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[5]}] +set_property -dict {LOC E17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[6]}] +set_property -dict {LOC F18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[7]}] +set_property -dict {LOC N12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[8]}] +set_property -dict {LOC P15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[9]}] +set_property -dict {LOC M13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[10]}] +set_property -dict {LOC P12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[11]}] +set_property -dict {LOC M12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[12]}] +set_property -dict {LOC N15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[13]}] +set_property -dict {LOC M14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[14]}] +set_property -dict {LOC P13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[15]}] +set_property -dict {LOC C17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[16]}] +set_property -dict {LOC C15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[17]}] +set_property -dict {LOC A16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[18]}] +set_property -dict {LOC A15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[19]}] +set_property -dict {LOC B17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[20]}] +set_property -dict {LOC D15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[21]}] +set_property -dict {LOC D18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[22]}] +set_property -dict {LOC D17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[23]}] +set_property -dict {LOC J14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[24]}] +set_property -dict {LOC L16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[25]}] +set_property -dict {LOC H15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[26]}] +set_property -dict {LOC H14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[27]}] +set_property -dict {LOC J15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[28]}] +set_property -dict {LOC K16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[29]}] +set_property -dict {LOC K15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[30]}] +set_property -dict {LOC H16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[31]}] +set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[32]}] +set_property -dict {LOC H19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[33]}] +set_property -dict {LOC J20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[34]}] +set_property -dict {LOC J19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[35]}] +set_property -dict {LOC K20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[36]}] +set_property -dict {LOC K18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[37]}] +set_property -dict {LOC H20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[38]}] +set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[39]}] +set_property -dict {LOC D20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[40]}] +set_property -dict {LOC B19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[41]}] +set_property -dict {LOC A21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[42]}] +set_property -dict {LOC A19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[43]}] +set_property -dict {LOC B21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[44]}] +set_property -dict {LOC D19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[45]}] +set_property -dict {LOC C21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[46]}] +set_property -dict {LOC A20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[47]}] +set_property -dict {LOC N19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[48]}] +set_property -dict {LOC N22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[49]}] +set_property -dict {LOC P20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[50]}] +set_property -dict {LOC N21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[51]}] +set_property -dict {LOC P19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[52]}] +set_property -dict {LOC N20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[53]}] +set_property -dict {LOC P18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[54]}] +set_property -dict {LOC P22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[55]}] +set_property -dict {LOC C25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[56]}] +set_property -dict {LOC A23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[57]}] +set_property -dict {LOC B26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[58]}] +set_property -dict {LOC A26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[59]}] +set_property -dict {LOC C26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[60]}] +set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[61]}] +set_property -dict {LOC A24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[62]}] +set_property -dict {LOC A25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[63]}] +set_property -dict {LOC H22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[64]}] +set_property -dict {LOC E21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[65]}] +set_property -dict {LOC G21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[66]}] +set_property -dict {LOC E22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[67]}] +set_property -dict {LOC H21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[68]}] +set_property -dict {LOC E20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[69]}] +set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[70]}] +set_property -dict {LOC D22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[71]}] +set_property -dict {LOC G14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[0]}] +set_property -dict {LOC F14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[0]}] +set_property -dict {LOC P14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[1]}] +set_property -dict {LOC N14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[1]}] +set_property -dict {LOC C16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[2]}] +set_property -dict {LOC B16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[2]}] +set_property -dict {LOC L15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[3]}] +set_property -dict {LOC L14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[3]}] +set_property -dict {LOC K22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[4]}] +set_property -dict {LOC J22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[4]}] +set_property -dict {LOC C20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[5]}] +set_property -dict {LOC C19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[5]}] +set_property -dict {LOC M21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[6]}] +set_property -dict {LOC L21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[6]}] +set_property -dict {LOC B23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[7]}] +set_property -dict {LOC B24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[7]}] +set_property -dict {LOC G19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[8]}] +set_property -dict {LOC G18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[8]}] +set_property -dict {LOC F15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dm_dbi_n[0]}] +set_property -dict {LOC N16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dm_dbi_n[1]}] +set_property -dict {LOC B14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dm_dbi_n[2]}] +set_property -dict {LOC K17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dm_dbi_n[3]}] +set_property -dict {LOC L20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dm_dbi_n[4]}] +set_property -dict {LOC B18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dm_dbi_n[5]}] +set_property -dict {LOC M19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dm_dbi_n[6]}] +set_property -dict {LOC C27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dm_dbi_n[7]}] +set_property -dict {LOC F21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dm_dbi_n[8]}] diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile index 46eb1b6d5..7cae09d8c 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile @@ -121,6 +121,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/cmac_usplus_0.tcl IP_TCL_FILES += ip/cmac_usplus_1.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl b/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl index 5d7e274b1..f8580e72f 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga/config.tcl @@ -137,6 +137,12 @@ dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "131072" dict set params RX_RAM_SIZE "131072" +# RAM configuration +dict set params DDR_CH "4" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" + # Application block configuration dict set params APP_ID "32'h00000000" dict set params APP_ENABLE "0" @@ -187,6 +193,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile index 0043f30b3..c8f5154c0 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile @@ -122,6 +122,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/cmac_usplus_0.tcl IP_TCL_FILES += ip/cmac_usplus_1.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/config.tcl b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/config.tcl index 92fd6b700..8c06793c5 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/config.tcl @@ -137,6 +137,12 @@ dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "131072" dict set params RX_RAM_SIZE "131072" +# RAM configuration +dict set params DDR_CH "4" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" + # Application block configuration dict set params APP_ID "32'h12348001" dict set params APP_ENABLE "1" @@ -187,6 +193,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile index 9c5672f56..f39bba904 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile @@ -125,6 +125,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/cmac_usplus_0.tcl IP_TCL_FILES += ip/cmac_usplus_1.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/config.tcl b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/config.tcl index 944fe8752..8b50c9337 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/config.tcl @@ -137,6 +137,12 @@ dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "131072" dict set params RX_RAM_SIZE "131072" +# RAM configuration +dict set params DDR_CH "4" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" + # Application block configuration dict set params APP_ID "32'h12340001" dict set params APP_ENABLE "1" @@ -187,6 +193,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile index fd3a2ddba..5b64e0cb4 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile @@ -123,6 +123,7 @@ XDC_FILES += ../../../common/syn/vivado/mqnic_ptp_clock.tcl IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/cmac_usplus_0.tcl IP_TCL_FILES += ip/cmac_usplus_1.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl index 5b4d55278..176dec750 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/config.tcl @@ -137,6 +137,12 @@ dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "131072" dict set params RX_RAM_SIZE "131072" +# RAM configuration +dict set params DDR_CH "4" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" + # Application block configuration dict set params APP_ID "32'h00000000" dict set params APP_ENABLE "0" @@ -187,6 +193,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/fb2CG/fpga_100g/ip/ddr4_0.tcl b/fpga/mqnic/fb2CG/fpga_100g/ip/ddr4_0.tcl new file mode 100644 index 000000000..ac9925b31 --- /dev/null +++ b/fpga/mqnic/fb2CG/fpga_100g/ip/ddr4_0.tcl @@ -0,0 +1,20 @@ + +create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 + +set_property -dict [list \ + CONFIG.System_Clock {No_Buffer} \ + CONFIG.C0.DDR4_AxiSelection {true} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_AxiIDWidth {8} \ + CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ + CONFIG.C0.DDR4_TimePeriod {750} \ + CONFIG.C0.DDR4_InputClockPeriod {3750} \ + CONFIG.C0.DDR4_MemoryType {Components} \ + CONFIG.C0.DDR4_MemoryPart {MT40A512M16HA-075E} \ + CONFIG.C0.DDR4_DataWidth {72} \ + CONFIG.C0.DDR4_DataMask {NO_DM_NO_DBI} \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_CasLatency {18} \ + CONFIG.C0.DDR4_CasWriteLatency {14} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} +] [get_ips ddr4_0] diff --git a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v index 7d23de2e3..1efe7b990 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v +++ b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v @@ -109,6 +109,15 @@ module fpga # parameter TX_RAM_SIZE = 131072, parameter RX_RAM_SIZE = 131072, + // RAM configuration + parameter DDR_CH = 4, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 32, + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -177,6 +186,10 @@ module fpga # * Clock: 100MHz */ input wire init_clk, + input wire clk_ddr4_refclk1_p, + input wire clk_ddr4_refclk1_n, + input wire clk_ddr4_refclk2_p, + input wire clk_ddr4_refclk2_n, /* * GPIO @@ -268,7 +281,82 @@ module fpga # output wire qsfp_1_lp_mode, input wire qsfp_1_intr_n, inout wire qsfp_1_i2c_scl, - inout wire qsfp_1_i2c_sda + inout wire qsfp_1_i2c_sda, + + /* + * DDR4 + */ + output wire [16:0] ddr4_c0_adr, + output wire [1:0] ddr4_c0_ba, + output wire [1:0] ddr4_c0_bg, + output wire ddr4_c0_ck_t, + output wire ddr4_c0_ck_c, + output wire ddr4_c0_cke, + output wire ddr4_c0_cs_n, + output wire ddr4_c0_act_n, + output wire ddr4_c0_odt, + output wire ddr4_c0_par, + input wire ddr4_c0_alert_n, + output wire ddr4_c0_reset_n, + output wire ddr4_c0_ten, + inout wire [71:0] ddr4_c0_dq, + inout wire [8:0] ddr4_c0_dqs_t, + inout wire [8:0] ddr4_c0_dqs_c, + inout wire [8:0] ddr4_c0_dm_dbi_n, + + output wire [16:0] ddr4_c1_adr, + output wire [1:0] ddr4_c1_ba, + output wire [1:0] ddr4_c1_bg, + output wire ddr4_c1_ck_t, + output wire ddr4_c1_ck_c, + output wire ddr4_c1_cke, + output wire ddr4_c1_cs_n, + output wire ddr4_c1_act_n, + output wire ddr4_c1_odt, + output wire ddr4_c1_par, + input wire ddr4_c1_alert_n, + output wire ddr4_c1_reset_n, + output wire ddr4_c1_ten, + inout wire [71:0] ddr4_c1_dq, + inout wire [8:0] ddr4_c1_dqs_t, + inout wire [8:0] ddr4_c1_dqs_c, + inout wire [8:0] ddr4_c1_dm_dbi_n, + + output wire [16:0] ddr4_c2_adr, + output wire [1:0] ddr4_c2_ba, + output wire [1:0] ddr4_c2_bg, + output wire ddr4_c2_ck_t, + output wire ddr4_c2_ck_c, + output wire ddr4_c2_cke, + output wire ddr4_c2_cs_n, + output wire ddr4_c2_act_n, + output wire ddr4_c2_odt, + output wire ddr4_c2_par, + input wire ddr4_c2_alert_n, + output wire ddr4_c2_reset_n, + output wire ddr4_c2_ten, + inout wire [71:0] ddr4_c2_dq, + inout wire [8:0] ddr4_c2_dqs_t, + inout wire [8:0] ddr4_c2_dqs_c, + inout wire [8:0] ddr4_c2_dm_dbi_n, + + output wire [16:0] ddr4_c3_adr, + output wire [1:0] ddr4_c3_ba, + output wire [1:0] ddr4_c3_bg, + output wire ddr4_c3_ck_t, + output wire ddr4_c3_ck_c, + output wire ddr4_c3_cke, + output wire ddr4_c3_cs_n, + output wire ddr4_c3_act_n, + output wire ddr4_c3_odt, + output wire ddr4_c3_par, + input wire ddr4_c3_alert_n, + output wire ddr4_c3_reset_n, + output wire ddr4_c3_ten, + inout wire [71:0] ddr4_c3_dq, + inout wire [8:0] ddr4_c3_dqs_t, + inout wire [8:0] ddr4_c3_dqs_c, + inout wire [8:0] ddr4_c3_dm_dbi_n ); // PTP configuration @@ -281,6 +369,9 @@ parameter PTP_SEPARATE_RX_CLOCK = 1; // Interface configuration parameter TX_TAG_WIDTH = 16; +// RAM configuration +parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8); + // Ethernet interface configuration parameter AXIS_ETH_DATA_WIDTH = 512; parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8; @@ -1772,6 +1863,565 @@ assign led_green[3:1] = 0; assign led_green[4] = qsfp_1_rx_status; assign led_green[7:5] = 0; +// DDR4 +wire [DDR_CH-1:0] ddr_clk; +wire [DDR_CH-1:0] ddr_rst; + +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr; +wire [DDR_CH*8-1:0] m_axi_ddr_awlen; +wire [DDR_CH*3-1:0] m_axi_ddr_awsize; +wire [DDR_CH*2-1:0] m_axi_ddr_awburst; +wire [DDR_CH-1:0] m_axi_ddr_awlock; +wire [DDR_CH*4-1:0] m_axi_ddr_awcache; +wire [DDR_CH*3-1:0] m_axi_ddr_awprot; +wire [DDR_CH*4-1:0] m_axi_ddr_awqos; +wire [DDR_CH-1:0] m_axi_ddr_awvalid; +wire [DDR_CH-1:0] m_axi_ddr_awready; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata; +wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb; +wire [DDR_CH-1:0] m_axi_ddr_wlast; +wire [DDR_CH-1:0] m_axi_ddr_wvalid; +wire [DDR_CH-1:0] m_axi_ddr_wready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid; +wire [DDR_CH*2-1:0] m_axi_ddr_bresp; +wire [DDR_CH-1:0] m_axi_ddr_bvalid; +wire [DDR_CH-1:0] m_axi_ddr_bready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr; +wire [DDR_CH*8-1:0] m_axi_ddr_arlen; +wire [DDR_CH*3-1:0] m_axi_ddr_arsize; +wire [DDR_CH*2-1:0] m_axi_ddr_arburst; +wire [DDR_CH-1:0] m_axi_ddr_arlock; +wire [DDR_CH*4-1:0] m_axi_ddr_arcache; +wire [DDR_CH*3-1:0] m_axi_ddr_arprot; +wire [DDR_CH*4-1:0] m_axi_ddr_arqos; +wire [DDR_CH-1:0] m_axi_ddr_arvalid; +wire [DDR_CH-1:0] m_axi_ddr_arready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata; +wire [DDR_CH*2-1:0] m_axi_ddr_rresp; +wire [DDR_CH-1:0] m_axi_ddr_rlast; +wire [DDR_CH-1:0] m_axi_ddr_rvalid; +wire [DDR_CH-1:0] m_axi_ddr_rready; + +wire [DDR_CH-1:0] ddr_status; + +generate + +wire clk_ddr4_refclk1_ibufg; +wire clk_ddr4_refclk1; + +IBUFGDS #( + .DIFF_TERM("FALSE"), + .IBUF_LOW_PWR("FALSE") +) +clk_ddr4_refclk1_ibufg_inst ( + .O (clk_ddr4_refclk1_ibufg), + .I (clk_ddr4_refclk1_p), + .IB (clk_ddr4_refclk1_n) +); + +BUFG +clk_ddr4_refclk1_bufg_inst ( + .I(clk_ddr4_refclk1_ibufg), + .O(clk_ddr4_refclk1) +); + +if (DDR_ENABLE && DDR_CH > 0) begin + +ddr4_0 ddr4_c0_inst ( + .c0_sys_clk_i(clk_ddr4_refclk1), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[0 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c0_adr), + .c0_ddr4_ba(ddr4_c0_ba), + .c0_ddr4_cke(ddr4_c0_cke), + .c0_ddr4_cs_n(ddr4_c0_cs_n), + .c0_ddr4_dq(ddr4_c0_dq), + .c0_ddr4_dqs_t(ddr4_c0_dqs_t), + .c0_ddr4_dqs_c(ddr4_c0_dqs_c), + .c0_ddr4_dm_dbi_n(ddr4_c0_dm_dbi_n), + .c0_ddr4_odt(ddr4_c0_odt), + .c0_ddr4_bg(ddr4_c0_bg), + .c0_ddr4_reset_n(ddr4_c0_reset_n), + .c0_ddr4_act_n(ddr4_c0_act_n), + .c0_ddr4_ck_t(ddr4_c0_ck_t), + .c0_ddr4_ck_c(ddr4_c0_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[0 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[0 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c0_adr = {17{1'bz}}; +assign ddr4_c0_ba = {2{1'bz}}; +assign ddr4_c0_bg = {2{1'bz}}; +assign ddr4_c0_cke = 1'bz; +assign ddr4_c0_cs_n = 1'bz; +assign ddr4_c0_act_n = 1'bz; +assign ddr4_c0_odt = 1'bz; +assign ddr4_c0_reset_n = 1'b0; +assign ddr4_c0_dq = {72{1'bz}}; +assign ddr4_c0_dqs_t = {9{1'bz}}; +assign ddr4_c0_dqs_c = {9{1'bz}}; +assign ddr4_c0_dm_dbi_n = {9{1'bz}}; + +OBUFTDS ddr4_c0_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c0_ck_t), + .OB(ddr4_c0_ck_c) +); + +assign ddr_clk = 0; +assign ddr_rst = 0; + +assign m_axi_ddr_awready = 0; +assign m_axi_ddr_wready = 0; +assign m_axi_ddr_bid = 0; +assign m_axi_ddr_bresp = 0; +assign m_axi_ddr_bvalid = 0; +assign m_axi_ddr_arready = 0; +assign m_axi_ddr_rid = 0; +assign m_axi_ddr_rdata = 0; +assign m_axi_ddr_rresp = 0; +assign m_axi_ddr_rlast = 0; +assign m_axi_ddr_rvalid = 0; + +assign ddr_status = 0; + +end + +assign ddr4_c0_par = 1'b0; +assign ddr4_c0_ten = 1'b0; + +if (DDR_ENABLE && DDR_CH > 1) begin + +ddr4_0 ddr4_c1_inst ( + .c0_sys_clk_i(clk_ddr4_refclk1), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[1 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c1_adr), + .c0_ddr4_ba(ddr4_c1_ba), + .c0_ddr4_cke(ddr4_c1_cke), + .c0_ddr4_cs_n(ddr4_c1_cs_n), + .c0_ddr4_dq(ddr4_c1_dq), + .c0_ddr4_dqs_t(ddr4_c1_dqs_t), + .c0_ddr4_dqs_c(ddr4_c1_dqs_c), + .c0_ddr4_dm_dbi_n(ddr4_c1_dm_dbi_n), + .c0_ddr4_odt(ddr4_c1_odt), + .c0_ddr4_bg(ddr4_c1_bg), + .c0_ddr4_reset_n(ddr4_c1_reset_n), + .c0_ddr4_act_n(ddr4_c1_act_n), + .c0_ddr4_ck_t(ddr4_c1_ck_t), + .c0_ddr4_ck_c(ddr4_c1_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[1 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[1 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[1 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[1*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[1*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[1*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[1 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[1*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[1*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[1*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[1 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[1 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[1*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[1 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[1 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[1 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[1 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[1*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[1 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[1*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[1*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[1*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[1 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[1*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[1*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[1*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[1 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[1 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[1 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[1 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[1 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[1*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c1_adr = {17{1'bz}}; +assign ddr4_c1_ba = {2{1'bz}}; +assign ddr4_c1_bg = {2{1'bz}}; +assign ddr4_c1_cke = 1'bz; +assign ddr4_c1_cs_n = 1'bz; +assign ddr4_c1_act_n = 1'bz; +assign ddr4_c1_odt = 1'bz; +assign ddr4_c1_reset_n = 1'b0; +assign ddr4_c1_dq = {72{1'bz}}; +assign ddr4_c1_dqs_t = {9{1'bz}}; +assign ddr4_c1_dqs_c = {9{1'bz}}; +assign ddr4_c1_dm_dbi_n = {9{1'bz}}; + +OBUFTDS ddr4_c1_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c1_ck_t), + .OB(ddr4_c1_ck_c) +); + +end + +assign ddr4_c1_par = 1'b0; +assign ddr4_c1_ten = 1'b0; + +wire clk_ddr4_refclk2_ibufg; +wire clk_ddr4_refclk2; + +IBUFGDS #( + .DIFF_TERM("FALSE"), + .IBUF_LOW_PWR("FALSE") +) +clk_ddr4_refclk2_ibufg_inst ( + .O (clk_ddr4_refclk2_ibufg), + .I (clk_ddr4_refclk2_p), + .IB (clk_ddr4_refclk2_n) +); + +BUFG +clk_ddr4_refclk2_bufg_inst ( + .I(clk_ddr4_refclk2_ibufg), + .O(clk_ddr4_refclk2) +); + +if (DDR_ENABLE && DDR_CH > 2) begin + +ddr4_0 ddr4_c2_inst ( + .c0_sys_clk_i(clk_ddr4_refclk2), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[2 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c2_adr), + .c0_ddr4_ba(ddr4_c2_ba), + .c0_ddr4_cke(ddr4_c2_cke), + .c0_ddr4_cs_n(ddr4_c2_cs_n), + .c0_ddr4_dq(ddr4_c2_dq), + .c0_ddr4_dqs_t(ddr4_c2_dqs_t), + .c0_ddr4_dqs_c(ddr4_c2_dqs_c), + .c0_ddr4_dm_dbi_n(ddr4_c2_dm_dbi_n), + .c0_ddr4_odt(ddr4_c2_odt), + .c0_ddr4_bg(ddr4_c2_bg), + .c0_ddr4_reset_n(ddr4_c2_reset_n), + .c0_ddr4_act_n(ddr4_c2_act_n), + .c0_ddr4_ck_t(ddr4_c2_ck_t), + .c0_ddr4_ck_c(ddr4_c2_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[2 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[2 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[2 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[2*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[2*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[2*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[2 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[2*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[2*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[2*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[2 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[2 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[2*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[2 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[2 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[2 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[2 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[2*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[2 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[2*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[2*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[2*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[2 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[2*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[2*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[2*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[2 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[2 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[2 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[2 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[2 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[2*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c2_adr = {17{1'bz}}; +assign ddr4_c2_ba = {2{1'bz}}; +assign ddr4_c2_bg = {2{1'bz}}; +assign ddr4_c2_cke = 1'bz; +assign ddr4_c2_cs_n = 1'bz; +assign ddr4_c2_act_n = 1'bz; +assign ddr4_c2_odt = 1'bz; +assign ddr4_c2_reset_n = 1'b0; +assign ddr4_c2_dq = {72{1'bz}}; +assign ddr4_c2_dqs_t = {9{1'bz}}; +assign ddr4_c2_dqs_c = {9{1'bz}}; +assign ddr4_c2_dm_dbi_n = {9{1'bz}}; + +OBUFTDS ddr4_c2_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c2_ck_t), + .OB(ddr4_c2_ck_c) +); + +end + +assign ddr4_c2_par = 1'b0; +assign ddr4_c2_ten = 1'b0; + +if (DDR_ENABLE && DDR_CH > 3) begin + +ddr4_0 ddr4_c3_inst ( + .c0_sys_clk_i(clk_ddr4_refclk2), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[3 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c3_adr), + .c0_ddr4_ba(ddr4_c3_ba), + .c0_ddr4_cke(ddr4_c3_cke), + .c0_ddr4_cs_n(ddr4_c3_cs_n), + .c0_ddr4_dq(ddr4_c3_dq), + .c0_ddr4_dqs_t(ddr4_c3_dqs_t), + .c0_ddr4_dqs_c(ddr4_c3_dqs_c), + .c0_ddr4_dm_dbi_n(ddr4_c3_dm_dbi_n), + .c0_ddr4_odt(ddr4_c3_odt), + .c0_ddr4_bg(ddr4_c3_bg), + .c0_ddr4_reset_n(ddr4_c3_reset_n), + .c0_ddr4_act_n(ddr4_c3_act_n), + .c0_ddr4_ck_t(ddr4_c3_ck_t), + .c0_ddr4_ck_c(ddr4_c3_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[3 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[3 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[3 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[3*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[3*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[3*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[3 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[3*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[3*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[3*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[3 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[3 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[3*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[3 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[3 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[3 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[3 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[3*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[3 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[3*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[3*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[3*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[3 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[3*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[3*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[3*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[3 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[3 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[3 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[3 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[3 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[3*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c3_adr = {17{1'bz}}; +assign ddr4_c3_ba = {2{1'bz}}; +assign ddr4_c3_bg = {2{1'bz}}; +assign ddr4_c3_cke = 1'bz; +assign ddr4_c3_cs_n = 1'bz; +assign ddr4_c3_act_n = 1'bz; +assign ddr4_c3_odt = 1'bz; +assign ddr4_c3_reset_n = 1'b0; +assign ddr4_c3_dq = {72{1'bz}}; +assign ddr4_c3_dqs_t = {9{1'bz}}; +assign ddr4_c3_dqs_c = {9{1'bz}}; +assign ddr4_c3_dm_dbi_n = {9{1'bz}}; + +OBUFTDS ddr4_c3_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c3_ck_t), + .OB(ddr4_c3_ck_c) +); + +end + +assign ddr4_c3_par = 1'b0; +assign ddr4_c3_ten = 1'b0; + +endgenerate + fpga_core #( // FW and board IDs .FPGA_ID(FPGA_ID), @@ -1846,6 +2496,16 @@ fpga_core #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -2095,6 +2755,52 @@ core_inst ( .qsfp_1_i2c_sda_o(qsfp_1_i2c_sda_o), .qsfp_1_i2c_sda_t(qsfp_1_i2c_sda_t), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + /* * QSPI flash */ diff --git a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v index c067653c2..7146a3957 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v +++ b/fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v @@ -115,6 +115,16 @@ module fpga_core # parameter TX_RAM_SIZE = 131072, parameter RX_RAM_SIZE = 131072, + // RAM configuration + parameter DDR_CH = 4, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 32, + parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -379,6 +389,52 @@ module fpga_core # output wire qsfp_1_i2c_sda_o, output wire qsfp_1_i2c_sda_t, + /* + * DDR + */ + input wire [DDR_CH-1:0] ddr_clk, + input wire [DDR_CH-1:0] ddr_rst, + + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, + output wire [DDR_CH-1:0] m_axi_ddr_awlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, + output wire [DDR_CH-1:0] m_axi_ddr_awvalid, + input wire [DDR_CH-1:0] m_axi_ddr_awready, + output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, + output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, + output wire [DDR_CH-1:0] m_axi_ddr_wlast, + output wire [DDR_CH-1:0] m_axi_ddr_wvalid, + input wire [DDR_CH-1:0] m_axi_ddr_wready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, + input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, + input wire [DDR_CH-1:0] m_axi_ddr_bvalid, + output wire [DDR_CH-1:0] m_axi_ddr_bready, + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, + output wire [DDR_CH-1:0] m_axi_ddr_arlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, + output wire [DDR_CH-1:0] m_axi_ddr_arvalid, + input wire [DDR_CH-1:0] m_axi_ddr_arready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, + input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, + input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, + input wire [DDR_CH-1:0] m_axi_ddr_rlast, + input wire [DDR_CH-1:0] m_axi_ddr_rvalid, + output wire [DDR_CH-1:0] m_axi_ddr_rready, + + input wire [DDR_CH-1:0] ddr_status, + /* * QSPI flash */ @@ -928,6 +984,25 @@ mqnic_core_pcie_us #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .DDR_GROUP_SIZE(1), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_AWUSER_ENABLE(0), + .AXI_DDR_WUSER_ENABLE(0), + .AXI_DDR_BUSER_ENABLE(0), + .AXI_DDR_ARUSER_ENABLE(0), + .AXI_DDR_RUSER_ENABLE(0), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + .AXI_DDR_FIXED_BURST(0), + .AXI_DDR_WRAP_BURST(1), + .HBM_ENABLE(0), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1205,6 +1280,108 @@ core_inst ( .eth_rx_status(eth_rx_status), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awuser(), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wuser(), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_buser(0), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_aruser(), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_ruser(0), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + + /* + * HBM + */ + .hbm_clk(0), + .hbm_rst(0), + + .m_axi_hbm_awid(), + .m_axi_hbm_awaddr(), + .m_axi_hbm_awlen(), + .m_axi_hbm_awsize(), + .m_axi_hbm_awburst(), + .m_axi_hbm_awlock(), + .m_axi_hbm_awcache(), + .m_axi_hbm_awprot(), + .m_axi_hbm_awqos(), + .m_axi_hbm_awuser(), + .m_axi_hbm_awvalid(), + .m_axi_hbm_awready(0), + .m_axi_hbm_wdata(), + .m_axi_hbm_wstrb(), + .m_axi_hbm_wlast(), + .m_axi_hbm_wuser(), + .m_axi_hbm_wvalid(), + .m_axi_hbm_wready(0), + .m_axi_hbm_bid(0), + .m_axi_hbm_bresp(0), + .m_axi_hbm_buser(0), + .m_axi_hbm_bvalid(0), + .m_axi_hbm_bready(), + .m_axi_hbm_arid(), + .m_axi_hbm_araddr(), + .m_axi_hbm_arlen(), + .m_axi_hbm_arsize(), + .m_axi_hbm_arburst(), + .m_axi_hbm_arlock(), + .m_axi_hbm_arcache(), + .m_axi_hbm_arprot(), + .m_axi_hbm_arqos(), + .m_axi_hbm_aruser(), + .m_axi_hbm_arvalid(), + .m_axi_hbm_arready(0), + .m_axi_hbm_rid(0), + .m_axi_hbm_rdata(0), + .m_axi_hbm_rresp(0), + .m_axi_hbm_rlast(0), + .m_axi_hbm_ruser(0), + .m_axi_hbm_rvalid(0), + .m_axi_hbm_rready(), + + .hbm_status(0), + /* * Statistics input */ diff --git a/fpga/mqnic/fb2CG/fpga_25g/README.md b/fpga/mqnic/fb2CG/fpga_25g/README.md index 44d87454a..bd42b52e3 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/README.md +++ b/fpga/mqnic/fb2CG/fpga_25g/README.md @@ -4,8 +4,9 @@ This design targets the Silicom fb2CG@KU15P FPGA board. -FPGA: xcku15p-ffve1760-2-e -PHY: 25G BASE-R PHY IP core and internal GTY transceiver +* FPGA: xcku15p-ffve1760-2-e +* PHY: 25G BASE-R PHY IP core and internal GTY transceiver +* RAM: 16GB DDR4 2666 (4x 512M x72) ## How to build diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga.xdc b/fpga/mqnic/fb2CG/fpga_25g/fpga.xdc index 8c80f7309..af9b8f811 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga.xdc +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga.xdc @@ -23,14 +23,22 @@ create_clock -period 20.000 -name init_clk [get_ports init_clk] set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets init_clk_bufg] # DDR4 refclk1 -#set_property -dict {LOC AT32 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk1_p] -#set_property -dict {LOC AU32 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk1_n] -#create_clock -period 3.750 -name clk_ddr4_refclk1 [get_ports clk_ddr4_refclk1_p] +set_property -dict {LOC AT32 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk1_p] +set_property -dict {LOC AU32 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk1_n] +create_clock -period 3.750 -name clk_ddr4_refclk1 [get_ports clk_ddr4_refclk1_p] + +# DDR ref clock sharing +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {name =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1 && name =~*ddr4_c0_inst*}] +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {name =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1 && name =~*ddr4_c1_inst*}] # DDR4 refclk2 -#set_property -dict {LOC G29 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk2_p] -#set_property -dict {LOC G28 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk2_n] -#create_clock -period 3.750 -name clk_ddr4_refclk2 [get_ports clk_ddr4_refclk1_p] +set_property -dict {LOC G28 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk2_p] +set_property -dict {LOC G29 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk2_n] +create_clock -period 3.750 -name clk_ddr4_refclk2 [get_ports clk_ddr4_refclk2_p] + +# DDR ref clock sharing +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {name =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1 && name =~*ddr4_c2_inst*}] +set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {name =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1 && name =~*ddr4_c3_inst*}] # LEDs set_property -dict {LOC C4 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports led_sreg_d] @@ -264,3 +272,539 @@ create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_refclk_p] set_false_path -from [get_ports {pcie_rst_n}] set_input_delay 0 [get_ports {pcie_rst_n}] + +# DDR4 C0 +# 5x K4A8G165WB-BCTD / MT40A512M16HA-075E +set_property -dict {LOC AY22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[0]}] +set_property -dict {LOC AY23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[1]}] +set_property -dict {LOC AV23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[2]}] +set_property -dict {LOC AY24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[3]}] +set_property -dict {LOC AK23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[4]}] +set_property -dict {LOC AV21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[5]}] +set_property -dict {LOC AV22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[6]}] +set_property -dict {LOC AT24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[7]}] +set_property -dict {LOC AW24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[8]}] +set_property -dict {LOC AY21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[9]}] +set_property -dict {LOC AT22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[10]}] +set_property -dict {LOC AP23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[11]}] +set_property -dict {LOC BA21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[12]}] +set_property -dict {LOC AU24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[13]}] +set_property -dict {LOC AL22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[14]}] +set_property -dict {LOC BB22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[15]}] +set_property -dict {LOC BB25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_adr[16]}] +set_property -dict {LOC AW21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[0]}] +set_property -dict {LOC AW23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_ba[1]}] +set_property -dict {LOC BA22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[0]}] +set_property -dict {LOC BB23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_bg[1]}] +set_property -dict {LOC BA24 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_t}] +set_property -dict {LOC BB24 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c0_ck_c}] +set_property -dict {LOC AL21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cke}] +set_property -dict {LOC BA25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_cs_n}] +set_property -dict {LOC AR21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_act_n}] +set_property -dict {LOC AT21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_odt}] +set_property -dict {LOC AK17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c0_par}] +set_property -dict {LOC BB20 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_reset_n}] +set_property -dict {LOC AV20 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_alert_n}] +set_property -dict {LOC AU20 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c0_ten}] + +set_property -dict {LOC AL17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[0]}] +set_property -dict {LOC AJ16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[1]}] +set_property -dict {LOC AK19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[2]}] +set_property -dict {LOC AK16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[3]}] +set_property -dict {LOC AL19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[4]}] +set_property -dict {LOC AH16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[5]}] +set_property -dict {LOC AM17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[6]}] +set_property -dict {LOC AH17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[7]}] +set_property -dict {LOC AL24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[8]}] +set_property -dict {LOC AH21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[9]}] +set_property -dict {LOC AK24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[10]}] +set_property -dict {LOC AJ24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[11]}] +set_property -dict {LOC AK21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[12]}] +set_property -dict {LOC AH22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[13]}] +set_property -dict {LOC AJ21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[14]}] +set_property -dict {LOC AJ23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[15]}] +set_property -dict {LOC BA14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[16]}] +set_property -dict {LOC BB13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[17]}] +set_property -dict {LOC AY13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[18]}] +set_property -dict {LOC BB14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[19]}] +set_property -dict {LOC AY14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[20]}] +set_property -dict {LOC BB15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[21]}] +set_property -dict {LOC BA15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[22]}] +set_property -dict {LOC BB12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[23]}] +set_property -dict {LOC AT15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[24]}] +set_property -dict {LOC AW13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[25]}] +set_property -dict {LOC AU15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[26]}] +set_property -dict {LOC AU13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[27]}] +set_property -dict {LOC AT16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[28]}] +set_property -dict {LOC AW14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[29]}] +set_property -dict {LOC AU14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[30]}] +set_property -dict {LOC AV13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[31]}] +set_property -dict {LOC BB18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[32]}] +set_property -dict {LOC AY18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[33]}] +set_property -dict {LOC BA19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[34]}] +set_property -dict {LOC AW19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[35]}] +set_property -dict {LOC BB17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[36]}] +set_property -dict {LOC AW18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[37]}] +set_property -dict {LOC BB19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[38]}] +set_property -dict {LOC AY19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[39]}] +set_property -dict {LOC AV17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[40]}] +set_property -dict {LOC AT19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[41]}] +set_property -dict {LOC AU18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[42]}] +set_property -dict {LOC AU19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[43]}] +set_property -dict {LOC AU17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[44]}] +set_property -dict {LOC AR19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[45]}] +set_property -dict {LOC AV18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[46]}] +set_property -dict {LOC AR18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[47]}] +set_property -dict {LOC AN16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[48]}] +set_property -dict {LOC AM20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[49]}] +set_property -dict {LOC AN18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[50]}] +set_property -dict {LOC AN20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[51]}] +set_property -dict {LOC AP16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[52]}] +set_property -dict {LOC AL20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[53]}] +set_property -dict {LOC AN17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[54]}] +set_property -dict {LOC AP20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[55]}] +set_property -dict {LOC AR23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[56]}] +set_property -dict {LOC AM23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[57]}] +set_property -dict {LOC AR24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[58]}] +set_property -dict {LOC AM24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[59]}] +set_property -dict {LOC AR22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[60]}] +set_property -dict {LOC AN22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[61]}] +set_property -dict {LOC AP24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[62]}] +set_property -dict {LOC AM22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[63]}] +set_property -dict {LOC AM14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[64]}] +set_property -dict {LOC AR12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[65]}] +set_property -dict {LOC AP15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[66]}] +set_property -dict {LOC AR13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[67]}] +set_property -dict {LOC AM15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[68]}] +set_property -dict {LOC AT12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[69]}] +set_property -dict {LOC AP14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[70]}] +set_property -dict {LOC AP13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dq[71]}] +set_property -dict {LOC AJ19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[0]}] +set_property -dict {LOC AJ18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[0]}] +set_property -dict {LOC AH20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[1]}] +set_property -dict {LOC AJ20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[1]}] +set_property -dict {LOC AY12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[2]}] +set_property -dict {LOC BA12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[2]}] +set_property -dict {LOC AU12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[3]}] +set_property -dict {LOC AV12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[3]}] +set_property -dict {LOC AY17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[4]}] +set_property -dict {LOC BA17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[4]}] +set_property -dict {LOC AR17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[5]}] +set_property -dict {LOC AT17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[5]}] +set_property -dict {LOC AM19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[6]}] +set_property -dict {LOC AM18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[6]}] +set_property -dict {LOC AN21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[7]}] +set_property -dict {LOC AP21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[7]}] +set_property -dict {LOC AN13 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_t[8]}] +set_property -dict {LOC AN12 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c0_dqs_c[8]}] +set_property -dict {LOC AK18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[0]}] +set_property -dict {LOC AK22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[1]}] +set_property -dict {LOC AY16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[2]}] +set_property -dict {LOC AV15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[3]}] +set_property -dict {LOC BA20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[4]}] +set_property -dict {LOC AT20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[5]}] +set_property -dict {LOC AP19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[6]}] +set_property -dict {LOC AN23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[7]}] +set_property -dict {LOC AR14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c0_dm_dbi_n[8]}] + +# DDR4 C1 +# 5x K4A8G165WB-BCTD / MT40A512M16HA-075E +set_property -dict {LOC AT30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}] +set_property -dict {LOC AR29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}] +set_property -dict {LOC AP30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}] +set_property -dict {LOC AR32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}] +set_property -dict {LOC AU30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}] +set_property -dict {LOC AP28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}] +set_property -dict {LOC AW31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}] +set_property -dict {LOC AM30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}] +set_property -dict {LOC AR33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}] +set_property -dict {LOC AN28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}] +set_property -dict {LOC AV31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}] +set_property -dict {LOC AP29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}] +set_property -dict {LOC AR31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}] +set_property -dict {LOC AN30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}] +set_property -dict {LOC AN32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}] +set_property -dict {LOC AV32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}] +set_property -dict {LOC BA34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}] +set_property -dict {LOC AP34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}] +set_property -dict {LOC AT31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}] +set_property -dict {LOC AP33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}] +set_property -dict {LOC AV33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[1]}] +set_property -dict {LOC AT34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t}] +set_property -dict {LOC AU34 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c}] +set_property -dict {LOC AP31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke}] +set_property -dict {LOC AR34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n}] +set_property -dict {LOC AU33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}] +set_property -dict {LOC AN31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt}] +set_property -dict {LOC AW26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}] +set_property -dict {LOC AV25 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}] +set_property -dict {LOC BA31 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_alert_n}] +set_property -dict {LOC AT27 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_ten}] + +set_property -dict {LOC AV41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] +set_property -dict {LOC BB39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] +set_property -dict {LOC AY42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] +set_property -dict {LOC BA40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] +set_property -dict {LOC AV42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] +set_property -dict {LOC BA39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] +set_property -dict {LOC AW41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] +set_property -dict {LOC BB40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] +set_property -dict {LOC AV38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] +set_property -dict {LOC BA37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] +set_property -dict {LOC AW38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] +set_property -dict {LOC AV37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] +set_property -dict {LOC AU37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] +set_property -dict {LOC AW36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] +set_property -dict {LOC BB38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] +set_property -dict {LOC AV36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] +set_property -dict {LOC BB34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] +set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] +set_property -dict {LOC BB33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] +set_property -dict {LOC AY33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] +set_property -dict {LOC BA36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] +set_property -dict {LOC AW34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] +set_property -dict {LOC BB37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] +set_property -dict {LOC AW33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] +set_property -dict {LOC BA32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] +set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] +set_property -dict {LOC BB29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] +set_property -dict {LOC AY29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] +set_property -dict {LOC BB32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] +set_property -dict {LOC AW30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] +set_property -dict {LOC BB28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] +set_property -dict {LOC AW29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] +set_property -dict {LOC AY28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] +set_property -dict {LOC AV26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] +set_property -dict {LOC BA26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] +set_property -dict {LOC AV27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] +set_property -dict {LOC AW28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] +set_property -dict {LOC AV28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] +set_property -dict {LOC AY26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] +set_property -dict {LOC AY27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] +set_property -dict {LOC AU27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] +set_property -dict {LOC AP25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] +set_property -dict {LOC AR27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] +set_property -dict {LOC AP26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] +set_property -dict {LOC AU28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] +set_property -dict {LOC AN25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] +set_property -dict {LOC AR26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] +set_property -dict {LOC AR28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] +set_property -dict {LOC AM29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] +set_property -dict {LOC AK30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] +set_property -dict {LOC AL29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] +set_property -dict {LOC AH30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] +set_property -dict {LOC AM28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] +set_property -dict {LOC AJ30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] +set_property -dict {LOC AK29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] +set_property -dict {LOC AJ29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] +set_property -dict {LOC AL25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] +set_property -dict {LOC AH26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] +set_property -dict {LOC AL27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] +set_property -dict {LOC AJ25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] +set_property -dict {LOC AM27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] +set_property -dict {LOC AH27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] +set_property -dict {LOC AM25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] +set_property -dict {LOC AJ26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] +set_property -dict {LOC AK13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}] +set_property -dict {LOC AJ13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}] +set_property -dict {LOC AL14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}] +set_property -dict {LOC AH13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}] +set_property -dict {LOC AK14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}] +set_property -dict {LOC AH12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}] +set_property -dict {LOC AL15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}] +set_property -dict {LOC AK12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}] +set_property -dict {LOC AY41 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] +set_property -dict {LOC BA41 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] +set_property -dict {LOC AY37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] +set_property -dict {LOC AY38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] +set_property -dict {LOC BA35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] +set_property -dict {LOC BB35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] +set_property -dict {LOC BA30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] +set_property -dict {LOC BB30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] +set_property -dict {LOC BA27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] +set_property -dict {LOC BB27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] +set_property -dict {LOC AT29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] +set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] +set_property -dict {LOC AJ28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] +set_property -dict {LOC AK28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] +set_property -dict {LOC AN26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] +set_property -dict {LOC AN27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] +set_property -dict {LOC AJ15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}] +set_property -dict {LOC AJ14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}] +set_property -dict {LOC AW39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[0]}] +set_property -dict {LOC AU35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[1]}] +set_property -dict {LOC AY34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[2]}] +set_property -dict {LOC AY31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[3]}] +set_property -dict {LOC AU25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[4]}] +set_property -dict {LOC AT26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[5]}] +set_property -dict {LOC AL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[6]}] +set_property -dict {LOC AK26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[7]}] +set_property -dict {LOC AM13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[8]}] + +# DDR4 C2 +# 5x K4A8G165WB-BCTD / MT40A512M16HA-075E +set_property -dict {LOC J30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[0]}] +set_property -dict {LOC J29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[1]}] +set_property -dict {LOC G32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[2]}] +set_property -dict {LOC F31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[3]}] +set_property -dict {LOC H29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[4]}] +set_property -dict {LOC F28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[5]}] +set_property -dict {LOC J28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[6]}] +set_property -dict {LOC H32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[7]}] +set_property -dict {LOC L29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[8]}] +set_property -dict {LOC H31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[9]}] +set_property -dict {LOC F30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[10]}] +set_property -dict {LOC J32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[11]}] +set_property -dict {LOC B28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[12]}] +set_property -dict {LOC K32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[13]}] +set_property -dict {LOC F29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[14]}] +set_property -dict {LOC D29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[15]}] +set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[16]}] +set_property -dict {LOC G31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[0]}] +set_property -dict {LOC H30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[1]}] +set_property -dict {LOC E31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[0]}] +set_property -dict {LOC D30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[1]}] +set_property -dict {LOC E32 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t}] +set_property -dict {LOC D32 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c}] +set_property -dict {LOC E30 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke}] +set_property -dict {LOC C31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n}] +set_property -dict {LOC E28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_act_n}] +set_property -dict {LOC D28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt}] +set_property -dict {LOC J18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_par}] +set_property -dict {LOC L19 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_reset_n}] +set_property -dict {LOC F19 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_alert_n}] +set_property -dict {LOC E15 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_ten}] + +set_property -dict {LOC G38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[0]}] +set_property -dict {LOC D42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[1]}] +set_property -dict {LOC F39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[2]}] +set_property -dict {LOC G41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[3]}] +set_property -dict {LOC F38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[4]}] +set_property -dict {LOC G42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[5]}] +set_property -dict {LOC G39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[6]}] +set_property -dict {LOC E42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[7]}] +set_property -dict {LOC C39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[8]}] +set_property -dict {LOC B41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[9]}] +set_property -dict {LOC B39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[10]}] +set_property -dict {LOC C41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[11]}] +set_property -dict {LOC B38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[12]}] +set_property -dict {LOC C42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[13]}] +set_property -dict {LOC A38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[14]}] +set_property -dict {LOC C40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[15]}] +set_property -dict {LOC AT36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[16]}] +set_property -dict {LOC AR38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[17]}] +set_property -dict {LOC AP36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[18]}] +set_property -dict {LOC AR37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[19]}] +set_property -dict {LOC AR36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[20]}] +set_property -dict {LOC AP39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[21]}] +set_property -dict {LOC AP37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[22]}] +set_property -dict {LOC AP40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[23]}] +set_property -dict {LOC N24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[24]}] +set_property -dict {LOC M26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[25]}] +set_property -dict {LOC N26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[26]}] +set_property -dict {LOC L25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[27]}] +set_property -dict {LOC N25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[28]}] +set_property -dict {LOC L26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[29]}] +set_property -dict {LOC M23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[30]}] +set_property -dict {LOC L23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[31]}] +set_property -dict {LOC AP41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[32]}] +set_property -dict {LOC AT41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[33]}] +set_property -dict {LOC AP42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[34]}] +set_property -dict {LOC AU40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[35]}] +set_property -dict {LOC AR41 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[36]}] +set_property -dict {LOC AV40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[37]}] +set_property -dict {LOC AR42 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[38]}] +set_property -dict {LOC AT40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[39]}] +set_property -dict {LOC K28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[40]}] +set_property -dict {LOC K31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[41]}] +set_property -dict {LOC P28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[42]}] +set_property -dict {LOC N28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[43]}] +set_property -dict {LOC M27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[44]}] +set_property -dict {LOC L31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[45]}] +set_property -dict {LOC N27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[46]}] +set_property -dict {LOC L28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[47]}] +set_property -dict {LOC D34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[48]}] +set_property -dict {LOC A34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[49]}] +set_property -dict {LOC C34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[50]}] +set_property -dict {LOC A35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[51]}] +set_property -dict {LOC C36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[52]}] +set_property -dict {LOC A36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[53]}] +set_property -dict {LOC C37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[54]}] +set_property -dict {LOC B34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[55]}] +set_property -dict {LOC B29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[56]}] +set_property -dict {LOC B33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[57]}] +set_property -dict {LOC A29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[58]}] +set_property -dict {LOC B32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[59]}] +set_property -dict {LOC A28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[60]}] +set_property -dict {LOC A33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[61]}] +set_property -dict {LOC C29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[62]}] +set_property -dict {LOC B31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[63]}] +set_property -dict {LOC E37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[64]}] +set_property -dict {LOC E36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[65]}] +set_property -dict {LOC F36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[66]}] +set_property -dict {LOC D37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[67]}] +set_property -dict {LOC E38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[68]}] +set_property -dict {LOC F33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[69]}] +set_property -dict {LOC G36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[70]}] +set_property -dict {LOC E33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[71]}] +set_property -dict {LOC F41 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[0]}] +set_property -dict {LOC E41 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[0]}] +set_property -dict {LOC A39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[1]}] +set_property -dict {LOC A40 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[1]}] +set_property -dict {LOC AT37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[2]}] +set_property -dict {LOC AU38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[2]}] +set_property -dict {LOC M24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[3]}] +set_property -dict {LOC L24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[3]}] +set_property -dict {LOC AT42 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[4]}] +set_property -dict {LOC AU42 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[4]}] +set_property -dict {LOC L30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[5]}] +set_property -dict {LOC K30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[5]}] +set_property -dict {LOC B36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[6]}] +set_property -dict {LOC B37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[6]}] +set_property -dict {LOC A30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[7]}] +set_property -dict {LOC A31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[7]}] +set_property -dict {LOC F35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[8]}] +set_property -dict {LOC E35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[8]}] +set_property -dict {LOC G40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[0]}] +set_property -dict {LOC D39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[1]}] +set_property -dict {LOC AP38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[2]}] +set_property -dict {LOC P23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[3]}] +set_property -dict {LOC AT39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[4]}] +set_property -dict {LOC M28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[5]}] +set_property -dict {LOC D35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[6]}] +set_property -dict {LOC C30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[7]}] +set_property -dict {LOC G34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[8]}] + +# DDR4 C3 +# 5x K4A8G165WB-BCTD / MT40A512M16HA-075E +set_property -dict {LOC F23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[0]}] +set_property -dict {LOC G23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[1]}] +set_property -dict {LOC H24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[2]}] +set_property -dict {LOC F25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[3]}] +set_property -dict {LOC F26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[4]}] +set_property -dict {LOC F24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[5]}] +set_property -dict {LOC K26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[6]}] +set_property -dict {LOC G27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[7]}] +set_property -dict {LOC J27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[8]}] +set_property -dict {LOC G24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[9]}] +set_property -dict {LOC E25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[10]}] +set_property -dict {LOC H27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[11]}] +set_property -dict {LOC E23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[12]}] +set_property -dict {LOC G26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[13]}] +set_property -dict {LOC J23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[14]}] +set_property -dict {LOC D23 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[15]}] +set_property -dict {LOC B27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_adr[16]}] +set_property -dict {LOC J25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[0]}] +set_property -dict {LOC K25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_ba[1]}] +set_property -dict {LOC J24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[0]}] +set_property -dict {LOC D25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_bg[1]}] +set_property -dict {LOC E27 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_t}] +set_property -dict {LOC D27 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c3_ck_c}] +set_property -dict {LOC E26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cke}] +set_property -dict {LOC H25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_cs_n}] +set_property -dict {LOC D24 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_act_n}] +set_property -dict {LOC B22 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_odt}] +set_property -dict {LOC A14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c3_par}] +set_property -dict {LOC M16 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c3_reset_n}] +set_property -dict {LOC F20 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c3_alert_n}] +set_property -dict {LOC J17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c3_ten}] + +set_property -dict {LOC E18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[0]}] +set_property -dict {LOC G17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[1]}] +set_property -dict {LOC F16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[2]}] +set_property -dict {LOC G16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[3]}] +set_property -dict {LOC E16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[4]}] +set_property -dict {LOC H17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[5]}] +set_property -dict {LOC E17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[6]}] +set_property -dict {LOC F18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[7]}] +set_property -dict {LOC N12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[8]}] +set_property -dict {LOC P15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[9]}] +set_property -dict {LOC M13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[10]}] +set_property -dict {LOC P12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[11]}] +set_property -dict {LOC M12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[12]}] +set_property -dict {LOC N15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[13]}] +set_property -dict {LOC M14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[14]}] +set_property -dict {LOC P13 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[15]}] +set_property -dict {LOC C17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[16]}] +set_property -dict {LOC C15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[17]}] +set_property -dict {LOC A16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[18]}] +set_property -dict {LOC A15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[19]}] +set_property -dict {LOC B17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[20]}] +set_property -dict {LOC D15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[21]}] +set_property -dict {LOC D18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[22]}] +set_property -dict {LOC D17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[23]}] +set_property -dict {LOC J14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[24]}] +set_property -dict {LOC L16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[25]}] +set_property -dict {LOC H15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[26]}] +set_property -dict {LOC H14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[27]}] +set_property -dict {LOC J15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[28]}] +set_property -dict {LOC K16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[29]}] +set_property -dict {LOC K15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[30]}] +set_property -dict {LOC H16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[31]}] +set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[32]}] +set_property -dict {LOC H19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[33]}] +set_property -dict {LOC J20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[34]}] +set_property -dict {LOC J19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[35]}] +set_property -dict {LOC K20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[36]}] +set_property -dict {LOC K18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[37]}] +set_property -dict {LOC H20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[38]}] +set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[39]}] +set_property -dict {LOC D20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[40]}] +set_property -dict {LOC B19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[41]}] +set_property -dict {LOC A21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[42]}] +set_property -dict {LOC A19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[43]}] +set_property -dict {LOC B21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[44]}] +set_property -dict {LOC D19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[45]}] +set_property -dict {LOC C21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[46]}] +set_property -dict {LOC A20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[47]}] +set_property -dict {LOC N19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[48]}] +set_property -dict {LOC N22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[49]}] +set_property -dict {LOC P20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[50]}] +set_property -dict {LOC N21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[51]}] +set_property -dict {LOC P19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[52]}] +set_property -dict {LOC N20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[53]}] +set_property -dict {LOC P18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[54]}] +set_property -dict {LOC P22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[55]}] +set_property -dict {LOC C25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[56]}] +set_property -dict {LOC A23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[57]}] +set_property -dict {LOC B26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[58]}] +set_property -dict {LOC A26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[59]}] +set_property -dict {LOC C26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[60]}] +set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[61]}] +set_property -dict {LOC A24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[62]}] +set_property -dict {LOC A25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[63]}] +set_property -dict {LOC H22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[64]}] +set_property -dict {LOC E21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[65]}] +set_property -dict {LOC G21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[66]}] +set_property -dict {LOC E22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[67]}] +set_property -dict {LOC H21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[68]}] +set_property -dict {LOC E20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[69]}] +set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[70]}] +set_property -dict {LOC D22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dq[71]}] +set_property -dict {LOC G14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[0]}] +set_property -dict {LOC F14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[0]}] +set_property -dict {LOC P14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[1]}] +set_property -dict {LOC N14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[1]}] +set_property -dict {LOC C16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[2]}] +set_property -dict {LOC B16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[2]}] +set_property -dict {LOC L15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[3]}] +set_property -dict {LOC L14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[3]}] +set_property -dict {LOC K22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[4]}] +set_property -dict {LOC J22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[4]}] +set_property -dict {LOC C20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[5]}] +set_property -dict {LOC C19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[5]}] +set_property -dict {LOC M21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[6]}] +set_property -dict {LOC L21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[6]}] +set_property -dict {LOC B23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[7]}] +set_property -dict {LOC B24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[7]}] +set_property -dict {LOC G19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_t[8]}] +set_property -dict {LOC G18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c3_dqs_c[8]}] +set_property -dict {LOC F15 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dm_dbi_n[0]}] +set_property -dict {LOC N16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dm_dbi_n[1]}] +set_property -dict {LOC B14 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dm_dbi_n[2]}] +set_property -dict {LOC K17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dm_dbi_n[3]}] +set_property -dict {LOC L20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dm_dbi_n[4]}] +set_property -dict {LOC B18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dm_dbi_n[5]}] +set_property -dict {LOC M19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dm_dbi_n[6]}] +set_property -dict {LOC C27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dm_dbi_n[7]}] +set_property -dict {LOC F21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c3_dm_dbi_n[8]}] diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile index 65a53e477..a82125da2 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile @@ -141,6 +141,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl b/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl index dd3d5e842..324df9f07 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga/config.tcl @@ -149,6 +149,12 @@ dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" dict set params RX_RAM_SIZE "131072" +# RAM configuration +dict set params DDR_CH "4" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" + # Application block configuration dict set params APP_ID "32'h00000000" dict set params APP_ENABLE "0" @@ -200,6 +206,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile index 65a53e477..a82125da2 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile @@ -141,6 +141,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl index 98342c885..97c4931d6 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/config.tcl @@ -149,6 +149,12 @@ dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" dict set params RX_RAM_SIZE "32768" +# RAM configuration +dict set params DDR_CH "4" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" + # Application block configuration dict set params APP_ID "32'h00000000" dict set params APP_ENABLE "0" @@ -200,6 +206,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile index 3c1b61280..0fe0e04ce 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile @@ -142,6 +142,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl IP_TCL_FILES += ip/eth_xcvr_gty.tcl +IP_TCL_FILES += ip/ddr4_0.tcl # Configuration CONFIG_TCL_FILES = ./config.tcl diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl index 124dee6f2..923a99fa7 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/config.tcl @@ -149,6 +149,12 @@ dict set params MAX_RX_SIZE "9214" dict set params TX_RAM_SIZE "32768" dict set params RX_RAM_SIZE "131072" +# RAM configuration +dict set params DDR_CH "4" +dict set params DDR_ENABLE "1" +dict set params AXI_DDR_ID_WIDTH "8" +dict set params AXI_DDR_MAX_BURST_LEN "256" + # Application block configuration dict set params APP_ID "32'h00000000" dict set params APP_ENABLE "0" @@ -200,6 +206,19 @@ dict set params STAT_PCIE_ENABLE "1" dict set params STAT_INC_WIDTH "24" dict set params STAT_ID_WIDTH "12" +# DDR4 MIG settings +if {[dict get $params DDR_ENABLE]} { + set ddr4 [get_ips ddr4_0] + + # set AXI ID width + set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4 + + # extract AXI configuration + dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4] + dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4] + dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1] +} + # PCIe IP core settings set pcie [get_ips pcie4_uscale_plus_0] diff --git a/fpga/mqnic/fb2CG/fpga_25g/ip/ddr4_0.tcl b/fpga/mqnic/fb2CG/fpga_25g/ip/ddr4_0.tcl new file mode 100644 index 000000000..ac9925b31 --- /dev/null +++ b/fpga/mqnic/fb2CG/fpga_25g/ip/ddr4_0.tcl @@ -0,0 +1,20 @@ + +create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0 + +set_property -dict [list \ + CONFIG.System_Clock {No_Buffer} \ + CONFIG.C0.DDR4_AxiSelection {true} \ + CONFIG.C0.DDR4_AxiDataWidth {512} \ + CONFIG.C0.DDR4_AxiIDWidth {8} \ + CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \ + CONFIG.C0.DDR4_TimePeriod {750} \ + CONFIG.C0.DDR4_InputClockPeriod {3750} \ + CONFIG.C0.DDR4_MemoryType {Components} \ + CONFIG.C0.DDR4_MemoryPart {MT40A512M16HA-075E} \ + CONFIG.C0.DDR4_DataWidth {72} \ + CONFIG.C0.DDR4_DataMask {NO_DM_NO_DBI} \ + CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \ + CONFIG.C0.DDR4_CasLatency {18} \ + CONFIG.C0.DDR4_CasWriteLatency {14} \ + CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} +] [get_ips ddr4_0] diff --git a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v index 6432b75c1..53cb53bbb 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v +++ b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v @@ -112,6 +112,15 @@ module fpga # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // RAM configuration + parameter DDR_CH = 4, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 32, + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -181,6 +190,10 @@ module fpga # * Clock: 100MHz */ input wire init_clk, + input wire clk_ddr4_refclk1_p, + input wire clk_ddr4_refclk1_n, + input wire clk_ddr4_refclk2_p, + input wire clk_ddr4_refclk2_n, /* * GPIO @@ -272,7 +285,82 @@ module fpga # output wire qsfp_1_lp_mode, input wire qsfp_1_intr_n, inout wire qsfp_1_i2c_scl, - inout wire qsfp_1_i2c_sda + inout wire qsfp_1_i2c_sda, + + /* + * DDR4 + */ + output wire [16:0] ddr4_c0_adr, + output wire [1:0] ddr4_c0_ba, + output wire [1:0] ddr4_c0_bg, + output wire ddr4_c0_ck_t, + output wire ddr4_c0_ck_c, + output wire ddr4_c0_cke, + output wire ddr4_c0_cs_n, + output wire ddr4_c0_act_n, + output wire ddr4_c0_odt, + output wire ddr4_c0_par, + input wire ddr4_c0_alert_n, + output wire ddr4_c0_reset_n, + output wire ddr4_c0_ten, + inout wire [71:0] ddr4_c0_dq, + inout wire [8:0] ddr4_c0_dqs_t, + inout wire [8:0] ddr4_c0_dqs_c, + inout wire [8:0] ddr4_c0_dm_dbi_n, + + output wire [16:0] ddr4_c1_adr, + output wire [1:0] ddr4_c1_ba, + output wire [1:0] ddr4_c1_bg, + output wire ddr4_c1_ck_t, + output wire ddr4_c1_ck_c, + output wire ddr4_c1_cke, + output wire ddr4_c1_cs_n, + output wire ddr4_c1_act_n, + output wire ddr4_c1_odt, + output wire ddr4_c1_par, + input wire ddr4_c1_alert_n, + output wire ddr4_c1_reset_n, + output wire ddr4_c1_ten, + inout wire [71:0] ddr4_c1_dq, + inout wire [8:0] ddr4_c1_dqs_t, + inout wire [8:0] ddr4_c1_dqs_c, + inout wire [8:0] ddr4_c1_dm_dbi_n, + + output wire [16:0] ddr4_c2_adr, + output wire [1:0] ddr4_c2_ba, + output wire [1:0] ddr4_c2_bg, + output wire ddr4_c2_ck_t, + output wire ddr4_c2_ck_c, + output wire ddr4_c2_cke, + output wire ddr4_c2_cs_n, + output wire ddr4_c2_act_n, + output wire ddr4_c2_odt, + output wire ddr4_c2_par, + input wire ddr4_c2_alert_n, + output wire ddr4_c2_reset_n, + output wire ddr4_c2_ten, + inout wire [71:0] ddr4_c2_dq, + inout wire [8:0] ddr4_c2_dqs_t, + inout wire [8:0] ddr4_c2_dqs_c, + inout wire [8:0] ddr4_c2_dm_dbi_n, + + output wire [16:0] ddr4_c3_adr, + output wire [1:0] ddr4_c3_ba, + output wire [1:0] ddr4_c3_bg, + output wire ddr4_c3_ck_t, + output wire ddr4_c3_ck_c, + output wire ddr4_c3_cke, + output wire ddr4_c3_cs_n, + output wire ddr4_c3_act_n, + output wire ddr4_c3_odt, + output wire ddr4_c3_par, + input wire ddr4_c3_alert_n, + output wire ddr4_c3_reset_n, + output wire ddr4_c3_ten, + inout wire [71:0] ddr4_c3_dq, + inout wire [8:0] ddr4_c3_dqs_t, + inout wire [8:0] ddr4_c3_dqs_c, + inout wire [8:0] ddr4_c3_dm_dbi_n ); // PTP configuration @@ -286,6 +374,9 @@ parameter IF_PTP_PERIOD_FNS = 16'h8F5C; // Interface configuration parameter TX_TAG_WIDTH = 16; +// RAM configuration +parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8); + // Ethernet interface configuration parameter XGMII_DATA_WIDTH = 64; parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8; @@ -1380,6 +1471,565 @@ assign led_green[5] = qsfp_1_rx_status_1; assign led_green[6] = qsfp_1_rx_status_2; assign led_green[7] = qsfp_1_rx_status_3; +// DDR4 +wire [DDR_CH-1:0] ddr_clk; +wire [DDR_CH-1:0] ddr_rst; + +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr; +wire [DDR_CH*8-1:0] m_axi_ddr_awlen; +wire [DDR_CH*3-1:0] m_axi_ddr_awsize; +wire [DDR_CH*2-1:0] m_axi_ddr_awburst; +wire [DDR_CH-1:0] m_axi_ddr_awlock; +wire [DDR_CH*4-1:0] m_axi_ddr_awcache; +wire [DDR_CH*3-1:0] m_axi_ddr_awprot; +wire [DDR_CH*4-1:0] m_axi_ddr_awqos; +wire [DDR_CH-1:0] m_axi_ddr_awvalid; +wire [DDR_CH-1:0] m_axi_ddr_awready; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata; +wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb; +wire [DDR_CH-1:0] m_axi_ddr_wlast; +wire [DDR_CH-1:0] m_axi_ddr_wvalid; +wire [DDR_CH-1:0] m_axi_ddr_wready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid; +wire [DDR_CH*2-1:0] m_axi_ddr_bresp; +wire [DDR_CH-1:0] m_axi_ddr_bvalid; +wire [DDR_CH-1:0] m_axi_ddr_bready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr; +wire [DDR_CH*8-1:0] m_axi_ddr_arlen; +wire [DDR_CH*3-1:0] m_axi_ddr_arsize; +wire [DDR_CH*2-1:0] m_axi_ddr_arburst; +wire [DDR_CH-1:0] m_axi_ddr_arlock; +wire [DDR_CH*4-1:0] m_axi_ddr_arcache; +wire [DDR_CH*3-1:0] m_axi_ddr_arprot; +wire [DDR_CH*4-1:0] m_axi_ddr_arqos; +wire [DDR_CH-1:0] m_axi_ddr_arvalid; +wire [DDR_CH-1:0] m_axi_ddr_arready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata; +wire [DDR_CH*2-1:0] m_axi_ddr_rresp; +wire [DDR_CH-1:0] m_axi_ddr_rlast; +wire [DDR_CH-1:0] m_axi_ddr_rvalid; +wire [DDR_CH-1:0] m_axi_ddr_rready; + +wire [DDR_CH-1:0] ddr_status; + +generate + +wire clk_ddr4_refclk1_ibufg; +wire clk_ddr4_refclk1; + +IBUFGDS #( + .DIFF_TERM("FALSE"), + .IBUF_LOW_PWR("FALSE") +) +clk_ddr4_refclk1_ibufg_inst ( + .O (clk_ddr4_refclk1_ibufg), + .I (clk_ddr4_refclk1_p), + .IB (clk_ddr4_refclk1_n) +); + +BUFG +clk_ddr4_refclk1_bufg_inst ( + .I(clk_ddr4_refclk1_ibufg), + .O(clk_ddr4_refclk1) +); + +if (DDR_ENABLE && DDR_CH > 0) begin + +ddr4_0 ddr4_c0_inst ( + .c0_sys_clk_i(clk_ddr4_refclk1), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[0 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c0_adr), + .c0_ddr4_ba(ddr4_c0_ba), + .c0_ddr4_cke(ddr4_c0_cke), + .c0_ddr4_cs_n(ddr4_c0_cs_n), + .c0_ddr4_dq(ddr4_c0_dq), + .c0_ddr4_dqs_t(ddr4_c0_dqs_t), + .c0_ddr4_dqs_c(ddr4_c0_dqs_c), + .c0_ddr4_dm_dbi_n(ddr4_c0_dm_dbi_n), + .c0_ddr4_odt(ddr4_c0_odt), + .c0_ddr4_bg(ddr4_c0_bg), + .c0_ddr4_reset_n(ddr4_c0_reset_n), + .c0_ddr4_act_n(ddr4_c0_act_n), + .c0_ddr4_ck_t(ddr4_c0_ck_t), + .c0_ddr4_ck_c(ddr4_c0_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[0 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[0 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c0_adr = {17{1'bz}}; +assign ddr4_c0_ba = {2{1'bz}}; +assign ddr4_c0_bg = {2{1'bz}}; +assign ddr4_c0_cke = 1'bz; +assign ddr4_c0_cs_n = 1'bz; +assign ddr4_c0_act_n = 1'bz; +assign ddr4_c0_odt = 1'bz; +assign ddr4_c0_reset_n = 1'b0; +assign ddr4_c0_dq = {72{1'bz}}; +assign ddr4_c0_dqs_t = {9{1'bz}}; +assign ddr4_c0_dqs_c = {9{1'bz}}; +assign ddr4_c0_dm_dbi_n = {9{1'bz}}; + +OBUFTDS ddr4_c0_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c0_ck_t), + .OB(ddr4_c0_ck_c) +); + +assign ddr_clk = 0; +assign ddr_rst = 0; + +assign m_axi_ddr_awready = 0; +assign m_axi_ddr_wready = 0; +assign m_axi_ddr_bid = 0; +assign m_axi_ddr_bresp = 0; +assign m_axi_ddr_bvalid = 0; +assign m_axi_ddr_arready = 0; +assign m_axi_ddr_rid = 0; +assign m_axi_ddr_rdata = 0; +assign m_axi_ddr_rresp = 0; +assign m_axi_ddr_rlast = 0; +assign m_axi_ddr_rvalid = 0; + +assign ddr_status = 0; + +end + +assign ddr4_c0_par = 1'b0; +assign ddr4_c0_ten = 1'b0; + +if (DDR_ENABLE && DDR_CH > 1) begin + +ddr4_0 ddr4_c1_inst ( + .c0_sys_clk_i(clk_ddr4_refclk1), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[1 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c1_adr), + .c0_ddr4_ba(ddr4_c1_ba), + .c0_ddr4_cke(ddr4_c1_cke), + .c0_ddr4_cs_n(ddr4_c1_cs_n), + .c0_ddr4_dq(ddr4_c1_dq), + .c0_ddr4_dqs_t(ddr4_c1_dqs_t), + .c0_ddr4_dqs_c(ddr4_c1_dqs_c), + .c0_ddr4_dm_dbi_n(ddr4_c1_dm_dbi_n), + .c0_ddr4_odt(ddr4_c1_odt), + .c0_ddr4_bg(ddr4_c1_bg), + .c0_ddr4_reset_n(ddr4_c1_reset_n), + .c0_ddr4_act_n(ddr4_c1_act_n), + .c0_ddr4_ck_t(ddr4_c1_ck_t), + .c0_ddr4_ck_c(ddr4_c1_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[1 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[1 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[1 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[1*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[1*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[1*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[1 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[1*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[1*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[1*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[1 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[1 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[1*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[1 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[1 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[1 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[1 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[1*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[1 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[1*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[1*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[1*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[1 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[1*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[1*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[1*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[1 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[1 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[1 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[1 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[1 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[1*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c1_adr = {17{1'bz}}; +assign ddr4_c1_ba = {2{1'bz}}; +assign ddr4_c1_bg = {2{1'bz}}; +assign ddr4_c1_cke = 1'bz; +assign ddr4_c1_cs_n = 1'bz; +assign ddr4_c1_act_n = 1'bz; +assign ddr4_c1_odt = 1'bz; +assign ddr4_c1_reset_n = 1'b0; +assign ddr4_c1_dq = {72{1'bz}}; +assign ddr4_c1_dqs_t = {9{1'bz}}; +assign ddr4_c1_dqs_c = {9{1'bz}}; +assign ddr4_c1_dm_dbi_n = {9{1'bz}}; + +OBUFTDS ddr4_c1_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c1_ck_t), + .OB(ddr4_c1_ck_c) +); + +end + +assign ddr4_c1_par = 1'b0; +assign ddr4_c1_ten = 1'b0; + +wire clk_ddr4_refclk2_ibufg; +wire clk_ddr4_refclk2; + +IBUFGDS #( + .DIFF_TERM("FALSE"), + .IBUF_LOW_PWR("FALSE") +) +clk_ddr4_refclk2_ibufg_inst ( + .O (clk_ddr4_refclk2_ibufg), + .I (clk_ddr4_refclk2_p), + .IB (clk_ddr4_refclk2_n) +); + +BUFG +clk_ddr4_refclk2_bufg_inst ( + .I(clk_ddr4_refclk2_ibufg), + .O(clk_ddr4_refclk2) +); + +if (DDR_ENABLE && DDR_CH > 2) begin + +ddr4_0 ddr4_c2_inst ( + .c0_sys_clk_i(clk_ddr4_refclk2), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[2 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c2_adr), + .c0_ddr4_ba(ddr4_c2_ba), + .c0_ddr4_cke(ddr4_c2_cke), + .c0_ddr4_cs_n(ddr4_c2_cs_n), + .c0_ddr4_dq(ddr4_c2_dq), + .c0_ddr4_dqs_t(ddr4_c2_dqs_t), + .c0_ddr4_dqs_c(ddr4_c2_dqs_c), + .c0_ddr4_dm_dbi_n(ddr4_c2_dm_dbi_n), + .c0_ddr4_odt(ddr4_c2_odt), + .c0_ddr4_bg(ddr4_c2_bg), + .c0_ddr4_reset_n(ddr4_c2_reset_n), + .c0_ddr4_act_n(ddr4_c2_act_n), + .c0_ddr4_ck_t(ddr4_c2_ck_t), + .c0_ddr4_ck_c(ddr4_c2_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[2 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[2 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[2 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[2*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[2*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[2*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[2 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[2*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[2*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[2*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[2 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[2 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[2*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[2 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[2 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[2 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[2 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[2*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[2 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[2*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[2*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[2*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[2 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[2*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[2*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[2*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[2 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[2 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[2 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[2 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[2 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[2*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c2_adr = {17{1'bz}}; +assign ddr4_c2_ba = {2{1'bz}}; +assign ddr4_c2_bg = {2{1'bz}}; +assign ddr4_c2_cke = 1'bz; +assign ddr4_c2_cs_n = 1'bz; +assign ddr4_c2_act_n = 1'bz; +assign ddr4_c2_odt = 1'bz; +assign ddr4_c2_reset_n = 1'b0; +assign ddr4_c2_dq = {72{1'bz}}; +assign ddr4_c2_dqs_t = {9{1'bz}}; +assign ddr4_c2_dqs_c = {9{1'bz}}; +assign ddr4_c2_dm_dbi_n = {9{1'bz}}; + +OBUFTDS ddr4_c2_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c2_ck_t), + .OB(ddr4_c2_ck_c) +); + +end + +assign ddr4_c2_par = 1'b0; +assign ddr4_c2_ten = 1'b0; + +if (DDR_ENABLE && DDR_CH > 3) begin + +ddr4_0 ddr4_c3_inst ( + .c0_sys_clk_i(clk_ddr4_refclk2), + .sys_rst(pcie_user_reset), + + .c0_init_calib_complete(ddr_status[3 +: 1]), + .c0_ddr4_interrupt(), + .dbg_clk(), + .dbg_bus(), + + .c0_ddr4_adr(ddr4_c3_adr), + .c0_ddr4_ba(ddr4_c3_ba), + .c0_ddr4_cke(ddr4_c3_cke), + .c0_ddr4_cs_n(ddr4_c3_cs_n), + .c0_ddr4_dq(ddr4_c3_dq), + .c0_ddr4_dqs_t(ddr4_c3_dqs_t), + .c0_ddr4_dqs_c(ddr4_c3_dqs_c), + .c0_ddr4_dm_dbi_n(ddr4_c3_dm_dbi_n), + .c0_ddr4_odt(ddr4_c3_odt), + .c0_ddr4_bg(ddr4_c3_bg), + .c0_ddr4_reset_n(ddr4_c3_reset_n), + .c0_ddr4_act_n(ddr4_c3_act_n), + .c0_ddr4_ck_t(ddr4_c3_ck_t), + .c0_ddr4_ck_c(ddr4_c3_ck_c), + + .c0_ddr4_ui_clk(ddr_clk[3 +: 1]), + .c0_ddr4_ui_clk_sync_rst(ddr_rst[3 +: 1]), + + .c0_ddr4_aresetn(!ddr_rst[3 +: 1]), + + .c0_ddr4_s_axi_ctrl_awvalid(1'b0), + .c0_ddr4_s_axi_ctrl_awready(), + .c0_ddr4_s_axi_ctrl_awaddr(32'd0), + .c0_ddr4_s_axi_ctrl_wvalid(1'b0), + .c0_ddr4_s_axi_ctrl_wready(), + .c0_ddr4_s_axi_ctrl_wdata(32'd0), + .c0_ddr4_s_axi_ctrl_bvalid(), + .c0_ddr4_s_axi_ctrl_bready(1'b1), + .c0_ddr4_s_axi_ctrl_bresp(), + .c0_ddr4_s_axi_ctrl_arvalid(1'b0), + .c0_ddr4_s_axi_ctrl_arready(), + .c0_ddr4_s_axi_ctrl_araddr(31'd0), + .c0_ddr4_s_axi_ctrl_rvalid(), + .c0_ddr4_s_axi_ctrl_rready(1'b1), + .c0_ddr4_s_axi_ctrl_rdata(), + .c0_ddr4_s_axi_ctrl_rresp(), + + .c0_ddr4_s_axi_awid(m_axi_ddr_awid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[3*8 +: 8]), + .c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[3*3 +: 3]), + .c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[3*2 +: 2]), + .c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[3 +: 1]), + .c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[3*4 +: 4]), + .c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[3*3 +: 3]), + .c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[3*4 +: 4]), + .c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[3 +: 1]), + .c0_ddr4_s_axi_awready(m_axi_ddr_awready[3 +: 1]), + .c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]), + .c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[3*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]), + .c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[3 +: 1]), + .c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[3 +: 1]), + .c0_ddr4_s_axi_wready(m_axi_ddr_wready[3 +: 1]), + .c0_ddr4_s_axi_bready(m_axi_ddr_bready[3 +: 1]), + .c0_ddr4_s_axi_bid(m_axi_ddr_bid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[3*2 +: 2]), + .c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[3 +: 1]), + .c0_ddr4_s_axi_arid(m_axi_ddr_arid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]), + .c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[3*8 +: 8]), + .c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[3*3 +: 3]), + .c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[3*2 +: 2]), + .c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[3 +: 1]), + .c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[3*4 +: 4]), + .c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[3*3 +: 3]), + .c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[3*4 +: 4]), + .c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[3 +: 1]), + .c0_ddr4_s_axi_arready(m_axi_ddr_arready[3 +: 1]), + .c0_ddr4_s_axi_rready(m_axi_ddr_rready[3 +: 1]), + .c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[3 +: 1]), + .c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[3 +: 1]), + .c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[3*2 +: 2]), + .c0_ddr4_s_axi_rid(m_axi_ddr_rid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]), + .c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]) +); + +end else begin + +assign ddr4_c3_adr = {17{1'bz}}; +assign ddr4_c3_ba = {2{1'bz}}; +assign ddr4_c3_bg = {2{1'bz}}; +assign ddr4_c3_cke = 1'bz; +assign ddr4_c3_cs_n = 1'bz; +assign ddr4_c3_act_n = 1'bz; +assign ddr4_c3_odt = 1'bz; +assign ddr4_c3_reset_n = 1'b0; +assign ddr4_c3_dq = {72{1'bz}}; +assign ddr4_c3_dqs_t = {9{1'bz}}; +assign ddr4_c3_dqs_c = {9{1'bz}}; +assign ddr4_c3_dm_dbi_n = {9{1'bz}}; + +OBUFTDS ddr4_c3_ck_obuftds_inst ( + .I(1'b0), + .T(1'b1), + .O(ddr4_c3_ck_t), + .OB(ddr4_c3_ck_c) +); + +end + +assign ddr4_c3_par = 1'b0; +assign ddr4_c3_ten = 1'b0; + +endgenerate + fpga_core #( // FW and board IDs .FPGA_ID(FPGA_ID), @@ -1458,6 +2108,16 @@ fpga_core #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1775,6 +2435,52 @@ core_inst ( .qsfp_1_i2c_sda_o(qsfp_1_i2c_sda_o), .qsfp_1_i2c_sda_t(qsfp_1_i2c_sda_t), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + /* * QSPI flash */ diff --git a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v index a15a3c14d..5dd0ee842 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v +++ b/fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v @@ -122,6 +122,16 @@ module fpga_core # parameter TX_RAM_SIZE = 32768, parameter RX_RAM_SIZE = 32768, + // RAM configuration + parameter DDR_CH = 4, + parameter DDR_ENABLE = 1, + parameter AXI_DDR_DATA_WIDTH = 512, + parameter AXI_DDR_ADDR_WIDTH = 32, + parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8), + parameter AXI_DDR_ID_WIDTH = 8, + parameter AXI_DDR_MAX_BURST_LEN = 256, + parameter AXI_DDR_NARROW_BURST = 0, + // Application block configuration parameter APP_ID = 32'h00000000, parameter APP_ENABLE = 0, @@ -444,6 +454,52 @@ module fpga_core # output wire qsfp_1_i2c_sda_o, output wire qsfp_1_i2c_sda_t, + /* + * DDR + */ + input wire [DDR_CH-1:0] ddr_clk, + input wire [DDR_CH-1:0] ddr_rst, + + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_awlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_awsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_awburst, + output wire [DDR_CH-1:0] m_axi_ddr_awlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_awcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_awprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_awqos, + output wire [DDR_CH-1:0] m_axi_ddr_awvalid, + input wire [DDR_CH-1:0] m_axi_ddr_awready, + output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata, + output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb, + output wire [DDR_CH-1:0] m_axi_ddr_wlast, + output wire [DDR_CH-1:0] m_axi_ddr_wvalid, + input wire [DDR_CH-1:0] m_axi_ddr_wready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid, + input wire [DDR_CH*2-1:0] m_axi_ddr_bresp, + input wire [DDR_CH-1:0] m_axi_ddr_bvalid, + output wire [DDR_CH-1:0] m_axi_ddr_bready, + output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid, + output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr, + output wire [DDR_CH*8-1:0] m_axi_ddr_arlen, + output wire [DDR_CH*3-1:0] m_axi_ddr_arsize, + output wire [DDR_CH*2-1:0] m_axi_ddr_arburst, + output wire [DDR_CH-1:0] m_axi_ddr_arlock, + output wire [DDR_CH*4-1:0] m_axi_ddr_arcache, + output wire [DDR_CH*3-1:0] m_axi_ddr_arprot, + output wire [DDR_CH*4-1:0] m_axi_ddr_arqos, + output wire [DDR_CH-1:0] m_axi_ddr_arvalid, + input wire [DDR_CH-1:0] m_axi_ddr_arready, + input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid, + input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata, + input wire [DDR_CH*2-1:0] m_axi_ddr_rresp, + input wire [DDR_CH-1:0] m_axi_ddr_rlast, + input wire [DDR_CH-1:0] m_axi_ddr_rvalid, + output wire [DDR_CH-1:0] m_axi_ddr_rready, + + input wire [DDR_CH-1:0] ddr_status, + /* * QSPI flash */ @@ -1194,6 +1250,25 @@ mqnic_core_pcie_us #( .TX_RAM_SIZE(TX_RAM_SIZE), .RX_RAM_SIZE(RX_RAM_SIZE), + // RAM configuration + .DDR_CH(DDR_CH), + .DDR_ENABLE(DDR_ENABLE), + .DDR_GROUP_SIZE(1), + .AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_DDR_AWUSER_ENABLE(0), + .AXI_DDR_WUSER_ENABLE(0), + .AXI_DDR_BUSER_ENABLE(0), + .AXI_DDR_ARUSER_ENABLE(0), + .AXI_DDR_RUSER_ENABLE(0), + .AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST), + .AXI_DDR_FIXED_BURST(0), + .AXI_DDR_WRAP_BURST(1), + .HBM_ENABLE(0), + // Application block configuration .APP_ID(APP_ID), .APP_ENABLE(APP_ENABLE), @@ -1471,6 +1546,108 @@ core_inst ( .eth_rx_status(eth_rx_status), + /* + * DDR + */ + .ddr_clk(ddr_clk), + .ddr_rst(ddr_rst), + + .m_axi_ddr_awid(m_axi_ddr_awid), + .m_axi_ddr_awaddr(m_axi_ddr_awaddr), + .m_axi_ddr_awlen(m_axi_ddr_awlen), + .m_axi_ddr_awsize(m_axi_ddr_awsize), + .m_axi_ddr_awburst(m_axi_ddr_awburst), + .m_axi_ddr_awlock(m_axi_ddr_awlock), + .m_axi_ddr_awcache(m_axi_ddr_awcache), + .m_axi_ddr_awprot(m_axi_ddr_awprot), + .m_axi_ddr_awqos(m_axi_ddr_awqos), + .m_axi_ddr_awuser(), + .m_axi_ddr_awvalid(m_axi_ddr_awvalid), + .m_axi_ddr_awready(m_axi_ddr_awready), + .m_axi_ddr_wdata(m_axi_ddr_wdata), + .m_axi_ddr_wstrb(m_axi_ddr_wstrb), + .m_axi_ddr_wlast(m_axi_ddr_wlast), + .m_axi_ddr_wuser(), + .m_axi_ddr_wvalid(m_axi_ddr_wvalid), + .m_axi_ddr_wready(m_axi_ddr_wready), + .m_axi_ddr_bid(m_axi_ddr_bid), + .m_axi_ddr_bresp(m_axi_ddr_bresp), + .m_axi_ddr_buser(0), + .m_axi_ddr_bvalid(m_axi_ddr_bvalid), + .m_axi_ddr_bready(m_axi_ddr_bready), + .m_axi_ddr_arid(m_axi_ddr_arid), + .m_axi_ddr_araddr(m_axi_ddr_araddr), + .m_axi_ddr_arlen(m_axi_ddr_arlen), + .m_axi_ddr_arsize(m_axi_ddr_arsize), + .m_axi_ddr_arburst(m_axi_ddr_arburst), + .m_axi_ddr_arlock(m_axi_ddr_arlock), + .m_axi_ddr_arcache(m_axi_ddr_arcache), + .m_axi_ddr_arprot(m_axi_ddr_arprot), + .m_axi_ddr_arqos(m_axi_ddr_arqos), + .m_axi_ddr_aruser(), + .m_axi_ddr_arvalid(m_axi_ddr_arvalid), + .m_axi_ddr_arready(m_axi_ddr_arready), + .m_axi_ddr_rid(m_axi_ddr_rid), + .m_axi_ddr_rdata(m_axi_ddr_rdata), + .m_axi_ddr_rresp(m_axi_ddr_rresp), + .m_axi_ddr_rlast(m_axi_ddr_rlast), + .m_axi_ddr_ruser(0), + .m_axi_ddr_rvalid(m_axi_ddr_rvalid), + .m_axi_ddr_rready(m_axi_ddr_rready), + + .ddr_status(ddr_status), + + /* + * HBM + */ + .hbm_clk(0), + .hbm_rst(0), + + .m_axi_hbm_awid(), + .m_axi_hbm_awaddr(), + .m_axi_hbm_awlen(), + .m_axi_hbm_awsize(), + .m_axi_hbm_awburst(), + .m_axi_hbm_awlock(), + .m_axi_hbm_awcache(), + .m_axi_hbm_awprot(), + .m_axi_hbm_awqos(), + .m_axi_hbm_awuser(), + .m_axi_hbm_awvalid(), + .m_axi_hbm_awready(0), + .m_axi_hbm_wdata(), + .m_axi_hbm_wstrb(), + .m_axi_hbm_wlast(), + .m_axi_hbm_wuser(), + .m_axi_hbm_wvalid(), + .m_axi_hbm_wready(0), + .m_axi_hbm_bid(0), + .m_axi_hbm_bresp(0), + .m_axi_hbm_buser(0), + .m_axi_hbm_bvalid(0), + .m_axi_hbm_bready(), + .m_axi_hbm_arid(), + .m_axi_hbm_araddr(), + .m_axi_hbm_arlen(), + .m_axi_hbm_arsize(), + .m_axi_hbm_arburst(), + .m_axi_hbm_arlock(), + .m_axi_hbm_arcache(), + .m_axi_hbm_arprot(), + .m_axi_hbm_arqos(), + .m_axi_hbm_aruser(), + .m_axi_hbm_arvalid(), + .m_axi_hbm_arready(0), + .m_axi_hbm_rid(0), + .m_axi_hbm_rdata(0), + .m_axi_hbm_rresp(0), + .m_axi_hbm_rlast(0), + .m_axi_hbm_ruser(0), + .m_axi_hbm_rvalid(0), + .m_axi_hbm_rready(), + + .hbm_status(0), + /* * Statistics input */