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Track ring active state
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parent
c9de7d24d0
commit
5e65a384e2
@ -200,6 +200,7 @@ struct mqnic_ring {
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struct net_device *ndev;
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struct mqnic_priv *priv;
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int ring_index;
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int active;
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u32 hw_ptr_mask;
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u8 __iomem *hw_addr;
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@ -225,6 +226,7 @@ struct mqnic_cq_ring {
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struct napi_struct napi;
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int ring_index;
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int eq_index;
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int active;
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void (*handler)(struct mqnic_cq_ring *ring);
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@ -251,6 +253,7 @@ struct mqnic_eq_ring {
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struct mqnic_priv *priv;
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int ring_index;
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int int_index;
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int active;
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int irq;
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@ -50,6 +50,7 @@ int mqnic_create_cq_ring(struct mqnic_priv *priv, struct mqnic_cq_ring **ring_pt
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ring->priv = priv;
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ring->ring_index = index;
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ring->active = 0;
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ring->size = roundup_pow_of_two(size);
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ring->size_mask = ring->size - 1;
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@ -98,7 +99,8 @@ void mqnic_destroy_cq_ring(struct mqnic_cq_ring **ring_ptr)
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struct mqnic_cq_ring *ring = *ring_ptr;
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*ring_ptr = NULL;
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mqnic_deactivate_cq_ring(ring);
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if (ring->active)
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mqnic_deactivate_cq_ring(ring);
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dma_free_coherent(ring->priv->dev, ring->buf_size, ring->buf, ring->buf_dma_addr);
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kfree(ring);
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@ -106,6 +108,9 @@ void mqnic_destroy_cq_ring(struct mqnic_cq_ring **ring_ptr)
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int mqnic_activate_cq_ring(struct mqnic_cq_ring *ring, int eq_index)
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{
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if (ring->active)
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mqnic_deactivate_cq_ring(ring);
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ring->eq_index = eq_index;
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// deactivate queue
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@ -122,6 +127,8 @@ int mqnic_activate_cq_ring(struct mqnic_cq_ring *ring, int eq_index)
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iowrite32(ilog2(ring->size) | MQNIC_CPL_QUEUE_ACTIVE_MASK,
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ring->hw_addr + MQNIC_CPL_QUEUE_ACTIVE_LOG_SIZE_REG);
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ring->active = 1;
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return 0;
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}
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@ -131,6 +138,8 @@ void mqnic_deactivate_cq_ring(struct mqnic_cq_ring *ring)
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iowrite32(ilog2(ring->size), ring->hw_addr + MQNIC_CPL_QUEUE_ACTIVE_LOG_SIZE_REG);
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// disarm queue
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iowrite32(ring->eq_index, ring->hw_addr + MQNIC_CPL_QUEUE_INTERRUPT_INDEX_REG);
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ring->active = 0;
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}
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bool mqnic_is_cq_ring_empty(const struct mqnic_cq_ring *ring)
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@ -50,6 +50,7 @@ int mqnic_create_eq_ring(struct mqnic_priv *priv, struct mqnic_eq_ring **ring_pt
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ring->priv = priv;
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ring->ring_index = index;
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ring->active = 0;
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ring->size = roundup_pow_of_two(size);
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ring->size_mask = ring->size - 1;
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@ -101,7 +102,8 @@ void mqnic_destroy_eq_ring(struct mqnic_eq_ring **ring_ptr)
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struct device *dev = ring->priv->dev;
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*ring_ptr = NULL;
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mqnic_deactivate_eq_ring(ring);
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if (ring->active)
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mqnic_deactivate_eq_ring(ring);
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dma_free_coherent(dev, ring->buf_size, ring->buf, ring->buf_dma_addr);
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kfree(ring);
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@ -109,6 +111,9 @@ void mqnic_destroy_eq_ring(struct mqnic_eq_ring **ring_ptr)
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int mqnic_activate_eq_ring(struct mqnic_eq_ring *ring, int int_index)
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{
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if (ring->active)
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mqnic_deactivate_eq_ring(ring);
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ring->int_index = int_index;
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// deactivate queue
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@ -127,6 +132,8 @@ int mqnic_activate_eq_ring(struct mqnic_eq_ring *ring, int int_index)
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iowrite32(ilog2(ring->size) | MQNIC_EVENT_QUEUE_ACTIVE_MASK,
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ring->hw_addr + MQNIC_EVENT_QUEUE_ACTIVE_LOG_SIZE_REG);
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ring->active = 1;
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return 0;
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}
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@ -136,6 +143,8 @@ void mqnic_deactivate_eq_ring(struct mqnic_eq_ring *ring)
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iowrite32(ilog2(ring->size), ring->hw_addr + MQNIC_EVENT_QUEUE_ACTIVE_LOG_SIZE_REG);
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// disarm queue
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iowrite32(ring->int_index, ring->hw_addr + MQNIC_EVENT_QUEUE_INTERRUPT_INDEX_REG);
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ring->active = 0;
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}
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bool mqnic_is_eq_ring_empty(const struct mqnic_eq_ring *ring)
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@ -51,6 +51,7 @@ int mqnic_create_rx_ring(struct mqnic_priv *priv, struct mqnic_ring **ring_ptr,
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ring->priv = priv;
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ring->ring_index = index;
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ring->active = 0;
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ring->size = roundup_pow_of_two(size);
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ring->size_mask = ring->size - 1;
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@ -114,7 +115,8 @@ void mqnic_destroy_rx_ring(struct mqnic_ring **ring_ptr)
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struct mqnic_ring *ring = *ring_ptr;
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*ring_ptr = NULL;
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mqnic_deactivate_rx_ring(ring);
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if (ring->active)
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mqnic_deactivate_rx_ring(ring);
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mqnic_free_rx_buf(ring);
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@ -126,6 +128,9 @@ void mqnic_destroy_rx_ring(struct mqnic_ring **ring_ptr)
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int mqnic_activate_rx_ring(struct mqnic_ring *ring, int cpl_index)
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{
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if (ring->active)
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mqnic_deactivate_rx_ring(ring);
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// deactivate queue
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iowrite32(0, ring->hw_addr + MQNIC_QUEUE_ACTIVE_LOG_SIZE_REG);
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// set base address
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@ -140,6 +145,8 @@ int mqnic_activate_rx_ring(struct mqnic_ring *ring, int cpl_index)
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iowrite32(ilog2(ring->size) | (ring->log_desc_block_size << 8) | MQNIC_QUEUE_ACTIVE_MASK,
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ring->hw_addr + MQNIC_QUEUE_ACTIVE_LOG_SIZE_REG);
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ring->active = 1;
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mqnic_refill_rx_buffers(ring);
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return 0;
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@ -150,6 +157,8 @@ void mqnic_deactivate_rx_ring(struct mqnic_ring *ring)
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// deactivate queue
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iowrite32(ilog2(ring->size) | (ring->log_desc_block_size << 8),
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ring->hw_addr + MQNIC_QUEUE_ACTIVE_LOG_SIZE_REG);
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ring->active = 0;
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}
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bool mqnic_is_rx_ring_empty(const struct mqnic_ring *ring)
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@ -52,6 +52,7 @@ int mqnic_create_tx_ring(struct mqnic_priv *priv, struct mqnic_ring **ring_ptr,
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ring->priv = priv;
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ring->ring_index = index;
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ring->active = 0;
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ring->size = roundup_pow_of_two(size);
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ring->full_size = ring->size >> 1;
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@ -116,7 +117,8 @@ void mqnic_destroy_tx_ring(struct mqnic_ring **ring_ptr)
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struct mqnic_ring *ring = *ring_ptr;
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*ring_ptr = NULL;
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mqnic_deactivate_tx_ring(ring);
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if (ring->active)
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mqnic_deactivate_tx_ring(ring);
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mqnic_free_tx_buf(ring);
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@ -128,6 +130,9 @@ void mqnic_destroy_tx_ring(struct mqnic_ring **ring_ptr)
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int mqnic_activate_tx_ring(struct mqnic_ring *ring, int cpl_index)
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{
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if (ring->active)
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mqnic_deactivate_tx_ring(ring);
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// deactivate queue
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iowrite32(0, ring->hw_addr + MQNIC_QUEUE_ACTIVE_LOG_SIZE_REG);
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// set base address
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@ -142,6 +147,8 @@ int mqnic_activate_tx_ring(struct mqnic_ring *ring, int cpl_index)
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iowrite32(ilog2(ring->size) | (ring->log_desc_block_size << 8) | MQNIC_QUEUE_ACTIVE_MASK,
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ring->hw_addr + MQNIC_QUEUE_ACTIVE_LOG_SIZE_REG);
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ring->active = 1;
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return 0;
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}
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@ -150,6 +157,8 @@ void mqnic_deactivate_tx_ring(struct mqnic_ring *ring)
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// deactivate queue
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iowrite32(ilog2(ring->size) | (ring->log_desc_block_size << 8),
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ring->hw_addr + MQNIC_QUEUE_ACTIVE_LOG_SIZE_REG);
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ring->active = 0;
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}
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bool mqnic_is_tx_ring_empty(const struct mqnic_ring *ring)
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