FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-30 08:32:52 +08:00
Code Issues Projects Releases Wiki Activity

merged changes in axi

Browse Source
This commit is contained in:
Alex Forencich 2021-05-20 15:17:25 -07:00
commit 5ebc741ffe
20 changed files with 206 additions and 172 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

132
fpga/lib/axi/README.md
View File

@ -9,69 +9,71 @@ GitHub repository: https://github.com/alexforencich/verilog-axi
## Introduction
Collection of AXI4 and AXI4 lite bus components. Most components are fully
parametrizable in interface widths. Includes full cocotb testbench that
utilizes [cocotbext-axi](https://github.com/alexforencich/cocotbext-axi).
parametrizable in interface widths. Includes full cocotb testbenches that
utilize [cocotbext-axi](https://github.com/alexforencich/cocotbext-axi).
## Documentation
### axi_adapter module
### `axi_adapter` module
AXI width adapter module with parametrizable data and address interface widths.
Supports INCR burst types and narrow bursts. Wrapper for axi_adapter_rd and axi_adapter_wr.
Supports INCR burst types and narrow bursts. Wrapper for `axi_adapter_rd` and `axi_adapter_wr`.
### axi_adapter_rd module
### `axi_adapter_rd` module
AXI width adapter module with parametrizable data and address interface widths.
Supports INCR burst types and narrow bursts.
### axi_adapter_wr module
### `axi_adapter_wr` module
AXI width adapter module with parametrizable data and address interface widths.
Supports INCR burst types and narrow bursts.
### axi_axil_adapter module
### `axi_axil_adapter` module
AXI to AXI lite converter and width adapter module with parametrizable data
and address interface widths. Supports INCR burst types and narrow bursts.
Wrapper for axi_axil_adapter_rd and axi_axil_adapter_wr.
Wrapper for `axi_axil_adapter_rd` and `axi_axil_adapter_wr`.
### axi_axil_adapter_rd module
### `axi_axil_adapter_rd` module
AXI to AXI lite converter and width adapter module with parametrizable data
and address interface widths. Supports INCR burst types and narrow bursts.
### axi_axil_adapter_wr module
### `axi_axil_adapter_wr` module
AXI to AXI lite converter and width adapter module with parametrizable data
and address interface widths. Supports INCR burst types and narrow bursts.
### axi_cdma module
### `axi_cdma` module
AXI to AXI DMA engine with parametrizable data and address interface widths.
Generates full-width INCR bursts only, with parametrizable maximum burst
length. Supports unaligned transfers, which can be disabled via parameter
to save on resource consumption.
### axi_cdma_desc_mux module
### `axi_cdma_desc_mux` module
Descriptor multiplexer/demultiplexer for AXI CDMA module. Enables sharing the
AXI CDMA module between multiple request sources, interleaving requests and
distributing responses.
### axi_crossbar module
### `axi_crossbar` module
AXI nonblocking crossbar interconnect with parametrizable data and address
interface widths and master and slave interface counts. Supports all burst
types. Fully nonblocking with completely separate read and write paths; ID
based transaction ordering protection logic; and per-port address decode,
admission control, and decode error handling. Wrapper for axi_crossbar_rd and
axi_crossbar_wr.
admission control, and decode error handling. Wrapper for `axi_crossbar_rd`
and `axi_crossbar_wr`.
### axi_crossbar_addr module
Wrappers can generated with `axi_crossbar_wrap.py`.
### `axi_crossbar_addr` module
Address decode and admission control module for AXI nonblocking crossbar interconnect.
### axi_crossbar_rd module
### `axi_crossbar_rd` module
AXI nonblocking crossbar interconnect with parametrizable data and address
interface widths and master and slave interface counts. Read interface only.
@ -79,7 +81,7 @@ Supports all burst types. Fully nonblocking with completely separate read and
write paths; ID based transaction ordering protection logic; and per-port
address decode, admission control, and decode error handling.
### axi_crossbar_wr module
### `axi_crossbar_wr` module
AXI nonblocking crossbar interconnect with parametrizable data and address
interface widths and master and slave interface counts. Write interface only.
@ -87,140 +89,168 @@ Supports all burst types. Fully nonblocking with completely separate read and
write paths; ID based transaction ordering protection logic; and per-port
address decode, admission control, and decode error handling.
### axi_dma module
### `axi_dma` module
AXI to AXI stream DMA engine with parametrizable data and address interface
widths. Generates full-width INCR bursts only, with parametrizable maximum
burst length. Supports unaligned transfers, which can be disabled via
parameter to save on resource consumption. Wrapper for axi_dma_rd and
axi_dma_wr.
parameter to save on resource consumption. Wrapper for `axi_dma_rd` and
`axi_dma_wr`.
### axi_dma_desc_mux module
### `axi_dma_desc_mux` module
Descriptor multiplexer/demultiplexer for AXI DMA module. Enables sharing the
AXI DMA module between multiple request sources, interleaving requests and
distributing responses.
### axi_dma_rd module
### `axi_dma_rd` module
AXI to AXI stream DMA engine with parametrizable data and address interface
widths. Generates full-width INCR bursts only, with parametrizable maximum
burst length. Supports unaligned transfers, which can be disabled via
parameter to save on resource consumption.
### axi_dma_wr module
### `axi_dma_wr` module
AXI stream to AXI DMA engine with parametrizable data and address interface
widths. Generates full-width INCR bursts only, with parametrizable maximum
burst length. Supports unaligned transfers, which can be disabled via
parameter to save on resource consumption.
### axi_fifo module
### `axi_dp_ram` module
AXI dual-port RAM with parametrizable data and address interface widths.
Supports FIXED and INCR burst types as well as narrow bursts.
### `axi_fifo` module
AXI FIFO with parametrizable data and address interface widths. Supports all
burst types. Optionally can delay the address channel until either the write
data is completely shifted into the FIFO or the read data FIFO has enough
capacity to fit the whole burst. Wrapper for axi_fifo_rd and axi_fifo_wr.
capacity to fit the whole burst. Wrapper for `axi_fifo_rd` and `axi_fifo_wr`.
### axi_fifo_rd module
### `axi_fifo_rd` module
AXI FIFO with parametrizable data and address interface widths. AR and R
channels only. Supports all burst types. Optionally can delay the address
channel until either the read data FIFO is empty or has enough capacity to fit
the whole burst.
### axi_fifo_wr module
### `axi_fifo_wr` module
AXI FIFO with parametrizable data and address interface widths. WR, W, and B
channels only. Supports all burst types. Optionally can delay the address
channel until the write data is shifted completely into the write data FIFO,
or the current burst completely fills the write data FIFO.
### axi_interconnect module
### `axi_interconnect` module
AXI shared interconnect with parametrizable data and address interface
widths and master and slave interface counts. Supports all burst types.
Small in area, but does not support concurrent operations.
### axi_ram module
Wrappers can generated with `axi_interconnect_wrap.py`.
AXI RAM with parametrizable data and address interface widths. Supports FIXED
### `axi_ram` module
AXI RAM with parametrizable data and address interface widths. Supports FIXED
and INCR burst types as well as narrow bursts.
### axi_register module
### `axi_ram_rd_if` module
AXI RAM read interface with parametrizable data and address interface widths.
Handles bursts and presents a simplified internal memory interface. Supports
FIXED and INCR burst types as well as narrow bursts.
### `axi_ram_wr_if` module
AXI RAM write interface with parametrizable data and address interface widths.
Handles bursts and presents a simplified internal memory interface. Supports
FIXED and INCR burst types as well as narrow bursts.
### `axi_ram_wr_rd_if` module
AXI RAM read/write interface with parametrizable data and address interface
widths. Handles bursts and presents a simplified internal memory interface.
Supports FIXED and INCR burst types as well as narrow bursts. Wrapper for
`axi_ram_rd_if` and `axi_ram_wr_if`.
### `axi_register` module
AXI register with parametrizable data and address interface widths. Supports
all burst types. Inserts simple buffers or skid buffers into all channels.
Channel register types can be individually changed or bypassed. Wrapper for
axi_register_rd and axi_register_wr.
`axi_register_rd` and `axi_register_wr`.
### axi_register_rd module
### `axi_register_rd` module
AXI register with parametrizable data and address interface widths. AR and R
channels only. Supports all burst types. Inserts simple buffers or skid
buffers into all channels. Channel register types can be individually changed
or bypassed.
### axi_register_wr module
### `axi_register_wr` module
AXI register with parametrizable data and address interface widths. WR, W,
and B channels only. Supports all burst types. Inserts simple buffers or
skid buffers into all channels. Channel register types can be individually
changed or bypassed.
### axil_adapter module
### `axil_adapter` module
AXI lite width adapter module with parametrizable data and address interface
widths. Wrapper for axi_adapter_rd and axi_adapter_wr.
widths. Wrapper for `axi_adapter_rd` and `axi_adapter_wr`.
### axil_adapter_rd module
### `axil_adapter_rd` module
AXI lite width adapter module with parametrizable data and address interface
widths.
### axil_adapter_wr module
### `axil_adapter_wr` module
AXI lite width adapter module with parametrizable data and address interface
widths.
### axil_cdc module
### `axil_cdc` module
AXI lite clock domain crossing module with parametrizable data and address
interface widths. Wrapper for axi_cdc_rd and axi_cdc_wr.
interface widths. Wrapper for `axi_cdc_rd` and `axi_cdc_wr`.
### axil_cdc_rd module
### `axil_cdc_rd` module
AXI lite clock domain crossing module with parametrizable data and address
interface widths.
### axil_cdc_wr module
### `axil_cdc_wr` module
AXI lite clock domain crossing module with parametrizable data and address
interface widths.
### axil_interconnect module
### `axil_interconnect` module
AXI lite shared interconnect with parametrizable data and address interface
widths and master and slave interface counts. Small in area, but does not
support concurrent operations.
### axil_ram module
Wrappers can generated with `axil_interconnect_wrap.py`.
### `axil_ram` module
AXI lite RAM with parametrizable data and address interface widths.
### axil_register module
### `axil_register` module
AXI lite register with parametrizable data and address interface widths.
Inserts skid buffers into all channels. Channel registers can be individually
bypassed. Wrapper for axil_register_rd and axil_register_wr.
bypassed. Wrapper for `axil_register_rd` and `axil_register_wr`.
### axil_register_rd module
### `axil_register_rd` module
AXI lite register with parametrizable data and address interface widths. AR
and R channels only. Inserts simple buffers into all channels. Channel
registers can be individually bypassed.
### axil_register_wr module
### `axil_register_wr` module
AXI lite register with parametrizable data and address interface widths. WR,
W, and B channels only. Inserts simple buffers into all channels. Channel
@ -309,11 +339,15 @@ registers can be individually bypassed.
rtl/axi_dma_desc_mux.v : AXI DMA descriptor mux
rtl/axi_dma_rd.v : AXI DMA engine (read)
rtl/axi_dma_wr.v : AXI DMA engine (write)
rtl/axi_dp_ram.v : AXI dual-port RAM
rtl/axi_fifo.v : AXI FIFO
rtl/axi_fifo_rd.v : AXI FIFO (read)
rtl/axi_fifo_wr.v : AXI FIFO (write)
rtl/axi_interconnect.v : AXI shared interconnect
rtl/axi_ram.v : AXI RAM
rtl/axi_ram_rd_if.v : AXI RAM read interface
rtl/axi_ram_wr_if.v : AXI RAM write interface
rtl/axi_ram_wr_rd_if.v : AXI RAM read/write interface
rtl/axi_register.v : AXI register
rtl/axi_register_rd.v : AXI register (read)
rtl/axi_register_wr.v : AXI register (write)

0
fpga/lib/axi/syn/axil_cdc.tcl → fpga/lib/axi/syn/vivado/axil_cdc.tcl
View File

16
fpga/lib/axi/tb/axi_adapter/test_axi_adapter.py
View File

@ -82,7 +82,7 @@ async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_ins
tb = TB(dut)
byte_width = tb.axi_master.write_if.byte_width
byte_lanes = tb.axi_master.write_if.byte_lanes
max_burst_size = tb.axi_master.write_if.max_burst_size
if size is None:
@ -93,8 +93,8 @@ async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_ins
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in list(range(1, byte_width*2))+[1024]:
for offset in list(range(byte_width, byte_width*2))+list(range(4096-byte_width, 4096)):
for length in list(range(1, byte_lanes*2))+[1024]:
for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
tb.log.info("length %d, offset %d, size %d", length, offset, size)
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
@ -117,7 +117,7 @@ async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inse
tb = TB(dut)
byte_width = tb.axi_master.write_if.byte_width
byte_lanes = tb.axi_master.write_if.byte_lanes
max_burst_size = tb.axi_master.write_if.max_burst_size
if size is None:
@ -128,8 +128,8 @@ async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inse
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in list(range(1, byte_width*2))+[1024]:
for offset in list(range(byte_width, byte_width*2))+[4096-byte_width]:
for length in list(range(1, byte_lanes*2))+[1024]:
for offset in list(range(byte_lanes, byte_lanes*2))+[4096-byte_lanes]:
tb.log.info("length %d, offset %d, size %d", length, offset, size)
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
@ -187,8 +187,8 @@ def cycle_pause():
if cocotb.SIM_NAME:
data_width = len(cocotb.top.s_axi_wdata)
byte_width = data_width // 8
max_burst_size = (byte_width-1).bit_length()
byte_lanes = data_width // 8
max_burst_size = (byte_lanes-1).bit_length()
for test in [run_test_write, run_test_read]:

20
fpga/lib/axi/tb/axi_axil_adapter/test_axi_axil_adapter.py
View File

@ -82,8 +82,8 @@ async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_ins
tb = TB(dut)
byte_width = tb.axi_master.write_if.byte_width
max_burst_size = (byte_width-1).bit_length()
byte_lanes = tb.axi_master.write_if.byte_lanes
max_burst_size = (byte_lanes-1).bit_length()
if size is None:
size = max_burst_size
@ -93,8 +93,8 @@ async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_ins
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in list(range(1, byte_width*2))+[1024]:
for offset in list(range(byte_width, byte_width*2))+list(range(4096-byte_width, 4096)):
for length in list(range(1, byte_lanes*2))+[1024]:
for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
tb.log.info("length %d, offset %d, size %d", length, offset, size)
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
@ -117,8 +117,8 @@ async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inse
tb = TB(dut)
byte_width = tb.axi_master.write_if.byte_width
max_burst_size = (byte_width-1).bit_length()
byte_lanes = tb.axi_master.write_if.byte_lanes
max_burst_size = (byte_lanes-1).bit_length()
if size is None:
size = max_burst_size
@ -128,8 +128,8 @@ async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inse
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in list(range(1, byte_width*2))+[1024]:
for offset in list(range(byte_width, byte_width*2))+list(range(4096-byte_width, 4096)):
for length in list(range(1, byte_lanes*2))+[1024]:
for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
tb.log.info("length %d, offset %d, size %d", length, offset, size)
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
@ -187,8 +187,8 @@ def cycle_pause():
if cocotb.SIM_NAME:
data_width = len(cocotb.top.s_axi_wdata)
byte_width = data_width // 8
max_burst_size = (byte_width-1).bit_length()
byte_lanes = data_width // 8
max_burst_size = (byte_lanes-1).bit_length()
for test in [run_test_write, run_test_read]:

10
fpga/lib/axi/tb/axi_cdma/test_axi_cdma.py
View File

@ -92,8 +92,8 @@ async def run_test(dut, data_in=None, idle_inserter=None, backpressure_inserter=
tb = TB(dut)
byte_width = tb.axi_ram.write_if.byte_width
step_size = 1 if int(os.getenv("PARAM_ENABLE_UNALIGNED")) else byte_width
byte_lanes = tb.axi_ram.write_if.byte_lanes
step_size = 1 if int(os.getenv("PARAM_ENABLE_UNALIGNED")) else byte_lanes
tag_count = 2**len(tb.desc_source.bus.tag)
cur_tag = 1
@ -105,9 +105,9 @@ async def run_test(dut, data_in=None, idle_inserter=None, backpressure_inserter=
dut.enable <= 1
for length in list(range(1, byte_width*4+1))+[128]:
for read_offset in list(range(8, 8+byte_width*2, step_size))+list(range(4096-byte_width*2, 4096, step_size)):
for write_offset in list(range(8, 8+byte_width*2, step_size))+list(range(4096-byte_width*2, 4096, step_size)):
for length in list(range(1, byte_lanes*4+1))+[128]:
for read_offset in list(range(8, 8+byte_lanes*2, step_size))+list(range(4096-byte_lanes*2, 4096, step_size)):
for write_offset in list(range(8, 8+byte_lanes*2, step_size))+list(range(4096-byte_lanes*2, 4096, step_size)):
tb.log.info("length %d, read_offset %d, write_offset %d", length, read_offset, write_offset)
read_addr = read_offset+0x1000
write_addr = 0x00008000+write_offset+0x1000

16
fpga/lib/axi/tb/axi_crossbar/test_axi_crossbar.py
View File

@ -96,7 +96,7 @@ async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_ins
tb = TB(dut)
byte_width = tb.axi_master[s].write_if.byte_width
byte_lanes = tb.axi_master[s].write_if.byte_lanes
max_burst_size = tb.axi_master[s].write_if.max_burst_size
if size is None:
@ -107,8 +107,8 @@ async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_ins
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in list(range(1, byte_width*2))+[1024]:
for offset in list(range(byte_width, byte_width*2))+list(range(4096-byte_width, 4096)):
for length in list(range(1, byte_lanes*2))+[1024]:
for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
tb.log.info("length %d, offset %d, size %d", length, offset, size)
ram_addr = offset+0x1000
addr = ram_addr + m*0x1000000
@ -132,7 +132,7 @@ async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inse
tb = TB(dut)
byte_width = tb.axi_master[s].write_if.byte_width
byte_lanes = tb.axi_master[s].write_if.byte_lanes
max_burst_size = tb.axi_master[s].write_if.max_burst_size
if size is None:
@ -143,8 +143,8 @@ async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inse
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in list(range(1, byte_width*2))+[1024]:
for offset in list(range(byte_width, byte_width*2))+list(range(4096-byte_width, 4096)):
for length in list(range(1, byte_lanes*2))+[1024]:
for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
tb.log.info("length %d, offset %d, size %d", length, offset, size)
ram_addr = offset+0x1000
addr = ram_addr + m*0x1000000
@ -207,8 +207,8 @@ if cocotb.SIM_NAME:
m_count = int(os.getenv("PARAM_M_COUNT"))
data_width = len(cocotb.top.s00_axi_wdata)
byte_width = data_width // 8
max_burst_size = (byte_width-1).bit_length()
byte_lanes = data_width // 8
max_burst_size = (byte_lanes-1).bit_length()
for test in [run_test_write, run_test_read]:

16
fpga/lib/axi/tb/axi_dma/test_axi_dma.py
View File

@ -107,8 +107,8 @@ async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_ins
tb = TB(dut)
byte_width = tb.axi_ram.write_if.byte_width
step_size = 1 if int(os.getenv("PARAM_ENABLE_UNALIGNED")) else byte_width
byte_lanes = tb.axi_ram.write_if.byte_lanes
step_size = 1 if int(os.getenv("PARAM_ENABLE_UNALIGNED")) else byte_lanes
tag_count = 2**len(tb.write_desc_source.bus.tag)
cur_tag = 1
@ -120,8 +120,8 @@ async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_ins
dut.write_enable <= 1
for length in list(range(1, byte_width*4+1))+[128]:
for offset in list(range(0, byte_width*2, step_size))+list(range(4096-byte_width*2, 4096, step_size)):
for length in list(range(1, byte_lanes*4+1))+[128]:
for offset in list(range(0, byte_lanes*2, step_size))+list(range(4096-byte_lanes*2, 4096, step_size)):
for diff in [-8, -2, -1, 0, 1, 2, 8]:
if length+diff < 1:
continue
@ -162,8 +162,8 @@ async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inse
tb = TB(dut)
byte_width = tb.axi_ram.read_if.byte_width
step_size = 1 if int(os.getenv("PARAM_ENABLE_UNALIGNED")) else byte_width
byte_lanes = tb.axi_ram.read_if.byte_lanes
step_size = 1 if int(os.getenv("PARAM_ENABLE_UNALIGNED")) else byte_lanes
tag_count = 2**len(tb.read_desc_source.bus.tag)
cur_tag = 1
@ -175,8 +175,8 @@ async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inse
dut.read_enable <= 1
for length in list(range(1, byte_width*4+1))+[128]:
for offset in list(range(0, byte_width*2, step_size))+list(range(4096-byte_width*2, 4096, step_size)):
for length in list(range(1, byte_lanes*4+1))+[128]:
for offset in list(range(0, byte_lanes*2, step_size))+list(range(4096-byte_lanes*2, 4096, step_size)):
tb.log.info("length %d, offset %d", length, offset)
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])

8
fpga/lib/axi/tb/axi_dma_rd/test_axi_dma_rd.py
View File

@ -94,8 +94,8 @@ async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inse
tb = TB(dut)
byte_width = tb.axi_ram.byte_width
step_size = 1 if int(os.getenv("PARAM_ENABLE_UNALIGNED")) else byte_width
byte_lanes = tb.axi_ram.byte_lanes
step_size = 1 if int(os.getenv("PARAM_ENABLE_UNALIGNED")) else byte_lanes
tag_count = 2**len(tb.read_desc_source.bus.tag)
cur_tag = 1
@ -107,8 +107,8 @@ async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inse
dut.enable <= 1
for length in list(range(1, byte_width*4+1))+[128]:
for offset in list(range(0, byte_width*2, step_size))+list(range(4096-byte_width*2, 4096, step_size)):
for length in list(range(1, byte_lanes*4+1))+[128]:
for offset in list(range(0, byte_lanes*2, step_size))+list(range(4096-byte_lanes*2, 4096, step_size)):
tb.log.info("length %d, offset %d", length, offset)
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])

8
fpga/lib/axi/tb/axi_dma_wr/test_axi_dma_wr.py
View File

@ -95,8 +95,8 @@ async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_ins
tb = TB(dut)
byte_width = tb.axi_ram.byte_width
step_size = 1 if int(os.getenv("PARAM_ENABLE_UNALIGNED")) else byte_width
byte_lanes = tb.axi_ram.byte_lanes
step_size = 1 if int(os.getenv("PARAM_ENABLE_UNALIGNED")) else byte_lanes
tag_count = 2**len(tb.write_desc_source.bus.tag)
cur_tag = 1
@ -108,8 +108,8 @@ async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_ins
dut.enable <= 1
for length in list(range(1, byte_width*4+1))+[128]:
for offset in list(range(0, byte_width*2, step_size))+list(range(4096-byte_width*2, 4096, step_size)):
for length in list(range(1, byte_lanes*4+1))+[128]:
for offset in list(range(0, byte_lanes*2, step_size))+list(range(4096-byte_lanes*2, 4096, step_size)):
for diff in [-8, -2, -1, 0, 1, 2, 8]:
if length+diff < 1:
continue

16
fpga/lib/axi/tb/axi_dp_ram/test_axi_dp_ram.py
View File

@ -87,7 +87,7 @@ async def run_test_write(dut, port=0, data_in=None, idle_inserter=None, backpres
tb = TB(dut)
axi_master = tb.axi_master[port]
byte_width = axi_master.write_if.byte_width
byte_lanes = axi_master.write_if.byte_lanes
max_burst_size = axi_master.write_if.max_burst_size
if size is None:
@ -98,8 +98,8 @@ async def run_test_write(dut, port=0, data_in=None, idle_inserter=None, backpres
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in list(range(1, byte_width*2))+[1024]:
for offset in list(range(byte_width, byte_width*2))+list(range(4096-byte_width, 4096)):
for length in list(range(1, byte_lanes*2))+[1024]:
for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
tb.log.info("length %d, offset %d, size %d", length, offset, size)
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
@ -121,7 +121,7 @@ async def run_test_read(dut, port=0, data_in=None, idle_inserter=None, backpress
tb = TB(dut)
axi_master = tb.axi_master[port]
byte_width = axi_master.write_if.byte_width
byte_lanes = axi_master.write_if.byte_lanes
max_burst_size = axi_master.write_if.max_burst_size
if size is None:
@ -132,8 +132,8 @@ async def run_test_read(dut, port=0, data_in=None, idle_inserter=None, backpress
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in list(range(1, byte_width*2))+[1024]:
for offset in list(range(byte_width, byte_width*2))+list(range(4096-byte_width, 4096)):
for length in list(range(1, byte_lanes*2))+[1024]:
for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
tb.log.info("length %d, offset %d, size %d", length, offset, size)
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
@ -220,8 +220,8 @@ def cycle_pause():
if cocotb.SIM_NAME:
data_width = len(cocotb.top.s_axi_a_wdata)
byte_width = data_width // 8
max_burst_size = (byte_width-1).bit_length()
byte_lanes = data_width // 8
max_burst_size = (byte_lanes-1).bit_length()
for test in [run_test_write, run_test_read]:

16
fpga/lib/axi/tb/axi_fifo/test_axi_fifo.py
View File

@ -82,7 +82,7 @@ async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_ins
tb = TB(dut)
byte_width = tb.axi_master.write_if.byte_width
byte_lanes = tb.axi_master.write_if.byte_lanes
max_burst_size = tb.axi_master.write_if.max_burst_size
if size is None:
@ -93,8 +93,8 @@ async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_ins
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in list(range(1, byte_width*2))+[1024]:
for offset in list(range(byte_width, byte_width*2))+list(range(4096-byte_width, 4096)):
for length in list(range(1, byte_lanes*2))+[1024]:
for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
tb.log.info("length %d, offset %d", length, offset)
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
@ -117,7 +117,7 @@ async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inse
tb = TB(dut)
byte_width = tb.axi_master.write_if.byte_width
byte_lanes = tb.axi_master.write_if.byte_lanes
max_burst_size = tb.axi_master.write_if.max_burst_size
if size is None:
@ -128,8 +128,8 @@ async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inse
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in list(range(1, byte_width*2))+[1024]:
for offset in list(range(byte_width, byte_width*2))+list(range(4096-byte_width, 4096)):
for length in list(range(1, byte_lanes*2))+[1024]:
for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
tb.log.info("length %d, offset %d", length, offset)
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
@ -188,8 +188,8 @@ def cycle_pause():
if cocotb.SIM_NAME:
data_width = len(cocotb.top.s_axi_wdata)
byte_width = data_width // 8
max_burst_size = (byte_width-1).bit_length()
byte_lanes = data_width // 8
max_burst_size = (byte_lanes-1).bit_length()
for test in [run_test_write, run_test_read]:

16
fpga/lib/axi/tb/axi_interconnect/test_axi_interconnect.py
View File

@ -90,7 +90,7 @@ async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_ins
tb = TB(dut)
byte_width = tb.axi_master[s].write_if.byte_width
byte_lanes = tb.axi_master[s].write_if.byte_lanes
max_burst_size = tb.axi_master[s].write_if.max_burst_size
if size is None:
@ -101,8 +101,8 @@ async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_ins
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in list(range(1, byte_width*2))+[1024]:
for offset in list(range(byte_width, byte_width*2))+list(range(4096-byte_width, 4096)):
for length in list(range(1, byte_lanes*2))+[1024]:
for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
tb.log.info("length %d, offset %d, size %d", length, offset, size)
ram_addr = offset+0x1000
addr = ram_addr + m*0x1000000
@ -126,7 +126,7 @@ async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inse
tb = TB(dut)
byte_width = tb.axi_master[s].write_if.byte_width
byte_lanes = tb.axi_master[s].write_if.byte_lanes
max_burst_size = tb.axi_master[s].write_if.max_burst_size
if size is None:
@ -137,8 +137,8 @@ async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inse
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in list(range(1, byte_width*2))+[1024]:
for offset in list(range(byte_width, byte_width*2))+list(range(4096-byte_width, 4096)):
for length in list(range(1, byte_lanes*2))+[1024]:
for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
tb.log.info("length %d, offset %d, size %d", length, offset, size)
ram_addr = offset+0x1000
addr = ram_addr + m*0x1000000
@ -201,8 +201,8 @@ if cocotb.SIM_NAME:
m_count = int(os.getenv("PARAM_M_COUNT"))
data_width = len(cocotb.top.s00_axi_wdata)
byte_width = data_width // 8
max_burst_size = (byte_width-1).bit_length()
byte_lanes = data_width // 8
max_burst_size = (byte_lanes-1).bit_length()
for test in [run_test_write, run_test_read]:

16
fpga/lib/axi/tb/axi_ram/test_axi_ram.py
View File

@ -76,7 +76,7 @@ async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_ins
tb = TB(dut)
byte_width = tb.axi_master.write_if.byte_width
byte_lanes = tb.axi_master.write_if.byte_lanes
max_burst_size = tb.axi_master.write_if.max_burst_size
if size is None:
@ -87,8 +87,8 @@ async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_ins
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in list(range(1, byte_width*2))+[1024]:
for offset in list(range(byte_width, byte_width*2))+list(range(4096-byte_width, 4096)):
for length in list(range(1, byte_lanes*2))+[1024]:
for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
tb.log.info("length %d, offset %d, size %d", length, offset, size)
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
@ -109,7 +109,7 @@ async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inse
tb = TB(dut)
byte_width = tb.axi_master.write_if.byte_width
byte_lanes = tb.axi_master.write_if.byte_lanes
max_burst_size = tb.axi_master.write_if.max_burst_size
if size is None:
@ -120,8 +120,8 @@ async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inse
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in list(range(1, byte_width*2))+[1024]:
for offset in list(range(byte_width, byte_width*2))+list(range(4096-byte_width, 4096)):
for length in list(range(1, byte_lanes*2))+[1024]:
for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
tb.log.info("length %d, offset %d, size %d", length, offset, size)
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
@ -179,8 +179,8 @@ def cycle_pause():
if cocotb.SIM_NAME:
data_width = len(cocotb.top.s_axi_wdata)
byte_width = data_width // 8
max_burst_size = (byte_width-1).bit_length()
byte_lanes = data_width // 8
max_burst_size = (byte_lanes-1).bit_length()
for test in [run_test_write, run_test_read]:

16
fpga/lib/axi/tb/axi_register/test_axi_register.py
View File

@ -82,7 +82,7 @@ async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_ins
tb = TB(dut)
byte_width = tb.axi_master.write_if.byte_width
byte_lanes = tb.axi_master.write_if.byte_lanes
max_burst_size = tb.axi_master.write_if.max_burst_size
if size is None:
@ -93,8 +93,8 @@ async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_ins
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in list(range(1, byte_width*2))+[1024]:
for offset in list(range(byte_width, byte_width*2))+list(range(4096-byte_width, 4096)):
for length in list(range(1, byte_lanes*2))+[1024]:
for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
tb.log.info("length %d, offset %d, size %d", length, offset, size)
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
@ -117,7 +117,7 @@ async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inse
tb = TB(dut)
byte_width = tb.axi_master.write_if.byte_width
byte_lanes = tb.axi_master.write_if.byte_lanes
max_burst_size = tb.axi_master.write_if.max_burst_size
if size is None:
@ -128,8 +128,8 @@ async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inse
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in list(range(1, byte_width*2))+[1024]:
for offset in list(range(byte_width, byte_width*2))+list(range(4096-byte_width, 4096)):
for length in list(range(1, byte_lanes*2))+[1024]:
for offset in list(range(byte_lanes, byte_lanes*2))+list(range(4096-byte_lanes, 4096)):
tb.log.info("length %d, offset %d, size %d", length, offset, size)
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
@ -187,8 +187,8 @@ def cycle_pause():
if cocotb.SIM_NAME:
data_width = len(cocotb.top.s_axi_wdata)
byte_width = data_width // 8
max_burst_size = (byte_width-1).bit_length()
byte_lanes = data_width // 8
max_burst_size = (byte_lanes-1).bit_length()
for test in [run_test_write, run_test_read]:

12
fpga/lib/axi/tb/axil_adapter/test_axil_adapter.py
View File

@ -82,15 +82,15 @@ async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_ins
tb = TB(dut)
byte_width = tb.axil_master.write_if.byte_width
byte_lanes = tb.axil_master.write_if.byte_lanes
await tb.cycle_reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in range(1, byte_width*2):
for offset in range(byte_width):
for length in range(1, byte_lanes*2):
for offset in range(byte_lanes):
tb.log.info("length %d, offset %d", length, offset)
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
@ -113,15 +113,15 @@ async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inse
tb = TB(dut)
byte_width = tb.axil_master.write_if.byte_width
byte_lanes = tb.axil_master.write_if.byte_lanes
await tb.cycle_reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in range(1, byte_width*2):
for offset in range(byte_width):
for length in range(1, byte_lanes*2):
for offset in range(byte_lanes):
tb.log.info("length %d, offset %d", length, offset)
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])

12
fpga/lib/axi/tb/axil_cdc/test_axil_cdc.py
View File

@ -87,15 +87,15 @@ async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_ins
tb = TB(dut)
byte_width = tb.axil_master.write_if.byte_width
byte_lanes = tb.axil_master.write_if.byte_lanes
await tb.cycle_reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in range(1, byte_width*2):
for offset in range(byte_width):
for length in range(1, byte_lanes*2):
for offset in range(byte_lanes):
tb.log.info("length %d, offset %d", length, offset)
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
@ -118,15 +118,15 @@ async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inse
tb = TB(dut)
byte_width = tb.axil_master.write_if.byte_width
byte_lanes = tb.axil_master.write_if.byte_lanes
await tb.cycle_reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in range(1, byte_width*2):
for offset in range(byte_width):
for length in range(1, byte_lanes*2):
for offset in range(byte_lanes):
tb.log.info("length %d, offset %d", length, offset)
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])

12
fpga/lib/axi/tb/axil_dp_ram/test_axil_dp_ram.py
View File

@ -87,15 +87,15 @@ async def run_test_write(dut, port=0, data_in=None, idle_inserter=None, backpres
tb = TB(dut)
axil_master = tb.axil_master[port]
byte_width = axil_master.write_if.byte_width
byte_lanes = axil_master.write_if.byte_lanes
await tb.cycle_reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in range(1, byte_width*2):
for offset in range(byte_width):
for length in range(1, byte_lanes*2):
for offset in range(byte_lanes):
tb.log.info("length %d, offset %d", length, offset)
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
@ -117,15 +117,15 @@ async def run_test_read(dut, port=0, data_in=None, idle_inserter=None, backpress
tb = TB(dut)
axil_master = tb.axil_master[port]
byte_width = axil_master.write_if.byte_width
byte_lanes = axil_master.write_if.byte_lanes
await tb.cycle_reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in range(1, byte_width*2):
for offset in range(byte_width):
for length in range(1, byte_lanes*2):
for offset in range(byte_lanes):
tb.log.info("length %d, offset %d", length, offset)
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])

12
fpga/lib/axi/tb/axil_interconnect/test_axil_interconnect.py
View File

@ -90,15 +90,15 @@ async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_ins
tb = TB(dut)
byte_width = tb.axil_master[s].write_if.byte_width
byte_lanes = tb.axil_master[s].write_if.byte_lanes
await tb.cycle_reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in range(1, byte_width*2):
for offset in range(byte_width):
for length in range(1, byte_lanes*2):
for offset in range(byte_lanes):
tb.log.info("length %d, offset %d", length, offset)
ram_addr = offset+0x1000
addr = ram_addr + m*0x1000000
@ -122,15 +122,15 @@ async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inse
tb = TB(dut)
byte_width = tb.axil_master[s].write_if.byte_width
byte_lanes = tb.axil_master[s].write_if.byte_lanes
await tb.cycle_reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in range(1, byte_width*2):
for offset in range(byte_width):
for length in range(1, byte_lanes*2):
for offset in range(byte_lanes):
tb.log.info("length %d, offset %d", length, offset)
ram_addr = offset+0x1000
addr = ram_addr + m*0x1000000

12
fpga/lib/axi/tb/axil_ram/test_axil_ram.py
View File

@ -76,15 +76,15 @@ async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_ins
tb = TB(dut)
byte_width = tb.axil_master.write_if.byte_width
byte_lanes = tb.axil_master.write_if.byte_lanes
await tb.cycle_reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in range(1, byte_width*2):
for offset in range(byte_width):
for length in range(1, byte_lanes*2):
for offset in range(byte_lanes):
tb.log.info("length %d, offset %d", length, offset)
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
@ -105,15 +105,15 @@ async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inse
tb = TB(dut)
byte_width = tb.axil_master.write_if.byte_width
byte_lanes = tb.axil_master.write_if.byte_lanes
await tb.cycle_reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in range(1, byte_width*2):
for offset in range(byte_width):
for length in range(1, byte_lanes*2):
for offset in range(byte_lanes):
tb.log.info("length %d, offset %d", length, offset)
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])

12
fpga/lib/axi/tb/axil_register/test_axil_register.py
View File

@ -82,15 +82,15 @@ async def run_test_write(dut, data_in=None, idle_inserter=None, backpressure_ins
tb = TB(dut)
byte_width = tb.axil_master.write_if.byte_width
byte_lanes = tb.axil_master.write_if.byte_lanes
await tb.cycle_reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in range(1, byte_width*2):
for offset in range(byte_width):
for length in range(1, byte_lanes*2):
for offset in range(byte_lanes):
tb.log.info("length %d, offset %d", length, offset)
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])
@ -113,15 +113,15 @@ async def run_test_read(dut, data_in=None, idle_inserter=None, backpressure_inse
tb = TB(dut)
byte_width = tb.axil_master.write_if.byte_width
byte_lanes = tb.axil_master.write_if.byte_lanes
await tb.cycle_reset()
tb.set_idle_generator(idle_inserter)
tb.set_backpressure_generator(backpressure_inserter)
for length in range(1, byte_width*2):
for offset in range(byte_width):
for length in range(1, byte_lanes*2):
for offset in range(byte_lanes):
tb.log.info("length %d, offset %d", length, offset)
addr = offset+0x1000
test_data = bytearray([x % 256 for x in range(length)])