diff --git a/rtl/axi_ram.v b/rtl/axi_ram.v index 075cbc738..4157d37d0 100644 --- a/rtl/axi_ram.v +++ b/rtl/axi_ram.v @@ -198,19 +198,20 @@ always @* begin WRITE_STATE_IDLE: begin s_axi_awready_next = (write_addr_ready || !write_addr_valid_reg) && (!s_axi_bvalid || s_axi_bready); - write_id_next = s_axi_awid; - write_addr_next = s_axi_awaddr; - write_count_next = s_axi_awlen; - write_size_next = s_axi_awsize < $clog2(STRB_WIDTH) ? s_axi_awsize : $clog2(STRB_WIDTH); - write_burst_next = s_axi_awburst; - if (s_axi_awready & s_axi_awvalid) begin - s_axi_awready_next = write_addr_ready; + write_id_next = s_axi_awid; + write_addr_next = s_axi_awaddr; + write_count_next = s_axi_awlen; + write_size_next = s_axi_awsize < $clog2(STRB_WIDTH) ? s_axi_awsize : $clog2(STRB_WIDTH); + write_burst_next = s_axi_awburst; + write_addr_valid_next = 1'b1; s_axi_wready_next = 1'b1; if (s_axi_awlen > 0) begin + s_axi_awready_next = 1'b0; write_state_next = WRITE_STATE_BURST; end else begin + s_axi_awready_next = 1'b0; s_axi_bid_next = write_id_next; s_axi_bresp_next = 2'b00; s_axi_bvalid_next = 1'b1; @@ -234,6 +235,8 @@ always @* begin write_state_next = WRITE_STATE_BURST; end else begin write_addr_valid_next = 1'b0; + s_axi_awready_next = 1'b0; + s_axi_wready_next = 1'b0; s_axi_bid_next = write_id_reg; s_axi_bresp_next = 2'b00; s_axi_bvalid_next = 1'b1; @@ -311,19 +314,20 @@ always @* begin READ_STATE_IDLE: begin s_axi_arready_next = (read_addr_ready || !read_addr_valid_reg); - read_id_next = s_axi_arid; - read_addr_next = s_axi_araddr; - read_count_next = s_axi_arlen; - read_size_next = s_axi_arsize < $clog2(STRB_WIDTH) ? s_axi_arsize : $clog2(STRB_WIDTH); - read_burst_next = s_axi_arburst; - if (s_axi_arready & s_axi_arvalid) begin - s_axi_arready_next = read_addr_ready; + read_id_next = s_axi_arid; + read_addr_next = s_axi_araddr; + read_count_next = s_axi_arlen; + read_size_next = s_axi_arsize < $clog2(STRB_WIDTH) ? s_axi_arsize : $clog2(STRB_WIDTH); + read_burst_next = s_axi_arburst; + read_addr_valid_next = 1'b1; if (s_axi_arlen > 0) begin + s_axi_arready_next = 1'b0; read_last_next = 1'b0; read_state_next = READ_STATE_BURST; end else begin + s_axi_arready_next = 1'b0; read_last_next = 1'b1; read_state_next = READ_STATE_IDLE; end @@ -344,6 +348,7 @@ always @* begin read_addr_valid_next = 1'b1; read_state_next = READ_STATE_BURST; end else begin + s_axi_arready_next = 1'b0; read_addr_valid_next = 1'b0; read_state_next = READ_STATE_IDLE; end diff --git a/tb/test_axi_ram.py b/tb/test_axi_ram.py index 2469ab93d..58102707e 100755 --- a/tb/test_axi_ram.py +++ b/tb/test_axi_ram.py @@ -217,19 +217,22 @@ def bench(): print("test 1: read and write") current_test.next = 1 - axi_master_inst.init_write(4, b'\x11\x22\x33\x44') + addr = 4 + test_data = b'\x11\x22\x33\x44' + + axi_master_inst.init_write(addr, test_data) yield axi_master_inst.wait() yield clk.posedge - axi_master_inst.init_read(4, 4) + axi_master_inst.init_read(addr, len(test_data)) yield axi_master_inst.wait() yield clk.posedge data = axi_master_inst.get_read_data() - assert data[0] == 4 - assert data[1] == b'\x11\x22\x33\x44' + assert data[0] == addr + assert data[1] == test_data yield delay(100) @@ -237,38 +240,52 @@ def bench(): print("test 2: various reads and writes") current_test.next = 2 - for length in range(1,8): - for offset in range(4,8): + for length in list(range(1,8))+[1024]: + for offset in list(range(4,8))+[4096-4]: for size in (2, 1, 0): for wait in wait_normal, wait_pause_master: - axi_master_inst.init_write(256*(16*offset+length)+offset-4, b'\xaa'*(length+8), size=size) + print("length %d, offset %d, size %d"% (length, offset, size)) + #addr = 256*(16*offset+length)+offset + addr = offset + test_data = bytearray([x%256 for x in range(length)]) + + axi_master_inst.init_write(addr-4, b'\xAA'*(length+8), size=size) yield axi_master_inst.wait() - axi_master_inst.init_write(256*(16*offset+length)+offset, b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length], size=size) + axi_master_inst.init_write(addr, test_data, size=size) yield wait() - axi_master_inst.init_read(256*(16*offset+length)+offset-1, length+2, size=size) + axi_master_inst.init_read(addr-1, length+2, size=size) yield axi_master_inst.wait() data = axi_master_inst.get_read_data() - assert data[0] == 256*(16*offset+length)+offset-1 - assert data[1] == b'\xaa'+b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length]+b'\xaa' + assert data[0] == addr-1 + assert data[1] == b'\xAA'+test_data+b'\xAA' - for length in range(1,8): - for offset in range(4,8): + for length in list(range(1,8))+[1024]: + for offset in list(range(4,8))+[4096-4]: for size in (2, 1, 0): for wait in wait_normal, wait_pause_master: - axi_master_inst.init_read(256*(16*offset+length)+offset, length, size=size) + print("length %d, offset %d, size %d"% (length, offset, size)) + #addr = 256*(16*offset+length)+offset + addr = offset + test_data = bytearray([x%256 for x in range(length)]) + + axi_master_inst.init_write(addr, test_data, size=size) + + yield axi_master_inst.wait() + + axi_master_inst.init_read(addr, length, size=size) yield wait() yield clk.posedge data = axi_master_inst.get_read_data() - assert data[0] == 256*(16*offset+length)+offset - assert data[1] == b'\x11\x22\x33\x44\x55\x66\x77\x88'[0:length] + assert data[0] == addr + assert data[1] == test_data yield delay(100)