From 5f7697178bb8d23059fbc75ccc33400e01e9cf7e Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Wed, 10 Feb 2021 18:42:32 -0800 Subject: [PATCH] Remove await ReadOnly --- tb/dma_psdp_ram.py | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/tb/dma_psdp_ram.py b/tb/dma_psdp_ram.py index 1a684535b..167b44f72 100644 --- a/tb/dma_psdp_ram.py +++ b/tb/dma_psdp_ram.py @@ -25,7 +25,7 @@ THE SOFTWARE. import logging import cocotb -from cocotb.triggers import RisingEdge, ReadOnly +from cocotb.triggers import RisingEdge from cocotb.bus import Bus from cocotbext.axi.memory import Memory @@ -92,7 +92,7 @@ class PsdpRamWrite(Memory): async def _run(self): while True: - await ReadOnly() + await RisingEdge(self.clock) cmd_be_sample = self.cmd_bus.wr_cmd_be.value cmd_addr_sample = self.cmd_bus.wr_cmd_addr.value @@ -101,12 +101,9 @@ class PsdpRamWrite(Memory): cmd_valid_sample = self.cmd_bus.wr_cmd_valid.value if self.reset is not None and self.reset.value: - await RisingEdge(self.clock) self.cmd_bus.wr_cmd_ready.setimmediatevalue(0) continue - await RisingEdge(self.clock) - # process segments for seg in range(self.seg_count): if cmd_ready_sample & cmd_valid_sample & (1 << seg): @@ -206,7 +203,7 @@ class PsdpRamRead(Memory): resp_data = 0 while True: - await ReadOnly() + await RisingEdge(self.clock) cmd_addr_sample = self.cmd_bus.rd_cmd_addr.value cmd_ready_sample = self.cmd_bus.rd_cmd_ready.value @@ -216,15 +213,12 @@ class PsdpRamRead(Memory): resp_valid_sample = self.resp_bus.rd_resp_valid.value if self.reset is not None and self.reset.value: - await RisingEdge(self.clock) self.cmd_bus.rd_cmd_ready.setimmediatevalue(0) self.resp_bus.rd_resp_valid.setimmediatevalue(0) cmd_ready = 0 resp_valid = 0 continue - await RisingEdge(self.clock) - # process segments for seg in range(self.seg_count): seg_mask = 1 << seg