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ZCU106/fpga_zynqmp: Sync module parameters

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2022-04-07 21:41:06 -07:00
parent 2eb4e5c4bd
commit 5f7c051b5b
3 changed files with 20 additions and 0 deletions
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4
fpga/mqnic/ZCU106/fpga_zynqmp/fpga/config.tcl
View File

@ -82,8 +82,11 @@ dict set params RELEASE_INFO [format "32'h%08x" $release_info]
dict set params IF_COUNT "2"
dict set params PORTS_PER_IF "1"
dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
# PTP configuration
dict set params PTP_CLOCK_PIPELINE "0"
dict set params PTP_PORT_CDC_PIPELINE "0"
dict set params PTP_PEROUT_ENABLE "1"
dict set params PTP_PEROUT_COUNT "1"
@ -149,6 +152,7 @@ dict set params AXI_ID_WIDTH [get_property CONFIG.ID_WIDTH $s_axi_mm]
# DMA interface configuration
dict set params DMA_LEN_WIDTH "16"
dict set params DMA_TAG_WIDTH "16"
dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
dict set params RAM_PIPELINE "2"
# NOTE: Querying the BD top-level interface port (or even the ZynqMP's interface
# pin) yields 256 for the maximum burst length, instead of 16, which is

8
fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga.v
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@ -55,8 +55,11 @@ module fpga #
// Structural configuration
parameter IF_COUNT = 2,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
// PTP configuration
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 1,
parameter PTP_PEROUT_COUNT = 1,
@ -121,6 +124,7 @@ module fpga #
// DMA interface configuration
parameter DMA_LEN_WIDTH = 16,
parameter DMA_TAG_WIDTH = 16,
parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
parameter RAM_PIPELINE = 2,
parameter AXI_DMA_MAX_BURST_LEN = 256,
@ -690,6 +694,7 @@ fpga_core #(
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
@ -699,7 +704,9 @@ fpga_core #(
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
@ -764,6 +771,7 @@ fpga_core #(
// DMA interface configuration
.DMA_LEN_WIDTH(DMA_LEN_WIDTH),
.DMA_TAG_WIDTH(DMA_TAG_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.RAM_PIPELINE(RAM_PIPELINE),
.AXI_DMA_MAX_BURST_LEN(AXI_DMA_MAX_BURST_LEN),

8
fpga/mqnic/ZCU106/fpga_zynqmp/rtl/fpga_core.v
View File

@ -55,6 +55,7 @@ module fpga_core #
// Structural configuration
parameter IF_COUNT = 2,
parameter PORTS_PER_IF = 1,
parameter SCHED_PER_IF = PORTS_PER_IF,
// PTP configuration
parameter PTP_TS_WIDTH = 96,
@ -64,7 +65,9 @@ module fpga_core #
parameter PTP_FNS_WIDTH = 32,
parameter PTP_PERIOD_NS = 4'd4,
parameter PTP_PERIOD_FNS = 32'd0,
parameter PTP_CLOCK_PIPELINE = 0,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter PTP_PORT_CDC_PIPELINE = 0,
parameter PTP_PEROUT_ENABLE = 1,
parameter PTP_PEROUT_COUNT = 1,
parameter IF_PTP_PERIOD_NS = 6'h6,
@ -134,6 +137,7 @@ module fpga_core #
// DMA interface configuration
parameter DMA_LEN_WIDTH = 16,
parameter DMA_TAG_WIDTH = 16,
parameter RAM_ADDR_WIDTH = $clog2(TX_RAM_SIZE > RX_RAM_SIZE ? TX_RAM_SIZE : RX_RAM_SIZE),
parameter RAM_PIPELINE = 2,
parameter AXI_DMA_MAX_BURST_LEN = 256,
@ -759,6 +763,7 @@ mqnic_core_axi #(
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.SCHED_PER_IF(SCHED_PER_IF),
.PORT_COUNT(PORT_COUNT),
@ -770,8 +775,10 @@ mqnic_core_axi #(
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_CLOCK_PIPELINE(PTP_CLOCK_PIPELINE),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_SEPARATE_RX_CLOCK(0),
.PTP_PORT_CDC_PIPELINE(PTP_PORT_CDC_PIPELINE),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
@ -838,6 +845,7 @@ mqnic_core_axi #(
// DMA interface configuration
.DMA_LEN_WIDTH(DMA_LEN_WIDTH),
.DMA_TAG_WIDTH(DMA_TAG_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.RAM_PIPELINE(RAM_PIPELINE),
.AXI_DMA_MAX_BURST_LEN(AXI_DMA_MAX_BURST_LEN),