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Testbench cleanup

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2022-07-13 16:35:51 -07:00
parent fc90d7f44d
commit 5fe904545c
4 changed files with 12 additions and 10 deletions
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4
example/520N_MX/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -48,8 +48,8 @@ class TB(object):
self.dev = S10PcieDevice(
# configuration options
pcie_generation=3,
# pcie_link_width=8,
# pld_clk_frequency=250e6,
pcie_link_width=16,
pld_clk_frequency=250e6,
l_tile=False,
pf_count=1,
max_payload_size=1024,

7
example/DE10_Agilex/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -48,8 +48,8 @@ class TB(object):
self.dev = PTilePcieDevice(
# configuration options
pcie_generation=3,
# pcie_link_width=2,
# pld_clk_frequency=250e6,
pcie_link_width=16,
pld_clk_frequency=250e6,
pf_count=1,
max_payload_size=512,
enable_extended_tag=True,
@ -62,7 +62,7 @@ class TB(object):
pf2_msi_count=1,
pf3_msi_enable=False,
pf3_msi_count=1,
pf0_msix_enable=False,
pf0_msix_enable=True,
pf0_msix_table_size=63,
pf0_msix_table_bir=4,
pf0_msix_table_offset=0x00000000,
@ -245,6 +245,7 @@ class TB(object):
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_awaddr))
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axi_ram_awaddr))
self.dev.functions[0].configure_bar(4, 2**len(dut.core_inst.core_pcie_inst.axil_msix_awaddr))
async def init(self):

7
example/S10DX_DK/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -48,8 +48,8 @@ class TB(object):
self.dev = PTilePcieDevice(
# configuration options
pcie_generation=3,
# pcie_link_width=2,
# pld_clk_frequency=250e6,
pcie_link_width=16,
pld_clk_frequency=250e6,
pf_count=1,
max_payload_size=512,
enable_extended_tag=True,
@ -62,7 +62,7 @@ class TB(object):
pf2_msi_count=1,
pf3_msi_enable=False,
pf3_msi_count=1,
pf0_msix_enable=False,
pf0_msix_enable=True,
pf0_msix_table_size=63,
pf0_msix_table_bir=4,
pf0_msix_table_offset=0x00000000,
@ -245,6 +245,7 @@ class TB(object):
self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_awaddr))
self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axi_ram_awaddr))
self.dev.functions[0].configure_bar(4, 2**len(dut.core_inst.core_pcie_inst.axil_msix_awaddr))
async def init(self):

4
example/S10MX_DK/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -48,8 +48,8 @@ class TB(object):
self.dev = S10PcieDevice(
# configuration options
pcie_generation=3,
# pcie_link_width=8,
# pld_clk_frequency=250e6,
pcie_link_width=16,
pld_clk_frequency=250e6,
l_tile=False,
pf_count=1,
max_payload_size=1024,