diff --git a/example/520N_MX/fpga/tb/fpga_core/test_fpga_core.py b/example/520N_MX/fpga/tb/fpga_core/test_fpga_core.py
index 64356c5bd..1947cf502 100644
--- a/example/520N_MX/fpga/tb/fpga_core/test_fpga_core.py
+++ b/example/520N_MX/fpga/tb/fpga_core/test_fpga_core.py
@@ -48,8 +48,8 @@ class TB(object):
         self.dev = S10PcieDevice(
             # configuration options
             pcie_generation=3,
-            # pcie_link_width=8,
-            # pld_clk_frequency=250e6,
+            pcie_link_width=16,
+            pld_clk_frequency=250e6,
             l_tile=False,
             pf_count=1,
             max_payload_size=1024,
diff --git a/example/DE10_Agilex/fpga/tb/fpga_core/test_fpga_core.py b/example/DE10_Agilex/fpga/tb/fpga_core/test_fpga_core.py
index 26e72a739..364bee7a8 100644
--- a/example/DE10_Agilex/fpga/tb/fpga_core/test_fpga_core.py
+++ b/example/DE10_Agilex/fpga/tb/fpga_core/test_fpga_core.py
@@ -48,8 +48,8 @@ class TB(object):
         self.dev = PTilePcieDevice(
             # configuration options
             pcie_generation=3,
-            # pcie_link_width=2,
-            # pld_clk_frequency=250e6,
+            pcie_link_width=16,
+            pld_clk_frequency=250e6,
             pf_count=1,
             max_payload_size=512,
             enable_extended_tag=True,
@@ -62,7 +62,7 @@ class TB(object):
             pf2_msi_count=1,
             pf3_msi_enable=False,
             pf3_msi_count=1,
-            pf0_msix_enable=False,
+            pf0_msix_enable=True,
             pf0_msix_table_size=63,
             pf0_msix_table_bir=4,
             pf0_msix_table_offset=0x00000000,
@@ -245,6 +245,7 @@ class TB(object):
 
         self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_awaddr))
         self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axi_ram_awaddr))
+        self.dev.functions[0].configure_bar(4, 2**len(dut.core_inst.core_pcie_inst.axil_msix_awaddr))
 
     async def init(self):
 
diff --git a/example/S10DX_DK/fpga/tb/fpga_core/test_fpga_core.py b/example/S10DX_DK/fpga/tb/fpga_core/test_fpga_core.py
index 26e72a739..364bee7a8 100644
--- a/example/S10DX_DK/fpga/tb/fpga_core/test_fpga_core.py
+++ b/example/S10DX_DK/fpga/tb/fpga_core/test_fpga_core.py
@@ -48,8 +48,8 @@ class TB(object):
         self.dev = PTilePcieDevice(
             # configuration options
             pcie_generation=3,
-            # pcie_link_width=2,
-            # pld_clk_frequency=250e6,
+            pcie_link_width=16,
+            pld_clk_frequency=250e6,
             pf_count=1,
             max_payload_size=512,
             enable_extended_tag=True,
@@ -62,7 +62,7 @@ class TB(object):
             pf2_msi_count=1,
             pf3_msi_enable=False,
             pf3_msi_count=1,
-            pf0_msix_enable=False,
+            pf0_msix_enable=True,
             pf0_msix_table_size=63,
             pf0_msix_table_bir=4,
             pf0_msix_table_offset=0x00000000,
@@ -245,6 +245,7 @@ class TB(object):
 
         self.dev.functions[0].configure_bar(0, 2**len(dut.core_inst.core_pcie_inst.axil_ctrl_awaddr))
         self.dev.functions[0].configure_bar(2, 2**len(dut.core_inst.core_pcie_inst.axi_ram_awaddr))
+        self.dev.functions[0].configure_bar(4, 2**len(dut.core_inst.core_pcie_inst.axil_msix_awaddr))
 
     async def init(self):
 
diff --git a/example/S10MX_DK/fpga/tb/fpga_core/test_fpga_core.py b/example/S10MX_DK/fpga/tb/fpga_core/test_fpga_core.py
index 64356c5bd..1947cf502 100644
--- a/example/S10MX_DK/fpga/tb/fpga_core/test_fpga_core.py
+++ b/example/S10MX_DK/fpga/tb/fpga_core/test_fpga_core.py
@@ -48,8 +48,8 @@ class TB(object):
         self.dev = S10PcieDevice(
             # configuration options
             pcie_generation=3,
-            # pcie_link_width=8,
-            # pld_clk_frequency=250e6,
+            pcie_link_width=16,
+            pld_clk_frequency=250e6,
             l_tile=False,
             pf_count=1,
             max_payload_size=1024,