FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00
Code Issues Projects Releases Wiki Activity

Reorganize FIFO write logic

Browse Source 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-08-14 18:55:02 -07:00
parent c3cd676c5d
commit 6020d09214
2 changed files with 116 additions and 104 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

42
rtl/axis_async_fifo.v
View File

@ -395,26 +395,11 @@ always @(posedge s_clk) begin
end
end
if (FRAME_FIFO) begin
// frame FIFO mode
if (s_axis_tready && s_axis_tvalid) begin
// transfer in
if (!FRAME_FIFO) begin
// normal FIFO mode
mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis;
if (drop_frame_reg && LAST_ENABLE) begin
// currently dropping frame
// (only for frame transfers interrupted by sink reset)
if (s_axis_tlast) begin
// end of frame, clear drop flag
drop_frame_reg <= 1'b0;
end
end else begin
// update pointers
wr_ptr_temp = wr_ptr_reg + 1;
wr_ptr_reg <= wr_ptr_temp;
wr_ptr_commit_reg <= wr_ptr_temp;
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
end
end else if ((full && DROP_WHEN_FULL) || (full_wr && DROP_OVERSIZE_FRAME) || drop_frame_reg) begin
if ((full && DROP_WHEN_FULL) || (full_wr && DROP_OVERSIZE_FRAME) || drop_frame_reg) begin
// full, packet overflow, or currently dropping frame
// drop frame
drop_frame_reg <= 1'b1;
@ -480,6 +465,27 @@ always @(posedge s_clk) begin
wr_ptr_update_valid_reg <= 1'b1;
end
end
end else begin
// normal FIFO mode
if (s_axis_tready && s_axis_tvalid) begin
// transfer in
mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis;
if (drop_frame_reg && LAST_ENABLE) begin
// currently dropping frame
// (only for frame transfers interrupted by sink reset)
if (s_axis_tlast) begin
// end of frame, clear drop flag
drop_frame_reg <= 1'b0;
end
end else begin
// update pointers
wr_ptr_temp = wr_ptr_reg + 1;
wr_ptr_reg <= wr_ptr_temp;
wr_ptr_commit_reg <= wr_ptr_temp;
wr_ptr_gray_reg <= bin2gray(wr_ptr_temp);
end
end
end
if (s_rst_sync3_reg) begin
wr_ptr_reg <= {ADDR_WIDTH+1{1'b0}};

20
rtl/axis_fifo.v
View File

@ -245,14 +245,11 @@ always @(posedge clk) begin
bad_frame_reg <= 1'b0;
good_frame_reg <= 1'b0;
if (FRAME_FIFO) begin
// frame FIFO mode
if (s_axis_tready && s_axis_tvalid) begin
// transfer in
if (!FRAME_FIFO) begin
// normal FIFO mode
mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis;
wr_ptr_reg <= wr_ptr_reg + 1;
wr_ptr_commit_reg <= wr_ptr_reg + 1;
end else if ((full && DROP_WHEN_FULL) || (full_wr && DROP_OVERSIZE_FRAME) || drop_frame_reg) begin
if ((full && DROP_WHEN_FULL) || (full_wr && DROP_OVERSIZE_FRAME) || drop_frame_reg) begin
// full, packet overflow, or currently dropping frame
// drop frame
drop_frame_reg <= 1'b1;
@ -280,12 +277,21 @@ always @(posedge clk) begin
end
end
end
end else if (s_axis_tvalid && full_wr && FRAME_FIFO && !DROP_OVERSIZE_FRAME) begin
end else if (s_axis_tvalid && full_wr && !DROP_OVERSIZE_FRAME) begin
// data valid with packet overflow
// update write pointer
send_frame_reg <= 1'b1;
wr_ptr_commit_reg <= wr_ptr_reg;
end
end else begin
// normal FIFO mode
if (s_axis_tready && s_axis_tvalid) begin
// transfer in
mem[wr_ptr_reg[ADDR_WIDTH-1:0]] <= s_axis;
wr_ptr_reg <= wr_ptr_reg + 1;
wr_ptr_commit_reg <= wr_ptr_reg + 1;
end
end
if (rst) begin
wr_ptr_reg <= {ADDR_WIDTH+1{1'b0}};