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Add mqnic core logic module for AXI

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Alex Forencich 2021-11-17 18:16:40 -08:00
parent 5bf9de656c
commit 605965fec9
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/*
Copyright 2021, The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
The views and conclusions contained in the software and documentation are those
of the authors and should not be interpreted as representing official policies,
either expressed or implied, of The Regents of the University of California.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* FPGA core logic
*/
module mqnic_core_axi #
(
// FW and board IDs
parameter FW_ID = 32'd0,
parameter FW_VER = {16'd0, 16'd1},
parameter BOARD_ID = {16'h1234, 16'h0000},
parameter BOARD_VER = {16'd0, 16'd1},
// Structural configuration
parameter IF_COUNT = 1,
parameter PORTS_PER_IF = 1,
parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF,
// PTP configuration
parameter PTP_TS_WIDTH = 96,
parameter PTP_TAG_WIDTH = 16,
parameter PTP_PERIOD_NS_WIDTH = 4,
parameter PTP_OFFSET_NS_WIDTH = 32,
parameter PTP_FNS_WIDTH = 32,
parameter PTP_PERIOD_NS = 4'd4,
parameter PTP_PERIOD_FNS = 32'd0,
parameter PTP_USE_SAMPLE_CLOCK = 0,
parameter PTP_PEROUT_ENABLE = 0,
parameter PTP_PEROUT_COUNT = 1,
// Queue manager configuration (interface)
parameter EVENT_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_QUEUE_OP_TABLE_SIZE = 32,
parameter RX_QUEUE_OP_TABLE_SIZE = 32,
parameter TX_CPL_QUEUE_OP_TABLE_SIZE = TX_QUEUE_OP_TABLE_SIZE,
parameter RX_CPL_QUEUE_OP_TABLE_SIZE = RX_QUEUE_OP_TABLE_SIZE,
parameter TX_QUEUE_INDEX_WIDTH = 13,
parameter RX_QUEUE_INDEX_WIDTH = 8,
parameter TX_CPL_QUEUE_INDEX_WIDTH = TX_QUEUE_INDEX_WIDTH,
parameter RX_CPL_QUEUE_INDEX_WIDTH = RX_QUEUE_INDEX_WIDTH,
parameter EVENT_QUEUE_PIPELINE = 3,
parameter TX_QUEUE_PIPELINE = 3+(TX_QUEUE_INDEX_WIDTH > 12 ? TX_QUEUE_INDEX_WIDTH-12 : 0),
parameter RX_QUEUE_PIPELINE = 3+(RX_QUEUE_INDEX_WIDTH > 12 ? RX_QUEUE_INDEX_WIDTH-12 : 0),
parameter TX_CPL_QUEUE_PIPELINE = TX_QUEUE_PIPELINE,
parameter RX_CPL_QUEUE_PIPELINE = RX_QUEUE_PIPELINE,
// TX and RX engine configuration (port)
parameter TX_DESC_TABLE_SIZE = 32,
parameter RX_DESC_TABLE_SIZE = 32,
// Scheduler configuration (port)
parameter TX_SCHEDULER_OP_TABLE_SIZE = TX_DESC_TABLE_SIZE,
parameter TX_SCHEDULER_PIPELINE = TX_QUEUE_PIPELINE,
parameter TDMA_INDEX_WIDTH = 6,
// Timestamping configuration (port)
parameter PTP_TS_ENABLE = 1,
parameter TX_PTP_TS_FIFO_DEPTH = 32,
parameter RX_PTP_TS_FIFO_DEPTH = 32,
// Interface configuration (port)
parameter TX_CHECKSUM_ENABLE = 1,
parameter RX_RSS_ENABLE = 1,
parameter RX_HASH_ENABLE = 1,
parameter RX_CHECKSUM_ENABLE = 1,
parameter TX_FIFO_DEPTH = 32768,
parameter RX_FIFO_DEPTH = 32768,
parameter MAX_TX_SIZE = 9214,
parameter MAX_RX_SIZE = 9214,
parameter TX_RAM_SIZE = 32768,
parameter RX_RAM_SIZE = 32768,
// Application block configuration
parameter APP_ENABLE = 0,
parameter APP_CTRL_ENABLE = 1,
parameter APP_DMA_ENABLE = 1,
parameter APP_AXIS_DIRECT_ENABLE = 1,
parameter APP_AXIS_SYNC_ENABLE = 1,
parameter APP_AXIS_IF_ENABLE = 1,
parameter APP_STAT_ENABLE = 1,
// AXI interface configuration (DMA)
parameter AXI_DATA_WIDTH = 128,
parameter AXI_ADDR_WIDTH = 32,
parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8),
parameter AXI_ID_WIDTH = 8,
// DMA interface configuration
parameter DMA_LEN_WIDTH = 16,
parameter DMA_TAG_WIDTH = 16,
parameter RAM_PIPELINE = 2,
parameter AXI_DMA_MAX_BURST_LEN = 256,
parameter AXI_DMA_USE_ID = 1,
parameter AXI_DMA_READ_OP_TABLE_SIZE = 2**(AXI_ID_WIDTH),
parameter AXI_DMA_WRITE_OP_TABLE_SIZE = 2**(AXI_ID_WIDTH),
// Interrupts
parameter IRQ_COUNT = 32,
// AXI lite interface configuration (control)
parameter AXIL_CTRL_DATA_WIDTH = 32,
parameter AXIL_CTRL_ADDR_WIDTH = 24,
parameter AXIL_CTRL_STRB_WIDTH = (AXIL_CTRL_DATA_WIDTH/8),
parameter AXIL_IF_CTRL_ADDR_WIDTH = AXIL_CTRL_ADDR_WIDTH-$clog2(IF_COUNT),
parameter AXIL_CSR_ADDR_WIDTH = AXIL_IF_CTRL_ADDR_WIDTH-5-$clog2((PORTS_PER_IF+3)/8),
parameter AXIL_CSR_PASSTHROUGH_ENABLE = 0,
// AXI lite interface configuration (application control)
parameter AXIL_APP_CTRL_DATA_WIDTH = AXIL_CTRL_DATA_WIDTH,
parameter AXIL_APP_CTRL_ADDR_WIDTH = 24,
parameter AXIL_APP_CTRL_STRB_WIDTH = (AXIL_APP_CTRL_DATA_WIDTH/8),
// Ethernet interface configuration
parameter AXIS_DATA_WIDTH = 64,
parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8,
parameter AXIS_SYNC_DATA_WIDTH = AXIS_DATA_WIDTH,
parameter AXIS_TX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TAG_WIDTH : 0) + 1,
parameter AXIS_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
parameter AXIS_RX_USE_READY = 0,
parameter AXIS_TX_PIPELINE = 0,
parameter AXIS_TX_FIFO_PIPELINE = 2,
parameter AXIS_TX_TS_PIPELINE = 0,
parameter AXIS_RX_PIPELINE = 0,
parameter AXIS_RX_FIFO_PIPELINE = 2,
// Statistics counter subsystem
parameter STAT_ENABLE = 1,
parameter STAT_DMA_ENABLE = 1,
parameter STAT_PCIE_ENABLE = 1,
parameter STAT_INC_WIDTH = 24,
parameter STAT_ID_WIDTH = 12
)
(
input wire clk,
input wire rst,
/*
* AXI master interface (DMA)
*/
output wire [AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [7:0] m_axi_awlen,
output wire [2:0] m_axi_awsize,
output wire [1:0] m_axi_awburst,
output wire m_axi_awlock,
output wire [3:0] m_axi_awcache,
output wire [2:0] m_axi_awprot,
output wire m_axi_awvalid,
input wire m_axi_awready,
output wire [AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [AXI_STRB_WIDTH-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire m_axi_wvalid,
input wire m_axi_wready,
input wire [AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [1:0] m_axi_bresp,
input wire m_axi_bvalid,
output wire m_axi_bready,
output wire [AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [7:0] m_axi_arlen,
output wire [2:0] m_axi_arsize,
output wire [1:0] m_axi_arburst,
output wire m_axi_arlock,
output wire [3:0] m_axi_arcache,
output wire [2:0] m_axi_arprot,
output wire m_axi_arvalid,
input wire m_axi_arready,
input wire [AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire m_axi_rvalid,
output wire m_axi_rready,
/*
* AXI-Lite slave interface (control)
*/
input wire [AXIL_CTRL_ADDR_WIDTH-1:0] s_axil_ctrl_awaddr,
input wire [2:0] s_axil_ctrl_awprot,
input wire s_axil_ctrl_awvalid,
output wire s_axil_ctrl_awready,
input wire [AXIL_CTRL_DATA_WIDTH-1:0] s_axil_ctrl_wdata,
input wire [AXIL_CTRL_STRB_WIDTH-1:0] s_axil_ctrl_wstrb,
input wire s_axil_ctrl_wvalid,
output wire s_axil_ctrl_wready,
output wire [1:0] s_axil_ctrl_bresp,
output wire s_axil_ctrl_bvalid,
input wire s_axil_ctrl_bready,
input wire [AXIL_CTRL_ADDR_WIDTH-1:0] s_axil_ctrl_araddr,
input wire [2:0] s_axil_ctrl_arprot,
input wire s_axil_ctrl_arvalid,
output wire s_axil_ctrl_arready,
output wire [AXIL_CTRL_DATA_WIDTH-1:0] s_axil_ctrl_rdata,
output wire [1:0] s_axil_ctrl_rresp,
output wire s_axil_ctrl_rvalid,
input wire s_axil_ctrl_rready,
/*
* AXI-Lite slave interface (application control)
*/
input wire [AXIL_APP_CTRL_ADDR_WIDTH-1:0] s_axil_app_ctrl_awaddr,
input wire [2:0] s_axil_app_ctrl_awprot,
input wire s_axil_app_ctrl_awvalid,
output wire s_axil_app_ctrl_awready,
input wire [AXIL_APP_CTRL_DATA_WIDTH-1:0] s_axil_app_ctrl_wdata,
input wire [AXIL_APP_CTRL_STRB_WIDTH-1:0] s_axil_app_ctrl_wstrb,
input wire s_axil_app_ctrl_wvalid,
output wire s_axil_app_ctrl_wready,
output wire [1:0] s_axil_app_ctrl_bresp,
output wire s_axil_app_ctrl_bvalid,
input wire s_axil_app_ctrl_bready,
input wire [AXIL_APP_CTRL_ADDR_WIDTH-1:0] s_axil_app_ctrl_araddr,
input wire [2:0] s_axil_app_ctrl_arprot,
input wire s_axil_app_ctrl_arvalid,
output wire s_axil_app_ctrl_arready,
output wire [AXIL_APP_CTRL_DATA_WIDTH-1:0] s_axil_app_ctrl_rdata,
output wire [1:0] s_axil_app_ctrl_rresp,
output wire s_axil_app_ctrl_rvalid,
input wire s_axil_app_ctrl_rready,
/*
* AXI-Lite master interface (passthrough for NIC control and status)
*/
output wire [AXIL_CSR_ADDR_WIDTH-1:0] m_axil_csr_awaddr,
output wire [2:0] m_axil_csr_awprot,
output wire m_axil_csr_awvalid,
input wire m_axil_csr_awready,
output wire [AXIL_CTRL_DATA_WIDTH-1:0] m_axil_csr_wdata,
output wire [AXIL_CTRL_STRB_WIDTH-1:0] m_axil_csr_wstrb,
output wire m_axil_csr_wvalid,
input wire m_axil_csr_wready,
input wire [1:0] m_axil_csr_bresp,
input wire m_axil_csr_bvalid,
output wire m_axil_csr_bready,
output wire [AXIL_CSR_ADDR_WIDTH-1:0] m_axil_csr_araddr,
output wire [2:0] m_axil_csr_arprot,
output wire m_axil_csr_arvalid,
input wire m_axil_csr_arready,
input wire [AXIL_CTRL_DATA_WIDTH-1:0] m_axil_csr_rdata,
input wire [1:0] m_axil_csr_rresp,
input wire m_axil_csr_rvalid,
output wire m_axil_csr_rready,
/*
* Control register interface
*/
output wire [AXIL_CSR_ADDR_WIDTH-1:0] ctrl_reg_wr_addr,
output wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_wr_data,
output wire [AXIL_CTRL_STRB_WIDTH-1:0] ctrl_reg_wr_strb,
output wire ctrl_reg_wr_en,
input wire ctrl_reg_wr_wait,
input wire ctrl_reg_wr_ack,
output wire [AXIL_CSR_ADDR_WIDTH-1:0] ctrl_reg_rd_addr,
output wire ctrl_reg_rd_en,
input wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data,
input wire ctrl_reg_rd_wait,
input wire ctrl_reg_rd_ack,
/*
* Interrupt outputs
*/
output wire [IRQ_COUNT-1:0] irq,
/*
* PTP clock
*/
input wire ptp_sample_clk,
output wire ptp_pps,
output wire [PTP_TS_WIDTH-1:0] ptp_ts_96,
output wire ptp_ts_step,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error,
output wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse,
/*
* Ethernet
*/
input wire [PORT_COUNT-1:0] tx_clk,
input wire [PORT_COUNT-1:0] tx_rst,
output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] tx_ptp_ts_96,
output wire [PORT_COUNT-1:0] tx_ptp_ts_step,
output wire [PORT_COUNT*AXIS_DATA_WIDTH-1:0] m_axis_tx_tdata,
output wire [PORT_COUNT*AXIS_KEEP_WIDTH-1:0] m_axis_tx_tkeep,
output wire [PORT_COUNT-1:0] m_axis_tx_tvalid,
input wire [PORT_COUNT-1:0] m_axis_tx_tready,
output wire [PORT_COUNT-1:0] m_axis_tx_tlast,
output wire [PORT_COUNT*AXIS_TX_USER_WIDTH-1:0] m_axis_tx_tuser,
input wire [PORT_COUNT*PTP_TS_WIDTH-1:0] s_axis_tx_ptp_ts,
input wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] s_axis_tx_ptp_ts_tag,
input wire [PORT_COUNT-1:0] s_axis_tx_ptp_ts_valid,
output wire [PORT_COUNT-1:0] s_axis_tx_ptp_ts_ready,
input wire [PORT_COUNT-1:0] rx_clk,
input wire [PORT_COUNT-1:0] rx_rst,
output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] rx_ptp_ts_96,
output wire [PORT_COUNT-1:0] rx_ptp_ts_step,
input wire [PORT_COUNT*AXIS_DATA_WIDTH-1:0] s_axis_rx_tdata,
input wire [PORT_COUNT*AXIS_KEEP_WIDTH-1:0] s_axis_rx_tkeep,
input wire [PORT_COUNT-1:0] s_axis_rx_tvalid,
output wire [PORT_COUNT-1:0] s_axis_rx_tready,
input wire [PORT_COUNT-1:0] s_axis_rx_tlast,
input wire [PORT_COUNT*AXIS_RX_USER_WIDTH-1:0] s_axis_rx_tuser,
/*
* Statistics increment input
*/
input wire [STAT_INC_WIDTH-1:0] s_axis_stat_tdata,
input wire [STAT_ID_WIDTH-1:0] s_axis_stat_tid,
input wire s_axis_stat_tvalid,
output wire s_axis_stat_tready
);
parameter DMA_ADDR_WIDTH = AXI_ADDR_WIDTH;
parameter RAM_SEG_COUNT = 2;
parameter RAM_SEG_DATA_WIDTH = AXI_DATA_WIDTH*2/RAM_SEG_COUNT;
parameter RAM_SEG_ADDR_WIDTH = 12;
parameter RAM_SEG_BE_WIDTH = RAM_SEG_DATA_WIDTH/8;
parameter IF_RAM_SEL_WIDTH = PORTS_PER_IF > 1 ? $clog2(PORTS_PER_IF) : 1;
parameter RAM_SEL_WIDTH = $clog2(IF_COUNT+(APP_ENABLE && APP_DMA_ENABLE ? 1 : 0))+IF_RAM_SEL_WIDTH+1;
parameter RAM_ADDR_WIDTH = RAM_SEG_ADDR_WIDTH+$clog2(RAM_SEG_COUNT)+$clog2(RAM_SEG_BE_WIDTH);
// DMA connections
wire [RAM_SEG_COUNT*RAM_SEL_WIDTH-1:0] dma_ram_wr_cmd_sel;
wire [RAM_SEG_COUNT*RAM_SEG_BE_WIDTH-1:0] dma_ram_wr_cmd_be;
wire [RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] dma_ram_wr_cmd_addr;
wire [RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0] dma_ram_wr_cmd_data;
wire [RAM_SEG_COUNT-1:0] dma_ram_wr_cmd_valid;
wire [RAM_SEG_COUNT-1:0] dma_ram_wr_cmd_ready;
wire [RAM_SEG_COUNT-1:0] dma_ram_wr_done;
wire [RAM_SEG_COUNT*RAM_SEL_WIDTH-1:0] dma_ram_rd_cmd_sel;
wire [RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] dma_ram_rd_cmd_addr;
wire [RAM_SEG_COUNT-1:0] dma_ram_rd_cmd_valid;
wire [RAM_SEG_COUNT-1:0] dma_ram_rd_cmd_ready;
wire [RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0] dma_ram_rd_resp_data;
wire [RAM_SEG_COUNT-1:0] dma_ram_rd_resp_valid;
wire [RAM_SEG_COUNT-1:0] dma_ram_rd_resp_ready;
// DMA control
wire [DMA_ADDR_WIDTH-1:0] dma_read_desc_dma_addr;
wire [RAM_SEL_WIDTH-1:0] dma_read_desc_ram_sel;
wire [RAM_ADDR_WIDTH-1:0] dma_read_desc_ram_addr;
wire [DMA_LEN_WIDTH-1:0] dma_read_desc_len;
wire [DMA_TAG_WIDTH-1:0] dma_read_desc_tag;
wire dma_read_desc_valid;
wire dma_read_desc_ready;
wire [DMA_TAG_WIDTH-1:0] dma_read_desc_status_tag;
wire [3:0] dma_read_desc_status_error;
wire dma_read_desc_status_valid;
wire [DMA_ADDR_WIDTH-1:0] dma_write_desc_dma_addr;
wire [RAM_SEL_WIDTH-1:0] dma_write_desc_ram_sel;
wire [RAM_ADDR_WIDTH-1:0] dma_write_desc_ram_addr;
wire [DMA_LEN_WIDTH-1:0] dma_write_desc_len;
wire [DMA_TAG_WIDTH-1:0] dma_write_desc_tag;
wire dma_write_desc_valid;
wire dma_write_desc_ready;
wire [DMA_TAG_WIDTH-1:0] dma_write_desc_status_tag;
wire [3:0] dma_write_desc_status_error;
wire dma_write_desc_status_valid;
wire dma_enable = 1;
dma_if_axi #(
.AXI_DATA_WIDTH(AXI_DATA_WIDTH),
.AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
.AXI_STRB_WIDTH(AXI_STRB_WIDTH),
.AXI_ID_WIDTH(AXI_ID_WIDTH),
.AXI_MAX_BURST_LEN(AXI_DMA_MAX_BURST_LEN),
.RAM_SEG_COUNT(RAM_SEG_COUNT),
.RAM_SEG_DATA_WIDTH(RAM_SEG_DATA_WIDTH),
.RAM_SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH),
.RAM_SEG_BE_WIDTH(RAM_SEG_BE_WIDTH),
.RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.LEN_WIDTH(DMA_LEN_WIDTH),
.TAG_WIDTH(DMA_TAG_WIDTH),
.READ_OP_TABLE_SIZE(AXI_DMA_READ_OP_TABLE_SIZE),
.WRITE_OP_TABLE_SIZE(AXI_DMA_WRITE_OP_TABLE_SIZE),
.USE_AXI_ID(AXI_DMA_USE_ID)
)
dma_if_axi_inst (
.clk(clk),
.rst(rst),
/*
* AXI master interface
*/
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready),
/*
* AXI read descriptor input
*/
.s_axis_read_desc_axi_addr(dma_read_desc_dma_addr),
.s_axis_read_desc_ram_sel(dma_read_desc_ram_sel),
.s_axis_read_desc_ram_addr(dma_read_desc_ram_addr),
.s_axis_read_desc_len(dma_read_desc_len),
.s_axis_read_desc_tag(dma_read_desc_tag),
.s_axis_read_desc_valid(dma_read_desc_valid),
.s_axis_read_desc_ready(dma_read_desc_ready),
/*
* AXI read descriptor status output
*/
.m_axis_read_desc_status_tag(dma_read_desc_status_tag),
.m_axis_read_desc_status_error(dma_read_desc_status_error),
.m_axis_read_desc_status_valid(dma_read_desc_status_valid),
/*
* AXI write descriptor input
*/
.s_axis_write_desc_axi_addr(dma_write_desc_dma_addr),
.s_axis_write_desc_ram_sel(dma_write_desc_ram_sel),
.s_axis_write_desc_ram_addr(dma_write_desc_ram_addr),
.s_axis_write_desc_len(dma_write_desc_len),
.s_axis_write_desc_tag(dma_write_desc_tag),
.s_axis_write_desc_valid(dma_write_desc_valid),
.s_axis_write_desc_ready(dma_write_desc_ready),
/*
* AXI write descriptor status output
*/
.m_axis_write_desc_status_tag(dma_write_desc_status_tag),
.m_axis_write_desc_status_error(dma_write_desc_status_error),
.m_axis_write_desc_status_valid(dma_write_desc_status_valid),
/*
* RAM interface
*/
.ram_wr_cmd_sel(dma_ram_wr_cmd_sel),
.ram_wr_cmd_be(dma_ram_wr_cmd_be),
.ram_wr_cmd_addr(dma_ram_wr_cmd_addr),
.ram_wr_cmd_data(dma_ram_wr_cmd_data),
.ram_wr_cmd_valid(dma_ram_wr_cmd_valid),
.ram_wr_cmd_ready(dma_ram_wr_cmd_ready),
.ram_wr_done(dma_ram_wr_done),
.ram_rd_cmd_sel(dma_ram_rd_cmd_sel),
.ram_rd_cmd_addr(dma_ram_rd_cmd_addr),
.ram_rd_cmd_valid(dma_ram_rd_cmd_valid),
.ram_rd_cmd_ready(dma_ram_rd_cmd_ready),
.ram_rd_resp_data(dma_ram_rd_resp_data),
.ram_rd_resp_valid(dma_ram_rd_resp_valid),
.ram_rd_resp_ready(dma_ram_rd_resp_ready),
/*
* Configuration
*/
.read_enable(dma_enable),
.write_enable(dma_enable)
);
mqnic_core #(
// FW and board IDs
.FW_ID(FW_ID),
.FW_VER(FW_VER),
.BOARD_ID(BOARD_ID),
.BOARD_VER(BOARD_VER),
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
.PORT_COUNT(PORT_COUNT),
// PTP configuration
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH),
.PTP_PERIOD_NS_WIDTH(PTP_PERIOD_NS_WIDTH),
.PTP_OFFSET_NS_WIDTH(PTP_OFFSET_NS_WIDTH),
.PTP_FNS_WIDTH(PTP_FNS_WIDTH),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.PTP_PEROUT_ENABLE(PTP_PEROUT_ENABLE),
.PTP_PEROUT_COUNT(PTP_PEROUT_COUNT),
// Queue manager configuration (interface)
.EVENT_QUEUE_OP_TABLE_SIZE(EVENT_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_OP_TABLE_SIZE(TX_QUEUE_OP_TABLE_SIZE),
.RX_QUEUE_OP_TABLE_SIZE(RX_QUEUE_OP_TABLE_SIZE),
.TX_CPL_QUEUE_OP_TABLE_SIZE(TX_CPL_QUEUE_OP_TABLE_SIZE),
.RX_CPL_QUEUE_OP_TABLE_SIZE(RX_CPL_QUEUE_OP_TABLE_SIZE),
.TX_QUEUE_INDEX_WIDTH(TX_QUEUE_INDEX_WIDTH),
.RX_QUEUE_INDEX_WIDTH(RX_QUEUE_INDEX_WIDTH),
.TX_CPL_QUEUE_INDEX_WIDTH(TX_CPL_QUEUE_INDEX_WIDTH),
.RX_CPL_QUEUE_INDEX_WIDTH(RX_CPL_QUEUE_INDEX_WIDTH),
.EVENT_QUEUE_PIPELINE(EVENT_QUEUE_PIPELINE),
.TX_QUEUE_PIPELINE(TX_QUEUE_PIPELINE),
.RX_QUEUE_PIPELINE(RX_QUEUE_PIPELINE),
.TX_CPL_QUEUE_PIPELINE(TX_CPL_QUEUE_PIPELINE),
.RX_CPL_QUEUE_PIPELINE(RX_CPL_QUEUE_PIPELINE),
// TX and RX engine configuration (port)
.TX_DESC_TABLE_SIZE(TX_DESC_TABLE_SIZE),
.RX_DESC_TABLE_SIZE(RX_DESC_TABLE_SIZE),
// Scheduler configuration (port)
.TX_SCHEDULER_OP_TABLE_SIZE(TX_SCHEDULER_OP_TABLE_SIZE),
.TX_SCHEDULER_PIPELINE(TX_SCHEDULER_PIPELINE),
.TDMA_INDEX_WIDTH(TDMA_INDEX_WIDTH),
// Timestamping configuration (port)
.PTP_TS_ENABLE(PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
// Interface configuration (port)
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
.RX_RSS_ENABLE(RX_RSS_ENABLE),
.RX_HASH_ENABLE(RX_HASH_ENABLE),
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.MAX_TX_SIZE(MAX_TX_SIZE),
.MAX_RX_SIZE(MAX_RX_SIZE),
.TX_RAM_SIZE(TX_RAM_SIZE),
.RX_RAM_SIZE(RX_RAM_SIZE),
// Application block configuration
.APP_ENABLE(APP_ENABLE),
.APP_CTRL_ENABLE(APP_CTRL_ENABLE),
.APP_DMA_ENABLE(APP_DMA_ENABLE),
.APP_AXIS_DIRECT_ENABLE(APP_AXIS_DIRECT_ENABLE),
.APP_AXIS_SYNC_ENABLE(APP_AXIS_SYNC_ENABLE),
.APP_AXIS_IF_ENABLE(APP_AXIS_IF_ENABLE),
.APP_STAT_ENABLE(APP_STAT_ENABLE),
// DMA interface configuration
.DMA_ADDR_WIDTH(DMA_ADDR_WIDTH),
.DMA_LEN_WIDTH(DMA_LEN_WIDTH),
.DMA_TAG_WIDTH(DMA_TAG_WIDTH),
.RAM_SEG_COUNT(RAM_SEG_COUNT),
.RAM_SEG_DATA_WIDTH(RAM_SEG_DATA_WIDTH),
.RAM_SEG_ADDR_WIDTH(RAM_SEG_ADDR_WIDTH),
.RAM_SEG_BE_WIDTH(RAM_SEG_BE_WIDTH),
.IF_RAM_SEL_WIDTH(IF_RAM_SEL_WIDTH),
.RAM_SEL_WIDTH(RAM_SEL_WIDTH),
.RAM_ADDR_WIDTH(RAM_ADDR_WIDTH),
.RAM_PIPELINE(RAM_PIPELINE),
.MSI_COUNT(IRQ_COUNT),
// AXI lite interface configuration (control)
.AXIL_CTRL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
.AXIL_CTRL_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH),
.AXIL_CTRL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH),
.AXIL_IF_CTRL_ADDR_WIDTH(AXIL_IF_CTRL_ADDR_WIDTH),
.AXIL_CSR_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH),
.AXIL_CSR_PASSTHROUGH_ENABLE(AXIL_CSR_PASSTHROUGH_ENABLE),
// AXI lite interface configuration (application control)
.AXIL_APP_CTRL_DATA_WIDTH(AXIL_APP_CTRL_DATA_WIDTH),
.AXIL_APP_CTRL_ADDR_WIDTH(AXIL_APP_CTRL_ADDR_WIDTH),
.AXIL_APP_CTRL_STRB_WIDTH(AXIL_APP_CTRL_STRB_WIDTH),
// Ethernet interface configuration
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.AXIS_SYNC_DATA_WIDTH(AXIS_SYNC_DATA_WIDTH),
.AXIS_TX_USER_WIDTH(AXIS_TX_USER_WIDTH),
.AXIS_RX_USER_WIDTH(AXIS_RX_USER_WIDTH),
.AXIS_RX_USE_READY(AXIS_RX_USE_READY),
.AXIS_TX_PIPELINE(AXIS_TX_PIPELINE),
.AXIS_TX_FIFO_PIPELINE(AXIS_TX_FIFO_PIPELINE),
.AXIS_TX_TS_PIPELINE(AXIS_TX_TS_PIPELINE),
.AXIS_RX_PIPELINE(AXIS_RX_PIPELINE),
.AXIS_RX_FIFO_PIPELINE(AXIS_RX_FIFO_PIPELINE),
// Statistics counter subsystem
.STAT_ENABLE(STAT_ENABLE),
.STAT_INC_WIDTH(STAT_INC_WIDTH),
.STAT_ID_WIDTH(STAT_ID_WIDTH)
)
core_inst (
.clk(clk),
.rst(rst),
/*
* DMA read descriptor output
*/
.m_axis_dma_read_desc_dma_addr(dma_read_desc_dma_addr),
.m_axis_dma_read_desc_ram_sel(dma_read_desc_ram_sel),
.m_axis_dma_read_desc_ram_addr(dma_read_desc_ram_addr),
.m_axis_dma_read_desc_len(dma_read_desc_len),
.m_axis_dma_read_desc_tag(dma_read_desc_tag),
.m_axis_dma_read_desc_valid(dma_read_desc_valid),
.m_axis_dma_read_desc_ready(dma_read_desc_ready),
/*
* DMA read descriptor status input
*/
.s_axis_dma_read_desc_status_tag(dma_read_desc_status_tag),
.s_axis_dma_read_desc_status_error(dma_read_desc_status_error),
.s_axis_dma_read_desc_status_valid(dma_read_desc_status_valid),
/*
* DMA write descriptor output
*/
.m_axis_dma_write_desc_dma_addr(dma_write_desc_dma_addr),
.m_axis_dma_write_desc_ram_sel(dma_write_desc_ram_sel),
.m_axis_dma_write_desc_ram_addr(dma_write_desc_ram_addr),
.m_axis_dma_write_desc_len(dma_write_desc_len),
.m_axis_dma_write_desc_tag(dma_write_desc_tag),
.m_axis_dma_write_desc_valid(dma_write_desc_valid),
.m_axis_dma_write_desc_ready(dma_write_desc_ready),
/*
* DMA write descriptor status input
*/
.s_axis_dma_write_desc_status_tag(dma_write_desc_status_tag),
.s_axis_dma_write_desc_status_error(dma_write_desc_status_error),
.s_axis_dma_write_desc_status_valid(dma_write_desc_status_valid),
/*
* AXI-Lite slave interface (control)
*/
.s_axil_ctrl_awaddr(s_axil_ctrl_awaddr),
.s_axil_ctrl_awprot(s_axil_ctrl_awprot),
.s_axil_ctrl_awvalid(s_axil_ctrl_awvalid),
.s_axil_ctrl_awready(s_axil_ctrl_awready),
.s_axil_ctrl_wdata(s_axil_ctrl_wdata),
.s_axil_ctrl_wstrb(s_axil_ctrl_wstrb),
.s_axil_ctrl_wvalid(s_axil_ctrl_wvalid),
.s_axil_ctrl_wready(s_axil_ctrl_wready),
.s_axil_ctrl_bresp(s_axil_ctrl_bresp),
.s_axil_ctrl_bvalid(s_axil_ctrl_bvalid),
.s_axil_ctrl_bready(s_axil_ctrl_bready),
.s_axil_ctrl_araddr(s_axil_ctrl_araddr),
.s_axil_ctrl_arprot(s_axil_ctrl_arprot),
.s_axil_ctrl_arvalid(s_axil_ctrl_arvalid),
.s_axil_ctrl_arready(s_axil_ctrl_arready),
.s_axil_ctrl_rdata(s_axil_ctrl_rdata),
.s_axil_ctrl_rresp(s_axil_ctrl_rresp),
.s_axil_ctrl_rvalid(s_axil_ctrl_rvalid),
.s_axil_ctrl_rready(s_axil_ctrl_rready),
/*
* AXI-Lite slave interface (application control)
*/
.s_axil_app_ctrl_awaddr(s_axil_app_ctrl_awaddr),
.s_axil_app_ctrl_awprot(s_axil_app_ctrl_awprot),
.s_axil_app_ctrl_awvalid(s_axil_app_ctrl_awvalid),
.s_axil_app_ctrl_awready(s_axil_app_ctrl_awready),
.s_axil_app_ctrl_wdata(s_axil_app_ctrl_wdata),
.s_axil_app_ctrl_wstrb(s_axil_app_ctrl_wstrb),
.s_axil_app_ctrl_wvalid(s_axil_app_ctrl_wvalid),
.s_axil_app_ctrl_wready(s_axil_app_ctrl_wready),
.s_axil_app_ctrl_bresp(s_axil_app_ctrl_bresp),
.s_axil_app_ctrl_bvalid(s_axil_app_ctrl_bvalid),
.s_axil_app_ctrl_bready(s_axil_app_ctrl_bready),
.s_axil_app_ctrl_araddr(s_axil_app_ctrl_araddr),
.s_axil_app_ctrl_arprot(s_axil_app_ctrl_arprot),
.s_axil_app_ctrl_arvalid(s_axil_app_ctrl_arvalid),
.s_axil_app_ctrl_arready(s_axil_app_ctrl_arready),
.s_axil_app_ctrl_rdata(s_axil_app_ctrl_rdata),
.s_axil_app_ctrl_rresp(s_axil_app_ctrl_rresp),
.s_axil_app_ctrl_rvalid(s_axil_app_ctrl_rvalid),
.s_axil_app_ctrl_rready(s_axil_app_ctrl_rready),
/*
* AXI-Lite master interface (passthrough for NIC control and status)
*/
.m_axil_csr_awaddr(m_axil_csr_awaddr),
.m_axil_csr_awprot(m_axil_csr_awprot),
.m_axil_csr_awvalid(m_axil_csr_awvalid),
.m_axil_csr_awready(m_axil_csr_awready),
.m_axil_csr_wdata(m_axil_csr_wdata),
.m_axil_csr_wstrb(m_axil_csr_wstrb),
.m_axil_csr_wvalid(m_axil_csr_wvalid),
.m_axil_csr_wready(m_axil_csr_wready),
.m_axil_csr_bresp(m_axil_csr_bresp),
.m_axil_csr_bvalid(m_axil_csr_bvalid),
.m_axil_csr_bready(m_axil_csr_bready),
.m_axil_csr_araddr(m_axil_csr_araddr),
.m_axil_csr_arprot(m_axil_csr_arprot),
.m_axil_csr_arvalid(m_axil_csr_arvalid),
.m_axil_csr_arready(m_axil_csr_arready),
.m_axil_csr_rdata(m_axil_csr_rdata),
.m_axil_csr_rresp(m_axil_csr_rresp),
.m_axil_csr_rvalid(m_axil_csr_rvalid),
.m_axil_csr_rready(m_axil_csr_rready),
/*
* Control register interface
*/
.ctrl_reg_wr_addr(ctrl_reg_wr_addr),
.ctrl_reg_wr_data(ctrl_reg_wr_data),
.ctrl_reg_wr_strb(ctrl_reg_wr_strb),
.ctrl_reg_wr_en(ctrl_reg_wr_en),
.ctrl_reg_wr_wait(ctrl_reg_wr_wait),
.ctrl_reg_wr_ack(ctrl_reg_wr_ack),
.ctrl_reg_rd_addr(ctrl_reg_rd_addr),
.ctrl_reg_rd_en(ctrl_reg_rd_en),
.ctrl_reg_rd_data(ctrl_reg_rd_data),
.ctrl_reg_rd_wait(ctrl_reg_rd_wait),
.ctrl_reg_rd_ack(ctrl_reg_rd_ack),
/*
* RAM interface
*/
.dma_ram_wr_cmd_sel(dma_ram_wr_cmd_sel),
.dma_ram_wr_cmd_be(dma_ram_wr_cmd_be),
.dma_ram_wr_cmd_addr(dma_ram_wr_cmd_addr),
.dma_ram_wr_cmd_data(dma_ram_wr_cmd_data),
.dma_ram_wr_cmd_valid(dma_ram_wr_cmd_valid),
.dma_ram_wr_cmd_ready(dma_ram_wr_cmd_ready),
.dma_ram_wr_done(dma_ram_wr_done),
.dma_ram_rd_cmd_sel(dma_ram_rd_cmd_sel),
.dma_ram_rd_cmd_addr(dma_ram_rd_cmd_addr),
.dma_ram_rd_cmd_valid(dma_ram_rd_cmd_valid),
.dma_ram_rd_cmd_ready(dma_ram_rd_cmd_ready),
.dma_ram_rd_resp_data(dma_ram_rd_resp_data),
.dma_ram_rd_resp_valid(dma_ram_rd_resp_valid),
.dma_ram_rd_resp_ready(dma_ram_rd_resp_ready),
/*
* MSI request outputs
*/
.msi_irq(irq),
/*
* PTP clock
*/
.ptp_sample_clk(ptp_sample_clk),
.ptp_pps(ptp_pps),
.ptp_ts_96(ptp_ts_96),
.ptp_ts_step(ptp_ts_step),
.ptp_perout_locked(ptp_perout_locked),
.ptp_perout_error(ptp_perout_error),
.ptp_perout_pulse(ptp_perout_pulse),
/*
* Ethernet
*/
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.tx_ptp_ts_96(tx_ptp_ts_96),
.tx_ptp_ts_step(tx_ptp_ts_step),
.m_axis_tx_tdata(m_axis_tx_tdata),
.m_axis_tx_tkeep(m_axis_tx_tkeep),
.m_axis_tx_tvalid(m_axis_tx_tvalid),
.m_axis_tx_tready(m_axis_tx_tready),
.m_axis_tx_tlast(m_axis_tx_tlast),
.m_axis_tx_tuser(m_axis_tx_tuser),
.s_axis_tx_ptp_ts(s_axis_tx_ptp_ts),
.s_axis_tx_ptp_ts_tag(s_axis_tx_ptp_ts_tag),
.s_axis_tx_ptp_ts_valid(s_axis_tx_ptp_ts_valid),
.s_axis_tx_ptp_ts_ready(s_axis_tx_ptp_ts_ready),
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.rx_ptp_ts_96(rx_ptp_ts_96),
.rx_ptp_ts_step(rx_ptp_ts_step),
.s_axis_rx_tdata(s_axis_rx_tdata),
.s_axis_rx_tkeep(s_axis_rx_tkeep),
.s_axis_rx_tvalid(s_axis_rx_tvalid),
.s_axis_rx_tready(s_axis_rx_tready),
.s_axis_rx_tlast(s_axis_rx_tlast),
.s_axis_rx_tuser(s_axis_rx_tuser),
/*
* Statistics input
*/
.s_axis_stat_tdata(s_axis_stat_tdata),
.s_axis_stat_tid(s_axis_stat_tid),
.s_axis_stat_tvalid(s_axis_stat_tvalid),
.s_axis_stat_tready(s_axis_stat_tready)
);
endmodule
`resetall

387
fpga/common/tb/mqnic_core_axi/Makefile Normal file
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@ -0,0 +1,387 @@
# Copyright 2021, The Regents of the University of California.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
#
# 1. Redistributions of source code must retain the above copyright notice,
# this list of conditions and the following disclaimer.
#
# 2. Redistributions in binary form must reproduce the above copyright notice,
# this list of conditions and the following disclaimer in the documentation
# and/or other materials provided with the distribution.
#
# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
# OF SUCH DAMAGE.
#
# The views and conclusions contained in the software and documentation are those
# of the authors and should not be interpreted as representing official policies,
# either expressed or implied, of The Regents of the University of California.
TOPLEVEL_LANG = verilog
SIM ?= icarus
WAVES ?= 0
COCOTB_HDL_TIMEUNIT = 1ns
COCOTB_HDL_TIMEPRECISION = 1ps
DUT = mqnic_core_axi
TOPLEVEL = $(DUT)
MODULE = test_$(DUT)
VERILOG_SOURCES += ../../rtl/$(DUT).v
VERILOG_SOURCES += ../../rtl/mqnic_core.v
VERILOG_SOURCES += ../../rtl/mqnic_interface.v
VERILOG_SOURCES += ../../rtl/mqnic_port.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp_clock.v
VERILOG_SOURCES += ../../rtl/mqnic_ptp_perout.v
VERILOG_SOURCES += ../../rtl/cpl_write.v
VERILOG_SOURCES += ../../rtl/cpl_op_mux.v
VERILOG_SOURCES += ../../rtl/desc_fetch.v
VERILOG_SOURCES += ../../rtl/desc_op_mux.v
VERILOG_SOURCES += ../../rtl/event_mux.v
VERILOG_SOURCES += ../../rtl/queue_manager.v
VERILOG_SOURCES += ../../rtl/cpl_queue_manager.v
VERILOG_SOURCES += ../../rtl/tx_engine.v
VERILOG_SOURCES += ../../rtl/rx_engine.v
VERILOG_SOURCES += ../../rtl/tx_checksum.v
VERILOG_SOURCES += ../../rtl/rx_hash.v
VERILOG_SOURCES += ../../rtl/rx_checksum.v
VERILOG_SOURCES += ../../rtl/stats_counter.v
VERILOG_SOURCES += ../../rtl/stats_collect.v
VERILOG_SOURCES += ../../rtl/stats_pcie_if.v
VERILOG_SOURCES += ../../rtl/stats_pcie_tlp.v
VERILOG_SOURCES += ../../rtl/stats_dma_if_pcie.v
VERILOG_SOURCES += ../../rtl/stats_dma_latency.v
VERILOG_SOURCES += ../../rtl/mqnic_tx_scheduler_block_rr.v
VERILOG_SOURCES += ../../rtl/tx_scheduler_rr.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_clock_cdc.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_perout.v
VERILOG_SOURCES += ../../lib/eth/rtl/ptp_ts_extract.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_addr.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_rd.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_crossbar_wr.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_rd.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_reg_if_wr.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_rd.v
VERILOG_SOURCES += ../../lib/axi/rtl/axil_register_wr.v
VERILOG_SOURCES += ../../lib/axi/rtl/arbiter.v
VERILOG_SOURCES += ../../lib/axi/rtl/priority_encoder.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_arb_mux.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_async_fifo_adapter.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_pipeline_fifo.v
VERILOG_SOURCES += ../../lib/axis/rtl/axis_register.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_axi.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_axi_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_axi_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_mux_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_desc_mux.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_rd.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_ram_demux_wr.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_sink.v
VERILOG_SOURCES += ../../lib/pcie/rtl/dma_client_axis_source.v
VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
# module parameters
# Structural configuration
export PARAM_IF_COUNT ?= 1
export PARAM_PORTS_PER_IF ?= 1
# PTP configuration
export PARAM_PTP_USE_SAMPLE_CLOCK ?= 0
export PARAM_PTP_PEROUT_ENABLE ?= 0
export PARAM_PTP_PEROUT_COUNT ?= 1
# Queue manager configuration (interface)
export PARAM_EVENT_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_TX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_RX_QUEUE_OP_TABLE_SIZE ?= 32
export PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_TX_QUEUE_OP_TABLE_SIZE)
export PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE ?= $(PARAM_RX_QUEUE_OP_TABLE_SIZE)
export PARAM_TX_QUEUE_INDEX_WIDTH ?= 13
export PARAM_RX_QUEUE_INDEX_WIDTH ?= 8
export PARAM_TX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_TX_QUEUE_INDEX_WIDTH)
export PARAM_RX_CPL_QUEUE_INDEX_WIDTH ?= $(PARAM_RX_QUEUE_INDEX_WIDTH)
export PARAM_EVENT_QUEUE_PIPELINE ?= 3
export PARAM_TX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_TX_QUEUE_INDEX_WIDTH)-12, 0))")
export PARAM_RX_QUEUE_PIPELINE ?= $(shell python -c "print(3 + max($(PARAM_RX_QUEUE_INDEX_WIDTH)-12, 0))")
export PARAM_TX_CPL_QUEUE_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_RX_CPL_QUEUE_PIPELINE ?= $(PARAM_RX_QUEUE_PIPELINE)
# TX and RX engine configuration (port)
export PARAM_TX_DESC_TABLE_SIZE ?= 32
export PARAM_RX_DESC_TABLE_SIZE ?= 32
# Scheduler configuration (port)
export PARAM_TX_SCHEDULER_OP_TABLE_SIZE ?= $(PARAM_TX_DESC_TABLE_SIZE)
export PARAM_TX_SCHEDULER_PIPELINE ?= $(PARAM_TX_QUEUE_PIPELINE)
export PARAM_TDMA_INDEX_WIDTH ?= 6
# Timestamping configuration (port)
export PARAM_PTP_TS_ENABLE ?= 1
export PARAM_TX_PTP_TS_FIFO_DEPTH ?= 32
export PARAM_RX_PTP_TS_FIFO_DEPTH ?= 32
# Interface configuration (port)
export PARAM_TX_CHECKSUM_ENABLE ?= 1
export PARAM_RX_RSS_ENABLE ?= 1
export PARAM_RX_HASH_ENABLE ?= 1
export PARAM_RX_CHECKSUM_ENABLE ?= 1
export PARAM_TX_FIFO_DEPTH ?= 32768
export PARAM_RX_FIFO_DEPTH ?= 131072
export PARAM_MAX_TX_SIZE ?= 9214
export PARAM_MAX_RX_SIZE ?= 9214
export PARAM_TX_RAM_SIZE ?= 131072
export PARAM_RX_RAM_SIZE ?= 131072
# Application block configuration
export PARAM_APP_ENABLE ?= 0
export PARAM_APP_CTRL_ENABLE ?= 1
export PARAM_APP_DMA_ENABLE ?= 1
export PARAM_APP_AXIS_DIRECT_ENABLE ?= 1
export PARAM_APP_AXIS_SYNC_ENABLE ?= 1
export PARAM_APP_AXIS_IF_ENABLE ?= 1
export PARAM_APP_STAT_ENABLE ?= 1
# AXI interface configuration (DMA)
export PARAM_AXI_DATA_WIDTH ?= 128
export PARAM_AXI_ADDR_WIDTH ?= 49
export PARAM_AXI_STRB_WIDTH ?= $(shell expr $(PARAM_AXI_DATA_WIDTH) / 8 )
export PARAM_AXI_ID_WIDTH ?= 6
# DMA interface configuration
export PARAM_DMA_LEN_WIDTH ?= 16
export PARAM_DMA_TAG_WIDTH ?= 16
export PARAM_RAM_PIPELINE ?= 2
export PARAM_AXI_DMA_MAX_BURST_LEN ?= 16
export PARAM_AXI_DMA_USE_ID ?= 1
export PARAM_AXI_DMA_READ_OP_TABLE_SIZE ?= $(shell echo "$$(( 1 << $(PARAM_AXI_ID_WIDTH) ))" )
export PARAM_AXI_DMA_WRITE_OP_TABLE_SIZE ?= $(shell echo "$$(( 1 << $(PARAM_AXI_ID_WIDTH) ))" )
# Interrupts
export PARAM_IRQ_COUNT ?= 32
# AXI lite interface configuration (control)
export PARAM_AXIL_CTRL_DATA_WIDTH ?= 32
export PARAM_AXIL_CTRL_ADDR_WIDTH ?= 24
export PARAM_AXIL_CSR_PASSTHROUGH_ENABLE ?= 0
# AXI lite interface configuration (application control)
export PARAM_AXIL_APP_CTRL_DATA_WIDTH ?= $(PARAM_AXIL_CTRL_DATA_WIDTH)
export PARAM_AXIL_APP_CTRL_ADDR_WIDTH ?= 24
# Ethernet interface configuration
export PARAM_AXIS_DATA_WIDTH ?= 64
export PARAM_AXIS_SYNC_DATA_WIDTH ?= $(PARAM_AXIS_DATA_WIDTH)
export PARAM_AXIS_RX_USE_READY ?= 0
export PARAM_AXIS_TX_PIPELINE ?= 0
export PARAM_AXIS_TX_FIFO_PIPELINE ?= 2
export PARAM_AXIS_TX_TS_PIPELINE ?= 0
export PARAM_AXIS_RX_PIPELINE ?= 0
export PARAM_AXIS_RX_FIFO_PIPELINE ?= 2
# Statistics counter subsystem
export PARAM_STAT_ENABLE ?= 1
export PARAM_STAT_DMA_ENABLE ?= 1
export PARAM_STAT_PCIE_ENABLE ?= 1
export PARAM_STAT_INC_WIDTH ?= 24
export PARAM_STAT_ID_WIDTH ?= 12
ifeq ($(SIM), icarus)
PLUSARGS += -fst
COMPILE_ARGS += -P $(TOPLEVEL).IF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).PORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_PEROUT_COUNT=$(PARAM_PTP_PEROUT_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).EVENT_QUEUE_OP_TABLE_SIZE=$(PARAM_EVENT_QUEUE_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_QUEUE_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_QUEUE_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_QUEUE_INDEX_WIDTH=$(PARAM_TX_QUEUE_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).RX_QUEUE_INDEX_WIDTH=$(PARAM_RX_QUEUE_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_TX_CPL_QUEUE_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).RX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_RX_CPL_QUEUE_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).EVENT_QUEUE_PIPELINE=$(PARAM_EVENT_QUEUE_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_QUEUE_PIPELINE=$(PARAM_TX_QUEUE_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_QUEUE_PIPELINE=$(PARAM_RX_QUEUE_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CPL_QUEUE_PIPELINE=$(PARAM_TX_CPL_QUEUE_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_CPL_QUEUE_PIPELINE=$(PARAM_RX_CPL_QUEUE_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_DESC_TABLE_SIZE=$(PARAM_TX_DESC_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_DESC_TABLE_SIZE=$(PARAM_RX_DESC_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_OP_TABLE_SIZE=$(PARAM_TX_SCHEDULER_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).TDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).PTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).RX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).TX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).RX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH)
COMPILE_ARGS += -P $(TOPLEVEL).MAX_TX_SIZE=$(PARAM_MAX_TX_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).MAX_RX_SIZE=$(PARAM_MAX_RX_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).TX_RAM_SIZE=$(PARAM_TX_RAM_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).RX_RAM_SIZE=$(PARAM_RX_RAM_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).APP_ENABLE=$(PARAM_APP_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).APP_CTRL_ENABLE=$(PARAM_APP_CTRL_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).APP_DMA_ENABLE=$(PARAM_APP_DMA_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_DIRECT_ENABLE=$(PARAM_APP_AXIS_DIRECT_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).APP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).APP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).AXI_DATA_WIDTH=$(PARAM_AXI_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXI_ADDR_WIDTH=$(PARAM_AXI_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXI_STRB_WIDTH=$(PARAM_AXI_STRB_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXI_ID_WIDTH=$(PARAM_AXI_ID_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).DMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).DMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).RAM_PIPELINE=$(PARAM_RAM_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).AXI_DMA_MAX_BURST_LEN=$(PARAM_AXI_DMA_MAX_BURST_LEN)
COMPILE_ARGS += -P $(TOPLEVEL).AXI_DMA_USE_ID=$(PARAM_AXI_DMA_USE_ID)
COMPILE_ARGS += -P $(TOPLEVEL).AXI_DMA_READ_OP_TABLE_SIZE=$(PARAM_AXI_DMA_READ_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).AXI_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_AXI_DMA_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).IRQ_COUNT=$(PARAM_IRQ_COUNT)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_CSR_PASSTHROUGH_ENABLE=$(PARAM_AXIL_CSR_PASSTHROUGH_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIL_APP_CTRL_ADDR_WIDTH=$(PARAM_AXIL_APP_CTRL_ADDR_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_DATA_WIDTH=$(PARAM_AXIS_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_SYNC_DATA_WIDTH=$(PARAM_AXIS_SYNC_DATA_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_RX_USE_READY=$(PARAM_AXIS_RX_USE_READY)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_TX_PIPELINE=$(PARAM_AXIS_TX_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_TX_FIFO_PIPELINE=$(PARAM_AXIS_TX_FIFO_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_TX_TS_PIPELINE=$(PARAM_AXIS_TX_TS_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_RX_PIPELINE=$(PARAM_AXIS_RX_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).AXIS_RX_FIFO_PIPELINE=$(PARAM_AXIS_RX_FIFO_PIPELINE)
COMPILE_ARGS += -P $(TOPLEVEL).STAT_ENABLE=$(PARAM_STAT_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).STAT_DMA_ENABLE=$(PARAM_STAT_DMA_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).STAT_PCIE_ENABLE=$(PARAM_STAT_PCIE_ENABLE)
COMPILE_ARGS += -P $(TOPLEVEL).STAT_INC_WIDTH=$(PARAM_STAT_INC_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).STAT_ID_WIDTH=$(PARAM_STAT_ID_WIDTH)
ifeq ($(WAVES), 1)
VERILOG_SOURCES += iverilog_dump.v
COMPILE_ARGS += -s iverilog_dump
endif
else ifeq ($(SIM), verilator)
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
COMPILE_ARGS += -GIF_COUNT=$(PARAM_IF_COUNT)
COMPILE_ARGS += -GPORTS_PER_IF=$(PARAM_PORTS_PER_IF)
COMPILE_ARGS += -GPTP_USE_SAMPLE_CLOCK=$(PARAM_PTP_USE_SAMPLE_CLOCK)
COMPILE_ARGS += -GPTP_PEROUT_ENABLE=$(PARAM_PTP_PEROUT_ENABLE)
COMPILE_ARGS += -GPTP_PEROUT_COUNT=$(PARAM_PTP_PEROUT_COUNT)
COMPILE_ARGS += -GEVENT_QUEUE_OP_TABLE_SIZE=$(PARAM_EVENT_QUEUE_OP_TABLE_SIZE)
COMPILE_ARGS += -GTX_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_QUEUE_OP_TABLE_SIZE)
COMPILE_ARGS += -GRX_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_QUEUE_OP_TABLE_SIZE)
COMPILE_ARGS += -GTX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_TX_CPL_QUEUE_OP_TABLE_SIZE)
COMPILE_ARGS += -GRX_CPL_QUEUE_OP_TABLE_SIZE=$(PARAM_RX_CPL_QUEUE_OP_TABLE_SIZE)
COMPILE_ARGS += -GTX_QUEUE_INDEX_WIDTH=$(PARAM_TX_QUEUE_INDEX_WIDTH)
COMPILE_ARGS += -GRX_QUEUE_INDEX_WIDTH=$(PARAM_RX_QUEUE_INDEX_WIDTH)
COMPILE_ARGS += -GTX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_TX_CPL_QUEUE_INDEX_WIDTH)
COMPILE_ARGS += -GRX_CPL_QUEUE_INDEX_WIDTH=$(PARAM_RX_CPL_QUEUE_INDEX_WIDTH)
COMPILE_ARGS += -GEVENT_QUEUE_PIPELINE=$(PARAM_EVENT_QUEUE_PIPELINE)
COMPILE_ARGS += -GTX_QUEUE_PIPELINE=$(PARAM_TX_QUEUE_PIPELINE)
COMPILE_ARGS += -GRX_QUEUE_PIPELINE=$(PARAM_RX_QUEUE_PIPELINE)
COMPILE_ARGS += -GTX_CPL_QUEUE_PIPELINE=$(PARAM_TX_CPL_QUEUE_PIPELINE)
COMPILE_ARGS += -GRX_CPL_QUEUE_PIPELINE=$(PARAM_RX_CPL_QUEUE_PIPELINE)
COMPILE_ARGS += -GTX_DESC_TABLE_SIZE=$(PARAM_TX_DESC_TABLE_SIZE)
COMPILE_ARGS += -GRX_DESC_TABLE_SIZE=$(PARAM_RX_DESC_TABLE_SIZE)
COMPILE_ARGS += -GTX_SCHEDULER_OP_TABLE_SIZE=$(PARAM_TX_SCHEDULER_OP_TABLE_SIZE)
COMPILE_ARGS += -GTX_SCHEDULER_PIPELINE=$(PARAM_TX_SCHEDULER_PIPELINE)
COMPILE_ARGS += -GTDMA_INDEX_WIDTH=$(PARAM_TDMA_INDEX_WIDTH)
COMPILE_ARGS += -GPTP_TS_ENABLE=$(PARAM_PTP_TS_ENABLE)
COMPILE_ARGS += -GTX_PTP_TS_FIFO_DEPTH=$(PARAM_TX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GRX_PTP_TS_FIFO_DEPTH=$(PARAM_RX_PTP_TS_FIFO_DEPTH)
COMPILE_ARGS += -GTX_CHECKSUM_ENABLE=$(PARAM_TX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GRX_RSS_ENABLE=$(PARAM_RX_RSS_ENABLE)
COMPILE_ARGS += -GRX_HASH_ENABLE=$(PARAM_RX_HASH_ENABLE)
COMPILE_ARGS += -GRX_CHECKSUM_ENABLE=$(PARAM_RX_CHECKSUM_ENABLE)
COMPILE_ARGS += -GTX_FIFO_DEPTH=$(PARAM_TX_FIFO_DEPTH)
COMPILE_ARGS += -GRX_FIFO_DEPTH=$(PARAM_RX_FIFO_DEPTH)
COMPILE_ARGS += -GMAX_TX_SIZE=$(PARAM_MAX_TX_SIZE)
COMPILE_ARGS += -GMAX_RX_SIZE=$(PARAM_MAX_RX_SIZE)
COMPILE_ARGS += -GTX_RAM_SIZE=$(PARAM_TX_RAM_SIZE)
COMPILE_ARGS += -GRX_RAM_SIZE=$(PARAM_RX_RAM_SIZE)
COMPILE_ARGS += -GAPP_ENABLE=$(PARAM_APP_ENABLE)
COMPILE_ARGS += -GAPP_CTRL_ENABLE=$(PARAM_APP_CTRL_ENABLE)
COMPILE_ARGS += -GAPP_DMA_ENABLE=$(PARAM_APP_DMA_ENABLE)
COMPILE_ARGS += -GAPP_AXIS_DIRECT_ENABLE=$(PARAM_APP_AXIS_DIRECT_ENABLE)
COMPILE_ARGS += -GAPP_AXIS_SYNC_ENABLE=$(PARAM_APP_AXIS_SYNC_ENABLE)
COMPILE_ARGS += -GAPP_AXIS_IF_ENABLE=$(PARAM_APP_AXIS_IF_ENABLE)
COMPILE_ARGS += -GAPP_STAT_ENABLE=$(PARAM_APP_STAT_ENABLE)
COMPILE_ARGS += -GAXI_DATA_WIDTH=$(PARAM_AXI_DATA_WIDTH)
COMPILE_ARGS += -GAXI_ADDR_WIDTH=$(PARAM_AXI_ADDR_WIDTH)
COMPILE_ARGS += -GAXI_STRB_WIDTH=$(PARAM_AXI_STRB_WIDTH)
COMPILE_ARGS += -GAXI_ID_WIDTH=$(PARAM_AXI_ID_WIDTH)
COMPILE_ARGS += -GDMA_LEN_WIDTH=$(PARAM_DMA_LEN_WIDTH)
COMPILE_ARGS += -GDMA_TAG_WIDTH=$(PARAM_DMA_TAG_WIDTH)
COMPILE_ARGS += -GRAM_PIPELINE=$(PARAM_RAM_PIPELINE)
COMPILE_ARGS += -GAXI_DMA_MAX_BURST_LEN=$(PARAM_AXI_DMA_MAX_BURST_LEN)
COMPILE_ARGS += -GAXI_DMA_USE_ID=$(PARAM_AXI_DMA_USE_ID)
COMPILE_ARGS += -GAXI_DMA_READ_OP_TABLE_SIZE=$(PARAM_AXI_DMA_READ_OP_TABLE_SIZE)
COMPILE_ARGS += -GAXI_DMA_WRITE_OP_TABLE_SIZE=$(PARAM_AXI_DMA_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -GIRQ_COUNT=$(PARAM_IRQ_COUNT)
COMPILE_ARGS += -GAXIL_CTRL_DATA_WIDTH=$(PARAM_AXIL_CTRL_DATA_WIDTH)
COMPILE_ARGS += -GAXIL_CTRL_ADDR_WIDTH=$(PARAM_AXIL_CTRL_ADDR_WIDTH)
COMPILE_ARGS += -GAXIL_CSR_PASSTHROUGH_ENABLE=$(PARAM_AXIL_CSR_PASSTHROUGH_ENABLE)
COMPILE_ARGS += -GAXIL_APP_CTRL_DATA_WIDTH=$(PARAM_AXIL_APP_CTRL_DATA_WIDTH)
COMPILE_ARGS += -GAXIL_APP_CTRL_ADDR_WIDTH=$(PARAM_AXIL_APP_CTRL_ADDR_WIDTH)
COMPILE_ARGS += -GAXIS_DATA_WIDTH=$(PARAM_AXIS_DATA_WIDTH)
COMPILE_ARGS += -GAXIS_SYNC_DATA_WIDTH=$(PARAM_AXIS_SYNC_DATA_WIDTH)
COMPILE_ARGS += -GAXIS_RX_USE_READY=$(PARAM_AXIS_RX_USE_READY)
COMPILE_ARGS += -GAXIS_TX_PIPELINE=$(PARAM_AXIS_TX_PIPELINE)
COMPILE_ARGS += -GAXIS_TX_FIFO_PIPELINE=$(PARAM_AXIS_TX_FIFO_PIPELINE)
COMPILE_ARGS += -GAXIS_TX_TS_PIPELINE=$(PARAM_AXIS_TX_TS_PIPELINE)
COMPILE_ARGS += -GAXIS_RX_PIPELINE=$(PARAM_AXIS_RX_PIPELINE)
COMPILE_ARGS += -GAXIS_RX_FIFO_PIPELINE=$(PARAM_AXIS_RX_FIFO_PIPELINE)
COMPILE_ARGS += -GSTAT_ENABLE=$(PARAM_STAT_ENABLE)
COMPILE_ARGS += -GSTAT_DMA_ENABLE=$(PARAM_STAT_DMA_ENABLE)
COMPILE_ARGS += -GSTAT_PCIE_ENABLE=$(PARAM_STAT_PCIE_ENABLE)
COMPILE_ARGS += -GSTAT_INC_WIDTH=$(PARAM_STAT_INC_WIDTH)
COMPILE_ARGS += -GSTAT_ID_WIDTH=$(PARAM_STAT_ID_WIDTH)
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst
endif
endif
include $(shell cocotb-config --makefiles)/Makefile.sim
iverilog_dump.v:
echo 'module iverilog_dump();' > $@
echo 'initial begin' >> $@
echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@
echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@
echo 'end' >> $@
echo 'endmodule' >> $@
clean::
@rm -rf iverilog_dump.v
@rm -rf dump.fst $(TOPLEVEL).fst

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fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py Normal file
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"""
Copyright 2021, The Regents of the University of California.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
The views and conclusions contained in the software and documentation are those
of the authors and should not be interpreted as representing official policies,
either expressed or implied, of The Regents of the University of California.
"""
import logging
import os
import sys
import scapy.utils
from scapy.layers.l2 import Ether
from scapy.layers.inet import IP, UDP
import cocotb_test.simulator
import pytest
import cocotb
from cocotb.log import SimLog
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, Timer
from cocotbext.axi import AxiStreamBus
from cocotbext.axi import AddressSpace
from cocotbext.axi import AxiLiteMaster, AxiLiteBus
from cocotbext.axi import AxiSlave, AxiBus
from cocotbext.eth import EthMac
try:
import mqnic
except ImportError:
# attempt import from current directory
sys.path.insert(0, os.path.join(os.path.dirname(__file__)))
try:
import mqnic
finally:
del sys.path[0]
class TB(object):
def __init__(self, dut):
self.dut = dut
self.log = SimLog("cocotb.tb")
self.log.setLevel(logging.DEBUG)
cocotb.fork(Clock(dut.clk, 4, units="ns").start())
# AXI
self.address_space = AddressSpace()
self.pool = self.address_space.create_pool(0, 0x8000_0000)
self.axil_master = AxiLiteMaster(AxiLiteBus.from_prefix(dut, "s_axil_ctrl"), dut.clk, dut.rst)
self.address_space.register_region(self.axil_master, 0x10_0000_0000)
self.hw_regs = self.address_space.create_window(0x10_0000_0000, self.axil_master.size)
self.axi_slave = AxiSlave(AxiBus.from_prefix(dut, "m_axi"), dut.clk, dut.rst, self.address_space)
self.driver = mqnic.Driver()
# Ethernet
self.port_mac = []
clock_period = 3.102
speed = 10e9
if len(dut.core_inst.iface[0].port[0].rx_fifo_inst.m_axis_tdata) == 64:
# 10G
clock_period = 6.4
speed = 10e9
elif len(dut.core_inst.iface[0].port[0].rx_fifo_inst.m_axis_tdata) == 128:
# 25G
clock_period = 2.56
speed = 25e9
elif len(dut.core_inst.iface[0].port[0].rx_fifo_inst.m_axis_tdata) == 512:
# 100G
clock_period = 3.102
speed = 100e9
for iface in dut.core_inst.iface:
for port in iface.port:
cocotb.fork(Clock(port.rx_async_fifo_inst.s_clk, clock_period, units="ns").start())
cocotb.fork(Clock(port.tx_async_fifo_inst.m_clk, clock_period, units="ns").start())
port.rx_async_fifo_inst.s_rst.setimmediatevalue(0)
port.tx_async_fifo_inst.m_rst.setimmediatevalue(0)
mac = EthMac(
tx_clk=port.tx_async_fifo_inst.m_clk,
tx_rst=port.tx_async_fifo_inst.m_rst,
tx_bus=AxiStreamBus.from_prefix(port, "axis_tx"),
tx_ptp_time=port.ptp.tx_ptp_cdc_inst.output_ts,
tx_ptp_ts=port.ptp.axis_tx_ptp_ts,
tx_ptp_ts_tag=port.ptp.axis_tx_ptp_ts_tag,
tx_ptp_ts_valid=port.ptp.axis_tx_ptp_ts_valid,
rx_clk=port.rx_async_fifo_inst.s_clk,
rx_rst=port.rx_async_fifo_inst.s_rst,
rx_bus=AxiStreamBus.from_prefix(port, "axis_rx"),
rx_ptp_time=port.ptp.rx_ptp_cdc_inst.output_ts,
ifg=12, speed=speed
)
self.port_mac.append(mac)
dut.ctrl_reg_wr_wait.setimmediatevalue(0)
dut.ctrl_reg_wr_ack.setimmediatevalue(0)
dut.ctrl_reg_rd_data.setimmediatevalue(0)
dut.ctrl_reg_rd_wait.setimmediatevalue(0)
dut.ctrl_reg_rd_ack.setimmediatevalue(0)
dut.ptp_sample_clk.setimmediatevalue(0)
dut.s_axis_stat_tdata.setimmediatevalue(0)
dut.s_axis_stat_tid.setimmediatevalue(0)
dut.s_axis_stat_tvalid.setimmediatevalue(0)
self.loopback_enable = False
cocotb.fork(self._run_loopback())
async def init(self):
self.dut.rst.setimmediatevalue(0)
for mac in self.port_mac:
mac.rx.reset.setimmediatevalue(0)
mac.tx.reset.setimmediatevalue(0)
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 1
for mac in self.port_mac:
mac.rx.reset.value = 1
mac.tx.reset.value = 1
await RisingEdge(self.dut.clk)
await RisingEdge(self.dut.clk)
self.dut.rst.value = 0
for mac in self.port_mac:
mac.rx.reset.value = 0
mac.tx.reset.value = 0
async def _run_loopback(self):
while True:
await RisingEdge(self.dut.clk)
if self.loopback_enable:
for mac in self.port_mac:
if not mac.tx.empty():
await mac.rx.send(await mac.tx.recv())
@cocotb.test()
async def run_test_nic(dut):
tb = TB(dut)
await tb.init()
tb.log.info("Init driver")
await tb.driver.init_axi_dev(tb.pool, tb.hw_regs, irq=dut.irq)
await tb.driver.interfaces[0].open()
# enable queues
tb.log.info("Enable queues")
await tb.driver.interfaces[0].ports[0].hw_regs.write_dword(mqnic.MQNIC_PORT_REG_SCHED_ENABLE, 0x00000001)
for k in range(tb.driver.interfaces[0].tx_queue_count):
await tb.driver.interfaces[0].ports[0].schedulers[0].hw_regs.write_dword(4*k, 0x00000003)
# wait for all writes to complete
await tb.driver.hw_regs.read_dword(0)
tb.log.info("Init complete")
tb.log.info("Send and receive single packet")
data = bytearray([x % 256 for x in range(1024)])
await tb.driver.interfaces[0].start_xmit(data, 0)
pkt = await tb.port_mac[0].tx.recv()
tb.log.info("Packet: %s", pkt)
await tb.port_mac[0].rx.send(pkt)
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
tb.log.info("RX and TX checksum tests")
payload = bytes([x % 256 for x in range(256)])
eth = Ether(src='5A:51:52:53:54:55', dst='DA:D1:D2:D3:D4:D5')
ip = IP(src='192.168.1.100', dst='192.168.1.101')
udp = UDP(sport=1, dport=2)
test_pkt = eth / ip / udp / payload
test_pkt2 = test_pkt.copy()
test_pkt2[UDP].chksum = scapy.utils.checksum(bytes(test_pkt2[UDP]))
await tb.driver.interfaces[0].start_xmit(test_pkt2.build(), 0, 34, 6)
pkt = await tb.port_mac[0].tx.recv()
tb.log.info("Packet: %s", pkt)
await tb.port_mac[0].rx.send(pkt)
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
assert Ether(pkt.data).build() == test_pkt.build()
tb.log.info("Multiple small packets")
count = 64
pkts = [bytearray([(x+k) % 256 for x in range(60)]) for k in range(count)]
tb.loopback_enable = True
for p in pkts:
await tb.driver.interfaces[0].start_xmit(p, 0)
for k in range(count):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.data == pkts[k]
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
tb.loopback_enable = False
tb.log.info("Multiple large packets")
count = 64
pkts = [bytearray([(x+k) % 256 for x in range(1514)]) for k in range(count)]
tb.loopback_enable = True
for p in pkts:
await tb.driver.interfaces[0].start_xmit(p, 0)
for k in range(count):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.data == pkts[k]
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
tb.loopback_enable = False
tb.log.info("Jumbo frames")
count = 64
pkts = [bytearray([(x+k) % 256 for x in range(9014)]) for k in range(count)]
tb.loopback_enable = True
for p in pkts:
await tb.driver.interfaces[0].start_xmit(p, 0)
for k in range(count):
pkt = await tb.driver.interfaces[0].recv()
tb.log.info("Packet: %s", pkt)
assert pkt.data == pkts[k]
assert pkt.rx_checksum == ~scapy.utils.checksum(bytes(pkt.data[14:])) & 0xffff
tb.loopback_enable = False
tb.log.info("Read statistics counters")
await Timer(2000, 'ns')
lst = []
for k in range(64):
lst.append(await tb.driver.hw_regs.read_dword(0x010000+k*8))
print(lst)
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
# cocotb-test
tests_dir = os.path.dirname(__file__)
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib'))
axi_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axi', 'rtl'))
axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'axis', 'rtl'))
eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl'))
pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl'))
@pytest.mark.parametrize(("axi_data_width", "axis_data_width", "axis_sync_data_width"),
[(128, 64, 64), (128, 64, 128)])
def test_mqnic_core_axi(request, axi_data_width, axis_data_width, axis_sync_data_width):
dut = "mqnic_core_axi"
module = os.path.splitext(os.path.basename(__file__))[0]
toplevel = dut
verilog_sources = [
os.path.join(rtl_dir, f"{dut}.v"),
os.path.join(rtl_dir, "mqnic_core.v"),
os.path.join(rtl_dir, "mqnic_interface.v"),
os.path.join(rtl_dir, "mqnic_port.v"),
os.path.join(rtl_dir, "mqnic_ptp.v"),
os.path.join(rtl_dir, "mqnic_ptp_clock.v"),
os.path.join(rtl_dir, "mqnic_ptp_perout.v"),
os.path.join(rtl_dir, "cpl_write.v"),
os.path.join(rtl_dir, "cpl_op_mux.v"),
os.path.join(rtl_dir, "desc_fetch.v"),
os.path.join(rtl_dir, "desc_op_mux.v"),
os.path.join(rtl_dir, "event_mux.v"),
os.path.join(rtl_dir, "queue_manager.v"),
os.path.join(rtl_dir, "cpl_queue_manager.v"),
os.path.join(rtl_dir, "tx_engine.v"),
os.path.join(rtl_dir, "rx_engine.v"),
os.path.join(rtl_dir, "tx_checksum.v"),
os.path.join(rtl_dir, "rx_hash.v"),
os.path.join(rtl_dir, "rx_checksum.v"),
os.path.join(rtl_dir, "stats_counter.v"),
os.path.join(rtl_dir, "stats_collect.v"),
os.path.join(rtl_dir, "stats_pcie_if.v"),
os.path.join(rtl_dir, "stats_pcie_tlp.v"),
os.path.join(rtl_dir, "stats_dma_if_pcie.v"),
os.path.join(rtl_dir, "stats_dma_latency.v"),
os.path.join(rtl_dir, "mqnic_tx_scheduler_block_rr.v"),
os.path.join(rtl_dir, "tx_scheduler_rr.v"),
os.path.join(eth_rtl_dir, "ptp_clock.v"),
os.path.join(eth_rtl_dir, "ptp_clock_cdc.v"),
os.path.join(eth_rtl_dir, "ptp_perout.v"),
os.path.join(eth_rtl_dir, "ptp_ts_extract.v"),
os.path.join(axi_rtl_dir, "axil_crossbar.v"),
os.path.join(axi_rtl_dir, "axil_crossbar_addr.v"),
os.path.join(axi_rtl_dir, "axil_crossbar_rd.v"),
os.path.join(axi_rtl_dir, "axil_crossbar_wr.v"),
os.path.join(axi_rtl_dir, "axil_reg_if.v"),
os.path.join(axi_rtl_dir, "axil_reg_if_rd.v"),
os.path.join(axi_rtl_dir, "axil_reg_if_wr.v"),
os.path.join(axi_rtl_dir, "axil_register_rd.v"),
os.path.join(axi_rtl_dir, "axil_register_wr.v"),
os.path.join(axi_rtl_dir, "arbiter.v"),
os.path.join(axi_rtl_dir, "priority_encoder.v"),
os.path.join(axis_rtl_dir, "axis_adapter.v"),
os.path.join(axis_rtl_dir, "axis_arb_mux.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
os.path.join(axis_rtl_dir, "axis_fifo.v"),
os.path.join(axis_rtl_dir, "axis_pipeline_fifo.v"),
os.path.join(axis_rtl_dir, "axis_register.v"),
os.path.join(pcie_rtl_dir, "dma_if_axi.v"),
os.path.join(pcie_rtl_dir, "dma_if_axi_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_axi_wr.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_rd.v"),
os.path.join(pcie_rtl_dir, "dma_if_mux_wr.v"),
os.path.join(pcie_rtl_dir, "dma_if_desc_mux.v"),
os.path.join(pcie_rtl_dir, "dma_ram_demux_rd.v"),
os.path.join(pcie_rtl_dir, "dma_ram_demux_wr.v"),
os.path.join(pcie_rtl_dir, "dma_psdpram.v"),
os.path.join(pcie_rtl_dir, "dma_client_axis_sink.v"),
os.path.join(pcie_rtl_dir, "dma_client_axis_source.v"),
os.path.join(pcie_rtl_dir, "pulse_merge.v"),
]
parameters = {}
# Structural configuration
parameters['IF_COUNT'] = 1
parameters['PORTS_PER_IF'] = 1
# PTP configuration
parameters['PTP_USE_SAMPLE_CLOCK'] = 0
parameters['PTP_PEROUT_ENABLE'] = 0
parameters['PTP_PEROUT_COUNT'] = 1
# Queue manager configuration (interface)
parameters['EVENT_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['RX_QUEUE_OP_TABLE_SIZE'] = 32
parameters['TX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['TX_QUEUE_OP_TABLE_SIZE']
parameters['RX_CPL_QUEUE_OP_TABLE_SIZE'] = parameters['RX_QUEUE_OP_TABLE_SIZE']
parameters['TX_QUEUE_INDEX_WIDTH'] = 13
parameters['RX_QUEUE_INDEX_WIDTH'] = 8
parameters['TX_CPL_QUEUE_INDEX_WIDTH'] = parameters['TX_QUEUE_INDEX_WIDTH']
parameters['RX_CPL_QUEUE_INDEX_WIDTH'] = parameters['RX_QUEUE_INDEX_WIDTH']
parameters['EVENT_QUEUE_PIPELINE'] = 3
parameters['TX_QUEUE_PIPELINE'] = 3 + max(parameters['TX_QUEUE_INDEX_WIDTH']-12, 0)
parameters['RX_QUEUE_PIPELINE'] = 3 + max(parameters['RX_QUEUE_INDEX_WIDTH']-12, 0)
parameters['TX_CPL_QUEUE_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['RX_CPL_QUEUE_PIPELINE'] = parameters['RX_QUEUE_PIPELINE']
# TX and RX engine configuration (port)
parameters['TX_DESC_TABLE_SIZE'] = 32
parameters['RX_DESC_TABLE_SIZE'] = 32
# Scheduler configuration (port)
parameters['TX_SCHEDULER_OP_TABLE_SIZE'] = parameters['TX_DESC_TABLE_SIZE']
parameters['TX_SCHEDULER_PIPELINE'] = parameters['TX_QUEUE_PIPELINE']
parameters['TDMA_INDEX_WIDTH'] = 6
# Timestamping configuration (port)
parameters['PTP_TS_ENABLE'] = 1
parameters['TX_PTP_TS_FIFO_DEPTH'] = 32
parameters['RX_PTP_TS_FIFO_DEPTH'] = 32
# Interface configuration (port)
parameters['TX_CHECKSUM_ENABLE'] = 1
parameters['RX_RSS_ENABLE'] = 1
parameters['RX_HASH_ENABLE'] = 1
parameters['RX_CHECKSUM_ENABLE'] = 1
parameters['TX_FIFO_DEPTH'] = 32768
parameters['RX_FIFO_DEPTH'] = 131072
parameters['MAX_TX_SIZE'] = 9214
parameters['MAX_RX_SIZE'] = 9214
parameters['TX_RAM_SIZE'] = 131072
parameters['RX_RAM_SIZE'] = 131072
# Application block configuration
parameters['APP_ENABLE'] = 0
parameters['APP_CTRL_ENABLE'] = 1
parameters['APP_DMA_ENABLE'] = 1
parameters['APP_AXIS_DIRECT_ENABLE'] = 1
parameters['APP_AXIS_SYNC_ENABLE'] = 1
parameters['APP_AXIS_IF_ENABLE'] = 1
parameters['APP_STAT_ENABLE'] = 1
# AXI interface configuration (DMA)
parameters['AXI_DATA_WIDTH'] = axi_data_width
parameters['AXI_ADDR_WIDTH'] = 49
parameters['AXI_STRB_WIDTH'] = parameters['AXI_DATA_WIDTH'] // 8
parameters['AXI_ID_WIDTH'] = 6
# DMA interface configuration
parameters['DMA_LEN_WIDTH'] = 16
parameters['DMA_TAG_WIDTH'] = 16
parameters['RAM_PIPELINE'] = 2
parameters['AXI_DMA_MAX_BURST_LEN'] = 16
parameters['AXI_DMA_USE_ID'] = 1
parameters['AXI_DMA_READ_OP_TABLE_SIZE'] = 2**parameters['AXI_ID_WIDTH']
parameters['AXI_DMA_WRITE_OP_TABLE_SIZE'] = 2**parameters['AXI_ID_WIDTH']
# Interrupts
parameters['IRQ_COUNT'] = 32
# AXI lite interface configuration (control)
parameters['AXIL_CTRL_DATA_WIDTH'] = 32
parameters['AXIL_CTRL_ADDR_WIDTH'] = 24
parameters['AXIL_CSR_PASSTHROUGH_ENABLE'] = 0
# AXI lite interface configuration (application control)
parameters['AXIL_APP_CTRL_DATA_WIDTH'] = parameters['AXIL_CTRL_DATA_WIDTH']
parameters['AXIL_APP_CTRL_ADDR_WIDTH'] = 24
# Ethernet interface configuration
parameters['AXIS_DATA_WIDTH'] = axis_data_width
parameters['AXIS_SYNC_DATA_WIDTH'] = axis_sync_data_width
parameters['AXIS_RX_USE_READY'] = 0
parameters['AXIS_TX_PIPELINE'] = 0
parameters['AXIS_TX_FIFO_PIPELINE'] = 2
parameters['AXIS_TX_TS_PIPELINE'] = 0
parameters['AXIS_RX_PIPELINE'] = 0
parameters['AXIS_RX_FIFO_PIPELINE'] = 2
# Statistics counter subsystem
parameters['STAT_ENABLE'] = 1
parameters['STAT_DMA_ENABLE'] = 1
parameters['STAT_PCIE_ENABLE'] = 1
parameters['STAT_INC_WIDTH'] = 24
parameters['STAT_ID_WIDTH'] = 12
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
sim_build = os.path.join(tests_dir, "sim_build",
request.node.name.replace('[', '-').replace(']', ''))
cocotb_test.simulator.run(
python_search=[tests_dir],
verilog_sources=verilog_sources,
toplevel=toplevel,
module=module,
parameters=parameters,
sim_build=sim_build,
extra_env=extra_env,
)