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fpga/mqnic/DK_DEV_1SDX_P_A: Fix MAC timing constraints for DK-DEV-1SDX-P-A

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-11-14 18:19:29 -08:00
parent 55c5ea335f
commit 614b33a205
7 changed files with 50 additions and 17 deletions
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13
fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga.sdc
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@ -92,16 +92,3 @@ set_clock_groups -asynchronous -group [ get_clocks "pcie_hip_inst|intel_pcie_pti
# PTP ref clock # PTP ref clock
set_clock_groups -asynchronous -group [ get_clocks "ref_div_inst|stratix10_clkctrl_0|clkdiv_inst|clock_div2" ] set_clock_groups -asynchronous -group [ get_clocks "ref_div_inst|stratix10_clkctrl_0|clkdiv_inst|clock_div2" ]
# E-Tile MACs
proc constrain_etile_mac { inst } {
puts "Inserting timing constraints for MAC $inst"
set_clock_groups -asynchronous -group [ get_clocks "$inst|mac_inst|alt_ehipc3_0|alt_ehipc3_hard_inst|E100GX4_FEC_PTP_PR.nphy_ptp0|alt_ehipc3_nphy_elane_ptp|tx_clkout|ch0" ]
set_clock_groups -asynchronous -group [ get_clocks "$inst|mac_inst|alt_ehipc3_0|alt_ehipc3_hard_inst|E100GX4_FEC_PTP_PR.nphy_ptp1|alt_ehipc3_nphy_elane_ptp|tx_clkout|ch0" ]
constrain_sync_reset_inst "$inst|.mac_reset_sync_inst"
}
constrain_etile_mac "qsfp1_mac_inst"
constrain_etile_mac "qsfp2_mac_inst"

3
fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_100g/Makefile
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@ -125,7 +125,8 @@ IP_TCL_FILES += ip/ref_div.tcl
QSF_FILES = fpga.qsf QSF_FILES = fpga.qsf
# SDC files # SDC files
SDC_FILES = fpga.sdc SDC_FILES += fpga.sdc
SDC_FILES += mac_100g.sdc
# Configuration # Configuration
CONFIG_TCL_FILES = ./config.tcl CONFIG_TCL_FILES = ./config.tcl

3
fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_100g_app_dma_bench/Makefile
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@ -127,7 +127,8 @@ IP_TCL_FILES += ip/ref_div.tcl
QSF_FILES = fpga.qsf QSF_FILES = fpga.qsf
# SDC files # SDC files
SDC_FILES = fpga.sdc SDC_FILES += fpga.sdc
SDC_FILES += mac_100g.sdc
# Configuration # Configuration
CONFIG_TCL_FILES = ./config.tcl CONFIG_TCL_FILES = ./config.tcl

3
fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_10g/Makefile
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@ -126,7 +126,8 @@ IP_TCL_FILES += ip/ref_div.tcl
QSF_FILES = fpga.qsf QSF_FILES = fpga.qsf
# SDC files # SDC files
SDC_FILES = fpga.sdc SDC_FILES += fpga.sdc
SDC_FILES += mac_25g.sdc
# Configuration # Configuration
CONFIG_TCL_FILES = ./config.tcl CONFIG_TCL_FILES = ./config.tcl

3
fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/fpga_25g/Makefile
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@ -126,7 +126,8 @@ IP_TCL_FILES += ip/ref_div.tcl
QSF_FILES = fpga.qsf QSF_FILES = fpga.qsf
# SDC files # SDC files
SDC_FILES = fpga.sdc SDC_FILES += fpga.sdc
SDC_FILES += mac_25g.sdc
# Configuration # Configuration
CONFIG_TCL_FILES = ./config.tcl CONFIG_TCL_FILES = ./config.tcl

12
fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/mac_100g.sdc Normal file
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@ -0,0 +1,12 @@
# E-Tile MACs
proc constrain_etile_mac { inst } {
puts "Inserting timing constraints for MAC $inst"
set_clock_groups -asynchronous -group [ get_clocks "$inst|mac_inst|alt_ehipc3_0|alt_ehipc3_hard_inst|E100GX4_FEC_PTP_PR.nphy_ptp0|alt_ehipc3_nphy_elane_ptp|tx_clkout|ch0" ]
set_clock_groups -asynchronous -group [ get_clocks "$inst|mac_inst|alt_ehipc3_0|alt_ehipc3_hard_inst|E100GX4_FEC_PTP_PR.nphy_ptp1|alt_ehipc3_nphy_elane_ptp|tx_clkout|ch0" ]
constrain_sync_reset_inst "$inst|.mac_reset_sync_inst"
}
constrain_etile_mac "qsfp1_mac_inst"
constrain_etile_mac "qsfp2_mac_inst"

30
fpga/mqnic/DK_DEV_1SDX_P_A/fpga_100g/mac_25g.sdc Normal file
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@ -0,0 +1,30 @@
# E-Tile MACs
set_clock_groups -asynchronous -group [ get_clocks "iopll_etile_ptp_inst|iopll_0_refclk" ]
set_clock_groups -asynchronous -group [ get_clocks "iopll_etile_ptp_inst|iopll_0_outclk0" ]
proc constrain_etile_mac_quad { inst } {
puts "Inserting timing constraints for MAC quad $inst"
for {set i 0} {$i < 4} {incr i} {
set_clock_groups -asynchronous -group [ get_clocks "$inst|mac_inst|alt_ehipc3_0|alt_ehipc3_hard_inst|SL_NPHY.altera_xcvr_native_inst|alt_ehipc3_nphy_elane|rx_clkout2|ch${i}" ]
set_clock_groups -asynchronous -group [ get_clocks "$inst|mac_inst|alt_ehipc3_0|alt_ehipc3_hard_inst|SL_NPHY.altera_xcvr_native_inst|alt_ehipc3_nphy_elane|rx_clkout|ch${i}" ]
set_clock_groups -asynchronous -group [ get_clocks "$inst|mac_inst|alt_ehipc3_0|alt_ehipc3_hard_inst|SL_NPHY.altera_xcvr_native_inst|alt_ehipc3_nphy_elane|tx_clkout2|ch${i}" ]
set_clock_groups -asynchronous -group [ get_clocks "$inst|mac_inst|alt_ehipc3_0|alt_ehipc3_hard_inst|SL_NPHY.altera_xcvr_native_inst|alt_ehipc3_nphy_elane|tx_clkout|ch${i}" ]
set_clock_groups -asynchronous -group [ get_clocks "$inst|mac_inst|alt_ehipc3_0|alt_ehipc3_hard_inst|SL_NPHY_RSFEC.altera_xcvr_native_inst|alt_ehipc3_nphy_elane|rx_clkout2|ch${i}" ]
set_clock_groups -asynchronous -group [ get_clocks "$inst|mac_inst|alt_ehipc3_0|alt_ehipc3_hard_inst|SL_NPHY_RSFEC.altera_xcvr_native_inst|alt_ehipc3_nphy_elane|rx_clkout|ch${i}" ]
set_clock_groups -asynchronous -group [ get_clocks "$inst|mac_inst|alt_ehipc3_0|alt_ehipc3_hard_inst|SL_NPHY_RSFEC.altera_xcvr_native_inst|alt_ehipc3_nphy_elane|tx_clkout2|ch${i}" ]
set_clock_groups -asynchronous -group [ get_clocks "$inst|mac_inst|alt_ehipc3_0|alt_ehipc3_hard_inst|SL_NPHY_RSFEC.altera_xcvr_native_inst|alt_ehipc3_nphy_elane|tx_clkout|ch${i}" ]
}
set_clock_groups -asynchronous -group [ get_clocks "$inst|mac_inst|alt_ehipc3_0|alt_ehipc3_hard_inst|SL_PTP_NPHY_CHPLL.nphy_ptp0|alt_ehipc3_nphy_elane_ptp|tx_clkout|ch0" ]
set_clock_groups -asynchronous -group [ get_clocks "$inst|mac_inst|alt_ehipc3_0|alt_ehipc3_hard_inst|SL_PTP_NPHY_CHPLL.nphy_ptp1|alt_ehipc3_nphy_elane_ptp_plloff|tx_transfer_clk|ch0" ]
for {set i 0} {$i < 4} {incr i} {
constrain_sync_reset_inst "$inst|mac_ch[$i].mac_tx_reset_sync_inst"
constrain_sync_reset_inst "$inst|mac_ch[$i].mac_tx_ptp_reset_sync_inst"
constrain_sync_reset_inst "$inst|mac_ch[$i].mac_rx_ptp_reset_sync_inst"
}
}
constrain_etile_mac_quad "qsfp1_mac_inst"
constrain_etile_mac_quad "qsfp2_mac_inst"