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Add output pipeline stage to descriptor FIFOs

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This commit is contained in:
Alex Forencich 2021-12-29 14:30:05 -08:00
parent 2091ef8c42
commit 6163efa0b8
1 changed files with 2 additions and 0 deletions
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2
fpga/common/rtl/mqnic_port.v
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@ -825,6 +825,7 @@ axis_fifo #(
.ID_WIDTH(DESC_REQ_TAG_WIDTH_INT),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.PIPELINE_OUTPUT(3),
.FRAME_FIFO(0)
)
tx_desc_fifo (
@ -1016,6 +1017,7 @@ axis_fifo #(
.ID_WIDTH(DESC_REQ_TAG_WIDTH_INT),
.DEST_ENABLE(0),
.USER_ENABLE(0),
.PIPELINE_OUTPUT(3),
.FRAME_FIFO(0)
)
rx_desc_fifo (