From 618fdff0b850d6fc3b1875aa79ca1763a9f31704 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Fri, 1 Oct 2021 15:21:10 -0700 Subject: [PATCH] Convert ADM_PCIE_9V3 to x16 --- .../{fpga_axi_x8 => fpga_axi}/Makefile | 0 .../{fpga_axi_x8 => fpga_axi}/README.md | 0 .../common/vivado.mk | 0 .../{fpga_axi_x8 => fpga_axi}/driver | 0 .../{fpga_axi_x8 => fpga_axi}/fpga.xdc | 64 +++++++++---------- .../{fpga_axi_x8 => fpga_axi}/fpga/Makefile | 0 .../ip/pcie4_uscale_plus_0.tcl | 6 +- .../{fpga_axi_x8 => fpga_axi}/lib/pcie | 0 .../{fpga_axi_x8 => fpga_axi}/rtl/axi_ram.v | 0 .../rtl/axis_register.v | 0 .../rtl/debounce_switch.v | 0 .../{fpga_axi_x8 => fpga_axi}/rtl/fpga.v | 30 ++++----- .../{fpga_axi_x8 => fpga_axi}/rtl/fpga_core.v | 10 +-- .../rtl/sync_reset.v | 0 .../rtl/sync_signal.v | 0 .../tb/fpga_core/Makefile | 2 +- .../tb/fpga_core/test_fpga_core.py | 4 +- 17 files changed, 58 insertions(+), 58 deletions(-) rename example/ADM_PCIE_9V3/{fpga_axi_x8 => fpga_axi}/Makefile (100%) rename example/ADM_PCIE_9V3/{fpga_axi_x8 => fpga_axi}/README.md (100%) rename example/ADM_PCIE_9V3/{fpga_axi_x8 => fpga_axi}/common/vivado.mk (100%) rename example/ADM_PCIE_9V3/{fpga_axi_x8 => fpga_axi}/driver (100%) rename example/ADM_PCIE_9V3/{fpga_axi_x8 => fpga_axi}/fpga.xdc (78%) rename example/ADM_PCIE_9V3/{fpga_axi_x8 => fpga_axi}/fpga/Makefile (100%) rename example/ADM_PCIE_9V3/{fpga_axi_x8 => fpga_axi}/ip/pcie4_uscale_plus_0.tcl (89%) rename example/ADM_PCIE_9V3/{fpga_axi_x8 => fpga_axi}/lib/pcie (100%) rename example/ADM_PCIE_9V3/{fpga_axi_x8 => fpga_axi}/rtl/axi_ram.v (100%) rename example/ADM_PCIE_9V3/{fpga_axi_x8 => fpga_axi}/rtl/axis_register.v (100%) rename example/ADM_PCIE_9V3/{fpga_axi_x8 => fpga_axi}/rtl/debounce_switch.v (100%) rename example/ADM_PCIE_9V3/{fpga_axi_x8 => fpga_axi}/rtl/fpga.v (95%) rename example/ADM_PCIE_9V3/{fpga_axi_x8 => fpga_axi}/rtl/fpga_core.v (99%) rename example/ADM_PCIE_9V3/{fpga_axi_x8 => fpga_axi}/rtl/sync_reset.v (100%) rename example/ADM_PCIE_9V3/{fpga_axi_x8 => fpga_axi}/rtl/sync_signal.v (100%) rename example/ADM_PCIE_9V3/{fpga_axi_x8 => fpga_axi}/tb/fpga_core/Makefile (99%) rename example/ADM_PCIE_9V3/{fpga_axi_x8 => fpga_axi}/tb/fpga_core/test_fpga_core.py (99%) diff --git a/example/ADM_PCIE_9V3/fpga_axi_x8/Makefile b/example/ADM_PCIE_9V3/fpga_axi/Makefile similarity index 100% rename from example/ADM_PCIE_9V3/fpga_axi_x8/Makefile rename to example/ADM_PCIE_9V3/fpga_axi/Makefile diff --git a/example/ADM_PCIE_9V3/fpga_axi_x8/README.md b/example/ADM_PCIE_9V3/fpga_axi/README.md similarity index 100% rename from example/ADM_PCIE_9V3/fpga_axi_x8/README.md rename to example/ADM_PCIE_9V3/fpga_axi/README.md diff --git a/example/ADM_PCIE_9V3/fpga_axi_x8/common/vivado.mk b/example/ADM_PCIE_9V3/fpga_axi/common/vivado.mk similarity index 100% rename from example/ADM_PCIE_9V3/fpga_axi_x8/common/vivado.mk rename to example/ADM_PCIE_9V3/fpga_axi/common/vivado.mk diff --git a/example/ADM_PCIE_9V3/fpga_axi_x8/driver b/example/ADM_PCIE_9V3/fpga_axi/driver similarity index 100% rename from example/ADM_PCIE_9V3/fpga_axi_x8/driver rename to example/ADM_PCIE_9V3/fpga_axi/driver diff --git a/example/ADM_PCIE_9V3/fpga_axi_x8/fpga.xdc b/example/ADM_PCIE_9V3/fpga_axi/fpga.xdc similarity index 78% rename from example/ADM_PCIE_9V3/fpga_axi_x8/fpga.xdc rename to example/ADM_PCIE_9V3/fpga_axi/fpga.xdc index d3ca56220..9810b2d08 100644 --- a/example/ADM_PCIE_9V3/fpga_axi_x8/fpga.xdc +++ b/example/ADM_PCIE_9V3/fpga_axi/fpga.xdc @@ -147,38 +147,38 @@ set_property -dict {LOC AC2 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_226 GTYE4 set_property -dict {LOC AC1 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2 set_property -dict {LOC AD5 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2 set_property -dict {LOC AD4 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2 -#set_property -dict {LOC AE2 } [get_ports {pcie_rx_p[8]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AE1 } [get_ports {pcie_rx_n[8]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AF5 } [get_ports {pcie_tx_p[8]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AF4 } [get_ports {pcie_tx_n[8]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AG2 } [get_ports {pcie_rx_p[9]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AG1 } [get_ports {pcie_rx_n[9]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AH5 } [get_ports {pcie_tx_p[9]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AH4 } [get_ports {pcie_tx_n[9]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AJ2 } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AJ1 } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AK5 } [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AK4 } [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AL2 } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AL1 } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AM5 } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AM4 } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1 -#set_property -dict {LOC AN2 } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC AN1 } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC AP5 } [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC AP4 } [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC AR2 } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC AR1 } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC AT5 } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC AT4 } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC AU2 } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC AU1 } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC AU7 } [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC AU6 } [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC AV4 } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC AV3 } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC AW7 } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0 -#set_property -dict {LOC AW6 } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0 +set_property -dict {LOC AE2 } [get_ports {pcie_rx_p[8]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1 +set_property -dict {LOC AE1 } [get_ports {pcie_rx_n[8]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1 +set_property -dict {LOC AF5 } [get_ports {pcie_tx_p[8]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1 +set_property -dict {LOC AF4 } [get_ports {pcie_tx_n[8]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1 +set_property -dict {LOC AG2 } [get_ports {pcie_rx_p[9]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1 +set_property -dict {LOC AG1 } [get_ports {pcie_rx_n[9]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1 +set_property -dict {LOC AH5 } [get_ports {pcie_tx_p[9]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1 +set_property -dict {LOC AH4 } [get_ports {pcie_tx_n[9]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1 +set_property -dict {LOC AJ2 } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1 +set_property -dict {LOC AJ1 } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1 +set_property -dict {LOC AK5 } [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1 +set_property -dict {LOC AK4 } [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1 +set_property -dict {LOC AL2 } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1 +set_property -dict {LOC AL1 } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1 +set_property -dict {LOC AM5 } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1 +set_property -dict {LOC AM4 } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1 +set_property -dict {LOC AN2 } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0 +set_property -dict {LOC AN1 } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0 +set_property -dict {LOC AP5 } [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0 +set_property -dict {LOC AP4 } [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0 +set_property -dict {LOC AR2 } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0 +set_property -dict {LOC AR1 } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0 +set_property -dict {LOC AT5 } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0 +set_property -dict {LOC AT4 } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0 +set_property -dict {LOC AU2 } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0 +set_property -dict {LOC AU1 } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0 +set_property -dict {LOC AU7 } [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0 +set_property -dict {LOC AU6 } [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0 +set_property -dict {LOC AV4 } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0 +set_property -dict {LOC AV3 } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0 +set_property -dict {LOC AW7 } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0 +set_property -dict {LOC AW6 } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0 set_property -dict {LOC AA7 } [get_ports pcie_refclk_1_p] ;# MGTREFCLK0P_226 set_property -dict {LOC AA6 } [get_ports pcie_refclk_1_n] ;# MGTREFCLK0N_226 #set_property -dict {LOC AJ7 } [get_ports pcie_refclk_2_p] ;# MGTREFCLK0P_224 diff --git a/example/ADM_PCIE_9V3/fpga_axi_x8/fpga/Makefile b/example/ADM_PCIE_9V3/fpga_axi/fpga/Makefile similarity index 100% rename from example/ADM_PCIE_9V3/fpga_axi_x8/fpga/Makefile rename to example/ADM_PCIE_9V3/fpga_axi/fpga/Makefile diff --git a/example/ADM_PCIE_9V3/fpga_axi_x8/ip/pcie4_uscale_plus_0.tcl b/example/ADM_PCIE_9V3/fpga_axi/ip/pcie4_uscale_plus_0.tcl similarity index 89% rename from example/ADM_PCIE_9V3/fpga_axi_x8/ip/pcie4_uscale_plus_0.tcl rename to example/ADM_PCIE_9V3/fpga_axi/ip/pcie4_uscale_plus_0.tcl index 8a396a22c..8a0e0451b 100644 --- a/example/ADM_PCIE_9V3/fpga_axi_x8/ip/pcie4_uscale_plus_0.tcl +++ b/example/ADM_PCIE_9V3/fpga_axi/ip/pcie4_uscale_plus_0.tcl @@ -3,10 +3,10 @@ create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pc set_property -dict [list \ CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \ - CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X8} \ - CONFIG.AXISTEN_IF_RC_STRADDLE {false} \ + CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \ + CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \ CONFIG.axisten_if_enable_client_tag {true} \ - CONFIG.axisten_if_width {256_bit} \ + CONFIG.axisten_if_width {512_bit} \ CONFIG.axisten_freq {250} \ CONFIG.PF0_CLASS_CODE {020000} \ CONFIG.PF0_DEVICE_ID {0001} \ diff --git a/example/ADM_PCIE_9V3/fpga_axi_x8/lib/pcie b/example/ADM_PCIE_9V3/fpga_axi/lib/pcie similarity index 100% rename from example/ADM_PCIE_9V3/fpga_axi_x8/lib/pcie rename to example/ADM_PCIE_9V3/fpga_axi/lib/pcie diff --git a/example/ADM_PCIE_9V3/fpga_axi_x8/rtl/axi_ram.v b/example/ADM_PCIE_9V3/fpga_axi/rtl/axi_ram.v similarity index 100% rename from example/ADM_PCIE_9V3/fpga_axi_x8/rtl/axi_ram.v rename to example/ADM_PCIE_9V3/fpga_axi/rtl/axi_ram.v diff --git a/example/ADM_PCIE_9V3/fpga_axi_x8/rtl/axis_register.v b/example/ADM_PCIE_9V3/fpga_axi/rtl/axis_register.v similarity index 100% rename from example/ADM_PCIE_9V3/fpga_axi_x8/rtl/axis_register.v rename to example/ADM_PCIE_9V3/fpga_axi/rtl/axis_register.v diff --git a/example/ADM_PCIE_9V3/fpga_axi_x8/rtl/debounce_switch.v b/example/ADM_PCIE_9V3/fpga_axi/rtl/debounce_switch.v similarity index 100% rename from example/ADM_PCIE_9V3/fpga_axi_x8/rtl/debounce_switch.v rename to example/ADM_PCIE_9V3/fpga_axi/rtl/debounce_switch.v diff --git a/example/ADM_PCIE_9V3/fpga_axi_x8/rtl/fpga.v b/example/ADM_PCIE_9V3/fpga_axi/rtl/fpga.v similarity index 95% rename from example/ADM_PCIE_9V3/fpga_axi_x8/rtl/fpga.v rename to example/ADM_PCIE_9V3/fpga_axi/rtl/fpga.v index 9f35065ca..50adc0ec4 100644 --- a/example/ADM_PCIE_9V3/fpga_axi_x8/rtl/fpga.v +++ b/example/ADM_PCIE_9V3/fpga_axi/rtl/fpga.v @@ -33,28 +33,28 @@ module fpga ( /* * GPIO */ - output wire [1:0] user_led_g, - output wire user_led_r, - output wire [1:0] front_led, + output wire [1:0] user_led_g, + output wire user_led_r, + output wire [1:0] front_led, /* * PCI express */ - input wire [7:0] pcie_rx_p, - input wire [7:0] pcie_rx_n, - output wire [7:0] pcie_tx_p, - output wire [7:0] pcie_tx_n, - input wire pcie_refclk_1_p, - input wire pcie_refclk_1_n, - input wire perst_0 + input wire [15:0] pcie_rx_p, + input wire [15:0] pcie_rx_n, + output wire [15:0] pcie_tx_p, + output wire [15:0] pcie_tx_n, + input wire pcie_refclk_1_p, + input wire pcie_refclk_1_n, + input wire perst_0 ); -parameter AXIS_PCIE_DATA_WIDTH = 256; +parameter AXIS_PCIE_DATA_WIDTH = 512; parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32); -parameter AXIS_PCIE_RC_USER_WIDTH = 75; -parameter AXIS_PCIE_RQ_USER_WIDTH = 62; -parameter AXIS_PCIE_CQ_USER_WIDTH = 88; -parameter AXIS_PCIE_CC_USER_WIDTH = 33; +parameter AXIS_PCIE_RC_USER_WIDTH = 161; +parameter AXIS_PCIE_RQ_USER_WIDTH = 137; +parameter AXIS_PCIE_CQ_USER_WIDTH = 183; +parameter AXIS_PCIE_CC_USER_WIDTH = 81; // PCIe wire pcie_user_clk; diff --git a/example/ADM_PCIE_9V3/fpga_axi_x8/rtl/fpga_core.v b/example/ADM_PCIE_9V3/fpga_axi/rtl/fpga_core.v similarity index 99% rename from example/ADM_PCIE_9V3/fpga_axi_x8/rtl/fpga_core.v rename to example/ADM_PCIE_9V3/fpga_axi/rtl/fpga_core.v index d1862f072..8e604fe18 100644 --- a/example/ADM_PCIE_9V3/fpga_axi_x8/rtl/fpga_core.v +++ b/example/ADM_PCIE_9V3/fpga_axi/rtl/fpga_core.v @@ -31,12 +31,12 @@ THE SOFTWARE. */ module fpga_core # ( - parameter AXIS_PCIE_DATA_WIDTH = 256, + parameter AXIS_PCIE_DATA_WIDTH = 512, parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32), - parameter AXIS_PCIE_RC_USER_WIDTH = 75, - parameter AXIS_PCIE_RQ_USER_WIDTH = 62, - parameter AXIS_PCIE_CQ_USER_WIDTH = 88, - parameter AXIS_PCIE_CC_USER_WIDTH = 33 + parameter AXIS_PCIE_RC_USER_WIDTH = 161, + parameter AXIS_PCIE_RQ_USER_WIDTH = 137, + parameter AXIS_PCIE_CQ_USER_WIDTH = 183, + parameter AXIS_PCIE_CC_USER_WIDTH = 81 ) ( /* diff --git a/example/ADM_PCIE_9V3/fpga_axi_x8/rtl/sync_reset.v b/example/ADM_PCIE_9V3/fpga_axi/rtl/sync_reset.v similarity index 100% rename from example/ADM_PCIE_9V3/fpga_axi_x8/rtl/sync_reset.v rename to example/ADM_PCIE_9V3/fpga_axi/rtl/sync_reset.v diff --git a/example/ADM_PCIE_9V3/fpga_axi_x8/rtl/sync_signal.v b/example/ADM_PCIE_9V3/fpga_axi/rtl/sync_signal.v similarity index 100% rename from example/ADM_PCIE_9V3/fpga_axi_x8/rtl/sync_signal.v rename to example/ADM_PCIE_9V3/fpga_axi/rtl/sync_signal.v diff --git a/example/ADM_PCIE_9V3/fpga_axi_x8/tb/fpga_core/Makefile b/example/ADM_PCIE_9V3/fpga_axi/tb/fpga_core/Makefile similarity index 99% rename from example/ADM_PCIE_9V3/fpga_axi_x8/tb/fpga_core/Makefile rename to example/ADM_PCIE_9V3/fpga_axi/tb/fpga_core/Makefile index c0f37fcea..faf89e167 100644 --- a/example/ADM_PCIE_9V3/fpga_axi_x8/tb/fpga_core/Makefile +++ b/example/ADM_PCIE_9V3/fpga_axi/tb/fpga_core/Makefile @@ -48,7 +48,7 @@ VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v # module parameters -export PARAM_AXIS_PCIE_DATA_WIDTH ?= 256 +export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512 export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 ) export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137) export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161) diff --git a/example/ADM_PCIE_9V3/fpga_axi_x8/tb/fpga_core/test_fpga_core.py b/example/ADM_PCIE_9V3/fpga_axi/tb/fpga_core/test_fpga_core.py similarity index 99% rename from example/ADM_PCIE_9V3/fpga_axi_x8/tb/fpga_core/test_fpga_core.py rename to example/ADM_PCIE_9V3/fpga_axi/tb/fpga_core/test_fpga_core.py index 2e2995e5a..f8d8ecb00 100644 --- a/example/ADM_PCIE_9V3/fpga_axi_x8/tb/fpga_core/test_fpga_core.py +++ b/example/ADM_PCIE_9V3/fpga_axi/tb/fpga_core/test_fpga_core.py @@ -50,7 +50,7 @@ class TB(object): self.dev = UltraScalePlusPcieDevice( # configuration options pcie_generation=3, - pcie_link_width=8, + pcie_link_width=16, user_clk_frequency=250e6, alignment="dword", cq_cc_straddle=False, @@ -350,7 +350,7 @@ def test_fpga_core(request): parameters = {} - parameters['AXIS_PCIE_DATA_WIDTH'] = 256 + parameters['AXIS_PCIE_DATA_WIDTH'] = 512 parameters['AXIS_PCIE_KEEP_WIDTH'] = parameters['AXIS_PCIE_DATA_WIDTH'] // 32 parameters['AXIS_PCIE_RQ_USER_WIDTH'] = 62 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 137 parameters['AXIS_PCIE_RC_USER_WIDTH'] = 75 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 161