diff --git a/example/VCU108/fpga_1g/fpga.xdc b/example/VCU108/fpga_1g/fpga.xdc
index 303ca62cd..f6df87b7e 100644
--- a/example/VCU108/fpga_1g/fpga.xdc
+++ b/example/VCU108/fpga_1g/fpga.xdc
@@ -72,6 +72,7 @@ set_property -dict {LOC AT21 IOSTANDARD LVCMOS18} [get_ports phy_int_n]
 #set_property -dict {LOC AV24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports phy_mdio]
 #set_property -dict {LOC AV21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports phy_mdc]
 
+# 625 MHz ref clock from SGMII PHY
 create_clock -period 1.600 -name phy_sgmii_clk [get_ports phy_sgmii_clk_p]
 set_clock_groups -asynchronous -group phy_sgmii_clk
 
diff --git a/example/VCU108/fpga_1g/rtl/fpga_core.v b/example/VCU108/fpga_1g/rtl/fpga_core.v
index 88a3ea82e..3b2dfdd27 100644
--- a/example/VCU108/fpga_1g/rtl/fpga_core.v
+++ b/example/VCU108/fpga_1g/rtl/fpga_core.v
@@ -29,10 +29,7 @@ THE SOFTWARE.
 /*
  * FPGA core logic
  */
-module fpga_core #
-(
-    parameter TARGET = "XILINX"
-)
+module fpga_core
 (
     /*
      * Clock: 125MHz
diff --git a/example/VCU108/fpga_1g/tb/test_fpga_core.py b/example/VCU108/fpga_1g/tb/test_fpga_core.py
index 65ad083d1..18d45cfd6 100755
--- a/example/VCU108/fpga_1g/tb/test_fpga_core.py
+++ b/example/VCU108/fpga_1g/tb/test_fpga_core.py
@@ -136,7 +136,6 @@ def dut_fpga_core(clk,
 def bench():
 
     # Parameters
-    TARGET = "SIM"
 
     # Inputs
     clk = Signal(bool(0))
diff --git a/example/VCU108/fpga_1g/tb/test_fpga_core.v b/example/VCU108/fpga_1g/tb/test_fpga_core.v
index 31ee68870..4f39a409f 100644
--- a/example/VCU108/fpga_1g/tb/test_fpga_core.v
+++ b/example/VCU108/fpga_1g/tb/test_fpga_core.v
@@ -32,7 +32,6 @@ THE SOFTWARE.
 module test_fpga_core;
 
 // Parameters
-parameter TARGET = "SIM";
 
 // Inputs
 reg clk = 0;
@@ -96,9 +95,7 @@ initial begin
     $dumpvars(0, test_fpga_core);
 end
 
-fpga_core #(
-    .TARGET(TARGET)
-)
+fpga_core
 UUT (
     .clk(clk),
     .rst(rst),