mirror of
https://github.com/corundum/corundum.git
synced 2025-01-16 08:12:53 +08:00
Add RSS support
This commit is contained in:
parent
bcd45fe9f2
commit
6270278c75
@ -94,6 +94,10 @@ module interface #
|
||||
parameter PTP_TS_WIDTH = 96,
|
||||
// Enable TX checksum offload
|
||||
parameter TX_CHECKSUM_ENABLE = 1,
|
||||
// Enable RX RSS
|
||||
parameter RX_RSS_ENABLE = 1,
|
||||
// Enable RX hashing
|
||||
parameter RX_HASH_ENABLE = 1,
|
||||
// Enable RX checksum offload
|
||||
parameter RX_CHECKSUM_ENABLE = 1,
|
||||
// Width of AXI lite data bus in bits
|
||||
@ -792,9 +796,11 @@ always @(posedge clk) begin
|
||||
16'h0000: axil_ctrl_rdata_reg <= 32'd0; // if_id
|
||||
16'h0004: begin
|
||||
// if_features
|
||||
axil_ctrl_rdata_reg[0] <= RX_RSS_ENABLE && RX_HASH_ENABLE;
|
||||
axil_ctrl_rdata_reg[4] <= PTP_TS_ENABLE;
|
||||
axil_ctrl_rdata_reg[8] <= TX_CHECKSUM_ENABLE;
|
||||
axil_ctrl_rdata_reg[9] <= RX_CHECKSUM_ENABLE;
|
||||
axil_ctrl_rdata_reg[10] <= RX_HASH_ENABLE;
|
||||
end
|
||||
16'h0010: axil_ctrl_rdata_reg <= 2**EVENT_QUEUE_INDEX_WIDTH; // event_queue_count
|
||||
16'h0014: axil_ctrl_rdata_reg <= AXIL_EQM_BASE_ADDR; // event_queue_offset
|
||||
@ -1949,6 +1955,8 @@ generate
|
||||
.PTP_TS_ENABLE(PTP_TS_ENABLE),
|
||||
.PTP_TS_WIDTH(PTP_TS_WIDTH),
|
||||
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
|
||||
.RX_RSS_ENABLE(RX_RSS_ENABLE),
|
||||
.RX_HASH_ENABLE(RX_HASH_ENABLE),
|
||||
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
|
||||
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
|
||||
.AXIL_ADDR_WIDTH(AXIL_PORT_ADDR_WIDTH),
|
||||
|
@ -88,6 +88,10 @@ module port #
|
||||
parameter PTP_TS_WIDTH = 96,
|
||||
// Enable TX checksum offload
|
||||
parameter TX_CHECKSUM_ENABLE = 1,
|
||||
// Enable RX RSS
|
||||
parameter RX_RSS_ENABLE = 1,
|
||||
// Enable RX hashing
|
||||
parameter RX_HASH_ENABLE = 1,
|
||||
// Enable RX checksum offload
|
||||
parameter RX_CHECKSUM_ENABLE = 1,
|
||||
// Width of AXI lite data bus in bits
|
||||
@ -353,7 +357,14 @@ wire [SCHED_COUNT*2-1:0] axil_sched_rresp;
|
||||
wire [SCHED_COUNT-1:0] axil_sched_rvalid;
|
||||
wire [SCHED_COUNT-1:0] axil_sched_rready;
|
||||
|
||||
// Checksumming
|
||||
// Checksumming and RSS
|
||||
wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata_int;
|
||||
wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep_int;
|
||||
wire rx_axis_tvalid_int;
|
||||
wire rx_axis_tready_int;
|
||||
wire rx_axis_tlast_int;
|
||||
wire rx_axis_tuser_int;
|
||||
|
||||
wire [AXIS_DATA_WIDTH-1:0] tx_axis_tdata_int;
|
||||
wire [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep_int;
|
||||
wire tx_axis_tvalid_int;
|
||||
@ -447,26 +458,14 @@ wire [REQ_TAG_WIDTH-1:0] tx_req_status_tag;
|
||||
wire tx_req_status_valid;
|
||||
|
||||
// RX engine
|
||||
reg rx_frame_reg = 0;
|
||||
|
||||
wire [RX_QUEUE_INDEX_WIDTH-1:0] rx_req_queue = 0; // TODO RSS of some form
|
||||
wire [REQ_TAG_WIDTH-1:0] rx_req_tag = 0;
|
||||
wire rx_req_valid = rx_axis_tvalid && !rx_frame_reg;
|
||||
wire [RX_QUEUE_INDEX_WIDTH-1:0] rx_req_queue;
|
||||
wire [REQ_TAG_WIDTH-1:0] rx_req_tag;
|
||||
wire rx_req_valid;
|
||||
wire rx_req_ready;
|
||||
|
||||
wire [REQ_TAG_WIDTH-1:0] rx_req_status_tag;
|
||||
wire rx_req_status_valid;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rx_axis_tready && rx_axis_tvalid) begin
|
||||
rx_frame_reg <= !rx_axis_tlast;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
rx_frame_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// Timestamps
|
||||
wire [95:0] rx_ptp_ts_96;
|
||||
wire rx_ptp_ts_valid;
|
||||
@ -476,6 +475,16 @@ wire [95:0] tx_ptp_ts_96;
|
||||
wire tx_ptp_ts_valid;
|
||||
wire tx_ptp_ts_ready;
|
||||
|
||||
// RX hashing
|
||||
wire [31:0] rx_hash;
|
||||
wire [3:0] rx_hash_type;
|
||||
wire rx_hash_valid;
|
||||
|
||||
wire [31:0] rx_fifo_hash;
|
||||
wire [3:0] rx_fifo_hash_type;
|
||||
wire rx_fifo_hash_valid;
|
||||
wire rx_fifo_hash_ready;
|
||||
|
||||
// Checksums
|
||||
wire [15:0] rx_csum;
|
||||
wire rx_csum_valid;
|
||||
@ -530,6 +539,8 @@ reg axil_ctrl_rvalid_reg = 1'b0;
|
||||
|
||||
reg sched_enable_reg = 1'b0;
|
||||
|
||||
reg [RX_QUEUE_INDEX_WIDTH-1:0] rss_mask_reg = 0;
|
||||
|
||||
reg tdma_enable_reg = 1'b0;
|
||||
wire tdma_locked;
|
||||
wire tdma_error;
|
||||
@ -583,6 +594,7 @@ always @(posedge clk) begin
|
||||
sched_enable_reg <= axil_ctrl_wdata[0];
|
||||
end
|
||||
end
|
||||
16'h0080: rss_mask_reg <= axil_ctrl_wdata; // RSS mask
|
||||
16'h0100: begin
|
||||
// TDMA control
|
||||
if (axil_ctrl_wstrb[0]) begin
|
||||
@ -630,9 +642,11 @@ always @(posedge clk) begin
|
||||
16'h0000: axil_ctrl_rdata_reg <= 32'd0; // port_id
|
||||
16'h0004: begin
|
||||
// port_features
|
||||
axil_ctrl_rdata_reg[0] <= RX_RSS_ENABLE && RX_HASH_ENABLE;
|
||||
axil_ctrl_rdata_reg[4] <= PTP_TS_ENABLE;
|
||||
axil_ctrl_rdata_reg[8] <= TX_CHECKSUM_ENABLE;
|
||||
axil_ctrl_rdata_reg[9] <= RX_CHECKSUM_ENABLE;
|
||||
axil_ctrl_rdata_reg[10] <= RX_HASH_ENABLE;
|
||||
end
|
||||
16'h0008: axil_ctrl_rdata_reg <= MAX_TX_SIZE; // port_mtu
|
||||
16'h0010: axil_ctrl_rdata_reg <= SCHED_COUNT; // scheduler_count
|
||||
@ -643,6 +657,7 @@ always @(posedge clk) begin
|
||||
// Scheduler enable
|
||||
axil_ctrl_rdata_reg[0] <= sched_enable_reg;
|
||||
end
|
||||
16'h0080: axil_ctrl_rdata_reg <= rss_mask_reg; // RSS mask
|
||||
16'h0100: begin
|
||||
// TDMA control
|
||||
axil_ctrl_rdata_reg[0] <= tdma_enable_reg;
|
||||
@ -676,6 +691,7 @@ always @(posedge clk) begin
|
||||
axil_ctrl_rvalid_reg <= 1'b0;
|
||||
|
||||
sched_enable_reg <= 1'b0;
|
||||
rss_mask_reg <= 0;
|
||||
tdma_enable_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
@ -1207,6 +1223,7 @@ rx_engine #(
|
||||
.AXIS_DESC_KEEP_WIDTH(AXIS_DESC_KEEP_WIDTH),
|
||||
.PKT_TABLE_SIZE(RX_PKT_TABLE_SIZE),
|
||||
.PTP_TS_ENABLE(PTP_TS_ENABLE),
|
||||
.RX_HASH_ENABLE(RX_HASH_ENABLE),
|
||||
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE)
|
||||
)
|
||||
rx_engine_inst (
|
||||
@ -1314,6 +1331,14 @@ rx_engine_inst (
|
||||
.s_axis_rx_ptp_ts_valid(s_axis_rx_ptp_ts_valid),
|
||||
.s_axis_rx_ptp_ts_ready(s_axis_rx_ptp_ts_ready),
|
||||
|
||||
/*
|
||||
* Receive hash input
|
||||
*/
|
||||
.s_axis_rx_hash(rx_fifo_hash),
|
||||
.s_axis_rx_hash_type(rx_fifo_hash_type),
|
||||
.s_axis_rx_hash_valid(rx_fifo_hash_valid),
|
||||
.s_axis_rx_hash_ready(rx_fifo_hash_ready),
|
||||
|
||||
/*
|
||||
* Receive checksum input
|
||||
*/
|
||||
@ -1329,6 +1354,196 @@ rx_engine_inst (
|
||||
|
||||
generate
|
||||
|
||||
if (RX_HASH_ENABLE) begin
|
||||
|
||||
rx_hash #(
|
||||
.DATA_WIDTH(AXIS_DATA_WIDTH)
|
||||
)
|
||||
rx_hash_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.s_axis_tdata(rx_axis_tdata),
|
||||
.s_axis_tkeep(rx_axis_tkeep),
|
||||
.s_axis_tvalid(rx_axis_tvalid & rx_axis_tready),
|
||||
.s_axis_tlast(rx_axis_tlast),
|
||||
.hash_key(320'h6d5a56da255b0ec24167253d43a38fb0d0ca2bcbae7b30b477cb2da38030f20c6a42b73bbeac01fa),
|
||||
.m_axis_hash(rx_hash),
|
||||
.m_axis_hash_type(rx_hash_type),
|
||||
.m_axis_hash_valid(rx_hash_valid)
|
||||
);
|
||||
|
||||
axis_fifo #(
|
||||
.DEPTH(32),
|
||||
.DATA_WIDTH(32+4),
|
||||
.KEEP_ENABLE(0),
|
||||
.LAST_ENABLE(0),
|
||||
.ID_ENABLE(0),
|
||||
.DEST_ENABLE(0),
|
||||
.USER_ENABLE(0),
|
||||
.FRAME_FIFO(0)
|
||||
)
|
||||
rx_hash_fifo (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
// AXI input
|
||||
.s_axis_tdata({rx_hash_type, rx_hash}),
|
||||
.s_axis_tkeep(0),
|
||||
.s_axis_tvalid(rx_hash_valid),
|
||||
.s_axis_tready(),
|
||||
.s_axis_tlast(0),
|
||||
.s_axis_tid(0),
|
||||
.s_axis_tdest(0),
|
||||
.s_axis_tuser(0),
|
||||
|
||||
// AXI output
|
||||
.m_axis_tdata({rx_fifo_hash_type, rx_fifo_hash}),
|
||||
.m_axis_tkeep(),
|
||||
.m_axis_tvalid(rx_fifo_hash_valid),
|
||||
.m_axis_tready(rx_fifo_hash_ready),
|
||||
.m_axis_tlast(),
|
||||
.m_axis_tid(),
|
||||
.m_axis_tdest(),
|
||||
.m_axis_tuser(),
|
||||
|
||||
// Status
|
||||
.status_overflow(),
|
||||
.status_bad_frame(),
|
||||
.status_good_frame()
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign rx_fifo_hash = 32'd0;
|
||||
assign rx_fifo_type = 4'd0;
|
||||
assign rx_fifo_hash_valid = 1'b0;
|
||||
|
||||
end
|
||||
|
||||
if (RX_RSS_ENABLE && RX_HASH_ENABLE) begin
|
||||
|
||||
axis_fifo #(
|
||||
.DEPTH(AXIS_KEEP_WIDTH*32),
|
||||
.DATA_WIDTH(AXIS_DATA_WIDTH),
|
||||
.KEEP_ENABLE(AXIS_KEEP_WIDTH > 1),
|
||||
.KEEP_WIDTH(AXIS_KEEP_WIDTH),
|
||||
.LAST_ENABLE(1),
|
||||
.ID_ENABLE(0),
|
||||
.DEST_ENABLE(0),
|
||||
.USER_ENABLE(1),
|
||||
.USER_WIDTH(1),
|
||||
.FRAME_FIFO(0)
|
||||
)
|
||||
rx_hash_data_fifo (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
// AXI input
|
||||
.s_axis_tdata(rx_axis_tdata),
|
||||
.s_axis_tkeep(rx_axis_tkeep),
|
||||
.s_axis_tvalid(rx_axis_tvalid),
|
||||
.s_axis_tready(rx_axis_tready),
|
||||
.s_axis_tlast(rx_axis_tlast),
|
||||
.s_axis_tid(0),
|
||||
.s_axis_tdest(0),
|
||||
.s_axis_tuser(rx_axis_tuser),
|
||||
|
||||
// AXI output
|
||||
.m_axis_tdata(rx_axis_tdata_int),
|
||||
.m_axis_tkeep(rx_axis_tkeep_int),
|
||||
.m_axis_tvalid(rx_axis_tvalid_int),
|
||||
.m_axis_tready(rx_axis_tready_int),
|
||||
.m_axis_tlast(rx_axis_tlast_int),
|
||||
.m_axis_tid(),
|
||||
.m_axis_tdest(),
|
||||
.m_axis_tuser(rx_axis_tuser_int),
|
||||
|
||||
// Status
|
||||
.status_overflow(),
|
||||
.status_bad_frame(),
|
||||
.status_good_frame()
|
||||
);
|
||||
|
||||
// Generate RX requests (RSS)
|
||||
assign rx_req_tag = 0;
|
||||
|
||||
axis_fifo #(
|
||||
.DEPTH(32),
|
||||
.DATA_WIDTH(RX_QUEUE_INDEX_WIDTH),
|
||||
.KEEP_ENABLE(0),
|
||||
.LAST_ENABLE(0),
|
||||
.ID_ENABLE(0),
|
||||
.DEST_ENABLE(0),
|
||||
.USER_ENABLE(0),
|
||||
.FRAME_FIFO(0)
|
||||
)
|
||||
rx_req_fifo (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
|
||||
// AXI input
|
||||
.s_axis_tdata(rx_hash & rss_mask_reg),
|
||||
.s_axis_tkeep(0),
|
||||
.s_axis_tvalid(rx_hash_valid),
|
||||
.s_axis_tready(),
|
||||
.s_axis_tlast(0),
|
||||
.s_axis_tid(0),
|
||||
.s_axis_tdest(0),
|
||||
.s_axis_tuser(0),
|
||||
|
||||
// AXI output
|
||||
.m_axis_tdata(rx_req_queue),
|
||||
.m_axis_tkeep(),
|
||||
.m_axis_tvalid(rx_req_valid),
|
||||
.m_axis_tready(rx_req_ready),
|
||||
.m_axis_tlast(),
|
||||
.m_axis_tid(),
|
||||
.m_axis_tdest(),
|
||||
.m_axis_tuser(),
|
||||
|
||||
// Status
|
||||
.status_overflow(),
|
||||
.status_bad_frame(),
|
||||
.status_good_frame()
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign rx_axis_tdata_int = rx_axis_tdata;
|
||||
assign rx_axis_tkeep_int = rx_axis_tkeep;
|
||||
assign rx_axis_tvalid_int = rx_axis_tvalid;
|
||||
assign rx_axis_tready = rx_axis_tready_int;
|
||||
assign rx_axis_tlast_int = rx_axis_tlast;
|
||||
assign rx_axis_tuser_int = rx_axis_tuser;
|
||||
|
||||
// Generate RX requests (no RSS)
|
||||
reg rx_frame_reg = 1'b0;
|
||||
reg rx_req_valid_reg = 1'b0;
|
||||
|
||||
assign rx_req_queue = 0;
|
||||
assign rx_req_tag = 0;
|
||||
assign rx_req_valid = rx_axis_tvalid_int && !rx_frame_reg;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rx_req_ready) begin
|
||||
rx_req_valid_reg <= 1'b0;
|
||||
end
|
||||
|
||||
if (rx_axis_tready_int && rx_axis_tvalid_int) begin
|
||||
if (!rx_frame_reg) begin
|
||||
rx_req_valid_reg <= 1'b1;
|
||||
end
|
||||
rx_frame_reg <= !rx_axis_tlast_int;
|
||||
end
|
||||
|
||||
if (rst) begin
|
||||
rx_frame_reg <= 1'b0;
|
||||
rx_req_valid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
if (RX_CHECKSUM_ENABLE) begin
|
||||
|
||||
rx_checksum #(
|
||||
@ -1337,16 +1552,16 @@ if (RX_CHECKSUM_ENABLE) begin
|
||||
rx_checksum_inst (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.s_axis_tdata(rx_axis_tdata),
|
||||
.s_axis_tkeep(rx_axis_tkeep),
|
||||
.s_axis_tvalid(rx_axis_tvalid & rx_axis_tready),
|
||||
.s_axis_tlast(rx_axis_tlast),
|
||||
.s_axis_tdata(rx_axis_tdata_int),
|
||||
.s_axis_tkeep(rx_axis_tkeep_int),
|
||||
.s_axis_tvalid(rx_axis_tvalid_int & rx_axis_tready_int),
|
||||
.s_axis_tlast(rx_axis_tlast_int),
|
||||
.m_axis_csum(rx_csum),
|
||||
.m_axis_csum_valid(rx_csum_valid)
|
||||
);
|
||||
|
||||
axis_fifo #(
|
||||
.DEPTH(16),
|
||||
.DEPTH(32),
|
||||
.DATA_WIDTH(16),
|
||||
.KEEP_ENABLE(0),
|
||||
.LAST_ENABLE(0),
|
||||
@ -1395,7 +1610,7 @@ end
|
||||
if (TX_CHECKSUM_ENABLE) begin
|
||||
|
||||
axis_fifo #(
|
||||
.DEPTH(16),
|
||||
.DEPTH(32),
|
||||
.DATA_WIDTH(1+8+8),
|
||||
.KEEP_ENABLE(0),
|
||||
.LAST_ENABLE(0),
|
||||
@ -1687,14 +1902,14 @@ dma_client_axis_sink_inst (
|
||||
/*
|
||||
* AXI stream write data input
|
||||
*/
|
||||
.s_axis_write_data_tdata(rx_axis_tdata),
|
||||
.s_axis_write_data_tkeep(rx_axis_tkeep),
|
||||
.s_axis_write_data_tvalid(rx_axis_tvalid),
|
||||
.s_axis_write_data_tready(rx_axis_tready),
|
||||
.s_axis_write_data_tlast(rx_axis_tlast),
|
||||
.s_axis_write_data_tdata(rx_axis_tdata_int),
|
||||
.s_axis_write_data_tkeep(rx_axis_tkeep_int),
|
||||
.s_axis_write_data_tvalid(rx_axis_tvalid_int),
|
||||
.s_axis_write_data_tready(rx_axis_tready_int),
|
||||
.s_axis_write_data_tlast(rx_axis_tlast_int),
|
||||
.s_axis_write_data_tid(0),
|
||||
.s_axis_write_data_tdest(0),
|
||||
.s_axis_write_data_tuser(rx_axis_tuser),
|
||||
.s_axis_write_data_tuser(rx_axis_tuser_int),
|
||||
|
||||
/*
|
||||
* RAM interface
|
||||
|
@ -82,6 +82,8 @@ module rx_engine #
|
||||
parameter AXIS_DESC_KEEP_WIDTH = AXIS_DESC_DATA_WIDTH/8,
|
||||
// Enable PTP timestamping
|
||||
parameter PTP_TS_ENABLE = 1,
|
||||
// Enable RX hashing
|
||||
parameter RX_HASH_ENABLE = 1,
|
||||
// Enable RX checksum offload
|
||||
parameter RX_CHECKSUM_ENABLE = 1
|
||||
)
|
||||
@ -191,6 +193,14 @@ module rx_engine #
|
||||
input wire s_axis_rx_ptp_ts_valid,
|
||||
output wire s_axis_rx_ptp_ts_ready,
|
||||
|
||||
/*
|
||||
* Receive hash input
|
||||
*/
|
||||
input wire [31:0] s_axis_rx_hash,
|
||||
input wire [3:0] s_axis_rx_hash_type,
|
||||
input wire s_axis_rx_hash_valid,
|
||||
output wire s_axis_rx_hash_ready,
|
||||
|
||||
/*
|
||||
* Receive checksum input
|
||||
*/
|
||||
@ -263,6 +273,8 @@ reg m_axis_rx_desc_valid_reg = 1'b0, m_axis_rx_desc_valid_next;
|
||||
|
||||
reg s_axis_rx_ptp_ts_ready_reg = 1'b0, s_axis_rx_ptp_ts_ready_next;
|
||||
|
||||
reg s_axis_rx_hash_ready_reg = 1'b0, s_axis_rx_hash_ready_next;
|
||||
|
||||
reg s_axis_rx_csum_ready_reg = 1'b0, s_axis_rx_csum_ready_next;
|
||||
|
||||
reg [DESC_TABLE_SIZE-1:0] desc_table_active = 0;
|
||||
@ -280,6 +292,8 @@ reg [DMA_CLIENT_LEN_WIDTH-1:0] desc_table_desc_len[DESC_TABLE_SIZE-1:0];
|
||||
reg [DMA_ADDR_WIDTH-1:0] desc_table_dma_addr[DESC_TABLE_SIZE-1:0];
|
||||
reg [CL_PKT_TABLE_SIZE-1:0] desc_table_pkt[DESC_TABLE_SIZE-1:0];
|
||||
reg [95:0] desc_table_ptp_ts[DESC_TABLE_SIZE-1:0];
|
||||
reg [31:0] desc_table_hash[DESC_TABLE_SIZE-1:0];
|
||||
reg [3:0] desc_table_hash_type[DESC_TABLE_SIZE-1:0];
|
||||
reg [15:0] desc_table_csum[DESC_TABLE_SIZE-1:0];
|
||||
|
||||
reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_start_ptr_reg = 0;
|
||||
@ -308,6 +322,10 @@ reg desc_table_data_written_en;
|
||||
reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_store_ptp_ts_ptr_reg = 0;
|
||||
reg [95:0] desc_table_store_ptp_ts;
|
||||
reg desc_table_store_ptp_ts_en;
|
||||
reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_store_hash_ptr_reg = 0;
|
||||
reg [31:0] desc_table_store_hash;
|
||||
reg [3:0] desc_table_store_hash_type;
|
||||
reg desc_table_store_hash_en;
|
||||
reg [CL_DESC_TABLE_SIZE+1-1:0] desc_table_store_csum_ptr_reg = 0;
|
||||
reg [15:0] desc_table_store_csum;
|
||||
reg desc_table_store_csum_en;
|
||||
@ -354,6 +372,8 @@ assign m_axis_rx_desc_valid = m_axis_rx_desc_valid_reg;
|
||||
|
||||
assign s_axis_rx_ptp_ts_ready = s_axis_rx_ptp_ts_ready_reg;
|
||||
|
||||
assign s_axis_rx_hash_ready = s_axis_rx_hash_ready_reg;
|
||||
|
||||
assign s_axis_rx_csum_ready = s_axis_rx_csum_ready_reg;
|
||||
|
||||
wire pkt_table_free_ptr_valid;
|
||||
@ -436,6 +456,8 @@ always @* begin
|
||||
|
||||
s_axis_rx_ptp_ts_ready_next = 1'b0;
|
||||
|
||||
s_axis_rx_hash_ready_next = 1'b0;
|
||||
|
||||
s_axis_rx_csum_ready_next = 1'b0;
|
||||
|
||||
desc_table_start_tag = s_axis_rx_req_tag;
|
||||
@ -460,6 +482,9 @@ always @* begin
|
||||
desc_table_data_written_en = 1'b0;
|
||||
desc_table_store_ptp_ts = s_axis_rx_ptp_ts_96;
|
||||
desc_table_store_ptp_ts_en = 1'b0;
|
||||
desc_table_store_hash = s_axis_rx_hash;
|
||||
desc_table_store_hash_type = s_axis_rx_hash_type;
|
||||
desc_table_store_hash_en = 1'b0;
|
||||
desc_table_store_csum = s_axis_rx_csum;
|
||||
desc_table_store_csum_en = 1'b0;
|
||||
desc_table_cpl_enqueue_start_en = 1'b0;
|
||||
@ -602,6 +627,24 @@ always @* begin
|
||||
end
|
||||
end
|
||||
|
||||
// store RX hash
|
||||
if (desc_table_active[desc_table_store_hash_ptr_reg & DESC_PTR_MASK] && desc_table_store_hash_ptr_reg != desc_table_start_ptr_reg && RX_HASH_ENABLE) begin
|
||||
s_axis_rx_hash_ready_next = 1'b1;
|
||||
if (desc_table_invalid[desc_table_store_hash_ptr_reg & DESC_PTR_MASK]) begin
|
||||
// invalid entry; skip
|
||||
desc_table_store_hash_en = 1'b1;
|
||||
|
||||
s_axis_rx_hash_ready_next = 1'b0;
|
||||
end else if (s_axis_rx_hash_ready && s_axis_rx_hash_valid) begin
|
||||
// update entry in descriptor table
|
||||
desc_table_store_hash = s_axis_rx_hash;
|
||||
desc_table_store_hash_type = s_axis_rx_hash_type;
|
||||
desc_table_store_hash_en = 1'b1;
|
||||
|
||||
s_axis_rx_hash_ready_next = 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
// store RX checksum
|
||||
if (desc_table_active[desc_table_store_csum_ptr_reg & DESC_PTR_MASK] && desc_table_store_csum_ptr_reg != desc_table_start_ptr_reg && RX_CHECKSUM_ENABLE) begin
|
||||
s_axis_rx_csum_ready_next = 1'b1;
|
||||
@ -620,7 +663,12 @@ always @* begin
|
||||
end
|
||||
|
||||
// finish write data; start completion enqueue
|
||||
if (desc_table_active[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] && desc_table_cpl_enqueue_start_ptr_reg != desc_table_start_ptr_reg && desc_table_cpl_enqueue_start_ptr_reg != desc_table_data_write_start_ptr_reg && (desc_table_cpl_enqueue_start_ptr_reg != desc_table_store_ptp_ts_ptr_reg || !PTP_TS_ENABLE) && (desc_table_cpl_enqueue_start_ptr_reg != desc_table_store_csum_ptr_reg || !RX_CHECKSUM_ENABLE)) begin
|
||||
if (desc_table_active[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] &&
|
||||
desc_table_cpl_enqueue_start_ptr_reg != desc_table_start_ptr_reg &&
|
||||
desc_table_cpl_enqueue_start_ptr_reg != desc_table_data_write_start_ptr_reg &&
|
||||
(desc_table_cpl_enqueue_start_ptr_reg != desc_table_store_ptp_ts_ptr_reg || !PTP_TS_ENABLE) &&
|
||||
(desc_table_cpl_enqueue_start_ptr_reg != desc_table_store_hash_ptr_reg || !RX_HASH_ENABLE) &&
|
||||
(desc_table_cpl_enqueue_start_ptr_reg != desc_table_store_csum_ptr_reg || !RX_CHECKSUM_ENABLE)) begin
|
||||
if (desc_table_invalid[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK]) begin
|
||||
// invalid entry; skip
|
||||
desc_table_cpl_enqueue_start_en = 1'b1;
|
||||
@ -648,6 +696,10 @@ always @* begin
|
||||
//m_axis_cpl_req_data_next[127:64] = desc_table_ptp_ts[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] >> 16;
|
||||
m_axis_cpl_req_data_next[111:64] = desc_table_ptp_ts[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK] >> 16;
|
||||
end
|
||||
if (RX_HASH_ENABLE) begin
|
||||
m_axis_cpl_req_data_next[159:128] = desc_table_hash[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
|
||||
m_axis_cpl_req_data_next[167:160] = desc_table_hash_type[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
|
||||
end
|
||||
if (RX_CHECKSUM_ENABLE) begin
|
||||
m_axis_cpl_req_data_next[127:112] = desc_table_csum[desc_table_cpl_enqueue_start_ptr_reg & DESC_PTR_MASK];
|
||||
end
|
||||
@ -695,6 +747,7 @@ always @(posedge clk) begin
|
||||
m_axis_dma_write_desc_valid_reg <= 1'b0;
|
||||
m_axis_rx_desc_valid_reg <= 1'b0;
|
||||
s_axis_rx_ptp_ts_ready_reg <= 1'b0;
|
||||
s_axis_rx_hash_ready_reg <= 1'b0;
|
||||
s_axis_rx_csum_ready_reg <= 1'b0;
|
||||
|
||||
desc_table_active <= 0;
|
||||
@ -707,6 +760,7 @@ always @(posedge clk) begin
|
||||
desc_table_dequeue_start_ptr_reg <= 0;
|
||||
desc_table_data_write_start_ptr_reg <= 0;
|
||||
desc_table_store_ptp_ts_ptr_reg <= 0;
|
||||
desc_table_store_hash_ptr_reg <= 0;
|
||||
desc_table_store_csum_ptr_reg <= 0;
|
||||
desc_table_cpl_enqueue_start_ptr_reg <= 0;
|
||||
desc_table_finish_ptr_reg <= 0;
|
||||
@ -721,6 +775,7 @@ always @(posedge clk) begin
|
||||
m_axis_dma_write_desc_valid_reg <= m_axis_dma_write_desc_valid_next;
|
||||
m_axis_rx_desc_valid_reg <= m_axis_rx_desc_valid_next;
|
||||
s_axis_rx_ptp_ts_ready_reg <= s_axis_rx_ptp_ts_ready_next;
|
||||
s_axis_rx_hash_ready_reg <= s_axis_rx_hash_ready_next;
|
||||
s_axis_rx_csum_ready_reg <= s_axis_rx_csum_ready_next;
|
||||
|
||||
if (desc_table_start_en) begin
|
||||
@ -755,6 +810,9 @@ always @(posedge clk) begin
|
||||
if (desc_table_store_ptp_ts_en) begin
|
||||
desc_table_store_ptp_ts_ptr_reg <= desc_table_store_ptp_ts_ptr_reg + 1;
|
||||
end
|
||||
if (desc_table_store_hash_en) begin
|
||||
desc_table_store_hash_ptr_reg <= desc_table_store_hash_ptr_reg + 1;
|
||||
end
|
||||
if (desc_table_store_csum_en) begin
|
||||
desc_table_store_csum_ptr_reg <= desc_table_store_csum_ptr_reg + 1;
|
||||
end
|
||||
@ -815,6 +873,10 @@ always @(posedge clk) begin
|
||||
if (desc_table_store_ptp_ts_en) begin
|
||||
desc_table_ptp_ts[desc_table_store_ptp_ts_ptr_reg & DESC_PTR_MASK] <= desc_table_store_ptp_ts;
|
||||
end
|
||||
if (desc_table_store_hash_en) begin
|
||||
desc_table_hash[desc_table_store_hash_ptr_reg & DESC_PTR_MASK] <= desc_table_store_hash;
|
||||
desc_table_hash_type[desc_table_store_hash_ptr_reg & DESC_PTR_MASK] <= desc_table_store_hash_type;
|
||||
end
|
||||
if (desc_table_store_csum_en) begin
|
||||
desc_table_csum[desc_table_store_csum_ptr_reg & DESC_PTR_MASK] <= desc_table_store_csum;
|
||||
end
|
||||
|
@ -26,6 +26,7 @@ SYN_FILES += rtl/common/tdma_ber_ch.v
|
||||
SYN_FILES += rtl/common/tx_engine.v
|
||||
SYN_FILES += rtl/common/rx_engine.v
|
||||
SYN_FILES += rtl/common/tx_checksum.v
|
||||
SYN_FILES += rtl/common/rx_hash.v
|
||||
SYN_FILES += rtl/common/rx_checksum.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
|
||||
|
@ -324,6 +324,8 @@ parameter RX_PTP_TS_FIFO_DEPTH = 32;
|
||||
|
||||
// Interface parameters (port)
|
||||
parameter TX_CHECKSUM_ENABLE = 1;
|
||||
parameter RX_RSS_ENABLE = 1;
|
||||
parameter RX_HASH_ENABLE = 1;
|
||||
parameter RX_CHECKSUM_ENABLE = 1;
|
||||
parameter ENABLE_PADDING = 1;
|
||||
parameter ENABLE_DIC = 1;
|
||||
@ -1823,6 +1825,8 @@ generate
|
||||
.PTP_TS_ENABLE(PTP_TS_ENABLE),
|
||||
.PTP_TS_WIDTH(PTP_TS_WIDTH),
|
||||
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
|
||||
.RX_RSS_ENABLE(RX_RSS_ENABLE),
|
||||
.RX_HASH_ENABLE(RX_HASH_ENABLE),
|
||||
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
|
||||
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
|
||||
.AXIL_ADDR_WIDTH(IF_AXIL_ADDR_WIDTH),
|
||||
|
@ -63,6 +63,7 @@ srcs.append("../rtl/common/cpl_queue_manager.v")
|
||||
srcs.append("../rtl/common/tx_engine.v")
|
||||
srcs.append("../rtl/common/rx_engine.v")
|
||||
srcs.append("../rtl/common/tx_checksum.v")
|
||||
srcs.append("../rtl/common/rx_hash.v")
|
||||
srcs.append("../rtl/common/rx_checksum.v")
|
||||
srcs.append("../rtl/common/tx_scheduler_rr.v")
|
||||
srcs.append("../rtl/common/event_mux.v")
|
||||
|
@ -26,6 +26,7 @@ SYN_FILES += rtl/common/tdma_ber_ch.v
|
||||
SYN_FILES += rtl/common/tx_engine.v
|
||||
SYN_FILES += rtl/common/rx_engine.v
|
||||
SYN_FILES += rtl/common/tx_checksum.v
|
||||
SYN_FILES += rtl/common/rx_hash.v
|
||||
SYN_FILES += rtl/common/rx_checksum.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
|
||||
|
@ -324,6 +324,8 @@ parameter RX_PTP_TS_FIFO_DEPTH = 32;
|
||||
|
||||
// Interface parameters (port)
|
||||
parameter TX_CHECKSUM_ENABLE = 1;
|
||||
parameter RX_RSS_ENABLE = 1;
|
||||
parameter RX_HASH_ENABLE = 1;
|
||||
parameter RX_CHECKSUM_ENABLE = 1;
|
||||
parameter ENABLE_PADDING = 1;
|
||||
parameter ENABLE_DIC = 1;
|
||||
@ -1823,6 +1825,8 @@ generate
|
||||
.PTP_TS_ENABLE(PTP_TS_ENABLE),
|
||||
.PTP_TS_WIDTH(PTP_TS_WIDTH),
|
||||
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
|
||||
.RX_RSS_ENABLE(RX_RSS_ENABLE),
|
||||
.RX_HASH_ENABLE(RX_HASH_ENABLE),
|
||||
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
|
||||
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
|
||||
.AXIL_ADDR_WIDTH(IF_AXIL_ADDR_WIDTH),
|
||||
|
@ -63,6 +63,7 @@ srcs.append("../rtl/common/cpl_queue_manager.v")
|
||||
srcs.append("../rtl/common/tx_engine.v")
|
||||
srcs.append("../rtl/common/rx_engine.v")
|
||||
srcs.append("../rtl/common/tx_checksum.v")
|
||||
srcs.append("../rtl/common/rx_hash.v")
|
||||
srcs.append("../rtl/common/rx_checksum.v")
|
||||
srcs.append("../rtl/common/tx_scheduler_rr.v")
|
||||
srcs.append("../rtl/common/event_mux.v")
|
||||
|
@ -24,6 +24,7 @@ SYN_FILES += rtl/common/tdma_scheduler.v
|
||||
SYN_FILES += rtl/common/tx_engine.v
|
||||
SYN_FILES += rtl/common/rx_engine.v
|
||||
SYN_FILES += rtl/common/tx_checksum.v
|
||||
SYN_FILES += rtl/common/rx_hash.v
|
||||
SYN_FILES += rtl/common/rx_checksum.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
|
||||
|
@ -247,6 +247,8 @@ parameter RX_PTP_TS_FIFO_DEPTH = 32;
|
||||
|
||||
// Interface parameters (port)
|
||||
parameter TX_CHECKSUM_ENABLE = 1;
|
||||
parameter RX_RSS_ENABLE = 1;
|
||||
parameter RX_HASH_ENABLE = 1;
|
||||
parameter RX_CHECKSUM_ENABLE = 1;
|
||||
parameter ENABLE_PADDING = 1;
|
||||
parameter ENABLE_DIC = 1;
|
||||
@ -1554,6 +1556,8 @@ generate
|
||||
.PTP_TS_ENABLE(PTP_TS_ENABLE),
|
||||
.PTP_TS_WIDTH(PTP_TS_WIDTH),
|
||||
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
|
||||
.RX_RSS_ENABLE(RX_RSS_ENABLE),
|
||||
.RX_HASH_ENABLE(RX_HASH_ENABLE),
|
||||
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
|
||||
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
|
||||
.AXIL_ADDR_WIDTH(IF_AXIL_ADDR_WIDTH),
|
||||
|
@ -63,6 +63,7 @@ srcs.append("../rtl/common/cpl_queue_manager.v")
|
||||
srcs.append("../rtl/common/tx_engine.v")
|
||||
srcs.append("../rtl/common/rx_engine.v")
|
||||
srcs.append("../rtl/common/tx_checksum.v")
|
||||
srcs.append("../rtl/common/rx_hash.v")
|
||||
srcs.append("../rtl/common/rx_checksum.v")
|
||||
srcs.append("../rtl/common/tx_scheduler_rr.v")
|
||||
srcs.append("../rtl/common/tdma_scheduler.v")
|
||||
|
@ -26,6 +26,7 @@ SYN_FILES += rtl/common/tdma_ber_ch.v
|
||||
SYN_FILES += rtl/common/tx_engine.v
|
||||
SYN_FILES += rtl/common/rx_engine.v
|
||||
SYN_FILES += rtl/common/tx_checksum.v
|
||||
SYN_FILES += rtl/common/rx_hash.v
|
||||
SYN_FILES += rtl/common/rx_checksum.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
|
||||
|
@ -249,6 +249,8 @@ parameter RX_PTP_TS_FIFO_DEPTH = 32;
|
||||
|
||||
// Interface parameters (port)
|
||||
parameter TX_CHECKSUM_ENABLE = 1;
|
||||
parameter RX_RSS_ENABLE = 1;
|
||||
parameter RX_HASH_ENABLE = 1;
|
||||
parameter RX_CHECKSUM_ENABLE = 1;
|
||||
parameter ENABLE_PADDING = 1;
|
||||
parameter ENABLE_DIC = 1;
|
||||
@ -1554,6 +1556,8 @@ generate
|
||||
.PTP_TS_ENABLE(PTP_TS_ENABLE),
|
||||
.PTP_TS_WIDTH(PTP_TS_WIDTH),
|
||||
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
|
||||
.RX_RSS_ENABLE(RX_RSS_ENABLE),
|
||||
.RX_HASH_ENABLE(RX_HASH_ENABLE),
|
||||
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
|
||||
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
|
||||
.AXIL_ADDR_WIDTH(IF_AXIL_ADDR_WIDTH),
|
||||
|
@ -63,6 +63,7 @@ srcs.append("../rtl/common/cpl_queue_manager.v")
|
||||
srcs.append("../rtl/common/tx_engine.v")
|
||||
srcs.append("../rtl/common/rx_engine.v")
|
||||
srcs.append("../rtl/common/tx_checksum.v")
|
||||
srcs.append("../rtl/common/rx_hash.v")
|
||||
srcs.append("../rtl/common/rx_checksum.v")
|
||||
srcs.append("../rtl/common/tx_scheduler_rr.v")
|
||||
srcs.append("../rtl/common/tdma_scheduler.v")
|
||||
|
@ -26,6 +26,7 @@ SYN_FILES += rtl/common/tdma_ber_ch.v
|
||||
SYN_FILES += rtl/common/tx_engine.v
|
||||
SYN_FILES += rtl/common/rx_engine.v
|
||||
SYN_FILES += rtl/common/tx_checksum.v
|
||||
SYN_FILES += rtl/common/rx_hash.v
|
||||
SYN_FILES += rtl/common/rx_checksum.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
|
||||
|
@ -275,6 +275,8 @@ parameter RX_PTP_TS_FIFO_DEPTH = 32;
|
||||
|
||||
// Interface parameters (port)
|
||||
parameter TX_CHECKSUM_ENABLE = 1;
|
||||
parameter RX_RSS_ENABLE = 1;
|
||||
parameter RX_HASH_ENABLE = 1;
|
||||
parameter RX_CHECKSUM_ENABLE = 1;
|
||||
parameter ENABLE_PADDING = 1;
|
||||
parameter ENABLE_DIC = 1;
|
||||
@ -1700,6 +1702,8 @@ generate
|
||||
.PTP_TS_ENABLE(PTP_TS_ENABLE),
|
||||
.PTP_TS_WIDTH(PTP_TS_WIDTH),
|
||||
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
|
||||
.RX_RSS_ENABLE(RX_RSS_ENABLE),
|
||||
.RX_HASH_ENABLE(RX_HASH_ENABLE),
|
||||
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
|
||||
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
|
||||
.AXIL_ADDR_WIDTH(IF_AXIL_ADDR_WIDTH),
|
||||
|
@ -63,6 +63,7 @@ srcs.append("../rtl/common/cpl_queue_manager.v")
|
||||
srcs.append("../rtl/common/tx_engine.v")
|
||||
srcs.append("../rtl/common/rx_engine.v")
|
||||
srcs.append("../rtl/common/tx_checksum.v")
|
||||
srcs.append("../rtl/common/rx_hash.v")
|
||||
srcs.append("../rtl/common/rx_checksum.v")
|
||||
srcs.append("../rtl/common/tx_scheduler_rr.v")
|
||||
srcs.append("../rtl/common/tdma_scheduler.v")
|
||||
|
@ -26,6 +26,7 @@ SYN_FILES += rtl/common/tdma_ber_ch.v
|
||||
SYN_FILES += rtl/common/tx_engine.v
|
||||
SYN_FILES += rtl/common/rx_engine.v
|
||||
SYN_FILES += rtl/common/tx_checksum.v
|
||||
SYN_FILES += rtl/common/rx_hash.v
|
||||
SYN_FILES += rtl/common/rx_checksum.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
|
||||
|
@ -314,6 +314,8 @@ parameter RX_PTP_TS_FIFO_DEPTH = 32;
|
||||
|
||||
// Interface parameters (port)
|
||||
parameter TX_CHECKSUM_ENABLE = 1;
|
||||
parameter RX_RSS_ENABLE = 1;
|
||||
parameter RX_HASH_ENABLE = 1;
|
||||
parameter RX_CHECKSUM_ENABLE = 1;
|
||||
parameter ENABLE_PADDING = 1;
|
||||
parameter ENABLE_DIC = 1;
|
||||
@ -1768,6 +1770,8 @@ generate
|
||||
.PTP_TS_ENABLE(PTP_TS_ENABLE),
|
||||
.PTP_TS_WIDTH(PTP_TS_WIDTH),
|
||||
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
|
||||
.RX_RSS_ENABLE(RX_RSS_ENABLE),
|
||||
.RX_HASH_ENABLE(RX_HASH_ENABLE),
|
||||
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
|
||||
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
|
||||
.AXIL_ADDR_WIDTH(IF_AXIL_ADDR_WIDTH),
|
||||
|
@ -63,6 +63,7 @@ srcs.append("../rtl/common/cpl_queue_manager.v")
|
||||
srcs.append("../rtl/common/tx_engine.v")
|
||||
srcs.append("../rtl/common/rx_engine.v")
|
||||
srcs.append("../rtl/common/tx_checksum.v")
|
||||
srcs.append("../rtl/common/rx_hash.v")
|
||||
srcs.append("../rtl/common/rx_checksum.v")
|
||||
srcs.append("../rtl/common/tx_scheduler_rr.v")
|
||||
srcs.append("../rtl/common/event_mux.v")
|
||||
|
@ -27,6 +27,7 @@ SYN_FILES += rtl/common/tdma_ber_ch.v
|
||||
SYN_FILES += rtl/common/tx_engine.v
|
||||
SYN_FILES += rtl/common/rx_engine.v
|
||||
SYN_FILES += rtl/common/tx_checksum.v
|
||||
SYN_FILES += rtl/common/rx_hash.v
|
||||
SYN_FILES += rtl/common/rx_checksum.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
|
||||
|
@ -324,6 +324,8 @@ parameter RX_PTP_TS_FIFO_DEPTH = 32;
|
||||
|
||||
// Interface parameters (port)
|
||||
parameter TX_CHECKSUM_ENABLE = 1;
|
||||
parameter RX_RSS_ENABLE = 1;
|
||||
parameter RX_HASH_ENABLE = 1;
|
||||
parameter RX_CHECKSUM_ENABLE = 1;
|
||||
parameter ENABLE_PADDING = 1;
|
||||
parameter ENABLE_DIC = 1;
|
||||
@ -1823,6 +1825,8 @@ generate
|
||||
.PTP_TS_ENABLE(PTP_TS_ENABLE),
|
||||
.PTP_TS_WIDTH(PTP_TS_WIDTH),
|
||||
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
|
||||
.RX_RSS_ENABLE(RX_RSS_ENABLE),
|
||||
.RX_HASH_ENABLE(RX_HASH_ENABLE),
|
||||
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
|
||||
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
|
||||
.AXIL_ADDR_WIDTH(IF_AXIL_ADDR_WIDTH),
|
||||
|
@ -63,6 +63,7 @@ srcs.append("../rtl/common/cpl_queue_manager.v")
|
||||
srcs.append("../rtl/common/tx_engine.v")
|
||||
srcs.append("../rtl/common/rx_engine.v")
|
||||
srcs.append("../rtl/common/tx_checksum.v")
|
||||
srcs.append("../rtl/common/rx_hash.v")
|
||||
srcs.append("../rtl/common/rx_checksum.v")
|
||||
srcs.append("../rtl/common/tx_scheduler_rr.v")
|
||||
srcs.append("../rtl/common/tx_scheduler_ctrl_tdma.v")
|
||||
|
@ -25,6 +25,7 @@ SYN_FILES += rtl/common/tdma_scheduler.v
|
||||
SYN_FILES += rtl/common/tx_engine.v
|
||||
SYN_FILES += rtl/common/rx_engine.v
|
||||
SYN_FILES += rtl/common/tx_checksum.v
|
||||
SYN_FILES += rtl/common/rx_hash.v
|
||||
SYN_FILES += rtl/common/rx_checksum.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
|
||||
|
@ -247,6 +247,8 @@ parameter RX_PTP_TS_FIFO_DEPTH = 32;
|
||||
|
||||
// Interface parameters (port)
|
||||
parameter TX_CHECKSUM_ENABLE = 1;
|
||||
parameter RX_RSS_ENABLE = 1;
|
||||
parameter RX_HASH_ENABLE = 1;
|
||||
parameter RX_CHECKSUM_ENABLE = 1;
|
||||
parameter ENABLE_PADDING = 1;
|
||||
parameter ENABLE_DIC = 1;
|
||||
@ -1554,6 +1556,8 @@ generate
|
||||
.PTP_TS_ENABLE(PTP_TS_ENABLE),
|
||||
.PTP_TS_WIDTH(PTP_TS_WIDTH),
|
||||
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
|
||||
.RX_RSS_ENABLE(RX_RSS_ENABLE),
|
||||
.RX_HASH_ENABLE(RX_HASH_ENABLE),
|
||||
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
|
||||
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
|
||||
.AXIL_ADDR_WIDTH(IF_AXIL_ADDR_WIDTH),
|
||||
|
@ -63,6 +63,7 @@ srcs.append("../rtl/common/cpl_queue_manager.v")
|
||||
srcs.append("../rtl/common/tx_engine.v")
|
||||
srcs.append("../rtl/common/rx_engine.v")
|
||||
srcs.append("../rtl/common/tx_checksum.v")
|
||||
srcs.append("../rtl/common/rx_hash.v")
|
||||
srcs.append("../rtl/common/rx_checksum.v")
|
||||
srcs.append("../rtl/common/tx_scheduler_rr.v")
|
||||
srcs.append("../rtl/common/tx_scheduler_ctrl_tdma.v")
|
||||
|
@ -27,6 +27,7 @@ SYN_FILES += rtl/common/tdma_ber_ch.v
|
||||
SYN_FILES += rtl/common/tx_engine.v
|
||||
SYN_FILES += rtl/common/rx_engine.v
|
||||
SYN_FILES += rtl/common/tx_checksum.v
|
||||
SYN_FILES += rtl/common/rx_hash.v
|
||||
SYN_FILES += rtl/common/rx_checksum.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
|
||||
|
@ -275,6 +275,8 @@ parameter RX_PTP_TS_FIFO_DEPTH = 32;
|
||||
|
||||
// Interface parameters (port)
|
||||
parameter TX_CHECKSUM_ENABLE = 1;
|
||||
parameter RX_RSS_ENABLE = 1;
|
||||
parameter RX_HASH_ENABLE = 1;
|
||||
parameter RX_CHECKSUM_ENABLE = 1;
|
||||
parameter ENABLE_PADDING = 1;
|
||||
parameter ENABLE_DIC = 1;
|
||||
@ -1700,6 +1702,8 @@ generate
|
||||
.PTP_TS_ENABLE(PTP_TS_ENABLE),
|
||||
.PTP_TS_WIDTH(PTP_TS_WIDTH),
|
||||
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
|
||||
.RX_RSS_ENABLE(RX_RSS_ENABLE),
|
||||
.RX_HASH_ENABLE(RX_HASH_ENABLE),
|
||||
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
|
||||
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
|
||||
.AXIL_ADDR_WIDTH(IF_AXIL_ADDR_WIDTH),
|
||||
|
@ -63,6 +63,7 @@ srcs.append("../rtl/common/cpl_queue_manager.v")
|
||||
srcs.append("../rtl/common/tx_engine.v")
|
||||
srcs.append("../rtl/common/rx_engine.v")
|
||||
srcs.append("../rtl/common/tx_checksum.v")
|
||||
srcs.append("../rtl/common/rx_hash.v")
|
||||
srcs.append("../rtl/common/rx_checksum.v")
|
||||
srcs.append("../rtl/common/tx_scheduler_rr.v")
|
||||
srcs.append("../rtl/common/tx_scheduler_ctrl_tdma.v")
|
||||
|
@ -27,6 +27,7 @@ SYN_FILES += rtl/common/tdma_ber_ch.v
|
||||
SYN_FILES += rtl/common/tx_engine.v
|
||||
SYN_FILES += rtl/common/rx_engine.v
|
||||
SYN_FILES += rtl/common/tx_checksum.v
|
||||
SYN_FILES += rtl/common/rx_hash.v
|
||||
SYN_FILES += rtl/common/rx_checksum.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
|
||||
|
@ -314,6 +314,8 @@ parameter RX_PTP_TS_FIFO_DEPTH = 32;
|
||||
|
||||
// Interface parameters (port)
|
||||
parameter TX_CHECKSUM_ENABLE = 1;
|
||||
parameter RX_RSS_ENABLE = 1;
|
||||
parameter RX_HASH_ENABLE = 1;
|
||||
parameter RX_CHECKSUM_ENABLE = 1;
|
||||
parameter ENABLE_PADDING = 1;
|
||||
parameter ENABLE_DIC = 1;
|
||||
@ -1768,6 +1770,8 @@ generate
|
||||
.PTP_TS_ENABLE(PTP_TS_ENABLE),
|
||||
.PTP_TS_WIDTH(PTP_TS_WIDTH),
|
||||
.TX_CHECKSUM_ENABLE(TX_CHECKSUM_ENABLE),
|
||||
.RX_RSS_ENABLE(RX_RSS_ENABLE),
|
||||
.RX_HASH_ENABLE(RX_HASH_ENABLE),
|
||||
.RX_CHECKSUM_ENABLE(RX_CHECKSUM_ENABLE),
|
||||
.AXIL_DATA_WIDTH(AXIL_DATA_WIDTH),
|
||||
.AXIL_ADDR_WIDTH(IF_AXIL_ADDR_WIDTH),
|
||||
|
@ -63,6 +63,7 @@ srcs.append("../rtl/common/cpl_queue_manager.v")
|
||||
srcs.append("../rtl/common/tx_engine.v")
|
||||
srcs.append("../rtl/common/rx_engine.v")
|
||||
srcs.append("../rtl/common/tx_checksum.v")
|
||||
srcs.append("../rtl/common/rx_hash.v")
|
||||
srcs.append("../rtl/common/rx_checksum.v")
|
||||
srcs.append("../rtl/common/tx_scheduler_rr.v")
|
||||
srcs.append("../rtl/common/tx_scheduler_ctrl_tdma.v")
|
||||
|
@ -292,6 +292,8 @@ int mqnic_create_port(struct mqnic_priv *priv, struct mqnic_port **port_ptr, int
|
||||
void mqnic_destroy_port(struct mqnic_priv *priv, struct mqnic_port **port_ptr);
|
||||
int mqnic_activate_port(struct mqnic_port *port);
|
||||
void mqnic_deactivate_port(struct mqnic_port *port);
|
||||
u32 mqnic_port_get_rss_mask(struct mqnic_port *port);
|
||||
void mqnic_port_set_rss_mask(struct mqnic_port *port, u32 rss_mask);
|
||||
|
||||
// mqnic_ptp.c
|
||||
void mqnic_register_phc(struct mqnic_dev *mdev);
|
||||
|
@ -130,6 +130,7 @@ either expressed or implied, of The Regents of the University of California.
|
||||
#define MQNIC_IF_FEATURE_PTP_TS (1 << 4)
|
||||
#define MQNIC_IF_FEATURE_TX_CSUM (1 << 8)
|
||||
#define MQNIC_IF_FEATURE_RX_CSUM (1 << 9)
|
||||
#define MQNIC_IF_FEATURE_RX_HASH (1 << 10)
|
||||
|
||||
// Port CSRs
|
||||
#define MQNIC_PORT_REG_PORT_ID 0x0000
|
||||
@ -141,6 +142,9 @@ either expressed or implied, of The Regents of the University of California.
|
||||
#define MQNIC_PORT_REG_SCHED_STRIDE 0x0018
|
||||
#define MQNIC_PORT_REG_SCHED_TYPE 0x001C
|
||||
#define MQNIC_PORT_REG_SCHED_ENABLE 0x0040
|
||||
|
||||
#define MQNIC_PORT_REG_RSS_MASK 0x0080
|
||||
|
||||
#define MQNIC_PORT_REG_TDMA_CTRL 0x0100
|
||||
#define MQNIC_PORT_REG_TDMA_STATUS 0x0104
|
||||
#define MQNIC_PORT_REG_TDMA_TIMESLOT_COUNT 0x0108
|
||||
@ -165,6 +169,7 @@ either expressed or implied, of The Regents of the University of California.
|
||||
#define MQNIC_PORT_FEATURE_PTP_TS (1 << 4)
|
||||
#define MQNIC_PORT_FEATURE_TX_CSUM (1 << 8)
|
||||
#define MQNIC_PORT_FEATURE_RX_CSUM (1 << 9)
|
||||
#define MQNIC_PORT_FEATURE_RX_HASH (1 << 10)
|
||||
|
||||
#define MQNIC_QUEUE_STRIDE 0x00000020
|
||||
#define MQNIC_CPL_QUEUE_STRIDE 0x00000020
|
||||
@ -222,6 +227,13 @@ struct mqnic_cpl {
|
||||
__u32 ts_ns;
|
||||
__u16 ts_s;
|
||||
__u16 rx_csum;
|
||||
__u32 rx_hash;
|
||||
__u8 rx_hash_type;
|
||||
__u8 rsvd1;
|
||||
__u8 rsvd2;
|
||||
__u8 rsvd3;
|
||||
__u32 rsvd4;
|
||||
__u32 rsvd5;
|
||||
};
|
||||
|
||||
struct mqnic_event {
|
||||
|
@ -542,6 +542,8 @@ int mqnic_init_netdev(struct mqnic_dev *mdev, int port, u8 __iomem *hw_addr)
|
||||
{
|
||||
goto fail;
|
||||
}
|
||||
|
||||
mqnic_port_set_rss_mask(priv->ports[k], 0xffffffff);
|
||||
}
|
||||
|
||||
// entry points
|
||||
|
@ -110,3 +110,13 @@ void mqnic_deactivate_port(struct mqnic_port *port)
|
||||
iowrite32(0, port->hw_addr+MQNIC_PORT_REG_SCHED_ENABLE);
|
||||
}
|
||||
|
||||
u32 mqnic_port_get_rss_mask(struct mqnic_port *port)
|
||||
{
|
||||
return ioread32(port->hw_addr+MQNIC_PORT_REG_RSS_MASK);
|
||||
}
|
||||
|
||||
void mqnic_port_set_rss_mask(struct mqnic_port *port, u32 rss_mask)
|
||||
{
|
||||
iowrite32(rss_mask, port->hw_addr+MQNIC_PORT_REG_RSS_MASK);
|
||||
}
|
||||
|
||||
|
Loading…
x
Reference in New Issue
Block a user