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Adjust clock connections to improve connection to testbench

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This commit is contained in:
Alex Forencich 2021-11-30 00:16:47 -08:00
parent 8f887005e5
commit 639117e53f
5 changed files with 61 additions and 46 deletions
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43
fpga/common/rtl/mqnic_core.v
View File

@ -1939,8 +1939,8 @@ always @* begin
end
// streaming connections to application
wire [PORT_COUNT-1:0] app_direct_tx_clk = tx_clk;
wire [PORT_COUNT-1:0] app_direct_tx_rst = tx_rst;
wire [PORT_COUNT-1:0] app_direct_tx_clk;
wire [PORT_COUNT-1:0] app_direct_tx_rst;
wire [PORT_COUNT*AXIS_DATA_WIDTH-1:0] app_s_axis_direct_tx_tdata;
wire [PORT_COUNT*AXIS_KEEP_WIDTH-1:0] app_s_axis_direct_tx_tkeep;
@ -1966,8 +1966,8 @@ wire [PORT_COUNT*PTP_TAG_WIDTH-1:0] app_m_axis_direct_tx_ptp_ts_tag;
wire [PORT_COUNT-1:0] app_m_axis_direct_tx_ptp_ts_valid;
wire [PORT_COUNT-1:0] app_m_axis_direct_tx_ptp_ts_ready;
wire [PORT_COUNT-1:0] app_direct_rx_clk = rx_clk;
wire [PORT_COUNT-1:0] app_direct_rx_rst = rx_rst;
wire [PORT_COUNT-1:0] app_direct_rx_clk;
wire [PORT_COUNT-1:0] app_direct_rx_rst;
wire [PORT_COUNT*AXIS_DATA_WIDTH-1:0] app_s_axis_direct_rx_tdata;
wire [PORT_COUNT*AXIS_KEEP_WIDTH-1:0] app_s_axis_direct_rx_tkeep;
@ -2346,6 +2346,21 @@ generate
for (m = 0; m < PORTS_PER_IF; m = m + 1) begin : port
wire port_tx_clk = tx_clk[n*PORTS_PER_IF+m];
wire port_tx_rst = tx_rst[n*PORTS_PER_IF+m];
wire port_rx_clk = tx_clk[n*PORTS_PER_IF+m];
wire port_rx_rst = tx_rst[n*PORTS_PER_IF+m];
wire port_rx_ptp_clk = PTP_SEPARATE_RX_CLOCK ? rx_ptp_clk[n*PORTS_PER_IF+m] : rx_clk[n*PORTS_PER_IF+m];
wire port_rx_ptp_rst = PTP_SEPARATE_RX_CLOCK ? rx_ptp_rst[n*PORTS_PER_IF+m] : rx_rst[n*PORTS_PER_IF+m];
assign app_direct_tx_clk[n*PORTS_PER_IF+m] = port_tx_clk;
assign app_direct_tx_rst[n*PORTS_PER_IF+m] = port_tx_rst;
assign app_direct_rx_clk[n*PORTS_PER_IF+m] = port_rx_clk;
assign app_direct_rx_rst[n*PORTS_PER_IF+m] = port_rx_rst;
if (PTP_TS_ENABLE) begin: ptp
// PTP CDC logic
@ -2358,8 +2373,8 @@ generate
tx_ptp_cdc_inst (
.input_clk(clk),
.input_rst(rst),
.output_clk(tx_clk[n*PORTS_PER_IF+m]),
.output_rst(tx_rst[n*PORTS_PER_IF+m]),
.output_clk(port_tx_clk),
.output_rst(port_tx_rst),
.sample_clk(ptp_sample_clk),
.input_ts(ptp_ts_96),
.input_ts_step(ptp_ts_step),
@ -2378,8 +2393,8 @@ generate
rx_ptp_cdc_inst (
.input_clk(clk),
.input_rst(rst),
.output_clk(PTP_SEPARATE_RX_CLOCK ? rx_ptp_clk[n*PORTS_PER_IF+m] : rx_clk[n*PORTS_PER_IF+m]),
.output_rst(PTP_SEPARATE_RX_CLOCK ? rx_ptp_rst[n*PORTS_PER_IF+m] : rx_rst[n*PORTS_PER_IF+m]),
.output_clk(port_rx_ptp_clk),
.output_rst(port_rx_ptp_rst),
.sample_clk(ptp_sample_clk),
.input_ts(ptp_ts_96),
.input_ts_step(ptp_ts_step),
@ -2460,8 +2475,8 @@ generate
)
tx_ptp_ts_fifo_inst (
// AXI input
.s_clk(tx_clk[n*PORTS_PER_IF+m]),
.s_rst(tx_rst[n*PORTS_PER_IF+m]),
.s_clk(port_tx_clk),
.s_rst(port_tx_rst),
.s_axis_tdata(axis_tx_in_ptp_ts),
.s_axis_tkeep(0),
.s_axis_tvalid(axis_tx_in_ptp_ts_valid),
@ -2909,8 +2924,8 @@ generate
.s_axis_tuser(axis_tx_async_fifo_tuser),
// AXI output
.m_clk(tx_clk[n*PORTS_PER_IF+m]),
.m_rst(tx_rst[n*PORTS_PER_IF+m]),
.m_clk(port_tx_clk),
.m_rst(port_tx_rst),
.m_axis_tdata(axis_tx_out_tdata),
.m_axis_tkeep(axis_tx_out_tkeep),
.m_axis_tvalid(axis_tx_out_tvalid),
@ -3076,8 +3091,8 @@ generate
)
rx_async_fifo_inst (
// AXI input
.s_clk(rx_clk[n*PORTS_PER_IF+m]),
.s_rst(rx_rst[n*PORTS_PER_IF+m]),
.s_clk(port_rx_clk),
.s_rst(port_rx_rst),
.s_axis_tdata(axis_rx_in_tdata),
.s_axis_tkeep(axis_rx_in_tkeep),
.s_axis_tvalid(axis_rx_in_tvalid),

16
fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py
View File

@ -107,22 +107,22 @@ class TB(object):
for iface in dut.core_inst.iface:
for port in iface.port:
cocotb.fork(Clock(port.rx_async_fifo_inst.s_clk, eth_clock_period, units="ns").start())
cocotb.fork(Clock(port.tx_async_fifo_inst.m_clk, eth_clock_period, units="ns").start())
cocotb.fork(Clock(port.port_rx_clk, eth_clock_period, units="ns").start())
cocotb.fork(Clock(port.port_tx_clk, eth_clock_period, units="ns").start())
port.rx_async_fifo_inst.s_rst.setimmediatevalue(0)
port.tx_async_fifo_inst.m_rst.setimmediatevalue(0)
port.port_rx_rst.setimmediatevalue(0)
port.port_tx_rst.setimmediatevalue(0)
mac = EthMac(
tx_clk=port.tx_async_fifo_inst.m_clk,
tx_rst=port.tx_async_fifo_inst.m_rst,
tx_clk=port.port_tx_clk,
tx_rst=port.port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(port, "axis_tx"),
tx_ptp_time=port.ptp.tx_ptp_cdc_inst.output_ts,
tx_ptp_ts=port.ptp.axis_tx_ptp_ts,
tx_ptp_ts_tag=port.ptp.axis_tx_ptp_ts_tag,
tx_ptp_ts_valid=port.ptp.axis_tx_ptp_ts_valid,
rx_clk=port.rx_async_fifo_inst.s_clk,
rx_rst=port.rx_async_fifo_inst.s_rst,
rx_clk=port.port_rx_clk,
rx_rst=port.port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(port, "axis_rx"),
rx_ptp_time=port.ptp.rx_ptp_cdc_inst.output_ts,
ifg=12, speed=eth_speed

16
fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py
View File

@ -216,22 +216,22 @@ class TB(object):
for iface in dut.core_pcie_inst.core_inst.iface:
for port in iface.port:
cocotb.fork(Clock(port.rx_async_fifo_inst.s_clk, eth_clock_period, units="ns").start())
cocotb.fork(Clock(port.tx_async_fifo_inst.m_clk, eth_clock_period, units="ns").start())
cocotb.fork(Clock(port.port_rx_clk, eth_clock_period, units="ns").start())
cocotb.fork(Clock(port.port_tx_clk, eth_clock_period, units="ns").start())
port.rx_async_fifo_inst.s_rst.setimmediatevalue(0)
port.tx_async_fifo_inst.m_rst.setimmediatevalue(0)
port.port_rx_rst.setimmediatevalue(0)
port.port_tx_rst.setimmediatevalue(0)
mac = EthMac(
tx_clk=port.tx_async_fifo_inst.m_clk,
tx_rst=port.tx_async_fifo_inst.m_rst,
tx_clk=port.port_tx_clk,
tx_rst=port.port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(port, "axis_tx"),
tx_ptp_time=port.ptp.tx_ptp_cdc_inst.output_ts,
tx_ptp_ts=port.ptp.axis_tx_ptp_ts,
tx_ptp_ts_tag=port.ptp.axis_tx_ptp_ts_tag,
tx_ptp_ts_valid=port.ptp.axis_tx_ptp_ts_valid,
rx_clk=port.rx_async_fifo_inst.s_clk,
rx_rst=port.rx_async_fifo_inst.s_rst,
rx_clk=port.port_rx_clk,
rx_rst=port.port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(port, "axis_rx"),
rx_ptp_time=port.ptp.rx_ptp_cdc_inst.output_ts,
ifg=12, speed=eth_speed

16
fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
View File

@ -291,22 +291,22 @@ class TB(object):
for iface in dut.core_pcie_inst.core_inst.iface:
for port in iface.port:
cocotb.fork(Clock(port.rx_async_fifo_inst.s_clk, eth_clock_period, units="ns").start())
cocotb.fork(Clock(port.tx_async_fifo_inst.m_clk, eth_clock_period, units="ns").start())
cocotb.fork(Clock(port.port_rx_clk, eth_clock_period, units="ns").start())
cocotb.fork(Clock(port.port_tx_clk, eth_clock_period, units="ns").start())
port.rx_async_fifo_inst.s_rst.setimmediatevalue(0)
port.tx_async_fifo_inst.m_rst.setimmediatevalue(0)
port.port_rx_rst.setimmediatevalue(0)
port.port_tx_rst.setimmediatevalue(0)
mac = EthMac(
tx_clk=port.tx_async_fifo_inst.m_clk,
tx_rst=port.tx_async_fifo_inst.m_rst,
tx_clk=port.port_tx_clk,
tx_rst=port.port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(port, "axis_tx"),
tx_ptp_time=port.ptp.tx_ptp_cdc_inst.output_ts,
tx_ptp_ts=port.ptp.axis_tx_ptp_ts,
tx_ptp_ts_tag=port.ptp.axis_tx_ptp_ts_tag,
tx_ptp_ts_valid=port.ptp.axis_tx_ptp_ts_valid,
rx_clk=port.rx_async_fifo_inst.s_clk,
rx_rst=port.rx_async_fifo_inst.s_rst,
rx_clk=port.port_rx_clk,
rx_rst=port.port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(port, "axis_rx"),
rx_ptp_time=port.ptp.rx_ptp_cdc_inst.output_ts,
ifg=12, speed=eth_speed

16
fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py
View File

@ -291,22 +291,22 @@ class TB(object):
for iface in dut.core_pcie_inst.core_inst.iface:
for port in iface.port:
cocotb.fork(Clock(port.rx_async_fifo_inst.s_clk, eth_clock_period, units="ns").start())
cocotb.fork(Clock(port.tx_async_fifo_inst.m_clk, eth_clock_period, units="ns").start())
cocotb.fork(Clock(port.port_rx_clk, eth_clock_period, units="ns").start())
cocotb.fork(Clock(port.port_tx_clk, eth_clock_period, units="ns").start())
port.rx_async_fifo_inst.s_rst.setimmediatevalue(0)
port.tx_async_fifo_inst.m_rst.setimmediatevalue(0)
port.port_rx_rst.setimmediatevalue(0)
port.port_tx_rst.setimmediatevalue(0)
mac = EthMac(
tx_clk=port.tx_async_fifo_inst.m_clk,
tx_rst=port.tx_async_fifo_inst.m_rst,
tx_clk=port.port_tx_clk,
tx_rst=port.port_tx_rst,
tx_bus=AxiStreamBus.from_prefix(port, "axis_tx"),
tx_ptp_time=port.ptp.tx_ptp_cdc_inst.output_ts,
tx_ptp_ts=port.ptp.axis_tx_ptp_ts,
tx_ptp_ts_tag=port.ptp.axis_tx_ptp_ts_tag,
tx_ptp_ts_valid=port.ptp.axis_tx_ptp_ts_valid,
rx_clk=port.rx_async_fifo_inst.s_clk,
rx_rst=port.rx_async_fifo_inst.s_rst,
rx_clk=port.port_rx_clk,
rx_rst=port.port_rx_rst,
rx_bus=AxiStreamBus.from_prefix(port, "axis_rx"),
rx_ptp_time=port.ptp.rx_ptp_cdc_inst.output_ts,
ifg=12, speed=eth_speed