mirror of
https://github.com/corundum/corundum.git
synced 2025-01-16 08:12:53 +08:00
Add 10G mqnic design for Alveo U280
This commit is contained in:
Alex Forencich
parent
2d4c7925f0
commit
6433275139
25
fpga/mqnic/AU280/fpga_10g/Makefile
Normal file
25
fpga/mqnic/AU280/fpga_10g/Makefile
Normal file
@ -0,0 +1,25 @@
|
||||
# Targets
|
||||
TARGETS:=
|
||||
|
||||
# Subdirectories
|
||||
SUBDIRS = fpga
|
||||
SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS))
|
||||
|
||||
# Rules
|
||||
.PHONY: all
|
||||
all: $(SUBDIRS) $(TARGETS)
|
||||
|
||||
.PHONY: $(SUBDIRS)
|
||||
$(SUBDIRS):
|
||||
cd $@ && $(MAKE)
|
||||
|
||||
.PHONY: $(SUBDIRS_CLEAN)
|
||||
$(SUBDIRS_CLEAN):
|
||||
cd $(@:.clean=) && $(MAKE) clean
|
||||
|
||||
.PHONY: clean
|
||||
clean: $(SUBDIRS_CLEAN)
|
||||
-rm -rf $(TARGETS)
|
||||
|
||||
program:
|
||||
#djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit
|
||||
24
fpga/mqnic/AU280/fpga_10g/README.md
Normal file
24
fpga/mqnic/AU280/fpga_10g/README.md
Normal file
@ -0,0 +1,24 @@
|
||||
# Corundum mqnic for Alveo U280
|
||||
|
||||
## Introduction
|
||||
|
||||
This design targets the Xilinx Alveo U280 FPGA board.
|
||||
|
||||
* FPGA: xcu280-fsvh2892-2L-e
|
||||
* PHY: 10G BASE-R PHY IP core and internal GTY transceivers
|
||||
|
||||
## How to build
|
||||
|
||||
Run make to build. Ensure that the Xilinx Vivado toolchain components are
|
||||
in PATH.
|
||||
|
||||
Run make to build the driver. Ensure the headers for the running kernel are
|
||||
installed, otherwise the driver cannot be compiled.
|
||||
|
||||
## How to test
|
||||
|
||||
Run make program to program the Alveo U280 board with Vivado. Then load the
|
||||
driver with insmod mqnic.ko. Check dmesg for output from driver
|
||||
initialization.
|
||||
|
||||
|
||||
120
fpga/mqnic/AU280/fpga_10g/common/vivado.mk
Normal file
120
fpga/mqnic/AU280/fpga_10g/common/vivado.mk
Normal file
@ -0,0 +1,120 @@
|
||||
###################################################################
|
||||
#
|
||||
# Xilinx Vivado FPGA Makefile
|
||||
#
|
||||
# Copyright (c) 2016 Alex Forencich
|
||||
#
|
||||
###################################################################
|
||||
#
|
||||
# Parameters:
|
||||
# FPGA_TOP - Top module name
|
||||
# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
|
||||
# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
|
||||
# SYN_FILES - space-separated list of source files
|
||||
# INC_FILES - space-separated list of include files
|
||||
# XDC_FILES - space-separated list of timing constraint files
|
||||
# XCI_FILES - space-separated list of IP XCI files
|
||||
#
|
||||
# Example:
|
||||
#
|
||||
# FPGA_TOP = fpga
|
||||
# FPGA_FAMILY = VirtexUltrascale
|
||||
# FPGA_DEVICE = xcvu095-ffva2104-2-e
|
||||
# SYN_FILES = rtl/fpga.v
|
||||
# XDC_FILES = fpga.xdc
|
||||
# XCI_FILES = ip/pcspma.xci
|
||||
# include ../common/vivado.mk
|
||||
#
|
||||
###################################################################
|
||||
|
||||
# phony targets
|
||||
.PHONY: clean fpga
|
||||
|
||||
# prevent make from deleting intermediate files and reports
|
||||
.PRECIOUS: %.xpr %.bit %.mcs %.prm
|
||||
.SECONDARY:
|
||||
|
||||
CONFIG ?= config.mk
|
||||
-include ../$(CONFIG)
|
||||
|
||||
SYN_FILES_REL = $(patsubst %, ../%, $(SYN_FILES))
|
||||
INC_FILES_REL = $(patsubst %, ../%, $(INC_FILES))
|
||||
XCI_FILES_REL = $(patsubst %, ../%, $(XCI_FILES))
|
||||
IP_TCL_FILES_REL = $(patsubst %, ../%, $(IP_TCL_FILES))
|
||||
|
||||
ifdef XDC_FILES
|
||||
XDC_FILES_REL = $(patsubst %, ../%, $(XDC_FILES))
|
||||
else
|
||||
XDC_FILES_REL = $(FPGA_TOP).xdc
|
||||
endif
|
||||
|
||||
###################################################################
|
||||
# Main Targets
|
||||
#
|
||||
# all: build everything
|
||||
# clean: remove output files and project files
|
||||
###################################################################
|
||||
|
||||
all: fpga
|
||||
|
||||
fpga: $(FPGA_TOP).bit
|
||||
|
||||
tmpclean:
|
||||
-rm -rf *.log *.jou *.cache *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
|
||||
-rm -rf create_project.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
|
||||
|
||||
clean: tmpclean
|
||||
-rm -rf *.bit program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
|
||||
|
||||
distclean: clean
|
||||
-rm -rf rev
|
||||
|
||||
###################################################################
|
||||
# Target implementations
|
||||
###################################################################
|
||||
|
||||
# Vivado project file
|
||||
%.xpr: Makefile $(XCI_FILES_REL)
|
||||
rm -rf defines.v
|
||||
touch defines.v
|
||||
for x in $(DEFS); do echo '`define' $$x >> defines.v; done
|
||||
echo "create_project -force -part $(FPGA_PART) $*" > create_project.tcl
|
||||
echo "add_files -fileset sources_1 defines.v" >> create_project.tcl
|
||||
for x in $(SYN_FILES_REL); do echo "add_files -fileset sources_1 $$x" >> create_project.tcl; done
|
||||
for x in $(XDC_FILES_REL); do echo "add_files -fileset constrs_1 $$x" >> create_project.tcl; done
|
||||
for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> create_project.tcl; done
|
||||
for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> create_project.tcl; done
|
||||
echo "exit" >> create_project.tcl
|
||||
vivado -nojournal -nolog -mode batch -source create_project.tcl
|
||||
|
||||
# synthesis run
|
||||
%.runs/synth_1/%.dcp: %.xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL)
|
||||
echo "open_project $*.xpr" > run_synth.tcl
|
||||
echo "reset_run synth_1" >> run_synth.tcl
|
||||
echo "launch_runs synth_1" >> run_synth.tcl
|
||||
echo "wait_on_run synth_1" >> run_synth.tcl
|
||||
echo "exit" >> run_synth.tcl
|
||||
vivado -nojournal -nolog -mode batch -source run_synth.tcl
|
||||
|
||||
# implementation run
|
||||
%.runs/impl_1/%_routed.dcp: %.runs/synth_1/%.dcp
|
||||
echo "open_project $*.xpr" > run_impl.tcl
|
||||
echo "reset_run impl_1" >> run_impl.tcl
|
||||
echo "launch_runs impl_1" >> run_impl.tcl
|
||||
echo "wait_on_run impl_1" >> run_impl.tcl
|
||||
echo "exit" >> run_impl.tcl
|
||||
vivado -nojournal -nolog -mode batch -source run_impl.tcl
|
||||
|
||||
# bit file
|
||||
%.bit: %.runs/impl_1/%_routed.dcp
|
||||
echo "open_project $*.xpr" > generate_bit.tcl
|
||||
echo "open_run impl_1" >> generate_bit.tcl
|
||||
echo "write_bitstream -force $*.bit" >> generate_bit.tcl
|
||||
echo "exit" >> generate_bit.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_bit.tcl
|
||||
mkdir -p rev
|
||||
EXT=bit; COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
cp $@ rev/$*_rev$$COUNT.$$EXT; \
|
||||
echo "Output: rev/$*_rev$$COUNT.$$EXT";
|
||||
194
fpga/mqnic/AU280/fpga_10g/fpga.xdc
Normal file
194
fpga/mqnic/AU280/fpga_10g/fpga.xdc
Normal file
@ -0,0 +1,194 @@
|
||||
# XDC constraints for the Xilinx Alveo U280 board
|
||||
# part: xcu280-fsvh2892-2L-e
|
||||
|
||||
# General configuration
|
||||
set_property CFGBVS GND [current_design]
|
||||
set_property CONFIG_VOLTAGE 1.8 [current_design]
|
||||
set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design]
|
||||
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
|
||||
set_property CONFIG_MODE SPIx4 [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
|
||||
set_property BITSTREAM.CONFIG.CONFIGRATE 85.0 [current_design]
|
||||
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
|
||||
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]
|
||||
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
|
||||
|
||||
# System clocks
|
||||
# 100 MHz (DDR4)
|
||||
#set_property -dict {LOC BJ43 IOSTANDARD LVDS} [get_ports clk_100mhz_0_p]
|
||||
#set_property -dict {LOC BJ44 IOSTANDARD LVDS} [get_ports clk_100mhz_0_n]
|
||||
#create_clock -period 10 -name clk_100mhz_0 [get_ports clk_100mhz_0_p]
|
||||
|
||||
# 100 MHz (DDR4)
|
||||
#set_property -dict {LOC BH6 IOSTANDARD LVDS} [get_ports clk_100mhz_1_p]
|
||||
#set_property -dict {LOC BJ6 IOSTANDARD LVDS} [get_ports clk_100mhz_1_n]
|
||||
#create_clock -period 10 -name clk_100mhz_1 [get_ports clk_100mhz_1_p]
|
||||
|
||||
# 100 MHz
|
||||
#set_property -dict {LOC G31 IOSTANDARD LVDS} [get_ports clk_100mhz_2_p]
|
||||
#set_property -dict {LOC F31 IOSTANDARD LVDS} [get_ports clk_100mhz_2_n]
|
||||
#create_clock -period 10 -name clk_100mhz_2 [get_ports clk_100mhz_2_p]
|
||||
|
||||
# SI570 user clock
|
||||
#set_property -dict {LOC G30 IOSTANDARD LVDS} [get_ports clk_si570_p]
|
||||
#set_property -dict {LOC F30 IOSTANDARD LVDS} [get_ports clk_si570_n]
|
||||
#create_clock -period 6.4 -name clk_si570 [get_ports clk_si570_p]
|
||||
|
||||
# Reset button
|
||||
#set_property -dict {LOC L30 IOSTANDARD LVCMOS18} [get_ports reset]
|
||||
|
||||
# UART
|
||||
#set_property -dict {LOC A28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports usb_uart_txd]
|
||||
#set_property -dict {LOC B33 IOSTANDARD LVCMOS18} [get_ports usb_uart_rxd]
|
||||
|
||||
# HBM overtemp
|
||||
set_property -dict {LOC D32 IOSTANDARD LVCMOS18} [get_ports hbm_cattrip]
|
||||
|
||||
# QSFP28 Interfaces
|
||||
set_property -dict {LOC L48 } [get_ports qsfp0_tx1_p] ;# MGTYTXP0_134 GTYE3_CHANNEL_X1Y40 / GTYE3_COMMON_X1Y10
|
||||
#set_property -dict {LOC L49 } [get_ports qsfp0_tx1_n] ;# MGTYTXN0_134 GTYE3_CHANNEL_X1Y40 / GTYE3_COMMON_X1Y10
|
||||
set_property -dict {LOC L53 } [get_ports qsfp0_rx1_p] ;# MGTYRXP0_134 GTYE3_CHANNEL_X1Y40 / GTYE3_COMMON_X1Y10
|
||||
#set_property -dict {LOC L54 } [get_ports qsfp0_rx1_n] ;# MGTYRXN0_134 GTYE3_CHANNEL_X1Y40 / GTYE3_COMMON_X1Y10
|
||||
set_property -dict {LOC L44 } [get_ports qsfp0_tx2_p] ;# MGTYTXP1_134 GTYE3_CHANNEL_X1Y41 / GTYE3_COMMON_X1Y10
|
||||
#set_property -dict {LOC L45 } [get_ports qsfp0_tx2_n] ;# MGTYTXN1_134 GTYE3_CHANNEL_X1Y41 / GTYE3_COMMON_X1Y10
|
||||
set_property -dict {LOC K51 } [get_ports qsfp0_rx2_p] ;# MGTYRXP1_134 GTYE3_CHANNEL_X1Y41 / GTYE3_COMMON_X1Y10
|
||||
#set_property -dict {LOC K52 } [get_ports qsfp0_rx2_n] ;# MGTYRXN1_134 GTYE3_CHANNEL_X1Y41 / GTYE3_COMMON_X1Y10
|
||||
set_property -dict {LOC K46 } [get_ports qsfp0_tx3_p] ;# MGTYTXP2_134 GTYE3_CHANNEL_X1Y42 / GTYE3_COMMON_X1Y10
|
||||
#set_property -dict {LOC K47 } [get_ports qsfp0_tx3_n] ;# MGTYTXN2_134 GTYE3_CHANNEL_X1Y42 / GTYE3_COMMON_X1Y10
|
||||
set_property -dict {LOC J53 } [get_ports qsfp0_rx3_p] ;# MGTYRXP2_134 GTYE3_CHANNEL_X1Y42 / GTYE3_COMMON_X1Y10
|
||||
#set_property -dict {LOC J54 } [get_ports qsfp0_rx3_n] ;# MGTYRXN2_134 GTYE3_CHANNEL_X1Y42 / GTYE3_COMMON_X1Y10
|
||||
set_property -dict {LOC J48 } [get_ports qsfp0_tx4_p] ;# MGTYTXP3_134 GTYE3_CHANNEL_X1Y43 / GTYE3_COMMON_X1Y10
|
||||
#set_property -dict {LOC J49 } [get_ports qsfp0_tx4_n] ;# MGTYTXN3_134 GTYE3_CHANNEL_X1Y43 / GTYE3_COMMON_X1Y10
|
||||
set_property -dict {LOC H51 } [get_ports qsfp0_rx4_p] ;# MGTYRXP3_134 GTYE3_CHANNEL_X1Y43 / GTYE3_COMMON_X1Y10
|
||||
#set_property -dict {LOC H52 } [get_ports qsfp0_rx4_n] ;# MGTYRXN3_134 GTYE3_CHANNEL_X1Y43 / GTYE3_COMMON_X1Y10
|
||||
#set_property -dict {LOC T42 } [get_ports qsfp0_mgt_refclk_0_p] ;# MGTREFCLK0P_134 from SI570
|
||||
#set_property -dict {LOC T43 } [get_ports qsfp0_mgt_refclk_0_n] ;# MGTREFCLK0N_134 from SI570
|
||||
set_property -dict {LOC R40 } [get_ports qsfp0_mgt_refclk_1_p] ;# MGTREFCLK1P_134 from SI546
|
||||
#set_property -dict {LOC R41 } [get_ports qsfp0_mgt_refclk_1_n] ;# MGTREFCLK1N_134 from SI546
|
||||
set_property -dict {LOC H32 IOSTANDARD LVCMOS18} [get_ports qsfp0_refclk_oe_b]
|
||||
set_property -dict {LOC G32 IOSTANDARD LVCMOS18} [get_ports qsfp0_refclk_fs]
|
||||
|
||||
# 156.25 MHz MGT reference clock (from SI570)
|
||||
#create_clock -period 6.400 -name qsfp0_mgt_refclk_0 [get_ports qsfp0_mgt_refclk_0_p]
|
||||
|
||||
# 156.25 MHz MGT reference clock (from SI546, fs = 0)
|
||||
#create_clock -period 6.400 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_1_p]
|
||||
|
||||
# 161.1328125 MHz MGT reference clock (from SI546, fs = 1)
|
||||
create_clock -period 6.206 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_1_p]
|
||||
|
||||
set_property -dict {LOC G48 } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_135 GTYE3_CHANNEL_X1Y44 / GTYE3_COMMON_X1Y11
|
||||
#set_property -dict {LOC G49 } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_135 GTYE3_CHANNEL_X1Y44 / GTYE3_COMMON_X1Y11
|
||||
set_property -dict {LOC G53 } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_135 GTYE3_CHANNEL_X1Y44 / GTYE3_COMMON_X1Y11
|
||||
#set_property -dict {LOC G54 } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_135 GTYE3_CHANNEL_X1Y44 / GTYE3_COMMON_X1Y11
|
||||
set_property -dict {LOC E48 } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_135 GTYE3_CHANNEL_X1Y45 / GTYE3_COMMON_X1Y11
|
||||
#set_property -dict {LOC E49 } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_135 GTYE3_CHANNEL_X1Y45 / GTYE3_COMMON_X1Y11
|
||||
set_property -dict {LOC F51 } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_135 GTYE3_CHANNEL_X1Y45 / GTYE3_COMMON_X1Y11
|
||||
#set_property -dict {LOC F52 } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_135 GTYE3_CHANNEL_X1Y45 / GTYE3_COMMON_X1Y11
|
||||
set_property -dict {LOC C48 } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_135 GTYE3_CHANNEL_X1Y46 / GTYE3_COMMON_X1Y11
|
||||
#set_property -dict {LOC C49 } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_135 GTYE3_CHANNEL_X1Y46 / GTYE3_COMMON_X1Y11
|
||||
set_property -dict {LOC E53 } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_135 GTYE3_CHANNEL_X1Y46 / GTYE3_COMMON_X1Y11
|
||||
#set_property -dict {LOC E54 } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_135 GTYE3_CHANNEL_X1Y46 / GTYE3_COMMON_X1Y11
|
||||
set_property -dict {LOC A49 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_135 GTYE3_CHANNEL_X1Y47 / GTYE3_COMMON_X1Y11
|
||||
#set_property -dict {LOC A50 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_135 GTYE3_CHANNEL_X1Y47 / GTYE3_COMMON_X1Y11
|
||||
set_property -dict {LOC D51 } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_135 GTYE3_CHANNEL_X1Y47 / GTYE3_COMMON_X1Y11
|
||||
#set_property -dict {LOC D52 } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_135 GTYE3_CHANNEL_X1Y47 / GTYE3_COMMON_X1Y11
|
||||
#set_property -dict {LOC P42 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_135 from SI570
|
||||
#set_property -dict {LOC P43 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_135 from SI570
|
||||
#set_property -dict {LOC M42 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_135 from SI546
|
||||
#set_property -dict {LOC M43 } [get_ports qsfp1_mgt_refclk_1_n] ;# MGTREFCLK1N_135 from SI546
|
||||
set_property -dict {LOC H30 IOSTANDARD LVCMOS18} [get_ports qsfp1_refclk_oe_b]
|
||||
set_property -dict {LOC G33 IOSTANDARD LVCMOS18} [get_ports qsfp1_refclk_fs]
|
||||
|
||||
# 156.25 MHz MGT reference clock (from SI570)
|
||||
#create_clock -period 6.400 -name qsfp1_mgt_refclk_0 [get_ports qsfp1_mgt_refclk_0_p]
|
||||
|
||||
# 156.25 MHz MGT reference clock (from SI546, fs = 0)
|
||||
#create_clock -period 6.400 -name qsfp1_mgt_refclk_1 [get_ports qsfp1_mgt_refclk_1_p]
|
||||
|
||||
# 161.1328125 MHz MGT reference clock (from SI546, fs = 1)
|
||||
#create_clock -period 6.206 -name qsfp1_mgt_refclk_1 [get_ports qsfp1_mgt_refclk_1_p]
|
||||
|
||||
# PCIe Interface
|
||||
set_property -dict {LOC AL2 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AL1 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||
set_property -dict {LOC AL11} [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AL10} [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y15 / GTYE4_COMMON_X1Y3
|
||||
set_property -dict {LOC AM4 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AM3 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||
set_property -dict {LOC AM9 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AM8 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y14 / GTYE4_COMMON_X1Y3
|
||||
set_property -dict {LOC AN6 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AN5 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||
set_property -dict {LOC AN11} [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AN10} [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y13 / GTYE4_COMMON_X1Y3
|
||||
set_property -dict {LOC AN2 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AN1 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||
set_property -dict {LOC AP9 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||
#set_property -dict {LOC AP8 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y12 / GTYE4_COMMON_X1Y3
|
||||
set_property -dict {LOC AP4 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AP3 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AR11} [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AR10} [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y11 / GTYE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AR2 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AR1 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AR7 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AR6 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y10 / GTYE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AT4 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AT3 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AT9 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AT8 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y9 / GTYE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AU2 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AU1 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AU11} [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||
#set_property -dict {LOC AU10} [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y8 / GTYE4_COMMON_X1Y2
|
||||
set_property -dict {LOC AV4 } [get_ports {pcie_rx_p[8]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AV3 } [get_ports {pcie_rx_n[8]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
set_property -dict {LOC AU7 } [get_ports {pcie_tx_p[8]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AU6 } [get_ports {pcie_tx_n[8]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y7 / GTYE4_COMMON_X1Y1
|
||||
set_property -dict {LOC AW6 } [get_ports {pcie_rx_p[9]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AW5 } [get_ports {pcie_rx_n[9]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
set_property -dict {LOC AV9 } [get_ports {pcie_tx_p[9]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AV8 } [get_ports {pcie_tx_n[9]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y6 / GTYE4_COMMON_X1Y1
|
||||
set_property -dict {LOC AW2 } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AW1 } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
set_property -dict {LOC AW11} [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AW10} [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y5 / GTYE4_COMMON_X1Y1
|
||||
set_property -dict {LOC AY4 } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AY3 } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
set_property -dict {LOC AY9 } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
#set_property -dict {LOC AY8 } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y4 / GTYE4_COMMON_X1Y1
|
||||
set_property -dict {LOC BA6 } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BA5 } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
set_property -dict {LOC BA11} [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BA10} [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y3 / GTYE4_COMMON_X1Y0
|
||||
set_property -dict {LOC BA2 } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BA1 } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
set_property -dict {LOC BB9 } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BB8 } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y2 / GTYE4_COMMON_X1Y0
|
||||
set_property -dict {LOC BB4 } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BB3 } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
set_property -dict {LOC BC11} [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BC10} [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y1 / GTYE4_COMMON_X1Y0
|
||||
set_property -dict {LOC BC2 } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BC1 } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
set_property -dict {LOC BC7 } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC BC6 } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y0 / GTYE4_COMMON_X1Y0
|
||||
#set_property -dict {LOC AL15} [get_ports pcie_refclk_0_p] ;# MGTREFCLK0P_227 (for x8 bifurcated lanes 0-7)
|
||||
#set_property -dict {LOC AL14} [get_ports pcie_refclk_0_n] ;# MGTREFCLK0N_227 (for x8 bifurcated lanes 0-7)
|
||||
#set_property -dict {LOC AK13} [get_ports pcie_refclk_2_p] ;# MGTREFCLK1P_227 (for async x8 bifurcated lanes 0-7)
|
||||
#set_property -dict {LOC AK12} [get_ports pcie_refclk_2_n] ;# MGTREFCLK1N_227 (for async x8 bifurcated lanes 0-7)
|
||||
set_property -dict {LOC AR15} [get_ports pcie_refclk_1_p] ;# MGTREFCLK0P_225 (for x16 or x8 bifurcated lanes 8-16)
|
||||
#set_property -dict {LOC AR14} [get_ports pcie_refclk_1_n] ;# MGTREFCLK0N_225 (for x16 or x8 bifurcated lanes 8-16)
|
||||
#set_property -dict {LOC AP13} [get_ports pcie_refclk_3_p] ;# MGTREFCLK1P_225 (for async x16 or x8 bifurcated lanes 8-16)
|
||||
#set_property -dict {LOC AP12} [get_ports pcie_refclk_3_n] ;# MGTREFCLK1N_225 (for async x16 or x8 bifurcated lanes 8-16)
|
||||
set_property -dict {LOC BH26 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_reset_n]
|
||||
|
||||
# 100 MHz MGT reference clock
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_0 [get_ports pcie_refclk_0_p]
|
||||
create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_1_p]
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_2 [get_ports pcie_refclk_2_p]
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_3 [get_ports pcie_refclk_3_p]
|
||||
|
||||
|
||||
93
fpga/mqnic/AU280/fpga_10g/fpga/Makefile
Normal file
93
fpga/mqnic/AU280/fpga_10g/fpga/Makefile
Normal file
@ -0,0 +1,93 @@
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcu280-fsvh2892-2L-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = virtexuplus
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = rtl/fpga.v
|
||||
SYN_FILES += rtl/fpga_core.v
|
||||
SYN_FILES += rtl/sync_signal.v
|
||||
SYN_FILES += rtl/common/interface.v
|
||||
SYN_FILES += rtl/common/port.v
|
||||
SYN_FILES += rtl/common/cpl_write.v
|
||||
SYN_FILES += rtl/common/cpl_op_mux.v
|
||||
SYN_FILES += rtl/common/desc_fetch.v
|
||||
SYN_FILES += rtl/common/desc_op_mux.v
|
||||
SYN_FILES += rtl/common/queue_manager.v
|
||||
SYN_FILES += rtl/common/cpl_queue_manager.v
|
||||
SYN_FILES += rtl/common/event_mux.v
|
||||
SYN_FILES += rtl/common/tx_scheduler_rr.v
|
||||
SYN_FILES += rtl/common/tdma_scheduler.v
|
||||
SYN_FILES += rtl/common/tdma_ber.v
|
||||
SYN_FILES += rtl/common/tdma_ber_ch.v
|
||||
SYN_FILES += rtl/common/tx_engine.v
|
||||
SYN_FILES += rtl/common/rx_engine.v
|
||||
SYN_FILES += rtl/common/tx_checksum.v
|
||||
SYN_FILES += rtl/common/rx_hash.v
|
||||
SYN_FILES += rtl/common/rx_checksum.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
|
||||
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
|
||||
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
|
||||
SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
|
||||
SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
|
||||
SYN_FILES += lib/eth/rtl/lfsr.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_clock.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
|
||||
SYN_FILES += lib/eth/rtl/ptp_ts_extract.v
|
||||
SYN_FILES += lib/axi/rtl/axil_interconnect.v
|
||||
SYN_FILES += lib/axi/rtl/arbiter.v
|
||||
SYN_FILES += lib/axi/rtl/priority_encoder.v
|
||||
SYN_FILES += lib/axis/rtl/axis_adapter.v
|
||||
SYN_FILES += lib/axis/rtl/axis_async_fifo.v
|
||||
SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
|
||||
SYN_FILES += lib/axis/rtl/axis_fifo.v
|
||||
SYN_FILES += lib/axis/rtl/axis_register.v
|
||||
SYN_FILES += lib/axis/rtl/sync_reset.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_pcie_us_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_mux.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_psdpram.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v
|
||||
SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
|
||||
SYN_FILES += lib/pcie/rtl/pcie_tag_manager.v
|
||||
SYN_FILES += lib/pcie/rtl/pulse_merge.v
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = fpga.xdc
|
||||
XDC_FILES += lib/axis/syn/axis_async_fifo.tcl
|
||||
XDC_FILES += lib/axis/syn/sync_reset.tcl
|
||||
XDC_FILES += lib/eth/syn/ptp_clock_cdc.tcl
|
||||
XDC_FILES += ../../../common/syn/tdma_ber_ch.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl
|
||||
IP_TCL_FILES += ip/gtwizard_ultrascale_0.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(FPGA_TOP).bit
|
||||
echo "open_hw" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
21
fpga/mqnic/AU280/fpga_10g/ip/gtwizard_ultrascale_0.tcl
Normal file
21
fpga/mqnic/AU280/fpga_10g/ip/gtwizard_ultrascale_0.tcl
Normal file
@ -0,0 +1,21 @@
|
||||
|
||||
create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name gtwizard_ultrascale_0
|
||||
|
||||
set_property -dict [list CONFIG.preset {GTY-10GBASE-R}] [get_ips gtwizard_ultrascale_0]
|
||||
|
||||
set_property -dict [list \
|
||||
CONFIG.CHANNEL_ENABLE {X0Y47 X0Y46 X0Y45 X0Y44 X0Y43 X0Y42 X0Y41 X0Y40} \
|
||||
CONFIG.TX_MASTER_CHANNEL {X0Y40} \
|
||||
CONFIG.RX_MASTER_CHANNEL {X0Y40} \
|
||||
CONFIG.TX_LINE_RATE {10.3125} \
|
||||
CONFIG.TX_REFCLK_FREQUENCY {161.1328125} \
|
||||
CONFIG.TX_USER_DATA_WIDTH {64} \
|
||||
CONFIG.TX_INT_DATA_WIDTH {64} \
|
||||
CONFIG.RX_LINE_RATE {10.3125} \
|
||||
CONFIG.RX_REFCLK_FREQUENCY {161.1328125} \
|
||||
CONFIG.RX_USER_DATA_WIDTH {64} \
|
||||
CONFIG.RX_INT_DATA_WIDTH {64} \
|
||||
CONFIG.RX_REFCLK_SOURCE {X0Y47 clk1-1 X0Y46 clk1-1 X0Y45 clk1-1 X0Y44 clk1-1 X0Y43 clk1 X0Y42 clk1 X0Y41 clk1 X0Y40 clk1} \
|
||||
CONFIG.TX_REFCLK_SOURCE {X0Y47 clk1-1 X0Y46 clk1-1 X0Y45 clk1-1 X0Y44 clk1-1 X0Y43 clk1 X0Y42 clk1 X0Y41 clk1 X0Y40 clk1} \
|
||||
CONFIG.FREERUN_FREQUENCY {125} \
|
||||
] [get_ips gtwizard_ultrascale_0]
|
||||
24
fpga/mqnic/AU280/fpga_10g/ip/pcie4c_uscale_plus_0.tcl
Normal file
24
fpga/mqnic/AU280/fpga_10g/ip/pcie4c_uscale_plus_0.tcl
Normal file
@ -0,0 +1,24 @@
|
||||
|
||||
create_ip -name pcie4c_uscale_plus -vendor xilinx.com -library ip -module_name pcie4c_uscale_plus_0
|
||||
|
||||
set_property -dict [list \
|
||||
CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \
|
||||
CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \
|
||||
CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \
|
||||
CONFIG.axisten_if_enable_client_tag {true} \
|
||||
CONFIG.axisten_if_width {512_bit} \
|
||||
CONFIG.axisten_freq {250} \
|
||||
CONFIG.PF0_CLASS_CODE {020000} \
|
||||
CONFIG.PF0_DEVICE_ID {1001} \
|
||||
CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \
|
||||
CONFIG.PF0_SUBSYSTEM_ID {1001} \
|
||||
CONFIG.PF0_SUBSYSTEM_VENDOR_ID {1234} \
|
||||
CONFIG.PF0_Use_Class_Code_Lookup_Assistant {true} \
|
||||
CONFIG.pf0_class_code_sub {00} \
|
||||
CONFIG.pf0_base_class_menu {Network_controller} \
|
||||
CONFIG.pf0_sub_class_interface_menu {Ethernet_controller} \
|
||||
CONFIG.pf0_bar0_scale {Megabytes} \
|
||||
CONFIG.pf0_bar0_size {16} \
|
||||
CONFIG.vendor_id {1234} \
|
||||
CONFIG.en_msi_per_vec_masking {true} \
|
||||
] [get_ips pcie4c_uscale_plus_0]
|
||||
1
fpga/mqnic/AU280/fpga_10g/lib
Symbolic link
1
fpga/mqnic/AU280/fpga_10g/lib
Symbolic link
@ -0,0 +1 @@
|
||||
../../../lib/
|
||||
1
fpga/mqnic/AU280/fpga_10g/rtl/common
Symbolic link
1
fpga/mqnic/AU280/fpga_10g/rtl/common
Symbolic link
@ -0,0 +1 @@
|
||||
../../../../common/rtl/
|
||||
1320
fpga/mqnic/AU280/fpga_10g/rtl/fpga.v
Normal file
1320
fpga/mqnic/AU280/fpga_10g/rtl/fpga.v
Normal file
File diff suppressed because it is too large
Load Diff
2399
fpga/mqnic/AU280/fpga_10g/rtl/fpga_core.v
Normal file
2399
fpga/mqnic/AU280/fpga_10g/rtl/fpga_core.v
Normal file
File diff suppressed because it is too large
Load Diff
58
fpga/mqnic/AU280/fpga_10g/rtl/sync_signal.v
Normal file
58
fpga/mqnic/AU280/fpga_10g/rtl/sync_signal.v
Normal file
@ -0,0 +1,58 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog-2001
|
||||
|
||||
`timescale 1 ns / 1 ps
|
||||
|
||||
/*
|
||||
* Synchronizes an asyncronous signal to a given clock by using a pipeline of
|
||||
* two registers.
|
||||
*/
|
||||
module sync_signal #(
|
||||
parameter WIDTH=1, // width of the input and output signals
|
||||
parameter N=2 // depth of synchronizer
|
||||
)(
|
||||
input wire clk,
|
||||
input wire [WIDTH-1:0] in,
|
||||
output wire [WIDTH-1:0] out
|
||||
);
|
||||
|
||||
reg [WIDTH-1:0] sync_reg[N-1:0];
|
||||
|
||||
/*
|
||||
* The synchronized output is the last register in the pipeline.
|
||||
*/
|
||||
assign out = sync_reg[N-1];
|
||||
|
||||
integer k;
|
||||
|
||||
always @(posedge clk) begin
|
||||
sync_reg[0] <= in;
|
||||
for (k = 1; k < N; k = k + 1) begin
|
||||
sync_reg[k] <= sync_reg[k-1];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
1
fpga/mqnic/AU280/fpga_10g/tb/axis_ep.py
Symbolic link
1
fpga/mqnic/AU280/fpga_10g/tb/axis_ep.py
Symbolic link
@ -0,0 +1 @@
|
||||
../lib/eth/tb/axis_ep.py
|
||||
1
fpga/mqnic/AU280/fpga_10g/tb/eth_ep.py
Symbolic link
1
fpga/mqnic/AU280/fpga_10g/tb/eth_ep.py
Symbolic link
@ -0,0 +1 @@
|
||||
../lib/eth/tb/eth_ep.py
|
||||
1
fpga/mqnic/AU280/fpga_10g/tb/ip_ep.py
Symbolic link
1
fpga/mqnic/AU280/fpga_10g/tb/ip_ep.py
Symbolic link
@ -0,0 +1 @@
|
||||
../lib/eth/tb/ip_ep.py
|
||||
1
fpga/mqnic/AU280/fpga_10g/tb/mqnic.py
Symbolic link
1
fpga/mqnic/AU280/fpga_10g/tb/mqnic.py
Symbolic link
@ -0,0 +1 @@
|
||||
../../../../common/tb/mqnic.py
|
||||
1
fpga/mqnic/AU280/fpga_10g/tb/pcie.py
Symbolic link
1
fpga/mqnic/AU280/fpga_10g/tb/pcie.py
Symbolic link
@ -0,0 +1 @@
|
||||
../lib/pcie/tb/pcie.py
|
||||
1
fpga/mqnic/AU280/fpga_10g/tb/pcie_us.py
Symbolic link
1
fpga/mqnic/AU280/fpga_10g/tb/pcie_us.py
Symbolic link
@ -0,0 +1 @@
|
||||
../lib/pcie/tb/pcie_us.py
|
||||
1
fpga/mqnic/AU280/fpga_10g/tb/pcie_usp.py
Symbolic link
1
fpga/mqnic/AU280/fpga_10g/tb/pcie_usp.py
Symbolic link
@ -0,0 +1 @@
|
||||
../lib/pcie/tb/pcie_usp.py
|
||||
990
fpga/mqnic/AU280/fpga_10g/tb/test_fpga_core.py
Executable file
990
fpga/mqnic/AU280/fpga_10g/tb/test_fpga_core.py
Executable file
@ -0,0 +1,990 @@
|
||||
#!/usr/bin/env python
|
||||
"""
|
||||
|
||||
Copyright 2019, The Regents of the University of California.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
|
||||
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
|
||||
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
|
||||
The views and conclusions contained in the software and documentation are those
|
||||
of the authors and should not be interpreted as representing official policies,
|
||||
either expressed or implied, of The Regents of the University of California.
|
||||
|
||||
"""
|
||||
|
||||
from myhdl import *
|
||||
import os
|
||||
|
||||
import pcie
|
||||
import pcie_usp
|
||||
import xgmii_ep
|
||||
import axis_ep
|
||||
import eth_ep
|
||||
import udp_ep
|
||||
|
||||
import struct
|
||||
|
||||
import mqnic
|
||||
|
||||
module = 'fpga_core'
|
||||
testbench = 'test_%s' % module
|
||||
|
||||
srcs = []
|
||||
|
||||
srcs.append("../rtl/%s.v" % module)
|
||||
srcs.append("../rtl/common/interface.v")
|
||||
srcs.append("../rtl/common/port.v")
|
||||
srcs.append("../rtl/common/cpl_write.v")
|
||||
srcs.append("../rtl/common/cpl_op_mux.v")
|
||||
srcs.append("../rtl/common/desc_fetch.v")
|
||||
srcs.append("../rtl/common/desc_op_mux.v")
|
||||
srcs.append("../rtl/common/queue_manager.v")
|
||||
srcs.append("../rtl/common/cpl_queue_manager.v")
|
||||
srcs.append("../rtl/common/tx_engine.v")
|
||||
srcs.append("../rtl/common/rx_engine.v")
|
||||
srcs.append("../rtl/common/tx_checksum.v")
|
||||
srcs.append("../rtl/common/rx_hash.v")
|
||||
srcs.append("../rtl/common/rx_checksum.v")
|
||||
srcs.append("../rtl/common/tx_scheduler_rr.v")
|
||||
srcs.append("../rtl/common/event_mux.v")
|
||||
srcs.append("../rtl/common/tdma_scheduler.v")
|
||||
srcs.append("../rtl/common/tdma_ber.v")
|
||||
srcs.append("../rtl/common/tdma_ber_ch.v")
|
||||
srcs.append("../lib/eth/rtl/eth_mac_10g_fifo.v")
|
||||
srcs.append("../lib/eth/rtl/eth_mac_10g.v")
|
||||
srcs.append("../lib/eth/rtl/axis_xgmii_rx_64.v")
|
||||
srcs.append("../lib/eth/rtl/axis_xgmii_tx_64.v")
|
||||
srcs.append("../lib/eth/rtl/lfsr.v")
|
||||
srcs.append("../lib/eth/rtl/ptp_clock.v")
|
||||
srcs.append("../lib/eth/rtl/ptp_clock_cdc.v")
|
||||
srcs.append("../lib/eth/rtl/ptp_ts_extract.v")
|
||||
srcs.append("../lib/axi/rtl/axil_interconnect.v")
|
||||
srcs.append("../lib/axi/rtl/arbiter.v")
|
||||
srcs.append("../lib/axi/rtl/priority_encoder.v")
|
||||
srcs.append("../lib/axis/rtl/axis_adapter.v")
|
||||
srcs.append("../lib/axis/rtl/axis_arb_mux.v")
|
||||
srcs.append("../lib/axis/rtl/axis_async_fifo.v")
|
||||
srcs.append("../lib/axis/rtl/axis_async_fifo_adapter.v")
|
||||
srcs.append("../lib/axis/rtl/axis_fifo.v")
|
||||
srcs.append("../lib/axis/rtl/axis_register.v")
|
||||
srcs.append("../lib/pcie/rtl/pcie_us_axil_master.v")
|
||||
srcs.append("../lib/pcie/rtl/dma_if_pcie_us.v")
|
||||
srcs.append("../lib/pcie/rtl/dma_if_pcie_us_rd.v")
|
||||
srcs.append("../lib/pcie/rtl/dma_if_pcie_us_wr.v")
|
||||
srcs.append("../lib/pcie/rtl/dma_if_mux.v")
|
||||
srcs.append("../lib/pcie/rtl/dma_if_mux_rd.v")
|
||||
srcs.append("../lib/pcie/rtl/dma_if_mux_wr.v")
|
||||
srcs.append("../lib/pcie/rtl/dma_psdpram.v")
|
||||
srcs.append("../lib/pcie/rtl/dma_client_axis_sink.v")
|
||||
srcs.append("../lib/pcie/rtl/dma_client_axis_source.v")
|
||||
srcs.append("../lib/pcie/rtl/pcie_us_cfg.v")
|
||||
srcs.append("../lib/pcie/rtl/pcie_us_msi.v")
|
||||
srcs.append("../lib/pcie/rtl/pcie_tag_manager.v")
|
||||
srcs.append("../lib/pcie/rtl/pulse_merge.v")
|
||||
srcs.append("%s.v" % testbench)
|
||||
|
||||
src = ' '.join(srcs)
|
||||
|
||||
build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
|
||||
|
||||
def frame_checksum(frame):
|
||||
data = frame[14:]
|
||||
|
||||
csum = 0
|
||||
odd = False
|
||||
|
||||
for b in data:
|
||||
if odd:
|
||||
csum += b
|
||||
else:
|
||||
csum += b << 8
|
||||
odd = not odd
|
||||
|
||||
csum = (csum & 0xffff) + (csum >> 16)
|
||||
csum = (csum & 0xffff) + (csum >> 16)
|
||||
|
||||
return csum
|
||||
|
||||
def bench():
|
||||
|
||||
# Parameters
|
||||
AXIS_PCIE_DATA_WIDTH = 512
|
||||
AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32)
|
||||
AXIS_PCIE_RC_USER_WIDTH = 161
|
||||
AXIS_PCIE_RQ_USER_WIDTH = 137
|
||||
AXIS_PCIE_CQ_USER_WIDTH = 183
|
||||
AXIS_PCIE_CC_USER_WIDTH = 81
|
||||
RQ_SEQ_NUM_WIDTH = 6
|
||||
BAR0_APERTURE = 24
|
||||
|
||||
# Inputs
|
||||
clk = Signal(bool(0))
|
||||
rst = Signal(bool(0))
|
||||
current_test = Signal(intbv(0)[8:])
|
||||
|
||||
clk_250mhz = Signal(bool(0))
|
||||
rst_250mhz = Signal(bool(0))
|
||||
m_axis_rq_tready = Signal(bool(0))
|
||||
s_axis_rc_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
|
||||
s_axis_rc_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
|
||||
s_axis_rc_tlast = Signal(bool(0))
|
||||
s_axis_rc_tuser = Signal(intbv(0)[AXIS_PCIE_RC_USER_WIDTH:])
|
||||
s_axis_rc_tvalid = Signal(bool(0))
|
||||
s_axis_cq_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
|
||||
s_axis_cq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
|
||||
s_axis_cq_tlast = Signal(bool(0))
|
||||
s_axis_cq_tuser = Signal(intbv(0)[AXIS_PCIE_CQ_USER_WIDTH:])
|
||||
s_axis_cq_tvalid = Signal(bool(0))
|
||||
m_axis_cc_tready = Signal(bool(0))
|
||||
s_axis_rq_seq_num_0 = Signal(intbv(0)[RQ_SEQ_NUM_WIDTH:])
|
||||
s_axis_rq_seq_num_valid_0 = Signal(bool(0))
|
||||
s_axis_rq_seq_num_1 = Signal(intbv(0)[RQ_SEQ_NUM_WIDTH:])
|
||||
s_axis_rq_seq_num_valid_1 = Signal(bool(0))
|
||||
pcie_tfc_nph_av = Signal(intbv(15)[4:])
|
||||
pcie_tfc_npd_av = Signal(intbv(15)[4:])
|
||||
cfg_max_payload = Signal(intbv(0)[2:])
|
||||
cfg_max_read_req = Signal(intbv(0)[3:])
|
||||
cfg_mgmt_read_data = Signal(intbv(0)[32:])
|
||||
cfg_mgmt_read_write_done = Signal(bool(0))
|
||||
cfg_fc_ph = Signal(intbv(0)[8:])
|
||||
cfg_fc_pd = Signal(intbv(0)[12:])
|
||||
cfg_fc_nph = Signal(intbv(0)[8:])
|
||||
cfg_fc_npd = Signal(intbv(0)[12:])
|
||||
cfg_fc_cplh = Signal(intbv(0)[8:])
|
||||
cfg_fc_cpld = Signal(intbv(0)[12:])
|
||||
cfg_interrupt_msi_enable = Signal(intbv(0)[4:])
|
||||
cfg_interrupt_msi_mmenable = Signal(intbv(0)[12:])
|
||||
cfg_interrupt_msi_mask_update = Signal(bool(0))
|
||||
cfg_interrupt_msi_data = Signal(intbv(0)[32:])
|
||||
cfg_interrupt_msi_sent = Signal(bool(0))
|
||||
cfg_interrupt_msi_fail = Signal(bool(0))
|
||||
qsfp0_tx_clk_1 = Signal(bool(0))
|
||||
qsfp0_tx_rst_1 = Signal(bool(0))
|
||||
qsfp0_rx_clk_1 = Signal(bool(0))
|
||||
qsfp0_rx_rst_1 = Signal(bool(0))
|
||||
qsfp0_rxd_1 = Signal(intbv(0)[64:])
|
||||
qsfp0_rxc_1 = Signal(intbv(0)[8:])
|
||||
qsfp0_tx_clk_2 = Signal(bool(0))
|
||||
qsfp0_tx_rst_2 = Signal(bool(0))
|
||||
qsfp0_rx_clk_2 = Signal(bool(0))
|
||||
qsfp0_rx_rst_2 = Signal(bool(0))
|
||||
qsfp0_rxd_2 = Signal(intbv(0)[64:])
|
||||
qsfp0_rxc_2 = Signal(intbv(0)[8:])
|
||||
qsfp0_tx_clk_3 = Signal(bool(0))
|
||||
qsfp0_tx_rst_3 = Signal(bool(0))
|
||||
qsfp0_rx_clk_3 = Signal(bool(0))
|
||||
qsfp0_rx_rst_3 = Signal(bool(0))
|
||||
qsfp0_rxd_3 = Signal(intbv(0)[64:])
|
||||
qsfp0_rxc_3 = Signal(intbv(0)[8:])
|
||||
qsfp0_tx_clk_4 = Signal(bool(0))
|
||||
qsfp0_tx_rst_4 = Signal(bool(0))
|
||||
qsfp0_rx_clk_4 = Signal(bool(0))
|
||||
qsfp0_rx_rst_4 = Signal(bool(0))
|
||||
qsfp0_rxd_4 = Signal(intbv(0)[64:])
|
||||
qsfp0_rxc_4 = Signal(intbv(0)[8:])
|
||||
qsfp1_tx_clk_1 = Signal(bool(0))
|
||||
qsfp1_tx_rst_1 = Signal(bool(0))
|
||||
qsfp1_rx_clk_1 = Signal(bool(0))
|
||||
qsfp1_rx_rst_1 = Signal(bool(0))
|
||||
qsfp1_rxd_1 = Signal(intbv(0)[64:])
|
||||
qsfp1_rxc_1 = Signal(intbv(0)[8:])
|
||||
qsfp1_tx_clk_2 = Signal(bool(0))
|
||||
qsfp1_tx_rst_2 = Signal(bool(0))
|
||||
qsfp1_rx_clk_2 = Signal(bool(0))
|
||||
qsfp1_rx_rst_2 = Signal(bool(0))
|
||||
qsfp1_rxd_2 = Signal(intbv(0)[64:])
|
||||
qsfp1_rxc_2 = Signal(intbv(0)[8:])
|
||||
qsfp1_tx_clk_3 = Signal(bool(0))
|
||||
qsfp1_tx_rst_3 = Signal(bool(0))
|
||||
qsfp1_rx_clk_3 = Signal(bool(0))
|
||||
qsfp1_rx_rst_3 = Signal(bool(0))
|
||||
qsfp1_rxd_3 = Signal(intbv(0)[64:])
|
||||
qsfp1_rxc_3 = Signal(intbv(0)[8:])
|
||||
qsfp1_tx_clk_4 = Signal(bool(0))
|
||||
qsfp1_tx_rst_4 = Signal(bool(0))
|
||||
qsfp1_rx_clk_4 = Signal(bool(0))
|
||||
qsfp1_rx_rst_4 = Signal(bool(0))
|
||||
qsfp1_rxd_4 = Signal(intbv(0)[64:])
|
||||
qsfp1_rxc_4 = Signal(intbv(0)[8:])
|
||||
|
||||
# Outputs
|
||||
m_axis_rq_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
|
||||
m_axis_rq_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
|
||||
m_axis_rq_tlast = Signal(bool(0))
|
||||
m_axis_rq_tuser = Signal(intbv(0)[AXIS_PCIE_RQ_USER_WIDTH:])
|
||||
m_axis_rq_tvalid = Signal(bool(0))
|
||||
s_axis_rc_tready = Signal(bool(0))
|
||||
s_axis_cq_tready = Signal(bool(0))
|
||||
m_axis_cc_tdata = Signal(intbv(0)[AXIS_PCIE_DATA_WIDTH:])
|
||||
m_axis_cc_tkeep = Signal(intbv(0)[AXIS_PCIE_KEEP_WIDTH:])
|
||||
m_axis_cc_tlast = Signal(bool(0))
|
||||
m_axis_cc_tuser = Signal(intbv(0)[AXIS_PCIE_CC_USER_WIDTH:])
|
||||
m_axis_cc_tvalid = Signal(bool(0))
|
||||
status_error_cor = Signal(bool(0))
|
||||
status_error_uncor = Signal(bool(0))
|
||||
cfg_mgmt_addr = Signal(intbv(0)[10:])
|
||||
cfg_mgmt_function_number = Signal(intbv(0)[8:])
|
||||
cfg_mgmt_write = Signal(bool(0))
|
||||
cfg_mgmt_write_data = Signal(intbv(0)[32:])
|
||||
cfg_mgmt_byte_enable = Signal(intbv(0)[4:])
|
||||
cfg_mgmt_read = Signal(bool(0))
|
||||
cfg_fc_sel = Signal(intbv(4)[3:])
|
||||
cfg_interrupt_msi_int = Signal(intbv(0)[32:])
|
||||
cfg_interrupt_msi_pending_status = Signal(intbv(0)[32:])
|
||||
cfg_interrupt_msi_select = Signal(intbv(0)[2:])
|
||||
cfg_interrupt_msi_pending_status_function_num = Signal(intbv(0)[2:])
|
||||
cfg_interrupt_msi_pending_status_data_enable = Signal(bool(0))
|
||||
cfg_interrupt_msi_attr = Signal(intbv(0)[3:])
|
||||
cfg_interrupt_msi_tph_present = Signal(bool(0))
|
||||
cfg_interrupt_msi_tph_type = Signal(intbv(0)[2:])
|
||||
cfg_interrupt_msi_tph_st_tag = Signal(intbv(0)[8:])
|
||||
cfg_interrupt_msi_function_number = Signal(intbv(0)[8:])
|
||||
qsfp0_txd_1 = Signal(intbv(0)[64:])
|
||||
qsfp0_txc_1 = Signal(intbv(0)[8:])
|
||||
qsfp0_txd_2 = Signal(intbv(0)[64:])
|
||||
qsfp0_txc_2 = Signal(intbv(0)[8:])
|
||||
qsfp0_txd_3 = Signal(intbv(0)[64:])
|
||||
qsfp0_txc_3 = Signal(intbv(0)[8:])
|
||||
qsfp0_txd_4 = Signal(intbv(0)[64:])
|
||||
qsfp0_txc_4 = Signal(intbv(0)[8:])
|
||||
qsfp1_txd_1 = Signal(intbv(0)[64:])
|
||||
qsfp1_txc_1 = Signal(intbv(0)[8:])
|
||||
qsfp1_txd_2 = Signal(intbv(0)[64:])
|
||||
qsfp1_txc_2 = Signal(intbv(0)[8:])
|
||||
qsfp1_txd_3 = Signal(intbv(0)[64:])
|
||||
qsfp1_txc_3 = Signal(intbv(0)[8:])
|
||||
qsfp1_txd_4 = Signal(intbv(0)[64:])
|
||||
qsfp1_txc_4 = Signal(intbv(0)[8:])
|
||||
|
||||
# sources and sinks
|
||||
qsfp0_1_source = xgmii_ep.XGMIISource()
|
||||
qsfp0_1_source_logic = qsfp0_1_source.create_logic(qsfp0_rx_clk_1, qsfp0_rx_rst_1, txd=qsfp0_rxd_1, txc=qsfp0_rxc_1, name='qsfp0_1_source')
|
||||
|
||||
qsfp0_1_sink = xgmii_ep.XGMIISink()
|
||||
qsfp0_1_sink_logic = qsfp0_1_sink.create_logic(qsfp0_tx_clk_1, qsfp0_tx_rst_1, rxd=qsfp0_txd_1, rxc=qsfp0_txc_1, name='qsfp0_1_sink')
|
||||
|
||||
qsfp0_2_source = xgmii_ep.XGMIISource()
|
||||
qsfp0_2_source_logic = qsfp0_2_source.create_logic(qsfp0_rx_clk_2, qsfp0_rx_rst_2, txd=qsfp0_rxd_2, txc=qsfp0_rxc_2, name='qsfp0_2_source')
|
||||
|
||||
qsfp0_2_sink = xgmii_ep.XGMIISink()
|
||||
qsfp0_2_sink_logic = qsfp0_2_sink.create_logic(qsfp0_tx_clk_2, qsfp0_tx_rst_2, rxd=qsfp0_txd_2, rxc=qsfp0_txc_2, name='qsfp0_2_sink')
|
||||
|
||||
qsfp0_3_source = xgmii_ep.XGMIISource()
|
||||
qsfp0_3_source_logic = qsfp0_3_source.create_logic(qsfp0_rx_clk_3, qsfp0_rx_rst_3, txd=qsfp0_rxd_3, txc=qsfp0_rxc_3, name='qsfp0_3_source')
|
||||
|
||||
qsfp0_3_sink = xgmii_ep.XGMIISink()
|
||||
qsfp0_3_sink_logic = qsfp0_3_sink.create_logic(qsfp0_tx_clk_3, qsfp0_tx_rst_3, rxd=qsfp0_txd_3, rxc=qsfp0_txc_3, name='qsfp0_3_sink')
|
||||
|
||||
qsfp0_4_source = xgmii_ep.XGMIISource()
|
||||
qsfp0_4_source_logic = qsfp0_4_source.create_logic(qsfp0_rx_clk_4, qsfp0_rx_rst_4, txd=qsfp0_rxd_4, txc=qsfp0_rxc_4, name='qsfp0_4_source')
|
||||
|
||||
qsfp0_4_sink = xgmii_ep.XGMIISink()
|
||||
qsfp0_4_sink_logic = qsfp0_4_sink.create_logic(qsfp0_tx_clk_4, qsfp0_tx_rst_4, rxd=qsfp0_txd_4, rxc=qsfp0_txc_4, name='qsfp0_4_sink')
|
||||
|
||||
qsfp1_1_source = xgmii_ep.XGMIISource()
|
||||
qsfp1_1_source_logic = qsfp1_1_source.create_logic(qsfp1_rx_clk_1, qsfp1_rx_rst_1, txd=qsfp1_rxd_1, txc=qsfp1_rxc_1, name='qsfp1_1_source')
|
||||
|
||||
qsfp1_1_sink = xgmii_ep.XGMIISink()
|
||||
qsfp1_1_sink_logic = qsfp1_1_sink.create_logic(qsfp1_tx_clk_1, qsfp1_tx_rst_1, rxd=qsfp1_txd_1, rxc=qsfp1_txc_1, name='qsfp1_1_sink')
|
||||
|
||||
qsfp1_2_source = xgmii_ep.XGMIISource()
|
||||
qsfp1_2_source_logic = qsfp1_2_source.create_logic(qsfp1_rx_clk_2, qsfp1_rx_rst_2, txd=qsfp1_rxd_2, txc=qsfp1_rxc_2, name='qsfp1_2_source')
|
||||
|
||||
qsfp1_2_sink = xgmii_ep.XGMIISink()
|
||||
qsfp1_2_sink_logic = qsfp1_2_sink.create_logic(qsfp1_tx_clk_2, qsfp1_tx_rst_2, rxd=qsfp1_txd_2, rxc=qsfp1_txc_2, name='qsfp1_2_sink')
|
||||
|
||||
qsfp1_3_source = xgmii_ep.XGMIISource()
|
||||
qsfp1_3_source_logic = qsfp1_3_source.create_logic(qsfp1_rx_clk_3, qsfp1_rx_rst_3, txd=qsfp1_rxd_3, txc=qsfp1_rxc_3, name='qsfp1_3_source')
|
||||
|
||||
qsfp1_3_sink = xgmii_ep.XGMIISink()
|
||||
qsfp1_3_sink_logic = qsfp1_3_sink.create_logic(qsfp1_tx_clk_3, qsfp1_tx_rst_3, rxd=qsfp1_txd_3, rxc=qsfp1_txc_3, name='qsfp1_3_sink')
|
||||
|
||||
qsfp1_4_source = xgmii_ep.XGMIISource()
|
||||
qsfp1_4_source_logic = qsfp1_4_source.create_logic(qsfp1_rx_clk_4, qsfp1_rx_rst_4, txd=qsfp1_rxd_4, txc=qsfp1_rxc_4, name='qsfp1_4_source')
|
||||
|
||||
qsfp1_4_sink = xgmii_ep.XGMIISink()
|
||||
qsfp1_4_sink_logic = qsfp1_4_sink.create_logic(qsfp1_tx_clk_4, qsfp1_tx_rst_4, rxd=qsfp1_txd_4, rxc=qsfp1_txc_4, name='qsfp1_4_sink')
|
||||
|
||||
# Clock and Reset Interface
|
||||
user_clk=Signal(bool(0))
|
||||
user_reset=Signal(bool(0))
|
||||
sys_clk=Signal(bool(0))
|
||||
sys_reset=Signal(bool(0))
|
||||
|
||||
# PCIe devices
|
||||
rc = pcie.RootComplex()
|
||||
|
||||
rc.max_payload_size = 0x1 # 256 bytes
|
||||
rc.max_read_request_size = 0x5 # 4096 bytes
|
||||
|
||||
driver = mqnic.Driver(rc)
|
||||
|
||||
dev = pcie_usp.UltrascalePlusPCIe()
|
||||
|
||||
dev.pcie_generation = 3
|
||||
dev.pcie_link_width = 16
|
||||
dev.user_clock_frequency = 250e6
|
||||
|
||||
dev.functions[0].msi_multiple_message_capable = 5
|
||||
|
||||
dev.functions[0].configure_bar(0, 2**BAR0_APERTURE)
|
||||
|
||||
rc.make_port().connect(dev)
|
||||
|
||||
cq_pause = Signal(bool(0))
|
||||
cc_pause = Signal(bool(0))
|
||||
rq_pause = Signal(bool(0))
|
||||
rc_pause = Signal(bool(0))
|
||||
|
||||
pcie_logic = dev.create_logic(
|
||||
# Completer reQuest Interface
|
||||
m_axis_cq_tdata=s_axis_cq_tdata,
|
||||
m_axis_cq_tuser=s_axis_cq_tuser,
|
||||
m_axis_cq_tlast=s_axis_cq_tlast,
|
||||
m_axis_cq_tkeep=s_axis_cq_tkeep,
|
||||
m_axis_cq_tvalid=s_axis_cq_tvalid,
|
||||
m_axis_cq_tready=s_axis_cq_tready,
|
||||
#pcie_cq_np_req=pcie_cq_np_req,
|
||||
pcie_cq_np_req=Signal(intbv(3)[2:]),
|
||||
#pcie_cq_np_req_count=pcie_cq_np_req_count,
|
||||
|
||||
# Completer Completion Interface
|
||||
s_axis_cc_tdata=m_axis_cc_tdata,
|
||||
s_axis_cc_tuser=m_axis_cc_tuser,
|
||||
s_axis_cc_tlast=m_axis_cc_tlast,
|
||||
s_axis_cc_tkeep=m_axis_cc_tkeep,
|
||||
s_axis_cc_tvalid=m_axis_cc_tvalid,
|
||||
s_axis_cc_tready=m_axis_cc_tready,
|
||||
|
||||
# Requester reQuest Interface
|
||||
s_axis_rq_tdata=m_axis_rq_tdata,
|
||||
s_axis_rq_tuser=m_axis_rq_tuser,
|
||||
s_axis_rq_tlast=m_axis_rq_tlast,
|
||||
s_axis_rq_tkeep=m_axis_rq_tkeep,
|
||||
s_axis_rq_tvalid=m_axis_rq_tvalid,
|
||||
s_axis_rq_tready=m_axis_rq_tready,
|
||||
pcie_rq_seq_num0=s_axis_rq_seq_num_0,
|
||||
pcie_rq_seq_num_vld0=s_axis_rq_seq_num_valid_0,
|
||||
pcie_rq_seq_num1=s_axis_rq_seq_num_1,
|
||||
pcie_rq_seq_num_vld1=s_axis_rq_seq_num_valid_1,
|
||||
#pcie_rq_tag0=pcie_rq_tag0,
|
||||
#pcie_rq_tag1=pcie_rq_tag1,
|
||||
#pcie_rq_tag_av=pcie_rq_tag_av,
|
||||
#pcie_rq_tag_vld0=pcie_rq_tag_vld0,
|
||||
#pcie_rq_tag_vld1=pcie_rq_tag_vld1,
|
||||
|
||||
# Requester Completion Interface
|
||||
m_axis_rc_tdata=s_axis_rc_tdata,
|
||||
m_axis_rc_tuser=s_axis_rc_tuser,
|
||||
m_axis_rc_tlast=s_axis_rc_tlast,
|
||||
m_axis_rc_tkeep=s_axis_rc_tkeep,
|
||||
m_axis_rc_tvalid=s_axis_rc_tvalid,
|
||||
m_axis_rc_tready=s_axis_rc_tready,
|
||||
|
||||
# Transmit Flow Control Interface
|
||||
#pcie_tfc_nph_av=pcie_tfc_nph_av,
|
||||
#pcie_tfc_npd_av=pcie_tfc_npd_av,
|
||||
|
||||
# Configuration Management Interface
|
||||
cfg_mgmt_addr=cfg_mgmt_addr,
|
||||
cfg_mgmt_function_number=cfg_mgmt_function_number,
|
||||
cfg_mgmt_write=cfg_mgmt_write,
|
||||
cfg_mgmt_write_data=cfg_mgmt_write_data,
|
||||
cfg_mgmt_byte_enable=cfg_mgmt_byte_enable,
|
||||
cfg_mgmt_read=cfg_mgmt_read,
|
||||
cfg_mgmt_read_data=cfg_mgmt_read_data,
|
||||
cfg_mgmt_read_write_done=cfg_mgmt_read_write_done,
|
||||
#cfg_mgmt_debug_access=cfg_mgmt_debug_access,
|
||||
|
||||
# Configuration Status Interface
|
||||
#cfg_phy_link_down=cfg_phy_link_down,
|
||||
#cfg_phy_link_status=cfg_phy_link_status,
|
||||
#cfg_negotiated_width=cfg_negotiated_width,
|
||||
#cfg_current_speed=cfg_current_speed,
|
||||
cfg_max_payload=cfg_max_payload,
|
||||
cfg_max_read_req=cfg_max_read_req,
|
||||
#cfg_function_status=cfg_function_status,
|
||||
#cfg_vf_status=cfg_vf_status,
|
||||
#cfg_function_power_state=cfg_function_power_state,
|
||||
#cfg_vf_power_state=cfg_vf_power_state,
|
||||
#cfg_link_power_state=cfg_link_power_state,
|
||||
#cfg_err_cor_out=cfg_err_cor_out,
|
||||
#cfg_err_nonfatal_out=cfg_err_nonfatal_out,
|
||||
#cfg_err_fatal_out=cfg_err_fatal_out,
|
||||
#cfg_local_err_out=cfg_local_err_out,
|
||||
#cfg_local_err_valid=cfg_local_err_valid,
|
||||
#cfg_rx_pm_state=cfg_rx_pm_state,
|
||||
#cfg_tx_pm_state=cfg_tx_pm_state,
|
||||
#cfg_ltssm_state=cfg_ltssm_state,
|
||||
#cfg_rcb_status=cfg_rcb_status,
|
||||
#cfg_obff_enable=cfg_obff_enable,
|
||||
#cfg_pl_status_change=cfg_pl_status_change,
|
||||
#cfg_tph_requester_enable=cfg_tph_requester_enable,
|
||||
#cfg_tph_st_mode=cfg_tph_st_mode,
|
||||
#cfg_vf_tph_requester_enable=cfg_vf_tph_requester_enable,
|
||||
#cfg_vf_tph_st_mode=cfg_vf_tph_st_mode,
|
||||
|
||||
# Configuration Received Message Interface
|
||||
#cfg_msg_received=cfg_msg_received,
|
||||
#cfg_msg_received_data=cfg_msg_received_data,
|
||||
#cfg_msg_received_type=cfg_msg_received_type,
|
||||
|
||||
# Configuration Transmit Message Interface
|
||||
#cfg_msg_transmit=cfg_msg_transmit,
|
||||
#cfg_msg_transmit_type=cfg_msg_transmit_type,
|
||||
#cfg_msg_transmit_data=cfg_msg_transmit_data,
|
||||
#cfg_msg_transmit_done=cfg_msg_transmit_done,
|
||||
|
||||
# Configuration Flow Control Interface
|
||||
cfg_fc_ph=cfg_fc_ph,
|
||||
cfg_fc_pd=cfg_fc_pd,
|
||||
cfg_fc_nph=cfg_fc_nph,
|
||||
cfg_fc_npd=cfg_fc_npd,
|
||||
cfg_fc_cplh=cfg_fc_cplh,
|
||||
cfg_fc_cpld=cfg_fc_cpld,
|
||||
cfg_fc_sel=cfg_fc_sel,
|
||||
|
||||
# Configuration Control Interface
|
||||
#cfg_hot_reset_in=cfg_hot_reset_in,
|
||||
#cfg_hot_reset_out=cfg_hot_reset_out,
|
||||
#cfg_config_space_enable=cfg_config_space_enable,
|
||||
#cfg_dsn=cfg_dsn,
|
||||
#cfg_ds_port_number=cfg_ds_port_number,
|
||||
#cfg_ds_bus_number=cfg_ds_bus_number,
|
||||
#cfg_ds_device_number=cfg_ds_device_number,
|
||||
#cfg_ds_function_number=cfg_ds_function_number,
|
||||
#cfg_power_state_change_ack=cfg_power_state_change_ack,
|
||||
#cfg_power_state_change_interrupt=cfg_power_state_change_interrupt,
|
||||
cfg_err_cor_in=status_error_cor,
|
||||
cfg_err_uncor_in=status_error_uncor,
|
||||
#cfg_flr_done=cfg_flr_done,
|
||||
#cfg_vf_flr_done=cfg_vf_flr_done,
|
||||
#cfg_flr_in_process=cfg_flr_in_process,
|
||||
#cfg_vf_flr_in_process=cfg_vf_flr_in_process,
|
||||
#cfg_req_pm_transition_l23_ready=cfg_req_pm_transition_l23_ready,
|
||||
#cfg_link_training_enable=cfg_link_training_enable,
|
||||
|
||||
# Configuration Interrupt Controller Interface
|
||||
#cfg_interrupt_int=cfg_interrupt_int,
|
||||
#cfg_interrupt_sent=cfg_interrupt_sent,
|
||||
#cfg_interrupt_pending=cfg_interrupt_pending,
|
||||
cfg_interrupt_msi_enable=cfg_interrupt_msi_enable,
|
||||
cfg_interrupt_msi_mmenable=cfg_interrupt_msi_mmenable,
|
||||
cfg_interrupt_msi_mask_update=cfg_interrupt_msi_mask_update,
|
||||
cfg_interrupt_msi_data=cfg_interrupt_msi_data,
|
||||
cfg_interrupt_msi_select=cfg_interrupt_msi_select,
|
||||
cfg_interrupt_msi_int=cfg_interrupt_msi_int,
|
||||
cfg_interrupt_msi_pending_status=cfg_interrupt_msi_pending_status,
|
||||
cfg_interrupt_msi_pending_status_data_enable=cfg_interrupt_msi_pending_status_data_enable,
|
||||
cfg_interrupt_msi_pending_status_function_num=cfg_interrupt_msi_pending_status_function_num,
|
||||
cfg_interrupt_msi_sent=cfg_interrupt_msi_sent,
|
||||
cfg_interrupt_msi_fail=cfg_interrupt_msi_fail,
|
||||
#cfg_interrupt_msix_enable=cfg_interrupt_msix_enable,
|
||||
#cfg_interrupt_msix_mask=cfg_interrupt_msix_mask,
|
||||
#cfg_interrupt_msix_vf_enable=cfg_interrupt_msix_vf_enable,
|
||||
#cfg_interrupt_msix_vf_mask=cfg_interrupt_msix_vf_mask,
|
||||
#cfg_interrupt_msix_address=cfg_interrupt_msix_address,
|
||||
#cfg_interrupt_msix_data=cfg_interrupt_msix_data,
|
||||
#cfg_interrupt_msix_int=cfg_interrupt_msix_int,
|
||||
#cfg_interrupt_msix_vec_pending=cfg_interrupt_msix_vec_pending,
|
||||
#cfg_interrupt_msix_vec_pending_status=cfg_interrupt_msix_vec_pending_status,
|
||||
cfg_interrupt_msi_attr=cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=cfg_interrupt_msi_tph_type,
|
||||
cfg_interrupt_msi_tph_st_tag=cfg_interrupt_msi_tph_st_tag,
|
||||
cfg_interrupt_msi_function_number=cfg_interrupt_msi_function_number,
|
||||
|
||||
# Configuration Extend Interface
|
||||
#cfg_ext_read_received=cfg_ext_read_received,
|
||||
#cfg_ext_write_received=cfg_ext_write_received,
|
||||
#cfg_ext_register_number=cfg_ext_register_number,
|
||||
#cfg_ext_function_number=cfg_ext_function_number,
|
||||
#cfg_ext_write_data=cfg_ext_write_data,
|
||||
#cfg_ext_write_byte_enable=cfg_ext_write_byte_enable,
|
||||
#cfg_ext_read_data=cfg_ext_read_data,
|
||||
#cfg_ext_read_data_valid=cfg_ext_read_data_valid,
|
||||
|
||||
# Clock and Reset Interface
|
||||
user_clk=user_clk,
|
||||
user_reset=user_reset,
|
||||
sys_clk=sys_clk,
|
||||
sys_clk_gt=sys_clk,
|
||||
sys_reset=sys_reset,
|
||||
#phy_rdy_out=phy_rdy_out,
|
||||
|
||||
cq_pause=cq_pause,
|
||||
cc_pause=cc_pause,
|
||||
rq_pause=rq_pause,
|
||||
rc_pause=rc_pause
|
||||
)
|
||||
|
||||
# DUT
|
||||
if os.system(build_cmd):
|
||||
raise Exception("Error running build command")
|
||||
|
||||
dut = Cosimulation(
|
||||
"vvp -m myhdl %s.vvp -lxt2" % testbench,
|
||||
clk=clk,
|
||||
rst=rst,
|
||||
current_test=current_test,
|
||||
clk_250mhz=user_clk,
|
||||
rst_250mhz=user_reset,
|
||||
m_axis_rq_tdata=m_axis_rq_tdata,
|
||||
m_axis_rq_tkeep=m_axis_rq_tkeep,
|
||||
m_axis_rq_tlast=m_axis_rq_tlast,
|
||||
m_axis_rq_tready=m_axis_rq_tready,
|
||||
m_axis_rq_tuser=m_axis_rq_tuser,
|
||||
m_axis_rq_tvalid=m_axis_rq_tvalid,
|
||||
s_axis_rc_tdata=s_axis_rc_tdata,
|
||||
s_axis_rc_tkeep=s_axis_rc_tkeep,
|
||||
s_axis_rc_tlast=s_axis_rc_tlast,
|
||||
s_axis_rc_tready=s_axis_rc_tready,
|
||||
s_axis_rc_tuser=s_axis_rc_tuser,
|
||||
s_axis_rc_tvalid=s_axis_rc_tvalid,
|
||||
s_axis_cq_tdata=s_axis_cq_tdata,
|
||||
s_axis_cq_tkeep=s_axis_cq_tkeep,
|
||||
s_axis_cq_tlast=s_axis_cq_tlast,
|
||||
s_axis_cq_tready=s_axis_cq_tready,
|
||||
s_axis_cq_tuser=s_axis_cq_tuser,
|
||||
s_axis_cq_tvalid=s_axis_cq_tvalid,
|
||||
m_axis_cc_tdata=m_axis_cc_tdata,
|
||||
m_axis_cc_tkeep=m_axis_cc_tkeep,
|
||||
m_axis_cc_tlast=m_axis_cc_tlast,
|
||||
m_axis_cc_tready=m_axis_cc_tready,
|
||||
m_axis_cc_tuser=m_axis_cc_tuser,
|
||||
m_axis_cc_tvalid=m_axis_cc_tvalid,
|
||||
s_axis_rq_seq_num_0=s_axis_rq_seq_num_0,
|
||||
s_axis_rq_seq_num_valid_0=s_axis_rq_seq_num_valid_0,
|
||||
s_axis_rq_seq_num_1=s_axis_rq_seq_num_1,
|
||||
s_axis_rq_seq_num_valid_1=s_axis_rq_seq_num_valid_1,
|
||||
pcie_tfc_nph_av=pcie_tfc_nph_av,
|
||||
pcie_tfc_npd_av=pcie_tfc_npd_av,
|
||||
cfg_max_payload=cfg_max_payload,
|
||||
cfg_max_read_req=cfg_max_read_req,
|
||||
cfg_mgmt_addr=cfg_mgmt_addr,
|
||||
cfg_mgmt_function_number=cfg_mgmt_function_number,
|
||||
cfg_mgmt_write=cfg_mgmt_write,
|
||||
cfg_mgmt_write_data=cfg_mgmt_write_data,
|
||||
cfg_mgmt_byte_enable=cfg_mgmt_byte_enable,
|
||||
cfg_mgmt_read=cfg_mgmt_read,
|
||||
cfg_mgmt_read_data=cfg_mgmt_read_data,
|
||||
cfg_mgmt_read_write_done=cfg_mgmt_read_write_done,
|
||||
cfg_fc_ph=cfg_fc_ph,
|
||||
cfg_fc_pd=cfg_fc_pd,
|
||||
cfg_fc_nph=cfg_fc_nph,
|
||||
cfg_fc_npd=cfg_fc_npd,
|
||||
cfg_fc_cplh=cfg_fc_cplh,
|
||||
cfg_fc_cpld=cfg_fc_cpld,
|
||||
cfg_fc_sel=cfg_fc_sel,
|
||||
cfg_interrupt_msi_enable=cfg_interrupt_msi_enable,
|
||||
cfg_interrupt_msi_int=cfg_interrupt_msi_int,
|
||||
cfg_interrupt_msi_sent=cfg_interrupt_msi_sent,
|
||||
cfg_interrupt_msi_fail=cfg_interrupt_msi_fail,
|
||||
cfg_interrupt_msi_mmenable=cfg_interrupt_msi_mmenable,
|
||||
cfg_interrupt_msi_pending_status=cfg_interrupt_msi_pending_status,
|
||||
cfg_interrupt_msi_mask_update=cfg_interrupt_msi_mask_update,
|
||||
cfg_interrupt_msi_select=cfg_interrupt_msi_select,
|
||||
cfg_interrupt_msi_data=cfg_interrupt_msi_data,
|
||||
cfg_interrupt_msi_pending_status_function_num=cfg_interrupt_msi_pending_status_function_num,
|
||||
cfg_interrupt_msi_pending_status_data_enable=cfg_interrupt_msi_pending_status_data_enable,
|
||||
cfg_interrupt_msi_attr=cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present=cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type=cfg_interrupt_msi_tph_type,
|
||||
cfg_interrupt_msi_tph_st_tag=cfg_interrupt_msi_tph_st_tag,
|
||||
cfg_interrupt_msi_function_number=cfg_interrupt_msi_function_number,
|
||||
status_error_cor=status_error_cor,
|
||||
status_error_uncor=status_error_uncor,
|
||||
qsfp0_tx_clk_1=qsfp0_tx_clk_1,
|
||||
qsfp0_tx_rst_1=qsfp0_tx_rst_1,
|
||||
qsfp0_txd_1=qsfp0_txd_1,
|
||||
qsfp0_txc_1=qsfp0_txc_1,
|
||||
qsfp0_rx_clk_1=qsfp0_rx_clk_1,
|
||||
qsfp0_rx_rst_1=qsfp0_rx_rst_1,
|
||||
qsfp0_rxd_1=qsfp0_rxd_1,
|
||||
qsfp0_rxc_1=qsfp0_rxc_1,
|
||||
qsfp0_tx_clk_2=qsfp0_tx_clk_2,
|
||||
qsfp0_tx_rst_2=qsfp0_tx_rst_2,
|
||||
qsfp0_txd_2=qsfp0_txd_2,
|
||||
qsfp0_txc_2=qsfp0_txc_2,
|
||||
qsfp0_rx_clk_2=qsfp0_rx_clk_2,
|
||||
qsfp0_rx_rst_2=qsfp0_rx_rst_2,
|
||||
qsfp0_rxd_2=qsfp0_rxd_2,
|
||||
qsfp0_rxc_2=qsfp0_rxc_2,
|
||||
qsfp0_tx_clk_3=qsfp0_tx_clk_3,
|
||||
qsfp0_tx_rst_3=qsfp0_tx_rst_3,
|
||||
qsfp0_txd_3=qsfp0_txd_3,
|
||||
qsfp0_txc_3=qsfp0_txc_3,
|
||||
qsfp0_rx_clk_3=qsfp0_rx_clk_3,
|
||||
qsfp0_rx_rst_3=qsfp0_rx_rst_3,
|
||||
qsfp0_rxd_3=qsfp0_rxd_3,
|
||||
qsfp0_rxc_3=qsfp0_rxc_3,
|
||||
qsfp0_tx_clk_4=qsfp0_tx_clk_4,
|
||||
qsfp0_tx_rst_4=qsfp0_tx_rst_4,
|
||||
qsfp0_txd_4=qsfp0_txd_4,
|
||||
qsfp0_txc_4=qsfp0_txc_4,
|
||||
qsfp0_rx_clk_4=qsfp0_rx_clk_4,
|
||||
qsfp0_rx_rst_4=qsfp0_rx_rst_4,
|
||||
qsfp0_rxd_4=qsfp0_rxd_4,
|
||||
qsfp0_rxc_4=qsfp0_rxc_4,
|
||||
qsfp1_tx_clk_1=qsfp1_tx_clk_1,
|
||||
qsfp1_tx_rst_1=qsfp1_tx_rst_1,
|
||||
qsfp1_txd_1=qsfp1_txd_1,
|
||||
qsfp1_txc_1=qsfp1_txc_1,
|
||||
qsfp1_rx_clk_1=qsfp1_rx_clk_1,
|
||||
qsfp1_rx_rst_1=qsfp1_rx_rst_1,
|
||||
qsfp1_rxd_1=qsfp1_rxd_1,
|
||||
qsfp1_rxc_1=qsfp1_rxc_1,
|
||||
qsfp1_tx_clk_2=qsfp1_tx_clk_2,
|
||||
qsfp1_tx_rst_2=qsfp1_tx_rst_2,
|
||||
qsfp1_txd_2=qsfp1_txd_2,
|
||||
qsfp1_txc_2=qsfp1_txc_2,
|
||||
qsfp1_rx_clk_2=qsfp1_rx_clk_2,
|
||||
qsfp1_rx_rst_2=qsfp1_rx_rst_2,
|
||||
qsfp1_rxd_2=qsfp1_rxd_2,
|
||||
qsfp1_rxc_2=qsfp1_rxc_2,
|
||||
qsfp1_tx_clk_3=qsfp1_tx_clk_3,
|
||||
qsfp1_tx_rst_3=qsfp1_tx_rst_3,
|
||||
qsfp1_txd_3=qsfp1_txd_3,
|
||||
qsfp1_txc_3=qsfp1_txc_3,
|
||||
qsfp1_rx_clk_3=qsfp1_rx_clk_3,
|
||||
qsfp1_rx_rst_3=qsfp1_rx_rst_3,
|
||||
qsfp1_rxd_3=qsfp1_rxd_3,
|
||||
qsfp1_rxc_3=qsfp1_rxc_3,
|
||||
qsfp1_tx_clk_4=qsfp1_tx_clk_4,
|
||||
qsfp1_tx_rst_4=qsfp1_tx_rst_4,
|
||||
qsfp1_txd_4=qsfp1_txd_4,
|
||||
qsfp1_txc_4=qsfp1_txc_4,
|
||||
qsfp1_rx_clk_4=qsfp1_rx_clk_4,
|
||||
qsfp1_rx_rst_4=qsfp1_rx_rst_4,
|
||||
qsfp1_rxd_4=qsfp1_rxd_4,
|
||||
qsfp1_rxc_4=qsfp1_rxc_4
|
||||
)
|
||||
|
||||
@always(delay(5))
|
||||
def clkgen():
|
||||
clk.next = not clk
|
||||
|
||||
@always(delay(3))
|
||||
def qsfp_clkgen():
|
||||
qsfp0_tx_clk_1.next = not qsfp0_tx_clk_1
|
||||
qsfp0_rx_clk_1.next = not qsfp0_rx_clk_1
|
||||
qsfp0_tx_clk_2.next = not qsfp0_tx_clk_2
|
||||
qsfp0_rx_clk_2.next = not qsfp0_rx_clk_2
|
||||
qsfp0_tx_clk_3.next = not qsfp0_tx_clk_3
|
||||
qsfp0_rx_clk_3.next = not qsfp0_rx_clk_3
|
||||
qsfp0_tx_clk_4.next = not qsfp0_tx_clk_4
|
||||
qsfp0_rx_clk_4.next = not qsfp0_rx_clk_4
|
||||
qsfp1_tx_clk_1.next = not qsfp1_tx_clk_1
|
||||
qsfp1_rx_clk_1.next = not qsfp1_rx_clk_1
|
||||
qsfp1_tx_clk_2.next = not qsfp1_tx_clk_2
|
||||
qsfp1_rx_clk_2.next = not qsfp1_rx_clk_2
|
||||
qsfp1_tx_clk_3.next = not qsfp1_tx_clk_3
|
||||
qsfp1_rx_clk_3.next = not qsfp1_rx_clk_3
|
||||
qsfp1_tx_clk_4.next = not qsfp1_tx_clk_4
|
||||
qsfp1_rx_clk_4.next = not qsfp1_rx_clk_4
|
||||
|
||||
@always_comb
|
||||
def clk_logic():
|
||||
sys_clk.next = clk
|
||||
sys_reset.next = not rst
|
||||
|
||||
loopback_enable = Signal(bool(0))
|
||||
|
||||
@instance
|
||||
def loopback():
|
||||
while True:
|
||||
|
||||
yield clk.posedge
|
||||
|
||||
if loopback_enable:
|
||||
if not qsfp0_1_sink.empty():
|
||||
pkt = qsfp0_1_sink.recv()
|
||||
qsfp0_1_source.send(pkt)
|
||||
if not qsfp0_2_sink.empty():
|
||||
pkt = qsfp0_2_sink.recv()
|
||||
qsfp0_2_source.send(pkt)
|
||||
if not qsfp0_3_sink.empty():
|
||||
pkt = qsfp0_3_sink.recv()
|
||||
qsfp0_3_source.send(pkt)
|
||||
if not qsfp0_4_sink.empty():
|
||||
pkt = qsfp0_4_sink.recv()
|
||||
qsfp0_4_source.send(pkt)
|
||||
if not qsfp1_1_sink.empty():
|
||||
pkt = qsfp1_1_sink.recv()
|
||||
qsfp1_1_source.send(pkt)
|
||||
if not qsfp1_2_sink.empty():
|
||||
pkt = qsfp1_2_sink.recv()
|
||||
qsfp1_2_source.send(pkt)
|
||||
if not qsfp1_3_sink.empty():
|
||||
pkt = qsfp1_3_sink.recv()
|
||||
qsfp1_3_source.send(pkt)
|
||||
if not qsfp1_4_sink.empty():
|
||||
pkt = qsfp1_4_sink.recv()
|
||||
qsfp1_4_source.send(pkt)
|
||||
|
||||
@instance
|
||||
def check():
|
||||
yield delay(100)
|
||||
yield clk.posedge
|
||||
rst.next = 1
|
||||
qsfp0_tx_rst_1.next = 1
|
||||
qsfp0_rx_rst_1.next = 1
|
||||
qsfp0_tx_rst_2.next = 1
|
||||
qsfp0_rx_rst_2.next = 1
|
||||
qsfp0_tx_rst_3.next = 1
|
||||
qsfp0_rx_rst_3.next = 1
|
||||
qsfp0_tx_rst_4.next = 1
|
||||
qsfp0_rx_rst_4.next = 1
|
||||
qsfp1_tx_rst_1.next = 1
|
||||
qsfp1_rx_rst_1.next = 1
|
||||
qsfp1_tx_rst_2.next = 1
|
||||
qsfp1_rx_rst_2.next = 1
|
||||
qsfp1_tx_rst_3.next = 1
|
||||
qsfp1_rx_rst_3.next = 1
|
||||
qsfp1_tx_rst_4.next = 1
|
||||
qsfp1_rx_rst_4.next = 1
|
||||
yield clk.posedge
|
||||
yield delay(100)
|
||||
rst.next = 0
|
||||
qsfp0_tx_rst_1.next = 0
|
||||
qsfp0_rx_rst_1.next = 0
|
||||
qsfp0_tx_rst_2.next = 0
|
||||
qsfp0_rx_rst_2.next = 0
|
||||
qsfp0_tx_rst_3.next = 0
|
||||
qsfp0_rx_rst_3.next = 0
|
||||
qsfp0_tx_rst_4.next = 0
|
||||
qsfp0_rx_rst_4.next = 0
|
||||
qsfp1_tx_rst_1.next = 0
|
||||
qsfp1_rx_rst_1.next = 0
|
||||
qsfp1_tx_rst_2.next = 0
|
||||
qsfp1_rx_rst_2.next = 0
|
||||
qsfp1_tx_rst_3.next = 0
|
||||
qsfp1_rx_rst_3.next = 0
|
||||
qsfp1_tx_rst_4.next = 0
|
||||
qsfp1_rx_rst_4.next = 0
|
||||
yield clk.posedge
|
||||
yield delay(100)
|
||||
yield clk.posedge
|
||||
|
||||
# testbench stimulus
|
||||
|
||||
current_tag = 1
|
||||
|
||||
yield clk.posedge
|
||||
print("test 1: enumeration")
|
||||
current_test.next = 1
|
||||
|
||||
yield rc.enumerate(enable_bus_mastering=True, configure_msi=True)
|
||||
|
||||
dev_pf0_bar0 = dev.functions[0].bar[0] & 0xfffffffc
|
||||
dev_pf0_bar1 = dev.functions[0].bar[1] & 0xfffffffc
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 2: init NIC")
|
||||
current_test.next = 2
|
||||
|
||||
#data = yield from rc.mem_read(dev_pf0_bar0+0x20000+0x10, 4);
|
||||
#print(data)
|
||||
|
||||
#yield delay(1000)
|
||||
|
||||
#raise StopSimulation
|
||||
|
||||
yield from driver.init_dev(dev.functions[0].get_id())
|
||||
yield from driver.interfaces[0].open()
|
||||
#yield from driver.interfaces[1].open()
|
||||
|
||||
# enable queues
|
||||
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].hw_addr+mqnic.MQNIC_PORT_REG_SCHED_ENABLE, 0x00000001)
|
||||
for k in range(driver.interfaces[0].tx_queue_count):
|
||||
yield from rc.mem_write_dword(driver.interfaces[0].ports[0].schedulers[0].hw_addr+4*k, 0x00000003)
|
||||
|
||||
yield from rc.mem_read(driver.hw_addr, 4) # wait for all writes to complete
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 3: send and receive a packet")
|
||||
current_test.next = 3
|
||||
|
||||
# test bad packet
|
||||
#qsfp0_1_source.send(b'\x55\x55\x55\x55\x55\xd5'+bytearray(range(128)))
|
||||
|
||||
data = bytearray([x%256 for x in range(1024)])
|
||||
|
||||
yield from driver.interfaces[0].start_xmit(data, 0)
|
||||
|
||||
yield qsfp0_1_sink.wait()
|
||||
|
||||
pkt = qsfp0_1_sink.recv()
|
||||
print(pkt)
|
||||
|
||||
qsfp0_1_source.send(pkt)
|
||||
|
||||
yield driver.interfaces[0].wait()
|
||||
|
||||
pkt = driver.interfaces[0].recv()
|
||||
|
||||
print(pkt)
|
||||
assert frame_checksum(pkt.data) == pkt.rx_checksum
|
||||
|
||||
# yield from driver.interfaces[1].start_xmit(data, 0)
|
||||
|
||||
# yield qsfp0_1_sink.wait()
|
||||
|
||||
# pkt = qsfp0_1_sink.recv()
|
||||
# print(pkt)
|
||||
|
||||
# qsfp0_1_source.send(pkt)
|
||||
|
||||
# yield driver.interfaces[1].wait()
|
||||
|
||||
# pkt = driver.interfaces[1].recv()
|
||||
|
||||
# print(pkt)
|
||||
# assert frame_checksum(pkt.data) == pkt.rx_checksum
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 4: checksum tests")
|
||||
current_test.next = 4
|
||||
|
||||
test_frame = udp_ep.UDPFrame()
|
||||
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
|
||||
test_frame.eth_src_mac = 0x5A5152535455
|
||||
test_frame.eth_type = 0x0800
|
||||
test_frame.ip_version = 4
|
||||
test_frame.ip_ihl = 5
|
||||
test_frame.ip_length = None
|
||||
test_frame.ip_identification = 0
|
||||
test_frame.ip_flags = 2
|
||||
test_frame.ip_fragment_offset = 0
|
||||
test_frame.ip_ttl = 64
|
||||
test_frame.ip_protocol = 0x11
|
||||
test_frame.ip_header_checksum = None
|
||||
test_frame.ip_source_ip = 0xc0a80164
|
||||
test_frame.ip_dest_ip = 0xc0a80165
|
||||
test_frame.udp_source_port = 1
|
||||
test_frame.udp_dest_port = 2
|
||||
test_frame.udp_length = None
|
||||
test_frame.udp_checksum = None
|
||||
test_frame.payload = bytearray((x%256 for x in range(256)))
|
||||
|
||||
test_frame.set_udp_pseudo_header_checksum()
|
||||
|
||||
axis_frame = test_frame.build_axis()
|
||||
|
||||
yield from driver.interfaces[0].start_xmit(axis_frame.data, 0, 34, 6)
|
||||
|
||||
yield qsfp0_1_sink.wait()
|
||||
|
||||
pkt = qsfp0_1_sink.recv()
|
||||
print(pkt)
|
||||
|
||||
qsfp0_1_source.send(pkt)
|
||||
|
||||
yield driver.interfaces[0].wait()
|
||||
|
||||
pkt = driver.interfaces[0].recv()
|
||||
|
||||
print(pkt)
|
||||
|
||||
assert pkt.rx_checksum == frame_checksum(pkt.data)
|
||||
|
||||
check_frame = udp_ep.UDPFrame()
|
||||
check_frame.parse_axis(pkt.data)
|
||||
|
||||
assert check_frame.verify_checksums()
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 5: multiple small packets")
|
||||
current_test.next = 5
|
||||
|
||||
count = 64
|
||||
|
||||
pkts = [bytearray([(x+k)%256 for x in range(64)]) for k in range(count)]
|
||||
|
||||
loopback_enable.next = True
|
||||
|
||||
for p in pkts:
|
||||
yield from driver.interfaces[0].start_xmit(p, 0)
|
||||
|
||||
for k in range(count):
|
||||
pkt = driver.interfaces[0].recv()
|
||||
|
||||
if not pkt:
|
||||
yield driver.interfaces[0].wait()
|
||||
pkt = driver.interfaces[0].recv()
|
||||
|
||||
print(pkt)
|
||||
assert pkt.data == pkts[k]
|
||||
assert frame_checksum(pkt.data) == pkt.rx_checksum
|
||||
|
||||
loopback_enable.next = False
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 6: multiple large packets")
|
||||
current_test.next = 6
|
||||
|
||||
count = 64
|
||||
|
||||
pkts = [bytearray([(x+k)%256 for x in range(1514)]) for k in range(count)]
|
||||
|
||||
loopback_enable.next = True
|
||||
|
||||
for p in pkts:
|
||||
yield from driver.interfaces[0].start_xmit(p, 0)
|
||||
|
||||
for k in range(count):
|
||||
pkt = driver.interfaces[0].recv()
|
||||
|
||||
if not pkt:
|
||||
yield driver.interfaces[0].wait()
|
||||
pkt = driver.interfaces[0].recv()
|
||||
|
||||
print(pkt)
|
||||
assert pkt.data == pkts[k]
|
||||
assert frame_checksum(pkt.data) == pkt.rx_checksum
|
||||
|
||||
loopback_enable.next = False
|
||||
|
||||
yield delay(100)
|
||||
|
||||
raise StopSimulation
|
||||
|
||||
return instances()
|
||||
|
||||
def test_bench():
|
||||
sim = Simulation(bench())
|
||||
sim.run()
|
||||
|
||||
if __name__ == '__main__':
|
||||
print("Running test...")
|
||||
test_bench()
|
||||
486
fpga/mqnic/AU280/fpga_10g/tb/test_fpga_core.v
Normal file
486
fpga/mqnic/AU280/fpga_10g/tb/test_fpga_core.v
Normal file
@ -0,0 +1,486 @@
|
||||
/*
|
||||
|
||||
Copyright 2019, The Regents of the University of California.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
|
||||
IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
|
||||
CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
|
||||
OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
|
||||
IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
|
||||
The views and conclusions contained in the software and documentation are those
|
||||
of the authors and should not be interpreted as representing official policies,
|
||||
either expressed or implied, of The Regents of the University of California.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`timescale 1ns / 1ps
|
||||
|
||||
/*
|
||||
* Testbench for fpga_core
|
||||
*/
|
||||
module test_fpga_core;
|
||||
|
||||
// Parameters
|
||||
parameter AXIS_PCIE_DATA_WIDTH = 512;
|
||||
parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32);
|
||||
parameter AXIS_PCIE_RC_USER_WIDTH = 161;
|
||||
parameter AXIS_PCIE_RQ_USER_WIDTH = 137;
|
||||
parameter AXIS_PCIE_CQ_USER_WIDTH = 183;
|
||||
parameter AXIS_PCIE_CC_USER_WIDTH = 81;
|
||||
parameter RQ_SEQ_NUM_WIDTH = 6;
|
||||
parameter BAR0_APERTURE = 24;
|
||||
|
||||
// Inputs
|
||||
reg clk = 0;
|
||||
reg rst = 0;
|
||||
reg [7:0] current_test = 0;
|
||||
|
||||
reg clk_250mhz = 0;
|
||||
reg rst_250mhz = 0;
|
||||
reg m_axis_rq_tready = 0;
|
||||
reg [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_rc_tdata = 0;
|
||||
reg [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_rc_tkeep = 0;
|
||||
reg s_axis_rc_tlast = 0;
|
||||
reg [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser = 0;
|
||||
reg s_axis_rc_tvalid = 0;
|
||||
reg [AXIS_PCIE_DATA_WIDTH-1:0] s_axis_cq_tdata = 0;
|
||||
reg [AXIS_PCIE_KEEP_WIDTH-1:0] s_axis_cq_tkeep = 0;
|
||||
reg s_axis_cq_tlast = 0;
|
||||
reg [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser = 0;
|
||||
reg s_axis_cq_tvalid = 0;
|
||||
reg m_axis_cc_tready = 0;
|
||||
reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_0 = 0;
|
||||
reg s_axis_rq_seq_num_valid_0 = 0;
|
||||
reg [RQ_SEQ_NUM_WIDTH-1:0] s_axis_rq_seq_num_1 = 0;
|
||||
reg s_axis_rq_seq_num_valid_1 = 0;
|
||||
reg [3:0] pcie_tfc_nph_av = 0;
|
||||
reg [3:0] pcie_tfc_npd_av = 0;
|
||||
reg [2:0] cfg_max_payload = 0;
|
||||
reg [2:0] cfg_max_read_req = 0;
|
||||
reg [31:0] cfg_mgmt_read_data = 0;
|
||||
reg cfg_mgmt_read_write_done = 0;
|
||||
reg [7:0] cfg_fc_ph = 0;
|
||||
reg [11:0] cfg_fc_pd = 0;
|
||||
reg [7:0] cfg_fc_nph = 0;
|
||||
reg [11:0] cfg_fc_npd = 0;
|
||||
reg [7:0] cfg_fc_cplh = 0;
|
||||
reg [11:0] cfg_fc_cpld = 0;
|
||||
reg [3:0] cfg_interrupt_msi_enable = 0;
|
||||
reg [11:0] cfg_interrupt_msi_mmenable = 0;
|
||||
reg cfg_interrupt_msi_mask_update = 0;
|
||||
reg [31:0] cfg_interrupt_msi_data = 0;
|
||||
reg cfg_interrupt_msi_sent = 0;
|
||||
reg cfg_interrupt_msi_fail = 0;
|
||||
reg qsfp0_tx_clk_1 = 0;
|
||||
reg qsfp0_tx_rst_1 = 0;
|
||||
reg qsfp0_rx_clk_1 = 0;
|
||||
reg qsfp0_rx_rst_1 = 0;
|
||||
reg [63:0] qsfp0_rxd_1 = 0;
|
||||
reg [7:0] qsfp0_rxc_1 = 0;
|
||||
reg qsfp0_tx_clk_2 = 0;
|
||||
reg qsfp0_tx_rst_2 = 0;
|
||||
reg qsfp0_rx_clk_2 = 0;
|
||||
reg qsfp0_rx_rst_2 = 0;
|
||||
reg [63:0] qsfp0_rxd_2 = 0;
|
||||
reg [7:0] qsfp0_rxc_2 = 0;
|
||||
reg qsfp0_tx_clk_3 = 0;
|
||||
reg qsfp0_tx_rst_3 = 0;
|
||||
reg qsfp0_rx_clk_3 = 0;
|
||||
reg qsfp0_rx_rst_3 = 0;
|
||||
reg [63:0] qsfp0_rxd_3 = 0;
|
||||
reg [7:0] qsfp0_rxc_3 = 0;
|
||||
reg qsfp0_tx_clk_4 = 0;
|
||||
reg qsfp0_tx_rst_4 = 0;
|
||||
reg qsfp0_rx_clk_4 = 0;
|
||||
reg qsfp0_rx_rst_4 = 0;
|
||||
reg [63:0] qsfp0_rxd_4 = 0;
|
||||
reg [7:0] qsfp0_rxc_4 = 0;
|
||||
reg qsfp1_tx_clk_1 = 0;
|
||||
reg qsfp1_tx_rst_1 = 0;
|
||||
reg qsfp1_rx_clk_1 = 0;
|
||||
reg qsfp1_rx_rst_1 = 0;
|
||||
reg [63:0] qsfp1_rxd_1 = 0;
|
||||
reg [7:0] qsfp1_rxc_1 = 0;
|
||||
reg qsfp1_tx_clk_2 = 0;
|
||||
reg qsfp1_tx_rst_2 = 0;
|
||||
reg qsfp1_rx_clk_2 = 0;
|
||||
reg qsfp1_rx_rst_2 = 0;
|
||||
reg [63:0] qsfp1_rxd_2 = 0;
|
||||
reg [7:0] qsfp1_rxc_2 = 0;
|
||||
reg qsfp1_tx_clk_3 = 0;
|
||||
reg qsfp1_tx_rst_3 = 0;
|
||||
reg qsfp1_rx_clk_3 = 0;
|
||||
reg qsfp1_rx_rst_3 = 0;
|
||||
reg [63:0] qsfp1_rxd_3 = 0;
|
||||
reg [7:0] qsfp1_rxc_3 = 0;
|
||||
reg qsfp1_tx_clk_4 = 0;
|
||||
reg qsfp1_tx_rst_4 = 0;
|
||||
reg qsfp1_rx_clk_4 = 0;
|
||||
reg qsfp1_rx_rst_4 = 0;
|
||||
reg [63:0] qsfp1_rxd_4 = 0;
|
||||
reg [7:0] qsfp1_rxc_4 = 0;
|
||||
|
||||
// Outputs
|
||||
wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_rq_tdata;
|
||||
wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_rq_tkeep;
|
||||
wire m_axis_rq_tlast;
|
||||
wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser;
|
||||
wire m_axis_rq_tvalid;
|
||||
wire s_axis_rc_tready;
|
||||
wire s_axis_cq_tready;
|
||||
wire [AXIS_PCIE_DATA_WIDTH-1:0] m_axis_cc_tdata;
|
||||
wire [AXIS_PCIE_KEEP_WIDTH-1:0] m_axis_cc_tkeep;
|
||||
wire m_axis_cc_tlast;
|
||||
wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser;
|
||||
wire m_axis_cc_tvalid;
|
||||
wire [9:0] cfg_mgmt_addr;
|
||||
wire [7:0] cfg_mgmt_function_number;
|
||||
wire cfg_mgmt_write;
|
||||
wire [31:0] cfg_mgmt_write_data;
|
||||
wire [3:0] cfg_mgmt_byte_enable;
|
||||
wire cfg_mgmt_read;
|
||||
wire [2:0] cfg_fc_sel;
|
||||
wire [3:0] cfg_interrupt_msi_select;
|
||||
wire [31:0] cfg_interrupt_msi_int;
|
||||
wire [31:0] cfg_interrupt_msi_pending_status;
|
||||
wire cfg_interrupt_msi_pending_status_data_enable;
|
||||
wire [3:0] cfg_interrupt_msi_pending_status_function_num;
|
||||
wire [2:0] cfg_interrupt_msi_attr;
|
||||
wire cfg_interrupt_msi_tph_present;
|
||||
wire [1:0] cfg_interrupt_msi_tph_type;
|
||||
wire [8:0] cfg_interrupt_msi_tph_st_tag;
|
||||
wire [3:0] cfg_interrupt_msi_function_number;
|
||||
wire status_error_cor;
|
||||
wire status_error_uncor;
|
||||
wire [63:0] qsfp0_txd_1;
|
||||
wire [7:0] qsfp0_txc_1;
|
||||
wire [63:0] qsfp0_txd_2;
|
||||
wire [7:0] qsfp0_txc_2;
|
||||
wire [63:0] qsfp0_txd_3;
|
||||
wire [7:0] qsfp0_txc_3;
|
||||
wire [63:0] qsfp0_txd_4;
|
||||
wire [7:0] qsfp0_txc_4;
|
||||
wire qsfp0_modsell;
|
||||
wire qsfp0_resetl;
|
||||
wire qsfp0_lpmode;
|
||||
wire [63:0] qsfp1_txd_1;
|
||||
wire [7:0] qsfp1_txc_1;
|
||||
wire [63:0] qsfp1_txd_2;
|
||||
wire [7:0] qsfp1_txc_2;
|
||||
wire [63:0] qsfp1_txd_3;
|
||||
wire [7:0] qsfp1_txc_3;
|
||||
wire [63:0] qsfp1_txd_4;
|
||||
wire [7:0] qsfp1_txc_4;
|
||||
wire qsfp1_modsell;
|
||||
wire qsfp1_resetl;
|
||||
wire qsfp1_lpmode;
|
||||
|
||||
initial begin
|
||||
// myhdl integration
|
||||
$from_myhdl(
|
||||
clk_250mhz,
|
||||
rst_250mhz,
|
||||
current_test,
|
||||
m_axis_rq_tready,
|
||||
s_axis_rc_tdata,
|
||||
s_axis_rc_tkeep,
|
||||
s_axis_rc_tlast,
|
||||
s_axis_rc_tuser,
|
||||
s_axis_rc_tvalid,
|
||||
s_axis_cq_tdata,
|
||||
s_axis_cq_tkeep,
|
||||
s_axis_cq_tlast,
|
||||
s_axis_cq_tuser,
|
||||
s_axis_cq_tvalid,
|
||||
m_axis_cc_tready,
|
||||
s_axis_rq_seq_num_0,
|
||||
s_axis_rq_seq_num_valid_0,
|
||||
s_axis_rq_seq_num_1,
|
||||
s_axis_rq_seq_num_valid_1,
|
||||
pcie_tfc_nph_av,
|
||||
pcie_tfc_npd_av,
|
||||
cfg_max_payload,
|
||||
cfg_max_read_req,
|
||||
cfg_mgmt_read_data,
|
||||
cfg_mgmt_read_write_done,
|
||||
cfg_fc_ph,
|
||||
cfg_fc_pd,
|
||||
cfg_fc_nph,
|
||||
cfg_fc_npd,
|
||||
cfg_fc_cplh,
|
||||
cfg_fc_cpld,
|
||||
cfg_interrupt_msi_enable,
|
||||
cfg_interrupt_msi_mmenable,
|
||||
cfg_interrupt_msi_mask_update,
|
||||
cfg_interrupt_msi_data,
|
||||
cfg_interrupt_msi_sent,
|
||||
cfg_interrupt_msi_fail,
|
||||
qsfp0_tx_clk_1,
|
||||
qsfp0_tx_rst_1,
|
||||
qsfp0_rx_clk_1,
|
||||
qsfp0_rx_rst_1,
|
||||
qsfp0_rxd_1,
|
||||
qsfp0_rxc_1,
|
||||
qsfp0_tx_clk_2,
|
||||
qsfp0_tx_rst_2,
|
||||
qsfp0_rx_clk_2,
|
||||
qsfp0_rx_rst_2,
|
||||
qsfp0_rxd_2,
|
||||
qsfp0_rxc_2,
|
||||
qsfp0_tx_clk_3,
|
||||
qsfp0_tx_rst_3,
|
||||
qsfp0_rx_clk_3,
|
||||
qsfp0_rx_rst_3,
|
||||
qsfp0_rxd_3,
|
||||
qsfp0_rxc_3,
|
||||
qsfp0_tx_clk_4,
|
||||
qsfp0_tx_rst_4,
|
||||
qsfp0_rx_clk_4,
|
||||
qsfp0_rx_rst_4,
|
||||
qsfp0_rxd_4,
|
||||
qsfp0_rxc_4,
|
||||
qsfp1_tx_clk_1,
|
||||
qsfp1_tx_rst_1,
|
||||
qsfp1_rx_clk_1,
|
||||
qsfp1_rx_rst_1,
|
||||
qsfp1_rxd_1,
|
||||
qsfp1_rxc_1,
|
||||
qsfp1_tx_clk_2,
|
||||
qsfp1_tx_rst_2,
|
||||
qsfp1_rx_clk_2,
|
||||
qsfp1_rx_rst_2,
|
||||
qsfp1_rxd_2,
|
||||
qsfp1_rxc_2,
|
||||
qsfp1_tx_clk_3,
|
||||
qsfp1_tx_rst_3,
|
||||
qsfp1_rx_clk_3,
|
||||
qsfp1_rx_rst_3,
|
||||
qsfp1_rxd_3,
|
||||
qsfp1_rxc_3,
|
||||
qsfp1_tx_clk_4,
|
||||
qsfp1_tx_rst_4,
|
||||
qsfp1_rx_clk_4,
|
||||
qsfp1_rx_rst_4,
|
||||
qsfp1_rxd_4,
|
||||
qsfp1_rxc_4
|
||||
);
|
||||
$to_myhdl(
|
||||
m_axis_rq_tdata,
|
||||
m_axis_rq_tkeep,
|
||||
m_axis_rq_tlast,
|
||||
m_axis_rq_tuser,
|
||||
m_axis_rq_tvalid,
|
||||
s_axis_rc_tready,
|
||||
s_axis_cq_tready,
|
||||
m_axis_cc_tdata,
|
||||
m_axis_cc_tkeep,
|
||||
m_axis_cc_tlast,
|
||||
m_axis_cc_tuser,
|
||||
m_axis_cc_tvalid,
|
||||
cfg_mgmt_addr,
|
||||
cfg_mgmt_function_number,
|
||||
cfg_mgmt_write,
|
||||
cfg_mgmt_write_data,
|
||||
cfg_mgmt_byte_enable,
|
||||
cfg_mgmt_read,
|
||||
cfg_fc_sel,
|
||||
cfg_interrupt_msi_select,
|
||||
cfg_interrupt_msi_int,
|
||||
cfg_interrupt_msi_pending_status,
|
||||
cfg_interrupt_msi_pending_status_data_enable,
|
||||
cfg_interrupt_msi_pending_status_function_num,
|
||||
cfg_interrupt_msi_attr,
|
||||
cfg_interrupt_msi_tph_present,
|
||||
cfg_interrupt_msi_tph_type,
|
||||
cfg_interrupt_msi_tph_st_tag,
|
||||
cfg_interrupt_msi_function_number,
|
||||
status_error_cor,
|
||||
status_error_uncor,
|
||||
qsfp0_txd_1,
|
||||
qsfp0_txc_1,
|
||||
qsfp0_txd_2,
|
||||
qsfp0_txc_2,
|
||||
qsfp0_txd_3,
|
||||
qsfp0_txc_3,
|
||||
qsfp0_txd_4,
|
||||
qsfp0_txc_4,
|
||||
qsfp1_txd_1,
|
||||
qsfp1_txc_1,
|
||||
qsfp1_txd_2,
|
||||
qsfp1_txc_2,
|
||||
qsfp1_txd_3,
|
||||
qsfp1_txc_3,
|
||||
qsfp1_txd_4,
|
||||
qsfp1_txc_4
|
||||
);
|
||||
|
||||
// dump file
|
||||
$dumpfile("test_fpga_core.lxt");
|
||||
$dumpvars(0, test_fpga_core);
|
||||
end
|
||||
|
||||
fpga_core #(
|
||||
.AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
|
||||
.AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
|
||||
.AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
|
||||
.AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
|
||||
.AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
|
||||
.AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
|
||||
.RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
|
||||
.BAR0_APERTURE(BAR0_APERTURE)
|
||||
)
|
||||
UUT (
|
||||
.clk_250mhz(clk_250mhz),
|
||||
.rst_250mhz(rst_250mhz),
|
||||
.m_axis_rq_tdata(m_axis_rq_tdata),
|
||||
.m_axis_rq_tkeep(m_axis_rq_tkeep),
|
||||
.m_axis_rq_tlast(m_axis_rq_tlast),
|
||||
.m_axis_rq_tready(m_axis_rq_tready),
|
||||
.m_axis_rq_tuser(m_axis_rq_tuser),
|
||||
.m_axis_rq_tvalid(m_axis_rq_tvalid),
|
||||
.s_axis_rc_tdata(s_axis_rc_tdata),
|
||||
.s_axis_rc_tkeep(s_axis_rc_tkeep),
|
||||
.s_axis_rc_tlast(s_axis_rc_tlast),
|
||||
.s_axis_rc_tready(s_axis_rc_tready),
|
||||
.s_axis_rc_tuser(s_axis_rc_tuser),
|
||||
.s_axis_rc_tvalid(s_axis_rc_tvalid),
|
||||
.s_axis_cq_tdata(s_axis_cq_tdata),
|
||||
.s_axis_cq_tkeep(s_axis_cq_tkeep),
|
||||
.s_axis_cq_tlast(s_axis_cq_tlast),
|
||||
.s_axis_cq_tready(s_axis_cq_tready),
|
||||
.s_axis_cq_tuser(s_axis_cq_tuser),
|
||||
.s_axis_cq_tvalid(s_axis_cq_tvalid),
|
||||
.m_axis_cc_tdata(m_axis_cc_tdata),
|
||||
.m_axis_cc_tkeep(m_axis_cc_tkeep),
|
||||
.m_axis_cc_tlast(m_axis_cc_tlast),
|
||||
.m_axis_cc_tready(m_axis_cc_tready),
|
||||
.m_axis_cc_tuser(m_axis_cc_tuser),
|
||||
.m_axis_cc_tvalid(m_axis_cc_tvalid),
|
||||
.s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
|
||||
.s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
|
||||
.s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
|
||||
.s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
|
||||
.pcie_tfc_nph_av(pcie_tfc_nph_av),
|
||||
.pcie_tfc_npd_av(pcie_tfc_npd_av),
|
||||
.cfg_max_payload(cfg_max_payload),
|
||||
.cfg_max_read_req(cfg_max_read_req),
|
||||
.cfg_mgmt_addr(cfg_mgmt_addr),
|
||||
.cfg_mgmt_function_number(cfg_mgmt_function_number),
|
||||
.cfg_mgmt_write(cfg_mgmt_write),
|
||||
.cfg_mgmt_write_data(cfg_mgmt_write_data),
|
||||
.cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
|
||||
.cfg_mgmt_read(cfg_mgmt_read),
|
||||
.cfg_mgmt_read_data(cfg_mgmt_read_data),
|
||||
.cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
|
||||
.cfg_fc_ph(cfg_fc_ph),
|
||||
.cfg_fc_pd(cfg_fc_pd),
|
||||
.cfg_fc_nph(cfg_fc_nph),
|
||||
.cfg_fc_npd(cfg_fc_npd),
|
||||
.cfg_fc_cplh(cfg_fc_cplh),
|
||||
.cfg_fc_cpld(cfg_fc_cpld),
|
||||
.cfg_fc_sel(cfg_fc_sel),
|
||||
.cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
|
||||
.cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
|
||||
.cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
|
||||
.cfg_interrupt_msi_data(cfg_interrupt_msi_data),
|
||||
.cfg_interrupt_msi_select(cfg_interrupt_msi_select),
|
||||
.cfg_interrupt_msi_int(cfg_interrupt_msi_int),
|
||||
.cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
|
||||
.cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
|
||||
.cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
|
||||
.cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
|
||||
.cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
|
||||
.cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
|
||||
.cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
|
||||
.cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
|
||||
.cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
|
||||
.cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
|
||||
.status_error_cor(status_error_cor),
|
||||
.status_error_uncor(status_error_uncor),
|
||||
.qsfp0_tx_clk_1(qsfp0_tx_clk_1),
|
||||
.qsfp0_tx_rst_1(qsfp0_tx_rst_1),
|
||||
.qsfp0_txd_1(qsfp0_txd_1),
|
||||
.qsfp0_txc_1(qsfp0_txc_1),
|
||||
.qsfp0_rx_clk_1(qsfp0_rx_clk_1),
|
||||
.qsfp0_rx_rst_1(qsfp0_rx_rst_1),
|
||||
.qsfp0_rxd_1(qsfp0_rxd_1),
|
||||
.qsfp0_rxc_1(qsfp0_rxc_1),
|
||||
.qsfp0_tx_clk_2(qsfp0_tx_clk_2),
|
||||
.qsfp0_tx_rst_2(qsfp0_tx_rst_2),
|
||||
.qsfp0_txd_2(qsfp0_txd_2),
|
||||
.qsfp0_txc_2(qsfp0_txc_2),
|
||||
.qsfp0_rx_clk_2(qsfp0_rx_clk_2),
|
||||
.qsfp0_rx_rst_2(qsfp0_rx_rst_2),
|
||||
.qsfp0_rxd_2(qsfp0_rxd_2),
|
||||
.qsfp0_rxc_2(qsfp0_rxc_2),
|
||||
.qsfp0_tx_clk_3(qsfp0_tx_clk_3),
|
||||
.qsfp0_tx_rst_3(qsfp0_tx_rst_3),
|
||||
.qsfp0_txd_3(qsfp0_txd_3),
|
||||
.qsfp0_txc_3(qsfp0_txc_3),
|
||||
.qsfp0_rx_clk_3(qsfp0_rx_clk_3),
|
||||
.qsfp0_rx_rst_3(qsfp0_rx_rst_3),
|
||||
.qsfp0_rxd_3(qsfp0_rxd_3),
|
||||
.qsfp0_rxc_3(qsfp0_rxc_3),
|
||||
.qsfp0_tx_clk_4(qsfp0_tx_clk_4),
|
||||
.qsfp0_tx_rst_4(qsfp0_tx_rst_4),
|
||||
.qsfp0_txd_4(qsfp0_txd_4),
|
||||
.qsfp0_txc_4(qsfp0_txc_4),
|
||||
.qsfp0_rx_clk_4(qsfp0_rx_clk_4),
|
||||
.qsfp0_rx_rst_4(qsfp0_rx_rst_4),
|
||||
.qsfp0_rxd_4(qsfp0_rxd_4),
|
||||
.qsfp0_rxc_4(qsfp0_rxc_4),
|
||||
.qsfp1_tx_clk_1(qsfp1_tx_clk_1),
|
||||
.qsfp1_tx_rst_1(qsfp1_tx_rst_1),
|
||||
.qsfp1_txd_1(qsfp1_txd_1),
|
||||
.qsfp1_txc_1(qsfp1_txc_1),
|
||||
.qsfp1_rx_clk_1(qsfp1_rx_clk_1),
|
||||
.qsfp1_rx_rst_1(qsfp1_rx_rst_1),
|
||||
.qsfp1_rxd_1(qsfp1_rxd_1),
|
||||
.qsfp1_rxc_1(qsfp1_rxc_1),
|
||||
.qsfp1_tx_clk_2(qsfp1_tx_clk_2),
|
||||
.qsfp1_tx_rst_2(qsfp1_tx_rst_2),
|
||||
.qsfp1_txd_2(qsfp1_txd_2),
|
||||
.qsfp1_txc_2(qsfp1_txc_2),
|
||||
.qsfp1_rx_clk_2(qsfp1_rx_clk_2),
|
||||
.qsfp1_rx_rst_2(qsfp1_rx_rst_2),
|
||||
.qsfp1_rxd_2(qsfp1_rxd_2),
|
||||
.qsfp1_rxc_2(qsfp1_rxc_2),
|
||||
.qsfp1_tx_clk_3(qsfp1_tx_clk_3),
|
||||
.qsfp1_tx_rst_3(qsfp1_tx_rst_3),
|
||||
.qsfp1_txd_3(qsfp1_txd_3),
|
||||
.qsfp1_txc_3(qsfp1_txc_3),
|
||||
.qsfp1_rx_clk_3(qsfp1_rx_clk_3),
|
||||
.qsfp1_rx_rst_3(qsfp1_rx_rst_3),
|
||||
.qsfp1_rxd_3(qsfp1_rxd_3),
|
||||
.qsfp1_rxc_3(qsfp1_rxc_3),
|
||||
.qsfp1_tx_clk_4(qsfp1_tx_clk_4),
|
||||
.qsfp1_tx_rst_4(qsfp1_tx_rst_4),
|
||||
.qsfp1_txd_4(qsfp1_txd_4),
|
||||
.qsfp1_txc_4(qsfp1_txc_4),
|
||||
.qsfp1_rx_clk_4(qsfp1_rx_clk_4),
|
||||
.qsfp1_rx_rst_4(qsfp1_rx_rst_4),
|
||||
.qsfp1_rxd_4(qsfp1_rxd_4),
|
||||
.qsfp1_rxc_4(qsfp1_rxc_4)
|
||||
);
|
||||
|
||||
endmodule
|
||||
1
fpga/mqnic/AU280/fpga_10g/tb/udp_ep.py
Symbolic link
1
fpga/mqnic/AU280/fpga_10g/tb/udp_ep.py
Symbolic link
@ -0,0 +1 @@
|
||||
../lib/eth/tb/udp_ep.py
|
||||
1
fpga/mqnic/AU280/fpga_10g/tb/xgmii_ep.py
Symbolic link
1
fpga/mqnic/AU280/fpga_10g/tb/xgmii_ep.py
Symbolic link
@ -0,0 +1 @@
|
||||
../lib/eth/tb/xgmii_ep.py
|
||||
Loading…
x
Reference in New Issue
Block a user