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fpga: Update designs for RX completion buffer management

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2023-05-31 10:26:40 -07:00
parent c45be17cea
commit 64cdae1ccf
95 changed files with 205 additions and 62 deletions
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2
fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
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@ -198,7 +198,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

2
fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
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@ -198,7 +198,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

6
fpga/common/rtl/mqnic_core_pcie.v
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@ -196,6 +196,8 @@ module mqnic_core_pcie #
parameter PCIE_TAG_COUNT = 256,
parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
parameter PCIE_DMA_READ_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH,
parameter PCIE_DMA_READ_CPLH_FC_LIMIT = 0,
parameter PCIE_DMA_READ_CPLD_FC_LIMIT = PCIE_DMA_READ_CPLH_FC_LIMIT*4,
parameter PCIE_DMA_WRITE_OP_TABLE_SIZE = 2**TX_SEQ_NUM_WIDTH,
parameter PCIE_DMA_WRITE_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH,
parameter TLP_FORCE_64_BIT_ADDR = 0,
@ -328,6 +330,7 @@ module mqnic_core_pcie #
*/
input wire [7:0] bus_num,
input wire [F_COUNT-1:0] ext_tag_enable,
input wire [F_COUNT-1:0] rcb_128b,
input wire [F_COUNT*3-1:0] max_read_request_size,
input wire [F_COUNT*3-1:0] max_payload_size,
input wire [F_COUNT-1:0] msix_enable,
@ -1112,6 +1115,8 @@ dma_if_pcie #(
.TAG_WIDTH(DMA_TAG_WIDTH),
.READ_OP_TABLE_SIZE(PCIE_DMA_READ_OP_TABLE_SIZE),
.READ_TX_LIMIT(PCIE_DMA_READ_TX_LIMIT),
.READ_CPLH_FC_LIMIT(PCIE_DMA_READ_CPLH_FC_LIMIT),
.READ_CPLD_FC_LIMIT(PCIE_DMA_READ_CPLD_FC_LIMIT),
.WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE),
.WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT),
.TLP_FORCE_64_BIT_ADDR(TLP_FORCE_64_BIT_ADDR),
@ -1224,6 +1229,7 @@ dma_if_pcie_inst (
.read_enable(dma_enable),
.write_enable(dma_enable),
.ext_tag_enable(ext_tag_enable),
.rcb_128b(rcb_128b),
.requester_id({bus_num, 5'd0, 3'd0}),
.max_read_request_size(max_read_request_size),
.max_payload_size(max_payload_size),

7
fpga/common/rtl/mqnic_core_pcie_ptile.v
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@ -196,6 +196,8 @@ module mqnic_core_pcie_ptile #
parameter PCIE_TAG_COUNT = 256,
parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
parameter PCIE_DMA_READ_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH,
parameter PCIE_DMA_READ_CPLH_FC_LIMIT = 1144,
parameter PCIE_DMA_READ_CPLD_FC_LIMIT = 2888,
parameter PCIE_DMA_WRITE_OP_TABLE_SIZE = 2**TX_SEQ_NUM_WIDTH,
parameter PCIE_DMA_WRITE_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH,
@ -574,6 +576,7 @@ wire pcie_tx_msix_wr_req_tlp_eop;
wire pcie_tx_msix_wr_req_tlp_ready;
wire [F_COUNT-1:0] ext_tag_enable;
wire [F_COUNT-1:0] rcb_128b;
wire [7:0] bus_num;
wire [F_COUNT*3-1:0] max_read_request_size;
wire [F_COUNT*3-1:0] max_payload_size;
@ -741,6 +744,7 @@ pcie_ptile_if_inst (
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.rcb_128b(rcb_128b),
.bus_num(bus_num),
.max_read_request_size(max_read_request_size),
.max_payload_size(max_payload_size),
@ -901,6 +905,8 @@ mqnic_core_pcie #(
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.PCIE_DMA_READ_OP_TABLE_SIZE(PCIE_DMA_READ_OP_TABLE_SIZE),
.PCIE_DMA_READ_TX_LIMIT(PCIE_DMA_READ_TX_LIMIT),
.PCIE_DMA_READ_CPLH_FC_LIMIT(PCIE_DMA_READ_CPLH_FC_LIMIT),
.PCIE_DMA_READ_CPLD_FC_LIMIT(PCIE_DMA_READ_CPLD_FC_LIMIT),
.PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE),
.PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT),
.TLP_FORCE_64_BIT_ADDR(0),
@ -1033,6 +1039,7 @@ core_pcie_inst (
*/
.bus_num(bus_num),
.ext_tag_enable(ext_tag_enable),
.rcb_128b(rcb_128b),
.max_read_request_size(max_read_request_size),
.max_payload_size(max_payload_size),
.msix_enable(msix_enable),

7
fpga/common/rtl/mqnic_core_pcie_s10.v
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@ -195,6 +195,8 @@ module mqnic_core_pcie_s10 #
parameter PCIE_TAG_COUNT = 256,
parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
parameter PCIE_DMA_READ_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH,
parameter PCIE_DMA_READ_CPLH_FC_LIMIT = 770,
parameter PCIE_DMA_READ_CPLD_FC_LIMIT = 2500,
parameter PCIE_DMA_WRITE_OP_TABLE_SIZE = 2**TX_SEQ_NUM_WIDTH,
parameter PCIE_DMA_WRITE_TX_LIMIT = 2**TX_SEQ_NUM_WIDTH,
@ -570,6 +572,7 @@ wire pcie_tx_msix_wr_req_tlp_eop;
wire pcie_tx_msix_wr_req_tlp_ready;
wire [F_COUNT-1:0] ext_tag_enable;
wire [F_COUNT-1:0] rcb_128b;
wire [7:0] bus_num;
wire [F_COUNT*3-1:0] max_read_request_size;
wire [F_COUNT*3-1:0] max_payload_size;
@ -745,6 +748,7 @@ pcie_s10_if_inst (
* Configuration outputs
*/
.ext_tag_enable(ext_tag_enable),
.rcb_128b(rcb_128b),
.bus_num(bus_num),
.max_read_request_size(max_read_request_size),
.max_payload_size(max_payload_size),
@ -910,6 +914,8 @@ mqnic_core_pcie #(
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.PCIE_DMA_READ_OP_TABLE_SIZE(PCIE_DMA_READ_OP_TABLE_SIZE),
.PCIE_DMA_READ_TX_LIMIT(PCIE_DMA_READ_TX_LIMIT),
.PCIE_DMA_READ_CPLH_FC_LIMIT(PCIE_DMA_READ_CPLH_FC_LIMIT),
.PCIE_DMA_READ_CPLD_FC_LIMIT(PCIE_DMA_READ_CPLD_FC_LIMIT),
.PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE),
.PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT),
.TLP_FORCE_64_BIT_ADDR(0),
@ -1042,6 +1048,7 @@ core_pcie_inst (
*/
.bus_num(bus_num),
.ext_tag_enable(ext_tag_enable),
.rcb_128b(rcb_128b),
.max_read_request_size(max_read_request_size),
.max_payload_size(max_payload_size),
.msix_enable(msix_enable),

7
fpga/common/rtl/mqnic_core_pcie_us.v
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@ -200,6 +200,8 @@ module mqnic_core_pcie_us #
parameter PCIE_TAG_COUNT = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 64 : 256,
parameter PCIE_DMA_READ_OP_TABLE_SIZE = PCIE_TAG_COUNT,
parameter PCIE_DMA_READ_TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1),
parameter PCIE_DMA_READ_CPLH_FC_LIMIT = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 64 : 128,
parameter PCIE_DMA_READ_CPLD_FC_LIMIT = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 992 : 2048,
parameter PCIE_DMA_WRITE_OP_TABLE_SIZE = 2**(RQ_SEQ_NUM_WIDTH-1),
parameter PCIE_DMA_WRITE_TX_LIMIT = 2**(RQ_SEQ_NUM_WIDTH-1),
@ -309,6 +311,7 @@ module mqnic_core_pcie_us #
*/
input wire [2:0] cfg_max_read_req,
input wire [2:0] cfg_max_payload,
input wire [3:0] cfg_rcb_status,
/*
* Configuration flow control interface
@ -1031,6 +1034,8 @@ mqnic_core_pcie #(
.PCIE_TAG_COUNT(PCIE_TAG_COUNT),
.PCIE_DMA_READ_OP_TABLE_SIZE(PCIE_DMA_READ_OP_TABLE_SIZE),
.PCIE_DMA_READ_TX_LIMIT(PCIE_DMA_READ_TX_LIMIT),
.PCIE_DMA_READ_CPLH_FC_LIMIT(PCIE_DMA_READ_CPLH_FC_LIMIT),
.PCIE_DMA_READ_CPLD_FC_LIMIT(PCIE_DMA_READ_CPLD_FC_LIMIT),
.PCIE_DMA_WRITE_OP_TABLE_SIZE(PCIE_DMA_WRITE_OP_TABLE_SIZE),
.PCIE_DMA_WRITE_TX_LIMIT(PCIE_DMA_WRITE_TX_LIMIT),
.TLP_FORCE_64_BIT_ADDR(1),
@ -1163,6 +1168,8 @@ core_pcie_inst (
*/
.bus_num(8'd0),
.ext_tag_enable(ext_tag_enable),
// .rcb_128b(cfg_rcb_status),
.rcb_128b(1'b1), // force RCB 128 due to insufficient CPLH limit in US+ PCIe HIP
.max_read_request_size(cfg_max_read_req),
.max_payload_size(cfg_max_payload),
.msix_enable(msix_enable),

2
fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py
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@ -198,7 +198,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

2
fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py
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@ -198,7 +198,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

4
fpga/mqnic/250_SoC/fpga_100g/rtl/fpga.v
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@ -525,6 +525,7 @@ wire [3:0] pcie_tfc_npd_av;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [9:0] cfg_mgmt_addr;
wire [7:0] cfg_mgmt_function_number;
@ -661,7 +662,7 @@ pcie4_uscale_plus_inst (
.cfg_ltssm_state(),
.cfg_rx_pm_state(),
.cfg_tx_pm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_obff_enable(),
.cfg_pl_status_change(),
.cfg_tph_requester_enable(),
@ -1467,6 +1468,7 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),

2
fpga/mqnic/250_SoC/fpga_100g/rtl/fpga_core.v
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@ -274,6 +274,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
@ -1155,6 +1156,7 @@ core_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
.cfg_rcb_status(cfg_rcb_status),
/*
* Configuration interface

2
fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py
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@ -196,7 +196,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

4
fpga/mqnic/250_SoC/fpga_25g/rtl/fpga.v
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@ -532,6 +532,7 @@ wire [3:0] pcie_tfc_npd_av;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [9:0] cfg_mgmt_addr;
wire [7:0] cfg_mgmt_function_number;
@ -668,7 +669,7 @@ pcie4_uscale_plus_inst (
.cfg_ltssm_state(),
.cfg_rx_pm_state(),
.cfg_tx_pm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_obff_enable(),
.cfg_pl_status_change(),
.cfg_tph_requester_enable(),
@ -1599,6 +1600,7 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),

2
fpga/mqnic/250_SoC/fpga_25g/rtl/fpga_core.v
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@ -283,6 +283,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
@ -1305,6 +1306,7 @@ core_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
.cfg_rcb_status(cfg_rcb_status),
/*
* Configuration interface

2
fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py
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@ -196,7 +196,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

4
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga.v
View File

@ -732,6 +732,7 @@ wire [3:0] pcie_tfc_npd_av;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [9:0] cfg_mgmt_addr;
wire [7:0] cfg_mgmt_function_number;
@ -896,7 +897,7 @@ pcie4_uscale_plus_inst (
.cfg_ltssm_state(),
.cfg_rx_pm_state(),
.cfg_tx_pm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_obff_enable(),
.cfg_pl_status_change(),
.cfg_tph_requester_enable(),
@ -1803,6 +1804,7 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),

2
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/rtl/fpga_core.v
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@ -253,6 +253,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
@ -1224,6 +1225,7 @@ core_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
.cfg_rcb_status(cfg_rcb_status),
/*
* Configuration interface

2
fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py
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@ -196,7 +196,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

4
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v
View File

@ -739,6 +739,7 @@ wire [3:0] pcie_tfc_npd_av;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [9:0] cfg_mgmt_addr;
wire [7:0] cfg_mgmt_function_number;
@ -903,7 +904,7 @@ pcie4_uscale_plus_inst (
.cfg_ltssm_state(),
.cfg_rx_pm_state(),
.cfg_tx_pm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_obff_enable(),
.cfg_pl_status_change(),
.cfg_tph_requester_enable(),
@ -1939,6 +1940,7 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),

2
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v
View File

@ -262,6 +262,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
@ -1373,6 +1374,7 @@ core_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
.cfg_rcb_status(cfg_rcb_status),
/*
* Configuration interface

2
fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -196,7 +196,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

4
fpga/mqnic/AU200/fpga_100g/rtl/fpga.v
View File

@ -911,6 +911,7 @@ wire [3:0] pcie_tfc_npd_av;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [9:0] cfg_mgmt_addr;
wire [7:0] cfg_mgmt_function_number;
@ -1047,7 +1048,7 @@ pcie4_uscale_plus_inst (
.cfg_ltssm_state(),
.cfg_rx_pm_state(),
.cfg_tx_pm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_obff_enable(),
.cfg_pl_status_change(),
.cfg_tph_requester_enable(),
@ -2214,6 +2215,7 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),

2
fpga/mqnic/AU200/fpga_100g/rtl/fpga_core.v
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@ -261,6 +261,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
@ -1232,6 +1233,7 @@ core_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
.cfg_rcb_status(cfg_rcb_status),
/*
* Configuration interface

2
fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -196,7 +196,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

4
fpga/mqnic/AU200/fpga_25g/rtl/fpga.v
View File

@ -918,6 +918,7 @@ wire [3:0] pcie_tfc_npd_av;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [9:0] cfg_mgmt_addr;
wire [7:0] cfg_mgmt_function_number;
@ -1054,7 +1055,7 @@ pcie4_uscale_plus_inst (
.cfg_ltssm_state(),
.cfg_rx_pm_state(),
.cfg_tx_pm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_obff_enable(),
.cfg_pl_status_change(),
.cfg_tph_requester_enable(),
@ -2347,6 +2348,7 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),

2
fpga/mqnic/AU200/fpga_25g/rtl/fpga_core.v
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@ -270,6 +270,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
@ -1382,6 +1383,7 @@ core_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
.cfg_rcb_status(cfg_rcb_status),
/*
* Configuration interface

2
fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -196,7 +196,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

4
fpga/mqnic/AU250/fpga_100g/rtl/fpga.v
View File

@ -911,6 +911,7 @@ wire [3:0] pcie_tfc_npd_av;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [9:0] cfg_mgmt_addr;
wire [7:0] cfg_mgmt_function_number;
@ -1047,7 +1048,7 @@ pcie4_uscale_plus_inst (
.cfg_ltssm_state(),
.cfg_rx_pm_state(),
.cfg_tx_pm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_obff_enable(),
.cfg_pl_status_change(),
.cfg_tph_requester_enable(),
@ -2214,6 +2215,7 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),

2
fpga/mqnic/AU250/fpga_100g/rtl/fpga_core.v
View File

@ -261,6 +261,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
@ -1232,6 +1233,7 @@ core_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
.cfg_rcb_status(cfg_rcb_status),
/*
* Configuration interface

2
fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -196,7 +196,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

4
fpga/mqnic/AU250/fpga_25g/rtl/fpga.v
View File

@ -918,6 +918,7 @@ wire [3:0] pcie_tfc_npd_av;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [9:0] cfg_mgmt_addr;
wire [7:0] cfg_mgmt_function_number;
@ -1054,7 +1055,7 @@ pcie4_uscale_plus_inst (
.cfg_ltssm_state(),
.cfg_rx_pm_state(),
.cfg_tx_pm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_obff_enable(),
.cfg_pl_status_change(),
.cfg_tph_requester_enable(),
@ -2347,6 +2348,7 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),

2
fpga/mqnic/AU250/fpga_25g/rtl/fpga_core.v
View File

@ -270,6 +270,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
@ -1382,6 +1383,7 @@ core_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
.cfg_rcb_status(cfg_rcb_status),
/*
* Configuration interface

2
fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -196,7 +196,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

4
fpga/mqnic/AU280/fpga_100g/rtl/fpga.v
View File

@ -779,6 +779,7 @@ wire [3:0] pcie_tfc_npd_av;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [9:0] cfg_mgmt_addr;
wire [7:0] cfg_mgmt_function_number;
@ -915,7 +916,7 @@ pcie4c_uscale_plus_inst (
.cfg_ltssm_state(),
.cfg_rx_pm_state(),
.cfg_tx_pm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_obff_enable(),
.cfg_pl_status_change(),
.cfg_tph_requester_enable(),
@ -3330,6 +3331,7 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),

2
fpga/mqnic/AU280/fpga_100g/rtl/fpga_core.v
View File

@ -253,6 +253,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
@ -1190,6 +1191,7 @@ core_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
.cfg_rcb_status(cfg_rcb_status),
/*
* Configuration interface

2
fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -196,7 +196,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

4
fpga/mqnic/AU280/fpga_25g/rtl/fpga.v
View File

@ -786,6 +786,7 @@ wire [3:0] pcie_tfc_npd_av;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [9:0] cfg_mgmt_addr;
wire [7:0] cfg_mgmt_function_number;
@ -922,7 +923,7 @@ pcie4c_uscale_plus_inst (
.cfg_ltssm_state(),
.cfg_rx_pm_state(),
.cfg_tx_pm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_obff_enable(),
.cfg_pl_status_change(),
.cfg_tph_requester_enable(),
@ -3473,6 +3474,7 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),

2
fpga/mqnic/AU280/fpga_25g/rtl/fpga_core.v
View File

@ -262,6 +262,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
@ -1340,6 +1341,7 @@ core_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
.cfg_rcb_status(cfg_rcb_status),
/*
* Configuration interface

2
fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -196,7 +196,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

4
fpga/mqnic/AU50/fpga_100g/rtl/fpga.v
View File

@ -714,6 +714,7 @@ wire [3:0] pcie_tfc_npd_av;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [9:0] cfg_mgmt_addr;
wire [7:0] cfg_mgmt_function_number;
@ -850,7 +851,7 @@ pcie4c_uscale_plus_inst (
.cfg_ltssm_state(),
.cfg_rx_pm_state(),
.cfg_tx_pm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_obff_enable(),
.cfg_pl_status_change(),
.cfg_tph_requester_enable(),
@ -2794,6 +2795,7 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),

2
fpga/mqnic/AU50/fpga_100g/rtl/fpga_core.v
View File

@ -252,6 +252,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
@ -1040,6 +1041,7 @@ core_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
.cfg_rcb_status(cfg_rcb_status),
/*
* Configuration interface

2
fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -196,7 +196,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

4
fpga/mqnic/AU50/fpga_25g/rtl/fpga.v
View File

@ -724,6 +724,7 @@ wire [3:0] pcie_tfc_npd_av;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [9:0] cfg_mgmt_addr;
wire [7:0] cfg_mgmt_function_number;
@ -860,7 +861,7 @@ pcie4c_uscale_plus_inst (
.cfg_ltssm_state(),
.cfg_rx_pm_state(),
.cfg_tx_pm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_obff_enable(),
.cfg_pl_status_change(),
.cfg_tph_requester_enable(),
@ -2868,6 +2869,7 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),

2
fpga/mqnic/AU50/fpga_25g/rtl/fpga_core.v
View File

@ -261,6 +261,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
@ -1167,6 +1168,7 @@ core_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
.cfg_rcb_status(cfg_rcb_status),
/*
* Configuration interface

2
fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -196,7 +196,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

4
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga.v
View File

@ -722,6 +722,7 @@ wire [1:0] pcie_tfc_npd_av;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [18:0] cfg_mgmt_addr;
wire cfg_mgmt_write;
@ -844,7 +845,7 @@ pcie3_ultrascale_inst (
.cfg_local_error(),
.cfg_ltr_enable(),
.cfg_ltssm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_dpa_substate_change(),
.cfg_obff_enable(),
.cfg_pl_status_change(),
@ -1780,6 +1781,7 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_write(cfg_mgmt_write),

2
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/rtl/fpga_core.v
View File

@ -261,6 +261,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [18:0] cfg_mgmt_addr,
output wire cfg_mgmt_write,
@ -1401,6 +1402,7 @@ core_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
.cfg_rcb_status(cfg_rcb_status),
/*
* Configuration interface

2
fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -171,7 +171,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

4
fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga.v
View File

@ -604,6 +604,7 @@ wire [3:0] pcie_tfc_npd_av;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [18:0] cfg_mgmt_addr;
wire cfg_mgmt_write;
@ -883,7 +884,7 @@ pcie3_7x_inst (
.cfg_err_fatal_out(),
.cfg_ltr_enable(),
.cfg_ltssm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_dpa_substate_change(),
.cfg_obff_enable(),
.cfg_pl_status_change(),
@ -1497,6 +1498,7 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_write(cfg_mgmt_write),

2
fpga/mqnic/NetFPGA_SUME/fpga/rtl/fpga_core.v
View File

@ -260,6 +260,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [18:0] cfg_mgmt_addr,
output wire cfg_mgmt_write,
@ -932,6 +933,7 @@ core_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
.cfg_rcb_status(cfg_rcb_status),
/*
* Configuration interface

2
fpga/mqnic/NetFPGA_SUME/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -171,7 +171,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

4
fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga.v
View File

@ -643,6 +643,7 @@ wire [1:0] pcie_tfc_npd_av;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [18:0] cfg_mgmt_addr;
wire cfg_mgmt_write;
@ -769,7 +770,7 @@ pcie3_ultrascale_inst (
.cfg_local_error(),
.cfg_ltr_enable(),
.cfg_ltssm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_dpa_substate_change(),
.cfg_obff_enable(),
.cfg_pl_status_change(),
@ -1214,6 +1215,7 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_write(cfg_mgmt_write),

2
fpga/mqnic/Nexus_K35_S/fpga/rtl/fpga_core.v
View File

@ -251,6 +251,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [18:0] cfg_mgmt_addr,
output wire cfg_mgmt_write,
@ -1086,6 +1087,7 @@ core_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
.cfg_rcb_status(cfg_rcb_status),
/*
* Configuration interface

2
fpga/mqnic/Nexus_K35_S/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -171,7 +171,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

4
fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga.v
View File

@ -783,6 +783,7 @@ wire [3:0] pcie_tfc_npd_av;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [9:0] cfg_mgmt_addr;
wire [7:0] cfg_mgmt_function_number;
@ -919,7 +920,7 @@ pcie4_uscale_plus_inst (
.cfg_ltssm_state(),
.cfg_rx_pm_state(),
.cfg_tx_pm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_obff_enable(),
.cfg_pl_status_change(),
.cfg_tph_requester_enable(),
@ -1805,6 +1806,7 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),

2
fpga/mqnic/Nexus_K3P_Q/fpga_25g/rtl/fpga_core.v
View File

@ -269,6 +269,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
@ -1436,6 +1437,7 @@ core_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
.cfg_rcb_status(cfg_rcb_status),
/*
* Configuration interface

2
fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -196,7 +196,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

4
fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga.v
View File

@ -729,6 +729,7 @@ wire [3:0] pcie_tfc_npd_av;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [9:0] cfg_mgmt_addr;
wire [7:0] cfg_mgmt_function_number;
@ -893,7 +894,7 @@ pcie4_uscale_plus_inst (
.cfg_ltssm_state(),
.cfg_rx_pm_state(),
.cfg_tx_pm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_obff_enable(),
.cfg_pl_status_change(),
.cfg_tph_requester_enable(),
@ -1353,6 +1354,7 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),

2
fpga/mqnic/Nexus_K3P_S/fpga_25g/rtl/fpga_core.v
View File

@ -256,6 +256,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
@ -1184,6 +1185,7 @@ core_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
.cfg_rcb_status(cfg_rcb_status),
/*
* Configuration interface

2
fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -196,7 +196,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

4
fpga/mqnic/VCU108/fpga_25g/rtl/fpga.v
View File

@ -727,6 +727,7 @@ wire [1:0] pcie_tfc_npd_av;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [18:0] cfg_mgmt_addr;
wire cfg_mgmt_write;
@ -853,7 +854,7 @@ pcie3_ultrascale_inst (
.cfg_local_error(),
.cfg_ltr_enable(),
.cfg_ltssm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_dpa_substate_change(),
.cfg_obff_enable(),
.cfg_pl_status_change(),
@ -1722,6 +1723,7 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_write(cfg_mgmt_write),

2
fpga/mqnic/VCU108/fpga_25g/rtl/fpga_core.v
View File

@ -275,6 +275,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [18:0] cfg_mgmt_addr,
output wire cfg_mgmt_write,
@ -1207,6 +1208,7 @@ core_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
.cfg_rcb_status(cfg_rcb_status),
/*
* Configuration interface

2
fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -171,7 +171,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

4
fpga/mqnic/VCU118/fpga_100g/rtl/fpga.v
View File

@ -747,6 +747,7 @@ wire [3:0] pcie_tfc_npd_av;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [9:0] cfg_mgmt_addr;
wire [7:0] cfg_mgmt_function_number;
@ -883,7 +884,7 @@ pcie4_uscale_plus_inst (
.cfg_ltssm_state(),
.cfg_rx_pm_state(),
.cfg_tx_pm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_obff_enable(),
.cfg_pl_status_change(),
.cfg_tph_requester_enable(),
@ -1808,6 +1809,7 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),

2
fpga/mqnic/VCU118/fpga_100g/rtl/fpga_core.v
View File

@ -268,6 +268,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
@ -1200,6 +1201,7 @@ core_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
.cfg_rcb_status(cfg_rcb_status),
/*
* Configuration interface

2
fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -196,7 +196,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

4
fpga/mqnic/VCU118/fpga_25g/rtl/fpga.v
View File

@ -754,6 +754,7 @@ wire [3:0] pcie_tfc_npd_av;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [9:0] cfg_mgmt_addr;
wire [7:0] cfg_mgmt_function_number;
@ -890,7 +891,7 @@ pcie4_uscale_plus_inst (
.cfg_ltssm_state(),
.cfg_rx_pm_state(),
.cfg_tx_pm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_obff_enable(),
.cfg_pl_status_change(),
.cfg_tph_requester_enable(),
@ -1940,6 +1941,7 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),

2
fpga/mqnic/VCU118/fpga_25g/rtl/fpga_core.v
View File

@ -277,6 +277,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
@ -1350,6 +1351,7 @@ core_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
.cfg_rcb_status(cfg_rcb_status),
/*
* Configuration interface

2
fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -196,7 +196,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

4
fpga/mqnic/VCU1525/fpga_100g/rtl/fpga.v
View File

@ -756,6 +756,7 @@ wire [3:0] pcie_tfc_npd_av;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [9:0] cfg_mgmt_addr;
wire [7:0] cfg_mgmt_function_number;
@ -892,7 +893,7 @@ pcie4_uscale_plus_inst (
.cfg_ltssm_state(),
.cfg_rx_pm_state(),
.cfg_tx_pm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_obff_enable(),
.cfg_pl_status_change(),
.cfg_tph_requester_enable(),
@ -2059,6 +2060,7 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),

2
fpga/mqnic/VCU1525/fpga_100g/rtl/fpga_core.v
View File

@ -261,6 +261,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
@ -1155,6 +1156,7 @@ core_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
.cfg_rcb_status(cfg_rcb_status),
/*
* Configuration interface

2
fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -196,7 +196,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

4
fpga/mqnic/VCU1525/fpga_25g/rtl/fpga.v
View File

@ -763,6 +763,7 @@ wire [3:0] pcie_tfc_npd_av;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [9:0] cfg_mgmt_addr;
wire [7:0] cfg_mgmt_function_number;
@ -899,7 +900,7 @@ pcie4_uscale_plus_inst (
.cfg_ltssm_state(),
.cfg_rx_pm_state(),
.cfg_tx_pm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_obff_enable(),
.cfg_pl_status_change(),
.cfg_tph_requester_enable(),
@ -2192,6 +2193,7 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),

2
fpga/mqnic/VCU1525/fpga_25g/rtl/fpga_core.v
View File

@ -270,6 +270,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
@ -1305,6 +1306,7 @@ core_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
.cfg_rcb_status(cfg_rcb_status),
/*
* Configuration interface

2
fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -196,7 +196,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

4
fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga.v
View File

@ -873,6 +873,7 @@ wire [3:0] pcie_tfc_npd_av;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [9:0] cfg_mgmt_addr;
wire [7:0] cfg_mgmt_function_number;
@ -1009,7 +1010,7 @@ pcie4_uscale_plus_inst (
.cfg_ltssm_state(),
.cfg_rx_pm_state(),
.cfg_tx_pm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_obff_enable(),
.cfg_pl_status_change(),
.cfg_tph_requester_enable(),
@ -2462,6 +2463,7 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),

2
fpga/mqnic/XUPP3R/fpga_100g/rtl/fpga_core.v
View File

@ -260,6 +260,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
@ -1527,6 +1528,7 @@ core_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
.cfg_rcb_status(cfg_rcb_status),
/*
* Configuration interface

2
fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -196,7 +196,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

4
fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga.v
View File

@ -880,6 +880,7 @@ wire [3:0] pcie_tfc_npd_av;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [9:0] cfg_mgmt_addr;
wire [7:0] cfg_mgmt_function_number;
@ -1016,7 +1017,7 @@ pcie4_uscale_plus_inst (
.cfg_ltssm_state(),
.cfg_rx_pm_state(),
.cfg_tx_pm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_obff_enable(),
.cfg_pl_status_change(),
.cfg_tph_requester_enable(),
@ -2722,6 +2723,7 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),

2
fpga/mqnic/XUPP3R/fpga_25g/rtl/fpga_core.v
View File

@ -269,6 +269,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
@ -1723,6 +1724,7 @@ core_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
.cfg_rcb_status(cfg_rcb_status),
/*
* Configuration interface

2
fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -196,7 +196,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

4
fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga.v
View File

@ -490,6 +490,7 @@ wire [3:0] pcie_tfc_npd_av;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [9:0] cfg_mgmt_addr;
wire [7:0] cfg_mgmt_function_number;
@ -626,7 +627,7 @@ pcie4_uscale_plus_inst (
.cfg_ltssm_state(),
.cfg_rx_pm_state(),
.cfg_tx_pm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_obff_enable(),
.cfg_pl_status_change(),
.cfg_tph_requester_enable(),
@ -1254,6 +1255,7 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),

2
fpga/mqnic/ZCU106/fpga_pcie/rtl/fpga_core.v
View File

@ -275,6 +275,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
@ -1065,6 +1066,7 @@ core_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
.cfg_rcb_status(cfg_rcb_status),
/*
* Configuration interface

2
fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py
View File

@ -196,7 +196,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

4
fpga/mqnic/fb2CG/fpga_100g/rtl/fpga.v
View File

@ -767,6 +767,7 @@ wire [3:0] pcie_tfc_npd_av;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [9:0] cfg_mgmt_addr;
wire [7:0] cfg_mgmt_function_number;
@ -931,7 +932,7 @@ pcie4_uscale_plus_inst (
.cfg_ltssm_state(),
.cfg_rx_pm_state(),
.cfg_tx_pm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_obff_enable(),
.cfg_pl_status_change(),
.cfg_tph_requester_enable(),
@ -2137,6 +2138,7 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),

2
fpga/mqnic/fb2CG/fpga_100g/rtl/fpga_core.v
View File

@ -266,6 +266,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
@ -1257,6 +1258,7 @@ core_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
.cfg_rcb_status(cfg_rcb_status),
/*
* Configuration interface

2
fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -196,7 +196,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

4
fpga/mqnic/fb2CG/fpga_25g/rtl/fpga.v
View File

@ -774,6 +774,7 @@ wire [3:0] pcie_tfc_npd_av;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [9:0] cfg_mgmt_addr;
wire [7:0] cfg_mgmt_function_number;
@ -938,7 +939,7 @@ pcie4_uscale_plus_inst (
.cfg_ltssm_state(),
.cfg_rx_pm_state(),
.cfg_tx_pm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_obff_enable(),
.cfg_pl_status_change(),
.cfg_tph_requester_enable(),
@ -2284,6 +2285,7 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),

2
fpga/mqnic/fb2CG/fpga_25g/rtl/fpga_core.v
View File

@ -275,6 +275,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
@ -1406,6 +1407,7 @@ core_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
.cfg_rcb_status(cfg_rcb_status),
/*
* Configuration interface

2
fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -196,7 +196,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

4
fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga.v
View File

@ -593,6 +593,7 @@ wire [3:0] pcie_tfc_npd_av;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [9:0] cfg_mgmt_addr;
wire [7:0] cfg_mgmt_function_number;
@ -729,7 +730,7 @@ pcie4_uscale_plus_inst (
.cfg_ltssm_state(),
.cfg_rx_pm_state(),
.cfg_tx_pm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_obff_enable(),
.cfg_pl_status_change(),
.cfg_tph_requester_enable(),
@ -1646,6 +1647,7 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),

2
fpga/mqnic/fb4CGg3/fpga_100g/rtl/fpga_core.v
View File

@ -246,6 +246,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
@ -1344,6 +1345,7 @@ core_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
.cfg_rcb_status(cfg_rcb_status),
/*
* Configuration interface

2
fpga/mqnic/fb4CGg3/fpga_100g/tb/fpga_core/test_fpga_core.py
View File

@ -196,7 +196,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable

4
fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga.v
View File

@ -592,6 +592,7 @@ wire [3:0] pcie_tfc_npd_av;
wire [2:0] cfg_max_payload;
wire [2:0] cfg_max_read_req;
wire [3:0] cfg_rcb_status;
wire [9:0] cfg_mgmt_addr;
wire [7:0] cfg_mgmt_function_number;
@ -728,7 +729,7 @@ pcie4_uscale_plus_inst (
.cfg_ltssm_state(),
.cfg_rx_pm_state(),
.cfg_tx_pm_state(),
.cfg_rcb_status(),
.cfg_rcb_status(cfg_rcb_status),
.cfg_obff_enable(),
.cfg_pl_status_change(),
.cfg_tph_requester_enable(),
@ -1917,6 +1918,7 @@ core_inst (
.cfg_max_payload(cfg_max_payload),
.cfg_max_read_req(cfg_max_read_req),
.cfg_rcb_status(cfg_rcb_status),
.cfg_mgmt_addr(cfg_mgmt_addr),
.cfg_mgmt_function_number(cfg_mgmt_function_number),

2
fpga/mqnic/fb4CGg3/fpga_25g/rtl/fpga_core.v
View File

@ -255,6 +255,7 @@ module fpga_core #
input wire [2:0] cfg_max_payload,
input wire [2:0] cfg_max_read_req,
input wire [3:0] cfg_rcb_status,
output wire [9:0] cfg_mgmt_addr,
output wire [7:0] cfg_mgmt_function_number,
@ -1555,6 +1556,7 @@ core_inst (
*/
.cfg_max_read_req(cfg_max_read_req),
.cfg_max_payload(cfg_max_payload),
.cfg_rcb_status(cfg_rcb_status),
/*
* Configuration interface

2
fpga/mqnic/fb4CGg3/fpga_25g/tb/fpga_core/test_fpga_core.py
View File

@ -196,7 +196,7 @@ class TB(object):
# cfg_rx_pm_state
# cfg_tx_pm_state
# cfg_ltssm_state
# cfg_rcb_status
cfg_rcb_status=dut.cfg_rcb_status,
# cfg_obff_enable
# cfg_pl_status_change
# cfg_tph_requester_enable