diff --git a/example/AU50/fpga_axi/fpga.xdc b/example/AU50/fpga_axi/fpga.xdc
index c27a5bb6e..6ea794391 100644
--- a/example/AU50/fpga_axi/fpga.xdc
+++ b/example/AU50/fpga_axi/fpga.xdc
@@ -28,9 +28,9 @@ set_operating_conditions -design_power_budget 63
 #create_clock -period 10 -name clk_100mhz_1 [get_ports clk_100mhz_1_p]
 
 # LEDs
-#set_property -dict {LOC E18 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp_led_act]
-#set_property -dict {LOC E16 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp_led_stat_g]
-#set_property -dict {LOC F17 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp_led_stat_y]
+set_property -dict {LOC E18 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp_led_act]
+set_property -dict {LOC E16 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp_led_stat_g]
+set_property -dict {LOC F17 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp_led_stat_y]
 
 # UART
 #set_property -dict {LOC BE26 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports usb_uart0_txd]