From 667076ee396c919ddd77f151d96d65da18c1dd4c Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 18 Nov 2021 13:50:32 -0800 Subject: [PATCH] Testbench cleanup --- example/520N_MX/fpga/tb/fpga_core/test_fpga_core.py | 5 ++--- example/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py | 5 ++--- example/S10MX_DK/fpga/tb/fpga_core/test_fpga_core.py | 5 ++--- example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py | 5 ++--- 4 files changed, 8 insertions(+), 12 deletions(-) diff --git a/example/520N_MX/fpga/tb/fpga_core/test_fpga_core.py b/example/520N_MX/fpga/tb/fpga_core/test_fpga_core.py index b9198d503..87888d60c 100644 --- a/example/520N_MX/fpga/tb/fpga_core/test_fpga_core.py +++ b/example/520N_MX/fpga/tb/fpga_core/test_fpga_core.py @@ -33,7 +33,6 @@ from cocotb.triggers import RisingEdge, FallingEdge, Timer from cocotbext.pcie.core import RootComplex from cocotbext.pcie.intel.s10 import S10PcieDevice, S10RxBus, S10TxBus -from cocotbext.axi.utils import hexdump_str class TB(object): @@ -156,8 +155,8 @@ class TB(object): self.dev.functions[0].msi_multiple_message_capable = 5 - self.dev.functions[0].configure_bar(0, 2**22) - self.dev.functions[0].configure_bar(2, 2**22) + self.dev.functions[0].configure_bar(0, 2**len(dut.example_core_pcie_s10_inst.core_pcie_inst.axil_ctrl_awaddr)) + self.dev.functions[0].configure_bar(2, 2**len(dut.example_core_pcie_s10_inst.core_pcie_inst.axi_ram_awaddr)) async def init(self): diff --git a/example/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py b/example/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py index 3a55373c3..f1d721c63 100644 --- a/example/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py +++ b/example/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py @@ -34,7 +34,6 @@ from cocotb.triggers import RisingEdge, FallingEdge, Timer from cocotbext.axi import AxiStreamBus from cocotbext.pcie.core import RootComplex from cocotbext.pcie.xilinx.us import UltraScalePcieDevice -from cocotbext.axi.utils import hexdump_str class TB(object): @@ -228,8 +227,8 @@ class TB(object): self.dev.functions[0].msi_multiple_message_capable = 5 - self.dev.functions[0].configure_bar(0, 2**24) - self.dev.functions[0].configure_bar(2, 2**24) + self.dev.functions[0].configure_bar(0, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axil_ctrl_awaddr)) + self.dev.functions[0].configure_bar(2, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axi_ram_awaddr)) async def init(self): diff --git a/example/S10MX_DK/fpga/tb/fpga_core/test_fpga_core.py b/example/S10MX_DK/fpga/tb/fpga_core/test_fpga_core.py index b9198d503..87888d60c 100644 --- a/example/S10MX_DK/fpga/tb/fpga_core/test_fpga_core.py +++ b/example/S10MX_DK/fpga/tb/fpga_core/test_fpga_core.py @@ -33,7 +33,6 @@ from cocotb.triggers import RisingEdge, FallingEdge, Timer from cocotbext.pcie.core import RootComplex from cocotbext.pcie.intel.s10 import S10PcieDevice, S10RxBus, S10TxBus -from cocotbext.axi.utils import hexdump_str class TB(object): @@ -156,8 +155,8 @@ class TB(object): self.dev.functions[0].msi_multiple_message_capable = 5 - self.dev.functions[0].configure_bar(0, 2**22) - self.dev.functions[0].configure_bar(2, 2**22) + self.dev.functions[0].configure_bar(0, 2**len(dut.example_core_pcie_s10_inst.core_pcie_inst.axil_ctrl_awaddr)) + self.dev.functions[0].configure_bar(2, 2**len(dut.example_core_pcie_s10_inst.core_pcie_inst.axi_ram_awaddr)) async def init(self): diff --git a/example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py b/example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py index 6a421b60a..6c5b428d1 100644 --- a/example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py +++ b/example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py @@ -34,7 +34,6 @@ from cocotb.triggers import RisingEdge, FallingEdge, Timer from cocotbext.axi import AxiStreamBus from cocotbext.pcie.core import RootComplex from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice -from cocotbext.axi.utils import hexdump_str class TB(object): @@ -234,8 +233,8 @@ class TB(object): self.dev.functions[0].msi_multiple_message_capable = 5 - self.dev.functions[0].configure_bar(0, 2**22) - self.dev.functions[0].configure_bar(2, 2**22) + self.dev.functions[0].configure_bar(0, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axil_ctrl_awaddr)) + self.dev.functions[0].configure_bar(2, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axi_ram_awaddr)) async def init(self):