From 66708ed6ff12fbdd14dde54ed1c2fb8bcb19273e Mon Sep 17 00:00:00 2001
From: Alex Forencich <alex@alexforencich.com>
Date: Mon, 14 Feb 2022 00:41:28 -0800
Subject: [PATCH] Add some more parameter checks

---
 fpga/common/rtl/rx_engine.v | 5 +++++
 fpga/common/rtl/tx_engine.v | 5 +++++
 2 files changed, 10 insertions(+)

diff --git a/fpga/common/rtl/rx_engine.v b/fpga/common/rtl/rx_engine.v
index 59610f502..8ef5078f3 100644
--- a/fpga/common/rtl/rx_engine.v
+++ b/fpga/common/rtl/rx_engine.v
@@ -264,6 +264,11 @@ initial begin
         $error("Error: DESC_REQ_TAG_WIDTH must be at least $clog2(DESC_TABLE_SIZE) (instance %m)");
         $finish;
     end
+
+    if (RAM_ADDR_WIDTH < CL_RX_BUFFER_SIZE) begin
+        $error("Error: RAM_ADDR_WIDTH insufficient for buffer size (instance %m)");
+        $finish;
+    end
 end
 
 reg s_axis_rx_req_ready_reg = 1'b0, s_axis_rx_req_ready_next;
diff --git a/fpga/common/rtl/tx_engine.v b/fpga/common/rtl/tx_engine.v
index 7fd07ffb5..eb185ab14 100644
--- a/fpga/common/rtl/tx_engine.v
+++ b/fpga/common/rtl/tx_engine.v
@@ -270,6 +270,11 @@ initial begin
         $error("Error: QUEUE_REQ_TAG_WIDTH must be at least REQ_TAG_WIDTH (instance %m)");
         $finish;
     end
+
+    if (RAM_ADDR_WIDTH < CL_TX_BUFFER_SIZE) begin
+        $error("Error: RAM_ADDR_WIDTH insufficient for buffer size (instance %m)");
+        $finish;
+    end
 end
 
 reg s_axis_tx_req_ready_reg = 1'b0, s_axis_tx_req_ready_next;