From 66987c8f62de33401c7b84945a5814ddbf6f0948 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Sat, 26 Aug 2023 01:08:32 -0700 Subject: [PATCH] Use quad wrappers in AU280 example design Signed-off-by: Alex Forencich --- example/AU280/fpga_25g/fpga.xdc | 64 +- example/AU280/fpga_25g/fpga/Makefile | 1 + example/AU280/fpga_25g/fpga_10g/Makefile | 1 + .../fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v | 395 ++++++++++++ .../AU280/fpga_25g/rtl/eth_xcvr_phy_wrapper.v | 18 +- example/AU280/fpga_25g/rtl/fpga.v | 566 ++++++------------ 6 files changed, 620 insertions(+), 425 deletions(-) create mode 100644 example/AU280/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v diff --git a/example/AU280/fpga_25g/fpga.xdc b/example/AU280/fpga_25g/fpga.xdc index ff6be120e..0c65a0b72 100644 --- a/example/AU280/fpga_25g/fpga.xdc +++ b/example/AU280/fpga_25g/fpga.xdc @@ -60,22 +60,22 @@ set_false_path -to [get_ports {hbm_cattrip}] set_output_delay 0 [get_ports {hbm_cattrip}] # QSFP28 Interfaces -set_property -dict {LOC L53 } [get_ports qsfp0_rx1_p] ;# MGTYRXP0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC L54 } [get_ports qsfp0_rx1_n] ;# MGTYRXN0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC L48 } [get_ports qsfp0_tx1_p] ;# MGTYTXP0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC L49 } [get_ports qsfp0_tx1_n] ;# MGTYTXN0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC K51 } [get_ports qsfp0_rx2_p] ;# MGTYRXP1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC K52 } [get_ports qsfp0_rx2_n] ;# MGTYRXN1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC L44 } [get_ports qsfp0_tx2_p] ;# MGTYTXP1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC L45 } [get_ports qsfp0_tx2_n] ;# MGTYTXN1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC J53 } [get_ports qsfp0_rx3_p] ;# MGTYRXP2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC J54 } [get_ports qsfp0_rx3_n] ;# MGTYRXN2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC K46 } [get_ports qsfp0_tx3_p] ;# MGTYTXP2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC K47 } [get_ports qsfp0_tx3_n] ;# MGTYTXN2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC H51 } [get_ports qsfp0_rx4_p] ;# MGTYRXP3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC H52 } [get_ports qsfp0_rx4_n] ;# MGTYRXN3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC J48 } [get_ports qsfp0_tx4_p] ;# MGTYTXP3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10 -set_property -dict {LOC J49 } [get_ports qsfp0_tx4_n] ;# MGTYTXN3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC L53 } [get_ports {qsfp0_rx_p[0]}] ;# MGTYRXP0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC L54 } [get_ports {qsfp0_rx_n[0]}] ;# MGTYRXN0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC L48 } [get_ports {qsfp0_tx_p[0]}] ;# MGTYTXP0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC L49 } [get_ports {qsfp0_tx_n[0]}] ;# MGTYTXN0_134 GTYE4_CHANNEL_X0Y40 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC K51 } [get_ports {qsfp0_rx_p[1]}] ;# MGTYRXP1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC K52 } [get_ports {qsfp0_rx_n[1]}] ;# MGTYRXN1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC L44 } [get_ports {qsfp0_tx_p[1]}] ;# MGTYTXP1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC L45 } [get_ports {qsfp0_tx_n[1]}] ;# MGTYTXN1_134 GTYE4_CHANNEL_X0Y41 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC J53 } [get_ports {qsfp0_rx_p[2]}] ;# MGTYRXP2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC J54 } [get_ports {qsfp0_rx_n[2]}] ;# MGTYRXN2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC K46 } [get_ports {qsfp0_tx_p[2]}] ;# MGTYTXP2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC K47 } [get_ports {qsfp0_tx_n[2]}] ;# MGTYTXN2_134 GTYE4_CHANNEL_X0Y42 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC H51 } [get_ports {qsfp0_rx_p[3]}] ;# MGTYRXP3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC H52 } [get_ports {qsfp0_rx_n[3]}] ;# MGTYRXN3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC J48 } [get_ports {qsfp0_tx_p[3]}] ;# MGTYTXP3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10 +set_property -dict {LOC J49 } [get_ports {qsfp0_tx_n[3]}] ;# MGTYTXN3_134 GTYE4_CHANNEL_X0Y43 / GTYE4_COMMON_X0Y10 #set_property -dict {LOC T42 } [get_ports qsfp0_mgt_refclk_0_p] ;# MGTREFCLK0P_134 from SI570 #set_property -dict {LOC T43 } [get_ports qsfp0_mgt_refclk_0_n] ;# MGTREFCLK0N_134 from SI570 set_property -dict {LOC R40 } [get_ports qsfp0_mgt_refclk_1_p] ;# MGTREFCLK1P_134 from SI546 @@ -95,22 +95,22 @@ create_clock -period 6.206 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_ set_false_path -to [get_ports {qsfp0_refclk_oe_b qsfp0_refclk_fs}] set_output_delay 0 [get_ports {qsfp0_refclk_oe_b qsfp0_refclk_fs}] -set_property -dict {LOC G53 } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC G54 } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC G48 } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC G49 } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC F51 } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC F52 } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC E48 } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC E49 } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC E53 } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC E54 } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC C48 } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC C49 } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC D51 } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC D52 } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC A49 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11 -set_property -dict {LOC A50 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC G53 } [get_ports {qsfp1_rx_p[0]}] ;# MGTYRXP0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC G54 } [get_ports {qsfp1_rx_n[0]}] ;# MGTYRXN0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC G48 } [get_ports {qsfp1_tx_p[0]}] ;# MGTYTXP0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC G49 } [get_ports {qsfp1_tx_n[0]}] ;# MGTYTXN0_135 GTYE4_CHANNEL_X0Y44 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC F51 } [get_ports {qsfp1_rx_p[1]}] ;# MGTYRXP1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC F52 } [get_ports {qsfp1_rx_n[1]}] ;# MGTYRXN1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC E48 } [get_ports {qsfp1_tx_p[1]}] ;# MGTYTXP1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC E49 } [get_ports {qsfp1_tx_n[1]}] ;# MGTYTXN1_135 GTYE4_CHANNEL_X0Y45 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC E53 } [get_ports {qsfp1_rx_p[2]}] ;# MGTYRXP2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC E54 } [get_ports {qsfp1_rx_n[2]}] ;# MGTYRXN2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC C48 } [get_ports {qsfp1_tx_p[2]}] ;# MGTYTXP2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC C49 } [get_ports {qsfp1_tx_n[2]}] ;# MGTYTXN2_135 GTYE4_CHANNEL_X0Y46 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC D51 } [get_ports {qsfp1_rx_p[3]}] ;# MGTYRXP3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC D52 } [get_ports {qsfp1_rx_n[3]}] ;# MGTYRXN3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC A49 } [get_ports {qsfp1_tx_p[3]}] ;# MGTYTXP3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11 +set_property -dict {LOC A50 } [get_ports {qsfp1_tx_n[3]}] ;# MGTYTXN3_135 GTYE4_CHANNEL_X0Y47 / GTYE4_COMMON_X0Y11 #set_property -dict {LOC P42 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_135 from SI570 #set_property -dict {LOC P43 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_135 from SI570 set_property -dict {LOC M42 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_135 from SI546 diff --git a/example/AU280/fpga_25g/fpga/Makefile b/example/AU280/fpga_25g/fpga/Makefile index 158a27cd0..0cb457f14 100644 --- a/example/AU280/fpga_25g/fpga/Makefile +++ b/example/AU280/fpga_25g/fpga/Makefile @@ -8,6 +8,7 @@ FPGA_ARCH = virtexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v SYN_FILES += rtl/sync_signal.v SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v SYN_FILES += lib/eth/rtl/eth_mac_10g.v diff --git a/example/AU280/fpga_25g/fpga_10g/Makefile b/example/AU280/fpga_25g/fpga_10g/Makefile index 158a27cd0..0cb457f14 100644 --- a/example/AU280/fpga_25g/fpga_10g/Makefile +++ b/example/AU280/fpga_25g/fpga_10g/Makefile @@ -8,6 +8,7 @@ FPGA_ARCH = virtexuplus SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/eth_xcvr_phy_wrapper.v +SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v SYN_FILES += rtl/sync_signal.v SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v SYN_FILES += lib/eth/rtl/eth_mac_10g.v diff --git a/example/AU280/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v b/example/AU280/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v new file mode 100644 index 000000000..c910d7906 --- /dev/null +++ b/example/AU280/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v @@ -0,0 +1,395 @@ +/* + +Copyright (c) 2023 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * Transceiver and PHY quad wrapper + */ +module eth_xcvr_phy_quad_wrapper # +( + parameter COUNT = 4, + parameter DATA_WIDTH = 64, + parameter CTRL_WIDTH = (DATA_WIDTH/8), + parameter HDR_WIDTH = 2, + parameter PRBS31_ENABLE = 0, + parameter TX_SERDES_PIPELINE = 0, + parameter RX_SERDES_PIPELINE = 0, + parameter BITSLIP_HIGH_CYCLES = 1, + parameter BITSLIP_LOW_CYCLES = 8, + parameter COUNT_125US = 125000/6.4 +) +( + input wire xcvr_ctrl_clk, + input wire xcvr_ctrl_rst, + + /* + * Common + */ + output wire xcvr_gtpowergood_out, + + /* + * PLL + */ + input wire xcvr_gtrefclk00_in, + + /* + * Serial data + */ + output wire [COUNT-1:0] xcvr_txp, + output wire [COUNT-1:0] xcvr_txn, + input wire [COUNT-1:0] xcvr_rxp, + input wire [COUNT-1:0] xcvr_rxn, + + /* + * PHY connections + */ + output wire phy_1_tx_clk, + output wire phy_1_tx_rst, + input wire [DATA_WIDTH-1:0] phy_1_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_1_xgmii_txc, + output wire phy_1_rx_clk, + output wire phy_1_rx_rst, + output wire [DATA_WIDTH-1:0] phy_1_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_1_xgmii_rxc, + output wire phy_1_tx_bad_block, + output wire [6:0] phy_1_rx_error_count, + output wire phy_1_rx_bad_block, + output wire phy_1_rx_sequence_error, + output wire phy_1_rx_block_lock, + output wire phy_1_rx_high_ber, + output wire phy_1_rx_status, + input wire phy_1_cfg_tx_prbs31_enable, + input wire phy_1_cfg_rx_prbs31_enable, + + output wire phy_2_tx_clk, + output wire phy_2_tx_rst, + input wire [DATA_WIDTH-1:0] phy_2_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_2_xgmii_txc, + output wire phy_2_rx_clk, + output wire phy_2_rx_rst, + output wire [DATA_WIDTH-1:0] phy_2_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_2_xgmii_rxc, + output wire phy_2_tx_bad_block, + output wire [6:0] phy_2_rx_error_count, + output wire phy_2_rx_bad_block, + output wire phy_2_rx_sequence_error, + output wire phy_2_rx_block_lock, + output wire phy_2_rx_high_ber, + output wire phy_2_rx_status, + input wire phy_2_cfg_tx_prbs31_enable, + input wire phy_2_cfg_rx_prbs31_enable, + + output wire phy_3_tx_clk, + output wire phy_3_tx_rst, + input wire [DATA_WIDTH-1:0] phy_3_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_3_xgmii_txc, + output wire phy_3_rx_clk, + output wire phy_3_rx_rst, + output wire [DATA_WIDTH-1:0] phy_3_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_3_xgmii_rxc, + output wire phy_3_tx_bad_block, + output wire [6:0] phy_3_rx_error_count, + output wire phy_3_rx_bad_block, + output wire phy_3_rx_sequence_error, + output wire phy_3_rx_block_lock, + output wire phy_3_rx_high_ber, + output wire phy_3_rx_status, + input wire phy_3_cfg_tx_prbs31_enable, + input wire phy_3_cfg_rx_prbs31_enable, + + output wire phy_4_tx_clk, + output wire phy_4_tx_rst, + input wire [DATA_WIDTH-1:0] phy_4_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_4_xgmii_txc, + output wire phy_4_rx_clk, + output wire phy_4_rx_rst, + output wire [DATA_WIDTH-1:0] phy_4_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_4_xgmii_rxc, + output wire phy_4_tx_bad_block, + output wire [6:0] phy_4_rx_error_count, + output wire phy_4_rx_bad_block, + output wire phy_4_rx_sequence_error, + output wire phy_4_rx_block_lock, + output wire phy_4_rx_high_ber, + output wire phy_4_rx_status, + input wire phy_4_cfg_tx_prbs31_enable, + input wire phy_4_cfg_rx_prbs31_enable +); + +generate + +wire xcvr_qpll0lock; +wire xcvr_qpll0clk; +wire xcvr_qpll0refclk; + +if (COUNT > 0) begin : phy1 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(1), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_1 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(xcvr_gtpowergood_out), + + // PLL out + .xcvr_gtrefclk00_in(xcvr_gtrefclk00_in), + .xcvr_qpll0lock_out(xcvr_qpll0lock), + .xcvr_qpll0clk_out(xcvr_qpll0clk), + .xcvr_qpll0refclk_out(xcvr_qpll0refclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(xcvr_txp[0]), + .xcvr_txn(xcvr_txn[0]), + .xcvr_rxp(xcvr_rxp[0]), + .xcvr_rxn(xcvr_rxn[0]), + + // PHY connections + .phy_tx_clk(phy_1_tx_clk), + .phy_tx_rst(phy_1_tx_rst), + .phy_xgmii_txd(phy_1_xgmii_txd), + .phy_xgmii_txc(phy_1_xgmii_txc), + .phy_rx_clk(phy_1_rx_clk), + .phy_rx_rst(phy_1_rx_rst), + .phy_xgmii_rxd(phy_1_xgmii_rxd), + .phy_xgmii_rxc(phy_1_xgmii_rxc), + .phy_tx_bad_block(phy_1_tx_bad_block), + .phy_rx_error_count(phy_1_rx_error_count), + .phy_rx_bad_block(phy_1_rx_bad_block), + .phy_rx_sequence_error(phy_1_rx_sequence_error), + .phy_rx_block_lock(phy_1_rx_block_lock), + .phy_rx_high_ber(phy_1_rx_high_ber), + .phy_rx_status(phy_1_rx_status), + .phy_cfg_tx_prbs31_enable(phy_1_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_1_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 1) begin : phy2 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_2 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[1]), + .xcvr_txn(xcvr_txn[1]), + .xcvr_rxp(xcvr_rxp[1]), + .xcvr_rxn(xcvr_rxn[1]), + + // PHY connections + .phy_tx_clk(phy_2_tx_clk), + .phy_tx_rst(phy_2_tx_rst), + .phy_xgmii_txd(phy_2_xgmii_txd), + .phy_xgmii_txc(phy_2_xgmii_txc), + .phy_rx_clk(phy_2_rx_clk), + .phy_rx_rst(phy_2_rx_rst), + .phy_xgmii_rxd(phy_2_xgmii_rxd), + .phy_xgmii_rxc(phy_2_xgmii_rxc), + .phy_tx_bad_block(phy_2_tx_bad_block), + .phy_rx_error_count(phy_2_rx_error_count), + .phy_rx_bad_block(phy_2_rx_bad_block), + .phy_rx_sequence_error(phy_2_rx_sequence_error), + .phy_rx_block_lock(phy_2_rx_block_lock), + .phy_rx_high_ber(phy_2_rx_high_ber), + .phy_rx_status(phy_2_rx_status), + .phy_cfg_tx_prbs31_enable(phy_2_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_2_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 2) begin : phy3 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_3 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[2]), + .xcvr_txn(xcvr_txn[2]), + .xcvr_rxp(xcvr_rxp[2]), + .xcvr_rxn(xcvr_rxn[2]), + + // PHY connections + .phy_tx_clk(phy_3_tx_clk), + .phy_tx_rst(phy_3_tx_rst), + .phy_xgmii_txd(phy_3_xgmii_txd), + .phy_xgmii_txc(phy_3_xgmii_txc), + .phy_rx_clk(phy_3_rx_clk), + .phy_rx_rst(phy_3_rx_rst), + .phy_xgmii_rxd(phy_3_xgmii_rxd), + .phy_xgmii_rxc(phy_3_xgmii_rxc), + .phy_tx_bad_block(phy_3_tx_bad_block), + .phy_rx_error_count(phy_3_rx_error_count), + .phy_rx_bad_block(phy_3_rx_bad_block), + .phy_rx_sequence_error(phy_3_rx_sequence_error), + .phy_rx_block_lock(phy_3_rx_block_lock), + .phy_rx_high_ber(phy_3_rx_high_ber), + .phy_rx_status(phy_3_rx_status), + .phy_cfg_tx_prbs31_enable(phy_3_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_3_cfg_rx_prbs31_enable) + ); + +end + +if (COUNT > 3) begin : phy4 + + eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) + ) + eth_xcvr_phy_4 ( + .xcvr_ctrl_clk(xcvr_ctrl_clk), + .xcvr_ctrl_rst(xcvr_ctrl_rst), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0clk_out(), + .xcvr_qpll0refclk_out(), + + // PLL in + .xcvr_qpll0lock_in(xcvr_qpll0lock), + .xcvr_qpll0clk_in(xcvr_qpll0clk), + .xcvr_qpll0refclk_in(xcvr_qpll0refclk), + + // Serial data + .xcvr_txp(xcvr_txp[3]), + .xcvr_txn(xcvr_txn[3]), + .xcvr_rxp(xcvr_rxp[3]), + .xcvr_rxn(xcvr_rxn[3]), + + // PHY connections + .phy_tx_clk(phy_4_tx_clk), + .phy_tx_rst(phy_4_tx_rst), + .phy_xgmii_txd(phy_4_xgmii_txd), + .phy_xgmii_txc(phy_4_xgmii_txc), + .phy_rx_clk(phy_4_rx_clk), + .phy_rx_rst(phy_4_rx_rst), + .phy_xgmii_rxd(phy_4_xgmii_rxd), + .phy_xgmii_rxc(phy_4_xgmii_rxc), + .phy_tx_bad_block(phy_4_tx_bad_block), + .phy_rx_error_count(phy_4_rx_error_count), + .phy_rx_bad_block(phy_4_rx_bad_block), + .phy_rx_sequence_error(phy_4_rx_sequence_error), + .phy_rx_block_lock(phy_4_rx_block_lock), + .phy_rx_high_ber(phy_4_rx_high_ber), + .phy_rx_status(phy_4_rx_status), + .phy_cfg_tx_prbs31_enable(phy_4_cfg_tx_prbs31_enable), + .phy_cfg_rx_prbs31_enable(phy_4_cfg_rx_prbs31_enable) + ); + +end + +endgenerate + +endmodule + +`resetall diff --git a/example/AU280/fpga_25g/rtl/eth_xcvr_phy_wrapper.v b/example/AU280/fpga_25g/rtl/eth_xcvr_phy_wrapper.v index c898dcabe..0d1142eb6 100644 --- a/example/AU280/fpga_25g/rtl/eth_xcvr_phy_wrapper.v +++ b/example/AU280/fpga_25g/rtl/eth_xcvr_phy_wrapper.v @@ -1,6 +1,6 @@ /* -Copyright (c) 2021 Alex Forencich +Copyright (c) 2021-2023 Alex Forencich Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal @@ -58,8 +58,8 @@ module eth_xcvr_phy_wrapper # */ input wire xcvr_gtrefclk00_in, output wire xcvr_qpll0lock_out, - output wire xcvr_qpll0outclk_out, - output wire xcvr_qpll0outrefclk_out, + output wire xcvr_qpll0clk_out, + output wire xcvr_qpll0refclk_out, /* * PLL in @@ -94,6 +94,7 @@ module eth_xcvr_phy_wrapper # output wire phy_rx_sequence_error, output wire phy_rx_block_lock, output wire phy_rx_high_ber, + output wire phy_rx_status, input wire phy_cfg_tx_prbs31_enable, input wire phy_cfg_rx_prbs31_enable ); @@ -128,8 +129,8 @@ if (HAS_COMMON) begin : xcvr // PLL .gtrefclk00_in(xcvr_gtrefclk00_in), .qpll0lock_out(xcvr_qpll0lock_out), - .qpll0outclk_out(xcvr_qpll0outclk_out), - .qpll0outrefclk_out(xcvr_qpll0outrefclk_out), + .qpll0outclk_out(xcvr_qpll0clk_out), + .qpll0outrefclk_out(xcvr_qpll0refclk_out), // Serial data .gtytxp_out(xcvr_txp), @@ -174,6 +175,8 @@ if (HAS_COMMON) begin : xcvr .rxstartofseq_out() ); + assign xcvr_qpll0reset_out = 1'b0; + end else begin : xcvr eth_xcvr_gt_channel @@ -234,6 +237,10 @@ end else begin : xcvr .rxstartofseq_out() ); + assign xcvr_qpll0lock_out = 1'b0; + assign xcvr_qpll0clk_out = 1'b0; + assign xcvr_qpll0refclk_out = 1'b0; + end endgenerate @@ -290,6 +297,7 @@ phy_inst ( .rx_sequence_error(phy_rx_sequence_error), .rx_block_lock(phy_rx_block_lock), .rx_high_ber(phy_rx_high_ber), + .rx_status(phy_rx_status), .cfg_tx_prbs31_enable(phy_cfg_tx_prbs31_enable), .cfg_rx_prbs31_enable(phy_cfg_rx_prbs31_enable) ); diff --git a/example/AU280/fpga_25g/rtl/fpga.v b/example/AU280/fpga_25g/rtl/fpga.v index e67a86339..634923269 100644 --- a/example/AU280/fpga_25g/rtl/fpga.v +++ b/example/AU280/fpga_25g/rtl/fpga.v @@ -45,22 +45,10 @@ module fpga ( /* * Ethernet: QSFP28 */ - output wire qsfp0_tx1_p, - output wire qsfp0_tx1_n, - input wire qsfp0_rx1_p, - input wire qsfp0_rx1_n, - output wire qsfp0_tx2_p, - output wire qsfp0_tx2_n, - input wire qsfp0_rx2_p, - input wire qsfp0_rx2_n, - output wire qsfp0_tx3_p, - output wire qsfp0_tx3_n, - input wire qsfp0_rx3_p, - input wire qsfp0_rx3_n, - output wire qsfp0_tx4_p, - output wire qsfp0_tx4_n, - input wire qsfp0_rx4_p, - input wire qsfp0_rx4_n, + output wire [3:0] qsfp0_tx_p, + output wire [3:0] qsfp0_tx_n, + input wire [3:0] qsfp0_rx_p, + input wire [3:0] qsfp0_rx_n, // input wire qsfp0_mgt_refclk_0_p, // input wire qsfp0_mgt_refclk_0_n, input wire qsfp0_mgt_refclk_1_p, @@ -68,22 +56,10 @@ module fpga ( output wire qsfp0_refclk_oe_b, output wire qsfp0_refclk_fs, - output wire qsfp1_tx1_p, - output wire qsfp1_tx1_n, - input wire qsfp1_rx1_p, - input wire qsfp1_rx1_n, - output wire qsfp1_tx2_p, - output wire qsfp1_tx2_n, - input wire qsfp1_rx2_p, - input wire qsfp1_rx2_n, - output wire qsfp1_tx3_p, - output wire qsfp1_tx3_n, - input wire qsfp1_rx3_p, - input wire qsfp1_rx3_n, - output wire qsfp1_tx4_p, - output wire qsfp1_tx4_n, - input wire qsfp1_rx4_p, - input wire qsfp1_rx4_n, + output wire [3:0] qsfp1_tx_p, + output wire [3:0] qsfp1_tx_n, + input wire [3:0] qsfp1_rx_p, + input wire [3:0] qsfp1_rx_n, // input wire qsfp1_mgt_refclk_0_p, // input wire qsfp1_mgt_refclk_0_n, input wire qsfp1_mgt_refclk_1_p, @@ -258,196 +234,103 @@ BUFG_GT bufg_gt_refclk_inst ( .O (qsfp0_mgt_refclk_1_bufg) ); -wire qsfp0_qpll0lock; -wire qsfp0_qpll0outclk; -wire qsfp0_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) +eth_xcvr_phy_quad_wrapper #( + .TX_SERDES_PIPELINE(2), + .RX_SERDES_PIPELINE(2), + .COUNT_125US(125000/2.56) ) -qsfp0_phy_1_inst ( +qsfp0_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(rst_125mhz_int), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(qsfp0_gtpowergood), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(qsfp0_mgt_refclk_1), - .xcvr_qpll0lock_out(qsfp0_qpll0lock), - .xcvr_qpll0outclk_out(qsfp0_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp0_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp0_tx_p), + .xcvr_txn(qsfp0_tx_n), + .xcvr_rxp(qsfp0_rx_p), + .xcvr_rxn(qsfp0_rx_n), - // Serial data - .xcvr_txp(qsfp0_tx1_p), - .xcvr_txn(qsfp0_tx1_n), - .xcvr_rxp(qsfp0_rx1_p), - .xcvr_rxn(qsfp0_rx1_n), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp0_tx_clk_1_int), + .phy_1_tx_rst(qsfp0_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp0_txd_1_int), + .phy_1_xgmii_txc(qsfp0_txc_1_int), + .phy_1_rx_clk(qsfp0_rx_clk_1_int), + .phy_1_rx_rst(qsfp0_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp0_rxd_1_int), + .phy_1_xgmii_rxc(qsfp0_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp0_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp0_tx_clk_1_int), - .phy_tx_rst(qsfp0_tx_rst_1_int), - .phy_xgmii_txd(qsfp0_txd_1_int), - .phy_xgmii_txc(qsfp0_txc_1_int), - .phy_rx_clk(qsfp0_rx_clk_1_int), - .phy_rx_rst(qsfp0_rx_rst_1_int), - .phy_xgmii_rxd(qsfp0_rxd_1_int), - .phy_xgmii_rxc(qsfp0_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp0_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp0_tx_clk_2_int), + .phy_2_tx_rst(qsfp0_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp0_txd_2_int), + .phy_2_xgmii_txc(qsfp0_txc_2_int), + .phy_2_rx_clk(qsfp0_rx_clk_2_int), + .phy_2_rx_rst(qsfp0_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp0_rxd_2_int), + .phy_2_xgmii_rxc(qsfp0_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp0_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp0_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), + .phy_3_tx_clk(qsfp0_tx_clk_3_int), + .phy_3_tx_rst(qsfp0_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp0_txd_3_int), + .phy_3_xgmii_txc(qsfp0_txc_3_int), + .phy_3_rx_clk(qsfp0_rx_clk_3_int), + .phy_3_rx_rst(qsfp0_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp0_rxd_3_int), + .phy_3_xgmii_rxc(qsfp0_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp0_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp0_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp0_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp0_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp0_tx2_p), - .xcvr_txn(qsfp0_tx2_n), - .xcvr_rxp(qsfp0_rx2_p), - .xcvr_rxn(qsfp0_rx2_n), - - // PHY connections - .phy_tx_clk(qsfp0_tx_clk_2_int), - .phy_tx_rst(qsfp0_tx_rst_2_int), - .phy_xgmii_txd(qsfp0_txd_2_int), - .phy_xgmii_txc(qsfp0_txc_2_int), - .phy_rx_clk(qsfp0_rx_clk_2_int), - .phy_rx_rst(qsfp0_rx_rst_2_int), - .phy_xgmii_rxd(qsfp0_rxd_2_int), - .phy_xgmii_rxc(qsfp0_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp0_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp0_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp0_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp0_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp0_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp0_tx3_p), - .xcvr_txn(qsfp0_tx3_n), - .xcvr_rxp(qsfp0_rx3_p), - .xcvr_rxn(qsfp0_rx3_n), - - // PHY connections - .phy_tx_clk(qsfp0_tx_clk_3_int), - .phy_tx_rst(qsfp0_tx_rst_3_int), - .phy_xgmii_txd(qsfp0_txd_3_int), - .phy_xgmii_txc(qsfp0_txc_3_int), - .phy_rx_clk(qsfp0_rx_clk_3_int), - .phy_rx_rst(qsfp0_rx_rst_3_int), - .phy_xgmii_rxd(qsfp0_rxd_3_int), - .phy_xgmii_rxc(qsfp0_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp0_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp0_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp0_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp0_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp0_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp0_tx4_p), - .xcvr_txn(qsfp0_tx4_n), - .xcvr_rxp(qsfp0_rx4_p), - .xcvr_rxn(qsfp0_rx4_n), - - // PHY connections - .phy_tx_clk(qsfp0_tx_clk_4_int), - .phy_tx_rst(qsfp0_tx_rst_4_int), - .phy_xgmii_txd(qsfp0_txd_4_int), - .phy_xgmii_txc(qsfp0_txc_4_int), - .phy_rx_clk(qsfp0_rx_clk_4_int), - .phy_rx_rst(qsfp0_rx_rst_4_int), - .phy_xgmii_rxd(qsfp0_rxd_4_int), - .phy_xgmii_rxc(qsfp0_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp0_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp0_tx_clk_4_int), + .phy_4_tx_rst(qsfp0_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp0_txd_4_int), + .phy_4_xgmii_txc(qsfp0_txc_4_int), + .phy_4_rx_clk(qsfp0_rx_clk_4_int), + .phy_4_rx_rst(qsfp0_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp0_rxd_4_int), + .phy_4_xgmii_rxc(qsfp0_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp0_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); // QSFP1 @@ -502,196 +385,103 @@ IBUFDS_GTE4 ibufds_gte4_qsfp1_mgt_refclk_1_inst ( .ODIV2 () ); -wire qsfp1_qpll0lock; -wire qsfp1_qpll0outclk; -wire qsfp1_qpll0outrefclk; - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(1) +eth_xcvr_phy_quad_wrapper #( + .TX_SERDES_PIPELINE(2), + .RX_SERDES_PIPELINE(2), + .COUNT_125US(125000/2.56) ) -qsfp1_phy_1_inst ( +qsfp1_phy_inst ( .xcvr_ctrl_clk(clk_125mhz_int), .xcvr_ctrl_rst(rst_125mhz_int), - // Common + /* + * Common + */ .xcvr_gtpowergood_out(), - // PLL out + /* + * PLL + */ .xcvr_gtrefclk00_in(qsfp1_mgt_refclk_1), - .xcvr_qpll0lock_out(qsfp1_qpll0lock), - .xcvr_qpll0outclk_out(qsfp1_qpll0outclk), - .xcvr_qpll0outrefclk_out(qsfp1_qpll0outrefclk), - // PLL in - .xcvr_qpll0lock_in(1'b0), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(1'b0), - .xcvr_qpll0refclk_in(1'b0), + /* + * Serial data + */ + .xcvr_txp(qsfp1_tx_p), + .xcvr_txn(qsfp1_tx_n), + .xcvr_rxp(qsfp1_rx_p), + .xcvr_rxn(qsfp1_rx_n), - // Serial data - .xcvr_txp(qsfp1_tx1_p), - .xcvr_txn(qsfp1_tx1_n), - .xcvr_rxp(qsfp1_rx1_p), - .xcvr_rxn(qsfp1_rx1_n), + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp1_tx_clk_1_int), + .phy_1_tx_rst(qsfp1_tx_rst_1_int), + .phy_1_xgmii_txd(qsfp1_txd_1_int), + .phy_1_xgmii_txc(qsfp1_txc_1_int), + .phy_1_rx_clk(qsfp1_rx_clk_1_int), + .phy_1_rx_rst(qsfp1_rx_rst_1_int), + .phy_1_xgmii_rxd(qsfp1_rxd_1_int), + .phy_1_xgmii_rxc(qsfp1_rxc_1_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp1_rx_block_lock_1), + .phy_1_rx_status(), + .phy_1_cfg_tx_prbs31_enable(1'b0), + .phy_1_cfg_rx_prbs31_enable(1'b0), - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_1_int), - .phy_tx_rst(qsfp1_tx_rst_1_int), - .phy_xgmii_txd(qsfp1_txd_1_int), - .phy_xgmii_txc(qsfp1_txc_1_int), - .phy_rx_clk(qsfp1_rx_clk_1_int), - .phy_rx_rst(qsfp1_rx_rst_1_int), - .phy_xgmii_rxd(qsfp1_rxd_1_int), - .phy_xgmii_rxc(qsfp1_rxc_1_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_1), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); + .phy_2_tx_clk(qsfp1_tx_clk_2_int), + .phy_2_tx_rst(qsfp1_tx_rst_2_int), + .phy_2_xgmii_txd(qsfp1_txd_2_int), + .phy_2_xgmii_txc(qsfp1_txc_2_int), + .phy_2_rx_clk(qsfp1_rx_clk_2_int), + .phy_2_rx_rst(qsfp1_rx_rst_2_int), + .phy_2_xgmii_rxd(qsfp1_rxd_2_int), + .phy_2_xgmii_rxc(qsfp1_rxc_2_int), + .phy_2_tx_bad_block(), + .phy_2_rx_error_count(), + .phy_2_rx_bad_block(), + .phy_2_rx_sequence_error(), + .phy_2_rx_block_lock(qsfp1_rx_block_lock_2), + .phy_2_rx_status(), + .phy_2_cfg_tx_prbs31_enable(1'b0), + .phy_2_cfg_rx_prbs31_enable(1'b0), -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp1_phy_2_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), + .phy_3_tx_clk(qsfp1_tx_clk_3_int), + .phy_3_tx_rst(qsfp1_tx_rst_3_int), + .phy_3_xgmii_txd(qsfp1_txd_3_int), + .phy_3_xgmii_txc(qsfp1_txc_3_int), + .phy_3_rx_clk(qsfp1_rx_clk_3_int), + .phy_3_rx_rst(qsfp1_rx_rst_3_int), + .phy_3_xgmii_rxd(qsfp1_rxd_3_int), + .phy_3_xgmii_rxc(qsfp1_rxc_3_int), + .phy_3_tx_bad_block(), + .phy_3_rx_error_count(), + .phy_3_rx_bad_block(), + .phy_3_rx_sequence_error(), + .phy_3_rx_block_lock(qsfp1_rx_block_lock_3), + .phy_3_rx_status(), + .phy_3_cfg_tx_prbs31_enable(1'b0), + .phy_3_cfg_rx_prbs31_enable(1'b0), - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp1_tx2_p), - .xcvr_txn(qsfp1_tx2_n), - .xcvr_rxp(qsfp1_rx2_p), - .xcvr_rxn(qsfp1_rx2_n), - - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_2_int), - .phy_tx_rst(qsfp1_tx_rst_2_int), - .phy_xgmii_txd(qsfp1_txd_2_int), - .phy_xgmii_txc(qsfp1_txc_2_int), - .phy_rx_clk(qsfp1_rx_clk_2_int), - .phy_rx_rst(qsfp1_rx_rst_2_int), - .phy_xgmii_rxd(qsfp1_rxd_2_int), - .phy_xgmii_rxc(qsfp1_rxc_2_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_2), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp1_phy_3_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp1_tx3_p), - .xcvr_txn(qsfp1_tx3_n), - .xcvr_rxp(qsfp1_rx3_p), - .xcvr_rxn(qsfp1_rx3_n), - - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_3_int), - .phy_tx_rst(qsfp1_tx_rst_3_int), - .phy_xgmii_txd(qsfp1_txd_3_int), - .phy_xgmii_txc(qsfp1_txc_3_int), - .phy_rx_clk(qsfp1_rx_clk_3_int), - .phy_rx_rst(qsfp1_rx_rst_3_int), - .phy_xgmii_rxd(qsfp1_rxd_3_int), - .phy_xgmii_rxc(qsfp1_rxc_3_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_3), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) -); - -eth_xcvr_phy_wrapper #( - .HAS_COMMON(0) -) -qsfp1_phy_4_inst ( - .xcvr_ctrl_clk(clk_125mhz_int), - .xcvr_ctrl_rst(rst_125mhz_int), - - // Common - .xcvr_gtpowergood_out(), - - // PLL out - .xcvr_gtrefclk00_in(1'b0), - .xcvr_qpll0lock_out(), - .xcvr_qpll0outclk_out(), - .xcvr_qpll0outrefclk_out(), - - // PLL in - .xcvr_qpll0lock_in(qsfp1_qpll0lock), - .xcvr_qpll0reset_out(), - .xcvr_qpll0clk_in(qsfp1_qpll0outclk), - .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), - - // Serial data - .xcvr_txp(qsfp1_tx4_p), - .xcvr_txn(qsfp1_tx4_n), - .xcvr_rxp(qsfp1_rx4_p), - .xcvr_rxn(qsfp1_rx4_n), - - // PHY connections - .phy_tx_clk(qsfp1_tx_clk_4_int), - .phy_tx_rst(qsfp1_tx_rst_4_int), - .phy_xgmii_txd(qsfp1_txd_4_int), - .phy_xgmii_txc(qsfp1_txc_4_int), - .phy_rx_clk(qsfp1_rx_clk_4_int), - .phy_rx_rst(qsfp1_rx_rst_4_int), - .phy_xgmii_rxd(qsfp1_rxd_4_int), - .phy_xgmii_rxc(qsfp1_rxc_4_int), - .phy_tx_bad_block(), - .phy_rx_error_count(), - .phy_rx_bad_block(), - .phy_rx_sequence_error(), - .phy_rx_block_lock(qsfp1_rx_block_lock_4), - .phy_rx_high_ber(), - .phy_cfg_tx_prbs31_enable(1'b0), - .phy_cfg_rx_prbs31_enable(1'b0) + .phy_4_tx_clk(qsfp1_tx_clk_4_int), + .phy_4_tx_rst(qsfp1_tx_rst_4_int), + .phy_4_xgmii_txd(qsfp1_txd_4_int), + .phy_4_xgmii_txc(qsfp1_txc_4_int), + .phy_4_rx_clk(qsfp1_rx_clk_4_int), + .phy_4_rx_rst(qsfp1_rx_rst_4_int), + .phy_4_xgmii_rxd(qsfp1_rxd_4_int), + .phy_4_xgmii_rxc(qsfp1_rxc_4_int), + .phy_4_tx_bad_block(), + .phy_4_rx_error_count(), + .phy_4_rx_bad_block(), + .phy_4_rx_sequence_error(), + .phy_4_rx_block_lock(qsfp1_rx_block_lock_4), + .phy_4_rx_status(), + .phy_4_cfg_tx_prbs31_enable(1'b0), + .phy_4_cfg_rx_prbs31_enable(1'b0) ); fpga_core