FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00
Code Issues Projects Releases Wiki Activity

Add busy output to statistics collection module

Browse Source
This commit is contained in:
Alex Forencich 2014-10-21 16:09:55 -07:00
parent f22381baa2
commit 67bb09ba42
3 changed files with 26 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
rtl/axis_stat_counter.v
View File

@ -59,7 +59,12 @@ module axis_stat_counter #
* Configuration
*/
input wire [15:0] tag,
input wire trigger
input wire trigger,
/*
* Status
*/
output wire busy
);
// state register
@ -81,6 +86,8 @@ reg [31:0] tick_count_output_reg = 0;
reg [31:0] byte_count_output_reg = 0;
reg [31:0] frame_count_output_reg = 0;
reg busy_reg = 0;
// internal datapath
reg [7:0] output_axis_tdata_int;
reg output_axis_tvalid_int;
@ -89,6 +96,8 @@ reg output_axis_tlast_int;
reg output_axis_tuser_int;
wire output_axis_tready_int_early = output_axis_tready;
assign busy = busy_reg;
function [3:0] keep2count;
input [7:0] k;
case (k)
@ -220,6 +229,7 @@ always @(posedge clk or posedge rst) begin
frame_count_reg <= 0;
frame_reg <= 0;
frame_ptr_reg <= 0;
busy_reg <= 0;
tick_count_output_reg <= 0;
byte_count_output_reg <= 0;
frame_count_output_reg <= 0;
@ -231,6 +241,8 @@ always @(posedge clk or posedge rst) begin
frame_reg <= frame_next;
frame_ptr_reg <= frame_ptr_next;
busy_reg <= state_next != STATE_IDLE;
if (store_output) begin
tick_count_output_reg <= tick_count_reg;
byte_count_output_reg <= byte_count_reg;

10
tb/test_axis_stat_counter.py
View File

@ -59,7 +59,8 @@ def dut_axis_stat_counter(clk,
output_axis_tuser,
tag,
trigger):
trigger,
busy):
if os.system(build_cmd):
raise Exception("Error running build command")
@ -82,7 +83,8 @@ def dut_axis_stat_counter(clk,
output_axis_tuser=output_axis_tuser,
tag=tag,
trigger=trigger)
trigger=trigger,
busy=busy)
def bench():
@ -107,6 +109,7 @@ def bench():
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
busy = Signal(bool(0))
# sources and sinks
source_queue = Queue()
@ -170,7 +173,8 @@ def bench():
output_axis_tuser,
tag,
trigger)
trigger,
busy)
@always(delay(4))
def clkgen():

8
tb/test_axis_stat_counter.v
View File

@ -48,6 +48,7 @@ wire [7:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
wire busy;
initial begin
// myhdl integration
@ -66,7 +67,8 @@ initial begin
$to_myhdl(output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser);
output_axis_tuser,
busy);
// dump file
$dumpfile("test_axis_stat_counter.lxt");
@ -92,7 +94,9 @@ UUT (
.output_axis_tuser(output_axis_tuser),
// configuration
.tag(tag),
.trigger(trigger)
.trigger(trigger),
// status
.busy(busy)
);
endmodule