diff --git a/lib/axis/rtl/axis_crosspoint.py b/lib/axis/rtl/axis_crosspoint.py index e779ad086..e37707bb3 100755 --- a/lib/axis/rtl/axis_crosspoint.py +++ b/lib/axis/rtl/axis_crosspoint.py @@ -114,6 +114,7 @@ module {{name}} # input wire [DATA_WIDTH-1:0] input_{{p}}_axis_tdata, input wire input_{{p}}_axis_tvalid, input wire input_{{p}}_axis_tlast, + input wire input_{{p}}_axis_tuser, {% endfor %} /* * AXI Stream outputs @@ -122,6 +123,7 @@ module {{name}} # output wire [DATA_WIDTH-1:0] output_{{p}}_axis_tdata, output wire output_{{p}}_axis_tvalid, output wire output_{{p}}_axis_tlast, + output wire output_{{p}}_axis_tuser, {% endfor %} /* * Control @@ -134,12 +136,14 @@ module {{name}} # reg [DATA_WIDTH-1:0] input_{{p}}_axis_tdata_reg = 0; reg input_{{p}}_axis_tvalid_reg = 0; reg input_{{p}}_axis_tlast_reg = 0; +reg input_{{p}}_axis_tuser_reg = 0; {% endfor %} {%- for p in ports %} reg [DATA_WIDTH-1:0] output_{{p}}_axis_tdata_reg = 0; reg output_{{p}}_axis_tvalid_reg = 0; reg output_{{p}}_axis_tlast_reg = 0; +reg output_{{p}}_axis_tuser_reg = 0; {% endfor %} {%- for p in ports %} @@ -149,6 +153,7 @@ reg [{{w-1}}:0] output_{{p}}_select_reg = 0; assign output_{{p}}_axis_tdata = output_{{p}}_axis_tdata_reg; assign output_{{p}}_axis_tvalid = output_{{p}}_axis_tvalid_reg; assign output_{{p}}_axis_tlast = output_{{p}}_axis_tlast_reg; +assign output_{{p}}_axis_tuser = output_{{p}}_axis_tuser_reg; {% endfor %} always @(posedge clk or posedge rst) begin @@ -157,18 +162,23 @@ always @(posedge clk or posedge rst) begin output_{{p}}_select_reg <= 0; {%- endfor %} {% for p in ports %} + input_{{p}}_axis_tdata_reg <= 0; input_{{p}}_axis_tvalid_reg <= 0; input_{{p}}_axis_tlast_reg <= 0; + input_{{p}}_axis_tuser_reg <= 0; {%- endfor %} {% for p in ports %} + output_{{p}}_axis_tdata_reg <= 0; output_{{p}}_axis_tvalid_reg <= 0; output_{{p}}_axis_tlast_reg <= 0; + output_{{p}}_axis_tuser_reg <= 0; {%- endfor %} end else begin {%- for p in ports %} input_{{p}}_axis_tdata_reg <= input_{{p}}_axis_tdata; input_{{p}}_axis_tvalid_reg <= input_{{p}}_axis_tvalid; input_{{p}}_axis_tlast_reg <= input_{{p}}_axis_tlast; + input_{{p}}_axis_tuser_reg <= input_{{p}}_axis_tuser; {% endfor %} {%- for p in ports %} output_{{p}}_select_reg <= output_{{p}}_select; @@ -181,6 +191,7 @@ always @(posedge clk or posedge rst) begin output_{{p}}_axis_tdata_reg <= input_{{q}}_axis_tdata_reg; output_{{p}}_axis_tvalid_reg <= input_{{q}}_axis_tvalid_reg; output_{{p}}_axis_tlast_reg <= input_{{q}}_axis_tlast_reg; + output_{{p}}_axis_tuser_reg <= input_{{q}}_axis_tuser_reg; end {%- endfor %} endcase diff --git a/lib/axis/rtl/axis_crosspoint_4x4.v b/lib/axis/rtl/axis_crosspoint_4x4.v index 859f4309c..581fdf016 100644 --- a/lib/axis/rtl/axis_crosspoint_4x4.v +++ b/lib/axis/rtl/axis_crosspoint_4x4.v @@ -43,18 +43,22 @@ module axis_crosspoint_4x4 # input wire [DATA_WIDTH-1:0] input_0_axis_tdata, input wire input_0_axis_tvalid, input wire input_0_axis_tlast, + input wire input_0_axis_tuser, input wire [DATA_WIDTH-1:0] input_1_axis_tdata, input wire input_1_axis_tvalid, input wire input_1_axis_tlast, + input wire input_1_axis_tuser, input wire [DATA_WIDTH-1:0] input_2_axis_tdata, input wire input_2_axis_tvalid, input wire input_2_axis_tlast, + input wire input_2_axis_tuser, input wire [DATA_WIDTH-1:0] input_3_axis_tdata, input wire input_3_axis_tvalid, input wire input_3_axis_tlast, + input wire input_3_axis_tuser, /* * AXI Stream outputs @@ -62,18 +66,22 @@ module axis_crosspoint_4x4 # output wire [DATA_WIDTH-1:0] output_0_axis_tdata, output wire output_0_axis_tvalid, output wire output_0_axis_tlast, + output wire output_0_axis_tuser, output wire [DATA_WIDTH-1:0] output_1_axis_tdata, output wire output_1_axis_tvalid, output wire output_1_axis_tlast, + output wire output_1_axis_tuser, output wire [DATA_WIDTH-1:0] output_2_axis_tdata, output wire output_2_axis_tvalid, output wire output_2_axis_tlast, + output wire output_2_axis_tuser, output wire [DATA_WIDTH-1:0] output_3_axis_tdata, output wire output_3_axis_tvalid, output wire output_3_axis_tlast, + output wire output_3_axis_tuser, /* * Control @@ -87,34 +95,42 @@ module axis_crosspoint_4x4 # reg [DATA_WIDTH-1:0] input_0_axis_tdata_reg = 0; reg input_0_axis_tvalid_reg = 0; reg input_0_axis_tlast_reg = 0; +reg input_0_axis_tuser_reg = 0; reg [DATA_WIDTH-1:0] input_1_axis_tdata_reg = 0; reg input_1_axis_tvalid_reg = 0; reg input_1_axis_tlast_reg = 0; +reg input_1_axis_tuser_reg = 0; reg [DATA_WIDTH-1:0] input_2_axis_tdata_reg = 0; reg input_2_axis_tvalid_reg = 0; reg input_2_axis_tlast_reg = 0; +reg input_2_axis_tuser_reg = 0; reg [DATA_WIDTH-1:0] input_3_axis_tdata_reg = 0; reg input_3_axis_tvalid_reg = 0; reg input_3_axis_tlast_reg = 0; +reg input_3_axis_tuser_reg = 0; reg [DATA_WIDTH-1:0] output_0_axis_tdata_reg = 0; reg output_0_axis_tvalid_reg = 0; reg output_0_axis_tlast_reg = 0; +reg output_0_axis_tuser_reg = 0; reg [DATA_WIDTH-1:0] output_1_axis_tdata_reg = 0; reg output_1_axis_tvalid_reg = 0; reg output_1_axis_tlast_reg = 0; +reg output_1_axis_tuser_reg = 0; reg [DATA_WIDTH-1:0] output_2_axis_tdata_reg = 0; reg output_2_axis_tvalid_reg = 0; reg output_2_axis_tlast_reg = 0; +reg output_2_axis_tuser_reg = 0; reg [DATA_WIDTH-1:0] output_3_axis_tdata_reg = 0; reg output_3_axis_tvalid_reg = 0; reg output_3_axis_tlast_reg = 0; +reg output_3_axis_tuser_reg = 0; reg [1:0] output_0_select_reg = 0; reg [1:0] output_1_select_reg = 0; @@ -124,18 +140,22 @@ reg [1:0] output_3_select_reg = 0; assign output_0_axis_tdata = output_0_axis_tdata_reg; assign output_0_axis_tvalid = output_0_axis_tvalid_reg; assign output_0_axis_tlast = output_0_axis_tlast_reg; +assign output_0_axis_tuser = output_0_axis_tuser_reg; assign output_1_axis_tdata = output_1_axis_tdata_reg; assign output_1_axis_tvalid = output_1_axis_tvalid_reg; assign output_1_axis_tlast = output_1_axis_tlast_reg; +assign output_1_axis_tuser = output_1_axis_tuser_reg; assign output_2_axis_tdata = output_2_axis_tdata_reg; assign output_2_axis_tvalid = output_2_axis_tvalid_reg; assign output_2_axis_tlast = output_2_axis_tlast_reg; +assign output_2_axis_tuser = output_2_axis_tuser_reg; assign output_3_axis_tdata = output_3_axis_tdata_reg; assign output_3_axis_tvalid = output_3_axis_tvalid_reg; assign output_3_axis_tlast = output_3_axis_tlast_reg; +assign output_3_axis_tuser = output_3_axis_tuser_reg; always @(posedge clk or posedge rst) begin @@ -145,39 +165,59 @@ always @(posedge clk or posedge rst) begin output_2_select_reg <= 0; output_3_select_reg <= 0; + input_0_axis_tdata_reg <= 0; input_0_axis_tvalid_reg <= 0; input_0_axis_tlast_reg <= 0; + input_0_axis_tuser_reg <= 0; + input_1_axis_tdata_reg <= 0; input_1_axis_tvalid_reg <= 0; input_1_axis_tlast_reg <= 0; + input_1_axis_tuser_reg <= 0; + input_2_axis_tdata_reg <= 0; input_2_axis_tvalid_reg <= 0; input_2_axis_tlast_reg <= 0; + input_2_axis_tuser_reg <= 0; + input_3_axis_tdata_reg <= 0; input_3_axis_tvalid_reg <= 0; input_3_axis_tlast_reg <= 0; + input_3_axis_tuser_reg <= 0; + output_0_axis_tdata_reg <= 0; output_0_axis_tvalid_reg <= 0; output_0_axis_tlast_reg <= 0; + output_0_axis_tuser_reg <= 0; + output_1_axis_tdata_reg <= 0; output_1_axis_tvalid_reg <= 0; output_1_axis_tlast_reg <= 0; + output_1_axis_tuser_reg <= 0; + output_2_axis_tdata_reg <= 0; output_2_axis_tvalid_reg <= 0; output_2_axis_tlast_reg <= 0; + output_2_axis_tuser_reg <= 0; + output_3_axis_tdata_reg <= 0; output_3_axis_tvalid_reg <= 0; output_3_axis_tlast_reg <= 0; + output_3_axis_tuser_reg <= 0; end else begin input_0_axis_tdata_reg <= input_0_axis_tdata; input_0_axis_tvalid_reg <= input_0_axis_tvalid; input_0_axis_tlast_reg <= input_0_axis_tlast; + input_0_axis_tuser_reg <= input_0_axis_tuser; input_1_axis_tdata_reg <= input_1_axis_tdata; input_1_axis_tvalid_reg <= input_1_axis_tvalid; input_1_axis_tlast_reg <= input_1_axis_tlast; + input_1_axis_tuser_reg <= input_1_axis_tuser; input_2_axis_tdata_reg <= input_2_axis_tdata; input_2_axis_tvalid_reg <= input_2_axis_tvalid; input_2_axis_tlast_reg <= input_2_axis_tlast; + input_2_axis_tuser_reg <= input_2_axis_tuser; input_3_axis_tdata_reg <= input_3_axis_tdata; input_3_axis_tvalid_reg <= input_3_axis_tvalid; input_3_axis_tlast_reg <= input_3_axis_tlast; + input_3_axis_tuser_reg <= input_3_axis_tuser; output_0_select_reg <= output_0_select; output_1_select_reg <= output_1_select; @@ -189,21 +229,25 @@ always @(posedge clk or posedge rst) begin output_0_axis_tdata_reg <= input_0_axis_tdata_reg; output_0_axis_tvalid_reg <= input_0_axis_tvalid_reg; output_0_axis_tlast_reg <= input_0_axis_tlast_reg; + output_0_axis_tuser_reg <= input_0_axis_tuser_reg; end 2'd1: begin output_0_axis_tdata_reg <= input_1_axis_tdata_reg; output_0_axis_tvalid_reg <= input_1_axis_tvalid_reg; output_0_axis_tlast_reg <= input_1_axis_tlast_reg; + output_0_axis_tuser_reg <= input_1_axis_tuser_reg; end 2'd2: begin output_0_axis_tdata_reg <= input_2_axis_tdata_reg; output_0_axis_tvalid_reg <= input_2_axis_tvalid_reg; output_0_axis_tlast_reg <= input_2_axis_tlast_reg; + output_0_axis_tuser_reg <= input_2_axis_tuser_reg; end 2'd3: begin output_0_axis_tdata_reg <= input_3_axis_tdata_reg; output_0_axis_tvalid_reg <= input_3_axis_tvalid_reg; output_0_axis_tlast_reg <= input_3_axis_tlast_reg; + output_0_axis_tuser_reg <= input_3_axis_tuser_reg; end endcase @@ -212,21 +256,25 @@ always @(posedge clk or posedge rst) begin output_1_axis_tdata_reg <= input_0_axis_tdata_reg; output_1_axis_tvalid_reg <= input_0_axis_tvalid_reg; output_1_axis_tlast_reg <= input_0_axis_tlast_reg; + output_1_axis_tuser_reg <= input_0_axis_tuser_reg; end 2'd1: begin output_1_axis_tdata_reg <= input_1_axis_tdata_reg; output_1_axis_tvalid_reg <= input_1_axis_tvalid_reg; output_1_axis_tlast_reg <= input_1_axis_tlast_reg; + output_1_axis_tuser_reg <= input_1_axis_tuser_reg; end 2'd2: begin output_1_axis_tdata_reg <= input_2_axis_tdata_reg; output_1_axis_tvalid_reg <= input_2_axis_tvalid_reg; output_1_axis_tlast_reg <= input_2_axis_tlast_reg; + output_1_axis_tuser_reg <= input_2_axis_tuser_reg; end 2'd3: begin output_1_axis_tdata_reg <= input_3_axis_tdata_reg; output_1_axis_tvalid_reg <= input_3_axis_tvalid_reg; output_1_axis_tlast_reg <= input_3_axis_tlast_reg; + output_1_axis_tuser_reg <= input_3_axis_tuser_reg; end endcase @@ -235,21 +283,25 @@ always @(posedge clk or posedge rst) begin output_2_axis_tdata_reg <= input_0_axis_tdata_reg; output_2_axis_tvalid_reg <= input_0_axis_tvalid_reg; output_2_axis_tlast_reg <= input_0_axis_tlast_reg; + output_2_axis_tuser_reg <= input_0_axis_tuser_reg; end 2'd1: begin output_2_axis_tdata_reg <= input_1_axis_tdata_reg; output_2_axis_tvalid_reg <= input_1_axis_tvalid_reg; output_2_axis_tlast_reg <= input_1_axis_tlast_reg; + output_2_axis_tuser_reg <= input_1_axis_tuser_reg; end 2'd2: begin output_2_axis_tdata_reg <= input_2_axis_tdata_reg; output_2_axis_tvalid_reg <= input_2_axis_tvalid_reg; output_2_axis_tlast_reg <= input_2_axis_tlast_reg; + output_2_axis_tuser_reg <= input_2_axis_tuser_reg; end 2'd3: begin output_2_axis_tdata_reg <= input_3_axis_tdata_reg; output_2_axis_tvalid_reg <= input_3_axis_tvalid_reg; output_2_axis_tlast_reg <= input_3_axis_tlast_reg; + output_2_axis_tuser_reg <= input_3_axis_tuser_reg; end endcase @@ -258,21 +310,25 @@ always @(posedge clk or posedge rst) begin output_3_axis_tdata_reg <= input_0_axis_tdata_reg; output_3_axis_tvalid_reg <= input_0_axis_tvalid_reg; output_3_axis_tlast_reg <= input_0_axis_tlast_reg; + output_3_axis_tuser_reg <= input_0_axis_tuser_reg; end 2'd1: begin output_3_axis_tdata_reg <= input_1_axis_tdata_reg; output_3_axis_tvalid_reg <= input_1_axis_tvalid_reg; output_3_axis_tlast_reg <= input_1_axis_tlast_reg; + output_3_axis_tuser_reg <= input_1_axis_tuser_reg; end 2'd2: begin output_3_axis_tdata_reg <= input_2_axis_tdata_reg; output_3_axis_tvalid_reg <= input_2_axis_tvalid_reg; output_3_axis_tlast_reg <= input_2_axis_tlast_reg; + output_3_axis_tuser_reg <= input_2_axis_tuser_reg; end 2'd3: begin output_3_axis_tdata_reg <= input_3_axis_tdata_reg; output_3_axis_tvalid_reg <= input_3_axis_tvalid_reg; output_3_axis_tlast_reg <= input_3_axis_tlast_reg; + output_3_axis_tuser_reg <= input_3_axis_tuser_reg; end endcase end diff --git a/lib/axis/rtl/axis_crosspoint_64.py b/lib/axis/rtl/axis_crosspoint_64.py index c666299a4..12dbe8ae5 100755 --- a/lib/axis/rtl/axis_crosspoint_64.py +++ b/lib/axis/rtl/axis_crosspoint_64.py @@ -116,6 +116,7 @@ module {{name}} # input wire [KEEP_WIDTH-1:0] input_{{p}}_axis_tkeep, input wire input_{{p}}_axis_tvalid, input wire input_{{p}}_axis_tlast, + input wire input_{{p}}_axis_tuser, {% endfor %} /* * AXI Stream outputs @@ -125,6 +126,7 @@ module {{name}} # output wire [KEEP_WIDTH-1:0] output_{{p}}_axis_tkeep, output wire output_{{p}}_axis_tvalid, output wire output_{{p}}_axis_tlast, + output wire output_{{p}}_axis_tuser, {% endfor %} /* * Control @@ -138,6 +140,7 @@ reg [DATA_WIDTH-1:0] input_{{p}}_axis_tdata_reg = 0; reg [KEEP_WIDTH-1:0] input_{{p}}_axis_tkeep_reg = 0; reg input_{{p}}_axis_tvalid_reg = 0; reg input_{{p}}_axis_tlast_reg = 0; +reg input_{{p}}_axis_tuser_reg = 0; {% endfor %} {%- for p in ports %} @@ -145,6 +148,7 @@ reg [DATA_WIDTH-1:0] output_{{p}}_axis_tdata_reg = 0; reg [KEEP_WIDTH-1:0] output_{{p}}_axis_tkeep_reg = 0; reg output_{{p}}_axis_tvalid_reg = 0; reg output_{{p}}_axis_tlast_reg = 0; +reg output_{{p}}_axis_tuser_reg = 0; {% endfor %} {%- for p in ports %} @@ -155,6 +159,7 @@ assign output_{{p}}_axis_tdata = output_{{p}}_axis_tdata_reg; assign output_{{p}}_axis_tkeep = output_{{p}}_axis_tkeep_reg; assign output_{{p}}_axis_tvalid = output_{{p}}_axis_tvalid_reg; assign output_{{p}}_axis_tlast = output_{{p}}_axis_tlast_reg; +assign output_{{p}}_axis_tuser = output_{{p}}_axis_tuser_reg; {% endfor %} always @(posedge clk or posedge rst) begin @@ -163,12 +168,18 @@ always @(posedge clk or posedge rst) begin output_{{p}}_select_reg <= 0; {%- endfor %} {% for p in ports %} + input_{{p}}_axis_tdata_reg <= 0; + input_{{p}}_axis_tkeep_reg <= 0; input_{{p}}_axis_tvalid_reg <= 0; input_{{p}}_axis_tlast_reg <= 0; + input_{{p}}_axis_tuser_reg <= 0; {%- endfor %} {% for p in ports %} + output_{{p}}_axis_tdata_reg <= 0; + output_{{p}}_axis_tkeep_reg <= 0; output_{{p}}_axis_tvalid_reg <= 0; output_{{p}}_axis_tlast_reg <= 0; + output_{{p}}_axis_tuser_reg <= 0; {%- endfor %} end else begin {%- for p in ports %} @@ -176,6 +187,7 @@ always @(posedge clk or posedge rst) begin input_{{p}}_axis_tkeep_reg <= input_{{p}}_axis_tkeep; input_{{p}}_axis_tvalid_reg <= input_{{p}}_axis_tvalid; input_{{p}}_axis_tlast_reg <= input_{{p}}_axis_tlast; + input_{{p}}_axis_tuser_reg <= input_{{p}}_axis_tuser; {% endfor %} {%- for p in ports %} output_{{p}}_select_reg <= output_{{p}}_select; @@ -189,6 +201,7 @@ always @(posedge clk or posedge rst) begin output_{{p}}_axis_tkeep_reg <= input_{{q}}_axis_tkeep_reg; output_{{p}}_axis_tvalid_reg <= input_{{q}}_axis_tvalid_reg; output_{{p}}_axis_tlast_reg <= input_{{q}}_axis_tlast_reg; + output_{{p}}_axis_tuser_reg <= input_{{q}}_axis_tuser_reg; end {%- endfor %} endcase diff --git a/lib/axis/rtl/axis_crosspoint_64_4x4.v b/lib/axis/rtl/axis_crosspoint_64_4x4.v index 08c41ad54..edf12f892 100644 --- a/lib/axis/rtl/axis_crosspoint_64_4x4.v +++ b/lib/axis/rtl/axis_crosspoint_64_4x4.v @@ -45,21 +45,25 @@ module axis_crosspoint_64_4x4 # input wire [KEEP_WIDTH-1:0] input_0_axis_tkeep, input wire input_0_axis_tvalid, input wire input_0_axis_tlast, + input wire input_0_axis_tuser, input wire [DATA_WIDTH-1:0] input_1_axis_tdata, input wire [KEEP_WIDTH-1:0] input_1_axis_tkeep, input wire input_1_axis_tvalid, input wire input_1_axis_tlast, + input wire input_1_axis_tuser, input wire [DATA_WIDTH-1:0] input_2_axis_tdata, input wire [KEEP_WIDTH-1:0] input_2_axis_tkeep, input wire input_2_axis_tvalid, input wire input_2_axis_tlast, + input wire input_2_axis_tuser, input wire [DATA_WIDTH-1:0] input_3_axis_tdata, input wire [KEEP_WIDTH-1:0] input_3_axis_tkeep, input wire input_3_axis_tvalid, input wire input_3_axis_tlast, + input wire input_3_axis_tuser, /* * AXI Stream outputs @@ -68,21 +72,25 @@ module axis_crosspoint_64_4x4 # output wire [KEEP_WIDTH-1:0] output_0_axis_tkeep, output wire output_0_axis_tvalid, output wire output_0_axis_tlast, + output wire output_0_axis_tuser, output wire [DATA_WIDTH-1:0] output_1_axis_tdata, output wire [KEEP_WIDTH-1:0] output_1_axis_tkeep, output wire output_1_axis_tvalid, output wire output_1_axis_tlast, + output wire output_1_axis_tuser, output wire [DATA_WIDTH-1:0] output_2_axis_tdata, output wire [KEEP_WIDTH-1:0] output_2_axis_tkeep, output wire output_2_axis_tvalid, output wire output_2_axis_tlast, + output wire output_2_axis_tuser, output wire [DATA_WIDTH-1:0] output_3_axis_tdata, output wire [KEEP_WIDTH-1:0] output_3_axis_tkeep, output wire output_3_axis_tvalid, output wire output_3_axis_tlast, + output wire output_3_axis_tuser, /* * Control @@ -97,41 +105,49 @@ reg [DATA_WIDTH-1:0] input_0_axis_tdata_reg = 0; reg [KEEP_WIDTH-1:0] input_0_axis_tkeep_reg = 0; reg input_0_axis_tvalid_reg = 0; reg input_0_axis_tlast_reg = 0; +reg input_0_axis_tuser_reg = 0; reg [DATA_WIDTH-1:0] input_1_axis_tdata_reg = 0; reg [KEEP_WIDTH-1:0] input_1_axis_tkeep_reg = 0; reg input_1_axis_tvalid_reg = 0; reg input_1_axis_tlast_reg = 0; +reg input_1_axis_tuser_reg = 0; reg [DATA_WIDTH-1:0] input_2_axis_tdata_reg = 0; reg [KEEP_WIDTH-1:0] input_2_axis_tkeep_reg = 0; reg input_2_axis_tvalid_reg = 0; reg input_2_axis_tlast_reg = 0; +reg input_2_axis_tuser_reg = 0; reg [DATA_WIDTH-1:0] input_3_axis_tdata_reg = 0; reg [KEEP_WIDTH-1:0] input_3_axis_tkeep_reg = 0; reg input_3_axis_tvalid_reg = 0; reg input_3_axis_tlast_reg = 0; +reg input_3_axis_tuser_reg = 0; reg [DATA_WIDTH-1:0] output_0_axis_tdata_reg = 0; reg [KEEP_WIDTH-1:0] output_0_axis_tkeep_reg = 0; reg output_0_axis_tvalid_reg = 0; reg output_0_axis_tlast_reg = 0; +reg output_0_axis_tuser_reg = 0; reg [DATA_WIDTH-1:0] output_1_axis_tdata_reg = 0; reg [KEEP_WIDTH-1:0] output_1_axis_tkeep_reg = 0; reg output_1_axis_tvalid_reg = 0; reg output_1_axis_tlast_reg = 0; +reg output_1_axis_tuser_reg = 0; reg [DATA_WIDTH-1:0] output_2_axis_tdata_reg = 0; reg [KEEP_WIDTH-1:0] output_2_axis_tkeep_reg = 0; reg output_2_axis_tvalid_reg = 0; reg output_2_axis_tlast_reg = 0; +reg output_2_axis_tuser_reg = 0; reg [DATA_WIDTH-1:0] output_3_axis_tdata_reg = 0; reg [KEEP_WIDTH-1:0] output_3_axis_tkeep_reg = 0; reg output_3_axis_tvalid_reg = 0; reg output_3_axis_tlast_reg = 0; +reg output_3_axis_tuser_reg = 0; reg [1:0] output_0_select_reg = 0; reg [1:0] output_1_select_reg = 0; @@ -142,21 +158,25 @@ assign output_0_axis_tdata = output_0_axis_tdata_reg; assign output_0_axis_tkeep = output_0_axis_tkeep_reg; assign output_0_axis_tvalid = output_0_axis_tvalid_reg; assign output_0_axis_tlast = output_0_axis_tlast_reg; +assign output_0_axis_tuser = output_0_axis_tuser_reg; assign output_1_axis_tdata = output_1_axis_tdata_reg; assign output_1_axis_tkeep = output_1_axis_tkeep_reg; assign output_1_axis_tvalid = output_1_axis_tvalid_reg; assign output_1_axis_tlast = output_1_axis_tlast_reg; +assign output_1_axis_tuser = output_1_axis_tuser_reg; assign output_2_axis_tdata = output_2_axis_tdata_reg; assign output_2_axis_tkeep = output_2_axis_tkeep_reg; assign output_2_axis_tvalid = output_2_axis_tvalid_reg; assign output_2_axis_tlast = output_2_axis_tlast_reg; +assign output_2_axis_tuser = output_2_axis_tuser_reg; assign output_3_axis_tdata = output_3_axis_tdata_reg; assign output_3_axis_tkeep = output_3_axis_tkeep_reg; assign output_3_axis_tvalid = output_3_axis_tvalid_reg; assign output_3_axis_tlast = output_3_axis_tlast_reg; +assign output_3_axis_tuser = output_3_axis_tuser_reg; always @(posedge clk or posedge rst) begin @@ -166,43 +186,71 @@ always @(posedge clk or posedge rst) begin output_2_select_reg <= 0; output_3_select_reg <= 0; + input_0_axis_tdata_reg <= 0; + input_0_axis_tkeep_reg <= 0; input_0_axis_tvalid_reg <= 0; input_0_axis_tlast_reg <= 0; + input_0_axis_tuser_reg <= 0; + input_1_axis_tdata_reg <= 0; + input_1_axis_tkeep_reg <= 0; input_1_axis_tvalid_reg <= 0; input_1_axis_tlast_reg <= 0; + input_1_axis_tuser_reg <= 0; + input_2_axis_tdata_reg <= 0; + input_2_axis_tkeep_reg <= 0; input_2_axis_tvalid_reg <= 0; input_2_axis_tlast_reg <= 0; + input_2_axis_tuser_reg <= 0; + input_3_axis_tdata_reg <= 0; + input_3_axis_tkeep_reg <= 0; input_3_axis_tvalid_reg <= 0; input_3_axis_tlast_reg <= 0; + input_3_axis_tuser_reg <= 0; + output_0_axis_tdata_reg <= 0; + output_0_axis_tkeep_reg <= 0; output_0_axis_tvalid_reg <= 0; output_0_axis_tlast_reg <= 0; + output_0_axis_tuser_reg <= 0; + output_1_axis_tdata_reg <= 0; + output_1_axis_tkeep_reg <= 0; output_1_axis_tvalid_reg <= 0; output_1_axis_tlast_reg <= 0; + output_1_axis_tuser_reg <= 0; + output_2_axis_tdata_reg <= 0; + output_2_axis_tkeep_reg <= 0; output_2_axis_tvalid_reg <= 0; output_2_axis_tlast_reg <= 0; + output_2_axis_tuser_reg <= 0; + output_3_axis_tdata_reg <= 0; + output_3_axis_tkeep_reg <= 0; output_3_axis_tvalid_reg <= 0; output_3_axis_tlast_reg <= 0; + output_3_axis_tuser_reg <= 0; end else begin input_0_axis_tdata_reg <= input_0_axis_tdata; input_0_axis_tkeep_reg <= input_0_axis_tkeep; input_0_axis_tvalid_reg <= input_0_axis_tvalid; input_0_axis_tlast_reg <= input_0_axis_tlast; + input_0_axis_tuser_reg <= input_0_axis_tuser; input_1_axis_tdata_reg <= input_1_axis_tdata; input_1_axis_tkeep_reg <= input_1_axis_tkeep; input_1_axis_tvalid_reg <= input_1_axis_tvalid; input_1_axis_tlast_reg <= input_1_axis_tlast; + input_1_axis_tuser_reg <= input_1_axis_tuser; input_2_axis_tdata_reg <= input_2_axis_tdata; input_2_axis_tkeep_reg <= input_2_axis_tkeep; input_2_axis_tvalid_reg <= input_2_axis_tvalid; input_2_axis_tlast_reg <= input_2_axis_tlast; + input_2_axis_tuser_reg <= input_2_axis_tuser; input_3_axis_tdata_reg <= input_3_axis_tdata; input_3_axis_tkeep_reg <= input_3_axis_tkeep; input_3_axis_tvalid_reg <= input_3_axis_tvalid; input_3_axis_tlast_reg <= input_3_axis_tlast; + input_3_axis_tuser_reg <= input_3_axis_tuser; output_0_select_reg <= output_0_select; output_1_select_reg <= output_1_select; @@ -215,24 +263,28 @@ always @(posedge clk or posedge rst) begin output_0_axis_tkeep_reg <= input_0_axis_tkeep_reg; output_0_axis_tvalid_reg <= input_0_axis_tvalid_reg; output_0_axis_tlast_reg <= input_0_axis_tlast_reg; + output_0_axis_tuser_reg <= input_0_axis_tuser_reg; end 2'd1: begin output_0_axis_tdata_reg <= input_1_axis_tdata_reg; output_0_axis_tkeep_reg <= input_1_axis_tkeep_reg; output_0_axis_tvalid_reg <= input_1_axis_tvalid_reg; output_0_axis_tlast_reg <= input_1_axis_tlast_reg; + output_0_axis_tuser_reg <= input_1_axis_tuser_reg; end 2'd2: begin output_0_axis_tdata_reg <= input_2_axis_tdata_reg; output_0_axis_tkeep_reg <= input_2_axis_tkeep_reg; output_0_axis_tvalid_reg <= input_2_axis_tvalid_reg; output_0_axis_tlast_reg <= input_2_axis_tlast_reg; + output_0_axis_tuser_reg <= input_2_axis_tuser_reg; end 2'd3: begin output_0_axis_tdata_reg <= input_3_axis_tdata_reg; output_0_axis_tkeep_reg <= input_3_axis_tkeep_reg; output_0_axis_tvalid_reg <= input_3_axis_tvalid_reg; output_0_axis_tlast_reg <= input_3_axis_tlast_reg; + output_0_axis_tuser_reg <= input_3_axis_tuser_reg; end endcase @@ -242,24 +294,28 @@ always @(posedge clk or posedge rst) begin output_1_axis_tkeep_reg <= input_0_axis_tkeep_reg; output_1_axis_tvalid_reg <= input_0_axis_tvalid_reg; output_1_axis_tlast_reg <= input_0_axis_tlast_reg; + output_1_axis_tuser_reg <= input_0_axis_tuser_reg; end 2'd1: begin output_1_axis_tdata_reg <= input_1_axis_tdata_reg; output_1_axis_tkeep_reg <= input_1_axis_tkeep_reg; output_1_axis_tvalid_reg <= input_1_axis_tvalid_reg; output_1_axis_tlast_reg <= input_1_axis_tlast_reg; + output_1_axis_tuser_reg <= input_1_axis_tuser_reg; end 2'd2: begin output_1_axis_tdata_reg <= input_2_axis_tdata_reg; output_1_axis_tkeep_reg <= input_2_axis_tkeep_reg; output_1_axis_tvalid_reg <= input_2_axis_tvalid_reg; output_1_axis_tlast_reg <= input_2_axis_tlast_reg; + output_1_axis_tuser_reg <= input_2_axis_tuser_reg; end 2'd3: begin output_1_axis_tdata_reg <= input_3_axis_tdata_reg; output_1_axis_tkeep_reg <= input_3_axis_tkeep_reg; output_1_axis_tvalid_reg <= input_3_axis_tvalid_reg; output_1_axis_tlast_reg <= input_3_axis_tlast_reg; + output_1_axis_tuser_reg <= input_3_axis_tuser_reg; end endcase @@ -269,24 +325,28 @@ always @(posedge clk or posedge rst) begin output_2_axis_tkeep_reg <= input_0_axis_tkeep_reg; output_2_axis_tvalid_reg <= input_0_axis_tvalid_reg; output_2_axis_tlast_reg <= input_0_axis_tlast_reg; + output_2_axis_tuser_reg <= input_0_axis_tuser_reg; end 2'd1: begin output_2_axis_tdata_reg <= input_1_axis_tdata_reg; output_2_axis_tkeep_reg <= input_1_axis_tkeep_reg; output_2_axis_tvalid_reg <= input_1_axis_tvalid_reg; output_2_axis_tlast_reg <= input_1_axis_tlast_reg; + output_2_axis_tuser_reg <= input_1_axis_tuser_reg; end 2'd2: begin output_2_axis_tdata_reg <= input_2_axis_tdata_reg; output_2_axis_tkeep_reg <= input_2_axis_tkeep_reg; output_2_axis_tvalid_reg <= input_2_axis_tvalid_reg; output_2_axis_tlast_reg <= input_2_axis_tlast_reg; + output_2_axis_tuser_reg <= input_2_axis_tuser_reg; end 2'd3: begin output_2_axis_tdata_reg <= input_3_axis_tdata_reg; output_2_axis_tkeep_reg <= input_3_axis_tkeep_reg; output_2_axis_tvalid_reg <= input_3_axis_tvalid_reg; output_2_axis_tlast_reg <= input_3_axis_tlast_reg; + output_2_axis_tuser_reg <= input_3_axis_tuser_reg; end endcase @@ -296,24 +356,28 @@ always @(posedge clk or posedge rst) begin output_3_axis_tkeep_reg <= input_0_axis_tkeep_reg; output_3_axis_tvalid_reg <= input_0_axis_tvalid_reg; output_3_axis_tlast_reg <= input_0_axis_tlast_reg; + output_3_axis_tuser_reg <= input_0_axis_tuser_reg; end 2'd1: begin output_3_axis_tdata_reg <= input_1_axis_tdata_reg; output_3_axis_tkeep_reg <= input_1_axis_tkeep_reg; output_3_axis_tvalid_reg <= input_1_axis_tvalid_reg; output_3_axis_tlast_reg <= input_1_axis_tlast_reg; + output_3_axis_tuser_reg <= input_1_axis_tuser_reg; end 2'd2: begin output_3_axis_tdata_reg <= input_2_axis_tdata_reg; output_3_axis_tkeep_reg <= input_2_axis_tkeep_reg; output_3_axis_tvalid_reg <= input_2_axis_tvalid_reg; output_3_axis_tlast_reg <= input_2_axis_tlast_reg; + output_3_axis_tuser_reg <= input_2_axis_tuser_reg; end 2'd3: begin output_3_axis_tdata_reg <= input_3_axis_tdata_reg; output_3_axis_tkeep_reg <= input_3_axis_tkeep_reg; output_3_axis_tvalid_reg <= input_3_axis_tvalid_reg; output_3_axis_tlast_reg <= input_3_axis_tlast_reg; + output_3_axis_tuser_reg <= input_3_axis_tuser_reg; end endcase end diff --git a/lib/axis/rtl/priority_encoder.v b/lib/axis/rtl/priority_encoder.v index cb380c760..e0d3c1a41 100644 --- a/lib/axis/rtl/priority_encoder.v +++ b/lib/axis/rtl/priority_encoder.v @@ -43,8 +43,8 @@ module priority_encoder # ); // power-of-two width -localparam W1 = 2**$clog2(WIDTH); -localparam W2 = W1/2; +parameter W1 = 2**$clog2(WIDTH); +parameter W2 = W1/2; generate if (WIDTH == 2) begin