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Update example design testbenches

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This commit is contained in:
Alex Forencich 2021-11-17 17:21:57 -08:00
parent 2c3a5f4bda
commit 6920845989
19 changed files with 778 additions and 598 deletions
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51
example/520N_MX/fpga/tb/fpga_core/test_fpga_core.py
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@ -174,67 +174,66 @@ async def run_test(dut):
await tb.init()
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
tb.log.info("Test memory write to BAR 2")
await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
test_data = b'\x11\x22\x33\x44'
await dev_pf0_bar2.write(0, test_data)
await Timer(100, 'ns')
tb.log.info("Test memory read from BAR 2")
val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
tb.log.info("Read data: %s", val)
assert val == b'\x11\x22\x33\x44'
assert val == test_data
tb.log.info("Test DMA")
# write packet data
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
# enable DMA
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000000, 1)
await dev_pf0_bar0.write_dword(0x000000, 1)
# enable interrupts
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000008, 3)
await dev_pf0_bar0.write_dword(0x000008, 0x3)
# write pcie read descriptor
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000100, (mem_base+0x0000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000108, (0x100) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00010C, (0x100 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000110, 0x400)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000114, 0xAA)
await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000108, 0x100)
await dev_pf0_bar0.write_dword(0x000110, 0x400)
await dev_pf0_bar0.write_dword(0x000114, 0xAA)
await Timer(2000, 'ns')
# read status
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x000118)
val = await dev_pf0_bar0.read_dword(0x000118)
tb.log.info("Status: 0x%x", val)
assert val == 0x800000AA
# write pcie write descriptor
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000200, (mem_base+0x1000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000208, (0x100) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00020C, (0x100 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000210, 0x400)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000214, 0x55)
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000208, 0x100)
await dev_pf0_bar0.write_dword(0x000210, 0x400)
await dev_pf0_bar0.write_dword(0x000214, 0x55)
await Timer(2000, 'ns')
# read status
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x000218)
val = await dev_pf0_bar0.read_dword(0x000218)
tb.log.info("Status: 0x%x", val)
assert val == 0x80000055
tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64))
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
assert mem[0:1024] == mem[0x1000:0x1000+1024]
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)

48
example/ADM_PCIE_9V3/fpga_axi/tb/fpga_core/test_fpga_core.py
View File

@ -252,64 +252,64 @@ async def run_test(dut):
await tb.init()
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
tb.log.info("Test memory write to BAR 2")
await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
test_data = b'\x11\x22\x33\x44'
await dev_pf0_bar2.write(0, test_data)
await Timer(100, 'ns')
tb.log.info("Test memory read from BAR 2")
val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
tb.log.info("Read data: %s", val)
assert val == b'\x11\x22\x33\x44'
assert val == test_data
tb.log.info("Test DMA")
# write packet data
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
# enable DMA
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100000, 1)
await dev_pf0_bar0.write_dword(0x000000, 1)
# write pcie read descriptor
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100100, (mem_base+0x0000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100104, (mem_base+0x0000 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100108, (0x100) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10010C, (0x100 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100110, 0x400)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100114, 0xAA)
await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000108, 0x100)
await dev_pf0_bar0.write_dword(0x000110, 0x400)
await dev_pf0_bar0.write_dword(0x000114, 0xAA)
await Timer(2000, 'ns')
# read status
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100118)
val = await dev_pf0_bar0.read_dword(0x000118)
tb.log.info("Status: 0x%x", val)
assert val == 0x800000AA
# write pcie write descriptor
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100200, (mem_base+0x1000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100204, (mem_base+0x1000 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100208, (0x100) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10020C, (0x100 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100210, 0x400)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100214, 0x55)
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000208, 0x100)
await dev_pf0_bar0.write_dword(0x000210, 0x400)
await dev_pf0_bar0.write_dword(0x000214, 0x55)
await Timer(2000, 'ns')
# read status
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100218)
val = await dev_pf0_bar0.read_dword(0x000218)
tb.log.info("Status: 0x%x", val)
assert val == 0x80000055
tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64))
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
assert mem[0:1024] == mem[0x1000:0x1000+1024]
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)

48
example/AU200/fpga_axi/tb/fpga_core/test_fpga_core.py
View File

@ -254,64 +254,64 @@ async def run_test(dut):
await tb.init()
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
tb.log.info("Test memory write to BAR 2")
await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
test_data = b'\x11\x22\x33\x44'
await dev_pf0_bar2.write(0, test_data)
await Timer(100, 'ns')
tb.log.info("Test memory read from BAR 2")
val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
tb.log.info("Read data: %s", val)
assert val == b'\x11\x22\x33\x44'
assert val == test_data
tb.log.info("Test DMA")
# write packet data
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
# enable DMA
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100000, 1)
await dev_pf0_bar0.write_dword(0x000000, 1)
# write pcie read descriptor
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100100, (mem_base+0x0000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100104, (mem_base+0x0000 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100108, (0x100) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10010C, (0x100 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100110, 0x400)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100114, 0xAA)
await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000108, 0x100)
await dev_pf0_bar0.write_dword(0x000110, 0x400)
await dev_pf0_bar0.write_dword(0x000114, 0xAA)
await Timer(2000, 'ns')
# read status
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100118)
val = await dev_pf0_bar0.read_dword(0x000118)
tb.log.info("Status: 0x%x", val)
assert val == 0x800000AA
# write pcie write descriptor
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100200, (mem_base+0x1000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100204, (mem_base+0x1000 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100208, (0x100) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10020C, (0x100 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100210, 0x400)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100214, 0x55)
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000208, 0x100)
await dev_pf0_bar0.write_dword(0x000210, 0x400)
await dev_pf0_bar0.write_dword(0x000214, 0x55)
await Timer(2000, 'ns')
# read status
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100218)
val = await dev_pf0_bar0.read_dword(0x000218)
tb.log.info("Status: 0x%x", val)
assert val == 0x80000055
tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64))
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
assert mem[0:1024] == mem[0x1000:0x1000+1024]
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)

48
example/AU250/fpga_axi/tb/fpga_core/test_fpga_core.py
View File

@ -254,64 +254,64 @@ async def run_test(dut):
await tb.init()
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
tb.log.info("Test memory write to BAR 2")
await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
test_data = b'\x11\x22\x33\x44'
await dev_pf0_bar2.write(0, test_data)
await Timer(100, 'ns')
tb.log.info("Test memory read from BAR 2")
val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
tb.log.info("Read data: %s", val)
assert val == b'\x11\x22\x33\x44'
assert val == test_data
tb.log.info("Test DMA")
# write packet data
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
# enable DMA
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100000, 1)
await dev_pf0_bar0.write_dword(0x000000, 1)
# write pcie read descriptor
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100100, (mem_base+0x0000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100104, (mem_base+0x0000 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100108, (0x100) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10010C, (0x100 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100110, 0x400)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100114, 0xAA)
await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000108, 0x100)
await dev_pf0_bar0.write_dword(0x000110, 0x400)
await dev_pf0_bar0.write_dword(0x000114, 0xAA)
await Timer(2000, 'ns')
# read status
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100118)
val = await dev_pf0_bar0.read_dword(0x000118)
tb.log.info("Status: 0x%x", val)
assert val == 0x800000AA
# write pcie write descriptor
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100200, (mem_base+0x1000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100204, (mem_base+0x1000 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100208, (0x100) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10020C, (0x100 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100210, 0x400)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100214, 0x55)
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000208, 0x100)
await dev_pf0_bar0.write_dword(0x000210, 0x400)
await dev_pf0_bar0.write_dword(0x000214, 0x55)
await Timer(2000, 'ns')
# read status
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100218)
val = await dev_pf0_bar0.read_dword(0x000218)
tb.log.info("Status: 0x%x", val)
assert val == 0x80000055
tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64))
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
assert mem[0:1024] == mem[0x1000:0x1000+1024]
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)

48
example/AU280/fpga_axi/tb/fpga_core/test_fpga_core.py
View File

@ -252,64 +252,64 @@ async def run_test(dut):
await tb.init()
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
tb.log.info("Test memory write to BAR 2")
await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
test_data = b'\x11\x22\x33\x44'
await dev_pf0_bar2.write(0, test_data)
await Timer(100, 'ns')
tb.log.info("Test memory read from BAR 2")
val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
tb.log.info("Read data: %s", val)
assert val == b'\x11\x22\x33\x44'
assert val == test_data
tb.log.info("Test DMA")
# write packet data
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
# enable DMA
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100000, 1)
await dev_pf0_bar0.write_dword(0x000000, 1)
# write pcie read descriptor
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100100, (mem_base+0x0000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100104, (mem_base+0x0000 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100108, (0x100) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10010C, (0x100 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100110, 0x400)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100114, 0xAA)
await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000108, 0x100)
await dev_pf0_bar0.write_dword(0x000110, 0x400)
await dev_pf0_bar0.write_dword(0x000114, 0xAA)
await Timer(2000, 'ns')
# read status
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100118)
val = await dev_pf0_bar0.read_dword(0x000118)
tb.log.info("Status: 0x%x", val)
assert val == 0x800000AA
# write pcie write descriptor
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100200, (mem_base+0x1000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100204, (mem_base+0x1000 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100208, (0x100) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10020C, (0x100 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100210, 0x400)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100214, 0x55)
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000208, 0x100)
await dev_pf0_bar0.write_dword(0x000210, 0x400)
await dev_pf0_bar0.write_dword(0x000214, 0x55)
await Timer(2000, 'ns')
# read status
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100218)
val = await dev_pf0_bar0.read_dword(0x000218)
tb.log.info("Status: 0x%x", val)
assert val == 0x80000055
tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64))
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
assert mem[0:1024] == mem[0x1000:0x1000+1024]
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)

48
example/AU50/fpga_axi/tb/fpga_core/test_fpga_core.py
View File

@ -252,64 +252,64 @@ async def run_test(dut):
await tb.init()
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
tb.log.info("Test memory write to BAR 2")
await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
test_data = b'\x11\x22\x33\x44'
await dev_pf0_bar2.write(0, test_data)
await Timer(100, 'ns')
tb.log.info("Test memory read from BAR 2")
val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
tb.log.info("Read data: %s", val)
assert val == b'\x11\x22\x33\x44'
assert val == test_data
tb.log.info("Test DMA")
# write packet data
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
# enable DMA
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100000, 1)
await dev_pf0_bar0.write_dword(0x000000, 1)
# write pcie read descriptor
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100100, (mem_base+0x0000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100104, (mem_base+0x0000 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100108, (0x100) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10010C, (0x100 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100110, 0x400)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100114, 0xAA)
await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000108, 0x100)
await dev_pf0_bar0.write_dword(0x000110, 0x400)
await dev_pf0_bar0.write_dword(0x000114, 0xAA)
await Timer(2000, 'ns')
# read status
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100118)
val = await dev_pf0_bar0.read_dword(0x000118)
tb.log.info("Status: 0x%x", val)
assert val == 0x800000AA
# write pcie write descriptor
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100200, (mem_base+0x1000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100204, (mem_base+0x1000 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100208, (0x100) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10020C, (0x100 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100210, 0x400)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100214, 0x55)
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000208, 0x100)
await dev_pf0_bar0.write_dword(0x000210, 0x400)
await dev_pf0_bar0.write_dword(0x000214, 0x55)
await Timer(2000, 'ns')
# read status
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100218)
val = await dev_pf0_bar0.read_dword(0x000218)
tb.log.info("Status: 0x%x", val)
assert val == 0x80000055
tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64))
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
assert mem[0:1024] == mem[0x1000:0x1000+1024]
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)

136
example/ExaNIC_X10/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -246,64 +246,152 @@ async def run_test(dut):
await tb.init()
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
tb.log.info("Test memory write to BAR 2")
await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
test_data = b'\x11\x22\x33\x44'
await dev_pf0_bar2.write(0, test_data)
await Timer(100, 'ns')
tb.log.info("Test memory read from BAR 2")
val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
tb.log.info("Read data: %s", val)
assert val == b'\x11\x22\x33\x44'
assert val == test_data
tb.log.info("Test DMA")
# write packet data
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
# enable DMA
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000000, 1)
await dev_pf0_bar0.write_dword(0x000000, 1)
# enable interrupts
await dev_pf0_bar0.write_dword(0x000008, 0x3)
# write pcie read descriptor
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000100, (mem_base+0x0000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000108, (0x100) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00010C, (0x100 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000110, 0x400)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000114, 0xAA)
await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000108, 0x100)
await dev_pf0_bar0.write_dword(0x000110, 0x400)
await dev_pf0_bar0.write_dword(0x000114, 0xAA)
await Timer(2000, 'ns')
# read status
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x000118)
val = await dev_pf0_bar0.read_dword(0x000118)
tb.log.info("Status: 0x%x", val)
assert val == 0x800000AA
# write pcie write descriptor
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000200, (mem_base+0x1000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000208, (0x100) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00020C, (0x100 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000210, 0x400)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000214, 0x55)
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000208, 0x100)
await dev_pf0_bar0.write_dword(0x000210, 0x400)
await dev_pf0_bar0.write_dword(0x000214, 0x55)
await Timer(2000, 'ns')
# read status
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x000218)
val = await dev_pf0_bar0.read_dword(0x000218)
tb.log.info("Status: 0x%x", val)
assert val == 0x80000055
tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64))
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
assert mem[0:1024] == mem[0x1000:0x1000+1024]
tb.log.info("Test DMA block operations")
# write packet data
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
# enable DMA
await dev_pf0_bar0.write_dword(0x000000, 1)
# disable interrupts
await dev_pf0_bar0.write_dword(0x000008, 0)
# configure operation (read)
# DMA base address
await dev_pf0_bar0.write_dword(0x001080, (mem_base+0x0000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x001084, (mem_base+0x0000 >> 32) & 0xffffffff)
# DMA offset address
await dev_pf0_bar0.write_dword(0x001088, 0)
await dev_pf0_bar0.write_dword(0x00108c, 0)
# DMA offset mask
await dev_pf0_bar0.write_dword(0x001090, 0x000003ff)
await dev_pf0_bar0.write_dword(0x001094, 0)
# DMA stride
await dev_pf0_bar0.write_dword(0x001098, 256)
await dev_pf0_bar0.write_dword(0x00109c, 0)
# RAM base address
await dev_pf0_bar0.write_dword(0x0010c0, 0)
await dev_pf0_bar0.write_dword(0x0010c4, 0)
# RAM offset address
await dev_pf0_bar0.write_dword(0x0010c8, 0)
await dev_pf0_bar0.write_dword(0x0010cc, 0)
# RAM offset mask
await dev_pf0_bar0.write_dword(0x0010d0, 0x000003ff)
await dev_pf0_bar0.write_dword(0x0010d4, 0)
# RAM stride
await dev_pf0_bar0.write_dword(0x0010d8, 256)
await dev_pf0_bar0.write_dword(0x0010dc, 0)
# clear cycle count
await dev_pf0_bar0.write_dword(0x001008, 0)
await dev_pf0_bar0.write_dword(0x00100c, 0)
# block length
await dev_pf0_bar0.write_dword(0x001010, 256)
# block count
await dev_pf0_bar0.write_dword(0x001018, 32)
await dev_pf0_bar0.write_dword(0x00101c, 0)
# start
await dev_pf0_bar0.write_dword(0x001000, 1)
await Timer(2000, 'ns')
# configure operation (write)
# DMA base address
await dev_pf0_bar0.write_dword(0x001180, (mem_base+0x0000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x001184, (mem_base+0x0000 >> 32) & 0xffffffff)
# DMA offset address
await dev_pf0_bar0.write_dword(0x001188, 0)
await dev_pf0_bar0.write_dword(0x00118c, 0)
# DMA offset mask
await dev_pf0_bar0.write_dword(0x001190, 0x000003ff)
await dev_pf0_bar0.write_dword(0x001194, 0)
# DMA stride
await dev_pf0_bar0.write_dword(0x001198, 256)
await dev_pf0_bar0.write_dword(0x00119c, 0)
# RAM base address
await dev_pf0_bar0.write_dword(0x0011c0, 0)
await dev_pf0_bar0.write_dword(0x0011c4, 0)
# RAM offset address
await dev_pf0_bar0.write_dword(0x0011c8, 0)
await dev_pf0_bar0.write_dword(0x0011cc, 0)
# RAM offset mask
await dev_pf0_bar0.write_dword(0x0011d0, 0x000003ff)
await dev_pf0_bar0.write_dword(0x0011d4, 0)
# RAM stride
await dev_pf0_bar0.write_dword(0x0011d8, 256)
await dev_pf0_bar0.write_dword(0x0011dc, 0)
# clear cycle count
await dev_pf0_bar0.write_dword(0x001108, 0)
await dev_pf0_bar0.write_dword(0x00110c, 0)
# block length
await dev_pf0_bar0.write_dword(0x001110, 256)
# block count
await dev_pf0_bar0.write_dword(0x001118, 32)
await dev_pf0_bar0.write_dword(0x00111c, 0)
# start
await dev_pf0_bar0.write_dword(0x001100, 1)
await Timer(2000, 'ns')
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)

48
example/ExaNIC_X10/fpga_axi/tb/fpga_core/test_fpga_core.py
View File

@ -246,64 +246,64 @@ async def run_test(dut):
await tb.init()
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
tb.log.info("Test memory write to BAR 2")
await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
test_data = b'\x11\x22\x33\x44'
await dev_pf0_bar2.write(0, test_data)
await Timer(100, 'ns')
tb.log.info("Test memory read from BAR 2")
val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
tb.log.info("Read data: %s", val)
assert val == b'\x11\x22\x33\x44'
assert val == test_data
tb.log.info("Test DMA")
# write packet data
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
# enable DMA
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100000, 1)
await dev_pf0_bar0.write_dword(0x000000, 1)
# write pcie read descriptor
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100100, (mem_base+0x0000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100104, (mem_base+0x0000 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100108, (0x100) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10010C, (0x100 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100110, 0x400)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100114, 0xAA)
await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000108, 0x100)
await dev_pf0_bar0.write_dword(0x000110, 0x400)
await dev_pf0_bar0.write_dword(0x000114, 0xAA)
await Timer(2000, 'ns')
# read status
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100118)
val = await dev_pf0_bar0.read_dword(0x000118)
tb.log.info("Status: 0x%x", val)
assert val == 0x800000AA
# write pcie write descriptor
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100200, (mem_base+0x1000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100204, (mem_base+0x1000 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100208, (0x100) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10020C, (0x100 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100210, 0x400)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100214, 0x55)
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000208, 0x100)
await dev_pf0_bar0.write_dword(0x000210, 0x400)
await dev_pf0_bar0.write_dword(0x000214, 0x55)
await Timer(2000, 'ns')
# read status
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100218)
val = await dev_pf0_bar0.read_dword(0x000218)
tb.log.info("Status: 0x%x", val)
assert val == 0x80000055
tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64))
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
assert mem[0:1024] == mem[0x1000:0x1000+1024]
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)

48
example/ExaNIC_X25/fpga_axi/tb/fpga_core/test_fpga_core.py
View File

@ -252,64 +252,64 @@ async def run_test(dut):
await tb.init()
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
tb.log.info("Test memory write to BAR 2")
await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
test_data = b'\x11\x22\x33\x44'
await dev_pf0_bar2.write(0, test_data)
await Timer(100, 'ns')
tb.log.info("Test memory read from BAR 2")
val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
tb.log.info("Read data: %s", val)
assert val == b'\x11\x22\x33\x44'
assert val == test_data
tb.log.info("Test DMA")
# write packet data
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
# enable DMA
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100000, 1)
await dev_pf0_bar0.write_dword(0x000000, 1)
# write pcie read descriptor
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100100, (mem_base+0x0000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100104, (mem_base+0x0000 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100108, (0x100) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10010C, (0x100 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100110, 0x400)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100114, 0xAA)
await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000108, 0x100)
await dev_pf0_bar0.write_dword(0x000110, 0x400)
await dev_pf0_bar0.write_dword(0x000114, 0xAA)
await Timer(2000, 'ns')
# read status
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100118)
val = await dev_pf0_bar0.read_dword(0x000118)
tb.log.info("Status: 0x%x", val)
assert val == 0x800000AA
# write pcie write descriptor
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100200, (mem_base+0x1000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100204, (mem_base+0x1000 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100208, (0x100) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10020C, (0x100 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100210, 0x400)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100214, 0x55)
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000208, 0x100)
await dev_pf0_bar0.write_dword(0x000210, 0x400)
await dev_pf0_bar0.write_dword(0x000214, 0x55)
await Timer(2000, 'ns')
# read status
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100218)
val = await dev_pf0_bar0.read_dword(0x000218)
tb.log.info("Status: 0x%x", val)
assert val == 0x80000055
tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64))
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
assert mem[0:1024] == mem[0x1000:0x1000+1024]
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)

51
example/S10MX_DK/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -174,67 +174,66 @@ async def run_test(dut):
await tb.init()
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
tb.log.info("Test memory write to BAR 2")
await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
test_data = b'\x11\x22\x33\x44'
await dev_pf0_bar2.write(0, test_data)
await Timer(100, 'ns')
tb.log.info("Test memory read from BAR 2")
val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
tb.log.info("Read data: %s", val)
assert val == b'\x11\x22\x33\x44'
assert val == test_data
tb.log.info("Test DMA")
# write packet data
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
# enable DMA
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000000, 1)
await dev_pf0_bar0.write_dword(0x000000, 1)
# enable interrupts
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000008, 3)
await dev_pf0_bar0.write_dword(0x000008, 0x3)
# write pcie read descriptor
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000100, (mem_base+0x0000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000108, (0x100) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00010C, (0x100 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000110, 0x400)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000114, 0xAA)
await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000108, 0x100)
await dev_pf0_bar0.write_dword(0x000110, 0x400)
await dev_pf0_bar0.write_dword(0x000114, 0xAA)
await Timer(2000, 'ns')
# read status
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x000118)
val = await dev_pf0_bar0.read_dword(0x000118)
tb.log.info("Status: 0x%x", val)
assert val == 0x800000AA
# write pcie write descriptor
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000200, (mem_base+0x1000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000208, (0x100) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00020C, (0x100 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000210, 0x400)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000214, 0x55)
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000208, 0x100)
await dev_pf0_bar0.write_dword(0x000210, 0x400)
await dev_pf0_bar0.write_dword(0x000214, 0x55)
await Timer(2000, 'ns')
# read status
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x000218)
val = await dev_pf0_bar0.read_dword(0x000218)
tb.log.info("Status: 0x%x", val)
assert val == 0x80000055
tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64))
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
assert mem[0:1024] == mem[0x1000:0x1000+1024]
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)

48
example/VCU108/fpga_axi/tb/fpga_core/test_fpga_core.py
View File

@ -253,64 +253,64 @@ async def run_test(dut):
await tb.init()
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
tb.log.info("Test memory write to BAR 2")
await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
test_data = b'\x11\x22\x33\x44'
await dev_pf0_bar2.write(0, test_data)
await Timer(100, 'ns')
tb.log.info("Test memory read from BAR 2")
val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
tb.log.info("Read data: %s", val)
assert val == b'\x11\x22\x33\x44'
assert val == test_data
tb.log.info("Test DMA")
# write packet data
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
# enable DMA
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100000, 1)
await dev_pf0_bar0.write_dword(0x000000, 1)
# write pcie read descriptor
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100100, (mem_base+0x0000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100104, (mem_base+0x0000 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100108, (0x100) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10010C, (0x100 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100110, 0x400)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100114, 0xAA)
await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000108, 0x100)
await dev_pf0_bar0.write_dword(0x000110, 0x400)
await dev_pf0_bar0.write_dword(0x000114, 0xAA)
await Timer(2000, 'ns')
# read status
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100118)
val = await dev_pf0_bar0.read_dword(0x000118)
tb.log.info("Status: 0x%x", val)
assert val == 0x800000AA
# write pcie write descriptor
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100200, (mem_base+0x1000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100204, (mem_base+0x1000 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100208, (0x100) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10020C, (0x100 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100210, 0x400)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100214, 0x55)
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000208, 0x100)
await dev_pf0_bar0.write_dword(0x000210, 0x400)
await dev_pf0_bar0.write_dword(0x000214, 0x55)
await Timer(2000, 'ns')
# read status
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100218)
val = await dev_pf0_bar0.read_dword(0x000218)
tb.log.info("Status: 0x%x", val)
assert val == 0x80000055
tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64))
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
assert mem[0:1024] == mem[0x1000:0x1000+1024]
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)

48
example/VCU118/fpga_axi/tb/fpga_core/test_fpga_core.py
View File

@ -259,64 +259,64 @@ async def run_test(dut):
await tb.init()
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
tb.log.info("Test memory write to BAR 2")
await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
test_data = b'\x11\x22\x33\x44'
await dev_pf0_bar2.write(0, test_data)
await Timer(100, 'ns')
tb.log.info("Test memory read from BAR 2")
val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
tb.log.info("Read data: %s", val)
assert val == b'\x11\x22\x33\x44'
assert val == test_data
tb.log.info("Test DMA")
# write packet data
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
# enable DMA
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100000, 1)
await dev_pf0_bar0.write_dword(0x000000, 1)
# write pcie read descriptor
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100100, (mem_base+0x0000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100104, (mem_base+0x0000 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100108, (0x100) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10010C, (0x100 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100110, 0x400)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100114, 0xAA)
await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000108, 0x100)
await dev_pf0_bar0.write_dword(0x000110, 0x400)
await dev_pf0_bar0.write_dword(0x000114, 0xAA)
await Timer(2000, 'ns')
# read status
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100118)
val = await dev_pf0_bar0.read_dword(0x000118)
tb.log.info("Status: 0x%x", val)
assert val == 0x800000AA
# write pcie write descriptor
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100200, (mem_base+0x1000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100204, (mem_base+0x1000 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100208, (0x100) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10020C, (0x100 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100210, 0x400)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100214, 0x55)
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000208, 0x100)
await dev_pf0_bar0.write_dword(0x000210, 0x400)
await dev_pf0_bar0.write_dword(0x000214, 0x55)
await Timer(2000, 'ns')
# read status
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100218)
val = await dev_pf0_bar0.read_dword(0x000218)
tb.log.info("Status: 0x%x", val)
assert val == 0x80000055
tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64))
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
assert mem[0:1024] == mem[0x1000:0x1000+1024]
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)

48
example/VCU1525/fpga_axi/tb/fpga_core/test_fpga_core.py
View File

@ -254,64 +254,64 @@ async def run_test(dut):
await tb.init()
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
tb.log.info("Test memory write to BAR 2")
await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
test_data = b'\x11\x22\x33\x44'
await dev_pf0_bar2.write(0, test_data)
await Timer(100, 'ns')
tb.log.info("Test memory read from BAR 2")
val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
tb.log.info("Read data: %s", val)
assert val == b'\x11\x22\x33\x44'
assert val == test_data
tb.log.info("Test DMA")
# write packet data
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
# enable DMA
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100000, 1)
await dev_pf0_bar0.write_dword(0x000000, 1)
# write pcie read descriptor
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100100, (mem_base+0x0000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100104, (mem_base+0x0000 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100108, (0x100) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10010C, (0x100 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100110, 0x400)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100114, 0xAA)
await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000108, 0x100)
await dev_pf0_bar0.write_dword(0x000110, 0x400)
await dev_pf0_bar0.write_dword(0x000114, 0xAA)
await Timer(2000, 'ns')
# read status
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100118)
val = await dev_pf0_bar0.read_dword(0x000118)
tb.log.info("Status: 0x%x", val)
assert val == 0x800000AA
# write pcie write descriptor
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100200, (mem_base+0x1000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100204, (mem_base+0x1000 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100208, (0x100) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10020C, (0x100 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100210, 0x400)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100214, 0x55)
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000208, 0x100)
await dev_pf0_bar0.write_dword(0x000210, 0x400)
await dev_pf0_bar0.write_dword(0x000214, 0x55)
await Timer(2000, 'ns')
# read status
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100218)
val = await dev_pf0_bar0.read_dword(0x000218)
tb.log.info("Status: 0x%x", val)
assert val == 0x80000055
tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64))
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
assert mem[0:1024] == mem[0x1000:0x1000+1024]
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)

48
example/ZCU106/fpga_axi/tb/fpga_core/test_fpga_core.py
View File

@ -259,64 +259,64 @@ async def run_test(dut):
await tb.init()
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
tb.log.info("Test memory write to BAR 2")
await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
test_data = b'\x11\x22\x33\x44'
await dev_pf0_bar2.write(0, test_data)
await Timer(100, 'ns')
tb.log.info("Test memory read from BAR 2")
val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
tb.log.info("Read data: %s", val)
assert val == b'\x11\x22\x33\x44'
assert val == test_data
tb.log.info("Test DMA")
# write packet data
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
# enable DMA
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100000, 1)
await dev_pf0_bar0.write_dword(0x000000, 1)
# write pcie read descriptor
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100100, (mem_base+0x0000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100104, (mem_base+0x0000 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100108, (0x100) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10010C, (0x100 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100110, 0x400)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100114, 0xAA)
await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000108, 0x100)
await dev_pf0_bar0.write_dword(0x000110, 0x400)
await dev_pf0_bar0.write_dword(0x000114, 0xAA)
await Timer(2000, 'ns')
# read status
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100118)
val = await dev_pf0_bar0.read_dword(0x000118)
tb.log.info("Status: 0x%x", val)
assert val == 0x800000AA
# write pcie write descriptor
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100200, (mem_base+0x1000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100204, (mem_base+0x1000 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100208, (0x100) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10020C, (0x100 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100210, 0x400)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100214, 0x55)
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000208, 0x100)
await dev_pf0_bar0.write_dword(0x000210, 0x400)
await dev_pf0_bar0.write_dword(0x000214, 0x55)
await Timer(2000, 'ns')
# read status
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100218)
val = await dev_pf0_bar0.read_dword(0x000218)
tb.log.info("Status: 0x%x", val)
assert val == 0x80000055
tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64))
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
assert mem[0:1024] == mem[0x1000:0x1000+1024]
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)

142
example/common/tb/example_core_pcie/test_example_core_pcie.py
View File

@ -137,150 +137,152 @@ async def run_test(dut):
await tb.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
tb.dut.bus_num.value = tb.dev.bus_num
tb.log.info("Test memory write to BAR 2")
await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
test_data = b'\x11\x22\x33\x44'
await dev_pf0_bar2.write(0, test_data)
await Timer(100, 'ns')
tb.log.info("Test memory read from BAR 2")
val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
tb.log.info("Read data: %s", val)
assert val == b'\x11\x22\x33\x44'
assert val == test_data
tb.log.info("Test DMA")
# write packet data
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
# enable DMA
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000000, 1)
await dev_pf0_bar0.write_dword(0x000000, 1)
# enable interrupts
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000008, 0x3)
await dev_pf0_bar0.write_dword(0x000008, 0x3)
# write pcie read descriptor
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000100, (mem_base+0x0000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000108, 0x100)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000110, 0x400)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000114, 0xAA)
await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000108, 0x100)
await dev_pf0_bar0.write_dword(0x000110, 0x400)
await dev_pf0_bar0.write_dword(0x000114, 0xAA)
await Timer(2000, 'ns')
# read status
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x000118)
val = await dev_pf0_bar0.read_dword(0x000118)
tb.log.info("Status: 0x%x", val)
assert val == 0x800000AA
# write pcie write descriptor
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000200, (mem_base+0x1000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000208, 0x100)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000210, 0x400)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000214, 0x55)
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000208, 0x100)
await dev_pf0_bar0.write_dword(0x000210, 0x400)
await dev_pf0_bar0.write_dword(0x000214, 0x55)
await Timer(2000, 'ns')
# read status
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100218)
val = await dev_pf0_bar0.read_dword(0x000218)
tb.log.info("Status: 0x%x", val)
assert val == 0x80000055
tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64))
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
assert mem[0:1024] == mem[0x1000:0x1000+1024]
tb.log.info("Test DMA block operations")
# write packet data
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
# enable DMA
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000000, 1)
await dev_pf0_bar0.write_dword(0x000000, 1)
# disable interrupts
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000008, 0)
await dev_pf0_bar0.write_dword(0x000008, 0)
# configure operation (read)
# DMA base address
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001080, (mem_base+0x0000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001084, (mem_base+0x0000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x001080, (mem_base+0x0000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x001084, (mem_base+0x0000 >> 32) & 0xffffffff)
# DMA offset address
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001088, 0)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00108c, 0)
await dev_pf0_bar0.write_dword(0x001088, 0)
await dev_pf0_bar0.write_dword(0x00108c, 0)
# DMA offset mask
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001090, 0x000003ff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001094, 0)
await dev_pf0_bar0.write_dword(0x001090, 0x000003ff)
await dev_pf0_bar0.write_dword(0x001094, 0)
# DMA stride
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001098, 256)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00109c, 0)
await dev_pf0_bar0.write_dword(0x001098, 256)
await dev_pf0_bar0.write_dword(0x00109c, 0)
# RAM base address
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010c0, 0)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010c4, 0)
await dev_pf0_bar0.write_dword(0x0010c0, 0)
await dev_pf0_bar0.write_dword(0x0010c4, 0)
# RAM offset address
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010c8, 0)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010cc, 0)
await dev_pf0_bar0.write_dword(0x0010c8, 0)
await dev_pf0_bar0.write_dword(0x0010cc, 0)
# RAM offset mask
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010d0, 0x000003ff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010d4, 0)
await dev_pf0_bar0.write_dword(0x0010d0, 0x000003ff)
await dev_pf0_bar0.write_dword(0x0010d4, 0)
# RAM stride
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010d8, 256)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010dc, 0)
await dev_pf0_bar0.write_dword(0x0010d8, 256)
await dev_pf0_bar0.write_dword(0x0010dc, 0)
# clear cycle count
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001008, 0)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00100c, 0)
await dev_pf0_bar0.write_dword(0x001008, 0)
await dev_pf0_bar0.write_dword(0x00100c, 0)
# block length
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001010, 256)
await dev_pf0_bar0.write_dword(0x001010, 256)
# block count
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001018, 32)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00101c, 0)
await dev_pf0_bar0.write_dword(0x001018, 32)
await dev_pf0_bar0.write_dword(0x00101c, 0)
# start
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001000, 1)
await dev_pf0_bar0.write_dword(0x001000, 1)
await Timer(2000, 'ns')
# configure operation (write)
# DMA base address
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001180, (mem_base+0x0000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001184, (mem_base+0x0000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x001180, (mem_base+0x0000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x001184, (mem_base+0x0000 >> 32) & 0xffffffff)
# DMA offset address
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001188, 0)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00118c, 0)
await dev_pf0_bar0.write_dword(0x001188, 0)
await dev_pf0_bar0.write_dword(0x00118c, 0)
# DMA offset mask
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001190, 0x000003ff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001194, 0)
await dev_pf0_bar0.write_dword(0x001190, 0x000003ff)
await dev_pf0_bar0.write_dword(0x001194, 0)
# DMA stride
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001198, 256)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00119c, 0)
await dev_pf0_bar0.write_dword(0x001198, 256)
await dev_pf0_bar0.write_dword(0x00119c, 0)
# RAM base address
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011c0, 0)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011c4, 0)
await dev_pf0_bar0.write_dword(0x0011c0, 0)
await dev_pf0_bar0.write_dword(0x0011c4, 0)
# RAM offset address
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011c8, 0)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011cc, 0)
await dev_pf0_bar0.write_dword(0x0011c8, 0)
await dev_pf0_bar0.write_dword(0x0011cc, 0)
# RAM offset mask
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011d0, 0x000003ff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011d4, 0)
await dev_pf0_bar0.write_dword(0x0011d0, 0x000003ff)
await dev_pf0_bar0.write_dword(0x0011d4, 0)
# RAM stride
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011d8, 256)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011dc, 0)
await dev_pf0_bar0.write_dword(0x0011d8, 256)
await dev_pf0_bar0.write_dword(0x0011dc, 0)
# clear cycle count
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001108, 0)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00110c, 0)
await dev_pf0_bar0.write_dword(0x001108, 0)
await dev_pf0_bar0.write_dword(0x00110c, 0)
# block length
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001110, 256)
await dev_pf0_bar0.write_dword(0x001110, 256)
# block count
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001118, 32)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00111c, 0)
await dev_pf0_bar0.write_dword(0x001118, 32)
await dev_pf0_bar0.write_dword(0x00111c, 0)
# start
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001100, 1)
await dev_pf0_bar0.write_dword(0x001100, 1)
await Timer(2000, 'ns')

142
example/common/tb/example_core_pcie_s10/test_example_core_pcie_s10.py
View File

@ -177,148 +177,150 @@ async def run_test(dut):
await tb.init()
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
tb.log.info("Test memory write to BAR 2")
await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
test_data = b'\x11\x22\x33\x44'
await dev_pf0_bar2.write(0, test_data)
await Timer(100, 'ns')
tb.log.info("Test memory read from BAR 2")
val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
tb.log.info("Read data: %s", val)
assert val == b'\x11\x22\x33\x44'
assert val == test_data
tb.log.info("Test DMA")
# write packet data
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
# enable DMA
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000000, 1)
await dev_pf0_bar0.write_dword(0x000000, 1)
# enable interrupts
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000008, 0x3)
await dev_pf0_bar0.write_dword(0x000008, 0x3)
# write pcie read descriptor
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000100, (mem_base+0x0000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000108, 0x100)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000110, 0x400)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000114, 0xAA)
await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000108, 0x100)
await dev_pf0_bar0.write_dword(0x000110, 0x400)
await dev_pf0_bar0.write_dword(0x000114, 0xAA)
await Timer(2000, 'ns')
# read status
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x000118)
val = await dev_pf0_bar0.read_dword(0x000118)
tb.log.info("Status: 0x%x", val)
assert val == 0x800000AA
# write pcie write descriptor
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000200, (mem_base+0x1000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000208, 0x100)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000210, 0x400)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000214, 0x55)
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000208, 0x100)
await dev_pf0_bar0.write_dword(0x000210, 0x400)
await dev_pf0_bar0.write_dword(0x000214, 0x55)
await Timer(2000, 'ns')
# read status
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x000218)
val = await dev_pf0_bar0.read_dword(0x000218)
tb.log.info("Status: 0x%x", val)
assert val == 0x80000055
tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64))
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
assert mem[0:1024] == mem[0x1000:0x1000+1024]
tb.log.info("Test DMA block operations")
# write packet data
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
# enable DMA
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000000, 1)
await dev_pf0_bar0.write_dword(0x000000, 1)
# disable interrupts
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000008, 0)
await dev_pf0_bar0.write_dword(0x000008, 0)
# configure operation (read)
# DMA base address
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001080, (mem_base+0x0000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001084, (mem_base+0x0000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x001080, (mem_base+0x0000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x001084, (mem_base+0x0000 >> 32) & 0xffffffff)
# DMA offset address
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001088, 0)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00108c, 0)
await dev_pf0_bar0.write_dword(0x001088, 0)
await dev_pf0_bar0.write_dword(0x00108c, 0)
# DMA offset mask
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001090, 0x000003ff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001094, 0)
await dev_pf0_bar0.write_dword(0x001090, 0x000003ff)
await dev_pf0_bar0.write_dword(0x001094, 0)
# DMA stride
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001098, 256)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00109c, 0)
await dev_pf0_bar0.write_dword(0x001098, 256)
await dev_pf0_bar0.write_dword(0x00109c, 0)
# RAM base address
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010c0, 0)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010c4, 0)
await dev_pf0_bar0.write_dword(0x0010c0, 0)
await dev_pf0_bar0.write_dword(0x0010c4, 0)
# RAM offset address
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010c8, 0)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010cc, 0)
await dev_pf0_bar0.write_dword(0x0010c8, 0)
await dev_pf0_bar0.write_dword(0x0010cc, 0)
# RAM offset mask
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010d0, 0x000003ff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010d4, 0)
await dev_pf0_bar0.write_dword(0x0010d0, 0x000003ff)
await dev_pf0_bar0.write_dword(0x0010d4, 0)
# RAM stride
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010d8, 256)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010dc, 0)
await dev_pf0_bar0.write_dword(0x0010d8, 256)
await dev_pf0_bar0.write_dword(0x0010dc, 0)
# clear cycle count
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001008, 0)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00100c, 0)
await dev_pf0_bar0.write_dword(0x001008, 0)
await dev_pf0_bar0.write_dword(0x00100c, 0)
# block length
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001010, 256)
await dev_pf0_bar0.write_dword(0x001010, 256)
# block count
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001018, 32)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00101c, 0)
await dev_pf0_bar0.write_dword(0x001018, 32)
await dev_pf0_bar0.write_dword(0x00101c, 0)
# start
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001000, 1)
await dev_pf0_bar0.write_dword(0x001000, 1)
await Timer(2000, 'ns')
# configure operation (write)
# DMA base address
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001180, (mem_base+0x0000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001184, (mem_base+0x0000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x001180, (mem_base+0x0000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x001184, (mem_base+0x0000 >> 32) & 0xffffffff)
# DMA offset address
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001188, 0)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00118c, 0)
await dev_pf0_bar0.write_dword(0x001188, 0)
await dev_pf0_bar0.write_dword(0x00118c, 0)
# DMA offset mask
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001190, 0x000003ff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001194, 0)
await dev_pf0_bar0.write_dword(0x001190, 0x000003ff)
await dev_pf0_bar0.write_dword(0x001194, 0)
# DMA stride
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001198, 256)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00119c, 0)
await dev_pf0_bar0.write_dword(0x001198, 256)
await dev_pf0_bar0.write_dword(0x00119c, 0)
# RAM base address
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011c0, 0)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011c4, 0)
await dev_pf0_bar0.write_dword(0x0011c0, 0)
await dev_pf0_bar0.write_dword(0x0011c4, 0)
# RAM offset address
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011c8, 0)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011cc, 0)
await dev_pf0_bar0.write_dword(0x0011c8, 0)
await dev_pf0_bar0.write_dword(0x0011cc, 0)
# RAM offset mask
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011d0, 0x000003ff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011d4, 0)
await dev_pf0_bar0.write_dword(0x0011d0, 0x000003ff)
await dev_pf0_bar0.write_dword(0x0011d4, 0)
# RAM stride
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011d8, 256)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011dc, 0)
await dev_pf0_bar0.write_dword(0x0011d8, 256)
await dev_pf0_bar0.write_dword(0x0011dc, 0)
# clear cycle count
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001108, 0)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00110c, 0)
await dev_pf0_bar0.write_dword(0x001108, 0)
await dev_pf0_bar0.write_dword(0x00110c, 0)
# block length
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001110, 256)
await dev_pf0_bar0.write_dword(0x001110, 256)
# block count
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001118, 32)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00111c, 0)
await dev_pf0_bar0.write_dword(0x001118, 32)
await dev_pf0_bar0.write_dword(0x00111c, 0)
# start
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001100, 1)
await dev_pf0_bar0.write_dword(0x001100, 1)
await Timer(2000, 'ns')

142
example/common/tb/example_core_pcie_us/test_example_core_pcie_us.py
View File

@ -271,148 +271,150 @@ async def run_test(dut):
await tb.init()
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
tb.log.info("Test memory write to BAR 2")
await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
test_data = b'\x11\x22\x33\x44'
await dev_pf0_bar2.write(0, test_data)
await Timer(100, 'ns')
tb.log.info("Test memory read from BAR 2")
val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
tb.log.info("Read data: %s", val)
assert val == b'\x11\x22\x33\x44'
assert val == test_data
tb.log.info("Test DMA")
# write packet data
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
# enable DMA
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000000, 1)
await dev_pf0_bar0.write_dword(0x000000, 1)
# enable interrupts
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000008, 0x3)
await dev_pf0_bar0.write_dword(0x000008, 0x3)
# write pcie read descriptor
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000100, (mem_base+0x0000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000108, 0x100)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000110, 0x400)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000114, 0xAA)
await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000108, 0x100)
await dev_pf0_bar0.write_dword(0x000110, 0x400)
await dev_pf0_bar0.write_dword(0x000114, 0xAA)
await Timer(2000, 'ns')
# read status
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x000118)
val = await dev_pf0_bar0.read_dword(0x000118)
tb.log.info("Status: 0x%x", val)
assert val == 0x800000AA
# write pcie write descriptor
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000200, (mem_base+0x1000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000208, 0x100)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000210, 0x400)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000214, 0x55)
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000208, 0x100)
await dev_pf0_bar0.write_dword(0x000210, 0x400)
await dev_pf0_bar0.write_dword(0x000214, 0x55)
await Timer(2000, 'ns')
# read status
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x000218)
val = await dev_pf0_bar0.read_dword(0x000218)
tb.log.info("Status: 0x%x", val)
assert val == 0x80000055
tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64))
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
assert mem[0:1024] == mem[0x1000:0x1000+1024]
tb.log.info("Test DMA block operations")
# write packet data
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
# enable DMA
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000000, 1)
await dev_pf0_bar0.write_dword(0x000000, 1)
# disable interrupts
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000008, 0)
await dev_pf0_bar0.write_dword(0x000008, 0)
# configure operation (read)
# DMA base address
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001080, (mem_base+0x0000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001084, (mem_base+0x0000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x001080, (mem_base+0x0000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x001084, (mem_base+0x0000 >> 32) & 0xffffffff)
# DMA offset address
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001088, 0)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00108c, 0)
await dev_pf0_bar0.write_dword(0x001088, 0)
await dev_pf0_bar0.write_dword(0x00108c, 0)
# DMA offset mask
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001090, 0x000003ff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001094, 0)
await dev_pf0_bar0.write_dword(0x001090, 0x000003ff)
await dev_pf0_bar0.write_dword(0x001094, 0)
# DMA stride
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001098, 256)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00109c, 0)
await dev_pf0_bar0.write_dword(0x001098, 256)
await dev_pf0_bar0.write_dword(0x00109c, 0)
# RAM base address
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010c0, 0)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010c4, 0)
await dev_pf0_bar0.write_dword(0x0010c0, 0)
await dev_pf0_bar0.write_dword(0x0010c4, 0)
# RAM offset address
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010c8, 0)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010cc, 0)
await dev_pf0_bar0.write_dword(0x0010c8, 0)
await dev_pf0_bar0.write_dword(0x0010cc, 0)
# RAM offset mask
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010d0, 0x000003ff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010d4, 0)
await dev_pf0_bar0.write_dword(0x0010d0, 0x000003ff)
await dev_pf0_bar0.write_dword(0x0010d4, 0)
# RAM stride
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010d8, 256)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0010dc, 0)
await dev_pf0_bar0.write_dword(0x0010d8, 256)
await dev_pf0_bar0.write_dword(0x0010dc, 0)
# clear cycle count
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001008, 0)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00100c, 0)
await dev_pf0_bar0.write_dword(0x001008, 0)
await dev_pf0_bar0.write_dword(0x00100c, 0)
# block length
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001010, 256)
await dev_pf0_bar0.write_dword(0x001010, 256)
# block count
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001018, 32)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00101c, 0)
await dev_pf0_bar0.write_dword(0x001018, 32)
await dev_pf0_bar0.write_dword(0x00101c, 0)
# start
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001000, 1)
await dev_pf0_bar0.write_dword(0x001000, 1)
await Timer(2000, 'ns')
# configure operation (write)
# DMA base address
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001180, (mem_base+0x0000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001184, (mem_base+0x0000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x001180, (mem_base+0x0000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x001184, (mem_base+0x0000 >> 32) & 0xffffffff)
# DMA offset address
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001188, 0)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00118c, 0)
await dev_pf0_bar0.write_dword(0x001188, 0)
await dev_pf0_bar0.write_dword(0x00118c, 0)
# DMA offset mask
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001190, 0x000003ff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001194, 0)
await dev_pf0_bar0.write_dword(0x001190, 0x000003ff)
await dev_pf0_bar0.write_dword(0x001194, 0)
# DMA stride
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001198, 256)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00119c, 0)
await dev_pf0_bar0.write_dword(0x001198, 256)
await dev_pf0_bar0.write_dword(0x00119c, 0)
# RAM base address
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011c0, 0)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011c4, 0)
await dev_pf0_bar0.write_dword(0x0011c0, 0)
await dev_pf0_bar0.write_dword(0x0011c4, 0)
# RAM offset address
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011c8, 0)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011cc, 0)
await dev_pf0_bar0.write_dword(0x0011c8, 0)
await dev_pf0_bar0.write_dword(0x0011cc, 0)
# RAM offset mask
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011d0, 0x000003ff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011d4, 0)
await dev_pf0_bar0.write_dword(0x0011d0, 0x000003ff)
await dev_pf0_bar0.write_dword(0x0011d4, 0)
# RAM stride
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011d8, 256)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x0011dc, 0)
await dev_pf0_bar0.write_dword(0x0011d8, 256)
await dev_pf0_bar0.write_dword(0x0011dc, 0)
# clear cycle count
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001108, 0)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00110c, 0)
await dev_pf0_bar0.write_dword(0x001108, 0)
await dev_pf0_bar0.write_dword(0x00110c, 0)
# block length
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001110, 256)
await dev_pf0_bar0.write_dword(0x001110, 256)
# block count
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001118, 32)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00111c, 0)
await dev_pf0_bar0.write_dword(0x001118, 32)
await dev_pf0_bar0.write_dword(0x00111c, 0)
# start
await tb.rc.mem_write_dword(dev_pf0_bar0+0x001100, 1)
await dev_pf0_bar0.write_dword(0x001100, 1)
await Timer(2000, 'ns')

136
example/fb2CG/fpga/tb/fpga_core/test_fpga_core.py
View File

@ -252,64 +252,152 @@ async def run_test(dut):
await tb.init()
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
tb.log.info("Test memory write to BAR 2")
await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
test_data = b'\x11\x22\x33\x44'
await dev_pf0_bar2.write(0, test_data)
await Timer(100, 'ns')
tb.log.info("Test memory read from BAR 2")
val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
tb.log.info("Read data: %s", val)
assert val == b'\x11\x22\x33\x44'
assert val == test_data
tb.log.info("Test DMA")
# write packet data
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
# enable DMA
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000000, 1)
await dev_pf0_bar0.write_dword(0x000000, 1)
# enable interrupts
await dev_pf0_bar0.write_dword(0x000008, 0x3)
# write pcie read descriptor
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000100, (mem_base+0x0000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000108, (0x100) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00010C, (0x100 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000110, 0x400)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000114, 0xAA)
await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000108, 0x100)
await dev_pf0_bar0.write_dword(0x000110, 0x400)
await dev_pf0_bar0.write_dword(0x000114, 0xAA)
await Timer(2000, 'ns')
# read status
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x000118)
val = await dev_pf0_bar0.read_dword(0x000118)
tb.log.info("Status: 0x%x", val)
assert val == 0x800000AA
# write pcie write descriptor
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000200, (mem_base+0x1000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000208, (0x100) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x00020C, (0x100 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000210, 0x400)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x000214, 0x55)
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000208, 0x100)
await dev_pf0_bar0.write_dword(0x000210, 0x400)
await dev_pf0_bar0.write_dword(0x000214, 0x55)
await Timer(2000, 'ns')
# read status
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x000218)
val = await dev_pf0_bar0.read_dword(0x000218)
tb.log.info("Status: 0x%x", val)
assert val == 0x80000055
tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64))
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
assert mem[0:1024] == mem[0x1000:0x1000+1024]
tb.log.info("Test DMA block operations")
# write packet data
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
# enable DMA
await dev_pf0_bar0.write_dword(0x000000, 1)
# disable interrupts
await dev_pf0_bar0.write_dword(0x000008, 0)
# configure operation (read)
# DMA base address
await dev_pf0_bar0.write_dword(0x001080, (mem_base+0x0000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x001084, (mem_base+0x0000 >> 32) & 0xffffffff)
# DMA offset address
await dev_pf0_bar0.write_dword(0x001088, 0)
await dev_pf0_bar0.write_dword(0x00108c, 0)
# DMA offset mask
await dev_pf0_bar0.write_dword(0x001090, 0x000003ff)
await dev_pf0_bar0.write_dword(0x001094, 0)
# DMA stride
await dev_pf0_bar0.write_dword(0x001098, 256)
await dev_pf0_bar0.write_dword(0x00109c, 0)
# RAM base address
await dev_pf0_bar0.write_dword(0x0010c0, 0)
await dev_pf0_bar0.write_dword(0x0010c4, 0)
# RAM offset address
await dev_pf0_bar0.write_dword(0x0010c8, 0)
await dev_pf0_bar0.write_dword(0x0010cc, 0)
# RAM offset mask
await dev_pf0_bar0.write_dword(0x0010d0, 0x000003ff)
await dev_pf0_bar0.write_dword(0x0010d4, 0)
# RAM stride
await dev_pf0_bar0.write_dword(0x0010d8, 256)
await dev_pf0_bar0.write_dword(0x0010dc, 0)
# clear cycle count
await dev_pf0_bar0.write_dword(0x001008, 0)
await dev_pf0_bar0.write_dword(0x00100c, 0)
# block length
await dev_pf0_bar0.write_dword(0x001010, 256)
# block count
await dev_pf0_bar0.write_dword(0x001018, 32)
await dev_pf0_bar0.write_dword(0x00101c, 0)
# start
await dev_pf0_bar0.write_dword(0x001000, 1)
await Timer(2000, 'ns')
# configure operation (write)
# DMA base address
await dev_pf0_bar0.write_dword(0x001180, (mem_base+0x0000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x001184, (mem_base+0x0000 >> 32) & 0xffffffff)
# DMA offset address
await dev_pf0_bar0.write_dword(0x001188, 0)
await dev_pf0_bar0.write_dword(0x00118c, 0)
# DMA offset mask
await dev_pf0_bar0.write_dword(0x001190, 0x000003ff)
await dev_pf0_bar0.write_dword(0x001194, 0)
# DMA stride
await dev_pf0_bar0.write_dword(0x001198, 256)
await dev_pf0_bar0.write_dword(0x00119c, 0)
# RAM base address
await dev_pf0_bar0.write_dword(0x0011c0, 0)
await dev_pf0_bar0.write_dword(0x0011c4, 0)
# RAM offset address
await dev_pf0_bar0.write_dword(0x0011c8, 0)
await dev_pf0_bar0.write_dword(0x0011cc, 0)
# RAM offset mask
await dev_pf0_bar0.write_dword(0x0011d0, 0x000003ff)
await dev_pf0_bar0.write_dword(0x0011d4, 0)
# RAM stride
await dev_pf0_bar0.write_dword(0x0011d8, 256)
await dev_pf0_bar0.write_dword(0x0011dc, 0)
# clear cycle count
await dev_pf0_bar0.write_dword(0x001108, 0)
await dev_pf0_bar0.write_dword(0x00110c, 0)
# block length
await dev_pf0_bar0.write_dword(0x001110, 256)
# block count
await dev_pf0_bar0.write_dword(0x001118, 32)
await dev_pf0_bar0.write_dword(0x00111c, 0)
# start
await dev_pf0_bar0.write_dword(0x001100, 1)
await Timer(2000, 'ns')
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)

48
example/fb2CG/fpga_axi/tb/fpga_core/test_fpga_core.py
View File

@ -252,64 +252,64 @@ async def run_test(dut):
await tb.init()
mem_base, mem_data = tb.rc.alloc_region(16*1024*1024)
mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
mem_base = mem.get_absolute_address(0)
dev_pf0_bar0 = tb.rc.tree[0][0].bar_addr[0]
dev_pf0_bar2 = tb.rc.tree[0][0].bar_addr[2]
dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
tb.log.info("Test memory write to BAR 2")
await tb.rc.mem_write(dev_pf0_bar2, b'\x11\x22\x33\x44')
test_data = b'\x11\x22\x33\x44'
await dev_pf0_bar2.write(0, test_data)
await Timer(100, 'ns')
tb.log.info("Test memory read from BAR 2")
val = await tb.rc.mem_read(dev_pf0_bar2, 4, 1000)
val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
tb.log.info("Read data: %s", val)
assert val == b'\x11\x22\x33\x44'
assert val == test_data
tb.log.info("Test DMA")
# write packet data
mem_data[0:1024] = bytearray([x % 256 for x in range(1024)])
mem[0:1024] = bytearray([x % 256 for x in range(1024)])
# enable DMA
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100000, 1)
await dev_pf0_bar0.write_dword(0x000000, 1)
# write pcie read descriptor
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100100, (mem_base+0x0000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100104, (mem_base+0x0000 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100108, (0x100) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10010C, (0x100 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100110, 0x400)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100114, 0xAA)
await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000108, 0x100)
await dev_pf0_bar0.write_dword(0x000110, 0x400)
await dev_pf0_bar0.write_dword(0x000114, 0xAA)
await Timer(2000, 'ns')
# read status
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100118)
val = await dev_pf0_bar0.read_dword(0x000118)
tb.log.info("Status: 0x%x", val)
assert val == 0x800000AA
# write pcie write descriptor
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100200, (mem_base+0x1000) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100204, (mem_base+0x1000 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100208, (0x100) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x10020C, (0x100 >> 32) & 0xffffffff)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100210, 0x400)
await tb.rc.mem_write_dword(dev_pf0_bar0+0x100214, 0x55)
await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
await dev_pf0_bar0.write_dword(0x000208, 0x100)
await dev_pf0_bar0.write_dword(0x000210, 0x400)
await dev_pf0_bar0.write_dword(0x000214, 0x55)
await Timer(2000, 'ns')
# read status
val = await tb.rc.mem_read_dword(dev_pf0_bar0+0x100218)
val = await dev_pf0_bar0.read_dword(0x000218)
tb.log.info("Status: 0x%x", val)
assert val == 0x80000055
tb.log.info("%s", hexdump_str(mem_data, 0x1000, 64))
tb.log.info("%s", mem.hexdump_str(0x1000, 64))
assert mem_data[0:1024] == mem_data[0x1000:0x1000+1024]
assert mem[0:1024] == mem[0x1000:0x1000+1024]
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)