From 69253d2d83c1641aa5f8df30789026060d801a70 Mon Sep 17 00:00:00 2001 From: Alex Forencich Date: Thu, 1 Jun 2017 06:48:50 -0700 Subject: [PATCH] Update VCU108 example design --- example/VCU108/fpga_10g/fpga/Makefile | 4 +-- example/VCU108/fpga_10g/rtl/fpga.v | 26 ++++++++++++++---- example/VCU108/fpga_10g/rtl/fpga_core.v | 18 ++++++++++--- example/VCU108/fpga_10g/tb/test_fpga_core.py | 22 ++++++++++++--- example/VCU108/fpga_10g/tb/test_fpga_core.v | 3 +++ example/VCU108/fpga_1g/fpga/Makefile | 4 +-- example/VCU108/fpga_1g/rtl/fpga.v | 28 +++++++++++++++----- example/VCU108/fpga_1g/rtl/fpga_core.v | 14 +++++++++- example/VCU108/fpga_1g/tb/test_fpga_core.py | 22 ++++++++++++--- example/VCU108/fpga_1g/tb/test_fpga_core.v | 3 +++ 10 files changed, 119 insertions(+), 25 deletions(-) diff --git a/example/VCU108/fpga_10g/fpga/Makefile b/example/VCU108/fpga_10g/fpga/Makefile index 11c1ed737..cfb2bb486 100644 --- a/example/VCU108/fpga_10g/fpga/Makefile +++ b/example/VCU108/fpga_10g/fpga/Makefile @@ -14,8 +14,8 @@ SYN_FILES += rtl/i2c_master.v SYN_FILES += rtl/si570_i2c_init.v SYN_FILES += lib/eth/rtl/eth_mac_1g_fifo.v SYN_FILES += lib/eth/rtl/eth_mac_1g.v -SYN_FILES += lib/eth/rtl/eth_mac_1g_rx.v -SYN_FILES += lib/eth/rtl/eth_mac_1g_tx.v +SYN_FILES += lib/eth/rtl/axis_gmii_rx.v +SYN_FILES += lib/eth/rtl/axis_gmii_tx.v SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v SYN_FILES += lib/eth/rtl/eth_mac_10g.v SYN_FILES += lib/eth/rtl/eth_mac_10g_rx.v diff --git a/example/VCU108/fpga_10g/rtl/fpga.v b/example/VCU108/fpga_10g/rtl/fpga.v index 8537dd5e0..c8e71796b 100644 --- a/example/VCU108/fpga_10g/rtl/fpga.v +++ b/example/VCU108/fpga_10g/rtl/fpga.v @@ -481,6 +481,7 @@ ten_gig_eth_pcs_pma_inst ( // SGMII interface to PHY wire phy_gmii_clk_int; wire phy_gmii_rst_int; +wire phy_gmii_clk_en_int; wire [7:0] phy_gmii_txd_int; wire phy_gmii_tx_en_int; wire phy_gmii_tx_er_int; @@ -488,7 +489,21 @@ wire [7:0] phy_gmii_rxd_int; wire phy_gmii_rx_dv_int; wire phy_gmii_rx_er_int; -wire [15:0] gig_eth_status_vector; +wire [15:0] gig_eth_pcspma_status_vector; + +wire gig_eth_pcspma_status_link_status = gig_eth_pcspma_status_vector[0]; +wire gig_eth_pcspma_status_link_synchronization = gig_eth_pcspma_status_vector[1]; +wire gig_eth_pcspma_status_rudi_c = gig_eth_pcspma_status_vector[2]; +wire gig_eth_pcspma_status_rudi_i = gig_eth_pcspma_status_vector[3]; +wire gig_eth_pcspma_status_rudi_invalid = gig_eth_pcspma_status_vector[4]; +wire gig_eth_pcspma_status_rxdisperr = gig_eth_pcspma_status_vector[5]; +wire gig_eth_pcspma_status_rxnotintable = gig_eth_pcspma_status_vector[6]; +wire gig_eth_pcspma_status_phy_link_status = gig_eth_pcspma_status_vector[7]; +wire [1:0] gig_eth_pcspma_status_remote_fault_encdg = gig_eth_pcspma_status_vector[9:8]; +wire [1:0] gig_eth_pcspma_status_speed = gig_eth_pcspma_status_vector[11:10]; +wire gig_eth_pcspma_status_duplex = gig_eth_pcspma_status_vector[12]; +wire gig_eth_pcspma_status_remote_fault = gig_eth_pcspma_status_vector[13]; +wire [1:0] gig_eth_pcspma_status_pause = gig_eth_pcspma_status_vector[15:14]; wire [4:0] gig_eth_pcspma_config_vector; @@ -537,11 +552,11 @@ gig_eth_pcspma ( // MAC clocking .sgmii_clk_r (), .sgmii_clk_f (), - .sgmii_clk_en (), // need to pass through to MAC + .sgmii_clk_en (phy_gmii_clk_en_int), // Speed control - .speed_is_10_100 (1'b0), - .speed_is_100 (1'b0), + .speed_is_10_100 (gig_eth_pcspma_status_speed != 2'b10), + .speed_is_100 (gig_eth_pcspma_status_speed == 2'b01), // Internal GMII .gmii_txd (phy_gmii_txd_int), @@ -560,7 +575,7 @@ gig_eth_pcspma ( .an_restart_config (1'b0), // Status - .status_vector (gig_eth_status_vector), + .status_vector (gig_eth_pcspma_status_vector), .signal_detect (1'b1) ); @@ -610,6 +625,7 @@ core_inst ( */ .phy_gmii_clk(phy_gmii_clk_int), .phy_gmii_rst(phy_gmii_rst_int), + .phy_gmii_clk_en(phy_gmii_clk_en_int), .phy_gmii_rxd(phy_gmii_rxd_int), .phy_gmii_rx_dv(phy_gmii_rx_dv_int), .phy_gmii_rx_er(phy_gmii_rx_er_int), diff --git a/example/VCU108/fpga_10g/rtl/fpga_core.v b/example/VCU108/fpga_10g/rtl/fpga_core.v index ddbcb2029..91bdb3570 100644 --- a/example/VCU108/fpga_10g/rtl/fpga_core.v +++ b/example/VCU108/fpga_10g/rtl/fpga_core.v @@ -77,6 +77,7 @@ module fpga_core # */ input wire phy_gmii_clk, input wire phy_gmii_rst, + input wire phy_gmii_clk_en, input wire [7:0] phy_gmii_rxd, input wire phy_gmii_rx_dv, input wire phy_gmii_rx_er, @@ -433,7 +434,7 @@ eth_mac_1g_fifo #( .TX_FIFO_ADDR_WIDTH(12), .RX_FIFO_ADDR_WIDTH(12) ) -eth_mac_1g_fifo_inst ( +eth_mac_1g_inst ( .rx_clk(phy_gmii_clk), .rx_rst(phy_gmii_rst), .tx_clk(phy_gmii_clk), @@ -460,8 +461,19 @@ eth_mac_1g_fifo_inst ( .gmii_tx_en(phy_gmii_tx_en), .gmii_tx_er(phy_gmii_tx_er), - .rx_error_bad_frame(), - .rx_error_bad_fcs(), + .rx_clk_enable(phy_gmii_clk_en), + .tx_clk_enable(phy_gmii_clk_en), + .rx_mii_select(1'b0), + .tx_mii_select(1'b0), + + .tx_fifo_overflow(), + .tx_fifo_bad_frame(), + .tx_fifo_good_frame(), + .rx_error_bad_frame(rx_error_bad_frame), + .rx_error_bad_fcs(rx_error_bad_fcs), + .rx_fifo_overflow(), + .rx_fifo_bad_frame(), + .rx_fifo_good_frame(), .ifg_delay(12) ); diff --git a/example/VCU108/fpga_10g/tb/test_fpga_core.py b/example/VCU108/fpga_10g/tb/test_fpga_core.py index 5641d0935..6436e9da1 100755 --- a/example/VCU108/fpga_10g/tb/test_fpga_core.py +++ b/example/VCU108/fpga_10g/tb/test_fpga_core.py @@ -40,8 +40,8 @@ srcs = [] srcs.append("../rtl/%s.v" % module) srcs.append("../lib/eth/rtl/eth_mac_1g_fifo.v") srcs.append("../lib/eth/rtl/eth_mac_1g.v") -srcs.append("../lib/eth/rtl/eth_mac_1g_rx.v") -srcs.append("../lib/eth/rtl/eth_mac_1g_tx.v") +srcs.append("../lib/eth/rtl/axis_gmii_rx.v") +srcs.append("../lib/eth/rtl/axis_gmii_tx.v") srcs.append("../lib/eth/rtl/eth_mac_10g_fifo.v") srcs.append("../lib/eth/rtl/eth_mac_10g.v") srcs.append("../lib/eth/rtl/eth_mac_10g_rx.v") @@ -108,6 +108,7 @@ def bench(): qsfp_rxc_4 = Signal(intbv(0)[8:]) phy_gmii_clk = Signal(bool(0)) phy_gmii_rst = Signal(bool(0)) + phy_gmii_clk_en = Signal(bool(0)) phy_gmii_rxd = Signal(intbv(0)[8:]) phy_gmii_rx_dv = Signal(bool(0)) phy_gmii_rx_er = Signal(bool(0)) @@ -165,6 +166,7 @@ def bench(): txd=phy_gmii_rxd, tx_en=phy_gmii_rx_dv, tx_er=phy_gmii_rx_er, + clk_enable=phy_gmii_clk_en, name='gmii_source' ) @@ -176,6 +178,7 @@ def bench(): rxd=phy_gmii_txd, rx_dv=phy_gmii_tx_en, rx_er=phy_gmii_tx_er, + clk_enable=phy_gmii_clk_en, name='gmii_sink' ) @@ -216,6 +219,7 @@ def bench(): phy_gmii_clk=phy_gmii_clk, phy_gmii_rst=phy_gmii_rst, + phy_gmii_clk_en=phy_gmii_clk_en, phy_gmii_rxd=phy_gmii_rxd, phy_gmii_rx_dv=phy_gmii_rx_dv, phy_gmii_rx_er=phy_gmii_rx_er, @@ -236,6 +240,18 @@ def bench(): clk.next = not clk phy_gmii_clk.next = not phy_gmii_clk + clk_enable_rate = Signal(int(0)) + clk_enable_div = Signal(int(0)) + + @always(clk.posedge) + def clk_enable_gen(): + if clk_enable_div.next > 0: + phy_gmii_clk_en.next = 0 + clk_enable_div.next = clk_enable_div - 1 + else: + phy_gmii_clk_en.next = 1 + clk_enable_div.next = clk_enable_rate - 1 + @instance def check(): yield delay(100) @@ -497,7 +513,7 @@ def bench(): raise StopSimulation - return dut, qsfp_1_source_logic, qsfp_1_sink_logic, qsfp_2_source_logic, qsfp_2_sink_logic, qsfp_3_source_logic, qsfp_3_sink_logic, qsfp_4_source_logic, qsfp_4_sink_logic, gmii_source_logic, gmii_sink_logic, clkgen, check + return dut, qsfp_1_source_logic, qsfp_1_sink_logic, qsfp_2_source_logic, qsfp_2_sink_logic, qsfp_3_source_logic, qsfp_3_sink_logic, qsfp_4_source_logic, qsfp_4_sink_logic, gmii_source_logic, gmii_sink_logic, clkgen, clk_enable_gen, check def test_bench(): sim = Simulation(bench()) diff --git a/example/VCU108/fpga_10g/tb/test_fpga_core.v b/example/VCU108/fpga_10g/tb/test_fpga_core.v index 38c74c6b1..56ea34739 100644 --- a/example/VCU108/fpga_10g/tb/test_fpga_core.v +++ b/example/VCU108/fpga_10g/tb/test_fpga_core.v @@ -54,6 +54,7 @@ reg [63:0] qsfp_rxd_4 = 0; reg [7:0] qsfp_rxc_4 = 0; reg phy_gmii_clk = 0; reg phy_gmii_rst = 0; +reg phy_gmii_clk_en = 0; reg [7:0] phy_gmii_rxd = 0; reg phy_gmii_rx_dv = 0; reg phy_gmii_rx_er = 0; @@ -101,6 +102,7 @@ initial begin qsfp_rxc_4, phy_gmii_clk, phy_gmii_rst, + phy_gmii_clk_en, phy_gmii_rxd, phy_gmii_rx_dv, phy_gmii_rx_er, @@ -160,6 +162,7 @@ UUT ( .qsfp_rxc_4(qsfp_rxc_4), .phy_gmii_clk(phy_gmii_clk), .phy_gmii_rst(phy_gmii_rst), + .phy_gmii_clk_en(phy_gmii_clk_en), .phy_gmii_rxd(phy_gmii_rxd), .phy_gmii_rx_dv(phy_gmii_rx_dv), .phy_gmii_rx_er(phy_gmii_rx_er), diff --git a/example/VCU108/fpga_1g/fpga/Makefile b/example/VCU108/fpga_1g/fpga/Makefile index 6c581c779..06fa804e2 100644 --- a/example/VCU108/fpga_1g/fpga/Makefile +++ b/example/VCU108/fpga_1g/fpga/Makefile @@ -12,8 +12,8 @@ SYN_FILES += rtl/sync_reset.v SYN_FILES += rtl/sync_signal.v SYN_FILES += lib/eth/rtl/eth_mac_1g_fifo.v SYN_FILES += lib/eth/rtl/eth_mac_1g.v -SYN_FILES += lib/eth/rtl/eth_mac_1g_rx.v -SYN_FILES += lib/eth/rtl/eth_mac_1g_tx.v +SYN_FILES += lib/eth/rtl/axis_gmii_rx.v +SYN_FILES += lib/eth/rtl/axis_gmii_tx.v SYN_FILES += lib/eth/rtl/lfsr.v SYN_FILES += lib/eth/rtl/eth_axis_rx.v SYN_FILES += lib/eth/rtl/eth_axis_tx.v diff --git a/example/VCU108/fpga_1g/rtl/fpga.v b/example/VCU108/fpga_1g/rtl/fpga.v index 3d60177f7..cfa3add86 100644 --- a/example/VCU108/fpga_1g/rtl/fpga.v +++ b/example/VCU108/fpga_1g/rtl/fpga.v @@ -212,6 +212,7 @@ sync_signal_inst ( // SGMII interface to PHY wire phy_gmii_clk_int; wire phy_gmii_rst_int; +wire phy_gmii_clk_en_int; wire [7:0] phy_gmii_txd_int; wire phy_gmii_tx_en_int; wire phy_gmii_tx_er_int; @@ -219,7 +220,21 @@ wire [7:0] phy_gmii_rxd_int; wire phy_gmii_rx_dv_int; wire phy_gmii_rx_er_int; -wire [15:0] status_vector; +wire [15:0] pcspma_status_vector; + +wire pcspma_status_link_status = pcspma_status_vector[0]; +wire pcspma_status_link_synchronization = pcspma_status_vector[1]; +wire pcspma_status_rudi_c = pcspma_status_vector[2]; +wire pcspma_status_rudi_i = pcspma_status_vector[3]; +wire pcspma_status_rudi_invalid = pcspma_status_vector[4]; +wire pcspma_status_rxdisperr = pcspma_status_vector[5]; +wire pcspma_status_rxnotintable = pcspma_status_vector[6]; +wire pcspma_status_phy_link_status = pcspma_status_vector[7]; +wire [1:0] pcspma_status_remote_fault_encdg = pcspma_status_vector[9:8]; +wire [1:0] pcspma_status_speed = pcspma_status_vector[11:10]; +wire pcspma_status_duplex = pcspma_status_vector[12]; +wire pcspma_status_remote_fault = pcspma_status_vector[13]; +wire [1:0] pcspma_status_pause = pcspma_status_vector[15:14]; wire [4:0] pcspma_config_vector; @@ -268,11 +283,11 @@ eth_pcspma ( // MAC clocking .sgmii_clk_r (), .sgmii_clk_f (), - .sgmii_clk_en (), // need to pass through to MAC + .sgmii_clk_en (phy_gmii_clk_en_int), // Speed control - .speed_is_10_100 (1'b0), - .speed_is_100 (1'b0), + .speed_is_10_100 (pcspma_status_speed != 2'b10), + .speed_is_100 (pcspma_status_speed == 2'b01), // Internal GMII .gmii_txd (phy_gmii_txd_int), @@ -291,7 +306,7 @@ eth_pcspma ( .an_restart_config (1'b0), // Status - .status_vector (status_vector), + .status_vector (pcspma_status_vector), .signal_detect (1'b1) ); @@ -300,7 +315,7 @@ wire [7:0] led_int; // SGMII interface debug: // SW12:4 (sw[0]) off for payload byte, on for status vector // SW12:3 (sw[1]) off for LSB of status vector, on for MSB -assign led = sw[0] ? (sw[1] ? status_vector[15:8] : status_vector[7:0]) : led_int; +assign led = sw[0] ? (sw[1] ? pcspma_status_vector[15:8] : pcspma_status_vector[7:0]) : led_int; fpga_core core_inst ( @@ -325,6 +340,7 @@ core_inst ( */ .phy_gmii_clk(phy_gmii_clk_int), .phy_gmii_rst(phy_gmii_rst_int), + .phy_gmii_clk_en(phy_gmii_clk_en_int), .phy_gmii_rxd(phy_gmii_rxd_int), .phy_gmii_rx_dv(phy_gmii_rx_dv_int), .phy_gmii_rx_er(phy_gmii_rx_er_int), diff --git a/example/VCU108/fpga_1g/rtl/fpga_core.v b/example/VCU108/fpga_1g/rtl/fpga_core.v index b90780ef2..08e66a651 100644 --- a/example/VCU108/fpga_1g/rtl/fpga_core.v +++ b/example/VCU108/fpga_1g/rtl/fpga_core.v @@ -54,6 +54,7 @@ module fpga_core */ input wire phy_gmii_clk, input wire phy_gmii_rst, + input wire phy_gmii_clk_en, input wire [7:0] phy_gmii_rxd, input wire phy_gmii_rx_dv, input wire phy_gmii_rx_er, @@ -316,7 +317,7 @@ eth_mac_1g_fifo #( .TX_FIFO_ADDR_WIDTH(12), .RX_FIFO_ADDR_WIDTH(12) ) -eth_mac_1g_fifo_inst ( +eth_mac_inst ( .rx_clk(phy_gmii_clk), .rx_rst(phy_gmii_rst), .tx_clk(phy_gmii_clk), @@ -343,8 +344,19 @@ eth_mac_1g_fifo_inst ( .gmii_tx_en(phy_gmii_tx_en), .gmii_tx_er(phy_gmii_tx_er), + .rx_clk_enable(phy_gmii_clk_en), + .tx_clk_enable(phy_gmii_clk_en), + .rx_mii_select(1'b0), + .tx_mii_select(1'b0), + + .tx_fifo_overflow(), + .tx_fifo_bad_frame(), + .tx_fifo_good_frame(), .rx_error_bad_frame(rx_error_bad_frame), .rx_error_bad_fcs(rx_error_bad_fcs), + .rx_fifo_overflow(), + .rx_fifo_bad_frame(), + .rx_fifo_good_frame(), .ifg_delay(12) ); diff --git a/example/VCU108/fpga_1g/tb/test_fpga_core.py b/example/VCU108/fpga_1g/tb/test_fpga_core.py index a4d3147e4..6d3ee4927 100755 --- a/example/VCU108/fpga_1g/tb/test_fpga_core.py +++ b/example/VCU108/fpga_1g/tb/test_fpga_core.py @@ -39,8 +39,8 @@ srcs = [] srcs.append("../rtl/%s.v" % module) srcs.append("../lib/eth/rtl/eth_mac_1g_fifo.v") srcs.append("../lib/eth/rtl/eth_mac_1g.v") -srcs.append("../lib/eth/rtl/eth_mac_1g_rx.v") -srcs.append("../lib/eth/rtl/eth_mac_1g_tx.v") +srcs.append("../lib/eth/rtl/axis_gmii_rx.v") +srcs.append("../lib/eth/rtl/axis_gmii_tx.v") srcs.append("../lib/eth/rtl/lfsr.v") srcs.append("../lib/eth/rtl/eth_axis_rx.v") srcs.append("../lib/eth/rtl/eth_axis_tx.v") @@ -88,6 +88,7 @@ def bench(): sw = Signal(intbv(0)[4:]) phy_gmii_clk = Signal(bool(0)) phy_gmii_rst = Signal(bool(0)) + phy_gmii_clk_en = Signal(bool(0)) phy_gmii_rxd = Signal(intbv(0)[8:]) phy_gmii_rx_dv = Signal(bool(0)) phy_gmii_rx_er = Signal(bool(0)) @@ -113,6 +114,7 @@ def bench(): txd=phy_gmii_rxd, tx_en=phy_gmii_rx_dv, tx_er=phy_gmii_rx_er, + clk_enable=phy_gmii_clk_en, name='gmii_source' ) @@ -124,6 +126,7 @@ def bench(): rxd=phy_gmii_txd, rx_dv=phy_gmii_tx_en, rx_er=phy_gmii_tx_er, + clk_enable=phy_gmii_clk_en, name='gmii_sink' ) @@ -147,6 +150,7 @@ def bench(): phy_gmii_clk=phy_gmii_clk, phy_gmii_rst=phy_gmii_rst, + phy_gmii_clk_en=phy_gmii_clk_en, phy_gmii_rxd=phy_gmii_rxd, phy_gmii_rx_dv=phy_gmii_rx_dv, phy_gmii_rx_er=phy_gmii_rx_er, @@ -167,6 +171,18 @@ def bench(): clk.next = not clk phy_gmii_clk.next = not phy_gmii_clk + clk_enable_rate = Signal(int(0)) + clk_enable_div = Signal(int(0)) + + @always(clk.posedge) + def clk_enable_gen(): + if clk_enable_div.next > 0: + phy_gmii_clk_en.next = 0 + clk_enable_div.next = clk_enable_div - 1 + else: + phy_gmii_clk_en.next = 1 + clk_enable_div.next = clk_enable_rate - 1 + @instance def check(): yield delay(100) @@ -288,7 +304,7 @@ def bench(): raise StopSimulation - return dut, gmii_source_logic, gmii_sink_logic, clkgen, check + return dut, gmii_source_logic, gmii_sink_logic, clkgen, clk_enable_gen, check def test_bench(): sim = Simulation(bench()) diff --git a/example/VCU108/fpga_1g/tb/test_fpga_core.v b/example/VCU108/fpga_1g/tb/test_fpga_core.v index 6d61842df..c36f2a9d6 100644 --- a/example/VCU108/fpga_1g/tb/test_fpga_core.v +++ b/example/VCU108/fpga_1g/tb/test_fpga_core.v @@ -46,6 +46,7 @@ reg btnc = 0; reg [3:0] sw = 0; reg phy_gmii_clk = 0; reg phy_gmii_rst = 0; +reg phy_gmii_clk_en = 0; reg [7:0] phy_gmii_rxd = 0; reg phy_gmii_rx_dv = 0; reg phy_gmii_rx_er = 0; @@ -77,6 +78,7 @@ initial begin sw, phy_gmii_clk, phy_gmii_rst, + phy_gmii_clk_en, phy_gmii_rxd, phy_gmii_rx_dv, phy_gmii_rx_er, @@ -112,6 +114,7 @@ UUT ( .led(led), .phy_gmii_clk(phy_gmii_clk), .phy_gmii_rst(phy_gmii_rst), + .phy_gmii_clk_en(phy_gmii_clk_en), .phy_gmii_rxd(phy_gmii_rxd), .phy_gmii_rx_dv(phy_gmii_rx_dv), .phy_gmii_rx_er(phy_gmii_rx_er),