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Convert FIFOs to use DEPTH parameter instead of ADDR_WIDTH

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This commit is contained in:
Alex Forencich 2019-07-18 11:27:25 -07:00
parent e0a1a73ce0
commit 69de6fd2a4
34 changed files with 64 additions and 60 deletions
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4
rtl/axis_async_fifo.v
View File

@ -31,7 +31,7 @@ THE SOFTWARE.
*/
module axis_async_fifo #
(
parameter ADDR_WIDTH = 12,
parameter DEPTH = 4096,
parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
@ -91,6 +91,8 @@ module axis_async_fifo #
output wire m_status_good_frame
);
parameter ADDR_WIDTH = (KEEP_ENABLE && KEEP_WIDTH > 1) ? $clog2(DEPTH/KEEP_WIDTH) : $clog2(DEPTH);
// check configuration
initial begin
if (FRAME_FIFO && !LAST_ENABLE) begin

4
rtl/axis_async_fifo_adapter.v
View File

@ -31,7 +31,7 @@ THE SOFTWARE.
*/
module axis_async_fifo_adapter #
(
parameter ADDR_WIDTH = 12,
parameter DEPTH = 4096,
parameter S_DATA_WIDTH = 8,
parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8),
parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8),
@ -269,7 +269,7 @@ end
endgenerate
axis_async_fifo #(
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(EXPAND_BUS ? M_KEEP_ENABLE : S_KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),

4
rtl/axis_cobs_encode.v
View File

@ -101,7 +101,7 @@ wire code_fifo_out_tuser;
reg code_fifo_out_tready;
axis_fifo #(
.ADDR_WIDTH(8),
.DEPTH(256),
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.LAST_ENABLE(1),
@ -149,7 +149,7 @@ wire data_fifo_out_tlast;
reg data_fifo_out_tready;
axis_fifo #(
.ADDR_WIDTH(8),
.DEPTH(256),
.DATA_WIDTH(8),
.KEEP_ENABLE(0),
.LAST_ENABLE(1),

4
rtl/axis_fifo.v
View File

@ -31,7 +31,7 @@ THE SOFTWARE.
*/
module axis_fifo #
(
parameter ADDR_WIDTH = 12,
parameter DEPTH = 4096,
parameter DATA_WIDTH = 8,
parameter KEEP_ENABLE = (DATA_WIDTH>8),
parameter KEEP_WIDTH = (DATA_WIDTH/8),
@ -84,6 +84,8 @@ module axis_fifo #
output wire status_good_frame
);
parameter ADDR_WIDTH = (KEEP_ENABLE && KEEP_WIDTH > 1) ? $clog2(DEPTH/KEEP_WIDTH) : $clog2(DEPTH);
// check configuration
initial begin
if (FRAME_FIFO && !LAST_ENABLE) begin

4
rtl/axis_fifo_adapter.v
View File

@ -31,7 +31,7 @@ THE SOFTWARE.
*/
module axis_fifo_adapter #
(
parameter ADDR_WIDTH = 12,
parameter DEPTH = 4096,
parameter S_DATA_WIDTH = 8,
parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8),
parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8),
@ -264,7 +264,7 @@ end
endgenerate
axis_fifo #(
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(EXPAND_BUS ? M_KEEP_ENABLE : S_KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),

8
rtl/axis_frame_length_adjust_fifo.v
View File

@ -40,8 +40,8 @@ module axis_frame_length_adjust_fifo #
parameter DEST_WIDTH = 8,
parameter USER_ENABLE = 1,
parameter USER_WIDTH = 1,
parameter FRAME_FIFO_ADDR_WIDTH = 12,
parameter HEADER_FIFO_ADDR_WIDTH = 3
parameter FRAME_FIFO_DEPTH = 4096,
parameter HEADER_FIFO_DEPTH = 8
)
(
input wire clk,
@ -145,7 +145,7 @@ axis_frame_length_adjust_inst (
);
axis_fifo #(
.ADDR_WIDTH(FRAME_FIFO_ADDR_WIDTH),
.DEPTH(FRAME_FIFO_DEPTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
@ -186,7 +186,7 @@ frame_fifo_inst (
);
axis_fifo #(
.ADDR_WIDTH(HEADER_FIFO_ADDR_WIDTH),
.DEPTH(HEADER_FIFO_DEPTH),
.DATA_WIDTH(1+1+16+16),
.KEEP_ENABLE(0),
.LAST_ENABLE(0),

2
tb/test_axis_async_fifo.py
View File

@ -43,7 +43,7 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
ADDR_WIDTH = 2
DEPTH = 4
DATA_WIDTH = 8
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8)

4
tb/test_axis_async_fifo.v
View File

@ -32,7 +32,7 @@ THE SOFTWARE.
module test_axis_async_fifo;
// Parameters
parameter ADDR_WIDTH = 2;
parameter DEPTH = 4;
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
@ -107,7 +107,7 @@ initial begin
end
axis_async_fifo #(
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),

2
tb/test_axis_async_fifo_64.py
View File

@ -43,7 +43,7 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
ADDR_WIDTH = 2
DEPTH = 32
DATA_WIDTH = 64
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8)

4
tb/test_axis_async_fifo_64.v
View File

@ -32,7 +32,7 @@ THE SOFTWARE.
module test_axis_async_fifo_64;
// Parameters
parameter ADDR_WIDTH = 2;
parameter DEPTH = 32;
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
@ -107,7 +107,7 @@ initial begin
end
axis_async_fifo #(
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),

2
tb/test_axis_async_fifo_adapter_64_8.py
View File

@ -45,7 +45,7 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
ADDR_WIDTH = 2
DEPTH = 32
S_DATA_WIDTH = 64
S_KEEP_ENABLE = (S_DATA_WIDTH>8)
S_KEEP_WIDTH = (S_DATA_WIDTH/8)

4
tb/test_axis_async_fifo_adapter_64_8.v
View File

@ -32,7 +32,7 @@ THE SOFTWARE.
module test_axis_async_fifo_adapter_64_8;
// Parameters
parameter ADDR_WIDTH = 2;
parameter DEPTH = 32;
parameter S_DATA_WIDTH = 64;
parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8);
parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8);
@ -111,7 +111,7 @@ initial begin
end
axis_async_fifo_adapter #(
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH),
.S_DATA_WIDTH(S_DATA_WIDTH),
.S_KEEP_ENABLE(S_KEEP_ENABLE),
.S_KEEP_WIDTH(S_KEEP_WIDTH),

2
tb/test_axis_async_fifo_adapter_8_64.py
View File

@ -45,7 +45,7 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
ADDR_WIDTH = 2
DEPTH = 32
S_DATA_WIDTH = 8
S_KEEP_ENABLE = (S_DATA_WIDTH>8)
S_KEEP_WIDTH = (S_DATA_WIDTH/8)

4
tb/test_axis_async_fifo_adapter_8_64.v
View File

@ -32,7 +32,7 @@ THE SOFTWARE.
module test_axis_async_fifo_adapter_8_64;
// Parameters
parameter ADDR_WIDTH = 2;
parameter DEPTH = 32;
parameter S_DATA_WIDTH = 8;
parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8);
parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8);
@ -111,7 +111,7 @@ initial begin
end
axis_async_fifo_adapter #(
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH),
.S_DATA_WIDTH(S_DATA_WIDTH),
.S_KEEP_ENABLE(S_KEEP_ENABLE),
.S_KEEP_WIDTH(S_KEEP_WIDTH),

2
tb/test_axis_async_frame_fifo.py
View File

@ -43,7 +43,7 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
ADDR_WIDTH = 9
DEPTH = 512
DATA_WIDTH = 8
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8)

4
tb/test_axis_async_frame_fifo.v
View File

@ -32,7 +32,7 @@ THE SOFTWARE.
module test_axis_async_frame_fifo;
// Parameters
parameter ADDR_WIDTH = 9;
parameter DEPTH = 512;
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
@ -119,7 +119,7 @@ initial begin
end
axis_async_fifo #(
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),

2
tb/test_axis_async_frame_fifo_64.py
View File

@ -43,7 +43,7 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
ADDR_WIDTH = 6
DEPTH = 512
DATA_WIDTH = 64
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8)

4
tb/test_axis_async_frame_fifo_64.v
View File

@ -32,7 +32,7 @@ THE SOFTWARE.
module test_axis_async_frame_fifo_64;
// Parameters
parameter ADDR_WIDTH = 6;
parameter DEPTH = 512;
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
@ -119,7 +119,7 @@ initial begin
end
axis_async_fifo #(
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),

2
tb/test_axis_fifo.py
View File

@ -43,7 +43,7 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
ADDR_WIDTH = 2
DEPTH = 4
DATA_WIDTH = 8
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8)

4
tb/test_axis_fifo.v
View File

@ -32,7 +32,7 @@ THE SOFTWARE.
module test_axis_fifo;
// Parameters
parameter ADDR_WIDTH = 2;
parameter DEPTH = 4;
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
@ -105,7 +105,7 @@ initial begin
end
axis_fifo #(
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),

2
tb/test_axis_fifo_64.py
View File

@ -43,7 +43,7 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
ADDR_WIDTH = 2
DEPTH = 32
DATA_WIDTH = 64
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8)

4
tb/test_axis_fifo_64.v
View File

@ -32,7 +32,7 @@ THE SOFTWARE.
module test_axis_fifo_64;
// Parameters
parameter ADDR_WIDTH = 2;
parameter DEPTH = 32;
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
@ -105,7 +105,7 @@ initial begin
end
axis_fifo #(
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),

2
tb/test_axis_fifo_adapter_64_8.py
View File

@ -45,7 +45,7 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
ADDR_WIDTH = 2
DEPTH = 32
S_DATA_WIDTH = 64
S_KEEP_ENABLE = (S_DATA_WIDTH>8)
S_KEEP_WIDTH = (S_DATA_WIDTH/8)

4
tb/test_axis_fifo_adapter_64_8.v
View File

@ -32,7 +32,7 @@ THE SOFTWARE.
module test_axis_fifo_adapter_64_8;
// Parameters
parameter ADDR_WIDTH = 2;
parameter DEPTH = 32;
parameter S_DATA_WIDTH = 64;
parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8);
parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8);
@ -107,7 +107,7 @@ initial begin
end
axis_fifo_adapter #(
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH),
.S_DATA_WIDTH(S_DATA_WIDTH),
.S_KEEP_ENABLE(S_KEEP_ENABLE),
.S_KEEP_WIDTH(S_KEEP_WIDTH),

2
tb/test_axis_fifo_adapter_8_64.py
View File

@ -45,7 +45,7 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
ADDR_WIDTH = 2
DEPTH = 32
S_DATA_WIDTH = 8
S_KEEP_ENABLE = (S_DATA_WIDTH>8)
S_KEEP_WIDTH = (S_DATA_WIDTH/8)

4
tb/test_axis_fifo_adapter_8_64.v
View File

@ -32,7 +32,7 @@ THE SOFTWARE.
module test_axis_fifo_adapter_8_64;
// Parameters
parameter ADDR_WIDTH = 2;
parameter DEPTH = 32;
parameter S_DATA_WIDTH = 8;
parameter S_KEEP_ENABLE = (S_DATA_WIDTH>8);
parameter S_KEEP_WIDTH = (S_DATA_WIDTH/8);
@ -107,7 +107,7 @@ initial begin
end
axis_fifo_adapter #(
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH),
.S_DATA_WIDTH(S_DATA_WIDTH),
.S_KEEP_ENABLE(S_KEEP_ENABLE),
.S_KEEP_WIDTH(S_KEEP_WIDTH),

2
tb/test_axis_frame_fifo.py
View File

@ -43,7 +43,7 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
ADDR_WIDTH = 9
DEPTH = 512
DATA_WIDTH = 8
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8)

4
tb/test_axis_frame_fifo.v
View File

@ -32,7 +32,7 @@ THE SOFTWARE.
module test_axis_frame_fifo;
// Parameters
parameter ADDR_WIDTH = 9;
parameter DEPTH = 512;
parameter DATA_WIDTH = 8;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
@ -111,7 +111,7 @@ initial begin
end
axis_fifo #(
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),

2
tb/test_axis_frame_fifo_64.py
View File

@ -43,7 +43,7 @@ build_cmd = "iverilog -o %s.vvp %s" % (testbench, src)
def bench():
# Parameters
ADDR_WIDTH = 6
DEPTH = 512
DATA_WIDTH = 64
KEEP_ENABLE = (DATA_WIDTH>8)
KEEP_WIDTH = (DATA_WIDTH/8)

4
tb/test_axis_frame_fifo_64.v
View File

@ -32,7 +32,7 @@ THE SOFTWARE.
module test_axis_frame_fifo_64;
// Parameters
parameter ADDR_WIDTH = 6;
parameter DEPTH = 512;
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
@ -111,7 +111,7 @@ initial begin
end
axis_fifo #(
.ADDR_WIDTH(ADDR_WIDTH),
.DEPTH(DEPTH),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),

4
tb/test_axis_frame_length_adjust_fifo.py
View File

@ -54,8 +54,8 @@ def bench():
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
FRAME_FIFO_ADDR_WIDTH = 12
HEADER_FIFO_ADDR_WIDTH = 3
FRAME_FIFO_DEPTH = 4096
HEADER_FIFO_DEPTH = 8
# Inputs
clk = Signal(bool(0))

8
tb/test_axis_frame_length_adjust_fifo.v
View File

@ -41,8 +41,8 @@ parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter FRAME_FIFO_ADDR_WIDTH = 12;
parameter HEADER_FIFO_ADDR_WIDTH = 3;
parameter FRAME_FIFO_DEPTH = 4096;
parameter HEADER_FIFO_DEPTH = 8;
// Inputs
reg clk = 0;
@ -125,8 +125,8 @@ axis_frame_length_adjust_fifo #(
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.FRAME_FIFO_ADDR_WIDTH(FRAME_FIFO_ADDR_WIDTH),
.HEADER_FIFO_ADDR_WIDTH(HEADER_FIFO_ADDR_WIDTH)
.FRAME_FIFO_DEPTH(FRAME_FIFO_DEPTH),
.HEADER_FIFO_DEPTH(HEADER_FIFO_DEPTH)
)
UUT (
.clk(clk),

4
tb/test_axis_frame_length_adjust_fifo_64.py
View File

@ -54,8 +54,8 @@ def bench():
DEST_WIDTH = 8
USER_ENABLE = 1
USER_WIDTH = 1
FRAME_FIFO_ADDR_WIDTH = 9
HEADER_FIFO_ADDR_WIDTH = 3
FRAME_FIFO_DEPTH = 4096
HEADER_FIFO_DEPTH = 8
# Inputs
clk = Signal(bool(0))

8
tb/test_axis_frame_length_adjust_fifo_64.v
View File

@ -41,8 +41,8 @@ parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter FRAME_FIFO_ADDR_WIDTH = 9;
parameter HEADER_FIFO_ADDR_WIDTH = 3;
parameter FRAME_FIFO_DEPTH = 4096;
parameter HEADER_FIFO_DEPTH = 8;
// Inputs
reg clk = 0;
@ -125,8 +125,8 @@ axis_frame_length_adjust_fifo #(
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.FRAME_FIFO_ADDR_WIDTH(FRAME_FIFO_ADDR_WIDTH),
.HEADER_FIFO_ADDR_WIDTH(HEADER_FIFO_ADDR_WIDTH)
.FRAME_FIFO_DEPTH(FRAME_FIFO_DEPTH),
.HEADER_FIFO_DEPTH(HEADER_FIFO_DEPTH)
)
UUT (
.clk(clk),