FPGA/corundum
1
0
Fork 0
mirror of https://github.com/corundum/corundum.git synced 2025-01-16 08:12:53 +08:00
Code Issues Projects Releases Wiki Activity

merged changes in pcie

Browse Source
This commit is contained in:
Alex Forencich 2022-02-03 00:58:24 -08:00
commit 69ec8a9b52
10 changed files with 100 additions and 48 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
fpga/lib/pcie/example/common/rtl/example_core.v
View File

@ -292,7 +292,7 @@ always @* begin
dma_write_desc_ram_addr_next = dma_write_desc_ram_addr_reg;
dma_write_desc_len_next = dma_write_desc_len_reg;
dma_write_desc_tag_next = dma_write_desc_tag_reg;
dma_write_desc_valid_next = dma_write_desc_valid_reg && !m_axis_dma_read_desc_ready;
dma_write_desc_valid_next = dma_write_desc_valid_reg && !m_axis_dma_write_desc_ready;
dma_write_desc_status_tag_next = dma_write_desc_status_tag_reg;
dma_write_desc_status_error_next = dma_write_desc_status_error_reg;

10
fpga/lib/pcie/rtl/dma_if_axi.v
View File

@ -63,8 +63,10 @@ module dma_if_axi #
parameter READ_OP_TABLE_SIZE = 2**(AXI_ID_WIDTH),
// Operation table size (write)
parameter WRITE_OP_TABLE_SIZE = 2**(AXI_ID_WIDTH),
// Use AXI ID signals
parameter USE_AXI_ID = 1
// Use AXI ID signals (read)
parameter READ_USE_AXI_ID = 0,
// Use AXI ID signals (write)
parameter WRITE_USE_AXI_ID = 1
)
(
input wire clk,
@ -185,7 +187,7 @@ dma_if_axi_rd #(
.LEN_WIDTH(LEN_WIDTH),
.TAG_WIDTH(TAG_WIDTH),
.OP_TABLE_SIZE(READ_OP_TABLE_SIZE),
.USE_AXI_ID(USE_AXI_ID)
.USE_AXI_ID(READ_USE_AXI_ID)
)
dma_if_axi_rd_inst (
.clk(clk),
@ -261,7 +263,7 @@ dma_if_axi_wr #(
.LEN_WIDTH(LEN_WIDTH),
.TAG_WIDTH(TAG_WIDTH),
.OP_TABLE_SIZE(WRITE_OP_TABLE_SIZE),
.USE_AXI_ID(USE_AXI_ID)
.USE_AXI_ID(WRITE_USE_AXI_ID)
)
dma_if_axi_wr_inst (
.clk(clk),

38
fpga/lib/pcie/rtl/dma_if_axi_rd.v
View File

@ -62,7 +62,7 @@ module dma_if_axi_rd #
// Operation table size
parameter OP_TABLE_SIZE = 2**(AXI_ID_WIDTH),
// Use AXI ID signals
parameter USE_AXI_ID = 1
parameter USE_AXI_ID = 0
)
(
input wire clk,
@ -275,17 +275,17 @@ reg [3:0] m_axis_read_desc_status_error_reg = 4'd0, m_axis_read_desc_status_erro
reg m_axis_read_desc_status_valid_reg = 1'b0, m_axis_read_desc_status_valid_next;
// internal datapath
reg [RAM_SEG_COUNT*RAM_SEL_WIDTH-1:0] ram_wr_cmd_sel_int;
reg [RAM_SEG_COUNT*RAM_SEL_WIDTH-1:0] ram_wr_cmd_sel_int;
reg [RAM_SEG_COUNT*RAM_SEG_BE_WIDTH-1:0] ram_wr_cmd_be_int;
reg [RAM_SEG_COUNT*RAM_SEG_ADDR_WIDTH-1:0] ram_wr_cmd_addr_int;
reg [RAM_SEG_COUNT*RAM_SEG_DATA_WIDTH-1:0] ram_wr_cmd_data_int;
reg [RAM_SEG_COUNT-1:0] ram_wr_cmd_valid_int;
reg [RAM_SEG_COUNT-1:0] ram_wr_cmd_ready_int;
reg [RAM_SEG_COUNT-1:0] ram_wr_cmd_valid_int;
wire [RAM_SEG_COUNT-1:0] ram_wr_cmd_ready_int;
wire [RAM_SEG_COUNT-1:0] out_done;
reg [RAM_SEG_COUNT-1:0] out_done_ack;
assign m_axi_arid = m_axi_arid_reg;
assign m_axi_arid = USE_AXI_ID ? m_axi_arid_reg : {AXI_ID_WIDTH{1'b0}};
assign m_axi_araddr = m_axi_araddr_reg;
assign m_axi_arlen = m_axi_arlen_reg;
assign m_axi_arsize = AXI_BURST_SIZE;
@ -312,6 +312,8 @@ reg [CYCLE_COUNT_WIDTH-1:0] op_table_start_cycle_count;
reg [TAG_WIDTH-1:0] op_table_start_tag;
reg op_table_start_last;
reg op_table_start_en;
reg op_table_read_complete_en;
reg [OP_TAG_WIDTH+1-1:0] op_table_read_complete_ptr_reg = 0;
reg op_table_write_complete_en;
reg [OP_TAG_WIDTH-1:0] op_table_write_complete_ptr;
reg [OP_TAG_WIDTH+1-1:0] op_table_finish_ptr_reg = 0;
@ -486,6 +488,7 @@ always @* begin
offset_next = offset_reg;
op_tag_next = op_tag_reg;
op_table_read_complete_en = 1'b0;
op_table_write_complete_en = 1'b0;
op_table_write_complete_ptr = m_axi_rid;
@ -523,15 +526,19 @@ always @* begin
// idle state, wait for read data
m_axi_rready_next = &ram_wr_cmd_ready_int && !status_fifo_half_full_reg;
op_tag_next = m_axi_rid[OP_TAG_WIDTH-1:0];
if (USE_AXI_ID) begin
op_tag_next = m_axi_rid[OP_TAG_WIDTH-1:0];
end else begin
op_tag_next = op_table_read_complete_ptr_reg;
end
ram_sel_next = op_table_ram_sel[op_tag_next];
addr_next = op_table_ram_addr[op_tag_next];
op_count_next = op_table_len[op_tag_next];
offset_next = op_table_ram_addr[op_tag_next][RAM_OFFSET_WIDTH-1:0]-(op_table_axi_addr[op_tag_next] & OFFSET_MASK);
if (m_axi_rready && m_axi_rvalid) begin
if (op_count_next > AXI_WORD_WIDTH-(op_table_axi_addr[m_axi_rid[OP_TAG_WIDTH-1:0]] & OFFSET_MASK)) begin
cycle_byte_count_next = AXI_WORD_WIDTH-(op_table_axi_addr[m_axi_rid[OP_TAG_WIDTH-1:0]] & OFFSET_MASK);
if (op_count_next > AXI_WORD_WIDTH-(op_table_axi_addr[op_tag_next] & OFFSET_MASK)) begin
cycle_byte_count_next = AXI_WORD_WIDTH-(op_table_axi_addr[op_tag_next] & OFFSET_MASK);
end else begin
cycle_byte_count_next = op_count_next;
end
@ -559,6 +566,10 @@ always @* begin
status_fifo_finish_next = 1'b0;
status_fifo_we_next = 1'b1;
if (!USE_AXI_ID) begin
op_table_read_complete_en = 1'b1;
end
if (m_axi_rlast) begin
status_fifo_finish_next = 1'b1;
axi_state_next = AXI_STATE_IDLE;
@ -749,6 +760,10 @@ always @(posedge clk) begin
op_table_write_complete[op_table_start_ptr_reg[OP_TAG_WIDTH-1:0]] <= 1'b0;
end
if (!USE_AXI_ID && op_table_read_complete_en) begin
op_table_read_complete_ptr_reg <= op_table_read_complete_ptr_reg + 1;
end
if (op_table_write_complete_en) begin
op_table_write_complete[op_table_write_complete_ptr] <= 1'b1;
end
@ -775,6 +790,9 @@ always @(posedge clk) begin
status_fifo_we_reg <= 1'b0;
status_fifo_rd_valid_reg <= 1'b0;
op_table_start_ptr_reg <= 0;
op_table_read_complete_ptr_reg <= 0;
op_table_finish_ptr_reg <= 0;
op_table_active <= 0;
end
end
@ -786,11 +804,11 @@ genvar n;
for (n = 0; n < RAM_SEG_COUNT; n = n + 1) begin
reg [RAM_SEL_WIDTH-1:0] ram_wr_cmd_sel_reg = {RAM_SEL_WIDTH{1'b0}};
reg [RAM_SEL_WIDTH-1:0] ram_wr_cmd_sel_reg = {RAM_SEL_WIDTH{1'b0}};
reg [RAM_SEG_BE_WIDTH-1:0] ram_wr_cmd_be_reg = {RAM_SEG_BE_WIDTH{1'b0}};
reg [RAM_SEG_ADDR_WIDTH-1:0] ram_wr_cmd_addr_reg = {RAM_SEG_ADDR_WIDTH{1'b0}};
reg [RAM_SEG_DATA_WIDTH-1:0] ram_wr_cmd_data_reg = {RAM_SEG_DATA_WIDTH{1'b0}};
reg ram_wr_cmd_valid_reg = 1'b0;
reg ram_wr_cmd_valid_reg = 1'b0;
reg [OUTPUT_FIFO_ADDR_WIDTH-1:0] out_fifo_wr_ptr_reg = 0;
reg [OUTPUT_FIFO_ADDR_WIDTH-1:0] out_fifo_rd_ptr_reg = 0;

58
fpga/lib/pcie/rtl/dma_if_axi_wr.v
View File

@ -304,7 +304,7 @@ reg m_axi_wlast_int;
reg m_axi_wvalid_int;
wire m_axi_wready_int;
assign m_axi_awid = m_axi_awid_reg;
assign m_axi_awid = USE_AXI_ID ? m_axi_awid_reg : {AXI_ID_WIDTH{1'b0}};
assign m_axi_awaddr = m_axi_awaddr_reg;
assign m_axi_awlen = m_axi_awlen_reg;
assign m_axi_awsize = AXI_BURST_SIZE;
@ -770,27 +770,47 @@ always @* begin
mask_fifo_rd_ptr_next = mask_fifo_rd_ptr_reg+1;
end
// accept write completions
m_axi_bready_next = 1'b1;
if (m_axi_bready && m_axi_bvalid) begin
op_table_write_complete_en = 1'b1;
op_table_write_complete_ptr = m_axi_bid;
end
if (USE_AXI_ID) begin
// accept write completions
m_axi_bready_next = 1'b1;
if (m_axi_bready && m_axi_bvalid) begin
op_table_write_complete_en = 1'b1;
op_table_write_complete_ptr = m_axi_bid;
end
// commit operations in-order
op_table_finish_en = 1'b0;
// commit operations in-order
op_table_finish_en = 1'b0;
m_axis_write_desc_status_tag_next = op_table_tag[op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]];
m_axis_write_desc_status_error_next = 0;
m_axis_write_desc_status_valid_next = 1'b0;
m_axis_write_desc_status_tag_next = op_table_tag[op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]];
m_axis_write_desc_status_error_next = 0;
m_axis_write_desc_status_valid_next = 1'b0;
if (op_table_active[op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]] && op_table_write_complete[op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]] && op_table_finish_ptr_reg != op_table_tx_finish_ptr_reg) begin
op_table_finish_en = 1'b1;
if (op_table_active[op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]] && op_table_write_complete[op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]] && op_table_finish_ptr_reg != op_table_tx_finish_ptr_reg) begin
op_table_finish_en = 1'b1;
if (op_table_last[op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]]) begin
m_axis_write_desc_status_tag_next = op_table_tag[op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]];
m_axis_write_desc_status_error_next = 0;
m_axis_write_desc_status_valid_next = 1'b1;
if (op_table_last[op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]]) begin
m_axis_write_desc_status_tag_next = op_table_tag[op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]];
m_axis_write_desc_status_error_next = 0;
m_axis_write_desc_status_valid_next = 1'b1;
end
end
end else begin
// accept write completions
op_table_finish_en = 1'b0;
m_axis_write_desc_status_tag_next = op_table_tag[op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]];
m_axis_write_desc_status_error_next = 0;
m_axis_write_desc_status_valid_next = 1'b0;
m_axi_bready_next = 1'b1;
if (m_axi_bready && m_axi_bvalid) begin
op_table_finish_en = 1'b1;
if (op_table_last[op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]]) begin
m_axis_write_desc_status_tag_next = op_table_tag[op_table_finish_ptr_reg[OP_TAG_WIDTH-1:0]];
m_axis_write_desc_status_error_next = 0;
m_axis_write_desc_status_valid_next = 1'b1;
end
end
end
end
@ -882,7 +902,7 @@ always @(posedge clk) begin
op_table_tx_finish_ptr_reg <= op_table_tx_finish_ptr_reg + 1;
end
if (op_table_write_complete_en) begin
if (USE_AXI_ID && op_table_write_complete_en) begin
op_table_write_complete[op_table_write_complete_ptr] <= 1'b1;
end

9
fpga/lib/pcie/tb/dma_if_axi/Makefile
View File

@ -48,7 +48,8 @@ export PARAM_LEN_WIDTH ?= 16
export PARAM_TAG_WIDTH ?= 8
export PARAM_READ_OP_TABLE_SIZE ?= $(shell python -c "print(2**$(PARAM_AXI_ID_WIDTH))")
export PARAM_WRITE_OP_TABLE_SIZE ?= $(shell python -c "print(2**$(PARAM_AXI_ID_WIDTH))")
export PARAM_USE_AXI_ID ?= 1
export PARAM_READ_USE_AXI_ID ?= 0
export PARAM_WRITE_USE_AXI_ID ?= 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst
@ -67,7 +68,8 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).TAG_WIDTH=$(PARAM_TAG_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).READ_OP_TABLE_SIZE=$(PARAM_READ_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).WRITE_OP_TABLE_SIZE=$(PARAM_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).USE_AXI_ID=$(PARAM_USE_AXI_ID)
COMPILE_ARGS += -P $(TOPLEVEL).READ_USE_AXI_ID=$(PARAM_READ_USE_AXI_ID)
COMPILE_ARGS += -P $(TOPLEVEL).WRITE_USE_AXI_ID=$(PARAM_WRITE_USE_AXI_ID)
ifeq ($(WAVES), 1)
VERILOG_SOURCES += iverilog_dump.v
@ -90,7 +92,8 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GTAG_WIDTH=$(PARAM_TAG_WIDTH)
COMPILE_ARGS += -GREAD_OP_TABLE_SIZE=$(PARAM_READ_OP_TABLE_SIZE)
COMPILE_ARGS += -GWRITE_OP_TABLE_SIZE=$(PARAM_WRITE_OP_TABLE_SIZE)
COMPILE_ARGS += -GUSE_AXI_ID=$(PARAM_USE_AXI_ID)
COMPILE_ARGS += -GREAD_USE_AXI_ID=$(PARAM_READ_USE_AXI_ID)
COMPILE_ARGS += -GWRITE_USE_AXI_ID=$(PARAM_WRITE_USE_AXI_ID)
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst

3
fpga/lib/pcie/tb/dma_if_axi/test_dma_if_axi.py
View File

@ -267,7 +267,8 @@ def test_dma_if_axi(request, axi_data_width):
parameters['TAG_WIDTH'] = 8
parameters['READ_OP_TABLE_SIZE'] = 2**parameters['AXI_ID_WIDTH']
parameters['WRITE_OP_TABLE_SIZE'] = 2**parameters['AXI_ID_WIDTH']
parameters['USE_AXI_ID'] = 1
parameters['READ_USE_AXI_ID'] = 0
parameters['WRITE_USE_AXI_ID'] = 1
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}

3
fpga/lib/pcie/tb/dma_if_axi_rd/Makefile
View File

@ -45,6 +45,7 @@ export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_SEG_ADDR_WID
export PARAM_LEN_WIDTH ?= 16
export PARAM_TAG_WIDTH ?= 8
export PARAM_OP_TABLE_SIZE ?= $(shell python -c "print(2**$(PARAM_AXI_ID_WIDTH))")
export PARAM_USE_AXI_ID ?= 0
ifeq ($(SIM), icarus)
PLUSARGS += -fst
@ -62,6 +63,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).LEN_WIDTH=$(PARAM_LEN_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TAG_WIDTH=$(PARAM_TAG_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).OP_TABLE_SIZE=$(PARAM_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).USE_AXI_ID=$(PARAM_USE_AXI_ID)
ifeq ($(WAVES), 1)
VERILOG_SOURCES += iverilog_dump.v
@ -83,6 +85,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GLEN_WIDTH=$(PARAM_LEN_WIDTH)
COMPILE_ARGS += -GTAG_WIDTH=$(PARAM_TAG_WIDTH)
COMPILE_ARGS += -GOP_TABLE_SIZE=$(PARAM_OP_TABLE_SIZE)
COMPILE_ARGS += -GUSE_AXI_ID=$(PARAM_USE_AXI_ID)
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst

2
fpga/lib/pcie/tb/dma_if_axi_rd/test_dma_if_axi_rd.py
View File

@ -202,7 +202,7 @@ def test_dma_if_axi_rd(request, axi_data_width):
parameters['LEN_WIDTH'] = 16
parameters['TAG_WIDTH'] = 8
parameters['OP_TABLE_SIZE'] = 2**parameters['AXI_ID_WIDTH']
parameters['USE_AXI_ID'] = 1
parameters['USE_AXI_ID'] = 0
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}

3
fpga/lib/pcie/tb/dma_if_axi_wr/Makefile
View File

@ -45,6 +45,7 @@ export PARAM_RAM_ADDR_WIDTH ?= $(shell python -c "print($(PARAM_RAM_SEG_ADDR_WID
export PARAM_LEN_WIDTH ?= 16
export PARAM_TAG_WIDTH ?= 8
export PARAM_OP_TABLE_SIZE ?= $(shell python -c "print(2**$(PARAM_AXI_ID_WIDTH))")
export PARAM_USE_AXI_ID ?= 1
ifeq ($(SIM), icarus)
PLUSARGS += -fst
@ -62,6 +63,7 @@ ifeq ($(SIM), icarus)
COMPILE_ARGS += -P $(TOPLEVEL).LEN_WIDTH=$(PARAM_LEN_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).TAG_WIDTH=$(PARAM_TAG_WIDTH)
COMPILE_ARGS += -P $(TOPLEVEL).OP_TABLE_SIZE=$(PARAM_OP_TABLE_SIZE)
COMPILE_ARGS += -P $(TOPLEVEL).USE_AXI_ID=$(PARAM_USE_AXI_ID)
ifeq ($(WAVES), 1)
VERILOG_SOURCES += iverilog_dump.v
@ -83,6 +85,7 @@ else ifeq ($(SIM), verilator)
COMPILE_ARGS += -GLEN_WIDTH=$(PARAM_LEN_WIDTH)
COMPILE_ARGS += -GTAG_WIDTH=$(PARAM_TAG_WIDTH)
COMPILE_ARGS += -GOP_TABLE_SIZE=$(PARAM_OP_TABLE_SIZE)
COMPILE_ARGS += -GUSE_AXI_ID=$(PARAM_USE_AXI_ID)
ifeq ($(WAVES), 1)
COMPILE_ARGS += --trace-fst

20
fpga/lib/pcie/tox.ini
View File

@ -1,21 +1,23 @@
# tox configuration
[tox]
envlist = py39
envlist = py3
skipsdist = True
minversion = 3.2.0
requires = virtualenv >= 16.1
[gh-actions]
python =
3.9: py39
3.9: py3
[testenv]
deps =
pytest
pytest-xdist
pytest-split
cocotb
cocotb-test
cocotbext-axi
cocotbext-pcie
pytest == 6.2.5
pytest-xdist == 2.4.0
pytest-split == 0.4.0
cocotb == 1.6.1
cocotb-test == 0.2.1
cocotbext-axi == 0.1.16
cocotbext-pcie == 0.1.20
commands =
pytest -n auto {posargs}