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Add CONVERT_NARROW_BURST and FORWARD_ID parameters to AXI adapter

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This commit is contained in:
Alex Forencich 2018-08-20 23:23:00 -07:00
parent b15e8d9f63
commit 6a002e2ce0
9 changed files with 59 additions and 18 deletions
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12
rtl/axi_adapter.v
View File

@ -47,7 +47,9 @@ module axi_adapter #
parameter ARUSER_WIDTH = 1,
parameter RUSER_ENABLE = 0,
parameter RUSER_WIDTH = 1,
parameter CONVERT_BURST = 1
parameter CONVERT_BURST = 1,
parameter CONVERT_NARROW_BURST = 0,
parameter FORWARD_ID = 0
)
(
input wire clk,
@ -163,7 +165,9 @@ axi_adapter_wr #(
.WUSER_WIDTH(WUSER_WIDTH),
.BUSER_ENABLE(BUSER_ENABLE),
.BUSER_WIDTH(BUSER_WIDTH),
.CONVERT_BURST(CONVERT_BURST)
.CONVERT_BURST(CONVERT_BURST),
.CONVERT_NARROW_BURST(CONVERT_NARROW_BURST),
.FORWARD_ID(FORWARD_ID)
)
axi_adapter_wr_inst (
.clk(clk),
@ -237,7 +241,9 @@ axi_adapter_rd #(
.ARUSER_WIDTH(ARUSER_WIDTH),
.RUSER_ENABLE(RUSER_ENABLE),
.RUSER_WIDTH(RUSER_WIDTH),
.CONVERT_BURST(CONVERT_BURST)
.CONVERT_BURST(CONVERT_BURST),
.CONVERT_NARROW_BURST(CONVERT_NARROW_BURST),
.FORWARD_ID(FORWARD_ID)
)
axi_adapter_rd_inst (
.clk(clk),

14
rtl/axi_adapter_rd.v
View File

@ -41,7 +41,9 @@ module axi_adapter_rd #
parameter ARUSER_WIDTH = 1,
parameter RUSER_ENABLE = 0,
parameter RUSER_WIDTH = 1,
parameter CONVERT_BURST = 1
parameter CONVERT_BURST = 1,
parameter CONVERT_NARROW_BURST = 0,
parameter FORWARD_ID = 0
)
(
input wire clk,
@ -194,7 +196,7 @@ wire s_axi_rready_int_early;
assign s_axi_arready = s_axi_arready_reg;
assign m_axi_arid = m_axi_arid_reg;
assign m_axi_arid = FORWARD_ID ? m_axi_arid_reg : {ID_WIDTH{1'b0}};
assign m_axi_araddr = m_axi_araddr_reg;
assign m_axi_arlen = m_axi_arlen_reg;
assign m_axi_arsize = m_axi_arsize_reg;
@ -318,11 +320,15 @@ always @* begin
addr_next = s_axi_araddr;
burst_next = s_axi_arlen;
burst_size_next = s_axi_arsize;
if (CONVERT_BURST && s_axi_arcache[1]) begin
if (CONVERT_BURST && s_axi_arcache[1] && (CONVERT_NARROW_BURST || s_axi_arsize == $clog2(S_WORD_WIDTH))) begin
// split reads
// require CONVERT_BURST and arcache[1] set
master_burst_size_next = $clog2(M_WORD_WIDTH);
m_axi_arlen_next = (({{S_ADDR_BIT_OFFSET+1{1'b0}}, s_axi_arlen} << s_axi_arsize) + s_axi_araddr[M_ADDR_BIT_OFFSET-1:0]) >> $clog2(M_WORD_WIDTH);
if (CONVERT_NARROW_BURST) begin
m_axi_arlen_next = (({{S_ADDR_BIT_OFFSET+1{1'b0}}, s_axi_arlen} << s_axi_arsize) + s_axi_araddr[M_ADDR_BIT_OFFSET-1:0]) >> $clog2(M_WORD_WIDTH);
end else begin
m_axi_arlen_next = ({1'b0, s_axi_arlen} + s_axi_araddr[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET]) >> $clog2(CYCLE_COUNT);
end
m_axi_arsize_next = $clog2(M_WORD_WIDTH);
state_next = STATE_DATA_READ;
end else begin

27
rtl/axi_adapter_wr.v
View File

@ -43,7 +43,9 @@ module axi_adapter_wr #
parameter WUSER_WIDTH = 1,
parameter BUSER_ENABLE = 0,
parameter BUSER_WIDTH = 1,
parameter CONVERT_BURST = 1
parameter CONVERT_BURST = 1,
parameter CONVERT_NARROW_BURST = 0,
parameter FORWARD_ID = 0
)
(
input wire clk,
@ -214,7 +216,7 @@ assign s_axi_bresp = s_axi_bresp_reg;
assign s_axi_buser = BUSER_ENABLE ? s_axi_buser_reg : {BUSER_WIDTH{1'b0}};
assign s_axi_bvalid = s_axi_bvalid_reg;
assign m_axi_awid = m_axi_awid_reg;
assign m_axi_awid = FORWARD_ID ? m_axi_awid_reg : {ID_WIDTH{1'b0}};
assign m_axi_awaddr = m_axi_awaddr_reg;
assign m_axi_awlen = m_axi_awlen_reg;
assign m_axi_awsize = m_axi_awsize_reg;
@ -362,11 +364,15 @@ always @* begin
addr_next = s_axi_awaddr;
burst_next = s_axi_awlen;
burst_size_next = s_axi_awsize;
if (CONVERT_BURST && s_axi_awcache[1]) begin
if (CONVERT_BURST && s_axi_awcache[1] && (CONVERT_NARROW_BURST || s_axi_awsize == $clog2(S_WORD_WIDTH))) begin
// merge writes
// require CONVERT_BURST and awcache[1] set
master_burst_size_next = $clog2(M_WORD_WIDTH);
m_axi_awlen_next = (({{S_ADDR_BIT_OFFSET+1{1'b0}}, s_axi_awlen} << s_axi_awsize) + s_axi_awaddr[M_ADDR_BIT_OFFSET-1:0]) >> $clog2(M_WORD_WIDTH);
if (CONVERT_NARROW_BURST) begin
m_axi_awlen_next = (({{S_ADDR_BIT_OFFSET+1{1'b0}}, s_axi_awlen} << s_axi_awsize) + s_axi_awaddr[M_ADDR_BIT_OFFSET-1:0]) >> $clog2(M_WORD_WIDTH);
end else begin
m_axi_awlen_next = ({1'b0, s_axi_awlen} + s_axi_awaddr[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET]) >> $clog2(CYCLE_COUNT);
end
m_axi_awsize_next = $clog2(M_WORD_WIDTH);
state_next = STATE_DATA_2;
end else begin
@ -415,11 +421,16 @@ always @* begin
s_axi_wready_next = m_axi_wready_int_early;
if (s_axi_wready && s_axi_wvalid) begin
for (i = 0; i < S_WORD_WIDTH; i = i + 1) begin
if (s_axi_wstrb[i]) begin
data_next[addr_reg[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET]*CYCLE_DATA_WIDTH+i*M_WORD_SIZE +: M_WORD_SIZE] = s_axi_wdata[i*M_WORD_SIZE +: M_WORD_SIZE];
strb_next[addr_reg[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET]*CYCLE_STRB_WIDTH+i] = 1'b1;
if (CONVERT_NARROW_BURST) begin
for (i = 0; i < S_WORD_WIDTH; i = i + 1) begin
if (s_axi_wstrb[i]) begin
data_next[addr_reg[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET]*CYCLE_DATA_WIDTH+i*M_WORD_SIZE +: M_WORD_SIZE] = s_axi_wdata[i*M_WORD_SIZE +: M_WORD_SIZE];
strb_next[addr_reg[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET]*CYCLE_STRB_WIDTH+i] = 1'b1;
end
end
end else begin
data_next[addr_reg[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET]*CYCLE_DATA_WIDTH +: CYCLE_DATA_WIDTH] = s_axi_wdata;
strb_next[addr_reg[M_ADDR_BIT_OFFSET-1:S_ADDR_BIT_OFFSET]*CYCLE_STRB_WIDTH +: CYCLE_STRB_WIDTH] = s_axi_wstrb;
end
m_axi_wdata_int = data_next;
m_axi_wstrb_int = strb_next;

2
tb/test_axi_adapter_16_32.py
View File

@ -62,6 +62,8 @@ def bench():
RUSER_ENABLE = 0
RUSER_WIDTH = 1
CONVERT_BURST = 1
CONVERT_NARROW_BURST = 1
FORWARD_ID = 1
# Inputs
clk = Signal(bool(0))

6
tb/test_axi_adapter_16_32.v
View File

@ -49,6 +49,8 @@ parameter ARUSER_WIDTH = 1;
parameter RUSER_ENABLE = 0;
parameter RUSER_WIDTH = 1;
parameter CONVERT_BURST = 1;
parameter CONVERT_NARROW_BURST = 1;
parameter FORWARD_ID = 1;
// Inputs
reg clk = 0;
@ -266,7 +268,9 @@ axi_adapter #(
.ARUSER_WIDTH(ARUSER_WIDTH),
.RUSER_ENABLE(RUSER_ENABLE),
.RUSER_WIDTH(RUSER_WIDTH),
.CONVERT_BURST(CONVERT_BURST)
.CONVERT_BURST(CONVERT_BURST),
.CONVERT_NARROW_BURST(CONVERT_NARROW_BURST),
.FORWARD_ID(FORWARD_ID)
)
UUT (
.clk(clk),

2
tb/test_axi_adapter_32_16.py
View File

@ -62,6 +62,8 @@ def bench():
RUSER_ENABLE = 0
RUSER_WIDTH = 1
CONVERT_BURST = 1
CONVERT_NARROW_BURST = 1
FORWARD_ID = 1
# Inputs
clk = Signal(bool(0))

6
tb/test_axi_adapter_32_16.v
View File

@ -49,6 +49,8 @@ parameter ARUSER_WIDTH = 1;
parameter RUSER_ENABLE = 0;
parameter RUSER_WIDTH = 1;
parameter CONVERT_BURST = 1;
parameter CONVERT_NARROW_BURST = 1;
parameter FORWARD_ID = 1;
// Inputs
reg clk = 0;
@ -266,7 +268,9 @@ axi_adapter #(
.ARUSER_WIDTH(ARUSER_WIDTH),
.RUSER_ENABLE(RUSER_ENABLE),
.RUSER_WIDTH(RUSER_WIDTH),
.CONVERT_BURST(CONVERT_BURST)
.CONVERT_BURST(CONVERT_BURST),
.CONVERT_NARROW_BURST(CONVERT_NARROW_BURST),
.FORWARD_ID(FORWARD_ID)
)
UUT (
.clk(clk),

2
tb/test_axi_adapter_32_32.py
View File

@ -62,6 +62,8 @@ def bench():
RUSER_ENABLE = 0
RUSER_WIDTH = 1
CONVERT_BURST = 1
CONVERT_NARROW_BURST = 1
FORWARD_ID = 1
# Inputs
clk = Signal(bool(0))

6
tb/test_axi_adapter_32_32.v
View File

@ -49,6 +49,8 @@ parameter ARUSER_WIDTH = 1;
parameter RUSER_ENABLE = 0;
parameter RUSER_WIDTH = 1;
parameter CONVERT_BURST = 1;
parameter CONVERT_NARROW_BURST = 1;
parameter FORWARD_ID = 1;
// Inputs
reg clk = 0;
@ -266,7 +268,9 @@ axi_adapter #(
.ARUSER_WIDTH(ARUSER_WIDTH),
.RUSER_ENABLE(RUSER_ENABLE),
.RUSER_WIDTH(RUSER_WIDTH),
.CONVERT_BURST(CONVERT_BURST)
.CONVERT_BURST(CONVERT_BURST),
.CONVERT_NARROW_BURST(CONVERT_NARROW_BURST),
.FORWARD_ID(FORWARD_ID)
)
UUT (
.clk(clk),