diff --git a/docs/source/devicelist.rst b/docs/source/devicelist.rst
index 74ac52f65..f987cbabc 100644
--- a/docs/source/devicelist.rst
+++ b/docs/source/devicelist.rst
@@ -108,61 +108,63 @@ This section details PCIe form-factor targets, which interface with a separate h
.. table:: Summary of the board-specific design variants and some important configuration parameters.
- ======================= =========================== ==== ======= ==== =====
- Board Design IFxP RXQ/TXQ MAC Sched
- ======================= =========================== ==== ======= ==== =====
- ADM-PCIE-9V3 mqnic/fpga_25g/fpga 2x1 256/8K 25G RR
- ADM-PCIE-9V3 mqnic/fpga_25g/fpga_10g 2x1 256/8K 10G RR
- ADM-PCIE-9V3 mqnic/fpga_25g/fpga_tdma 2x1 256/256 25G TDMA
- ADM-PCIE-9V3 mqnic/fpga_100g/fpga 2x1 256/8K 100G RR
- ADM-PCIE-9V3 mqnic/fpga_100g/fpga_tdma 2x1 256/256 100G TDMA
- DNPCIe_40G_KU_LL_2QSFP mqnic/fpga/fpga_ku040 2x1 256/2K 10G RR
- DNPCIe_40G_KU_LL_2QSFP mqnic/fpga/fpga_ku060 2x1 256/2K 10G RR
- Nexus K35-S mqnic/fpga/fpga 2x1 256/2K 10G RR
- Nexus K3P-S mqnic/fpga_25g/fpga 2x1 256/8K 25G RR
- Nexus K3P-S mqnic/fpga_25g/fpga_10g 2x1 256/8K 10G RR
- Nexus K3P-Q mqnic/fpga_25g/fpga 2x1 256/8K 25G RR
- Nexus K3P-Q mqnic/fpga_25g/fpga_10g 2x1 256/8K 10G RR
- fb2CG\@KU15P mqnic/fpga_25g/fpga 2x1 256/8K 25G RR
- fb2CG\@KU15P mqnic/fpga_25g/fpga_10g 2x1 256/8K 10G RR
- fb2CG\@KU15P mqnic/fpga_25g/fpga_tdma 2x1 256/256 25G TDMA
- fb2CG\@KU15P mqnic/fpga_100g/fpga 2x1 256/8K 100G RR
- fb2CG\@KU15P mqnic/fpga_100g/fpga_tdma 2x1 256/256 100G TDMA
- NetFPGA SUME mqnic/fpga/fpga 1x1 256/512 10G RR
- 250-SoC mqnic/fpga_25g/fpga 2x1 256/8K 25G RR
- 250-SoC mqnic/fpga_25g/fpga_10g 2x1 256/8K 10G RR
- 250-SoC mqnic/fpga_100g/fpga 2x1 256/8K 100G RR
- XUP-P3R mqnic/fpga_25g/fpga 4x1 256/8K 25G RR
- XUP-P3R mqnic/fpga_25g/fpga_10g 4x1 256/8K 10G RR
- XUP-P3R mqnic/fpga_100g/fpga 4x1 256/8K 100G RR
- DK-DEV-1SMX-H-A mqnic/fpga_10g/fpga_1sm21b 2x1 256/1K 10G RR
- DK-DEV-1SMC-H-A mqnic/fpga_10g/fpga_1sm21c 2x1 256/1K 10G RR
- DK-DEV-1SDX-P-A mqnic/fpga_25g/fpga 2x1 256/1K 25G RR
- DK-DEV-1SDX-P-A mqnic/fpga_25g/fpga_10g 2x1 256/1K 10G RR
- DE10-Agilex mqnic/fpga_25g/fpga 2x1 256/1K 25G RR
- DE10-Agilex mqnic/fpga_25g/fpga_10g 2x1 256/1K 10G RR
- DE10-Agilex mqnic/fpga_100g/fpga 2x1 256/1K 100G RR
- Alveo U50 mqnic/fpga_25g/fpga 1x1 256/8K 25G RR
- Alveo U50 mqnic/fpga_25g/fpga_10g 1x1 256/8K 10G RR
- Alveo U50 mqnic/fpga_100g/fpga 1x1 256/8K 100G RR
- Alveo U200 mqnic/fpga_25g/fpga 2x1 256/8K 25G RR
- Alveo U200 mqnic/fpga_25g/fpga_10g 2x1 256/8K 10G RR
- Alveo U200 mqnic/fpga_100g/fpga 2x1 256/8K 100G RR
- Alveo U250 mqnic/fpga_25g/fpga 2x1 256/8K 25G RR
- Alveo U250 mqnic/fpga_25g/fpga_10g 2x1 256/8K 10G RR
- Alveo U250 mqnic/fpga_100g/fpga 2x1 256/8K 100G RR
- Alveo U280 mqnic/fpga_25g/fpga 2x1 256/8K 25G RR
- Alveo U280 mqnic/fpga_25g/fpga_10g 2x1 256/8K 10G RR
- Alveo U280 mqnic/fpga_100g/fpga 2x1 256/8K 100G RR
- VCU108 mqnic/fpga_10g/fpga 1x1 256/2K 10G RR
- VCU118 mqnic/fpga_25g/fpga 2x1 256/8K 25G RR
- VCU118 mqnic/fpga_25g/fpga_10g 2x1 256/8K 10G RR
- VCU118 mqnic/fpga_100g/fpga 2x1 256/8K 100G RR
- VCU1525 mqnic/fpga_25g/fpga 2x1 256/8K 25G RR
- VCU1525 mqnic/fpga_25g/fpga_10g 2x1 256/8K 10G RR
- VCU1525 mqnic/fpga_100g/fpga 2x1 256/8K 100G RR
- ZCU106 mqnic/fpga_pcie/fpga 2x1 256/8K 10G RR
- ======================= =========================== ==== ======= ==== =====
+ ======================= =============================== ==== ======= ==== =====
+ Board Design IFxP RXQ/TXQ MAC Sched
+ ======================= =============================== ==== ======= ==== =====
+ ADM-PCIE-9V3 mqnic/fpga_25g/fpga 2x1 256/8K 25G RR
+ ADM-PCIE-9V3 mqnic/fpga_25g/fpga_10g 2x1 256/8K 10G RR
+ ADM-PCIE-9V3 mqnic/fpga_25g/fpga_tdma 2x1 256/256 25G TDMA
+ ADM-PCIE-9V3 mqnic/fpga_100g/fpga 2x1 256/8K 100G RR
+ ADM-PCIE-9V3 mqnic/fpga_100g/fpga_tdma 2x1 256/256 100G TDMA
+ DNPCIe_40G_KU_LL_2QSFP mqnic/fpga/fpga_ku040 2x1 256/2K 10G RR
+ DNPCIe_40G_KU_LL_2QSFP mqnic/fpga/fpga_ku060 2x1 256/2K 10G RR
+ Nexus K35-S mqnic/fpga/fpga 2x1 256/2K 10G RR
+ Nexus K3P-S mqnic/fpga_25g/fpga 2x1 256/8K 25G RR
+ Nexus K3P-S mqnic/fpga_25g/fpga_10g 2x1 256/8K 10G RR
+ Nexus K3P-Q mqnic/fpga_25g/fpga 2x1 256/8K 25G RR
+ Nexus K3P-Q mqnic/fpga_25g/fpga_10g 2x1 256/8K 10G RR
+ fb2CG\@KU15P mqnic/fpga_25g/fpga 2x1 256/8K 25G RR
+ fb2CG\@KU15P mqnic/fpga_25g/fpga_10g 2x1 256/8K 10G RR
+ fb2CG\@KU15P mqnic/fpga_25g/fpga_tdma 2x1 256/256 25G TDMA
+ fb2CG\@KU15P mqnic/fpga_100g/fpga 2x1 256/8K 100G RR
+ fb2CG\@KU15P mqnic/fpga_100g/fpga_tdma 2x1 256/256 100G TDMA
+ NetFPGA SUME mqnic/fpga/fpga 1x1 256/512 10G RR
+ 250-SoC mqnic/fpga_25g/fpga 2x1 256/8K 25G RR
+ 250-SoC mqnic/fpga_25g/fpga_10g 2x1 256/8K 10G RR
+ 250-SoC mqnic/fpga_100g/fpga 2x1 256/8K 100G RR
+ XUP-P3R mqnic/fpga_25g/fpga 4x1 256/8K 25G RR
+ XUP-P3R mqnic/fpga_25g/fpga_10g 4x1 256/8K 10G RR
+ XUP-P3R mqnic/fpga_100g/fpga 4x1 256/8K 100G RR
+ DK-DEV-1SMX-H-A mqnic/fpga_25g/fpga_1sm21b 2x1 256/1K 25G RR
+ DK-DEV-1SMC-H-A mqnic/fpga_25g/fpga_1sm21c 2x1 256/1K 25G RR
+ DK-DEV-1SMX-H-A mqnic/fpga_25g/fpga_10g_1sm21b 2x1 256/1K 10G RR
+ DK-DEV-1SMC-H-A mqnic/fpga_25g/fpga_10g_1sm21c 2x1 256/1K 10G RR
+ DK-DEV-1SDX-P-A mqnic/fpga_25g/fpga 2x1 256/1K 25G RR
+ DK-DEV-1SDX-P-A mqnic/fpga_25g/fpga_10g 2x1 256/1K 10G RR
+ DE10-Agilex mqnic/fpga_25g/fpga 2x1 256/1K 25G RR
+ DE10-Agilex mqnic/fpga_25g/fpga_10g 2x1 256/1K 10G RR
+ DE10-Agilex mqnic/fpga_100g/fpga 2x1 256/1K 100G RR
+ Alveo U50 mqnic/fpga_25g/fpga 1x1 256/8K 25G RR
+ Alveo U50 mqnic/fpga_25g/fpga_10g 1x1 256/8K 10G RR
+ Alveo U50 mqnic/fpga_100g/fpga 1x1 256/8K 100G RR
+ Alveo U200 mqnic/fpga_25g/fpga 2x1 256/8K 25G RR
+ Alveo U200 mqnic/fpga_25g/fpga_10g 2x1 256/8K 10G RR
+ Alveo U200 mqnic/fpga_100g/fpga 2x1 256/8K 100G RR
+ Alveo U250 mqnic/fpga_25g/fpga 2x1 256/8K 25G RR
+ Alveo U250 mqnic/fpga_25g/fpga_10g 2x1 256/8K 10G RR
+ Alveo U250 mqnic/fpga_100g/fpga 2x1 256/8K 100G RR
+ Alveo U280 mqnic/fpga_25g/fpga 2x1 256/8K 25G RR
+ Alveo U280 mqnic/fpga_25g/fpga_10g 2x1 256/8K 10G RR
+ Alveo U280 mqnic/fpga_100g/fpga 2x1 256/8K 100G RR
+ VCU108 mqnic/fpga_10g/fpga 1x1 256/2K 10G RR
+ VCU118 mqnic/fpga_25g/fpga 2x1 256/8K 25G RR
+ VCU118 mqnic/fpga_25g/fpga_10g 2x1 256/8K 10G RR
+ VCU118 mqnic/fpga_100g/fpga 2x1 256/8K 100G RR
+ VCU1525 mqnic/fpga_25g/fpga 2x1 256/8K 25G RR
+ VCU1525 mqnic/fpga_25g/fpga_10g 2x1 256/8K 10G RR
+ VCU1525 mqnic/fpga_100g/fpga 2x1 256/8K 100G RR
+ ZCU106 mqnic/fpga_pcie/fpga 2x1 256/8K 10G RR
+ ======================= =============================== ==== ======= ==== =====
SoC
===
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/fpga.sdc b/fpga/mqnic/S10MX_DK/fpga_10g/fpga.sdc
deleted file mode 100644
index 1147e198b..000000000
--- a/fpga/mqnic/S10MX_DK/fpga_10g/fpga.sdc
+++ /dev/null
@@ -1,107 +0,0 @@
-# Timing constraints for the Intel Stratix 10 MX FPGA development board
-
-set_time_format -unit ns -decimal_places 3
-
-# Clock constraints
-create_clock -period 20.000 -name {clk_sys_50m_p} [ get_ports {clk_sys_50m_p} ]
-create_clock -period 10.000 -name {clk_sys_100m_p} [ get_ports {clk_sys_100m_p} ]
-create_clock -period 10.000 -name {clk_core_bak_p} [ get_ports {clk_core_bak_p} ]
-create_clock -period 10.000 -name {clk_uib0_p} [ get_ports {clk_uib0_p} ]
-create_clock -period 10.000 -name {clk_uib1_p} [ get_ports {clk_uib1_p} ]
-create_clock -period 10.000 -name {clk_esram0_p} [ get_ports {clk_esram0_p} ]
-create_clock -period 10.000 -name {clk_esram1_p} [ get_ports {clk_esram1_p} ]
-create_clock -period 7.500 -name {clk_ddr4_comp_p} [ get_ports {clk_ddr4_comp_p} ]
-create_clock -period 7.500 -name {clk_ddr4_dimm_p} [ get_ports {clk_ddr4_dimm_p} ]
-
-create_clock -period 10.000 -name {refclk_pcie_ep_p} [ get_ports {refclk_pcie_ep_p} ]
-create_clock -period 10.000 -name {refclk_pcie_ep_edge_p} [ get_ports {refclk_pcie_ep_edge_p} ]
-create_clock -period 10.000 -name {refclk_pcie_ep1_p} [ get_ports {refclk_pcie_ep1_p} ]
-create_clock -period 10.000 -name {refclk_pcie_rp_p} [ get_ports {refclk_pcie_rp_p} ]
-
-create_clock -period 1.551 -name {refclk_qsfp0_p} [ get_ports {refclk_qsfp0_p} ]
-create_clock -period 1.551 -name {refclk_qsfp1_p} [ get_ports {refclk_qsfp1_p} ]
-
-derive_clock_uncertainty
-
-set_clock_groups -asynchronous -group [ get_clocks {clk_sys_50m_p} ]
-set_clock_groups -asynchronous -group [ get_clocks {clk_sys_100m_p} ]
-set_clock_groups -asynchronous -group [ get_clocks {clk_core_bak_p} ]
-set_clock_groups -asynchronous -group [ get_clocks {clk_uib0_p} ]
-set_clock_groups -asynchronous -group [ get_clocks {clk_uib1_p} ]
-set_clock_groups -asynchronous -group [ get_clocks {clk_esram0_p} ]
-set_clock_groups -asynchronous -group [ get_clocks {clk_esram1_p} ]
-set_clock_groups -asynchronous -group [ get_clocks {clk_ddr4_comp_p} ]
-set_clock_groups -asynchronous -group [ get_clocks {clk_ddr4_dimm_p} ]
-
-set_clock_groups -asynchronous -group [ get_clocks {refclk_pcie_ep_p} ]
-set_clock_groups -asynchronous -group [ get_clocks {refclk_pcie_ep_edge_p} ]
-set_clock_groups -asynchronous -group [ get_clocks {refclk_pcie_ep1_p} ]
-set_clock_groups -asynchronous -group [ get_clocks {refclk_pcie_rp_p} ]
-
-set_clock_groups -asynchronous -group [ get_clocks {refclk_qsfp0_p} ]
-set_clock_groups -asynchronous -group [ get_clocks {refclk_qsfp1_p} ]
-
-# JTAG constraints
-create_clock -name {altera_reserved_tck} -period 40.800 {altera_reserved_tck}
-
-set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
-
-# IO constraints
-set_false_path -from "cpu_resetn"
-set_false_path -to "user_led[*]"
-
-set_false_path -from "s10_pcie_perstn0"
-set_false_path -from "s10_pcie_perstn1"
-
-
-source ../lib/eth/syn/quartus_pro/eth_mac_fifo.sdc
-source ../lib/eth/lib/axis/syn/quartus_pro/sync_reset.sdc
-source ../lib/eth/lib/axis/syn/quartus_pro/axis_async_fifo.sdc
-
-# clocking infrastructure
-constrain_sync_reset_inst "sync_reset_100mhz_inst"
-constrain_sync_reset_inst "ptp_rst_reset_sync_inst"
-
-# PTP ref clock
-set_clock_groups -asynchronous -group [ get_clocks {ref_div_inst|stratix10_clkctrl_0|clkdiv_inst|clock_div4} ]
-
-# PHY clocks
-set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_1|eth_xcvr_inst|tx_clkout|ch0} ]
-set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_1|eth_xcvr_inst|rx_clkout|ch0} ]
-set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_2|eth_xcvr_inst|tx_clkout|ch0} ]
-set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_2|eth_xcvr_inst|rx_clkout|ch0} ]
-set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_3|eth_xcvr_inst|tx_clkout|ch0} ]
-set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_3|eth_xcvr_inst|rx_clkout|ch0} ]
-set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_4|eth_xcvr_inst|tx_clkout|ch0} ]
-set_clock_groups -asynchronous -group [ get_clocks {qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_4|eth_xcvr_inst|rx_clkout|ch0} ]
-set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_1|eth_xcvr_inst|tx_clkout|ch0} ]
-set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_1|eth_xcvr_inst|rx_clkout|ch0} ]
-set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_2|eth_xcvr_inst|tx_clkout|ch0} ]
-set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_2|eth_xcvr_inst|rx_clkout|ch0} ]
-set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_3|eth_xcvr_inst|tx_clkout|ch0} ]
-set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_3|eth_xcvr_inst|rx_clkout|ch0} ]
-set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_4|eth_xcvr_inst|tx_clkout|ch0} ]
-set_clock_groups -asynchronous -group [ get_clocks {qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_4|eth_xcvr_inst|rx_clkout|ch0} ]
-
-# PHY resets
-constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_1|phy_tx_rst_reset_sync_inst"
-constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_1|phy_rx_rst_reset_sync_inst"
-constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_2|phy_tx_rst_reset_sync_inst"
-constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_2|phy_rx_rst_reset_sync_inst"
-constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_3|phy_tx_rst_reset_sync_inst"
-constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_3|phy_rx_rst_reset_sync_inst"
-constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_4|phy_tx_rst_reset_sync_inst"
-constrain_sync_reset_inst "qsfp0_eth_xcvr_phy_quad|eth_xcvr_phy_4|phy_rx_rst_reset_sync_inst"
-constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_1|phy_tx_rst_reset_sync_inst"
-constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_1|phy_rx_rst_reset_sync_inst"
-constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_2|phy_tx_rst_reset_sync_inst"
-constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_2|phy_rx_rst_reset_sync_inst"
-constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_3|phy_tx_rst_reset_sync_inst"
-constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_3|phy_rx_rst_reset_sync_inst"
-constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_4|phy_tx_rst_reset_sync_inst"
-constrain_sync_reset_inst "qsfp1_eth_xcvr_phy_quad|eth_xcvr_phy_4|phy_rx_rst_reset_sync_inst"
-
-# 10G MAC
-constrain_eth_mac_fifo_inst "core_inst|eth_mac_10g_fifo_inst"
-constrain_axis_async_fifo_inst "core_inst|eth_mac_10g_fifo_inst|rx_fifo|fifo_inst"
-constrain_axis_async_fifo_inst "core_inst|eth_mac_10g_fifo_inst|tx_fifo|fifo_inst"
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/rtl/eth_xcvr_phy_quad_wrapper.v b/fpga/mqnic/S10MX_DK/fpga_10g/rtl/eth_xcvr_phy_quad_wrapper.v
deleted file mode 100644
index a6074a8cf..000000000
--- a/fpga/mqnic/S10MX_DK/fpga_10g/rtl/eth_xcvr_phy_quad_wrapper.v
+++ /dev/null
@@ -1,290 +0,0 @@
-/*
-
-Copyright 2021, The Regents of the University of California.
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
- 1. Redistributions of source code must retain the above copyright notice,
- this list of conditions and the following disclaimer.
-
- 2. Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
- and/or other materials provided with the distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
-IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
-CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
-OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
-IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
-OF SUCH DAMAGE.
-
-The views and conclusions contained in the software and documentation are those
-of the authors and should not be interpreted as representing official policies,
-either expressed or implied, of The Regents of the University of California.
-
-*/
-
-// Language: Verilog 2001
-
-`resetall
-`timescale 1ns / 1ps
-`default_nettype none
-
-/*
- * Transceiver and PHY quad wrapper
- */
-module eth_xcvr_phy_quad_wrapper (
- input wire xcvr_ctrl_clk,
- input wire xcvr_ctrl_rst,
- input wire xcvr_ref_clk,
- output wire [3:0] xcvr_tx_serial_data,
- input wire [3:0] xcvr_rx_serial_data,
-
- output wire phy_1_tx_clk,
- output wire phy_1_tx_rst,
- input wire [63:0] phy_1_xgmii_txd,
- input wire [7:0] phy_1_xgmii_txc,
- output wire phy_1_rx_clk,
- output wire phy_1_rx_rst,
- output wire [63:0] phy_1_xgmii_rxd,
- output wire [7:0] phy_1_xgmii_rxc,
- output wire phy_1_rx_block_lock,
- output wire phy_1_rx_high_ber,
- output wire phy_1_rx_status,
- output wire phy_2_tx_clk,
- output wire phy_2_tx_rst,
- input wire [63:0] phy_2_xgmii_txd,
- input wire [7:0] phy_2_xgmii_txc,
- output wire phy_2_rx_clk,
- output wire phy_2_rx_rst,
- output wire [63:0] phy_2_xgmii_rxd,
- output wire [7:0] phy_2_xgmii_rxc,
- output wire phy_2_rx_block_lock,
- output wire phy_2_rx_high_ber,
- output wire phy_2_rx_status,
- output wire phy_3_tx_clk,
- output wire phy_3_tx_rst,
- input wire [63:0] phy_3_xgmii_txd,
- input wire [7:0] phy_3_xgmii_txc,
- output wire phy_3_rx_clk,
- output wire phy_3_rx_rst,
- output wire [63:0] phy_3_xgmii_rxd,
- output wire [7:0] phy_3_xgmii_rxc,
- output wire phy_3_rx_block_lock,
- output wire phy_3_rx_high_ber,
- output wire phy_3_rx_status,
- output wire phy_4_tx_clk,
- output wire phy_4_tx_rst,
- input wire [63:0] phy_4_xgmii_txd,
- input wire [7:0] phy_4_xgmii_txc,
- output wire phy_4_rx_clk,
- output wire phy_4_rx_rst,
- output wire [63:0] phy_4_xgmii_rxd,
- output wire [7:0] phy_4_xgmii_rxc,
- output wire phy_4_rx_block_lock,
- output wire phy_4_rx_high_ber,
- output wire phy_4_rx_status
-);
-
-wire xcvr_pll_locked;
-wire xcvr_pll_cal_busy;
-
-wire xcvr_tx_serial_clk;
-
-wire [3:0] xcvr_tx_analogreset;
-wire [3:0] xcvr_rx_analogreset;
-wire [3:0] xcvr_tx_digitalreset;
-wire [3:0] xcvr_rx_digitalreset;
-wire [3:0] xcvr_tx_analogreset_stat;
-wire [3:0] xcvr_rx_analogreset_stat;
-wire [3:0] xcvr_tx_digitalreset_stat;
-wire [3:0] xcvr_rx_digitalreset_stat;
-wire [3:0] xcvr_tx_cal_busy;
-wire [3:0] xcvr_rx_cal_busy;
-wire [3:0] xcvr_rx_is_lockedtoref;
-wire [3:0] xcvr_rx_is_lockedtodata;
-wire [3:0] xcvr_tx_ready;
-wire [3:0] xcvr_rx_ready;
-
-eth_xcvr_reset eth_xcvr_reset_inst (
- .clock (xcvr_ctrl_clk),
- .reset (xcvr_ctrl_rst),
- .tx_analogreset (xcvr_tx_analogreset),
- .tx_digitalreset (xcvr_tx_digitalreset),
- .tx_ready (xcvr_tx_ready),
- .pll_locked (xcvr_pll_locked),
- .pll_select (4'd0),
- .tx_cal_busy (xcvr_tx_cal_busy),
- .tx_analogreset_stat (xcvr_tx_analogreset_stat),
- .tx_digitalreset_stat (xcvr_tx_digitalreset_stat),
- .pll_cal_busy (xcvr_pll_cal_busy),
- .rx_analogreset (xcvr_rx_analogreset),
- .rx_digitalreset (xcvr_rx_digitalreset),
- .rx_ready (xcvr_rx_ready),
- .rx_is_lockedtodata (xcvr_rx_is_lockedtodata),
- .rx_cal_busy (xcvr_rx_cal_busy),
- .rx_analogreset_stat (xcvr_rx_analogreset_stat),
- .rx_digitalreset_stat (xcvr_rx_digitalreset_stat)
-);
-
-eth_xcvr_pll eth_xcvr_pll_inst (
- .pll_refclk0 (xcvr_ref_clk),
- .tx_serial_clk (xcvr_tx_serial_clk),
- .pll_locked (xcvr_pll_locked),
- .pll_cal_busy (xcvr_pll_cal_busy)
-);
-
-eth_xcvr_phy_wrapper eth_xcvr_phy_1 (
- .xcvr_ctrl_clk(xcvr_ctrl_clk),
- .xcvr_ctrl_rst(xcvr_ctrl_rst),
-
- .xcvr_tx_analogreset(xcvr_tx_analogreset[0]),
- .xcvr_rx_analogreset(xcvr_rx_analogreset[0]),
- .xcvr_tx_digitalreset(xcvr_tx_digitalreset[0]),
- .xcvr_rx_digitalreset(xcvr_rx_digitalreset[0]),
- .xcvr_tx_analogreset_stat(xcvr_tx_analogreset_stat[0]),
- .xcvr_rx_analogreset_stat(xcvr_rx_analogreset_stat[0]),
- .xcvr_tx_digitalreset_stat(xcvr_tx_digitalreset_stat[0]),
- .xcvr_rx_digitalreset_stat(xcvr_rx_digitalreset_stat[0]),
- .xcvr_tx_cal_busy(xcvr_tx_cal_busy[0]),
- .xcvr_rx_cal_busy(xcvr_rx_cal_busy[0]),
- .xcvr_tx_serial_clk(xcvr_tx_serial_clk),
- .xcvr_rx_cdr_refclk(xcvr_ref_clk),
- .xcvr_tx_serial_data(xcvr_tx_serial_data[0]),
- .xcvr_rx_serial_data(xcvr_rx_serial_data[0]),
- .xcvr_rx_is_lockedtoref(xcvr_rx_is_lockedtoref[0]),
- .xcvr_rx_is_lockedtodata(xcvr_rx_is_lockedtodata[0]),
- .xcvr_tx_ready(xcvr_tx_ready[0]),
- .xcvr_rx_ready(xcvr_rx_ready[0]),
-
- .phy_tx_clk(phy_1_tx_clk),
- .phy_tx_rst(phy_1_tx_rst),
- .phy_xgmii_txd(phy_1_xgmii_txd),
- .phy_xgmii_txc(phy_1_xgmii_txc),
- .phy_rx_clk(phy_1_rx_clk),
- .phy_rx_rst(phy_1_rx_rst),
- .phy_xgmii_rxd(phy_1_xgmii_rxd),
- .phy_xgmii_rxc(phy_1_xgmii_rxc),
- .phy_rx_block_lock(phy_1_rx_block_lock),
- .phy_rx_high_ber(phy_1_rx_high_ber),
- .phy_rx_status(phy_1_rx_status)
-);
-
-eth_xcvr_phy_wrapper eth_xcvr_phy_2 (
- .xcvr_ctrl_clk(xcvr_ctrl_clk),
- .xcvr_ctrl_rst(xcvr_ctrl_rst),
-
- .xcvr_tx_analogreset(xcvr_tx_analogreset[1]),
- .xcvr_rx_analogreset(xcvr_rx_analogreset[1]),
- .xcvr_tx_digitalreset(xcvr_tx_digitalreset[1]),
- .xcvr_rx_digitalreset(xcvr_rx_digitalreset[1]),
- .xcvr_tx_analogreset_stat(xcvr_tx_analogreset_stat[1]),
- .xcvr_rx_analogreset_stat(xcvr_rx_analogreset_stat[1]),
- .xcvr_tx_digitalreset_stat(xcvr_tx_digitalreset_stat[1]),
- .xcvr_rx_digitalreset_stat(xcvr_rx_digitalreset_stat[1]),
- .xcvr_tx_cal_busy(xcvr_tx_cal_busy[1]),
- .xcvr_rx_cal_busy(xcvr_rx_cal_busy[1]),
- .xcvr_tx_serial_clk(xcvr_tx_serial_clk),
- .xcvr_rx_cdr_refclk(xcvr_ref_clk),
- .xcvr_tx_serial_data(xcvr_tx_serial_data[1]),
- .xcvr_rx_serial_data(xcvr_rx_serial_data[1]),
- .xcvr_rx_is_lockedtoref(xcvr_rx_is_lockedtoref[1]),
- .xcvr_rx_is_lockedtodata(xcvr_rx_is_lockedtodata[1]),
- .xcvr_tx_ready(xcvr_tx_ready[1]),
- .xcvr_rx_ready(xcvr_rx_ready[1]),
-
- .phy_tx_clk(phy_2_tx_clk),
- .phy_tx_rst(phy_2_tx_rst),
- .phy_xgmii_txd(phy_2_xgmii_txd),
- .phy_xgmii_txc(phy_2_xgmii_txc),
- .phy_rx_clk(phy_2_rx_clk),
- .phy_rx_rst(phy_2_rx_rst),
- .phy_xgmii_rxd(phy_2_xgmii_rxd),
- .phy_xgmii_rxc(phy_2_xgmii_rxc),
- .phy_rx_block_lock(phy_2_rx_block_lock),
- .phy_rx_high_ber(phy_2_rx_high_ber),
- .phy_rx_status(phy_2_rx_status)
-);
-
-eth_xcvr_phy_wrapper eth_xcvr_phy_3 (
- .xcvr_ctrl_clk(xcvr_ctrl_clk),
- .xcvr_ctrl_rst(xcvr_ctrl_rst),
-
- .xcvr_tx_analogreset(xcvr_tx_analogreset[2]),
- .xcvr_rx_analogreset(xcvr_rx_analogreset[2]),
- .xcvr_tx_digitalreset(xcvr_tx_digitalreset[2]),
- .xcvr_rx_digitalreset(xcvr_rx_digitalreset[2]),
- .xcvr_tx_analogreset_stat(xcvr_tx_analogreset_stat[2]),
- .xcvr_rx_analogreset_stat(xcvr_rx_analogreset_stat[2]),
- .xcvr_tx_digitalreset_stat(xcvr_tx_digitalreset_stat[2]),
- .xcvr_rx_digitalreset_stat(xcvr_rx_digitalreset_stat[2]),
- .xcvr_tx_cal_busy(xcvr_tx_cal_busy[2]),
- .xcvr_rx_cal_busy(xcvr_rx_cal_busy[2]),
- .xcvr_tx_serial_clk(xcvr_tx_serial_clk),
- .xcvr_rx_cdr_refclk(xcvr_ref_clk),
- .xcvr_tx_serial_data(xcvr_tx_serial_data[2]),
- .xcvr_rx_serial_data(xcvr_rx_serial_data[2]),
- .xcvr_rx_is_lockedtoref(xcvr_rx_is_lockedtoref[2]),
- .xcvr_rx_is_lockedtodata(xcvr_rx_is_lockedtodata[2]),
- .xcvr_tx_ready(xcvr_tx_ready[2]),
- .xcvr_rx_ready(xcvr_rx_ready[2]),
-
- .phy_tx_clk(phy_3_tx_clk),
- .phy_tx_rst(phy_3_tx_rst),
- .phy_xgmii_txd(phy_3_xgmii_txd),
- .phy_xgmii_txc(phy_3_xgmii_txc),
- .phy_rx_clk(phy_3_rx_clk),
- .phy_rx_rst(phy_3_rx_rst),
- .phy_xgmii_rxd(phy_3_xgmii_rxd),
- .phy_xgmii_rxc(phy_3_xgmii_rxc),
- .phy_rx_block_lock(phy_3_rx_block_lock),
- .phy_rx_high_ber(phy_3_rx_high_ber),
- .phy_rx_status(phy_3_rx_status)
-);
-
-eth_xcvr_phy_wrapper eth_xcvr_phy_4 (
- .xcvr_ctrl_clk(xcvr_ctrl_clk),
- .xcvr_ctrl_rst(xcvr_ctrl_rst),
-
- .xcvr_tx_analogreset(xcvr_tx_analogreset[3]),
- .xcvr_rx_analogreset(xcvr_rx_analogreset[3]),
- .xcvr_tx_digitalreset(xcvr_tx_digitalreset[3]),
- .xcvr_rx_digitalreset(xcvr_rx_digitalreset[3]),
- .xcvr_tx_analogreset_stat(xcvr_tx_analogreset_stat[3]),
- .xcvr_rx_analogreset_stat(xcvr_rx_analogreset_stat[3]),
- .xcvr_tx_digitalreset_stat(xcvr_tx_digitalreset_stat[3]),
- .xcvr_rx_digitalreset_stat(xcvr_rx_digitalreset_stat[3]),
- .xcvr_tx_cal_busy(xcvr_tx_cal_busy[3]),
- .xcvr_rx_cal_busy(xcvr_rx_cal_busy[3]),
- .xcvr_tx_serial_clk(xcvr_tx_serial_clk),
- .xcvr_rx_cdr_refclk(xcvr_ref_clk),
- .xcvr_tx_serial_data(xcvr_tx_serial_data[3]),
- .xcvr_rx_serial_data(xcvr_rx_serial_data[3]),
- .xcvr_rx_is_lockedtoref(xcvr_rx_is_lockedtoref[3]),
- .xcvr_rx_is_lockedtodata(xcvr_rx_is_lockedtodata[3]),
- .xcvr_tx_ready(xcvr_tx_ready[3]),
- .xcvr_rx_ready(xcvr_rx_ready[3]),
-
- .phy_tx_clk(phy_4_tx_clk),
- .phy_tx_rst(phy_4_tx_rst),
- .phy_xgmii_txd(phy_4_xgmii_txd),
- .phy_xgmii_txc(phy_4_xgmii_txc),
- .phy_rx_clk(phy_4_rx_clk),
- .phy_rx_rst(phy_4_rx_rst),
- .phy_xgmii_rxd(phy_4_xgmii_rxd),
- .phy_xgmii_rxc(phy_4_xgmii_rxc),
- .phy_rx_block_lock(phy_4_rx_block_lock),
- .phy_rx_high_ber(phy_4_rx_high_ber),
- .phy_rx_status(phy_4_rx_status)
-);
-
-endmodule
-
-`resetall
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/rtl/eth_xcvr_phy_wrapper.v b/fpga/mqnic/S10MX_DK/fpga_10g/rtl/eth_xcvr_phy_wrapper.v
deleted file mode 100644
index d327714fb..000000000
--- a/fpga/mqnic/S10MX_DK/fpga_10g/rtl/eth_xcvr_phy_wrapper.v
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
-
-Copyright 2021, The Regents of the University of California.
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
- 1. Redistributions of source code must retain the above copyright notice,
- this list of conditions and the following disclaimer.
-
- 2. Redistributions in binary form must reproduce the above copyright notice,
- this list of conditions and the following disclaimer in the documentation
- and/or other materials provided with the distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
-IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
-CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
-OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
-IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
-OF SUCH DAMAGE.
-
-The views and conclusions contained in the software and documentation are those
-of the authors and should not be interpreted as representing official policies,
-either expressed or implied, of The Regents of the University of California.
-
-*/
-
-// Language: Verilog 2001
-
-`resetall
-`timescale 1ns / 1ps
-`default_nettype none
-
-/*
- * Transceiver and PHY wrapper
- */
-module eth_xcvr_phy_wrapper (
- input wire xcvr_ctrl_clk,
- input wire xcvr_ctrl_rst,
-
- input wire xcvr_tx_analogreset,
- input wire xcvr_rx_analogreset,
- input wire xcvr_tx_digitalreset,
- input wire xcvr_rx_digitalreset,
- output wire xcvr_tx_analogreset_stat,
- output wire xcvr_rx_analogreset_stat,
- output wire xcvr_tx_digitalreset_stat,
- output wire xcvr_rx_digitalreset_stat,
- output wire xcvr_tx_cal_busy,
- output wire xcvr_rx_cal_busy,
- input wire xcvr_tx_serial_clk,
- input wire xcvr_rx_cdr_refclk,
- output wire xcvr_tx_serial_data,
- input wire xcvr_rx_serial_data,
- output wire xcvr_rx_is_lockedtoref,
- output wire xcvr_rx_is_lockedtodata,
- input wire xcvr_tx_ready,
- input wire xcvr_rx_ready,
-
- output wire phy_tx_clk,
- output wire phy_tx_rst,
- input wire [63:0] phy_xgmii_txd,
- input wire [7:0] phy_xgmii_txc,
- output wire phy_rx_clk,
- output wire phy_rx_rst,
- output wire [63:0] phy_xgmii_rxd,
- output wire [7:0] phy_xgmii_rxc,
- output wire phy_rx_block_lock,
- output wire phy_rx_high_ber,
- output wire phy_rx_status
-);
-
-wire xcvr_tx_clk;
-wire xcvr_rx_clk;
-
-assign phy_tx_clk = xcvr_tx_clk;
-assign phy_rx_clk = xcvr_rx_clk;
-
-wire [1:0] xcvr_tx_hdr;
-wire [63:0] xcvr_tx_data;
-wire [1:0] xcvr_rx_hdr;
-wire [63:0] xcvr_rx_data;
-
-wire [1:0] phy_tx_hdr;
-wire [63:0] phy_tx_data;
-wire [1:0] phy_rx_hdr;
-wire [63:0] phy_rx_data;
-
-wire xcvr_rx_bitslip;
-
-assign {xcvr_tx_hdr, xcvr_tx_data} = {phy_tx_data, phy_tx_hdr};
-assign {phy_rx_data, phy_rx_hdr} = {xcvr_rx_hdr, xcvr_rx_data};
-
-eth_xcvr eth_xcvr_inst (
- .tx_analogreset (xcvr_tx_analogreset),
- .rx_analogreset (xcvr_rx_analogreset),
- .tx_digitalreset (xcvr_tx_digitalreset),
- .rx_digitalreset (xcvr_rx_digitalreset),
- .tx_analogreset_stat (xcvr_tx_analogreset_stat),
- .rx_analogreset_stat (xcvr_rx_analogreset_stat),
- .tx_digitalreset_stat (xcvr_tx_digitalreset_stat),
- .rx_digitalreset_stat (xcvr_rx_digitalreset_stat),
- .tx_cal_busy (xcvr_tx_cal_busy),
- .rx_cal_busy (xcvr_rx_cal_busy),
- .tx_serial_clk0 (xcvr_tx_serial_clk),
- .rx_cdr_refclk0 (xcvr_rx_cdr_refclk),
- .tx_serial_data (xcvr_tx_serial_data),
- .rx_serial_data (xcvr_rx_serial_data),
- .rx_is_lockedtoref (xcvr_rx_is_lockedtoref),
- .rx_is_lockedtodata (xcvr_rx_is_lockedtodata),
- .tx_coreclkin (xcvr_tx_clk),
- .rx_coreclkin (xcvr_rx_clk),
- .tx_clkout (xcvr_tx_clk),
- .tx_clkout2 (),
- .rx_clkout (xcvr_rx_clk),
- .rx_clkout2 (),
- .tx_parallel_data (xcvr_tx_data),
- .tx_control (xcvr_tx_hdr),
- .tx_enh_data_valid (1'b1),
- .unused_tx_parallel_data (13'd0),
- .rx_parallel_data (xcvr_rx_data),
- .rx_control (xcvr_rx_hdr),
- .rx_enh_data_valid (),
- .unused_rx_parallel_data (),
- .rx_bitslip (xcvr_rx_bitslip)
-);
-
-sync_reset #(
- .N(4)
-)
-phy_tx_rst_reset_sync_inst (
- .clk(phy_tx_clk),
- .rst(~xcvr_tx_ready),
- .out(phy_tx_rst)
-);
-
-sync_reset #(
- .N(4)
-)
-phy_rx_rst_reset_sync_inst (
- .clk(phy_rx_clk),
- .rst(~xcvr_rx_ready),
- .out(phy_rx_rst)
-);
-
-eth_phy_10g #(
- .BIT_REVERSE(0),
- .BITSLIP_HIGH_CYCLES(32),
- .BITSLIP_LOW_CYCLES(32)
-)
-phy_inst (
- .tx_clk(phy_tx_clk),
- .tx_rst(phy_tx_rst),
- .rx_clk(phy_rx_clk),
- .rx_rst(phy_rx_rst),
- .xgmii_txd(phy_xgmii_txd),
- .xgmii_txc(phy_xgmii_txc),
- .xgmii_rxd(phy_xgmii_rxd),
- .xgmii_rxc(phy_xgmii_rxc),
- .serdes_tx_data(phy_tx_data),
- .serdes_tx_hdr(phy_tx_hdr),
- .serdes_rx_data(phy_rx_data),
- .serdes_rx_hdr(phy_rx_hdr),
- .serdes_rx_bitslip(xcvr_rx_bitslip),
- .rx_block_lock(phy_rx_block_lock),
- .rx_high_ber(phy_rx_high_ber),
- .rx_status(phy_rx_status)
-);
-
-endmodule
-
-`resetall
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/README.md b/fpga/mqnic/S10MX_DK/fpga_25g/README.md
similarity index 100%
rename from fpga/mqnic/S10MX_DK/fpga_10g/README.md
rename to fpga/mqnic/S10MX_DK/fpga_25g/README.md
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/app b/fpga/mqnic/S10MX_DK/fpga_25g/app
similarity index 100%
rename from fpga/mqnic/S10MX_DK/fpga_10g/app
rename to fpga/mqnic/S10MX_DK/fpga_25g/app
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/common/quartus_pro.mk b/fpga/mqnic/S10MX_DK/fpga_25g/common/quartus_pro.mk
similarity index 100%
rename from fpga/mqnic/S10MX_DK/fpga_10g/common/quartus_pro.mk
rename to fpga/mqnic/S10MX_DK/fpga_25g/common/quartus_pro.mk
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/fpga.qsf b/fpga/mqnic/S10MX_DK/fpga_25g/fpga.qsf
similarity index 100%
rename from fpga/mqnic/S10MX_DK/fpga_10g/fpga.qsf
rename to fpga/mqnic/S10MX_DK/fpga_25g/fpga.qsf
diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/fpga.sdc b/fpga/mqnic/S10MX_DK/fpga_25g/fpga.sdc
new file mode 100644
index 000000000..2bb088e79
--- /dev/null
+++ b/fpga/mqnic/S10MX_DK/fpga_25g/fpga.sdc
@@ -0,0 +1,93 @@
+# Timing constraints for the Intel Stratix 10 MX FPGA development board
+
+set_time_format -unit ns -decimal_places 3
+
+# Clock constraints
+create_clock -period 20.000 -name {clk_sys_50m_p} [ get_ports {clk_sys_50m_p} ]
+create_clock -period 10.000 -name {clk_sys_100m_p} [ get_ports {clk_sys_100m_p} ]
+create_clock -period 10.000 -name {clk_core_bak_p} [ get_ports {clk_core_bak_p} ]
+create_clock -period 10.000 -name {clk_uib0_p} [ get_ports {clk_uib0_p} ]
+create_clock -period 10.000 -name {clk_uib1_p} [ get_ports {clk_uib1_p} ]
+create_clock -period 10.000 -name {clk_esram0_p} [ get_ports {clk_esram0_p} ]
+create_clock -period 10.000 -name {clk_esram1_p} [ get_ports {clk_esram1_p} ]
+create_clock -period 7.500 -name {clk_ddr4_comp_p} [ get_ports {clk_ddr4_comp_p} ]
+create_clock -period 7.500 -name {clk_ddr4_dimm_p} [ get_ports {clk_ddr4_dimm_p} ]
+
+create_clock -period 10.000 -name {refclk_pcie_ep_p} [ get_ports {refclk_pcie_ep_p} ]
+create_clock -period 10.000 -name {refclk_pcie_ep_edge_p} [ get_ports {refclk_pcie_ep_edge_p} ]
+create_clock -period 10.000 -name {refclk_pcie_ep1_p} [ get_ports {refclk_pcie_ep1_p} ]
+create_clock -period 10.000 -name {refclk_pcie_rp_p} [ get_ports {refclk_pcie_rp_p} ]
+
+create_clock -period 1.551 -name {refclk_qsfp0_p} [ get_ports {refclk_qsfp0_p} ]
+create_clock -period 1.551 -name {refclk_qsfp1_p} [ get_ports {refclk_qsfp1_p} ]
+
+derive_clock_uncertainty
+
+set_clock_groups -asynchronous -group [ get_clocks {clk_sys_50m_p} ]
+set_clock_groups -asynchronous -group [ get_clocks {clk_sys_100m_p} ]
+set_clock_groups -asynchronous -group [ get_clocks {clk_core_bak_p} ]
+set_clock_groups -asynchronous -group [ get_clocks {clk_uib0_p} ]
+set_clock_groups -asynchronous -group [ get_clocks {clk_uib1_p} ]
+set_clock_groups -asynchronous -group [ get_clocks {clk_esram0_p} ]
+set_clock_groups -asynchronous -group [ get_clocks {clk_esram1_p} ]
+set_clock_groups -asynchronous -group [ get_clocks {clk_ddr4_comp_p} ]
+set_clock_groups -asynchronous -group [ get_clocks {clk_ddr4_dimm_p} ]
+
+set_clock_groups -asynchronous -group [ get_clocks {refclk_pcie_ep_p} ]
+set_clock_groups -asynchronous -group [ get_clocks {refclk_pcie_ep_edge_p} ]
+set_clock_groups -asynchronous -group [ get_clocks {refclk_pcie_ep1_p} ]
+set_clock_groups -asynchronous -group [ get_clocks {refclk_pcie_rp_p} ]
+
+set_clock_groups -asynchronous -group [ get_clocks {refclk_qsfp0_p} ]
+set_clock_groups -asynchronous -group [ get_clocks {refclk_qsfp1_p} ]
+
+# JTAG constraints
+create_clock -name {altera_reserved_tck} -period 40.800 {altera_reserved_tck}
+
+set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
+
+# IO constraints
+set_false_path -from "cpu_resetn"
+set_false_path -to "user_led[*]"
+
+set_false_path -from "s10_pcie_perstn0"
+set_false_path -from "s10_pcie_perstn1"
+
+
+source ../lib/eth/syn/quartus_pro/eth_mac_fifo.sdc
+source ../lib/eth/lib/axis/syn/quartus_pro/sync_reset.sdc
+source ../lib/eth/lib/axis/syn/quartus_pro/axis_async_fifo.sdc
+
+# clocking infrastructure
+constrain_sync_reset_inst "sync_reset_100mhz_inst"
+constrain_sync_reset_inst "ptp_rst_reset_sync_inst"
+
+# PTP ref clock
+set_clock_groups -asynchronous -group [ get_clocks {ref_div_inst|stratix10_clkctrl_0|clkdiv_inst|clock_div4} ]
+
+# PHYs
+proc constrain_phy { inst } {
+ puts "Inserting timing constraints for PHY $inst"
+
+ set_clock_groups -asynchronous -group [ get_clocks "${inst}|eth_xcvr_inst|tx_clkout|ch0" ]
+ set_clock_groups -asynchronous -group [ get_clocks "${inst}|eth_xcvr_inst|rx_clkout|ch0" ]
+ set_clock_groups -asynchronous -group [ get_clocks "${inst}|eth_xcvr_inst|profile0|tx_clkout|ch0" ]
+ set_clock_groups -asynchronous -group [ get_clocks "${inst}|eth_xcvr_inst|profile0|rx_clkout|ch0" ]
+ set_clock_groups -asynchronous -group [ get_clocks "${inst}|eth_xcvr_inst|profile1|tx_clkout|ch0" ]
+ set_clock_groups -asynchronous -group [ get_clocks "${inst}|eth_xcvr_inst|profile1|rx_clkout|ch0" ]
+
+ constrain_sync_reset_inst "$inst|phy_tx_rst_reset_sync_inst"
+ constrain_sync_reset_inst "$inst|phy_rx_rst_reset_sync_inst"
+}
+
+proc constrain_phy_quad { inst } {
+ puts "Inserting timing constraints for PHY quad $inst"
+
+ constrain_phy "${inst}|eth_xcvr_phy_1"
+ constrain_phy "${inst}|eth_xcvr_phy_2"
+ constrain_phy "${inst}|eth_xcvr_phy_3"
+ constrain_phy "${inst}|eth_xcvr_phy_4"
+}
+
+constrain_phy_quad "qsfp0_eth_xcvr_phy_quad"
+constrain_phy_quad "qsfp1_eth_xcvr_phy_quad"
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21b/Makefile b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21b/Makefile
similarity index 98%
rename from fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21b/Makefile
rename to fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21b/Makefile
index e052d689a..4d6fcc24b 100644
--- a/fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21b/Makefile
+++ b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21b/Makefile
@@ -122,8 +122,8 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
# IP files
IP_TCL_FILES += ip/reset_release.tcl
IP_TCL_FILES += ip/pcie.tcl
-IP_TCL_FILES += ip/eth_xcvr.tcl
-IP_TCL_FILES += ip/eth_xcvr_pll.tcl
+IP_TCL_FILES += ip/eth_xcvr_gx.tcl
+IP_TCL_FILES += ip/eth_xcvr_gx_pll.tcl
IP_TCL_FILES += ip/eth_xcvr_reset.tcl
IP_TCL_FILES += ip/ref_div.tcl
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21b/config.tcl b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21b/config.tcl
similarity index 98%
rename from fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21b/config.tcl
rename to fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21b/config.tcl
index b3eb64320..9d8522ffe 100644
--- a/fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21b/config.tcl
+++ b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21b/config.tcl
@@ -70,6 +70,7 @@ set pcie_revision_id [expr 0x00]
set pcie_subsystem_vendor_id $board_vendor_id
set pcie_subsystem_device_id $board_device_id
+# FW ID block
dict set params FPGA_ID [format "32'h%08x" $fpga_id]
dict set params FW_ID [format "32'h%08x" $fw_id]
dict set params FW_VER [format "32'h%02x%02x%02x%02x" {*}[split $fw_ver .-] 0 0 0 0]
@@ -79,6 +80,9 @@ dict set params BUILD_DATE "32'd${build_date}"
dict set params GIT_HASH "32'h${git_hash}"
dict set params RELEASE_INFO [format "32'h%08x" $release_info]
+# Board configuration
+dict set params TDMA_BER_ENABLE "0"
+
# Structural configuration
dict set params IF_COUNT "2"
dict set params PORTS_PER_IF "1"
@@ -175,11 +179,13 @@ dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
# Ethernet interface configuration
+dict set params AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE "0"
dict set params AXIS_ETH_TX_PIPELINE "0"
dict set params AXIS_ETH_TX_FIFO_PIPELINE "2"
dict set params AXIS_ETH_TX_TS_PIPELINE "0"
dict set params AXIS_ETH_RX_PIPELINE "0"
dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
+dict set params ETH_XCVR_GXT "0"
# Statistics counter subsystem
dict set params STAT_ENABLE "0"
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21c/Makefile b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21c/Makefile
similarity index 98%
rename from fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21c/Makefile
rename to fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21c/Makefile
index 71e70e965..ab946ab5d 100644
--- a/fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21c/Makefile
+++ b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21c/Makefile
@@ -122,8 +122,8 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
# IP files
IP_TCL_FILES += ip/reset_release.tcl
IP_TCL_FILES += ip/pcie.tcl
-IP_TCL_FILES += ip/eth_xcvr.tcl
-IP_TCL_FILES += ip/eth_xcvr_pll.tcl
+IP_TCL_FILES += ip/eth_xcvr_gx.tcl
+IP_TCL_FILES += ip/eth_xcvr_gx_pll.tcl
IP_TCL_FILES += ip/eth_xcvr_reset.tcl
IP_TCL_FILES += ip/ref_div.tcl
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21c/config.tcl b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21c/config.tcl
similarity index 98%
rename from fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21c/config.tcl
rename to fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21c/config.tcl
index d386477c3..5f2ad7152 100644
--- a/fpga/mqnic/S10MX_DK/fpga_10g/fpga_1sm21c/config.tcl
+++ b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_10g_1sm21c/config.tcl
@@ -70,6 +70,7 @@ set pcie_revision_id [expr 0x00]
set pcie_subsystem_vendor_id $board_vendor_id
set pcie_subsystem_device_id $board_device_id
+# FW ID block
dict set params FPGA_ID [format "32'h%08x" $fpga_id]
dict set params FW_ID [format "32'h%08x" $fw_id]
dict set params FW_VER [format "32'h%02x%02x%02x%02x" {*}[split $fw_ver .-] 0 0 0 0]
@@ -79,6 +80,9 @@ dict set params BUILD_DATE "32'd${build_date}"
dict set params GIT_HASH "32'h${git_hash}"
dict set params RELEASE_INFO [format "32'h%08x" $release_info]
+# Board configuration
+dict set params TDMA_BER_ENABLE "0"
+
# Structural configuration
dict set params IF_COUNT "2"
dict set params PORTS_PER_IF "1"
@@ -173,11 +177,13 @@ dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
# Ethernet interface configuration
+dict set params AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE "0"
dict set params AXIS_ETH_TX_PIPELINE "0"
dict set params AXIS_ETH_TX_FIFO_PIPELINE "2"
dict set params AXIS_ETH_TX_TS_PIPELINE "0"
dict set params AXIS_ETH_RX_PIPELINE "0"
dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
+dict set params ETH_XCVR_GXT "0"
# Statistics counter subsystem
dict set params STAT_ENABLE "0"
diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21b/Makefile b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21b/Makefile
new file mode 100644
index 000000000..46b3d878f
--- /dev/null
+++ b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21b/Makefile
@@ -0,0 +1,144 @@
+
+# FPGA settings
+FPGA_TOP = fpga
+FPGA_FAMILY = "Stratix 10 MX"
+FPGA_DEVICE = 1SM21BHU2F53E1VG
+
+# Files for synthesis
+SYN_FILES = rtl/fpga.v
+SYN_FILES += rtl/fpga_core.v
+SYN_FILES += rtl/sync_signal.v
+SYN_FILES += rtl/eth_xcvr_phy_wrapper.v
+SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v
+SYN_FILES += rtl/common/mqnic_core_pcie_s10.v
+SYN_FILES += rtl/common/mqnic_core_pcie.v
+SYN_FILES += rtl/common/mqnic_core.v
+SYN_FILES += rtl/common/mqnic_interface.v
+SYN_FILES += rtl/common/mqnic_interface_tx.v
+SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
+SYN_FILES += rtl/common/mqnic_egress.v
+SYN_FILES += rtl/common/mqnic_ingress.v
+SYN_FILES += rtl/common/mqnic_l2_egress.v
+SYN_FILES += rtl/common/mqnic_l2_ingress.v
+SYN_FILES += rtl/common/mqnic_rx_queue_map.v
+SYN_FILES += rtl/common/mqnic_ptp.v
+SYN_FILES += rtl/common/mqnic_ptp_clock.v
+SYN_FILES += rtl/common/mqnic_ptp_perout.v
+SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v
+SYN_FILES += rtl/common/cpl_write.v
+SYN_FILES += rtl/common/cpl_op_mux.v
+SYN_FILES += rtl/common/desc_fetch.v
+SYN_FILES += rtl/common/desc_op_mux.v
+SYN_FILES += rtl/common/event_mux.v
+SYN_FILES += rtl/common/queue_manager.v
+SYN_FILES += rtl/common/cpl_queue_manager.v
+SYN_FILES += rtl/common/tx_fifo.v
+SYN_FILES += rtl/common/rx_fifo.v
+SYN_FILES += rtl/common/tx_req_mux.v
+SYN_FILES += rtl/common/tx_engine.v
+SYN_FILES += rtl/common/rx_engine.v
+SYN_FILES += rtl/common/tx_checksum.v
+SYN_FILES += rtl/common/rx_hash.v
+SYN_FILES += rtl/common/rx_checksum.v
+SYN_FILES += rtl/common/stats_counter.v
+SYN_FILES += rtl/common/stats_collect.v
+SYN_FILES += rtl/common/stats_pcie_if.v
+SYN_FILES += rtl/common/stats_pcie_tlp.v
+SYN_FILES += rtl/common/stats_dma_if_pcie.v
+SYN_FILES += rtl/common/stats_dma_latency.v
+SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
+SYN_FILES += rtl/common/tx_scheduler_rr.v
+SYN_FILES += rtl/common/tdma_scheduler.v
+SYN_FILES += rtl/common/tdma_ber.v
+SYN_FILES += rtl/common/tdma_ber_ch.v
+SYN_FILES += lib/eth/rtl/eth_mac_10g.v
+SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
+SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
+SYN_FILES += lib/eth/rtl/eth_phy_10g.v
+SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
+SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v
+SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v
+SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v
+SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v
+SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v
+SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
+SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
+SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
+SYN_FILES += lib/eth/rtl/lfsr.v
+SYN_FILES += lib/eth/rtl/ptp_clock.v
+SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
+SYN_FILES += lib/eth/rtl/ptp_perout.v
+SYN_FILES += lib/axi/rtl/axil_interconnect.v
+SYN_FILES += lib/axi/rtl/axil_crossbar.v
+SYN_FILES += lib/axi/rtl/axil_crossbar_addr.v
+SYN_FILES += lib/axi/rtl/axil_crossbar_rd.v
+SYN_FILES += lib/axi/rtl/axil_crossbar_wr.v
+SYN_FILES += lib/axi/rtl/axil_reg_if.v
+SYN_FILES += lib/axi/rtl/axil_reg_if_rd.v
+SYN_FILES += lib/axi/rtl/axil_reg_if_wr.v
+SYN_FILES += lib/axi/rtl/axil_register_rd.v
+SYN_FILES += lib/axi/rtl/axil_register_wr.v
+SYN_FILES += lib/axi/rtl/arbiter.v
+SYN_FILES += lib/axi/rtl/priority_encoder.v
+SYN_FILES += lib/axis/rtl/axis_adapter.v
+SYN_FILES += lib/axis/rtl/axis_arb_mux.v
+SYN_FILES += lib/axis/rtl/axis_async_fifo.v
+SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
+SYN_FILES += lib/axis/rtl/axis_demux.v
+SYN_FILES += lib/axis/rtl/axis_fifo.v
+SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
+SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
+SYN_FILES += lib/axis/rtl/axis_register.v
+SYN_FILES += lib/axis/rtl/sync_reset.v
+SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_msix.v
+SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
+SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
+SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
+SYN_FILES += lib/pcie/rtl/dma_if_mux.v
+SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
+SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v
+SYN_FILES += lib/pcie/rtl/dma_if_desc_mux.v
+SYN_FILES += lib/pcie/rtl/dma_ram_demux_rd.v
+SYN_FILES += lib/pcie/rtl/dma_ram_demux_wr.v
+SYN_FILES += lib/pcie/rtl/dma_psdpram.v
+SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v
+SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v
+SYN_FILES += lib/pcie/rtl/pcie_s10_if.v
+SYN_FILES += lib/pcie/rtl/pcie_s10_if_rx.v
+SYN_FILES += lib/pcie/rtl/pcie_s10_if_tx.v
+SYN_FILES += lib/pcie/rtl/pcie_s10_cfg.v
+SYN_FILES += lib/pcie/rtl/pulse_merge.v
+
+# IP files
+IP_TCL_FILES += ip/reset_release.tcl
+IP_TCL_FILES += ip/pcie.tcl
+IP_TCL_FILES += ip/eth_xcvr_gxt.tcl
+IP_TCL_FILES += ip/eth_xcvr_gx_pll.tcl
+IP_TCL_FILES += ip/eth_xcvr_gxt_pll.tcl
+IP_TCL_FILES += ip/eth_xcvr_gxt_buf.tcl
+IP_TCL_FILES += ip/eth_xcvr_reset.tcl
+IP_TCL_FILES += ip/ref_div.tcl
+
+# QSF files
+QSF_FILES = fpga.qsf
+
+# SDC files
+SDC_FILES = fpga.sdc
+
+# Configuration
+CONFIG_TCL_FILES = ./config.tcl
+
+include ../common/quartus_pro.mk
+
+program: fpga
+ quartus_pgm --no_banner --mode=jtag -o "P;$(FPGA_TOP).sof@1"
diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21b/config.tcl b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21b/config.tcl
new file mode 100644
index 000000000..50da6cf6f
--- /dev/null
+++ b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21b/config.tcl
@@ -0,0 +1,247 @@
+# Copyright 2021, The Regents of the University of California.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
+# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+# OF SUCH DAMAGE.
+#
+# The views and conclusions contained in the software and documentation are those
+# of the authors and should not be interpreted as representing official policies,
+# either expressed or implied, of The Regents of the University of California.
+
+set params [dict create]
+
+# collect build information
+set build_date [clock seconds]
+set git_hash 00000000
+set git_tag ""
+
+if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } {
+ puts "Error running git or project not under version control"
+}
+
+if { [catch {set git_tag [exec git describe --tags HEAD]}] } {
+ puts "Error running git, project not under version control, or no tag found"
+}
+
+puts "Build date: ${build_date}"
+puts "Git hash: ${git_hash}"
+puts "Git tag: ${git_tag}"
+
+if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } {
+ puts "Failed to extract version from git tag"
+ set tag_ver 0.0.1
+}
+
+puts "Tag version: ${tag_ver}"
+
+# FW and board IDs
+set fpga_id [expr 0x632AC0DD]
+set fw_id [expr 0x00000000]
+set fw_ver $tag_ver
+set board_vendor_id [expr 0x1172]
+set board_device_id [expr 0x0001]
+set board_ver 1.0
+set release_info [expr 0x00000000]
+
+# PCIe IDs
+set pcie_vendor_id [expr 0x1234]
+set pcie_device_id [expr 0x1001]
+set pcie_class_code [expr 0x020000]
+set pcie_revision_id [expr 0x00]
+set pcie_subsystem_vendor_id $board_vendor_id
+set pcie_subsystem_device_id $board_device_id
+
+# FW ID block
+dict set params FPGA_ID [format "32'h%08x" $fpga_id]
+dict set params FW_ID [format "32'h%08x" $fw_id]
+dict set params FW_VER [format "32'h%02x%02x%02x%02x" {*}[split $fw_ver .-] 0 0 0 0]
+dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id]
+dict set params BOARD_VER [format "32'h%02x%02x%02x%02x" {*}[split $board_ver .-] 0 0 0 0]
+dict set params BUILD_DATE "32'd${build_date}"
+dict set params GIT_HASH "32'h${git_hash}"
+dict set params RELEASE_INFO [format "32'h%08x" $release_info]
+
+# Board configuration
+dict set params TDMA_BER_ENABLE "0"
+
+# Structural configuration
+dict set params IF_COUNT "2"
+dict set params PORTS_PER_IF "1"
+dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
+dict set params PORT_MASK "0"
+
+# PTP configuration
+dict set params PTP_CLOCK_PIPELINE "0"
+dict set params PTP_CLOCK_CDC_PIPELINE "0"
+dict set params PTP_PORT_CDC_PIPELINE "0"
+dict set params PTP_PEROUT_ENABLE "1"
+dict set params PTP_PEROUT_COUNT "1"
+
+# Queue manager configuration
+dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
+dict set params TX_QUEUE_OP_TABLE_SIZE "32"
+dict set params RX_QUEUE_OP_TABLE_SIZE "32"
+dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
+dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
+dict set params EVENT_QUEUE_INDEX_WIDTH "6"
+dict set params TX_QUEUE_INDEX_WIDTH "10"
+dict set params RX_QUEUE_INDEX_WIDTH "8"
+dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
+dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH]
+dict set params EVENT_QUEUE_PIPELINE "3"
+dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)]
+dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)]
+dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
+dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
+
+# TX and RX engine configuration
+dict set params TX_DESC_TABLE_SIZE "32"
+dict set params RX_DESC_TABLE_SIZE "32"
+
+# Scheduler configuration
+dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
+dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
+dict set params TDMA_INDEX_WIDTH "6"
+
+# Interface configuration
+dict set params PTP_TS_ENABLE "1"
+dict set params TX_CPL_FIFO_DEPTH "32"
+dict set params TX_CHECKSUM_ENABLE "1"
+dict set params RX_RSS_ENABLE "1"
+dict set params RX_HASH_ENABLE "1"
+dict set params RX_CHECKSUM_ENABLE "1"
+dict set params TX_FIFO_DEPTH "32768"
+dict set params RX_FIFO_DEPTH "32768"
+dict set params MAX_TX_SIZE "9214"
+dict set params MAX_RX_SIZE "9214"
+dict set params TX_RAM_SIZE "32768"
+dict set params RX_RAM_SIZE "32768"
+
+# Application block configuration
+dict set params APP_ID "32'h00000000"
+dict set params APP_ENABLE "0"
+dict set params APP_CTRL_ENABLE "1"
+dict set params APP_DMA_ENABLE "1"
+dict set params APP_AXIS_DIRECT_ENABLE "1"
+dict set params APP_AXIS_SYNC_ENABLE "1"
+dict set params APP_AXIS_IF_ENABLE "1"
+dict set params APP_STAT_ENABLE "1"
+
+# DMA interface configuration
+dict set params DMA_IMM_ENABLE "0"
+dict set params DMA_IMM_WIDTH "32"
+dict set params DMA_LEN_WIDTH "16"
+dict set params DMA_TAG_WIDTH "16"
+dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
+dict set params RAM_PIPELINE "2"
+
+# PCIe interface configuration
+dict set params SEG_COUNT "1"
+dict set params SEG_DATA_WIDTH "256"
+dict set params SEG_EMPTY_WIDTH [expr int(ceil(log([dict get $params SEG_DATA_WIDTH]/32.0)/log(2)))]
+dict set params TX_SEQ_NUM_WIDTH "6"
+dict set params PCIE_TAG_COUNT "256"
+dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
+dict set params PCIE_DMA_READ_TX_LIMIT "16"
+dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
+dict set params PCIE_DMA_WRITE_OP_TABLE_SIZE "16"
+dict set params PCIE_DMA_WRITE_TX_LIMIT "3"
+dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1"
+
+# Interrupt configuration
+dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
+
+# AXI lite interface configuration (control)
+dict set params AXIL_CTRL_DATA_WIDTH "32"
+dict set params AXIL_CTRL_ADDR_WIDTH "24"
+
+# AXI lite interface configuration (application control)
+dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
+dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
+
+# Ethernet interface configuration
+dict set params AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE "1"
+dict set params AXIS_ETH_TX_PIPELINE "0"
+dict set params AXIS_ETH_TX_FIFO_PIPELINE "2"
+dict set params AXIS_ETH_TX_TS_PIPELINE "0"
+dict set params AXIS_ETH_RX_PIPELINE "0"
+dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
+dict set params ETH_XCVR_GXT "1"
+
+# Statistics counter subsystem
+dict set params STAT_ENABLE "0"
+dict set params STAT_DMA_ENABLE "1"
+dict set params STAT_PCIE_ENABLE "1"
+dict set params STAT_INC_WIDTH "24"
+dict set params STAT_ID_WIDTH "12"
+
+# PCIe IP core settings
+set pcie pcie_s10_hip_ast_0
+set pcie_ip pcie
+set fp [open "update_ip_${pcie_ip}.tcl" "w"]
+
+puts $fp "package require qsys"
+puts $fp "load_system ip/${pcie_ip}.ip"
+
+# PCIe IDs
+puts $fp "set_instance_parameter_value ${pcie} {pf0_pci_type0_device_id_hwtcl} {$pcie_device_id}"
+puts $fp "set_instance_parameter_value ${pcie} {pf0_pci_type0_vendor_id_hwtcl} {$pcie_vendor_id}"
+puts $fp "set_instance_parameter_value ${pcie} {pf0_class_code_hwtcl} {$pcie_class_code}"
+puts $fp "set_instance_parameter_value ${pcie} {pf0_revision_id_hwtcl} {$pcie_revision_id}"
+puts $fp "set_instance_parameter_value ${pcie} {pf0_subsys_dev_id_hwtcl} {$pcie_subsystem_device_id}"
+puts $fp "set_instance_parameter_value ${pcie} {pf0_subsys_vendor_id_hwtcl} {$pcie_subsystem_vendor_id}"
+
+# PCIe IP core configuration
+puts $fp "set_instance_parameter_value ${pcie} {pf0_pci_msix_table_size_hwtcl} {[expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]}"
+
+# configure BAR settings
+proc configure_bar {fp pcie pf bar aperture} {
+ if {$aperture > 0} {
+ puts "PF${pf} BAR${bar}: aperture ${aperture} bits"
+
+ puts $fp "set_instance_parameter_value ${pcie} {pf${pf}_bar${bar}_address_width_hwtcl} {${aperture}}"
+ puts $fp "set_instance_parameter_value ${pcie} {pf${pf}_bar${bar}_type_hwtcl} {64-bit prefetchable memory}"
+
+ return
+ }
+ puts "PF${pf} BAR${bar}: disabled"
+
+ puts $fp "set_instance_parameter_value ${pcie} {pf${pf}_bar${bar}_address_width_hwtcl} {0}"
+ puts $fp "set_instance_parameter_value ${pcie} {pf${pf}_bar${bar}_type_hwtcl} {Disabled}"
+}
+
+# Control BAR (BAR 0)
+configure_bar $fp $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH]
+
+# Application BAR (BAR 2)
+configure_bar $fp $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0]
+
+puts $fp "save_system"
+close $fp
+
+# apply parameters to PCIe IP core
+exec -ignorestderr qsys-script "--qpf=fpga.qpf" "--script=update_ip_${pcie_ip}.tcl"
+
+# apply parameters to top-level
+dict for {name value} $params {
+ set_parameter -name $name $value
+}
diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21c/Makefile b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21c/Makefile
new file mode 100644
index 000000000..bbfa67be0
--- /dev/null
+++ b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21c/Makefile
@@ -0,0 +1,144 @@
+
+# FPGA settings
+FPGA_TOP = fpga
+FPGA_FAMILY = "Stratix 10 MX"
+FPGA_DEVICE = 1SM21CHU1F53E1VG
+
+# Files for synthesis
+SYN_FILES = rtl/fpga.v
+SYN_FILES += rtl/fpga_core.v
+SYN_FILES += rtl/sync_signal.v
+SYN_FILES += rtl/eth_xcvr_phy_wrapper.v
+SYN_FILES += rtl/eth_xcvr_phy_quad_wrapper.v
+SYN_FILES += rtl/common/mqnic_core_pcie_s10.v
+SYN_FILES += rtl/common/mqnic_core_pcie.v
+SYN_FILES += rtl/common/mqnic_core.v
+SYN_FILES += rtl/common/mqnic_interface.v
+SYN_FILES += rtl/common/mqnic_interface_tx.v
+SYN_FILES += rtl/common/mqnic_interface_rx.v
+SYN_FILES += rtl/common/mqnic_port.v
+SYN_FILES += rtl/common/mqnic_port_tx.v
+SYN_FILES += rtl/common/mqnic_port_rx.v
+SYN_FILES += rtl/common/mqnic_egress.v
+SYN_FILES += rtl/common/mqnic_ingress.v
+SYN_FILES += rtl/common/mqnic_l2_egress.v
+SYN_FILES += rtl/common/mqnic_l2_ingress.v
+SYN_FILES += rtl/common/mqnic_rx_queue_map.v
+SYN_FILES += rtl/common/mqnic_ptp.v
+SYN_FILES += rtl/common/mqnic_ptp_clock.v
+SYN_FILES += rtl/common/mqnic_ptp_perout.v
+SYN_FILES += rtl/common/mqnic_port_map_phy_xgmii.v
+SYN_FILES += rtl/common/cpl_write.v
+SYN_FILES += rtl/common/cpl_op_mux.v
+SYN_FILES += rtl/common/desc_fetch.v
+SYN_FILES += rtl/common/desc_op_mux.v
+SYN_FILES += rtl/common/event_mux.v
+SYN_FILES += rtl/common/queue_manager.v
+SYN_FILES += rtl/common/cpl_queue_manager.v
+SYN_FILES += rtl/common/tx_fifo.v
+SYN_FILES += rtl/common/rx_fifo.v
+SYN_FILES += rtl/common/tx_req_mux.v
+SYN_FILES += rtl/common/tx_engine.v
+SYN_FILES += rtl/common/rx_engine.v
+SYN_FILES += rtl/common/tx_checksum.v
+SYN_FILES += rtl/common/rx_hash.v
+SYN_FILES += rtl/common/rx_checksum.v
+SYN_FILES += rtl/common/stats_counter.v
+SYN_FILES += rtl/common/stats_collect.v
+SYN_FILES += rtl/common/stats_pcie_if.v
+SYN_FILES += rtl/common/stats_pcie_tlp.v
+SYN_FILES += rtl/common/stats_dma_if_pcie.v
+SYN_FILES += rtl/common/stats_dma_latency.v
+SYN_FILES += rtl/common/mqnic_tx_scheduler_block_rr.v
+SYN_FILES += rtl/common/tx_scheduler_rr.v
+SYN_FILES += rtl/common/tdma_scheduler.v
+SYN_FILES += rtl/common/tdma_ber.v
+SYN_FILES += rtl/common/tdma_ber_ch.v
+SYN_FILES += lib/eth/rtl/eth_mac_10g.v
+SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
+SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
+SYN_FILES += lib/eth/rtl/eth_phy_10g.v
+SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
+SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v
+SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v
+SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v
+SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v
+SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v
+SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
+SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
+SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
+SYN_FILES += lib/eth/rtl/lfsr.v
+SYN_FILES += lib/eth/rtl/ptp_clock.v
+SYN_FILES += lib/eth/rtl/ptp_clock_cdc.v
+SYN_FILES += lib/eth/rtl/ptp_perout.v
+SYN_FILES += lib/axi/rtl/axil_interconnect.v
+SYN_FILES += lib/axi/rtl/axil_crossbar.v
+SYN_FILES += lib/axi/rtl/axil_crossbar_addr.v
+SYN_FILES += lib/axi/rtl/axil_crossbar_rd.v
+SYN_FILES += lib/axi/rtl/axil_crossbar_wr.v
+SYN_FILES += lib/axi/rtl/axil_reg_if.v
+SYN_FILES += lib/axi/rtl/axil_reg_if_rd.v
+SYN_FILES += lib/axi/rtl/axil_reg_if_wr.v
+SYN_FILES += lib/axi/rtl/axil_register_rd.v
+SYN_FILES += lib/axi/rtl/axil_register_wr.v
+SYN_FILES += lib/axi/rtl/arbiter.v
+SYN_FILES += lib/axi/rtl/priority_encoder.v
+SYN_FILES += lib/axis/rtl/axis_adapter.v
+SYN_FILES += lib/axis/rtl/axis_arb_mux.v
+SYN_FILES += lib/axis/rtl/axis_async_fifo.v
+SYN_FILES += lib/axis/rtl/axis_async_fifo_adapter.v
+SYN_FILES += lib/axis/rtl/axis_demux.v
+SYN_FILES += lib/axis/rtl/axis_fifo.v
+SYN_FILES += lib/axis/rtl/axis_fifo_adapter.v
+SYN_FILES += lib/axis/rtl/axis_pipeline_fifo.v
+SYN_FILES += lib/axis/rtl/axis_register.v
+SYN_FILES += lib/axis/rtl/sync_reset.v
+SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_raw.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_fifo_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_msix.v
+SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
+SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
+SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
+SYN_FILES += lib/pcie/rtl/dma_if_mux.v
+SYN_FILES += lib/pcie/rtl/dma_if_mux_rd.v
+SYN_FILES += lib/pcie/rtl/dma_if_mux_wr.v
+SYN_FILES += lib/pcie/rtl/dma_if_desc_mux.v
+SYN_FILES += lib/pcie/rtl/dma_ram_demux_rd.v
+SYN_FILES += lib/pcie/rtl/dma_ram_demux_wr.v
+SYN_FILES += lib/pcie/rtl/dma_psdpram.v
+SYN_FILES += lib/pcie/rtl/dma_client_axis_sink.v
+SYN_FILES += lib/pcie/rtl/dma_client_axis_source.v
+SYN_FILES += lib/pcie/rtl/pcie_s10_if.v
+SYN_FILES += lib/pcie/rtl/pcie_s10_if_rx.v
+SYN_FILES += lib/pcie/rtl/pcie_s10_if_tx.v
+SYN_FILES += lib/pcie/rtl/pcie_s10_cfg.v
+SYN_FILES += lib/pcie/rtl/pulse_merge.v
+
+# IP files
+IP_TCL_FILES += ip/reset_release.tcl
+IP_TCL_FILES += ip/pcie.tcl
+IP_TCL_FILES += ip/eth_xcvr_gxt.tcl
+IP_TCL_FILES += ip/eth_xcvr_gx_pll.tcl
+IP_TCL_FILES += ip/eth_xcvr_gxt_pll.tcl
+IP_TCL_FILES += ip/eth_xcvr_gxt_buf.tcl
+IP_TCL_FILES += ip/eth_xcvr_reset.tcl
+IP_TCL_FILES += ip/ref_div.tcl
+
+# QSF files
+QSF_FILES = fpga.qsf
+
+# SDC files
+SDC_FILES = fpga.sdc
+
+# Configuration
+CONFIG_TCL_FILES = ./config.tcl
+
+include ../common/quartus_pro.mk
+
+program: fpga
+ quartus_pgm --no_banner --mode=jtag -o "P;$(FPGA_TOP).sof@1"
diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21c/config.tcl b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21c/config.tcl
new file mode 100644
index 000000000..8ee9b0a28
--- /dev/null
+++ b/fpga/mqnic/S10MX_DK/fpga_25g/fpga_1sm21c/config.tcl
@@ -0,0 +1,245 @@
+# Copyright 2021, The Regents of the University of California.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
+# IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+# DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+# OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+# IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+# OF SUCH DAMAGE.
+#
+# The views and conclusions contained in the software and documentation are those
+# of the authors and should not be interpreted as representing official policies,
+# either expressed or implied, of The Regents of the University of California.
+
+set params [dict create]
+
+# collect build information
+set build_date [clock seconds]
+set git_hash 00000000
+set git_tag ""
+
+if { [catch {set git_hash [exec git rev-parse --short=8 HEAD]}] } {
+ puts "Error running git or project not under version control"
+}
+
+if { [catch {set git_tag [exec git describe --tags HEAD]}] } {
+ puts "Error running git, project not under version control, or no tag found"
+}
+
+puts "Build date: ${build_date}"
+puts "Git hash: ${git_hash}"
+puts "Git tag: ${git_tag}"
+
+if { ! [regsub {^.*(\d+\.\d+\.\d+([\.-]\d+)?).*$} $git_tag {\1} tag_ver ] } {
+ puts "Failed to extract version from git tag"
+ set tag_ver 0.0.1
+}
+
+puts "Tag version: ${tag_ver}"
+
+# FW and board IDs
+set fpga_id [expr 0x432AC0DD]
+set fw_id [expr 0x00000000]
+set fw_ver $tag_ver
+set board_vendor_id [expr 0x1172]
+set board_device_id [expr 0x0001]
+set board_ver 1.0
+set release_info [expr 0x00000000]
+
+# PCIe IDs
+set pcie_vendor_id [expr 0x1234]
+set pcie_device_id [expr 0x1001]
+set pcie_class_code [expr 0x020000]
+set pcie_revision_id [expr 0x00]
+set pcie_subsystem_vendor_id $board_vendor_id
+set pcie_subsystem_device_id $board_device_id
+
+# FW ID block
+dict set params FPGA_ID [format "32'h%08x" $fpga_id]
+dict set params FW_ID [format "32'h%08x" $fw_id]
+dict set params FW_VER [format "32'h%02x%02x%02x%02x" {*}[split $fw_ver .-] 0 0 0 0]
+dict set params BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id]
+dict set params BOARD_VER [format "32'h%02x%02x%02x%02x" {*}[split $board_ver .-] 0 0 0 0]
+dict set params BUILD_DATE "32'd${build_date}"
+dict set params GIT_HASH "32'h${git_hash}"
+dict set params RELEASE_INFO [format "32'h%08x" $release_info]
+
+# Board configuration
+dict set params TDMA_BER_ENABLE "0"
+
+# Structural configuration
+dict set params IF_COUNT "2"
+dict set params PORTS_PER_IF "1"
+dict set params SCHED_PER_IF [dict get $params PORTS_PER_IF]
+dict set params PORT_MASK "0"
+
+# PTP configuration
+dict set params PTP_CLOCK_PIPELINE "0"
+dict set params PTP_CLOCK_CDC_PIPELINE "0"
+dict set params PTP_PORT_CDC_PIPELINE "0"
+dict set params PTP_PEROUT_ENABLE "1"
+dict set params PTP_PEROUT_COUNT "1"
+
+# Queue manager configuration
+dict set params EVENT_QUEUE_OP_TABLE_SIZE "32"
+dict set params TX_QUEUE_OP_TABLE_SIZE "32"
+dict set params RX_QUEUE_OP_TABLE_SIZE "32"
+dict set params TX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params TX_QUEUE_OP_TABLE_SIZE]
+dict set params RX_CPL_QUEUE_OP_TABLE_SIZE [dict get $params RX_QUEUE_OP_TABLE_SIZE]
+dict set params EVENT_QUEUE_INDEX_WIDTH "6"
+dict set params TX_QUEUE_INDEX_WIDTH "10"
+dict set params RX_QUEUE_INDEX_WIDTH "8"
+dict set params TX_CPL_QUEUE_INDEX_WIDTH [dict get $params TX_QUEUE_INDEX_WIDTH]
+dict set params RX_CPL_QUEUE_INDEX_WIDTH [dict get $params RX_QUEUE_INDEX_WIDTH]
+dict set params EVENT_QUEUE_PIPELINE "3"
+dict set params TX_QUEUE_PIPELINE [expr 3+([dict get $params TX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params TX_QUEUE_INDEX_WIDTH]-12 : 0)]
+dict set params RX_QUEUE_PIPELINE [expr 3+([dict get $params RX_QUEUE_INDEX_WIDTH] > 12 ? [dict get $params RX_QUEUE_INDEX_WIDTH]-12 : 0)]
+dict set params TX_CPL_QUEUE_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
+dict set params RX_CPL_QUEUE_PIPELINE [dict get $params RX_QUEUE_PIPELINE]
+
+# TX and RX engine configuration
+dict set params TX_DESC_TABLE_SIZE "32"
+dict set params RX_DESC_TABLE_SIZE "32"
+
+# Scheduler configuration
+dict set params TX_SCHEDULER_OP_TABLE_SIZE [dict get $params TX_DESC_TABLE_SIZE]
+dict set params TX_SCHEDULER_PIPELINE [dict get $params TX_QUEUE_PIPELINE]
+dict set params TDMA_INDEX_WIDTH "6"
+
+# Interface configuration
+dict set params PTP_TS_ENABLE "1"
+dict set params TX_CPL_FIFO_DEPTH "32"
+dict set params TX_CHECKSUM_ENABLE "1"
+dict set params RX_RSS_ENABLE "1"
+dict set params RX_HASH_ENABLE "1"
+dict set params RX_CHECKSUM_ENABLE "1"
+dict set params TX_FIFO_DEPTH "32768"
+dict set params RX_FIFO_DEPTH "32768"
+dict set params MAX_TX_SIZE "9214"
+dict set params MAX_RX_SIZE "9214"
+dict set params TX_RAM_SIZE "32768"
+dict set params RX_RAM_SIZE "32768"
+
+# Application block configuration
+dict set params APP_ID "32'h00000000"
+dict set params APP_ENABLE "0"
+dict set params APP_CTRL_ENABLE "1"
+dict set params APP_DMA_ENABLE "1"
+dict set params APP_AXIS_DIRECT_ENABLE "1"
+dict set params APP_AXIS_SYNC_ENABLE "1"
+dict set params APP_AXIS_IF_ENABLE "1"
+dict set params APP_STAT_ENABLE "1"
+
+# DMA interface configuration
+dict set params DMA_LEN_WIDTH "16"
+dict set params DMA_TAG_WIDTH "16"
+dict set params RAM_ADDR_WIDTH [expr int(ceil(log(max([dict get $params TX_RAM_SIZE], [dict get $params RX_RAM_SIZE]))/log(2)))]
+dict set params RAM_PIPELINE "2"
+
+# PCIe interface configuration
+dict set params SEG_COUNT "1"
+dict set params SEG_DATA_WIDTH "256"
+dict set params SEG_EMPTY_WIDTH [expr int(ceil(log([dict get $params SEG_DATA_WIDTH]/32.0)/log(2)))]
+dict set params TX_SEQ_NUM_WIDTH "6"
+dict set params PCIE_TAG_COUNT "256"
+dict set params PCIE_DMA_READ_OP_TABLE_SIZE [dict get $params PCIE_TAG_COUNT]
+dict set params PCIE_DMA_READ_TX_LIMIT "16"
+dict set params PCIE_DMA_READ_TX_FC_ENABLE "1"
+dict set params PCIE_DMA_WRITE_OP_TABLE_SIZE "16"
+dict set params PCIE_DMA_WRITE_TX_LIMIT "3"
+dict set params PCIE_DMA_WRITE_TX_FC_ENABLE "1"
+
+# Interrupt configuration
+dict set params IRQ_INDEX_WIDTH [dict get $params EVENT_QUEUE_INDEX_WIDTH]
+
+# AXI lite interface configuration (control)
+dict set params AXIL_CTRL_DATA_WIDTH "32"
+dict set params AXIL_CTRL_ADDR_WIDTH "24"
+
+# AXI lite interface configuration (application control)
+dict set params AXIL_APP_CTRL_DATA_WIDTH [dict get $params AXIL_CTRL_DATA_WIDTH]
+dict set params AXIL_APP_CTRL_ADDR_WIDTH "24"
+
+# Ethernet interface configuration
+dict set params AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE "1"
+dict set params AXIS_ETH_TX_PIPELINE "0"
+dict set params AXIS_ETH_TX_FIFO_PIPELINE "2"
+dict set params AXIS_ETH_TX_TS_PIPELINE "0"
+dict set params AXIS_ETH_RX_PIPELINE "0"
+dict set params AXIS_ETH_RX_FIFO_PIPELINE "2"
+dict set params ETH_XCVR_GXT "1"
+
+# Statistics counter subsystem
+dict set params STAT_ENABLE "0"
+dict set params STAT_DMA_ENABLE "1"
+dict set params STAT_PCIE_ENABLE "1"
+dict set params STAT_INC_WIDTH "24"
+dict set params STAT_ID_WIDTH "12"
+
+# PCIe IP core settings
+set pcie pcie_s10_hip_ast_0
+set pcie_ip pcie
+set fp [open "update_ip_${pcie_ip}.tcl" "w"]
+
+puts $fp "package require qsys"
+puts $fp "load_system ip/${pcie_ip}.ip"
+
+# PCIe IDs
+puts $fp "set_instance_parameter_value ${pcie} {pf0_pci_type0_device_id_hwtcl} {$pcie_device_id}"
+puts $fp "set_instance_parameter_value ${pcie} {pf0_pci_type0_vendor_id_hwtcl} {$pcie_vendor_id}"
+puts $fp "set_instance_parameter_value ${pcie} {pf0_class_code_hwtcl} {$pcie_class_code}"
+puts $fp "set_instance_parameter_value ${pcie} {pf0_revision_id_hwtcl} {$pcie_revision_id}"
+puts $fp "set_instance_parameter_value ${pcie} {pf0_subsys_dev_id_hwtcl} {$pcie_subsystem_device_id}"
+puts $fp "set_instance_parameter_value ${pcie} {pf0_subsys_vendor_id_hwtcl} {$pcie_subsystem_vendor_id}"
+
+# PCIe IP core configuration
+puts $fp "set_instance_parameter_value ${pcie} {pf0_pci_msix_table_size_hwtcl} {[expr 2**[dict get $params IRQ_INDEX_WIDTH]-1]}"
+
+# configure BAR settings
+proc configure_bar {fp pcie pf bar aperture} {
+ if {$aperture > 0} {
+ puts "PF${pf} BAR${bar}: aperture ${aperture} bits"
+
+ puts $fp "set_instance_parameter_value ${pcie} {pf${pf}_bar${bar}_address_width_hwtcl} {${aperture}}"
+ puts $fp "set_instance_parameter_value ${pcie} {pf${pf}_bar${bar}_type_hwtcl} {64-bit prefetchable memory}"
+
+ return
+ }
+ puts "PF${pf} BAR${bar}: disabled"
+
+ puts $fp "set_instance_parameter_value ${pcie} {pf${pf}_bar${bar}_address_width_hwtcl} {0}"
+ puts $fp "set_instance_parameter_value ${pcie} {pf${pf}_bar${bar}_type_hwtcl} {Disabled}"
+}
+
+# Control BAR (BAR 0)
+configure_bar $fp $pcie 0 0 [dict get $params AXIL_CTRL_ADDR_WIDTH]
+
+# Application BAR (BAR 2)
+configure_bar $fp $pcie 0 2 [expr [dict get $params APP_ENABLE] ? [dict get $params AXIL_APP_CTRL_ADDR_WIDTH] : 0]
+
+puts $fp "save_system"
+close $fp
+
+# apply parameters to PCIe IP core
+exec -ignorestderr qsys-script "--qpf=fpga.qpf" "--script=update_ip_${pcie_ip}.tcl"
+
+# apply parameters to top-level
+dict for {name value} $params {
+ set_parameter -name $name $value
+}
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/ip/eth_xcvr.tcl b/fpga/mqnic/S10MX_DK/fpga_25g/ip/eth_xcvr_gx.tcl
similarity index 98%
rename from fpga/mqnic/S10MX_DK/fpga_10g/ip/eth_xcvr.tcl
rename to fpga/mqnic/S10MX_DK/fpga_25g/ip/eth_xcvr_gx.tcl
index 20bb8cc2b..cd2367302 100644
--- a/fpga/mqnic/S10MX_DK/fpga_10g/ip/eth_xcvr.tcl
+++ b/fpga/mqnic/S10MX_DK/fpga_25g/ip/eth_xcvr_gx.tcl
@@ -1,9 +1,9 @@
-package require -exact qsys 20.4
+package require -exact qsys 21.3
-# create the system "eth_xcvr"
-proc do_create_eth_xcvr {} {
+# create the system "eth_xcvr_gx"
+proc do_create_eth_xcvr_gx {} {
# create the system
- create_system eth_xcvr
+ create_system eth_xcvr_gx
set_project_property DEVICE {1SM21CHU1F53E1VG}
set_project_property DEVICE_FAMILY {Stratix 10}
set_project_property HIDE_FROM_IP_CATALOG {true}
@@ -160,7 +160,7 @@ proc do_create_eth_xcvr {} {
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_polinv_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_randomdispbit_enable} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_scram_enable} {0}
- set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_scram_seed} {2.88230376152e+17}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_scram_seed} {2.0}
set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_sh_err} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {generate_add_hdl_instance_example} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {generate_docs} {1}
@@ -242,10 +242,11 @@ proc do_create_eth_xcvr {} {
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_fifo_pempty} {2}
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_fifo_pfull} {10}
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_adapt_mode} {ctle_dfe}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_adapt_start_gui} {1}
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_analog_mode} {user_custom}
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_div_clkout_divider} {33}
- set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_optimal_settings} {1}
- set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_term_sel} {r_r2}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_optimal_settings} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_term_sel} {r_r4}
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_ppm_detect_threshold} {1000}
set_instance_parameter_value xcvr_native_s10_htile_0 {rx_vga_dc_gain} {0}
set_instance_parameter_value xcvr_native_s10_htile_0 {set_capability_reg_enable} {0}
@@ -320,6 +321,8 @@ proc do_create_eth_xcvr {} {
# add wirelevel expressions
+ # preserve ports for debug
+
# add the exports
set_interface_property tx_analogreset EXPORT_OF xcvr_native_s10_htile_0.tx_analogreset
set_interface_property rx_analogreset EXPORT_OF xcvr_native_s10_htile_0.rx_analogreset
@@ -363,20 +366,20 @@ proc do_create_eth_xcvr {} {
}
- set_module_property FILE {eth_xcvr.ip}
+ set_module_property FILE {eth_xcvr_gx.ip}
set_module_property GENERATION_ID {0x00000000}
- set_module_property NAME {eth_xcvr}
+ set_module_property NAME {eth_xcvr_gx}
# save the system
sync_sysinfo_parameters
- save_system eth_xcvr
+ save_system eth_xcvr_gx
}
proc do_set_exported_interface_sysinfo_parameters {} {
}
# create all the systems, from bottom up
-do_create_eth_xcvr
+do_create_eth_xcvr_gx
# set system info parameters on exported interface, from bottom up
do_set_exported_interface_sysinfo_parameters
diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/ip/eth_xcvr_gx_pll.tcl b/fpga/mqnic/S10MX_DK/fpga_25g/ip/eth_xcvr_gx_pll.tcl
new file mode 100644
index 000000000..8a90f042d
--- /dev/null
+++ b/fpga/mqnic/S10MX_DK/fpga_25g/ip/eth_xcvr_gx_pll.tcl
@@ -0,0 +1,143 @@
+package require -exact qsys 21.3
+
+# create the system "eth_xcvr_gx_pll"
+proc do_create_eth_xcvr_gx_pll {} {
+ # create the system
+ create_system eth_xcvr_gx_pll
+ set_project_property DEVICE {1SM21CHU1F53E1VG}
+ set_project_property DEVICE_FAMILY {Stratix 10}
+ set_project_property HIDE_FROM_IP_CATALOG {true}
+ set_use_testbench_naming_pattern 0 {}
+
+ # add HDL parameters
+
+ # add the components
+ add_instance xcvr_fpll_s10_htile_0 altera_xcvr_fpll_s10_htile
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {base_device} {Unknown}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_analog_resets} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_bonding_clks} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_debug_ports_parameters} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_fb_comp_bonding} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_hfreq_clk} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_hip_cal_done_port} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_manual_configuration} {1}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_mcgb} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_mcgb_hip_cal_done_port} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_mcgb_pcie_clksw} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_mcgb_reset} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_pcie_hip_connectivity} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_pld_fpll_cal_busy_port} {1}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {enable_pld_mcgb_cal_busy_port} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {generate_add_hdl_instance_example} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {generate_docs} {1}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {mcgb_aux_clkin_cnt} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {mcgb_div} {1}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {message_level} {error}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {outclk_en} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {pma_width} {64}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {powerdown_mode} {powerup}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_debug} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_enable} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_enable_avmm_busy_port} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_file_prefix} {altera_xcvr_fpll_s10}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_files_as_common_package} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_h_file_enable} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_jtag_enable} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_mif_file_enable} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_multi_enable} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_profile_cnt} {2}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_profile_data0} {}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_profile_data1} {}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_profile_data2} {}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_profile_data3} {}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_profile_data4} {}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_profile_data5} {}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_profile_data6} {}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_profile_data7} {}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_profile_select} {1}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_reduced_files_enable} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_sdc_derived_profile_data0} {}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_sdc_derived_profile_data1} {}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_sdc_derived_profile_data2} {}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_sdc_derived_profile_data3} {}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_sdc_derived_profile_data4} {}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_sdc_derived_profile_data5} {}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_sdc_derived_profile_data6} {}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_sdc_derived_profile_data7} {}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_separate_avmm_busy} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_sv_file_enable} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {rcfg_txt_file_enable} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {select_manual_config} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_altera_xcvr_fpll_s10_calibration_en} {1}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_auto_reference_clock_frequency} {644.53125}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_bw_sel} {medium}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_capability_reg_enable} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_csr_soft_logic_enable} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_enable_dps} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_enable_fractional} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_enable_hclk_out} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_fref_clock_frequency} {100.0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_hip_cal_en} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_initial_phase_shift} {0.0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_initial_phase_shift_units} {degrees}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_manual_c_counter} {4}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_manual_k_counter} {1.0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_manual_l_counter} {2}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_manual_m_counter} {50}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_manual_output_clock_frequency} {2500.0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_manual_ref_clk_div} {1}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_manual_reference_clock_frequency} {100.0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_output_clock_frequency} {5156.25}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_power_mode} {1_1V}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_primary_use} {2}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_prot_mode} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_rcfg_emb_strm_enable} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_refclk_cnt} {1}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_refclk_index} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_user_identifier} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_x1_core_clock} {1}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_x2_core_clock} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {set_x4_core_clock} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {silicon_rev} {0}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {support_mode} {user_mode}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {test_mode} {false}
+ set_instance_parameter_value xcvr_fpll_s10_htile_0 {usr_enable_vco_bypass} {0}
+ set_instance_property xcvr_fpll_s10_htile_0 AUTO_EXPORT true
+
+ # add wirelevel expressions
+
+ # preserve ports for debug
+
+ # add the exports
+ set_interface_property pll_refclk0 EXPORT_OF xcvr_fpll_s10_htile_0.pll_refclk0
+ set_interface_property tx_serial_clk EXPORT_OF xcvr_fpll_s10_htile_0.tx_serial_clk
+ set_interface_property pll_locked EXPORT_OF xcvr_fpll_s10_htile_0.pll_locked
+ set_interface_property pll_cal_busy EXPORT_OF xcvr_fpll_s10_htile_0.pll_cal_busy
+
+ # set values for exposed HDL parameters
+
+ # set the the module properties
+ set_module_property BONUS_DATA {
+
+
+
+
+
+}
+ set_module_property FILE {eth_xcvr_gx_pll.ip}
+ set_module_property GENERATION_ID {0x00000000}
+ set_module_property NAME {eth_xcvr_gx_pll}
+
+ # save the system
+ sync_sysinfo_parameters
+ save_system eth_xcvr_gx_pll
+}
+
+proc do_set_exported_interface_sysinfo_parameters {} {
+}
+
+# create all the systems, from bottom up
+do_create_eth_xcvr_gx_pll
+
+# set system info parameters on exported interface, from bottom up
+do_set_exported_interface_sysinfo_parameters
diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/ip/eth_xcvr_gxt.tcl b/fpga/mqnic/S10MX_DK/fpga_25g/ip/eth_xcvr_gxt.tcl
new file mode 100644
index 000000000..267954e5e
--- /dev/null
+++ b/fpga/mqnic/S10MX_DK/fpga_25g/ip/eth_xcvr_gxt.tcl
@@ -0,0 +1,389 @@
+package require -exact qsys 21.3
+
+# create the system "eth_xcvr_gxt"
+proc do_create_eth_xcvr_gxt {} {
+ # create the system
+ create_system eth_xcvr_gxt
+ set_project_property DEVICE {1SM21CHU1F53E1VG}
+ set_project_property DEVICE_FAMILY {Stratix 10}
+ set_project_property HIDE_FROM_IP_CATALOG {true}
+ set_use_testbench_naming_pattern 0 {}
+
+ # add HDL parameters
+
+ # add the components
+ add_instance xcvr_native_s10_htile_0 altera_xcvr_native_s10_htile
+ set_instance_parameter_value xcvr_native_s10_htile_0 {adapter_ehip_mode} {disable_hip}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {anlg_link} {lr}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {anlg_voltage} {1_1V}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {avmm_ehip_mode} {disable_hip}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {base_device} {Unknown}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {bonded_mode} {not_bonded}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {cdr_refclk_cnt} {1}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {cdr_refclk_select} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {channel_type} {GXT}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {channels} {1}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {delay_measurement_clkout2_sel} {clock_delay_measurement_clkout}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {delay_measurement_clkout_sel} {clock_delay_measurement_clkout}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {design_environment} {NATIVE}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {design_example_filename} {dexample}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {disable_digital_reset_sequencer} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {disable_reset_sequencer} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {duplex_mode} {duplex}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {early_spd_chng_t1} {60}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {early_spd_chng_t2} {150}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {early_spd_chng_t3} {1000}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_advanced_user_mode} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_background_cal_gui} {1}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_channel_powerdown} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_de_hardware_debug} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_debug_ports} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_direct_reset_control} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_double_rate_transfer} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_early_spd_chng} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ehip} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_fast_sim} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_hard_reset} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_hip} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_insert_eios_err} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_mac_total_control} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_manual_bonding_settings} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_clock_delay_measurement} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_krfec_rx_enh_frame} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_krfec_rx_enh_frame_diag_status} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_krfec_tx_enh_frame} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_latency_measurement} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_clkout2} {1}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_clkout2_hioint} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_clkout_hioint} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_data_valid} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_bitslip} {1}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_blk_lock} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_clr_errblk_count} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_crc32_err} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_frame} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_frame_diag_status} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_frame_lock} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_highber} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_enh_highber_clr_cnt} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_align_clr} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_del} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_empty} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_full} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_insert} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_latency_adj_ena} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_pempty} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_pfull} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_fifo_rd_en} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_is_lockedtodata} {1}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_is_lockedtoref} {1}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_pcs_fifo_empty} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_pcs_fifo_full} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_pma_clkslip} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_pma_iqtxrx_clkout} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_pma_qpipulldn} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_polinv} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_seriallpbken} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_bitrev_ena} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_bitslip} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_bitslipboundarysel} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_byterev_ena} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_rmfifo_empty} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_rmfifo_full} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_signaldetect} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_wa_a1a2size} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_rx_std_wa_patternalign} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_clkout2} {1}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_clkout2_hioint} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_clkout_hioint} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_dll_lock} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_enh_bitslip} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_enh_frame} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_enh_frame_burst_en} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_enh_frame_diag_status} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_fifo_empty} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_fifo_full} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_fifo_latency_adj_ena} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_fifo_pempty} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_fifo_pfull} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pcs_fifo_empty} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pcs_fifo_full} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pma_elecidle} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pma_iqtxrx_clkout} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pma_qpipulldn} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pma_qpipullup} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pma_rxfound} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_pma_txdetectrx} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_polinv} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_port_tx_std_bitslipboundarysel} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ports_adaptation} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ports_pipe_hclk} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ports_pipe_rx_elecidle} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ports_pipe_sw} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ports_rx_manual_cdr_mode} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_ports_rx_prbs} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_qpi_async_transfer} {1}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_qpi_mode} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_rcfg_tx_digitalreset_release_ctrl} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_rx_fast_pipeln_reg} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_simple_interface} {1}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_split_interface} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_transparent_pcs} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_tx_coreclkin2} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_tx_fast_pipeln_reg} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enable_workaround_rules} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enh_advanced_user_mode} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enh_low_latency_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enh_pcs_pma_width} {64}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enh_pld_pcs_width} {66}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_64b66b_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_bitslip_enable} {1}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_blksync_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_crcchk_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_descram_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_dispchk_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_frmsync_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_frmsync_mfrm_length} {2048}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_krfec_err_mark_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_krfec_err_mark_type} {10G}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enh_rx_polinv_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_64b66b_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_bitslip_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_crcerr_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_crcgen_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_dispgen_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_frmgen_burst_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_frmgen_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_frmgen_mfrm_length} {2048}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_krfec_burst_err_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_krfec_burst_err_len} {1}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_polinv_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_randomdispbit_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_scram_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_scram_seed} {2.0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {enh_tx_sh_err} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {generate_add_hdl_instance_example} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {generate_docs} {1}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {hip_channels} {x1}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {hip_mode} {disable_hip}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {hip_prot_mode} {gen1}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {loopback_tx_clk_sel} {internal_clk}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {manual_pcs_bonding_comp_cnt} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {manual_pcs_bonding_mode} {individual}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {manual_rx_core_aib_bonding_comp_cnt} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {manual_rx_core_aib_bonding_mode} {individual}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {manual_rx_core_aib_indv} {indv_en}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {manual_rx_hssi_aib_bonding_comp_cnt} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {manual_rx_hssi_aib_bonding_mode} {individual}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {manual_rx_hssi_aib_indv} {indv_en}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {manual_tx_core_aib_bonding_comp_cnt} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {manual_tx_core_aib_bonding_mode} {individual}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {manual_tx_core_aib_indv} {indv_en}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {manual_tx_hssi_aib_bonding_comp_cnt} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {manual_tx_hssi_aib_bonding_mode} {individual}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {manual_tx_hssi_aib_indv} {indv_en}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {message_level} {error}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {number_physical_bonding_clocks} {1}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {osc_clk_divider} {1}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {ovrd_rx_dv_mode} {1}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {ovrd_tx_dv_mode} {1}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {parallel_loopback_mode} {disable}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {pcie_rate_match} {Bypass}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {pcs_direct_width} {8}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {pcs_reset_sequencing_mode} {not_bonded}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {pll_select} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {plls} {2}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {pma_mode} {basic}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {protocol_mode} {basic_enh}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {qsf_assignments_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_debug} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_enable} {1}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_enable_avmm_busy_port} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_file_prefix} {altera_xcvr_rcfg_10}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_files_as_common_package} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_h_file_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_iface_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_jtag_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_mif_file_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_multi_enable} {1}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_cnt} {2}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data0} {rcfg_debug 0 rcfg_enable 1 rcfg_jtag_enable 0 rcfg_separate_avmm_busy 0 rcfg_enable_avmm_busy_port 0 set_capability_reg_enable 0 set_user_identifier 0 set_csr_soft_logic_enable 1 support_mode user_mode channel_type GXT protocol_mode basic_enh pma_mode basic duplex_mode duplex channels 1 set_data_rate 25781.25 rcfg_iface_enable 0 enable_simple_interface 1 enable_split_interface 0 set_enable_calibration 1 enable_double_rate_transfer 0 enable_background_cal_gui 1 enable_direct_reset_control 0 disable_reset_sequencer 0 disable_digital_reset_sequencer 0 bonded_mode not_bonded set_pcs_bonding_master Auto pcs_reset_sequencing_mode not_bonded manual_pcs_bonding_mode individual manual_pcs_bonding_comp_cnt 0 manual_tx_hssi_aib_bonding_mode individual manual_tx_hssi_aib_bonding_comp_cnt 0 manual_tx_core_aib_bonding_mode individual manual_tx_core_aib_bonding_comp_cnt 0 manual_rx_hssi_aib_bonding_mode individual manual_rx_hssi_aib_bonding_comp_cnt 0 manual_rx_core_aib_bonding_mode individual manual_rx_core_aib_bonding_comp_cnt 0 manual_tx_hssi_aib_indv indv_en manual_tx_core_aib_indv indv_en manual_rx_hssi_aib_indv indv_en manual_rx_core_aib_indv indv_en tx_pma_clk_div 1 plls 2 pll_select 0 enable_port_tx_pma_iqtxrx_clkout 0 enable_port_tx_pma_elecidle 0 number_physical_bonding_clocks 1 enable_qpi_mode 0 enable_qpi_async_transfer 1 enable_port_tx_pma_qpipullup 0 enable_port_tx_pma_qpipulldn 0 enable_port_tx_pma_rxfound 0 enable_port_rx_pma_qpipulldn 0 enable_port_tx_pma_txdetectrx 0 cdr_refclk_cnt 1 cdr_refclk_select 0 set_cdr_refclk_freq 644.531250 rx_ppm_detect_threshold 1000 enable_port_rx_pma_iqtxrx_clkout 0 enable_port_rx_pma_clkslip 0 enable_port_rx_is_lockedtodata 1 enable_port_rx_is_lockedtoref 1 enable_ports_rx_manual_cdr_mode 0 enable_ports_rx_prbs 0 enable_port_rx_seriallpbken 0 std_pcs_pma_width 10 std_low_latency_bypass_enable 0 enable_hip 0 enable_hard_reset 0 set_hip_cal_en 0 hip_mode disable_hip hip_prot_mode gen1 hip_channels x1 enable_ehip 0 avmm_ehip_mode disable_hip adapter_ehip_mode disable_hip std_tx_byte_ser_mode Disabled std_rx_byte_deser_mode Disabled std_tx_8b10b_enable 0 std_tx_8b10b_disp_ctrl_enable 0 std_rx_8b10b_enable 0 std_rx_rmfifo_mode disabled std_rx_rmfifo_pattern_n 0 std_rx_rmfifo_pattern_p 0 enable_port_rx_std_rmfifo_full 0 enable_port_rx_std_rmfifo_empty 0 pcie_rate_match Bypass std_tx_bitslip_enable 0 enable_port_tx_std_bitslipboundarysel 0 std_rx_word_aligner_mode bitslip std_rx_word_aligner_pattern_len 7 std_rx_word_aligner_pattern 0 std_rx_word_aligner_rknumber 3 std_rx_word_aligner_renumber 3 std_rx_word_aligner_rgnumber 3 std_rx_word_aligner_fast_sync_status_enable 0 enable_port_rx_std_wa_patternalign 0 enable_port_rx_std_wa_a1a2size 0 enable_port_rx_std_bitslipboundarysel 0 enable_port_rx_std_bitslip 0 std_tx_bitrev_enable 0 std_tx_byterev_enable 0 std_tx_polinv_enable 0 enable_port_tx_polinv 0 std_rx_bitrev_enable 0 enable_port_rx_std_bitrev_ena 0 std_rx_byterev_enable 0 enable_port_rx_std_byterev_ena 0 std_rx_polinv_enable 0 enable_port_rx_polinv 0 enable_port_rx_std_signaldetect 0 enable_ports_pipe_sw 0 enable_ports_pipe_rx_elecidle 0 enable_ports_pipe_hclk 0 enh_pcs_pma_width 64 enh_pld_pcs_width 66 enh_low_latency_enable 0 enh_advanced_user_mode 0 enh_tx_frmgen_enable 0 enh_tx_frmgen_mfrm_length 2048 enh_tx_frmgen_burst_enable 0 enable_port_tx_enh_frame 0 enable_port_tx_enh_frame_diag_status 0 enable_port_tx_enh_frame_burst_en 0 enh_rx_frmsync_enable 0 enh_rx_frmsync_mfrm_length 2048 enable_port_rx_enh_frame 0 enable_port_rx_enh_frame_lock 0 enable_port_rx_enh_frame_diag_status 0 enh_tx_crcgen_enable 0 enh_tx_crcerr_enable 0 enh_rx_crcchk_enable 0 enable_port_rx_enh_crc32_err 0 enable_port_rx_enh_highber 0 enable_port_rx_enh_highber_clr_cnt 0 enable_port_rx_enh_clr_errblk_count 0 enh_tx_64b66b_enable 0 enh_rx_64b66b_enable 0 enh_tx_sh_err 0 enh_tx_scram_enable 0 enh_tx_scram_seed 2 enh_rx_descram_enable 0 enh_tx_dispgen_enable 0 enh_rx_dispchk_enable 0 enh_tx_randomdispbit_enable 0 enh_rx_blksync_enable 0 enable_port_rx_enh_blk_lock 0 enh_tx_bitslip_enable 0 enh_tx_polinv_enable 0 enh_rx_bitslip_enable 1 enh_rx_polinv_enable 0 enable_port_tx_enh_bitslip 0 enable_port_rx_enh_bitslip 1 enh_rx_krfec_err_mark_enable 0 enh_rx_krfec_err_mark_type 10G enh_tx_krfec_burst_err_enable 0 enh_tx_krfec_burst_err_len 1 enable_port_krfec_tx_enh_frame 0 enable_port_krfec_rx_enh_frame 0 enable_port_krfec_rx_enh_frame_diag_status 0 pcs_direct_width 8 enable_tx_fast_pipeln_reg 0 enable_rx_fast_pipeln_reg 0 parallel_loopback_mode disable loopback_tx_clk_sel internal_clk enable_debug_ports 0 tx_fifo_mode {Phase compensation} tx_fifo_pfull 10 tx_fifo_pempty 2 enable_port_tx_fifo_full 0 enable_port_tx_fifo_empty 0 enable_port_tx_fifo_pfull 0 enable_port_tx_fifo_pempty 0 enable_port_tx_pcs_fifo_full 0 enable_port_tx_pcs_fifo_empty 0 enable_port_tx_dll_lock 0 rx_fifo_mode {Phase compensation} rx_fifo_pfull 10 rx_fifo_pempty 2 rx_fifo_align_del 0 rx_fifo_control_del 0 enable_port_rx_data_valid 0 enable_port_rx_fifo_full 0 enable_port_rx_fifo_empty 0 enable_port_rx_fifo_pfull 0 enable_port_rx_fifo_pempty 0 enable_port_rx_fifo_del 0 enable_port_rx_fifo_insert 0 enable_port_rx_fifo_rd_en 0 enable_port_rx_fifo_align_clr 0 enable_port_rx_pcs_fifo_full 0 enable_port_rx_pcs_fifo_empty 0 tx_clkout_sel pma_div_clkout enable_port_tx_clkout2 1 tx_clkout2_sel pcs_clkout enable_port_tx_clkout_hioint 0 enable_port_tx_clkout2_hioint 0 tx_pma_div_clkout_divider 33 tx_coreclkin_clock_network dedicated tx_pcs_bonding_clock_network dedicated rx_clkout_sel pma_div_clkout enable_port_rx_clkout2 1 rx_clkout2_sel pcs_clkout enable_port_rx_clkout_hioint 0 enable_port_rx_clkout2_hioint 0 rx_pma_div_clkout_divider 33 rx_coreclkin_clock_network dedicated osc_clk_divider 1 enable_port_tx_fifo_latency_adj_ena 0 enable_port_rx_fifo_latency_adj_ena 0 enable_port_latency_measurement 0 enable_port_clock_delay_measurement 0 delay_measurement_clkout_sel clock_delay_measurement_clkout delay_measurement_clkout2_sel clock_delay_measurement_clkout ovrd_tx_dv_mode 1 usr_tx_dv_mode enable ovrd_rx_dv_mode 1 usr_rx_dv_mode enable set_prbs_soft_logic_enable 0 enable_rcfg_tx_digitalreset_release_ctrl 0 anlg_voltage 1_1V anlg_link lr enable_ports_adaptation 0 tx_pma_analog_mode user_custom rx_pma_analog_mode user_custom tx_pma_optimal_settings 1 tx_pma_output_swing_ctrl 12 tx_pma_pre_emp_sign_pre_tap_1t negative tx_pma_pre_emp_switching_ctrl_pre_tap_1t 0 tx_pma_pre_emp_sign_1st_post_tap negative tx_pma_pre_emp_switching_ctrl_1st_post_tap 0 tx_pma_slew_rate_ctrl 0 tx_pma_term_sel r_r1 tx_pma_compensation_en enable rx_pma_adapt_mode ctle_dfe rx_pma_term_sel r_r4 rx_ctle_ac_gain 0 rx_ctle_eq_gain 0 rx_vga_dc_gain 0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data1} {rcfg_debug 0 rcfg_enable 1 rcfg_jtag_enable 0 rcfg_separate_avmm_busy 0 rcfg_enable_avmm_busy_port 0 set_capability_reg_enable 0 set_user_identifier 0 set_csr_soft_logic_enable 1 support_mode user_mode channel_type GX protocol_mode basic_enh pma_mode basic duplex_mode duplex channels 1 set_data_rate 10312.5 rcfg_iface_enable 0 enable_simple_interface 1 enable_split_interface 0 set_enable_calibration 1 enable_double_rate_transfer 0 enable_background_cal_gui 1 enable_direct_reset_control 0 disable_reset_sequencer 0 disable_digital_reset_sequencer 0 bonded_mode not_bonded set_pcs_bonding_master Auto pcs_reset_sequencing_mode not_bonded manual_pcs_bonding_mode individual manual_pcs_bonding_comp_cnt 0 manual_tx_hssi_aib_bonding_mode individual manual_tx_hssi_aib_bonding_comp_cnt 0 manual_tx_core_aib_bonding_mode individual manual_tx_core_aib_bonding_comp_cnt 0 manual_rx_hssi_aib_bonding_mode individual manual_rx_hssi_aib_bonding_comp_cnt 0 manual_rx_core_aib_bonding_mode individual manual_rx_core_aib_bonding_comp_cnt 0 manual_tx_hssi_aib_indv indv_en manual_tx_core_aib_indv indv_en manual_rx_hssi_aib_indv indv_en manual_rx_core_aib_indv indv_en tx_pma_clk_div 1 plls 2 pll_select 1 enable_port_tx_pma_iqtxrx_clkout 0 enable_port_tx_pma_elecidle 0 number_physical_bonding_clocks 1 enable_qpi_mode 0 enable_qpi_async_transfer 1 enable_port_tx_pma_qpipullup 0 enable_port_tx_pma_qpipulldn 0 enable_port_tx_pma_rxfound 0 enable_port_rx_pma_qpipulldn 0 enable_port_tx_pma_txdetectrx 0 cdr_refclk_cnt 1 cdr_refclk_select 0 set_cdr_refclk_freq 644.531250 rx_ppm_detect_threshold 1000 enable_port_rx_pma_iqtxrx_clkout 0 enable_port_rx_pma_clkslip 0 enable_port_rx_is_lockedtodata 1 enable_port_rx_is_lockedtoref 1 enable_ports_rx_manual_cdr_mode 0 enable_ports_rx_prbs 0 enable_port_rx_seriallpbken 0 std_pcs_pma_width 10 std_low_latency_bypass_enable 0 enable_hip 0 enable_hard_reset 0 set_hip_cal_en 0 hip_mode disable_hip hip_prot_mode gen1 hip_channels x1 enable_ehip 0 avmm_ehip_mode disable_hip adapter_ehip_mode disable_hip std_tx_byte_ser_mode Disabled std_rx_byte_deser_mode Disabled std_tx_8b10b_enable 0 std_tx_8b10b_disp_ctrl_enable 0 std_rx_8b10b_enable 0 std_rx_rmfifo_mode disabled std_rx_rmfifo_pattern_n 0 std_rx_rmfifo_pattern_p 0 enable_port_rx_std_rmfifo_full 0 enable_port_rx_std_rmfifo_empty 0 pcie_rate_match Bypass std_tx_bitslip_enable 0 enable_port_tx_std_bitslipboundarysel 0 std_rx_word_aligner_mode bitslip std_rx_word_aligner_pattern_len 7 std_rx_word_aligner_pattern 0 std_rx_word_aligner_rknumber 3 std_rx_word_aligner_renumber 3 std_rx_word_aligner_rgnumber 3 std_rx_word_aligner_fast_sync_status_enable 0 enable_port_rx_std_wa_patternalign 0 enable_port_rx_std_wa_a1a2size 0 enable_port_rx_std_bitslipboundarysel 0 enable_port_rx_std_bitslip 0 std_tx_bitrev_enable 0 std_tx_byterev_enable 0 std_tx_polinv_enable 0 enable_port_tx_polinv 0 std_rx_bitrev_enable 0 enable_port_rx_std_bitrev_ena 0 std_rx_byterev_enable 0 enable_port_rx_std_byterev_ena 0 std_rx_polinv_enable 0 enable_port_rx_polinv 0 enable_port_rx_std_signaldetect 0 enable_ports_pipe_sw 0 enable_ports_pipe_rx_elecidle 0 enable_ports_pipe_hclk 0 enh_pcs_pma_width 64 enh_pld_pcs_width 66 enh_low_latency_enable 0 enh_advanced_user_mode 0 enh_tx_frmgen_enable 0 enh_tx_frmgen_mfrm_length 2048 enh_tx_frmgen_burst_enable 0 enable_port_tx_enh_frame 0 enable_port_tx_enh_frame_diag_status 0 enable_port_tx_enh_frame_burst_en 0 enh_rx_frmsync_enable 0 enh_rx_frmsync_mfrm_length 2048 enable_port_rx_enh_frame 0 enable_port_rx_enh_frame_lock 0 enable_port_rx_enh_frame_diag_status 0 enh_tx_crcgen_enable 0 enh_tx_crcerr_enable 0 enh_rx_crcchk_enable 0 enable_port_rx_enh_crc32_err 0 enable_port_rx_enh_highber 0 enable_port_rx_enh_highber_clr_cnt 0 enable_port_rx_enh_clr_errblk_count 0 enh_tx_64b66b_enable 0 enh_rx_64b66b_enable 0 enh_tx_sh_err 0 enh_tx_scram_enable 0 enh_tx_scram_seed 2 enh_rx_descram_enable 0 enh_tx_dispgen_enable 0 enh_rx_dispchk_enable 0 enh_tx_randomdispbit_enable 0 enh_rx_blksync_enable 0 enable_port_rx_enh_blk_lock 0 enh_tx_bitslip_enable 0 enh_tx_polinv_enable 0 enh_rx_bitslip_enable 1 enh_rx_polinv_enable 0 enable_port_tx_enh_bitslip 0 enable_port_rx_enh_bitslip 1 enh_rx_krfec_err_mark_enable 0 enh_rx_krfec_err_mark_type 10G enh_tx_krfec_burst_err_enable 0 enh_tx_krfec_burst_err_len 1 enable_port_krfec_tx_enh_frame 0 enable_port_krfec_rx_enh_frame 0 enable_port_krfec_rx_enh_frame_diag_status 0 pcs_direct_width 8 enable_tx_fast_pipeln_reg 0 enable_rx_fast_pipeln_reg 0 parallel_loopback_mode disable loopback_tx_clk_sel internal_clk enable_debug_ports 0 tx_fifo_mode {Phase compensation} tx_fifo_pfull 10 tx_fifo_pempty 2 enable_port_tx_fifo_full 0 enable_port_tx_fifo_empty 0 enable_port_tx_fifo_pfull 0 enable_port_tx_fifo_pempty 0 enable_port_tx_pcs_fifo_full 0 enable_port_tx_pcs_fifo_empty 0 enable_port_tx_dll_lock 0 rx_fifo_mode {Phase compensation} rx_fifo_pfull 10 rx_fifo_pempty 2 rx_fifo_align_del 0 rx_fifo_control_del 0 enable_port_rx_data_valid 0 enable_port_rx_fifo_full 0 enable_port_rx_fifo_empty 0 enable_port_rx_fifo_pfull 0 enable_port_rx_fifo_pempty 0 enable_port_rx_fifo_del 0 enable_port_rx_fifo_insert 0 enable_port_rx_fifo_rd_en 0 enable_port_rx_fifo_align_clr 0 enable_port_rx_pcs_fifo_full 0 enable_port_rx_pcs_fifo_empty 0 tx_clkout_sel pma_div_clkout enable_port_tx_clkout2 1 tx_clkout2_sel pcs_clkout enable_port_tx_clkout_hioint 0 enable_port_tx_clkout2_hioint 0 tx_pma_div_clkout_divider 33 tx_coreclkin_clock_network dedicated tx_pcs_bonding_clock_network dedicated rx_clkout_sel pma_div_clkout enable_port_rx_clkout2 1 rx_clkout2_sel pcs_clkout enable_port_rx_clkout_hioint 0 enable_port_rx_clkout2_hioint 0 rx_pma_div_clkout_divider 33 rx_coreclkin_clock_network dedicated osc_clk_divider 1 enable_port_tx_fifo_latency_adj_ena 0 enable_port_rx_fifo_latency_adj_ena 0 enable_port_latency_measurement 0 enable_port_clock_delay_measurement 0 delay_measurement_clkout_sel clock_delay_measurement_clkout delay_measurement_clkout2_sel clock_delay_measurement_clkout ovrd_tx_dv_mode 1 usr_tx_dv_mode enable ovrd_rx_dv_mode 1 usr_rx_dv_mode enable set_prbs_soft_logic_enable 0 enable_rcfg_tx_digitalreset_release_ctrl 0 anlg_voltage 1_1V anlg_link lr enable_ports_adaptation 0 tx_pma_analog_mode user_custom rx_pma_analog_mode user_custom tx_pma_optimal_settings 1 tx_pma_output_swing_ctrl 12 tx_pma_pre_emp_sign_pre_tap_1t negative tx_pma_pre_emp_switching_ctrl_pre_tap_1t 0 tx_pma_pre_emp_sign_1st_post_tap negative tx_pma_pre_emp_switching_ctrl_1st_post_tap 0 tx_pma_slew_rate_ctrl 0 tx_pma_term_sel r_r1 tx_pma_compensation_en enable rx_pma_adapt_mode ctle_dfe rx_pma_term_sel r_r4 rx_ctle_ac_gain 0 rx_ctle_eq_gain 0 rx_vga_dc_gain 0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data2} {}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data3} {}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data4} {}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data5} {}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data6} {}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_data7} {}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_profile_select} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_reduced_files_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data0} {enable_multi_profile 1 dbg_embedded_debug_enable 1 dbg_capability_reg_enable 0 dbg_user_identifier 0 dbg_stat_soft_logic_enable 1 dbg_ctrl_soft_logic_enable 1 l_tx_transfer_clk_hz 805664062 l_rx_transfer_clk_hz 805664062 enable_background_cal 1 l_tx_fifo_transfer_mode x2 l_rx_fifo_transfer_mode x2 l_num_tx_digitalreset 1 l_num_rx_digitalreset 1 l_enable_channel_bonding 0 l_enable_pma_bonding 0 l_enable_pcs_bonding 0 l_tx_hssi_aib_indv indv_en l_tx_core_aib_indv indv_en l_rx_hssi_aib_indv indv_en l_rx_core_aib_indv indv_en display_std_tx_pld_adapt_width 10 display_std_rx_pld_adapt_width 10 datapath_select Enhanced}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data1} {enable_multi_profile 1 dbg_embedded_debug_enable 1 dbg_capability_reg_enable 0 dbg_user_identifier 0 dbg_stat_soft_logic_enable 1 dbg_ctrl_soft_logic_enable 1 l_tx_transfer_clk_hz 322265624 l_rx_transfer_clk_hz 322265624 enable_background_cal 1 l_tx_fifo_transfer_mode x2 l_rx_fifo_transfer_mode x2 l_num_tx_digitalreset 1 l_num_rx_digitalreset 1 l_enable_channel_bonding 0 l_enable_pma_bonding 0 l_enable_pcs_bonding 0 l_tx_hssi_aib_indv indv_en l_tx_core_aib_indv indv_en l_rx_hssi_aib_indv indv_en l_rx_core_aib_indv indv_en display_std_tx_pld_adapt_width 10 display_std_rx_pld_adapt_width 10 datapath_select Enhanced}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data2} {}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data3} {}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data4} {}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data5} {}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data6} {}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sdc_derived_profile_data7} {}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_separate_avmm_busy} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_shared} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_sv_file_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_txt_file_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rcfg_use_clk_reset_only} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {reduced_reset_sim_time} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rx_clkout2_sel} {pcs_clkout}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rx_clkout_sel} {pma_div_clkout}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rx_coreclkin_clock_network} {dedicated}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rx_ctle_ac_gain} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rx_ctle_eq_gain} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rx_fifo_align_del} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rx_fifo_control_del} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rx_fifo_mode} {Phase compensation}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rx_fifo_pempty} {2}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rx_fifo_pfull} {10}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_adapt_mode} {ctle_dfe}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_adapt_start_gui} {1}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_analog_mode} {user_custom}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_div_clkout_divider} {33}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_optimal_settings} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rx_pma_term_sel} {r_r4}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rx_ppm_detect_threshold} {1000}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {rx_vga_dc_gain} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {set_capability_reg_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {set_cdr_refclk_freq} {644.531250}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {set_cdr_refclk_receiver_detect_src} {iqclk}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {set_csr_soft_logic_enable} {1}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {set_data_rate} {25781.25}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {set_embedded_debug_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {set_enable_calibration} {1}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {set_enable_eios_rx_protect} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {set_hip_cal_en} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {set_odi_soft_logic_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {set_pcs_bonding_master} {Auto}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {set_prbs_soft_logic_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {set_rcfg_emb_strm_enable} {1}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {set_user_identifier} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {std_low_latency_bypass_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {std_pcs_pma_width} {10}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_8b10b_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_bitrev_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_byte_deser_mode} {Disabled}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_byterev_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_polinv_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_rmfifo_mode} {disabled}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_rmfifo_pattern_n} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_rmfifo_pattern_p} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_fast_sync_status_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_mode} {bitslip}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_pattern} {0.0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_pattern_len} {7}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_renumber} {3}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_rgnumber} {3}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_rknumber} {3}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {std_rx_word_aligner_rvnumber} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_8b10b_disp_ctrl_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_8b10b_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_bitrev_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_bitslip_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_byte_ser_mode} {Disabled}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_byterev_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {std_tx_polinv_enable} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {support_mode} {user_mode}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {suppress_design_example_messages} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {tile_type_suffix} {}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {tx_clkout2_sel} {pcs_clkout}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {tx_clkout_sel} {pma_div_clkout}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {tx_coreclkin_clock_network} {dedicated}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {tx_fifo_mode} {Phase compensation}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {tx_fifo_pempty} {2}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {tx_fifo_pfull} {10}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pcs_bonding_clock_network} {dedicated}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pll_refclk} {644.53125}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pll_type} {ATX}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_analog_mode} {user_custom}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_clk_div} {1}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_compensation_en} {enable}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_div_clkout_divider} {33}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_optimal_settings} {1}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_output_swing_ctrl} {12}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_pre_emp_sign_1st_post_tap} {negative}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_pre_emp_sign_pre_tap_1t} {negative}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_pre_emp_switching_ctrl_1st_post_tap} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_pre_emp_switching_ctrl_pre_tap_1t} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_slew_rate_ctrl} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {tx_pma_term_sel} {r_r1}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {use_rx_clkout2} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {use_tx_clkout2} {0}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {usr_rx_dv_mode} {enable}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {usr_tx_dv_mode} {enable}
+ set_instance_parameter_value xcvr_native_s10_htile_0 {validation_rule_select} {}
+ set_instance_property xcvr_native_s10_htile_0 AUTO_EXPORT true
+
+ # add wirelevel expressions
+
+ # preserve ports for debug
+
+ # add the exports
+ set_interface_property tx_analogreset EXPORT_OF xcvr_native_s10_htile_0.tx_analogreset
+ set_interface_property rx_analogreset EXPORT_OF xcvr_native_s10_htile_0.rx_analogreset
+ set_interface_property tx_digitalreset EXPORT_OF xcvr_native_s10_htile_0.tx_digitalreset
+ set_interface_property rx_digitalreset EXPORT_OF xcvr_native_s10_htile_0.rx_digitalreset
+ set_interface_property tx_analogreset_stat EXPORT_OF xcvr_native_s10_htile_0.tx_analogreset_stat
+ set_interface_property rx_analogreset_stat EXPORT_OF xcvr_native_s10_htile_0.rx_analogreset_stat
+ set_interface_property tx_digitalreset_stat EXPORT_OF xcvr_native_s10_htile_0.tx_digitalreset_stat
+ set_interface_property rx_digitalreset_stat EXPORT_OF xcvr_native_s10_htile_0.rx_digitalreset_stat
+ set_interface_property tx_cal_busy EXPORT_OF xcvr_native_s10_htile_0.tx_cal_busy
+ set_interface_property rx_cal_busy EXPORT_OF xcvr_native_s10_htile_0.rx_cal_busy
+ set_interface_property tx_serial_clk0 EXPORT_OF xcvr_native_s10_htile_0.tx_serial_clk0
+ set_interface_property tx_serial_clk1 EXPORT_OF xcvr_native_s10_htile_0.tx_serial_clk1
+ set_interface_property rx_cdr_refclk0 EXPORT_OF xcvr_native_s10_htile_0.rx_cdr_refclk0
+ set_interface_property tx_serial_data EXPORT_OF xcvr_native_s10_htile_0.tx_serial_data
+ set_interface_property rx_serial_data EXPORT_OF xcvr_native_s10_htile_0.rx_serial_data
+ set_interface_property rx_is_lockedtoref EXPORT_OF xcvr_native_s10_htile_0.rx_is_lockedtoref
+ set_interface_property rx_is_lockedtodata EXPORT_OF xcvr_native_s10_htile_0.rx_is_lockedtodata
+ set_interface_property tx_coreclkin EXPORT_OF xcvr_native_s10_htile_0.tx_coreclkin
+ set_interface_property rx_coreclkin EXPORT_OF xcvr_native_s10_htile_0.rx_coreclkin
+ set_interface_property tx_clkout EXPORT_OF xcvr_native_s10_htile_0.tx_clkout
+ set_interface_property tx_clkout2 EXPORT_OF xcvr_native_s10_htile_0.tx_clkout2
+ set_interface_property rx_clkout EXPORT_OF xcvr_native_s10_htile_0.rx_clkout
+ set_interface_property rx_clkout2 EXPORT_OF xcvr_native_s10_htile_0.rx_clkout2
+ set_interface_property tx_parallel_data EXPORT_OF xcvr_native_s10_htile_0.tx_parallel_data
+ set_interface_property tx_control EXPORT_OF xcvr_native_s10_htile_0.tx_control
+ set_interface_property tx_enh_data_valid EXPORT_OF xcvr_native_s10_htile_0.tx_enh_data_valid
+ set_interface_property unused_tx_parallel_data EXPORT_OF xcvr_native_s10_htile_0.unused_tx_parallel_data
+ set_interface_property rx_parallel_data EXPORT_OF xcvr_native_s10_htile_0.rx_parallel_data
+ set_interface_property rx_control EXPORT_OF xcvr_native_s10_htile_0.rx_control
+ set_interface_property rx_enh_data_valid EXPORT_OF xcvr_native_s10_htile_0.rx_enh_data_valid
+ set_interface_property unused_rx_parallel_data EXPORT_OF xcvr_native_s10_htile_0.unused_rx_parallel_data
+ set_interface_property rx_bitslip EXPORT_OF xcvr_native_s10_htile_0.rx_bitslip
+ set_interface_property reconfig_clk EXPORT_OF xcvr_native_s10_htile_0.reconfig_clk
+ set_interface_property reconfig_reset EXPORT_OF xcvr_native_s10_htile_0.reconfig_reset
+ set_interface_property reconfig_avmm EXPORT_OF xcvr_native_s10_htile_0.reconfig_avmm
+
+ # set values for exposed HDL parameters
+
+ # set the the module properties
+ set_module_property BONUS_DATA {
+
+
+
+
+
+}
+ set_module_property FILE {eth_xcvr_gxt.ip}
+ set_module_property GENERATION_ID {0x00000000}
+ set_module_property NAME {eth_xcvr_gxt}
+
+ # save the system
+ sync_sysinfo_parameters
+ save_system eth_xcvr_gxt
+}
+
+proc do_set_exported_interface_sysinfo_parameters {} {
+}
+
+# create all the systems, from bottom up
+do_create_eth_xcvr_gxt
+
+# set system info parameters on exported interface, from bottom up
+do_set_exported_interface_sysinfo_parameters
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/ip/eth_xcvr_pll.tcl b/fpga/mqnic/S10MX_DK/fpga_25g/ip/eth_xcvr_gxt_buf.tcl
similarity index 92%
rename from fpga/mqnic/S10MX_DK/fpga_10g/ip/eth_xcvr_pll.tcl
rename to fpga/mqnic/S10MX_DK/fpga_25g/ip/eth_xcvr_gxt_buf.tcl
index 93d7851a4..3fc1cb81a 100644
--- a/fpga/mqnic/S10MX_DK/fpga_10g/ip/eth_xcvr_pll.tcl
+++ b/fpga/mqnic/S10MX_DK/fpga_25g/ip/eth_xcvr_gxt_buf.tcl
@@ -1,9 +1,9 @@
-package require -exact qsys 20.4
+package require -exact qsys 21.3
-# create the system "eth_xcvr_pll"
-proc do_create_eth_xcvr_pll {} {
+# create the system "eth_xcvr_gxt_buf"
+proc do_create_eth_xcvr_gxt_buf {} {
# create the system
- create_system eth_xcvr_pll
+ create_system eth_xcvr_gxt_buf
set_project_property DEVICE {1SM21CHU1F53E1VG}
set_project_property DEVICE_FAMILY {Stratix 10}
set_project_property HIDE_FROM_IP_CATALOG {true}
@@ -16,12 +16,12 @@ proc do_create_eth_xcvr_pll {} {
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {base_device} {Unknown}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {bw_sel} {high}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_input_frm_abv_atx} {0}
- set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_input_frm_blw_atx} {0}
- set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_local_atx_path} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_input_frm_blw_atx} {1}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_local_atx_path} {1}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_output_frm_abv_atx} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_output_frm_blw_atx} {0}
- set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_8G_path} {1}
- set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_GXT_clock_source} {disabled}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_8G_path} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_GXT_clock_source} {atx_blw}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_GXT_out_buffer_abv} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_GXT_out_buffer_blw} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_analog_resets} {0}
@@ -47,7 +47,7 @@ proc do_create_eth_xcvr_pll {} {
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {mcgb_div} {1}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {message_level} {error}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {pma_width} {64}
- set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {primary_pll_buffer} {GX clock output buffer}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {primary_pll_buffer} {GXT clock output buffer}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {prot_mode} {Basic}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_debug} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_enable} {0}
@@ -94,7 +94,7 @@ proc do_create_eth_xcvr_pll {} {
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_l_counter} {4}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_m_counter} {24}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_manual_reference_clock_frequency} {200.0}
- set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_output_clock_frequency} {5156.25}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_output_clock_frequency} {12890.625}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_rcfg_emb_strm_enable} {0}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_ref_clk_div} {1}
set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_user_identifier} {0}
@@ -106,9 +106,12 @@ proc do_create_eth_xcvr_pll {} {
# add wirelevel expressions
+ # preserve ports for debug
+
# add the exports
set_interface_property pll_refclk0 EXPORT_OF xcvr_atx_pll_s10_htile_0.pll_refclk0
- set_interface_property tx_serial_clk EXPORT_OF xcvr_atx_pll_s10_htile_0.tx_serial_clk
+ set_interface_property tx_serial_clk_gxt EXPORT_OF xcvr_atx_pll_s10_htile_0.tx_serial_clk_gxt
+ set_interface_property gxt_input_from_blw_atx EXPORT_OF xcvr_atx_pll_s10_htile_0.gxt_input_from_blw_atx
set_interface_property pll_locked EXPORT_OF xcvr_atx_pll_s10_htile_0.pll_locked
set_interface_property pll_cal_busy EXPORT_OF xcvr_atx_pll_s10_htile_0.pll_cal_busy
@@ -122,20 +125,20 @@ proc do_create_eth_xcvr_pll {} {
}
- set_module_property FILE {eth_xcvr_pll.ip}
+ set_module_property FILE {eth_xcvr_gxt_buf.ip}
set_module_property GENERATION_ID {0x00000000}
- set_module_property NAME {eth_xcvr_pll}
+ set_module_property NAME {eth_xcvr_gxt_buf}
# save the system
sync_sysinfo_parameters
- save_system eth_xcvr_pll
+ save_system eth_xcvr_gxt_buf
}
proc do_set_exported_interface_sysinfo_parameters {} {
}
# create all the systems, from bottom up
-do_create_eth_xcvr_pll
+do_create_eth_xcvr_gxt_buf
# set system info parameters on exported interface, from bottom up
do_set_exported_interface_sysinfo_parameters
diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/ip/eth_xcvr_gxt_pll.tcl b/fpga/mqnic/S10MX_DK/fpga_25g/ip/eth_xcvr_gxt_pll.tcl
new file mode 100644
index 000000000..80adc35ec
--- /dev/null
+++ b/fpga/mqnic/S10MX_DK/fpga_25g/ip/eth_xcvr_gxt_pll.tcl
@@ -0,0 +1,144 @@
+package require -exact qsys 21.3
+
+# create the system "eth_xcvr_gxt_pll"
+proc do_create_eth_xcvr_gxt_pll {} {
+ # create the system
+ create_system eth_xcvr_gxt_pll
+ set_project_property DEVICE {1SM21CHU1F53E1VG}
+ set_project_property DEVICE_FAMILY {Stratix 10}
+ set_project_property HIDE_FROM_IP_CATALOG {true}
+ set_use_testbench_naming_pattern 0 {}
+
+ # add HDL parameters
+
+ # add the components
+ add_instance xcvr_atx_pll_s10_htile_0 altera_xcvr_atx_pll_s10_htile
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {base_device} {Unknown}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {bw_sel} {high}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_input_frm_abv_atx} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_input_frm_blw_atx} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_local_atx_path} {1}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_output_frm_abv_atx} {1}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_28G_output_frm_blw_atx} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_8G_path} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_GXT_clock_source} {atx_lcl}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_GXT_out_buffer_abv} {1}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_GXT_out_buffer_blw} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_analog_resets} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_bonding_clks} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_cascade_out} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_debug_ports_parameters} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_ext_lockdetect_ports} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_fb_comp_bonding} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_hfreq_clk} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_hip_cal_done_port} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_manual_configuration} {1}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_mcgb} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_mcgb_pcie_clksw} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_mcgb_reset} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_pcie_clk} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_pcie_hip_connectivity} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_pld_atx_cal_busy_port} {1}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_pld_mcgb_cal_busy_port} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_pll_lock} {1}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {enable_vco_bypass} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {generate_add_hdl_instance_example} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {mcgb_aux_clkin_cnt} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {mcgb_div} {1}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {message_level} {error}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {pma_width} {64}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {primary_pll_buffer} {GXT clock output buffer}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {prot_mode} {Basic}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_debug} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_enable} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_enable_avmm_busy_port} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_file_prefix} {altera_xcvr_atx_pll_s10}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_files_as_common_package} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_h_file_enable} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_jtag_enable} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_mif_file_enable} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_multi_enable} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_cnt} {2}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data0} {}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data1} {}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data2} {}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data3} {}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data4} {}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data5} {}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data6} {}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_data7} {}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_profile_select} {1}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_reduced_files_enable} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data0} {}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data1} {}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data2} {}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data3} {}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data4} {}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data5} {}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data6} {}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sdc_derived_profile_data7} {}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_separate_avmm_busy} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_sv_file_enable} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {rcfg_txt_file_enable} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {refclk_cnt} {1}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {refclk_index} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_altera_xcvr_atx_pll_s10_calibration_en} {1}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_auto_reference_clock_frequency} {644.53125}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_capability_reg_enable} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_csr_soft_logic_enable} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_fref_clock_frequency} {156.25}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_hip_cal_en} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_k_counter} {1.0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_l_cascade_counter} {4}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_l_cascade_predivider} {1}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_l_counter} {4}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_m_counter} {24}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_manual_reference_clock_frequency} {200.0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_output_clock_frequency} {12890.625}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_rcfg_emb_strm_enable} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_ref_clk_div} {1}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {set_user_identifier} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {silicon_rev} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {support_mode} {user_mode}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {test_mode} {0}
+ set_instance_parameter_value xcvr_atx_pll_s10_htile_0 {usr_analog_voltage} {1_1V}
+ set_instance_property xcvr_atx_pll_s10_htile_0 AUTO_EXPORT true
+
+ # add wirelevel expressions
+
+ # preserve ports for debug
+
+ # add the exports
+ set_interface_property pll_refclk0 EXPORT_OF xcvr_atx_pll_s10_htile_0.pll_refclk0
+ set_interface_property tx_serial_clk_gxt EXPORT_OF xcvr_atx_pll_s10_htile_0.tx_serial_clk_gxt
+ set_interface_property gxt_output_to_abv_atx EXPORT_OF xcvr_atx_pll_s10_htile_0.gxt_output_to_abv_atx
+ set_interface_property pll_locked EXPORT_OF xcvr_atx_pll_s10_htile_0.pll_locked
+ set_interface_property pll_cal_busy EXPORT_OF xcvr_atx_pll_s10_htile_0.pll_cal_busy
+
+ # set values for exposed HDL parameters
+
+ # set the the module properties
+ set_module_property BONUS_DATA {
+
+
+
+
+
+}
+ set_module_property FILE {eth_xcvr_gxt_pll.ip}
+ set_module_property GENERATION_ID {0x00000000}
+ set_module_property NAME {eth_xcvr_gxt_pll}
+
+ # save the system
+ sync_sysinfo_parameters
+ save_system eth_xcvr_gxt_pll
+}
+
+proc do_set_exported_interface_sysinfo_parameters {} {
+}
+
+# create all the systems, from bottom up
+do_create_eth_xcvr_gxt_pll
+
+# set system info parameters on exported interface, from bottom up
+do_set_exported_interface_sysinfo_parameters
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/ip/eth_xcvr_reset.tcl b/fpga/mqnic/S10MX_DK/fpga_25g/ip/eth_xcvr_reset.tcl
similarity index 99%
rename from fpga/mqnic/S10MX_DK/fpga_10g/ip/eth_xcvr_reset.tcl
rename to fpga/mqnic/S10MX_DK/fpga_25g/ip/eth_xcvr_reset.tcl
index b33562c45..f8319e637 100644
--- a/fpga/mqnic/S10MX_DK/fpga_10g/ip/eth_xcvr_reset.tcl
+++ b/fpga/mqnic/S10MX_DK/fpga_25g/ip/eth_xcvr_reset.tcl
@@ -13,7 +13,7 @@ proc do_create_eth_xcvr_reset {} {
# add the components
add_instance xcvr_reset_control_s10_0 altera_xcvr_reset_control_s10
- set_instance_parameter_value xcvr_reset_control_s10_0 {CHANNELS} {4}
+ set_instance_parameter_value xcvr_reset_control_s10_0 {CHANNELS} {1}
set_instance_parameter_value xcvr_reset_control_s10_0 {ENABLE_DIGITAL_SEQ} {0}
set_instance_parameter_value xcvr_reset_control_s10_0 {PLLS} {1}
set_instance_parameter_value xcvr_reset_control_s10_0 {REDUCED_SIM_TIME} {1}
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/ip/pcie.tcl b/fpga/mqnic/S10MX_DK/fpga_25g/ip/pcie.tcl
similarity index 100%
rename from fpga/mqnic/S10MX_DK/fpga_10g/ip/pcie.tcl
rename to fpga/mqnic/S10MX_DK/fpga_25g/ip/pcie.tcl
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/ip/ref_div.tcl b/fpga/mqnic/S10MX_DK/fpga_25g/ip/ref_div.tcl
similarity index 100%
rename from fpga/mqnic/S10MX_DK/fpga_10g/ip/ref_div.tcl
rename to fpga/mqnic/S10MX_DK/fpga_25g/ip/ref_div.tcl
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/ip/reset_release.tcl b/fpga/mqnic/S10MX_DK/fpga_25g/ip/reset_release.tcl
similarity index 100%
rename from fpga/mqnic/S10MX_DK/fpga_10g/ip/reset_release.tcl
rename to fpga/mqnic/S10MX_DK/fpga_25g/ip/reset_release.tcl
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/lib b/fpga/mqnic/S10MX_DK/fpga_25g/lib
similarity index 100%
rename from fpga/mqnic/S10MX_DK/fpga_10g/lib
rename to fpga/mqnic/S10MX_DK/fpga_25g/lib
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/rtl/common b/fpga/mqnic/S10MX_DK/fpga_25g/rtl/common
similarity index 100%
rename from fpga/mqnic/S10MX_DK/fpga_10g/rtl/common
rename to fpga/mqnic/S10MX_DK/fpga_25g/rtl/common
diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v b/fpga/mqnic/S10MX_DK/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v
new file mode 100644
index 000000000..3c04cac10
--- /dev/null
+++ b/fpga/mqnic/S10MX_DK/fpga_25g/rtl/eth_xcvr_phy_quad_wrapper.v
@@ -0,0 +1,386 @@
+/*
+
+Copyright 2021, The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
+IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
+CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+
+The views and conclusions contained in the software and documentation are those
+of the authors and should not be interpreted as representing official policies,
+either expressed or implied, of The Regents of the University of California.
+
+*/
+
+// Language: Verilog 2001
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * Transceiver and PHY quad wrapper
+ */
+module eth_xcvr_phy_quad_wrapper #
+(
+ parameter GXT = 0,
+
+ // PHY parameters
+ parameter DATA_WIDTH = 64,
+ parameter CTRL_WIDTH = (DATA_WIDTH/8),
+ parameter HDR_WIDTH = 2,
+ parameter PRBS31_ENABLE = 0,
+ parameter TX_SERDES_PIPELINE = 0,
+ parameter RX_SERDES_PIPELINE = 0,
+ parameter BITSLIP_HIGH_CYCLES = 32,
+ parameter BITSLIP_LOW_CYCLES = 32,
+ parameter COUNT_125US = 125000/6.4
+)
+(
+ input wire xcvr_ctrl_clk,
+ input wire xcvr_ctrl_rst,
+
+ /*
+ * Common
+ */
+ input wire xcvr_ref_clk,
+
+ /*
+ * Serial data
+ */
+ output wire [3:0] xcvr_tx_serial_data,
+ input wire [3:0] xcvr_rx_serial_data,
+
+ /*
+ * PHY connections
+ */
+ output wire phy_1_tx_clk,
+ output wire phy_1_tx_rst,
+ input wire [DATA_WIDTH-1:0] phy_1_xgmii_txd,
+ input wire [CTRL_WIDTH-1:0] phy_1_xgmii_txc,
+ output wire phy_1_rx_clk,
+ output wire phy_1_rx_rst,
+ output wire [DATA_WIDTH-1:0] phy_1_xgmii_rxd,
+ output wire [CTRL_WIDTH-1:0] phy_1_xgmii_rxc,
+ output wire phy_1_tx_bad_block,
+ output wire [6:0] phy_1_rx_error_count,
+ output wire phy_1_rx_bad_block,
+ output wire phy_1_rx_sequence_error,
+ output wire phy_1_rx_block_lock,
+ output wire phy_1_rx_high_ber,
+ output wire phy_1_rx_status,
+ input wire phy_1_tx_prbs31_enable,
+ input wire phy_1_rx_prbs31_enable,
+
+ output wire phy_2_tx_clk,
+ output wire phy_2_tx_rst,
+ input wire [DATA_WIDTH-1:0] phy_2_xgmii_txd,
+ input wire [CTRL_WIDTH-1:0] phy_2_xgmii_txc,
+ output wire phy_2_rx_clk,
+ output wire phy_2_rx_rst,
+ output wire [DATA_WIDTH-1:0] phy_2_xgmii_rxd,
+ output wire [CTRL_WIDTH-1:0] phy_2_xgmii_rxc,
+ output wire phy_2_tx_bad_block,
+ output wire [6:0] phy_2_rx_error_count,
+ output wire phy_2_rx_bad_block,
+ output wire phy_2_rx_sequence_error,
+ output wire phy_2_rx_block_lock,
+ output wire phy_2_rx_high_ber,
+ output wire phy_2_rx_status,
+ input wire phy_2_tx_prbs31_enable,
+ input wire phy_2_rx_prbs31_enable,
+
+ output wire phy_3_tx_clk,
+ output wire phy_3_tx_rst,
+ input wire [DATA_WIDTH-1:0] phy_3_xgmii_txd,
+ input wire [CTRL_WIDTH-1:0] phy_3_xgmii_txc,
+ output wire phy_3_rx_clk,
+ output wire phy_3_rx_rst,
+ output wire [DATA_WIDTH-1:0] phy_3_xgmii_rxd,
+ output wire [CTRL_WIDTH-1:0] phy_3_xgmii_rxc,
+ output wire phy_3_tx_bad_block,
+ output wire [6:0] phy_3_rx_error_count,
+ output wire phy_3_rx_bad_block,
+ output wire phy_3_rx_sequence_error,
+ output wire phy_3_rx_block_lock,
+ output wire phy_3_rx_high_ber,
+ output wire phy_3_rx_status,
+ input wire phy_3_tx_prbs31_enable,
+ input wire phy_3_rx_prbs31_enable,
+
+ output wire phy_4_tx_clk,
+ output wire phy_4_tx_rst,
+ input wire [DATA_WIDTH-1:0] phy_4_xgmii_txd,
+ input wire [CTRL_WIDTH-1:0] phy_4_xgmii_txc,
+ output wire phy_4_rx_clk,
+ output wire phy_4_rx_rst,
+ output wire [DATA_WIDTH-1:0] phy_4_xgmii_rxd,
+ output wire [CTRL_WIDTH-1:0] phy_4_xgmii_rxc,
+ output wire phy_4_tx_bad_block,
+ output wire [6:0] phy_4_rx_error_count,
+ output wire phy_4_rx_bad_block,
+ output wire phy_4_rx_sequence_error,
+ output wire phy_4_rx_block_lock,
+ output wire phy_4_rx_high_ber,
+ output wire phy_4_rx_status,
+ input wire phy_4_tx_prbs31_enable,
+ input wire phy_4_rx_prbs31_enable
+);
+
+wire xcvr_gx_pll_locked;
+wire xcvr_gx_pll_cal_busy;
+wire xcvr_gxt_pll_locked;
+wire xcvr_gxt_pll_cal_busy;
+
+wire xcvr_tx_serial_gx_clk;
+wire [1:0] xcvr_tx_serial_gxt_clk;
+
+eth_xcvr_gx_pll eth_xcvr_gx_pll_inst (
+ .pll_refclk0 (xcvr_ref_clk),
+ .tx_serial_clk (xcvr_tx_serial_gx_clk),
+ .pll_locked (xcvr_gx_pll_locked),
+ .pll_cal_busy (xcvr_gx_pll_cal_busy)
+);
+
+generate
+
+if (GXT) begin
+
+ wire atx_pll_cascade_clk;
+
+ eth_xcvr_gxt_pll eth_xcvr_gxt_pll_inst (
+ .pll_refclk0 (xcvr_ref_clk),
+ .tx_serial_clk_gxt (xcvr_tx_serial_gxt_clk[0]),
+ .gxt_output_to_abv_atx (atx_pll_cascade_clk),
+ .pll_locked (xcvr_gxt_pll_locked),
+ .pll_cal_busy (xcvr_gxt_pll_cal_busy)
+ );
+
+ eth_xcvr_gxt_buf eth_xcvr_gxt_buf_inst (
+ .pll_refclk0 (xcvr_ref_clk),
+ .tx_serial_clk_gxt (xcvr_tx_serial_gxt_clk[1]),
+ .gxt_input_from_blw_atx (atx_pll_cascade_clk),
+ .pll_locked (),
+ .pll_cal_busy ()
+ );
+
+end else begin
+
+ assign xcvr_tx_serial_gxt_clk = 2'b00;
+ assign xcvr_gxt_pll_locked = 1'b1;
+ assign xcvr_gxt_pll_cal_busy = 1'b0;
+
+end
+
+endgenerate
+
+eth_xcvr_phy_wrapper #(
+ .GXT(GXT),
+ .DATA_WIDTH(DATA_WIDTH),
+ .CTRL_WIDTH(CTRL_WIDTH),
+ .HDR_WIDTH(HDR_WIDTH),
+ .PRBS31_ENABLE(PRBS31_ENABLE),
+ .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
+ .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
+ .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
+ .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
+ .COUNT_125US(COUNT_125US)
+)
+eth_xcvr_phy_1 (
+ .xcvr_ctrl_clk(xcvr_ctrl_clk),
+ .xcvr_ctrl_rst(xcvr_ctrl_rst),
+
+ // Transceiver connections
+ .xcvr_gx_pll_locked(xcvr_gx_pll_locked),
+ .xcvr_gxt_pll_locked(xcvr_gxt_pll_locked),
+ .xcvr_gx_pll_cal_busy(xcvr_gx_pll_cal_busy),
+ .xcvr_gxt_pll_cal_busy(xcvr_gxt_pll_cal_busy),
+ .xcvr_tx_serial_gx_clk(xcvr_tx_serial_gx_clk),
+ .xcvr_tx_serial_gxt_clk(xcvr_tx_serial_gxt_clk[0]),
+ .xcvr_rx_cdr_refclk(xcvr_ref_clk),
+ .xcvr_tx_serial_data(xcvr_tx_serial_data[0]),
+ .xcvr_rx_serial_data(xcvr_rx_serial_data[0]),
+
+ // PHY connections
+ .phy_tx_clk(phy_1_tx_clk),
+ .phy_tx_rst(phy_1_tx_rst),
+ .phy_xgmii_txd(phy_1_xgmii_txd),
+ .phy_xgmii_txc(phy_1_xgmii_txc),
+ .phy_rx_clk(phy_1_rx_clk),
+ .phy_rx_rst(phy_1_rx_rst),
+ .phy_xgmii_rxd(phy_1_xgmii_rxd),
+ .phy_xgmii_rxc(phy_1_xgmii_rxc),
+ .phy_tx_bad_block(phy_1_tx_bad_block),
+ .phy_rx_error_count(phy_1_rx_error_count),
+ .phy_rx_bad_block(phy_1_rx_bad_block),
+ .phy_rx_sequence_error(phy_1_rx_sequence_error),
+ .phy_rx_block_lock(phy_1_rx_block_lock),
+ .phy_rx_high_ber(phy_1_rx_high_ber),
+ .phy_rx_status(phy_1_rx_status),
+ .phy_tx_prbs31_enable(phy_1_tx_prbs31_enable),
+ .phy_rx_prbs31_enable(phy_1_rx_prbs31_enable)
+);
+
+eth_xcvr_phy_wrapper #(
+ .GXT(GXT),
+ .DATA_WIDTH(DATA_WIDTH),
+ .CTRL_WIDTH(CTRL_WIDTH),
+ .HDR_WIDTH(HDR_WIDTH),
+ .PRBS31_ENABLE(PRBS31_ENABLE),
+ .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
+ .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
+ .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
+ .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
+ .COUNT_125US(COUNT_125US)
+)
+eth_xcvr_phy_2 (
+ .xcvr_ctrl_clk(xcvr_ctrl_clk),
+ .xcvr_ctrl_rst(xcvr_ctrl_rst),
+
+ // Transceiver connections
+ .xcvr_gx_pll_locked(xcvr_gx_pll_locked),
+ .xcvr_gxt_pll_locked(xcvr_gxt_pll_locked),
+ .xcvr_gx_pll_cal_busy(xcvr_gx_pll_cal_busy),
+ .xcvr_gxt_pll_cal_busy(xcvr_gxt_pll_cal_busy),
+ .xcvr_tx_serial_gx_clk(xcvr_tx_serial_gx_clk),
+ .xcvr_tx_serial_gxt_clk(xcvr_tx_serial_gxt_clk[0]),
+ .xcvr_rx_cdr_refclk(xcvr_ref_clk),
+ .xcvr_tx_serial_data(xcvr_tx_serial_data[1]),
+ .xcvr_rx_serial_data(xcvr_rx_serial_data[1]),
+
+ // PHY connections
+ .phy_tx_clk(phy_2_tx_clk),
+ .phy_tx_rst(phy_2_tx_rst),
+ .phy_xgmii_txd(phy_2_xgmii_txd),
+ .phy_xgmii_txc(phy_2_xgmii_txc),
+ .phy_rx_clk(phy_2_rx_clk),
+ .phy_rx_rst(phy_2_rx_rst),
+ .phy_xgmii_rxd(phy_2_xgmii_rxd),
+ .phy_xgmii_rxc(phy_2_xgmii_rxc),
+ .phy_tx_bad_block(phy_2_tx_bad_block),
+ .phy_rx_error_count(phy_2_rx_error_count),
+ .phy_rx_bad_block(phy_2_rx_bad_block),
+ .phy_rx_sequence_error(phy_2_rx_sequence_error),
+ .phy_rx_block_lock(phy_2_rx_block_lock),
+ .phy_rx_high_ber(phy_2_rx_high_ber),
+ .phy_rx_status(phy_2_rx_status),
+ .phy_tx_prbs31_enable(phy_2_tx_prbs31_enable),
+ .phy_rx_prbs31_enable(phy_2_rx_prbs31_enable)
+);
+
+eth_xcvr_phy_wrapper #(
+ .GXT(GXT),
+ .DATA_WIDTH(DATA_WIDTH),
+ .CTRL_WIDTH(CTRL_WIDTH),
+ .HDR_WIDTH(HDR_WIDTH),
+ .PRBS31_ENABLE(PRBS31_ENABLE),
+ .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
+ .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
+ .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
+ .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
+ .COUNT_125US(COUNT_125US)
+)
+eth_xcvr_phy_3 (
+ .xcvr_ctrl_clk(xcvr_ctrl_clk),
+ .xcvr_ctrl_rst(xcvr_ctrl_rst),
+
+ // Transceiver connections
+ .xcvr_gx_pll_locked(xcvr_gx_pll_locked),
+ .xcvr_gxt_pll_locked(xcvr_gxt_pll_locked),
+ .xcvr_gx_pll_cal_busy(xcvr_gx_pll_cal_busy),
+ .xcvr_gxt_pll_cal_busy(xcvr_gxt_pll_cal_busy),
+ .xcvr_tx_serial_gx_clk(xcvr_tx_serial_gx_clk),
+ .xcvr_tx_serial_gxt_clk(xcvr_tx_serial_gxt_clk[1]),
+ .xcvr_rx_cdr_refclk(xcvr_ref_clk),
+ .xcvr_tx_serial_data(xcvr_tx_serial_data[2]),
+ .xcvr_rx_serial_data(xcvr_rx_serial_data[2]),
+
+ // PHY connections
+ .phy_tx_clk(phy_3_tx_clk),
+ .phy_tx_rst(phy_3_tx_rst),
+ .phy_xgmii_txd(phy_3_xgmii_txd),
+ .phy_xgmii_txc(phy_3_xgmii_txc),
+ .phy_rx_clk(phy_3_rx_clk),
+ .phy_rx_rst(phy_3_rx_rst),
+ .phy_xgmii_rxd(phy_3_xgmii_rxd),
+ .phy_xgmii_rxc(phy_3_xgmii_rxc),
+ .phy_tx_bad_block(phy_3_tx_bad_block),
+ .phy_rx_error_count(phy_3_rx_error_count),
+ .phy_rx_bad_block(phy_3_rx_bad_block),
+ .phy_rx_sequence_error(phy_3_rx_sequence_error),
+ .phy_rx_block_lock(phy_3_rx_block_lock),
+ .phy_rx_high_ber(phy_3_rx_high_ber),
+ .phy_rx_status(phy_3_rx_status),
+ .phy_tx_prbs31_enable(phy_3_tx_prbs31_enable),
+ .phy_rx_prbs31_enable(phy_3_rx_prbs31_enable)
+);
+
+eth_xcvr_phy_wrapper #(
+ .GXT(GXT),
+ .DATA_WIDTH(DATA_WIDTH),
+ .CTRL_WIDTH(CTRL_WIDTH),
+ .HDR_WIDTH(HDR_WIDTH),
+ .PRBS31_ENABLE(PRBS31_ENABLE),
+ .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
+ .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
+ .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
+ .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
+ .COUNT_125US(COUNT_125US)
+)
+eth_xcvr_phy_4 (
+ .xcvr_ctrl_clk(xcvr_ctrl_clk),
+ .xcvr_ctrl_rst(xcvr_ctrl_rst),
+
+ // Transceiver connections
+ .xcvr_gx_pll_locked(xcvr_gx_pll_locked),
+ .xcvr_gxt_pll_locked(xcvr_gxt_pll_locked),
+ .xcvr_gx_pll_cal_busy(xcvr_gx_pll_cal_busy),
+ .xcvr_gxt_pll_cal_busy(xcvr_gxt_pll_cal_busy),
+ .xcvr_tx_serial_gx_clk(xcvr_tx_serial_gx_clk),
+ .xcvr_tx_serial_gxt_clk(xcvr_tx_serial_gxt_clk[1]),
+ .xcvr_rx_cdr_refclk(xcvr_ref_clk),
+ .xcvr_tx_serial_data(xcvr_tx_serial_data[3]),
+ .xcvr_rx_serial_data(xcvr_rx_serial_data[3]),
+
+ // PHY connections
+ .phy_tx_clk(phy_4_tx_clk),
+ .phy_tx_rst(phy_4_tx_rst),
+ .phy_xgmii_txd(phy_4_xgmii_txd),
+ .phy_xgmii_txc(phy_4_xgmii_txc),
+ .phy_rx_clk(phy_4_rx_clk),
+ .phy_rx_rst(phy_4_rx_rst),
+ .phy_xgmii_rxd(phy_4_xgmii_rxd),
+ .phy_xgmii_rxc(phy_4_xgmii_rxc),
+ .phy_tx_bad_block(phy_4_tx_bad_block),
+ .phy_rx_error_count(phy_4_rx_error_count),
+ .phy_rx_bad_block(phy_4_rx_bad_block),
+ .phy_rx_sequence_error(phy_4_rx_sequence_error),
+ .phy_rx_block_lock(phy_4_rx_block_lock),
+ .phy_rx_high_ber(phy_4_rx_high_ber),
+ .phy_rx_status(phy_4_rx_status),
+ .phy_tx_prbs31_enable(phy_4_tx_prbs31_enable),
+ .phy_rx_prbs31_enable(phy_4_rx_prbs31_enable)
+);
+
+endmodule
+
+`resetall
diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/rtl/eth_xcvr_phy_wrapper.v b/fpga/mqnic/S10MX_DK/fpga_25g/rtl/eth_xcvr_phy_wrapper.v
new file mode 100644
index 000000000..675acd98b
--- /dev/null
+++ b/fpga/mqnic/S10MX_DK/fpga_25g/rtl/eth_xcvr_phy_wrapper.v
@@ -0,0 +1,330 @@
+/*
+
+Copyright 2021, The Regents of the University of California.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+ 1. Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ 2. Redistributions in binary form must reproduce the above copyright notice,
+ this list of conditions and the following disclaimer in the documentation
+ and/or other materials provided with the distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS
+IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR
+CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+OF SUCH DAMAGE.
+
+The views and conclusions contained in the software and documentation are those
+of the authors and should not be interpreted as representing official policies,
+either expressed or implied, of The Regents of the University of California.
+
+*/
+
+// Language: Verilog 2001
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * Transceiver and PHY wrapper
+ */
+module eth_xcvr_phy_wrapper #
+(
+ parameter GXT = 0,
+
+ // PHY parameters
+ parameter DATA_WIDTH = 64,
+ parameter CTRL_WIDTH = (DATA_WIDTH/8),
+ parameter HDR_WIDTH = 2,
+ parameter PRBS31_ENABLE = 0,
+ parameter TX_SERDES_PIPELINE = 0,
+ parameter RX_SERDES_PIPELINE = 0,
+ parameter BITSLIP_HIGH_CYCLES = 32,
+ parameter BITSLIP_LOW_CYCLES = 32,
+ parameter COUNT_125US = 125000/6.4
+)
+(
+ input wire xcvr_ctrl_clk,
+ input wire xcvr_ctrl_rst,
+
+ /*
+ * Transceiver connections
+ */
+ input wire xcvr_gx_pll_locked,
+ input wire xcvr_gxt_pll_locked,
+ input wire xcvr_gx_pll_cal_busy,
+ input wire xcvr_gxt_pll_cal_busy,
+ input wire xcvr_tx_serial_gx_clk,
+ input wire xcvr_tx_serial_gxt_clk,
+ input wire xcvr_rx_cdr_refclk,
+ output wire xcvr_tx_serial_data,
+ input wire xcvr_rx_serial_data,
+
+ /*
+ * PHY connections
+ */
+ output wire phy_tx_clk,
+ output wire phy_tx_rst,
+ input wire [DATA_WIDTH-1:0] phy_xgmii_txd,
+ input wire [CTRL_WIDTH-1:0] phy_xgmii_txc,
+ output wire phy_rx_clk,
+ output wire phy_rx_rst,
+ output wire [DATA_WIDTH-1:0] phy_xgmii_rxd,
+ output wire [CTRL_WIDTH-1:0] phy_xgmii_rxc,
+ output wire phy_tx_bad_block,
+ output wire [6:0] phy_rx_error_count,
+ output wire phy_rx_bad_block,
+ output wire phy_rx_sequence_error,
+ output wire phy_rx_block_lock,
+ output wire phy_rx_high_ber,
+ output wire phy_rx_status,
+ input wire phy_tx_prbs31_enable,
+ input wire phy_rx_prbs31_enable
+);
+
+wire xcvr_tx_analogreset;
+wire xcvr_rx_analogreset;
+wire xcvr_tx_digitalreset;
+wire xcvr_rx_digitalreset;
+wire xcvr_tx_analogreset_stat;
+wire xcvr_rx_analogreset_stat;
+wire xcvr_tx_digitalreset_stat;
+wire xcvr_rx_digitalreset_stat;
+wire xcvr_tx_cal_busy;
+wire xcvr_rx_cal_busy;
+wire xcvr_rx_is_lockedtoref;
+wire xcvr_rx_is_lockedtodata;
+wire xcvr_tx_ready;
+wire xcvr_rx_ready;
+
+wire xcvr_tx_clk;
+wire xcvr_rx_clk;
+
+assign phy_tx_clk = xcvr_tx_clk;
+assign phy_rx_clk = xcvr_rx_clk;
+
+wire [1:0] xcvr_tx_hdr;
+wire [DATA_WIDTH-1:0] xcvr_tx_data;
+wire [1:0] xcvr_rx_hdr;
+wire [DATA_WIDTH-1:0] xcvr_rx_data;
+
+wire [1:0] phy_tx_hdr;
+wire [DATA_WIDTH-1:0] phy_tx_data;
+wire [1:0] phy_rx_hdr;
+wire [DATA_WIDTH-1:0] phy_rx_data;
+
+assign {xcvr_tx_hdr, xcvr_tx_data} = {phy_tx_data, phy_tx_hdr};
+assign {phy_rx_data, phy_rx_hdr} = {xcvr_rx_hdr, xcvr_rx_data};
+
+wire xcvr_rx_bitslip;
+
+wire phy_rx_reset_req;
+wire phy_rx_reset_req_sync;
+
+sync_reset #(
+ .N(4)
+)
+phy_rx_rst_req_reset_sync_inst (
+ .clk(xcvr_ctrl_clk),
+ .rst(phy_rx_reset_req),
+ .out(phy_rx_reset_req_sync)
+);
+
+eth_xcvr_reset eth_xcvr_reset_inst (
+ .clock (xcvr_ctrl_clk),
+ .reset (xcvr_ctrl_rst),
+ .tx_analogreset (xcvr_tx_analogreset),
+ .tx_digitalreset (xcvr_tx_digitalreset),
+ .tx_ready (xcvr_tx_ready),
+ .pll_locked (xcvr_gx_pll_locked && (GXT || xcvr_gxt_pll_locked)),
+ .pll_select (1'b0),
+ .tx_cal_busy (xcvr_tx_cal_busy),
+ .tx_analogreset_stat (xcvr_tx_analogreset_stat),
+ .tx_digitalreset_stat (xcvr_tx_digitalreset_stat),
+ .pll_cal_busy (xcvr_gx_pll_cal_busy || (GXT && xcvr_gxt_pll_cal_busy)),
+ .rx_analogreset (xcvr_rx_analogreset),
+ .rx_digitalreset (xcvr_rx_digitalreset),
+ .rx_ready (xcvr_rx_ready),
+ .rx_is_lockedtodata (xcvr_rx_is_lockedtodata),
+ .rx_cal_busy (xcvr_rx_cal_busy || phy_rx_reset_req_sync),
+ .rx_analogreset_stat (xcvr_rx_analogreset_stat),
+ .rx_digitalreset_stat (xcvr_rx_digitalreset_stat)
+);
+
+generate
+
+if (GXT) begin
+
+ eth_xcvr_gxt eth_xcvr_inst (
+ .tx_analogreset (xcvr_tx_analogreset),
+ .rx_analogreset (xcvr_rx_analogreset),
+ .tx_digitalreset (xcvr_tx_digitalreset),
+ .rx_digitalreset (xcvr_rx_digitalreset),
+ .tx_analogreset_stat (xcvr_tx_analogreset_stat),
+ .rx_analogreset_stat (xcvr_rx_analogreset_stat),
+ .tx_digitalreset_stat (xcvr_tx_digitalreset_stat),
+ .rx_digitalreset_stat (xcvr_rx_digitalreset_stat),
+ .tx_cal_busy (xcvr_tx_cal_busy),
+ .rx_cal_busy (xcvr_rx_cal_busy),
+ .tx_serial_clk0 (xcvr_tx_serial_gxt_clk),
+ .tx_serial_clk1 (xcvr_tx_serial_gx_clk),
+ .rx_cdr_refclk0 (xcvr_rx_cdr_refclk),
+ .tx_serial_data (xcvr_tx_serial_data),
+ .rx_serial_data (xcvr_rx_serial_data),
+ .rx_is_lockedtoref (xcvr_rx_is_lockedtoref),
+ .rx_is_lockedtodata (xcvr_rx_is_lockedtodata),
+ .tx_coreclkin (xcvr_tx_clk),
+ .rx_coreclkin (xcvr_rx_clk),
+ .tx_clkout (xcvr_tx_clk),
+ .tx_clkout2 (),
+ .rx_clkout (xcvr_rx_clk),
+ .rx_clkout2 (),
+ .tx_parallel_data (xcvr_tx_data),
+ .tx_control (xcvr_tx_hdr),
+ .tx_enh_data_valid (1'b1),
+ .unused_tx_parallel_data (13'd0),
+ .rx_parallel_data (xcvr_rx_data),
+ .rx_control (xcvr_rx_hdr),
+ .rx_enh_data_valid (),
+ .unused_rx_parallel_data (),
+ .rx_bitslip (xcvr_rx_bitslip),
+ .reconfig_clk (xcvr_ctrl_clk),
+ .reconfig_reset (xcvr_ctrl_rst),
+ .reconfig_write (1'b0),
+ .reconfig_read (1'b0),
+ .reconfig_address (11'd0),
+ .reconfig_writedata (32'd0),
+ .reconfig_readdata (),
+ .reconfig_waitrequest ()
+ );
+
+end else begin
+
+ eth_xcvr_gx eth_xcvr_inst (
+ .tx_analogreset (xcvr_tx_analogreset),
+ .rx_analogreset (xcvr_rx_analogreset),
+ .tx_digitalreset (xcvr_tx_digitalreset),
+ .rx_digitalreset (xcvr_rx_digitalreset),
+ .tx_analogreset_stat (xcvr_tx_analogreset_stat),
+ .rx_analogreset_stat (xcvr_rx_analogreset_stat),
+ .tx_digitalreset_stat (xcvr_tx_digitalreset_stat),
+ .rx_digitalreset_stat (xcvr_rx_digitalreset_stat),
+ .tx_cal_busy (xcvr_tx_cal_busy),
+ .rx_cal_busy (xcvr_rx_cal_busy),
+ .tx_serial_clk0 (xcvr_tx_serial_gx_clk),
+ .rx_cdr_refclk0 (xcvr_rx_cdr_refclk),
+ .tx_serial_data (xcvr_tx_serial_data),
+ .rx_serial_data (xcvr_rx_serial_data),
+ .rx_is_lockedtoref (xcvr_rx_is_lockedtoref),
+ .rx_is_lockedtodata (xcvr_rx_is_lockedtodata),
+ .tx_coreclkin (xcvr_tx_clk),
+ .rx_coreclkin (xcvr_rx_clk),
+ .tx_clkout (xcvr_tx_clk),
+ .tx_clkout2 (),
+ .rx_clkout (xcvr_rx_clk),
+ .rx_clkout2 (),
+ .tx_parallel_data (xcvr_tx_data),
+ .tx_control (xcvr_tx_hdr),
+ .tx_enh_data_valid (1'b1),
+ .unused_tx_parallel_data (13'd0),
+ .rx_parallel_data (xcvr_rx_data),
+ .rx_control (xcvr_rx_hdr),
+ .rx_enh_data_valid (),
+ .unused_rx_parallel_data (),
+ .rx_bitslip (xcvr_rx_bitslip)
+ );
+
+end
+
+endgenerate
+
+wire phy_tx_rst_int;
+reg phy_tx_rst_reg = 1'b0;
+
+sync_reset #(
+ .N(4)
+)
+phy_tx_rst_reset_sync_inst (
+ .clk(phy_tx_clk),
+ .rst(~xcvr_tx_ready),
+ .out(phy_tx_rst_int)
+);
+
+always @(posedge phy_tx_clk) begin
+ phy_tx_rst_reg <= phy_tx_rst_int;
+end
+
+assign phy_tx_rst = phy_tx_rst_reg;
+
+wire phy_rx_rst_int;
+reg phy_rx_rst_reg = 1'b0;
+
+sync_reset #(
+ .N(4)
+)
+phy_rx_rst_reset_sync_inst (
+ .clk(phy_rx_clk),
+ .rst(~xcvr_rx_ready),
+ .out(phy_rx_rst_int)
+);
+
+always @(posedge phy_rx_clk) begin
+ phy_rx_rst_reg <= phy_rx_rst_int;
+end
+
+assign phy_rx_rst = phy_rx_rst_reg;
+
+eth_phy_10g #(
+ .DATA_WIDTH(DATA_WIDTH),
+ .CTRL_WIDTH(CTRL_WIDTH),
+ .HDR_WIDTH(HDR_WIDTH),
+ .BIT_REVERSE(0),
+ .SCRAMBLER_DISABLE(0),
+ .PRBS31_ENABLE(PRBS31_ENABLE),
+ .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
+ .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
+ .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
+ .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
+ .COUNT_125US(COUNT_125US)
+)
+phy_inst (
+ .tx_clk(phy_tx_clk),
+ .tx_rst(phy_tx_rst),
+ .rx_clk(phy_rx_clk),
+ .rx_rst(phy_rx_rst),
+ .xgmii_txd(phy_xgmii_txd),
+ .xgmii_txc(phy_xgmii_txc),
+ .xgmii_rxd(phy_xgmii_rxd),
+ .xgmii_rxc(phy_xgmii_rxc),
+ .serdes_tx_data(phy_tx_data),
+ .serdes_tx_hdr(phy_tx_hdr),
+ .serdes_rx_data(phy_rx_data),
+ .serdes_rx_hdr(phy_rx_hdr),
+ .serdes_rx_bitslip(xcvr_rx_bitslip),
+ .serdes_rx_reset_req(phy_rx_reset_req),
+ .tx_bad_block(phy_tx_bad_block),
+ .rx_error_count(phy_rx_error_count),
+ .rx_bad_block(phy_rx_bad_block),
+ .rx_sequence_error(phy_rx_sequence_error),
+ .rx_block_lock(phy_rx_block_lock),
+ .rx_high_ber(phy_rx_high_ber),
+ .rx_status(phy_rx_status),
+ .tx_prbs31_enable(phy_tx_prbs31_enable),
+ .rx_prbs31_enable(phy_rx_prbs31_enable)
+);
+
+endmodule
+
+`resetall
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/rtl/fpga.v b/fpga/mqnic/S10MX_DK/fpga_25g/rtl/fpga.v
similarity index 93%
rename from fpga/mqnic/S10MX_DK/fpga_10g/rtl/fpga.v
rename to fpga/mqnic/S10MX_DK/fpga_25g/rtl/fpga.v
index 87a415fc8..eaceaf2e0 100644
--- a/fpga/mqnic/S10MX_DK/fpga_10g/rtl/fpga.v
+++ b/fpga/mqnic/S10MX_DK/fpga_25g/rtl/fpga.v
@@ -52,6 +52,9 @@ module fpga #
parameter GIT_HASH = 32'hdce357bf,
parameter RELEASE_INFO = 32'h00000000,
+ // Board configuration
+ parameter TDMA_BER_ENABLE = 0,
+
// Structural configuration
parameter IF_COUNT = 2,
parameter PORTS_PER_IF = 1,
@@ -150,11 +153,13 @@ module fpga #
parameter AXIL_APP_CTRL_ADDR_WIDTH = 24,
// Ethernet interface configuration
+ parameter AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE = 1,
parameter AXIS_ETH_TX_PIPELINE = 0,
parameter AXIS_ETH_TX_FIFO_PIPELINE = 2,
parameter AXIS_ETH_TX_TS_PIPELINE = 0,
parameter AXIS_ETH_RX_PIPELINE = 0,
parameter AXIS_ETH_RX_FIFO_PIPELINE = 2,
+ parameter ETH_XCVR_GXT = 1,
// Statistics counter subsystem
parameter STAT_ENABLE = 1,
@@ -224,7 +229,7 @@ parameter XGMII_DATA_WIDTH = 64;
parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8;
parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH;
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8;
-parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH;
+parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*(AXIS_ETH_SYNC_DATA_WIDTH_DOUBLE ? 2 : 1);
parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1;
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1;
@@ -673,13 +678,25 @@ wire qsfp0_rx_status_3;
wire qsfp0_rx_block_lock_4;
wire qsfp0_rx_status_4;
-eth_xcvr_phy_quad_wrapper qsfp0_eth_xcvr_phy_quad (
+eth_xcvr_phy_quad_wrapper #(
+ .GXT(ETH_XCVR_GXT),
+ .DATA_WIDTH(XGMII_DATA_WIDTH),
+ .CTRL_WIDTH(XGMII_CTRL_WIDTH),
+ .PRBS31_ENABLE(1),
+ .TX_SERDES_PIPELINE(1),
+ .RX_SERDES_PIPELINE(1),
+ .COUNT_125US(125000/2.56)
+)
+qsfp0_eth_xcvr_phy_quad (
.xcvr_ctrl_clk(clk_100mhz),
.xcvr_ctrl_rst(rst_100mhz),
.xcvr_ref_clk(refclk_qsfp0_p),
.xcvr_tx_serial_data(qsfp0_tx_p),
.xcvr_rx_serial_data(qsfp0_rx_p),
+ /*
+ * PHY connections
+ */
.phy_1_tx_clk(qsfp0_tx_clk_1_int),
.phy_1_tx_rst(qsfp0_tx_rst_1_int),
.phy_1_xgmii_txd(qsfp0_txd_1_int),
@@ -688,9 +705,16 @@ eth_xcvr_phy_quad_wrapper qsfp0_eth_xcvr_phy_quad (
.phy_1_rx_rst(qsfp0_rx_rst_1_int),
.phy_1_xgmii_rxd(qsfp0_rxd_1_int),
.phy_1_xgmii_rxc(qsfp0_rxc_1_int),
+ .phy_1_tx_bad_block(),
+ .phy_1_rx_error_count(qsfp0_rx_error_count_1_int),
+ .phy_1_rx_bad_block(),
+ .phy_1_rx_sequence_error(),
.phy_1_rx_block_lock(qsfp0_rx_block_lock_1),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp0_rx_status_1),
+ .phy_1_tx_prbs31_enable(qsfp0_tx_prbs31_enable_1_int),
+ .phy_1_rx_prbs31_enable(qsfp0_rx_prbs31_enable_1_int),
+
.phy_2_tx_clk(qsfp0_tx_clk_2_int),
.phy_2_tx_rst(qsfp0_tx_rst_2_int),
.phy_2_xgmii_txd(qsfp0_txd_2_int),
@@ -699,9 +723,16 @@ eth_xcvr_phy_quad_wrapper qsfp0_eth_xcvr_phy_quad (
.phy_2_rx_rst(qsfp0_rx_rst_2_int),
.phy_2_xgmii_rxd(qsfp0_rxd_2_int),
.phy_2_xgmii_rxc(qsfp0_rxc_2_int),
+ .phy_2_tx_bad_block(),
+ .phy_2_rx_error_count(qsfp0_rx_error_count_2_int),
+ .phy_2_rx_bad_block(),
+ .phy_2_rx_sequence_error(),
.phy_2_rx_block_lock(qsfp0_rx_block_lock_2),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp0_rx_status_2),
+ .phy_2_tx_prbs31_enable(qsfp0_tx_prbs31_enable_2_int),
+ .phy_2_rx_prbs31_enable(qsfp0_rx_prbs31_enable_2_int),
+
.phy_3_tx_clk(qsfp0_tx_clk_3_int),
.phy_3_tx_rst(qsfp0_tx_rst_3_int),
.phy_3_xgmii_txd(qsfp0_txd_3_int),
@@ -710,9 +741,16 @@ eth_xcvr_phy_quad_wrapper qsfp0_eth_xcvr_phy_quad (
.phy_3_rx_rst(qsfp0_rx_rst_3_int),
.phy_3_xgmii_rxd(qsfp0_rxd_3_int),
.phy_3_xgmii_rxc(qsfp0_rxc_3_int),
+ .phy_3_tx_bad_block(),
+ .phy_3_rx_error_count(qsfp0_rx_error_count_3_int),
+ .phy_3_rx_bad_block(),
+ .phy_3_rx_sequence_error(),
.phy_3_rx_block_lock(qsfp0_rx_block_lock_3),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp0_rx_status_3),
+ .phy_3_tx_prbs31_enable(qsfp0_tx_prbs31_enable_3_int),
+ .phy_3_rx_prbs31_enable(qsfp0_rx_prbs31_enable_3_int),
+
.phy_4_tx_clk(qsfp0_tx_clk_4_int),
.phy_4_tx_rst(qsfp0_tx_rst_4_int),
.phy_4_xgmii_txd(qsfp0_txd_4_int),
@@ -721,9 +759,15 @@ eth_xcvr_phy_quad_wrapper qsfp0_eth_xcvr_phy_quad (
.phy_4_rx_rst(qsfp0_rx_rst_4_int),
.phy_4_xgmii_rxd(qsfp0_rxd_4_int),
.phy_4_xgmii_rxc(qsfp0_rxc_4_int),
+ .phy_4_tx_bad_block(),
+ .phy_4_rx_error_count(qsfp0_rx_error_count_4_int),
+ .phy_4_rx_bad_block(),
+ .phy_4_rx_sequence_error(),
.phy_4_rx_block_lock(qsfp0_rx_block_lock_4),
.phy_4_rx_high_ber(),
- .phy_4_rx_status(qsfp0_rx_status_4)
+ .phy_4_rx_status(qsfp0_rx_status_4),
+ .phy_4_tx_prbs31_enable(qsfp0_tx_prbs31_enable_4_int),
+ .phy_4_rx_prbs31_enable(qsfp0_rx_prbs31_enable_4_int)
);
// QSFP1
@@ -785,13 +829,25 @@ wire qsfp1_rx_status_3;
wire qsfp1_rx_block_lock_4;
wire qsfp1_rx_status_4;
-eth_xcvr_phy_quad_wrapper qsfp1_eth_xcvr_phy_quad (
+eth_xcvr_phy_quad_wrapper #(
+ .GXT(ETH_XCVR_GXT),
+ .DATA_WIDTH(XGMII_DATA_WIDTH),
+ .CTRL_WIDTH(XGMII_CTRL_WIDTH),
+ .PRBS31_ENABLE(1),
+ .TX_SERDES_PIPELINE(1),
+ .RX_SERDES_PIPELINE(1),
+ .COUNT_125US(125000/2.56)
+)
+qsfp1_eth_xcvr_phy_quad (
.xcvr_ctrl_clk(clk_100mhz),
.xcvr_ctrl_rst(rst_100mhz),
.xcvr_ref_clk(refclk_qsfp1_p),
.xcvr_tx_serial_data(qsfp1_tx_p),
.xcvr_rx_serial_data(qsfp1_rx_p),
+ /*
+ * PHY connections
+ */
.phy_1_tx_clk(qsfp1_tx_clk_1_int),
.phy_1_tx_rst(qsfp1_tx_rst_1_int),
.phy_1_xgmii_txd(qsfp1_txd_1_int),
@@ -800,9 +856,16 @@ eth_xcvr_phy_quad_wrapper qsfp1_eth_xcvr_phy_quad (
.phy_1_rx_rst(qsfp1_rx_rst_1_int),
.phy_1_xgmii_rxd(qsfp1_rxd_1_int),
.phy_1_xgmii_rxc(qsfp1_rxc_1_int),
+ .phy_1_tx_bad_block(),
+ .phy_1_rx_error_count(qsfp1_rx_error_count_1_int),
+ .phy_1_rx_bad_block(),
+ .phy_1_rx_sequence_error(),
.phy_1_rx_block_lock(qsfp1_rx_block_lock_1),
.phy_1_rx_high_ber(),
.phy_1_rx_status(qsfp1_rx_status_1),
+ .phy_1_tx_prbs31_enable(qsfp1_tx_prbs31_enable_1_int),
+ .phy_1_rx_prbs31_enable(qsfp1_rx_prbs31_enable_1_int),
+
.phy_2_tx_clk(qsfp1_tx_clk_2_int),
.phy_2_tx_rst(qsfp1_tx_rst_2_int),
.phy_2_xgmii_txd(qsfp1_txd_2_int),
@@ -811,9 +874,16 @@ eth_xcvr_phy_quad_wrapper qsfp1_eth_xcvr_phy_quad (
.phy_2_rx_rst(qsfp1_rx_rst_2_int),
.phy_2_xgmii_rxd(qsfp1_rxd_2_int),
.phy_2_xgmii_rxc(qsfp1_rxc_2_int),
+ .phy_2_tx_bad_block(),
+ .phy_2_rx_error_count(qsfp1_rx_error_count_2_int),
+ .phy_2_rx_bad_block(),
+ .phy_2_rx_sequence_error(),
.phy_2_rx_block_lock(qsfp1_rx_block_lock_2),
.phy_2_rx_high_ber(),
.phy_2_rx_status(qsfp1_rx_status_2),
+ .phy_2_tx_prbs31_enable(qsfp1_tx_prbs31_enable_2_int),
+ .phy_2_rx_prbs31_enable(qsfp1_rx_prbs31_enable_2_int),
+
.phy_3_tx_clk(qsfp1_tx_clk_3_int),
.phy_3_tx_rst(qsfp1_tx_rst_3_int),
.phy_3_xgmii_txd(qsfp1_txd_3_int),
@@ -822,9 +892,16 @@ eth_xcvr_phy_quad_wrapper qsfp1_eth_xcvr_phy_quad (
.phy_3_rx_rst(qsfp1_rx_rst_3_int),
.phy_3_xgmii_rxd(qsfp1_rxd_3_int),
.phy_3_xgmii_rxc(qsfp1_rxc_3_int),
+ .phy_3_tx_bad_block(),
+ .phy_3_rx_error_count(qsfp1_rx_error_count_3_int),
+ .phy_3_rx_bad_block(),
+ .phy_3_rx_sequence_error(),
.phy_3_rx_block_lock(qsfp1_rx_block_lock_3),
.phy_3_rx_high_ber(),
.phy_3_rx_status(qsfp1_rx_status_3),
+ .phy_3_tx_prbs31_enable(qsfp1_tx_prbs31_enable_3_int),
+ .phy_3_rx_prbs31_enable(qsfp1_rx_prbs31_enable_3_int),
+
.phy_4_tx_clk(qsfp1_tx_clk_4_int),
.phy_4_tx_rst(qsfp1_tx_rst_4_int),
.phy_4_xgmii_txd(qsfp1_txd_4_int),
@@ -833,9 +910,15 @@ eth_xcvr_phy_quad_wrapper qsfp1_eth_xcvr_phy_quad (
.phy_4_rx_rst(qsfp1_rx_rst_4_int),
.phy_4_xgmii_rxd(qsfp1_rxd_4_int),
.phy_4_xgmii_rxc(qsfp1_rxc_4_int),
+ .phy_4_tx_bad_block(),
+ .phy_4_rx_error_count(qsfp1_rx_error_count_4_int),
+ .phy_4_rx_bad_block(),
+ .phy_4_rx_sequence_error(),
.phy_4_rx_block_lock(qsfp1_rx_block_lock_4),
.phy_4_rx_high_ber(),
- .phy_4_rx_status(qsfp1_rx_status_4)
+ .phy_4_rx_status(qsfp1_rx_status_4),
+ .phy_4_tx_prbs31_enable(qsfp1_tx_prbs31_enable_4_int),
+ .phy_4_rx_prbs31_enable(qsfp1_rx_prbs31_enable_4_int)
);
wire ptp_clk;
@@ -871,6 +954,9 @@ fpga_core #(
.GIT_HASH(GIT_HASH),
.RELEASE_INFO(RELEASE_INFO),
+ // Board configuration
+ .TDMA_BER_ENABLE(TDMA_BER_ENABLE),
+
// Structural configuration
.IF_COUNT(IF_COUNT),
.PORTS_PER_IF(PORTS_PER_IF),
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/rtl/fpga_core.v b/fpga/mqnic/S10MX_DK/fpga_25g/rtl/fpga_core.v
similarity index 92%
rename from fpga/mqnic/S10MX_DK/fpga_10g/rtl/fpga_core.v
rename to fpga/mqnic/S10MX_DK/fpga_25g/rtl/fpga_core.v
index 7f9af9465..50f1b2a5b 100644
--- a/fpga/mqnic/S10MX_DK/fpga_10g/rtl/fpga_core.v
+++ b/fpga/mqnic/S10MX_DK/fpga_25g/rtl/fpga_core.v
@@ -52,6 +52,9 @@ module fpga_core #
parameter GIT_HASH = 32'hdce357bf,
parameter RELEASE_INFO = 32'h00000000,
+ // Board configuration
+ parameter TDMA_BER_ENABLE = 0,
+
// Structural configuration
parameter IF_COUNT = 2,
parameter PORTS_PER_IF = 1,
@@ -164,7 +167,7 @@ module fpga_core #
parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8,
parameter AXIS_ETH_DATA_WIDTH = XGMII_DATA_WIDTH,
parameter AXIS_ETH_KEEP_WIDTH = AXIS_ETH_DATA_WIDTH/8,
- parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH,
+ parameter AXIS_ETH_SYNC_DATA_WIDTH = AXIS_ETH_DATA_WIDTH*2,
parameter AXIS_ETH_TX_USER_WIDTH = TX_TAG_WIDTH + 1,
parameter AXIS_ETH_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1,
parameter AXIS_ETH_TX_PIPELINE = 0,
@@ -583,53 +586,81 @@ always @(posedge clk_250mhz) begin
end
end
-// // BER tester
-// tdma_ber #(
-// .COUNT(8),
-// .INDEX_WIDTH(6),
-// .SLICE_WIDTH(5),
-// .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
-// .AXIL_ADDR_WIDTH(8+6+$clog2(8)),
-// .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH),
-// .SCHEDULE_START_S(0),
-// .SCHEDULE_START_NS(0),
-// .SCHEDULE_PERIOD_S(0),
-// .SCHEDULE_PERIOD_NS(1000000),
-// .TIMESLOT_PERIOD_S(0),
-// .TIMESLOT_PERIOD_NS(100000),
-// .ACTIVE_PERIOD_S(0),
-// .ACTIVE_PERIOD_NS(90000)
-// )
-// tdma_ber_inst (
-// .clk(clk_250mhz),
-// .rst(rst_250mhz),
-// .phy_tx_clk({qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1, qsfp0_tx_clk_4, qsfp0_tx_clk_3, qsfp0_tx_clk_2, qsfp0_tx_clk_1}),
-// .phy_rx_clk({qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}),
-// .phy_rx_error_count({qsfp1_rx_error_count_4, qsfp1_rx_error_count_3, qsfp1_rx_error_count_2, qsfp1_rx_error_count_1, qsfp0_rx_error_count_4, qsfp0_rx_error_count_3, qsfp0_rx_error_count_2, qsfp0_rx_error_count_1}),
-// .phy_tx_prbs31_enable({qsfp1_tx_prbs31_enable_4, qsfp1_tx_prbs31_enable_3, qsfp1_tx_prbs31_enable_2, qsfp1_tx_prbs31_enable_1, qsfp0_tx_prbs31_enable_4, qsfp0_tx_prbs31_enable_3, qsfp0_tx_prbs31_enable_2, qsfp0_tx_prbs31_enable_1}),
-// .phy_rx_prbs31_enable({qsfp1_rx_prbs31_enable_4, qsfp1_rx_prbs31_enable_3, qsfp1_rx_prbs31_enable_2, qsfp1_rx_prbs31_enable_1, qsfp0_rx_prbs31_enable_4, qsfp0_rx_prbs31_enable_3, qsfp0_rx_prbs31_enable_2, qsfp0_rx_prbs31_enable_1}),
-// .s_axil_awaddr(axil_csr_awaddr),
-// .s_axil_awprot(axil_csr_awprot),
-// .s_axil_awvalid(axil_csr_awvalid),
-// .s_axil_awready(axil_csr_awready),
-// .s_axil_wdata(axil_csr_wdata),
-// .s_axil_wstrb(axil_csr_wstrb),
-// .s_axil_wvalid(axil_csr_wvalid),
-// .s_axil_wready(axil_csr_wready),
-// .s_axil_bresp(axil_csr_bresp),
-// .s_axil_bvalid(axil_csr_bvalid),
-// .s_axil_bready(axil_csr_bready),
-// .s_axil_araddr(axil_csr_araddr),
-// .s_axil_arprot(axil_csr_arprot),
-// .s_axil_arvalid(axil_csr_arvalid),
-// .s_axil_arready(axil_csr_arready),
-// .s_axil_rdata(axil_csr_rdata),
-// .s_axil_rresp(axil_csr_rresp),
-// .s_axil_rvalid(axil_csr_rvalid),
-// .s_axil_rready(axil_csr_rready),
-// .ptp_ts_96(ptp_ts_96),
-// .ptp_ts_step(ptp_ts_step)
-// );
+generate
+
+if (TDMA_BER_ENABLE) begin
+
+ // BER tester
+ tdma_ber #(
+ .COUNT(8),
+ .INDEX_WIDTH(6),
+ .SLICE_WIDTH(5),
+ .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH),
+ .AXIL_ADDR_WIDTH(8+6+$clog2(8)),
+ .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH),
+ .SCHEDULE_START_S(0),
+ .SCHEDULE_START_NS(0),
+ .SCHEDULE_PERIOD_S(0),
+ .SCHEDULE_PERIOD_NS(1000000),
+ .TIMESLOT_PERIOD_S(0),
+ .TIMESLOT_PERIOD_NS(100000),
+ .ACTIVE_PERIOD_S(0),
+ .ACTIVE_PERIOD_NS(90000),
+ .PHY_PIPELINE(2)
+ )
+ tdma_ber_inst (
+ .clk(clk_250mhz),
+ .rst(rst_250mhz),
+ .phy_tx_clk({qsfp1_tx_clk_4, qsfp1_tx_clk_3, qsfp1_tx_clk_2, qsfp1_tx_clk_1, qsfp0_tx_clk_4, qsfp0_tx_clk_3, qsfp0_tx_clk_2, qsfp0_tx_clk_1}),
+ .phy_rx_clk({qsfp1_rx_clk_4, qsfp1_rx_clk_3, qsfp1_rx_clk_2, qsfp1_rx_clk_1, qsfp0_rx_clk_4, qsfp0_rx_clk_3, qsfp0_rx_clk_2, qsfp0_rx_clk_1}),
+ .phy_rx_error_count({qsfp1_rx_error_count_4, qsfp1_rx_error_count_3, qsfp1_rx_error_count_2, qsfp1_rx_error_count_1, qsfp0_rx_error_count_4, qsfp0_rx_error_count_3, qsfp0_rx_error_count_2, qsfp0_rx_error_count_1}),
+ .phy_tx_prbs31_enable({qsfp1_tx_prbs31_enable_4, qsfp1_tx_prbs31_enable_3, qsfp1_tx_prbs31_enable_2, qsfp1_tx_prbs31_enable_1, qsfp0_tx_prbs31_enable_4, qsfp0_tx_prbs31_enable_3, qsfp0_tx_prbs31_enable_2, qsfp0_tx_prbs31_enable_1}),
+ .phy_rx_prbs31_enable({qsfp1_rx_prbs31_enable_4, qsfp1_rx_prbs31_enable_3, qsfp1_rx_prbs31_enable_2, qsfp1_rx_prbs31_enable_1, qsfp0_rx_prbs31_enable_4, qsfp0_rx_prbs31_enable_3, qsfp0_rx_prbs31_enable_2, qsfp0_rx_prbs31_enable_1}),
+ .s_axil_awaddr(axil_csr_awaddr),
+ .s_axil_awprot(axil_csr_awprot),
+ .s_axil_awvalid(axil_csr_awvalid),
+ .s_axil_awready(axil_csr_awready),
+ .s_axil_wdata(axil_csr_wdata),
+ .s_axil_wstrb(axil_csr_wstrb),
+ .s_axil_wvalid(axil_csr_wvalid),
+ .s_axil_wready(axil_csr_wready),
+ .s_axil_bresp(axil_csr_bresp),
+ .s_axil_bvalid(axil_csr_bvalid),
+ .s_axil_bready(axil_csr_bready),
+ .s_axil_araddr(axil_csr_araddr),
+ .s_axil_arprot(axil_csr_arprot),
+ .s_axil_arvalid(axil_csr_arvalid),
+ .s_axil_arready(axil_csr_arready),
+ .s_axil_rdata(axil_csr_rdata),
+ .s_axil_rresp(axil_csr_rresp),
+ .s_axil_rvalid(axil_csr_rvalid),
+ .s_axil_rready(axil_csr_rready),
+ .ptp_ts_96(ptp_sync_ts_96),
+ .ptp_ts_step(ptp_sync_ts_step)
+ );
+
+end else begin
+
+ assign qsfp0_tx_prbs31_enable_1 = 1'b0;
+ assign qsfp0_rx_prbs31_enable_1 = 1'b0;
+ assign qsfp0_tx_prbs31_enable_2 = 1'b0;
+ assign qsfp0_rx_prbs31_enable_2 = 1'b0;
+ assign qsfp0_tx_prbs31_enable_3 = 1'b0;
+ assign qsfp0_rx_prbs31_enable_3 = 1'b0;
+ assign qsfp0_tx_prbs31_enable_4 = 1'b0;
+ assign qsfp0_rx_prbs31_enable_4 = 1'b0;
+ assign qsfp1_tx_prbs31_enable_1 = 1'b0;
+ assign qsfp1_rx_prbs31_enable_1 = 1'b0;
+ assign qsfp1_tx_prbs31_enable_2 = 1'b0;
+ assign qsfp1_rx_prbs31_enable_2 = 1'b0;
+ assign qsfp1_tx_prbs31_enable_3 = 1'b0;
+ assign qsfp1_rx_prbs31_enable_3 = 1'b0;
+ assign qsfp1_tx_prbs31_enable_4 = 1'b0;
+ assign qsfp1_rx_prbs31_enable_4 = 1'b0;
+
+end
+
+endgenerate
assign user_led[0] = 1'b0;
assign user_led[1] = 1'b0;
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/rtl/sync_signal.v b/fpga/mqnic/S10MX_DK/fpga_25g/rtl/sync_signal.v
similarity index 100%
rename from fpga/mqnic/S10MX_DK/fpga_10g/rtl/sync_signal.v
rename to fpga/mqnic/S10MX_DK/fpga_25g/rtl/sync_signal.v
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/Makefile b/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/Makefile
similarity index 100%
rename from fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/Makefile
rename to fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/Makefile
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/mqnic.py b/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/mqnic.py
similarity index 100%
rename from fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/mqnic.py
rename to fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/mqnic.py
diff --git a/fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py
similarity index 96%
rename from fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py
rename to fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py
index 6bfb7dd58..c8ba37edb 100644
--- a/fpga/mqnic/S10MX_DK/fpga_10g/tb/fpga_core/test_fpga_core.py
+++ b/fpga/mqnic/S10MX_DK/fpga_25g/tb/fpga_core/test_fpga_core.py
@@ -77,8 +77,8 @@ class TB(object):
self.dev = S10PcieDevice(
# configuration options
pcie_generation=3,
- # pcie_link_width=8,
- # pld_clk_frequency=250e6,
+ pcie_link_width=8,
+ pld_clk_frequency=250e6,
l_tile=False,
pf_count=1,
max_payload_size=1024,
@@ -229,44 +229,44 @@ class TB(object):
cocotb.start_soon(Clock(dut.ptp_sample_clk, 8, units="ns").start())
# Ethernet
- cocotb.start_soon(Clock(dut.qsfp0_rx_clk_1, 6.4, units="ns").start())
+ cocotb.start_soon(Clock(dut.qsfp0_rx_clk_1, 2.56, units="ns").start())
self.qsfp0_1_source = XgmiiSource(dut.qsfp0_rxd_1, dut.qsfp0_rxc_1, dut.qsfp0_rx_clk_1, dut.qsfp0_rx_rst_1)
- cocotb.start_soon(Clock(dut.qsfp0_tx_clk_1, 6.4, units="ns").start())
+ cocotb.start_soon(Clock(dut.qsfp0_tx_clk_1, 2.56, units="ns").start())
self.qsfp0_1_sink = XgmiiSink(dut.qsfp0_txd_1, dut.qsfp0_txc_1, dut.qsfp0_tx_clk_1, dut.qsfp0_tx_rst_1)
- cocotb.start_soon(Clock(dut.qsfp0_rx_clk_2, 6.4, units="ns").start())
+ cocotb.start_soon(Clock(dut.qsfp0_rx_clk_2, 2.56, units="ns").start())
self.qsfp0_2_source = XgmiiSource(dut.qsfp0_rxd_2, dut.qsfp0_rxc_2, dut.qsfp0_rx_clk_2, dut.qsfp0_rx_rst_2)
- cocotb.start_soon(Clock(dut.qsfp0_tx_clk_2, 6.4, units="ns").start())
+ cocotb.start_soon(Clock(dut.qsfp0_tx_clk_2, 2.56, units="ns").start())
self.qsfp0_2_sink = XgmiiSink(dut.qsfp0_txd_2, dut.qsfp0_txc_2, dut.qsfp0_tx_clk_2, dut.qsfp0_tx_rst_2)
- cocotb.start_soon(Clock(dut.qsfp0_rx_clk_3, 6.4, units="ns").start())
+ cocotb.start_soon(Clock(dut.qsfp0_rx_clk_3, 2.56, units="ns").start())
self.qsfp0_3_source = XgmiiSource(dut.qsfp0_rxd_3, dut.qsfp0_rxc_3, dut.qsfp0_rx_clk_3, dut.qsfp0_rx_rst_3)
- cocotb.start_soon(Clock(dut.qsfp0_tx_clk_3, 6.4, units="ns").start())
+ cocotb.start_soon(Clock(dut.qsfp0_tx_clk_3, 2.56, units="ns").start())
self.qsfp0_3_sink = XgmiiSink(dut.qsfp0_txd_3, dut.qsfp0_txc_3, dut.qsfp0_tx_clk_3, dut.qsfp0_tx_rst_3)
- cocotb.start_soon(Clock(dut.qsfp0_rx_clk_4, 6.4, units="ns").start())
+ cocotb.start_soon(Clock(dut.qsfp0_rx_clk_4, 2.56, units="ns").start())
self.qsfp0_4_source = XgmiiSource(dut.qsfp0_rxd_4, dut.qsfp0_rxc_4, dut.qsfp0_rx_clk_4, dut.qsfp0_rx_rst_4)
- cocotb.start_soon(Clock(dut.qsfp0_tx_clk_4, 6.4, units="ns").start())
+ cocotb.start_soon(Clock(dut.qsfp0_tx_clk_4, 2.56, units="ns").start())
self.qsfp0_4_sink = XgmiiSink(dut.qsfp0_txd_4, dut.qsfp0_txc_4, dut.qsfp0_tx_clk_4, dut.qsfp0_tx_rst_4)
- cocotb.start_soon(Clock(dut.qsfp1_rx_clk_1, 6.4, units="ns").start())
+ cocotb.start_soon(Clock(dut.qsfp1_rx_clk_1, 2.56, units="ns").start())
self.qsfp1_1_source = XgmiiSource(dut.qsfp1_rxd_1, dut.qsfp1_rxc_1, dut.qsfp1_rx_clk_1, dut.qsfp1_rx_rst_1)
- cocotb.start_soon(Clock(dut.qsfp1_tx_clk_1, 6.4, units="ns").start())
+ cocotb.start_soon(Clock(dut.qsfp1_tx_clk_1, 2.56, units="ns").start())
self.qsfp1_1_sink = XgmiiSink(dut.qsfp1_txd_1, dut.qsfp1_txc_1, dut.qsfp1_tx_clk_1, dut.qsfp1_tx_rst_1)
- cocotb.start_soon(Clock(dut.qsfp1_rx_clk_2, 6.4, units="ns").start())
+ cocotb.start_soon(Clock(dut.qsfp1_rx_clk_2, 2.56, units="ns").start())
self.qsfp1_2_source = XgmiiSource(dut.qsfp1_rxd_2, dut.qsfp1_rxc_2, dut.qsfp1_rx_clk_2, dut.qsfp1_rx_rst_2)
- cocotb.start_soon(Clock(dut.qsfp1_tx_clk_2, 6.4, units="ns").start())
+ cocotb.start_soon(Clock(dut.qsfp1_tx_clk_2, 2.56, units="ns").start())
self.qsfp1_2_sink = XgmiiSink(dut.qsfp1_txd_2, dut.qsfp1_txc_2, dut.qsfp1_tx_clk_2, dut.qsfp1_tx_rst_2)
- cocotb.start_soon(Clock(dut.qsfp1_rx_clk_3, 6.4, units="ns").start())
+ cocotb.start_soon(Clock(dut.qsfp1_rx_clk_3, 2.56, units="ns").start())
self.qsfp1_3_source = XgmiiSource(dut.qsfp1_rxd_3, dut.qsfp1_rxc_3, dut.qsfp1_rx_clk_3, dut.qsfp1_rx_rst_3)
- cocotb.start_soon(Clock(dut.qsfp1_tx_clk_3, 6.4, units="ns").start())
+ cocotb.start_soon(Clock(dut.qsfp1_tx_clk_3, 2.56, units="ns").start())
self.qsfp1_3_sink = XgmiiSink(dut.qsfp1_txd_3, dut.qsfp1_txc_3, dut.qsfp1_tx_clk_3, dut.qsfp1_tx_rst_3)
- cocotb.start_soon(Clock(dut.qsfp1_rx_clk_4, 6.4, units="ns").start())
+ cocotb.start_soon(Clock(dut.qsfp1_rx_clk_4, 2.56, units="ns").start())
self.qsfp1_4_source = XgmiiSource(dut.qsfp1_rxd_4, dut.qsfp1_rxc_4, dut.qsfp1_rx_clk_4, dut.qsfp1_rx_rst_4)
- cocotb.start_soon(Clock(dut.qsfp1_tx_clk_4, 6.4, units="ns").start())
+ cocotb.start_soon(Clock(dut.qsfp1_tx_clk_4, 2.56, units="ns").start())
self.qsfp1_4_sink = XgmiiSink(dut.qsfp1_txd_4, dut.qsfp1_txc_4, dut.qsfp1_tx_clk_4, dut.qsfp1_tx_rst_4)
dut.qsfp0_rx_status_1.setimmediatevalue(1)