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Normalize descriptor table sizes

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This commit is contained in:
Alex Forencich 2019-08-22 19:03:19 -07:00
parent 5e0bf48b37
commit 6a354e7aa3
4 changed files with 8 additions and 8 deletions
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4
fpga/mqnic/ExaNIC_X10/fpga/rtl/fpga_core.v
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@ -236,9 +236,9 @@ parameter TX_CPL_QUEUE_INDEX_WIDTH = 6;
parameter RX_CPL_QUEUE_INDEX_WIDTH = 6;
// TX and RX engine parameters (port)
parameter TX_DESC_TABLE_SIZE = 16;
parameter TX_DESC_TABLE_SIZE = 32;
parameter TX_PKT_TABLE_SIZE = 8;
parameter RX_DESC_TABLE_SIZE = 16;
parameter RX_DESC_TABLE_SIZE = 32;
parameter RX_PKT_TABLE_SIZE = 8;
// Scheduler parameters (port)

4
fpga/mqnic/VCU108/fpga_10g/rtl/fpga_core.v
View File

@ -262,9 +262,9 @@ parameter TX_CPL_QUEUE_INDEX_WIDTH = 6;
parameter RX_CPL_QUEUE_INDEX_WIDTH = 6;
// TX and RX engine parameters (port)
parameter TX_DESC_TABLE_SIZE = 16;
parameter TX_DESC_TABLE_SIZE = 32;
parameter TX_PKT_TABLE_SIZE = 8;
parameter RX_DESC_TABLE_SIZE = 16;
parameter RX_DESC_TABLE_SIZE = 32;
parameter RX_PKT_TABLE_SIZE = 8;
// Scheduler parameters (port)

4
fpga/mqnic_tdma/ExaNIC_X10/fpga/rtl/fpga_core.v
View File

@ -236,9 +236,9 @@ parameter TX_CPL_QUEUE_INDEX_WIDTH = 6;
parameter RX_CPL_QUEUE_INDEX_WIDTH = 6;
// TX and RX engine parameters (port)
parameter TX_DESC_TABLE_SIZE = 16;
parameter TX_DESC_TABLE_SIZE = 32;
parameter TX_PKT_TABLE_SIZE = 8;
parameter RX_DESC_TABLE_SIZE = 16;
parameter RX_DESC_TABLE_SIZE = 32;
parameter RX_PKT_TABLE_SIZE = 8;
// Scheduler parameters (port)

4
fpga/mqnic_tdma/VCU108/fpga_10g/rtl/fpga_core.v
View File

@ -262,9 +262,9 @@ parameter TX_CPL_QUEUE_INDEX_WIDTH = 6;
parameter RX_CPL_QUEUE_INDEX_WIDTH = 6;
// TX and RX engine parameters (port)
parameter TX_DESC_TABLE_SIZE = 16;
parameter TX_DESC_TABLE_SIZE = 32;
parameter TX_PKT_TABLE_SIZE = 8;
parameter RX_DESC_TABLE_SIZE = 16;
parameter RX_DESC_TABLE_SIZE = 32;
parameter RX_PKT_TABLE_SIZE = 8;
// Scheduler parameters (port)