diff --git a/fpga/mqnic/AU200/fpga_10g/fpga.xdc b/fpga/mqnic/AU200/fpga_10g/fpga.xdc index 471f11965..be5af950f 100644 --- a/fpga/mqnic/AU200/fpga_10g/fpga.xdc +++ b/fpga/mqnic/AU200/fpga_10g/fpga.xdc @@ -148,8 +148,8 @@ set_property -dict {LOC P7 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_230 GTYE4_CHAN set_property -dict {LOC P6 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11 #set_property -dict {LOC T11 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_230 from U14.4 via U43.15 #set_property -dict {LOC T10 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_230 from U14.5 via U43.16 -#set_property -dict {LOC P11 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_230 from U12.18 -#set_property -dict {LOC P10 } [get_ports qsfp1_mgt_refclk_1_n] ;# MGTREFCLK1N_230 from U12.17 +set_property -dict {LOC P11 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_230 from U12.18 +set_property -dict {LOC P10 } [get_ports qsfp1_mgt_refclk_1_n] ;# MGTREFCLK1N_230 from U12.17 set_property -dict {LOC AY20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_modsell] set_property -dict {LOC BC18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_resetl] set_property -dict {LOC BC19 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp1_modprsl] @@ -166,7 +166,7 @@ set_property -dict {LOC AU20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports { #create_clock -period 6.400 -name qsfp1_mgt_refclk_1 [get_ports qsfp1_mgt_refclk_1_p] # 161.1328125 MHz MGT reference clock (from SI5335, FS = 0b10) -#create_clock -period 6.206 -name qsfp1_mgt_refclk_1 [get_ports qsfp1_mgt_refclk_1_p] +create_clock -period 6.206 -name qsfp1_mgt_refclk_1 [get_ports qsfp1_mgt_refclk_1_p] set_false_path -to [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode qsfp1_refclk_reset qsfp1_fs[*]}] set_output_delay 0 [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode qsfp1_refclk_reset qsfp1_fs[*]}] diff --git a/fpga/mqnic/AU200/fpga_10g/fpga/Makefile b/fpga/mqnic/AU200/fpga_10g/fpga/Makefile index 89fc5c8e5..a8ec68a7c 100644 --- a/fpga/mqnic/AU200/fpga_10g/fpga/Makefile +++ b/fpga/mqnic/AU200/fpga_10g/fpga/Makefile @@ -7,6 +7,7 @@ FPGA_ARCH = virtexuplus # Files for synthesis SYN_FILES = rtl/fpga.v SYN_FILES += rtl/fpga_core.v +SYN_FILES += rtl/eth_xcvr_phy_wrapper.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v @@ -119,7 +120,7 @@ XDC_FILES += ../../../common/syn/vivado/tdma_ber_ch.tcl # IP IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl -IP_TCL_FILES += ip/gtwizard_ultrascale_0.tcl +IP_TCL_FILES += ip/eth_xcvr_gt.tcl IP_TCL_FILES += ip/cms.tcl # Configuration diff --git a/fpga/mqnic/AU200/fpga_10g/ip/eth_xcvr_gt.tcl b/fpga/mqnic/AU200/fpga_10g/ip/eth_xcvr_gt.tcl new file mode 100644 index 000000000..cecca12f7 --- /dev/null +++ b/fpga/mqnic/AU200/fpga_10g/ip/eth_xcvr_gt.tcl @@ -0,0 +1,76 @@ +# Copyright (c) 2021 Alex Forencich +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +# THE SOFTWARE. + +set base_name {eth_xcvr_gt} + +set preset {GTY-10GBASE-R} + +set freerun_freq {125} +set line_rate {10.3125} +set refclk_freq {161.1328125} +set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}] +set user_data_width {64} +set int_data_width $user_data_width +set extra_ports [list] +set extra_pll_ports [list {qpll0lock_out}] + +set config [dict create] + +dict set config TX_LINE_RATE $line_rate +dict set config TX_REFCLK_FREQUENCY $refclk_freq +dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn +dict set config TX_USER_DATA_WIDTH $user_data_width +dict set config TX_INT_DATA_WIDTH $int_data_width +dict set config RX_LINE_RATE $line_rate +dict set config RX_REFCLK_FREQUENCY $refclk_freq +dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn +dict set config RX_USER_DATA_WIDTH $user_data_width +dict set config RX_INT_DATA_WIDTH $int_data_width +dict set config ENABLE_OPTIONAL_PORTS $extra_ports +dict set config LOCATE_COMMON {CORE} +dict set config LOCATE_RESET_CONTROLLER {CORE} +dict set config LOCATE_TX_USER_CLOCKING {CORE} +dict set config LOCATE_RX_USER_CLOCKING {CORE} +dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE} +dict set config FREERUN_FREQUENCY $freerun_freq +dict set config DISABLE_LOC_XDC {1} + +proc create_gtwizard_ip {name preset config} { + create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name + set ip [get_ips $name] + set_property CONFIG.preset $preset $ip + set config_list {} + dict for {name value} $config { + lappend config_list "CONFIG.${name}" $value + } + set_property -dict $config_list $ip +} + +# variant with channel and common +dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports] +dict set config LOCATE_COMMON {CORE} + +create_gtwizard_ip "${base_name}_full" $preset $config + +# variant with channel only +dict set config ENABLE_OPTIONAL_PORTS $extra_ports +dict set config LOCATE_COMMON {EXAMPLE_DESIGN} + +create_gtwizard_ip "${base_name}_channel" $preset $config diff --git a/fpga/mqnic/AU200/fpga_10g/ip/gtwizard_ultrascale_0.tcl b/fpga/mqnic/AU200/fpga_10g/ip/gtwizard_ultrascale_0.tcl deleted file mode 100644 index 73e63d46f..000000000 --- a/fpga/mqnic/AU200/fpga_10g/ip/gtwizard_ultrascale_0.tcl +++ /dev/null @@ -1,21 +0,0 @@ - -create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name gtwizard_ultrascale_0 - -set_property -dict [list CONFIG.preset {GTY-10GBASE-R}] [get_ips gtwizard_ultrascale_0] - -set_property -dict [list \ - CONFIG.CHANNEL_ENABLE {X1Y51 X1Y50 X1Y49 X1Y48 X1Y47 X1Y46 X1Y45 X1Y44} \ - CONFIG.TX_MASTER_CHANNEL {X1Y48} \ - CONFIG.RX_MASTER_CHANNEL {X1Y48} \ - CONFIG.TX_LINE_RATE {10.3125} \ - CONFIG.TX_REFCLK_FREQUENCY {161.1328125} \ - CONFIG.TX_USER_DATA_WIDTH {64} \ - CONFIG.TX_INT_DATA_WIDTH {64} \ - CONFIG.RX_LINE_RATE {10.3125} \ - CONFIG.RX_REFCLK_FREQUENCY {161.1328125} \ - CONFIG.RX_USER_DATA_WIDTH {64} \ - CONFIG.RX_INT_DATA_WIDTH {64} \ - CONFIG.RX_REFCLK_SOURCE {X1Y51 clk1 X1Y50 clk1 X1Y49 clk1 X1Y48 clk1 X1Y47 clk1+1 X1Y46 clk1+1 X1Y45 clk1+1 X1Y44 clk1+1} \ - CONFIG.TX_REFCLK_SOURCE {X1Y51 clk1 X1Y50 clk1 X1Y49 clk1 X1Y48 clk1 X1Y47 clk1+1 X1Y46 clk1+1 X1Y45 clk1+1 X1Y44 clk1+1} \ - CONFIG.FREERUN_FREQUENCY {125} \ -] [get_ips gtwizard_ultrascale_0] diff --git a/fpga/mqnic/AU200/fpga_10g/rtl/eth_xcvr_phy_wrapper.v b/fpga/mqnic/AU200/fpga_10g/rtl/eth_xcvr_phy_wrapper.v new file mode 100644 index 000000000..acac5e3f9 --- /dev/null +++ b/fpga/mqnic/AU200/fpga_10g/rtl/eth_xcvr_phy_wrapper.v @@ -0,0 +1,299 @@ +/* + +Copyright (c) 2021 Alex Forencich + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in +all copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN +THE SOFTWARE. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * Transceiver and PHY wrapper + */ +module eth_xcvr_phy_wrapper # +( + parameter HAS_COMMON = 1, + parameter DATA_WIDTH = 64, + parameter CTRL_WIDTH = (DATA_WIDTH/8), + parameter HDR_WIDTH = 2, + parameter PRBS31_ENABLE = 0, + parameter TX_SERDES_PIPELINE = 0, + parameter RX_SERDES_PIPELINE = 0, + parameter BITSLIP_HIGH_CYCLES = 1, + parameter BITSLIP_LOW_CYCLES = 8, + parameter COUNT_125US = 125000/6.4 +) +( + input wire xcvr_ctrl_clk, + input wire xcvr_ctrl_rst, + + /* + * Common + */ + output wire xcvr_gtpowergood_out, + + /* + * PLL out + */ + input wire xcvr_gtrefclk00_in, + output wire xcvr_qpll0lock_out, + output wire xcvr_qpll0outclk_out, + output wire xcvr_qpll0outrefclk_out, + + /* + * PLL in + */ + input wire xcvr_qpll0lock_in, + output wire xcvr_qpll0reset_out, + input wire xcvr_qpll0clk_in, + input wire xcvr_qpll0refclk_in, + + /* + * Serial data + */ + output wire xcvr_txp, + output wire xcvr_txn, + input wire xcvr_rxp, + input wire xcvr_rxn, + + /* + * PHY connections + */ + output wire phy_tx_clk, + output wire phy_tx_rst, + input wire [DATA_WIDTH-1:0] phy_xgmii_txd, + input wire [CTRL_WIDTH-1:0] phy_xgmii_txc, + output wire phy_rx_clk, + output wire phy_rx_rst, + output wire [DATA_WIDTH-1:0] phy_xgmii_rxd, + output wire [CTRL_WIDTH-1:0] phy_xgmii_rxc, + output wire phy_tx_bad_block, + output wire [6:0] phy_rx_error_count, + output wire phy_rx_bad_block, + output wire phy_rx_sequence_error, + output wire phy_rx_block_lock, + output wire phy_rx_high_ber, + input wire phy_tx_prbs31_enable, + input wire phy_rx_prbs31_enable +); + +wire phy_rx_reset_req; + +wire gt_reset_tx_datapath = 1'b0; +wire gt_reset_rx_datapath = phy_rx_reset_req; + +wire gt_reset_tx_done; +wire gt_reset_rx_done; + +wire [5:0] gt_txheader; +wire [63:0] gt_txdata; +wire gt_rxgearboxslip; +wire [5:0] gt_rxheader; +wire [1:0] gt_rxheadervalid; +wire [63:0] gt_rxdata; +wire [1:0] gt_rxdatavalid; + +generate + +if (HAS_COMMON) begin : xcvr + + eth_xcvr_gt_full + eth_xcvr_gt_full_inst ( + // Common + .gtwiz_reset_clk_freerun_in(xcvr_ctrl_clk), + .gtwiz_reset_all_in(xcvr_ctrl_rst), + .gtpowergood_out(xcvr_gtpowergood_out), + + // PLL + .gtrefclk00_in(xcvr_gtrefclk00_in), + .qpll0lock_out(xcvr_qpll0lock_out), + .qpll0outclk_out(xcvr_qpll0outclk_out), + .qpll0outrefclk_out(xcvr_qpll0outrefclk_out), + + // Serial data + .gtytxp_out(xcvr_txp), + .gtytxn_out(xcvr_txn), + .gtyrxp_in(xcvr_rxp), + .gtyrxn_in(xcvr_rxn), + + // Transmit + .gtwiz_userclk_tx_reset_in(1'b0), + .gtwiz_userclk_tx_srcclk_out(), + .gtwiz_userclk_tx_usrclk_out(), + .gtwiz_userclk_tx_usrclk2_out(phy_tx_clk), + .gtwiz_userclk_tx_active_out(), + .gtwiz_reset_tx_pll_and_datapath_in(1'b0), + .gtwiz_reset_tx_datapath_in(gt_reset_tx_datapath), + .gtwiz_reset_tx_done_out(gt_reset_tx_done), + .txpmaresetdone_out(), + .txprgdivresetdone_out(), + + .gtwiz_userdata_tx_in(gt_txdata), + .txheader_in(gt_txheader), + .txsequence_in(7'b0), + + // Receive + .gtwiz_userclk_rx_reset_in(1'b0), + .gtwiz_userclk_rx_srcclk_out(), + .gtwiz_userclk_rx_usrclk_out(), + .gtwiz_userclk_rx_usrclk2_out(phy_rx_clk), + .gtwiz_userclk_rx_active_out(), + .gtwiz_reset_rx_pll_and_datapath_in(1'b0), + .gtwiz_reset_rx_datapath_in(gt_reset_rx_datapath), + .gtwiz_reset_rx_cdr_stable_out(), + .gtwiz_reset_rx_done_out(gt_reset_rx_done), + .rxpmaresetdone_out(), + .rxprgdivresetdone_out(), + + .rxgearboxslip_in(gt_rxgearboxslip), + .gtwiz_userdata_rx_out(gt_rxdata), + .rxdatavalid_out(gt_rxdatavalid), + .rxheader_out(gt_rxheader), + .rxheadervalid_out(gt_rxheadervalid), + .rxstartofseq_out() + ); + +end else begin : xcvr + + eth_xcvr_gt_channel + eth_xcvr_gt_channel_inst ( + // Common + .gtwiz_reset_clk_freerun_in(xcvr_ctrl_clk), + .gtwiz_reset_all_in(xcvr_ctrl_rst), + .gtpowergood_out(xcvr_gtpowergood_out), + + // PLL + .gtwiz_reset_qpll0lock_in(xcvr_qpll0lock_in), + .gtwiz_reset_qpll0reset_out(xcvr_qpll0reset_out), + .qpll0clk_in(xcvr_qpll0clk_in), + .qpll0refclk_in(xcvr_qpll0refclk_in), + .qpll1clk_in(1'b0), + .qpll1refclk_in(1'b0), + + // Serial data + .gtytxp_out(xcvr_txp), + .gtytxn_out(xcvr_txn), + .gtyrxp_in(xcvr_rxp), + .gtyrxn_in(xcvr_rxn), + + // Transmit + .gtwiz_userclk_tx_reset_in(1'b0), + .gtwiz_userclk_tx_srcclk_out(), + .gtwiz_userclk_tx_usrclk_out(), + .gtwiz_userclk_tx_usrclk2_out(phy_tx_clk), + .gtwiz_userclk_tx_active_out(), + .gtwiz_reset_tx_pll_and_datapath_in(1'b0), + .gtwiz_reset_tx_datapath_in(gt_reset_tx_datapath), + .gtwiz_reset_tx_done_out(gt_reset_tx_done), + .txpmaresetdone_out(), + .txprgdivresetdone_out(), + + .gtwiz_userdata_tx_in(gt_txdata), + .txheader_in(gt_txheader), + .txsequence_in(7'b0), + + // Receive + .gtwiz_userclk_rx_reset_in(1'b0), + .gtwiz_userclk_rx_srcclk_out(), + .gtwiz_userclk_rx_usrclk_out(), + .gtwiz_userclk_rx_usrclk2_out(phy_rx_clk), + .gtwiz_userclk_rx_active_out(), + .gtwiz_reset_rx_pll_and_datapath_in(1'b0), + .gtwiz_reset_rx_datapath_in(gt_reset_rx_datapath), + .gtwiz_reset_rx_cdr_stable_out(), + .gtwiz_reset_rx_done_out(gt_reset_rx_done), + .rxpmaresetdone_out(), + .rxprgdivresetdone_out(), + + .rxgearboxslip_in(gt_rxgearboxslip), + .gtwiz_userdata_rx_out(gt_rxdata), + .rxdatavalid_out(gt_rxdatavalid), + .rxheader_out(gt_rxheader), + .rxheadervalid_out(gt_rxheadervalid), + .rxstartofseq_out() + ); + +end + +endgenerate + +sync_reset #( + .N(4) +) +tx_reset_sync_inst ( + .clk(phy_tx_clk), + .rst(!gt_reset_tx_done), + .out(phy_tx_rst) +); + +sync_reset #( + .N(4) +) +rx_reset_sync_inst ( + .clk(phy_rx_clk), + .rst(!gt_reset_rx_done), + .out(phy_rx_rst) +); + +eth_phy_10g #( + .DATA_WIDTH(DATA_WIDTH), + .CTRL_WIDTH(CTRL_WIDTH), + .HDR_WIDTH(HDR_WIDTH), + .BIT_REVERSE(1), + .SCRAMBLER_DISABLE(0), + .PRBS31_ENABLE(PRBS31_ENABLE), + .TX_SERDES_PIPELINE(TX_SERDES_PIPELINE), + .RX_SERDES_PIPELINE(RX_SERDES_PIPELINE), + .BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES), + .BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES), + .COUNT_125US(COUNT_125US) +) +phy_inst ( + .tx_clk(phy_tx_clk), + .tx_rst(phy_tx_rst), + .rx_clk(phy_rx_clk), + .rx_rst(phy_rx_rst), + .xgmii_txd(phy_xgmii_txd), + .xgmii_txc(phy_xgmii_txc), + .xgmii_rxd(phy_xgmii_rxd), + .xgmii_rxc(phy_xgmii_rxc), + .serdes_tx_data(gt_txdata), + .serdes_tx_hdr(gt_txheader), + .serdes_rx_data(gt_rxdata), + .serdes_rx_hdr(gt_rxheader), + .serdes_rx_bitslip(gt_rxgearboxslip), + .serdes_rx_reset_req(phy_rx_reset_req), + .tx_bad_block(phy_tx_bad_block), + .rx_error_count(phy_rx_error_count), + .rx_bad_block(phy_rx_bad_block), + .rx_sequence_error(phy_rx_sequence_error), + .rx_block_lock(phy_rx_block_lock), + .rx_high_ber(phy_rx_high_ber), + .tx_prbs31_enable(phy_tx_prbs31_enable), + .rx_prbs31_enable(phy_rx_prbs31_enable) +); + +endmodule + +`resetall diff --git a/fpga/mqnic/AU200/fpga_10g/rtl/fpga.v b/fpga/mqnic/AU200/fpga_10g/rtl/fpga.v index ea5e4e3bc..871234a6a 100644 --- a/fpga/mqnic/AU200/fpga_10g/rtl/fpga.v +++ b/fpga/mqnic/AU200/fpga_10g/rtl/fpga.v @@ -229,8 +229,8 @@ module fpga # input wire qsfp1_rx4_n, // input wire qsfp1_mgt_refclk_0_p, // input wire qsfp1_mgt_refclk_0_n, - // input wire qsfp1_mgt_refclk_1_p, - // input wire qsfp1_mgt_refclk_1_n, + input wire qsfp1_mgt_refclk_1_p, + input wire qsfp1_mgt_refclk_1_n, output wire qsfp1_modsell, output wire qsfp1_resetl, input wire qsfp1_modprsl, @@ -1037,6 +1037,8 @@ pcie4_uscale_plus_inst ( ); // XGMII 10G PHY + +// QSFP0 assign qsfp0_refclk_reset = qsfp_refclk_reset_reg; assign qsfp0_fs = 2'b10; @@ -1085,6 +1087,234 @@ wire [XGMII_CTRL_WIDTH-1:0] qsfp0_rxc_4_int; wire qsfp0_rx_prbs31_enable_4_int; wire [6:0] qsfp0_rx_error_count_4_int; +wire qsfp0_rx_block_lock_1; +wire qsfp0_rx_block_lock_2; +wire qsfp0_rx_block_lock_3; +wire qsfp0_rx_block_lock_4; + +wire qsfp0_gtpowergood; + +wire qsfp0_mgt_refclk_1; +wire qsfp0_mgt_refclk_1_int; +wire qsfp0_mgt_refclk_1_bufg; + +assign clk_161mhz_ref_int = qsfp0_mgt_refclk_1_bufg; + +IBUFDS_GTE4 ibufds_gte4_qsfp0_mgt_refclk_1_inst ( + .I (qsfp0_mgt_refclk_1_p), + .IB (qsfp0_mgt_refclk_1_n), + .CEB (1'b0), + .O (qsfp0_mgt_refclk_1), + .ODIV2 (qsfp0_mgt_refclk_1_int) +); + +BUFG_GT bufg_gt_refclk_inst ( + .CE (qsfp0_gtpowergood), + .CEMASK (1'b1), + .CLR (1'b0), + .CLRMASK (1'b1), + .DIV (3'd0), + .I (qsfp0_mgt_refclk_1_int), + .O (qsfp0_mgt_refclk_1_bufg) +); + +wire qsfp0_qpll0lock; +wire qsfp0_qpll0outclk; +wire qsfp0_qpll0outrefclk; + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1), + .PRBS31_ENABLE(1) +) +qsfp0_phy_1_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(rst_125mhz_int), + + // Common + .xcvr_gtpowergood_out(qsfp0_gtpowergood), + + // PLL out + .xcvr_gtrefclk00_in(qsfp0_mgt_refclk_1), + .xcvr_qpll0lock_out(qsfp0_qpll0lock), + .xcvr_qpll0outclk_out(qsfp0_qpll0outclk), + .xcvr_qpll0outrefclk_out(qsfp0_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(qsfp0_tx1_p), + .xcvr_txn(qsfp0_tx1_n), + .xcvr_rxp(qsfp0_rx1_p), + .xcvr_rxn(qsfp0_rx1_n), + + // PHY connections + .phy_tx_clk(qsfp0_tx_clk_1_int), + .phy_tx_rst(qsfp0_tx_rst_1_int), + .phy_xgmii_txd(qsfp0_txd_1_int), + .phy_xgmii_txc(qsfp0_txc_1_int), + .phy_rx_clk(qsfp0_rx_clk_1_int), + .phy_rx_rst(qsfp0_rx_rst_1_int), + .phy_xgmii_rxd(qsfp0_rxd_1_int), + .phy_xgmii_rxc(qsfp0_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(qsfp0_rx_error_count_1_int), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp0_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(qsfp0_tx_prbs31_enable_1_int), + .phy_rx_prbs31_enable(qsfp0_rx_prbs31_enable_1_int) +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .PRBS31_ENABLE(1) +) +qsfp0_phy_2_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(rst_125mhz_int), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp0_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp0_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp0_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp0_tx2_p), + .xcvr_txn(qsfp0_tx2_n), + .xcvr_rxp(qsfp0_rx2_p), + .xcvr_rxn(qsfp0_rx2_n), + + // PHY connections + .phy_tx_clk(qsfp0_tx_clk_2_int), + .phy_tx_rst(qsfp0_tx_rst_2_int), + .phy_xgmii_txd(qsfp0_txd_2_int), + .phy_xgmii_txc(qsfp0_txc_2_int), + .phy_rx_clk(qsfp0_rx_clk_2_int), + .phy_rx_rst(qsfp0_rx_rst_2_int), + .phy_xgmii_rxd(qsfp0_rxd_2_int), + .phy_xgmii_rxc(qsfp0_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(qsfp0_rx_error_count_2_int), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp0_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(qsfp0_tx_prbs31_enable_2_int), + .phy_rx_prbs31_enable(qsfp0_rx_prbs31_enable_2_int) +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .PRBS31_ENABLE(1) +) +qsfp0_phy_3_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(rst_125mhz_int), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp0_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp0_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp0_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp0_tx3_p), + .xcvr_txn(qsfp0_tx3_n), + .xcvr_rxp(qsfp0_rx3_p), + .xcvr_rxn(qsfp0_rx3_n), + + // PHY connections + .phy_tx_clk(qsfp0_tx_clk_3_int), + .phy_tx_rst(qsfp0_tx_rst_3_int), + .phy_xgmii_txd(qsfp0_txd_3_int), + .phy_xgmii_txc(qsfp0_txc_3_int), + .phy_rx_clk(qsfp0_rx_clk_3_int), + .phy_rx_rst(qsfp0_rx_rst_3_int), + .phy_xgmii_rxd(qsfp0_rxd_3_int), + .phy_xgmii_rxc(qsfp0_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(qsfp0_rx_error_count_3_int), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp0_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(qsfp0_tx_prbs31_enable_3_int), + .phy_rx_prbs31_enable(qsfp0_rx_prbs31_enable_3_int) +); + +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), + .PRBS31_ENABLE(1) +) +qsfp0_phy_4_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(rst_125mhz_int), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp0_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp0_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp0_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp0_tx4_p), + .xcvr_txn(qsfp0_tx4_n), + .xcvr_rxp(qsfp0_rx4_p), + .xcvr_rxn(qsfp0_rx4_n), + + // PHY connections + .phy_tx_clk(qsfp0_tx_clk_4_int), + .phy_tx_rst(qsfp0_tx_rst_4_int), + .phy_xgmii_txd(qsfp0_txd_4_int), + .phy_xgmii_txc(qsfp0_txc_4_int), + .phy_rx_clk(qsfp0_rx_clk_4_int), + .phy_rx_rst(qsfp0_rx_rst_4_int), + .phy_xgmii_rxd(qsfp0_rxd_4_int), + .phy_xgmii_rxc(qsfp0_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(qsfp0_rx_error_count_4_int), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp0_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(qsfp0_tx_prbs31_enable_4_int), + .phy_rx_prbs31_enable(qsfp0_rx_prbs31_enable_4_int) +); + +// QSFP1 assign qsfp1_refclk_reset = qsfp_refclk_reset_reg; assign qsfp1_fs = 2'b10; @@ -1133,550 +1363,215 @@ wire [XGMII_CTRL_WIDTH-1:0] qsfp1_rxc_4_int; wire qsfp1_rx_prbs31_enable_4_int; wire [6:0] qsfp1_rx_error_count_4_int; -wire qsfp0_rx_block_lock_1; -wire qsfp0_rx_block_lock_2; -wire qsfp0_rx_block_lock_3; -wire qsfp0_rx_block_lock_4; - wire qsfp1_rx_block_lock_1; wire qsfp1_rx_block_lock_2; wire qsfp1_rx_block_lock_3; wire qsfp1_rx_block_lock_4; -wire [7:0] qsfp_gtpowergood; +wire qsfp1_mgt_refclk_1; -wire qsfp0_mgt_refclk_1; -wire qsfp0_mgt_refclk_1_int; -wire qsfp0_mgt_refclk_1_bufg; - -assign clk_161mhz_ref_int = qsfp0_mgt_refclk_1_bufg; - -wire [7:0] gt_txclkout; -wire gt_txusrclk; - -wire [7:0] gt_rxclkout; -wire [7:0] gt_rxusrclk; - -wire gt_reset_tx_done; -wire gt_reset_rx_done; - -wire [7:0] gt_txprgdivresetdone; -wire [7:0] gt_txpmaresetdone; -wire [7:0] gt_rxprgdivresetdone; -wire [7:0] gt_rxpmaresetdone; - -wire gt_tx_reset = ~((>_txprgdivresetdone) & (>_txpmaresetdone)); -wire gt_rx_reset = ~>_rxpmaresetdone; - -reg gt_userclk_tx_active = 1'b0; -reg [7:0] gt_userclk_rx_active = 1'b0; - -IBUFDS_GTE4 ibufds_gte4_qsfp0_mgt_refclk_1_inst ( - .I (qsfp0_mgt_refclk_1_p), - .IB (qsfp0_mgt_refclk_1_n), - .CEB (1'b0), - .O (qsfp0_mgt_refclk_1), - .ODIV2 (qsfp0_mgt_refclk_1_int) +IBUFDS_GTE4 ibufds_gte4_qsfp1_mgt_refclk_1_inst ( + .I (qsfp1_mgt_refclk_1_p), + .IB (qsfp1_mgt_refclk_1_n), + .CEB (1'b0), + .O (qsfp1_mgt_refclk_1), + .ODIV2 () ); -BUFG_GT bufg_gt_refclk_inst ( - .CE (&qsfp_gtpowergood), - .CEMASK (1'b1), - .CLR (1'b0), - .CLRMASK (1'b1), - .DIV (3'd0), - .I (qsfp0_mgt_refclk_1_int), - .O (qsfp0_mgt_refclk_1_bufg) -); +wire qsfp1_qpll0lock; +wire qsfp1_qpll0outclk; +wire qsfp1_qpll0outrefclk; -BUFG_GT bufg_gt_tx_usrclk_inst ( - .CE (1'b1), - .CEMASK (1'b0), - .CLR (gt_tx_reset), - .CLRMASK (1'b0), - .DIV (3'd0), - .I (gt_txclkout[0]), - .O (gt_txusrclk) -); - -assign clk_156mhz_int = gt_txusrclk; - -always @(posedge gt_txusrclk, posedge gt_tx_reset) begin - if (gt_tx_reset) begin - gt_userclk_tx_active <= 1'b0; - end else begin - gt_userclk_tx_active <= 1'b1; - end -end - -genvar n; - -generate - -for (n = 0; n < 8; n = n + 1) begin - - BUFG_GT bufg_gt_rx_usrclk_inst ( - .CE (1'b1), - .CEMASK (1'b0), - .CLR (gt_rx_reset), - .CLRMASK (1'b0), - .DIV (3'd0), - .I (gt_rxclkout[n]), - .O (gt_rxusrclk[n]) - ); - - always @(posedge gt_rxusrclk[n], posedge gt_rx_reset) begin - if (gt_rx_reset) begin - gt_userclk_rx_active[n] <= 1'b0; - end else begin - gt_userclk_rx_active[n] <= 1'b1; - end - end - -end - -endgenerate - -sync_reset #( - .N(4) -) -sync_reset_156mhz_inst ( - .clk(clk_156mhz_int), - .rst(~gt_reset_tx_done), - .out(rst_156mhz_int) -); - -wire [5:0] qsfp0_gt_txheader_1; -wire [63:0] qsfp0_gt_txdata_1; -wire qsfp0_gt_rxgearboxslip_1; -wire [5:0] qsfp0_gt_rxheader_1; -wire [1:0] qsfp0_gt_rxheadervalid_1; -wire [63:0] qsfp0_gt_rxdata_1; -wire [1:0] qsfp0_gt_rxdatavalid_1; - -wire [5:0] qsfp0_gt_txheader_2; -wire [63:0] qsfp0_gt_txdata_2; -wire qsfp0_gt_rxgearboxslip_2; -wire [5:0] qsfp0_gt_rxheader_2; -wire [1:0] qsfp0_gt_rxheadervalid_2; -wire [63:0] qsfp0_gt_rxdata_2; -wire [1:0] qsfp0_gt_rxdatavalid_2; - -wire [5:0] qsfp0_gt_txheader_3; -wire [63:0] qsfp0_gt_txdata_3; -wire qsfp0_gt_rxgearboxslip_3; -wire [5:0] qsfp0_gt_rxheader_3; -wire [1:0] qsfp0_gt_rxheadervalid_3; -wire [63:0] qsfp0_gt_rxdata_3; -wire [1:0] qsfp0_gt_rxdatavalid_3; - -wire [5:0] qsfp0_gt_txheader_4; -wire [63:0] qsfp0_gt_txdata_4; -wire qsfp0_gt_rxgearboxslip_4; -wire [5:0] qsfp0_gt_rxheader_4; -wire [1:0] qsfp0_gt_rxheadervalid_4; -wire [63:0] qsfp0_gt_rxdata_4; -wire [1:0] qsfp0_gt_rxdatavalid_4; - -wire [5:0] qsfp1_gt_txheader_1; -wire [63:0] qsfp1_gt_txdata_1; -wire qsfp1_gt_rxgearboxslip_1; -wire [5:0] qsfp1_gt_rxheader_1; -wire [1:0] qsfp1_gt_rxheadervalid_1; -wire [63:0] qsfp1_gt_rxdata_1; -wire [1:0] qsfp1_gt_rxdatavalid_1; - -wire [5:0] qsfp1_gt_txheader_2; -wire [63:0] qsfp1_gt_txdata_2; -wire qsfp1_gt_rxgearboxslip_2; -wire [5:0] qsfp1_gt_rxheader_2; -wire [1:0] qsfp1_gt_rxheadervalid_2; -wire [63:0] qsfp1_gt_rxdata_2; -wire [1:0] qsfp1_gt_rxdatavalid_2; - -wire [5:0] qsfp1_gt_txheader_3; -wire [63:0] qsfp1_gt_txdata_3; -wire qsfp1_gt_rxgearboxslip_3; -wire [5:0] qsfp1_gt_rxheader_3; -wire [1:0] qsfp1_gt_rxheadervalid_3; -wire [63:0] qsfp1_gt_rxdata_3; -wire [1:0] qsfp1_gt_rxdatavalid_3; - -wire [5:0] qsfp1_gt_txheader_4; -wire [63:0] qsfp1_gt_txdata_4; -wire qsfp1_gt_rxgearboxslip_4; -wire [5:0] qsfp1_gt_rxheader_4; -wire [1:0] qsfp1_gt_rxheadervalid_4; -wire [63:0] qsfp1_gt_rxdata_4; -wire [1:0] qsfp1_gt_rxdatavalid_4; - -gtwizard_ultrascale_0 -qsfp_gty_inst ( - .gtwiz_userclk_tx_active_in(>_userclk_tx_active), - .gtwiz_userclk_rx_active_in(>_userclk_rx_active), - - .gtwiz_reset_clk_freerun_in(clk_125mhz_int), - .gtwiz_reset_all_in(rst_125mhz_int), - - .gtwiz_reset_tx_pll_and_datapath_in(1'b0), - .gtwiz_reset_tx_datapath_in(1'b0), - - .gtwiz_reset_rx_pll_and_datapath_in(1'b0), - .gtwiz_reset_rx_datapath_in(1'b0), - - .gtwiz_reset_rx_cdr_stable_out(), - - .gtwiz_reset_tx_done_out(gt_reset_tx_done), - .gtwiz_reset_rx_done_out(gt_reset_rx_done), - - .gtrefclk00_in({2{qsfp0_mgt_refclk_1}}), - - .qpll0outclk_out(), - .qpll0outrefclk_out(), - - .gtyrxn_in({qsfp0_rx4_n, qsfp0_rx3_n, qsfp0_rx2_n, qsfp0_rx1_n, qsfp1_rx4_n, qsfp1_rx3_n, qsfp1_rx2_n, qsfp1_rx1_n}), - .gtyrxp_in({qsfp0_rx4_p, qsfp0_rx3_p, qsfp0_rx2_p, qsfp0_rx1_p, qsfp1_rx4_p, qsfp1_rx3_p, qsfp1_rx2_p, qsfp1_rx1_p}), - - .rxusrclk_in(gt_rxusrclk), - .rxusrclk2_in(gt_rxusrclk), - - .gtwiz_userdata_tx_in({qsfp0_gt_txdata_4, qsfp0_gt_txdata_3, qsfp0_gt_txdata_2, qsfp0_gt_txdata_1, qsfp1_gt_txdata_4, qsfp1_gt_txdata_3, qsfp1_gt_txdata_2, qsfp1_gt_txdata_1}), - .txheader_in({qsfp0_gt_txheader_4, qsfp0_gt_txheader_3, qsfp0_gt_txheader_2, qsfp0_gt_txheader_1, qsfp1_gt_txheader_4, qsfp1_gt_txheader_3, qsfp1_gt_txheader_2, qsfp1_gt_txheader_1}), - .txsequence_in({8{1'b0}}), - - .txusrclk_in({8{gt_txusrclk}}), - .txusrclk2_in({8{gt_txusrclk}}), - - .gtpowergood_out(qsfp_gtpowergood), - - .gtytxn_out({qsfp0_tx4_n, qsfp0_tx3_n, qsfp0_tx2_n, qsfp0_tx1_n, qsfp1_tx4_n, qsfp1_tx3_n, qsfp1_tx2_n, qsfp1_tx1_n}), - .gtytxp_out({qsfp0_tx4_p, qsfp0_tx3_p, qsfp0_tx2_p, qsfp0_tx1_p, qsfp1_tx4_p, qsfp1_tx3_p, qsfp1_tx2_p, qsfp1_tx1_p}), - - .rxgearboxslip_in({qsfp0_gt_rxgearboxslip_4, qsfp0_gt_rxgearboxslip_3, qsfp0_gt_rxgearboxslip_2, qsfp0_gt_rxgearboxslip_1, qsfp1_gt_rxgearboxslip_4, qsfp1_gt_rxgearboxslip_3, qsfp1_gt_rxgearboxslip_2, qsfp1_gt_rxgearboxslip_1}), - .gtwiz_userdata_rx_out({qsfp0_gt_rxdata_4, qsfp0_gt_rxdata_3, qsfp0_gt_rxdata_2, qsfp0_gt_rxdata_1, qsfp1_gt_rxdata_4, qsfp1_gt_rxdata_3, qsfp1_gt_rxdata_2, qsfp1_gt_rxdata_1}), - .rxdatavalid_out({qsfp0_gt_rxdatavalid_4, qsfp0_gt_rxdatavalid_3, qsfp0_gt_rxdatavalid_2, qsfp0_gt_rxdatavalid_1, qsfp1_gt_rxdatavalid_4, qsfp1_gt_rxdatavalid_3, qsfp1_gt_rxdatavalid_2, qsfp1_gt_rxdatavalid_1}), - .rxheader_out({qsfp0_gt_rxheader_4, qsfp0_gt_rxheader_3, qsfp0_gt_rxheader_2, qsfp0_gt_rxheader_1, qsfp1_gt_rxheader_4, qsfp1_gt_rxheader_3, qsfp1_gt_rxheader_2, qsfp1_gt_rxheader_1}), - .rxheadervalid_out({qsfp0_gt_rxheadervalid_4, qsfp0_gt_rxheadervalid_3, qsfp0_gt_rxheadervalid_2, qsfp0_gt_rxheadervalid_1, qsfp1_gt_rxheadervalid_4, qsfp1_gt_rxheadervalid_3, qsfp1_gt_rxheadervalid_2, qsfp1_gt_rxheadervalid_1}), - .rxoutclk_out(gt_rxclkout), - .rxpmaresetdone_out(gt_rxpmaresetdone), - .rxprgdivresetdone_out(gt_rxprgdivresetdone), - .rxstartofseq_out(), - - .txoutclk_out(gt_txclkout), - .txpmaresetdone_out(gt_txpmaresetdone), - .txprgdivresetdone_out(gt_txprgdivresetdone) -); - -assign qsfp0_tx_clk_1_int = clk_156mhz_int; -assign qsfp0_tx_rst_1_int = rst_156mhz_int; - -assign qsfp0_rx_clk_1_int = gt_rxusrclk[4]; - -sync_reset #( - .N(4) -) -qsfp0_rx_rst_1_reset_sync_inst ( - .clk(qsfp0_rx_clk_1_int), - .rst(~gt_reset_rx_done), - .out(qsfp0_rx_rst_1_int) -); - -eth_phy_10g #( - .BIT_REVERSE(1), - .PRBS31_ENABLE(1) -) -qsfp0_phy_1_inst ( - .tx_clk(qsfp0_tx_clk_1_int), - .tx_rst(qsfp0_tx_rst_1_int), - .rx_clk(qsfp0_rx_clk_1_int), - .rx_rst(qsfp0_rx_rst_1_int), - .xgmii_txd(qsfp0_txd_1_int), - .xgmii_txc(qsfp0_txc_1_int), - .xgmii_rxd(qsfp0_rxd_1_int), - .xgmii_rxc(qsfp0_rxc_1_int), - .serdes_tx_data(qsfp0_gt_txdata_1), - .serdes_tx_hdr(qsfp0_gt_txheader_1), - .serdes_rx_data(qsfp0_gt_rxdata_1), - .serdes_rx_hdr(qsfp0_gt_rxheader_1), - .serdes_rx_bitslip(qsfp0_gt_rxgearboxslip_1), - .rx_error_count(qsfp0_rx_error_count_1_int), - .rx_block_lock(qsfp0_rx_block_lock_1), - .rx_high_ber(), - .tx_prbs31_enable(qsfp0_tx_prbs31_enable_1_int), - .rx_prbs31_enable(qsfp0_rx_prbs31_enable_1_int) -); - -assign qsfp0_tx_clk_2_int = clk_156mhz_int; -assign qsfp0_tx_rst_2_int = rst_156mhz_int; - -assign qsfp0_rx_clk_2_int = gt_rxusrclk[5]; - -sync_reset #( - .N(4) -) -qsfp0_rx_rst_2_reset_sync_inst ( - .clk(qsfp0_rx_clk_2_int), - .rst(~gt_reset_rx_done), - .out(qsfp0_rx_rst_2_int) -); - -eth_phy_10g #( - .BIT_REVERSE(1), - .PRBS31_ENABLE(1) -) -qsfp0_phy_2_inst ( - .tx_clk(qsfp0_tx_clk_2_int), - .tx_rst(qsfp0_tx_rst_2_int), - .rx_clk(qsfp0_rx_clk_2_int), - .rx_rst(qsfp0_rx_rst_2_int), - .xgmii_txd(qsfp0_txd_2_int), - .xgmii_txc(qsfp0_txc_2_int), - .xgmii_rxd(qsfp0_rxd_2_int), - .xgmii_rxc(qsfp0_rxc_2_int), - .serdes_tx_data(qsfp0_gt_txdata_2), - .serdes_tx_hdr(qsfp0_gt_txheader_2), - .serdes_rx_data(qsfp0_gt_rxdata_2), - .serdes_rx_hdr(qsfp0_gt_rxheader_2), - .serdes_rx_bitslip(qsfp0_gt_rxgearboxslip_2), - .rx_error_count(qsfp0_rx_error_count_2_int), - .rx_block_lock(qsfp0_rx_block_lock_2), - .rx_high_ber(), - .tx_prbs31_enable(qsfp0_tx_prbs31_enable_2_int), - .rx_prbs31_enable(qsfp0_rx_prbs31_enable_2_int) -); - -assign qsfp0_tx_clk_3_int = clk_156mhz_int; -assign qsfp0_tx_rst_3_int = rst_156mhz_int; - -assign qsfp0_rx_clk_3_int = gt_rxusrclk[6]; - -sync_reset #( - .N(4) -) -qsfp0_rx_rst_3_reset_sync_inst ( - .clk(qsfp0_rx_clk_3_int), - .rst(~gt_reset_rx_done), - .out(qsfp0_rx_rst_3_int) -); - -eth_phy_10g #( - .BIT_REVERSE(1), - .PRBS31_ENABLE(1) -) -qsfp0_phy_3_inst ( - .tx_clk(qsfp0_tx_clk_3_int), - .tx_rst(qsfp0_tx_rst_3_int), - .rx_clk(qsfp0_rx_clk_3_int), - .rx_rst(qsfp0_rx_rst_3_int), - .xgmii_txd(qsfp0_txd_3_int), - .xgmii_txc(qsfp0_txc_3_int), - .xgmii_rxd(qsfp0_rxd_3_int), - .xgmii_rxc(qsfp0_rxc_3_int), - .serdes_tx_data(qsfp0_gt_txdata_3), - .serdes_tx_hdr(qsfp0_gt_txheader_3), - .serdes_rx_data(qsfp0_gt_rxdata_3), - .serdes_rx_hdr(qsfp0_gt_rxheader_3), - .serdes_rx_bitslip(qsfp0_gt_rxgearboxslip_3), - .rx_error_count(qsfp0_rx_error_count_3_int), - .rx_block_lock(qsfp0_rx_block_lock_3), - .rx_high_ber(), - .tx_prbs31_enable(qsfp0_tx_prbs31_enable_3_int), - .rx_prbs31_enable(qsfp0_rx_prbs31_enable_3_int) -); - -assign qsfp0_tx_clk_4_int = clk_156mhz_int; -assign qsfp0_tx_rst_4_int = rst_156mhz_int; - -assign qsfp0_rx_clk_4_int = gt_rxusrclk[7]; - -sync_reset #( - .N(4) -) -qsfp0_rx_rst_4_reset_sync_inst ( - .clk(qsfp0_rx_clk_4_int), - .rst(~gt_reset_rx_done), - .out(qsfp0_rx_rst_4_int) -); - -eth_phy_10g #( - .BIT_REVERSE(1), - .PRBS31_ENABLE(1) -) -qsfp0_phy_4_inst ( - .tx_clk(qsfp0_tx_clk_4_int), - .tx_rst(qsfp0_tx_rst_4_int), - .rx_clk(qsfp0_rx_clk_4_int), - .rx_rst(qsfp0_rx_rst_4_int), - .xgmii_txd(qsfp0_txd_4_int), - .xgmii_txc(qsfp0_txc_4_int), - .xgmii_rxd(qsfp0_rxd_4_int), - .xgmii_rxc(qsfp0_rxc_4_int), - .serdes_tx_data(qsfp0_gt_txdata_4), - .serdes_tx_hdr(qsfp0_gt_txheader_4), - .serdes_rx_data(qsfp0_gt_rxdata_4), - .serdes_rx_hdr(qsfp0_gt_rxheader_4), - .serdes_rx_bitslip(qsfp0_gt_rxgearboxslip_4), - .rx_error_count(qsfp0_rx_error_count_4_int), - .rx_block_lock(qsfp0_rx_block_lock_4), - .rx_high_ber(), - .tx_prbs31_enable(qsfp0_tx_prbs31_enable_4_int), - .rx_prbs31_enable(qsfp0_rx_prbs31_enable_4_int) -); - -assign qsfp1_tx_clk_1_int = clk_156mhz_int; -assign qsfp1_tx_rst_1_int = rst_156mhz_int; - -assign qsfp1_rx_clk_1_int = gt_rxusrclk[0]; - -sync_reset #( - .N(4) -) -qsfp1_rx_rst_1_reset_sync_inst ( - .clk(qsfp1_rx_clk_1_int), - .rst(~gt_reset_rx_done), - .out(qsfp1_rx_rst_1_int) -); - -eth_phy_10g #( - .BIT_REVERSE(1), +eth_xcvr_phy_wrapper #( + .HAS_COMMON(1), .PRBS31_ENABLE(1) ) qsfp1_phy_1_inst ( - .tx_clk(qsfp1_tx_clk_1_int), - .tx_rst(qsfp1_tx_rst_1_int), - .rx_clk(qsfp1_rx_clk_1_int), - .rx_rst(qsfp1_rx_rst_1_int), - .xgmii_txd(qsfp1_txd_1_int), - .xgmii_txc(qsfp1_txc_1_int), - .xgmii_rxd(qsfp1_rxd_1_int), - .xgmii_rxc(qsfp1_rxc_1_int), - .serdes_tx_data(qsfp1_gt_txdata_1), - .serdes_tx_hdr(qsfp1_gt_txheader_1), - .serdes_rx_data(qsfp1_gt_rxdata_1), - .serdes_rx_hdr(qsfp1_gt_rxheader_1), - .serdes_rx_bitslip(qsfp1_gt_rxgearboxslip_1), - .rx_error_count(qsfp1_rx_error_count_1_int), - .rx_block_lock(qsfp1_rx_block_lock_1), - .rx_high_ber(), - .tx_prbs31_enable(qsfp1_tx_prbs31_enable_1_int), - .rx_prbs31_enable(qsfp1_rx_prbs31_enable_1_int) + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(rst_125mhz_int), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(qsfp1_mgt_refclk_1), + .xcvr_qpll0lock_out(qsfp1_qpll0lock), + .xcvr_qpll0outclk_out(qsfp1_qpll0outclk), + .xcvr_qpll0outrefclk_out(qsfp1_qpll0outrefclk), + + // PLL in + .xcvr_qpll0lock_in(1'b0), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(1'b0), + .xcvr_qpll0refclk_in(1'b0), + + // Serial data + .xcvr_txp(qsfp1_tx1_p), + .xcvr_txn(qsfp1_tx1_n), + .xcvr_rxp(qsfp1_rx1_p), + .xcvr_rxn(qsfp1_rx1_n), + + // PHY connections + .phy_tx_clk(qsfp1_tx_clk_1_int), + .phy_tx_rst(qsfp1_tx_rst_1_int), + .phy_xgmii_txd(qsfp1_txd_1_int), + .phy_xgmii_txc(qsfp1_txc_1_int), + .phy_rx_clk(qsfp1_rx_clk_1_int), + .phy_rx_rst(qsfp1_rx_rst_1_int), + .phy_xgmii_rxd(qsfp1_rxd_1_int), + .phy_xgmii_rxc(qsfp1_rxc_1_int), + .phy_tx_bad_block(), + .phy_rx_error_count(qsfp1_rx_error_count_1_int), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp1_rx_block_lock_1), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(qsfp1_tx_prbs31_enable_1_int), + .phy_rx_prbs31_enable(qsfp1_rx_prbs31_enable_1_int) ); -assign qsfp1_tx_clk_2_int = clk_156mhz_int; -assign qsfp1_tx_rst_2_int = rst_156mhz_int; - -assign qsfp1_rx_clk_2_int = gt_rxusrclk[1]; - -sync_reset #( - .N(4) -) -qsfp1_rx_rst_2_reset_sync_inst ( - .clk(qsfp1_rx_clk_2_int), - .rst(~gt_reset_rx_done), - .out(qsfp1_rx_rst_2_int) -); - -eth_phy_10g #( - .BIT_REVERSE(1), +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), .PRBS31_ENABLE(1) ) qsfp1_phy_2_inst ( - .tx_clk(qsfp1_tx_clk_2_int), - .tx_rst(qsfp1_tx_rst_2_int), - .rx_clk(qsfp1_rx_clk_2_int), - .rx_rst(qsfp1_rx_rst_2_int), - .xgmii_txd(qsfp1_txd_2_int), - .xgmii_txc(qsfp1_txc_2_int), - .xgmii_rxd(qsfp1_rxd_2_int), - .xgmii_rxc(qsfp1_rxc_2_int), - .serdes_tx_data(qsfp1_gt_txdata_2), - .serdes_tx_hdr(qsfp1_gt_txheader_2), - .serdes_rx_data(qsfp1_gt_rxdata_2), - .serdes_rx_hdr(qsfp1_gt_rxheader_2), - .serdes_rx_bitslip(qsfp1_gt_rxgearboxslip_2), - .rx_error_count(qsfp1_rx_error_count_2_int), - .rx_block_lock(qsfp1_rx_block_lock_2), - .rx_high_ber(), - .tx_prbs31_enable(qsfp1_tx_prbs31_enable_2_int), - .rx_prbs31_enable(qsfp1_rx_prbs31_enable_2_int) + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(rst_125mhz_int), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp1_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp1_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp1_tx2_p), + .xcvr_txn(qsfp1_tx2_n), + .xcvr_rxp(qsfp1_rx2_p), + .xcvr_rxn(qsfp1_rx2_n), + + // PHY connections + .phy_tx_clk(qsfp1_tx_clk_2_int), + .phy_tx_rst(qsfp1_tx_rst_2_int), + .phy_xgmii_txd(qsfp1_txd_2_int), + .phy_xgmii_txc(qsfp1_txc_2_int), + .phy_rx_clk(qsfp1_rx_clk_2_int), + .phy_rx_rst(qsfp1_rx_rst_2_int), + .phy_xgmii_rxd(qsfp1_rxd_2_int), + .phy_xgmii_rxc(qsfp1_rxc_2_int), + .phy_tx_bad_block(), + .phy_rx_error_count(qsfp1_rx_error_count_2_int), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp1_rx_block_lock_2), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(qsfp1_tx_prbs31_enable_2_int), + .phy_rx_prbs31_enable(qsfp1_rx_prbs31_enable_2_int) ); -assign qsfp1_tx_clk_3_int = clk_156mhz_int; -assign qsfp1_tx_rst_3_int = rst_156mhz_int; - -assign qsfp1_rx_clk_3_int = gt_rxusrclk[2]; - -sync_reset #( - .N(4) -) -qsfp1_rx_rst_3_reset_sync_inst ( - .clk(qsfp1_rx_clk_3_int), - .rst(~gt_reset_rx_done), - .out(qsfp1_rx_rst_3_int) -); - -eth_phy_10g #( - .BIT_REVERSE(1), +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), .PRBS31_ENABLE(1) ) qsfp1_phy_3_inst ( - .tx_clk(qsfp1_tx_clk_3_int), - .tx_rst(qsfp1_tx_rst_3_int), - .rx_clk(qsfp1_rx_clk_3_int), - .rx_rst(qsfp1_rx_rst_3_int), - .xgmii_txd(qsfp1_txd_3_int), - .xgmii_txc(qsfp1_txc_3_int), - .xgmii_rxd(qsfp1_rxd_3_int), - .xgmii_rxc(qsfp1_rxc_3_int), - .serdes_tx_data(qsfp1_gt_txdata_3), - .serdes_tx_hdr(qsfp1_gt_txheader_3), - .serdes_rx_data(qsfp1_gt_rxdata_3), - .serdes_rx_hdr(qsfp1_gt_rxheader_3), - .serdes_rx_bitslip(qsfp1_gt_rxgearboxslip_3), - .rx_error_count(qsfp1_rx_error_count_3_int), - .rx_block_lock(qsfp1_rx_block_lock_3), - .rx_high_ber(), - .tx_prbs31_enable(qsfp1_tx_prbs31_enable_3_int), - .rx_prbs31_enable(qsfp1_rx_prbs31_enable_3_int) + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(rst_125mhz_int), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp1_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp1_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp1_tx3_p), + .xcvr_txn(qsfp1_tx3_n), + .xcvr_rxp(qsfp1_rx3_p), + .xcvr_rxn(qsfp1_rx3_n), + + // PHY connections + .phy_tx_clk(qsfp1_tx_clk_3_int), + .phy_tx_rst(qsfp1_tx_rst_3_int), + .phy_xgmii_txd(qsfp1_txd_3_int), + .phy_xgmii_txc(qsfp1_txc_3_int), + .phy_rx_clk(qsfp1_rx_clk_3_int), + .phy_rx_rst(qsfp1_rx_rst_3_int), + .phy_xgmii_rxd(qsfp1_rxd_3_int), + .phy_xgmii_rxc(qsfp1_rxc_3_int), + .phy_tx_bad_block(), + .phy_rx_error_count(qsfp1_rx_error_count_3_int), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp1_rx_block_lock_3), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(qsfp1_tx_prbs31_enable_3_int), + .phy_rx_prbs31_enable(qsfp1_rx_prbs31_enable_3_int) ); -assign qsfp1_tx_clk_4_int = clk_156mhz_int; -assign qsfp1_tx_rst_4_int = rst_156mhz_int; - -assign qsfp1_rx_clk_4_int = gt_rxusrclk[3]; - -sync_reset #( - .N(4) -) -qsfp1_rx_rst_4_reset_sync_inst ( - .clk(qsfp1_rx_clk_4_int), - .rst(~gt_reset_rx_done), - .out(qsfp1_rx_rst_4_int) -); - -eth_phy_10g #( - .BIT_REVERSE(1), +eth_xcvr_phy_wrapper #( + .HAS_COMMON(0), .PRBS31_ENABLE(1) ) qsfp1_phy_4_inst ( - .tx_clk(qsfp1_tx_clk_4_int), - .tx_rst(qsfp1_tx_rst_4_int), - .rx_clk(qsfp1_rx_clk_4_int), - .rx_rst(qsfp1_rx_rst_4_int), - .xgmii_txd(qsfp1_txd_4_int), - .xgmii_txc(qsfp1_txc_4_int), - .xgmii_rxd(qsfp1_rxd_4_int), - .xgmii_rxc(qsfp1_rxc_4_int), - .serdes_tx_data(qsfp1_gt_txdata_4), - .serdes_tx_hdr(qsfp1_gt_txheader_4), - .serdes_rx_data(qsfp1_gt_rxdata_4), - .serdes_rx_hdr(qsfp1_gt_rxheader_4), - .serdes_rx_bitslip(qsfp1_gt_rxgearboxslip_4), - .rx_error_count(qsfp1_rx_error_count_4_int), - .rx_block_lock(qsfp1_rx_block_lock_4), - .rx_high_ber(), - .tx_prbs31_enable(qsfp1_tx_prbs31_enable_4_int), - .rx_prbs31_enable(qsfp1_rx_prbs31_enable_4_int) + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(rst_125mhz_int), + + // Common + .xcvr_gtpowergood_out(), + + // PLL out + .xcvr_gtrefclk00_in(1'b0), + .xcvr_qpll0lock_out(), + .xcvr_qpll0outclk_out(), + .xcvr_qpll0outrefclk_out(), + + // PLL in + .xcvr_qpll0lock_in(qsfp1_qpll0lock), + .xcvr_qpll0reset_out(), + .xcvr_qpll0clk_in(qsfp1_qpll0outclk), + .xcvr_qpll0refclk_in(qsfp1_qpll0outrefclk), + + // Serial data + .xcvr_txp(qsfp1_tx4_p), + .xcvr_txn(qsfp1_tx4_n), + .xcvr_rxp(qsfp1_rx4_p), + .xcvr_rxn(qsfp1_rx4_n), + + // PHY connections + .phy_tx_clk(qsfp1_tx_clk_4_int), + .phy_tx_rst(qsfp1_tx_rst_4_int), + .phy_xgmii_txd(qsfp1_txd_4_int), + .phy_xgmii_txc(qsfp1_txc_4_int), + .phy_rx_clk(qsfp1_rx_clk_4_int), + .phy_rx_rst(qsfp1_rx_rst_4_int), + .phy_xgmii_rxd(qsfp1_rxd_4_int), + .phy_xgmii_rxc(qsfp1_rxc_4_int), + .phy_tx_bad_block(), + .phy_rx_error_count(qsfp1_rx_error_count_4_int), + .phy_rx_bad_block(), + .phy_rx_sequence_error(), + .phy_rx_block_lock(qsfp1_rx_block_lock_4), + .phy_rx_high_ber(), + .phy_tx_prbs31_enable(qsfp1_tx_prbs31_enable_4_int), + .phy_rx_prbs31_enable(qsfp1_rx_prbs31_enable_4_int) ); fpga_core #(