Add default_nettype none and resetall directives

example/ADM_PCIE_9V3/fpga_10g/rtl/debounce_switch.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes switch and button inputs with a slow sampled shift register
@@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin
 end
 
 endmodule
+
+`resetall

example/ADM_PCIE_9V3/fpga_10g/rtl/eth_xcvr_phy_wrapper.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * Transceiver and PHY wrapper
@@ -293,3 +295,5 @@ phy_inst (
 );
 
 endmodule
+
+`resetall

example/ADM_PCIE_9V3/fpga_10g/rtl/fpga.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA top-level module
@@ -782,3 +784,5 @@ core_inst (
 );
 
 endmodule
+
+`resetall

example/ADM_PCIE_9V3/fpga_10g/rtl/fpga_core.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA core logic
@@ -659,3 +661,5 @@ udp_payload_fifo (
 );
 
 endmodule
+
+`resetall

example/ADM_PCIE_9V3/fpga_10g/rtl/sync_signal.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an asyncronous signal to a given clock by using a pipeline of
@@ -56,3 +58,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/ADM_PCIE_9V3/fpga_25g/rtl/debounce_switch.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes switch and button inputs with a slow sampled shift register
@@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin
 end
 
 endmodule
+
+`resetall

example/ADM_PCIE_9V3/fpga_25g/rtl/eth_xcvr_phy_wrapper.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * Transceiver and PHY wrapper
@@ -293,3 +295,5 @@ phy_inst (
 );
 
 endmodule
+
+`resetall

example/ADM_PCIE_9V3/fpga_25g/rtl/fpga.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA top-level module
@@ -806,3 +808,5 @@ core_inst (
 );
 
 endmodule
+
+`resetall

example/ADM_PCIE_9V3/fpga_25g/rtl/fpga_core.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA core logic
@@ -659,3 +661,5 @@ udp_payload_fifo (
 );
 
 endmodule
+
+`resetall

example/ADM_PCIE_9V3/fpga_25g/rtl/sync_signal.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an asyncronous signal to a given clock by using a pipeline of
@@ -56,3 +58,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/ATLYS/fpga/rtl/debounce_switch.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes switch and button inputs with a slow sampled shift register
@@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin
 end
 
 endmodule
+
+`resetall

example/ATLYS/fpga/rtl/fpga.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA top-level module
@@ -222,3 +224,5 @@ core_inst (
 );
 
 endmodule
+
+`resetall

example/ATLYS/fpga/rtl/fpga_core.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA core logic
@@ -581,3 +583,5 @@ udp_payload_fifo (
 );
 
 endmodule
+
+`resetall

example/ATLYS/fpga/rtl/sync_signal.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an asyncronous signal to a given clock by using a pipeline of
@@ -56,3 +58,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/AU200/fpga_10g/rtl/debounce_switch.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes switch and button inputs with a slow sampled shift register
@@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin
 end
 
 endmodule
+
+`resetall

example/AU200/fpga_10g/rtl/eth_xcvr_phy_wrapper.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * Transceiver and PHY wrapper
@@ -293,3 +295,5 @@ phy_inst (
 );
 
 endmodule
+
+`resetall

example/AU200/fpga_10g/rtl/fpga.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA top-level module
@@ -898,3 +900,5 @@ core_inst (
 );
 
 endmodule
+
+`resetall

example/AU200/fpga_10g/rtl/fpga_core.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA core logic
@@ -662,3 +664,5 @@ udp_payload_fifo (
 );
 
 endmodule
+
+`resetall

example/AU200/fpga_10g/rtl/sync_signal.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an asyncronous signal to a given clock by using a pipeline of
@@ -56,3 +58,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/AU250/fpga_10g/rtl/debounce_switch.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes switch and button inputs with a slow sampled shift register
@@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin
 end
 
 endmodule
+
+`resetall

example/AU250/fpga_10g/rtl/eth_xcvr_phy_wrapper.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * Transceiver and PHY wrapper
@@ -293,3 +295,5 @@ phy_inst (
 );
 
 endmodule
+
+`resetall

example/AU250/fpga_10g/rtl/fpga.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA top-level module
@@ -898,3 +900,5 @@ core_inst (
 );
 
 endmodule
+
+`resetall

example/AU250/fpga_10g/rtl/fpga_core.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA core logic
@@ -662,3 +664,5 @@ udp_payload_fifo (
 );
 
 endmodule
+
+`resetall

example/AU250/fpga_10g/rtl/sync_signal.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an asyncronous signal to a given clock by using a pipeline of
@@ -56,3 +58,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/AU280/fpga_10g/rtl/eth_xcvr_phy_wrapper.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * Transceiver and PHY wrapper
@@ -293,3 +295,5 @@ phy_inst (
 );
 
 endmodule
+
+`resetall

example/AU280/fpga_10g/rtl/fpga.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA top-level module
@@ -762,3 +764,5 @@ core_inst (
 );
 
 endmodule
+
+`resetall

example/AU280/fpga_10g/rtl/fpga_core.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA core logic
@@ -647,3 +649,5 @@ udp_payload_fifo (
 );
 
 endmodule
+
+`resetall

example/AU280/fpga_10g/rtl/sync_signal.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an asyncronous signal to a given clock by using a pipeline of
@@ -56,3 +58,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/AU50/fpga_10g/rtl/eth_xcvr_phy_wrapper.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * Transceiver and PHY wrapper
@@ -293,3 +295,5 @@ phy_inst (
 );
 
 endmodule
+
+`resetall

example/AU50/fpga_10g/rtl/fpga.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA top-level module
@@ -464,3 +466,5 @@ core_inst (
 );
 
 endmodule
+
+`resetall

example/AU50/fpga_10g/rtl/fpga_core.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA core logic
@@ -614,3 +616,5 @@ udp_payload_fifo (
 );
 
 endmodule
+
+`resetall

example/AU50/fpga_10g/rtl/sync_signal.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an asyncronous signal to a given clock by using a pipeline of
@@ -56,3 +58,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/Arty/fpga/rtl/debounce_switch.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes switch and button inputs with a slow sampled shift register
@@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin
 end
 
 endmodule
+
+`resetall

example/Arty/fpga/rtl/fpga.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA top-level module
@@ -268,3 +270,5 @@ core_inst (
 );
 
 endmodule
+
+`resetall

example/Arty/fpga/rtl/fpga_core.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA core logic
@@ -588,3 +590,5 @@ udp_payload_fifo (
 );
 
 endmodule
+
+`resetall

example/Arty/fpga/rtl/sync_signal.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an asyncronous signal to a given clock by using a pipeline of
@@ -56,3 +58,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/C10LP/fpga/rtl/debounce_switch.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes switch and button inputs with a slow sampled shift register
@@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin
 end
 
 endmodule
+
+`resetall

example/C10LP/fpga/rtl/fpga.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA top-level module
@@ -230,3 +232,5 @@ core_inst (
 );
 
 endmodule
+
+`resetall

example/C10LP/fpga/rtl/fpga_core.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA core logic
@@ -565,3 +567,5 @@ udp_payload_fifo (
 );
 
 endmodule
+
+`resetall

example/C10LP/fpga/rtl/sync_signal.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an asyncronous signal to a given clock by using a pipeline of
@@ -56,3 +58,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/DE2-115/fpga/rtl/debounce_switch.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes switch and button inputs with a slow sampled shift register
@@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin
 end
 
 endmodule
+
+`resetall

example/DE2-115/fpga/rtl/fpga.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA top-level module
@@ -263,3 +265,5 @@ core_inst (
 );
 
 endmodule
+
+`resetall

example/DE2-115/fpga/rtl/fpga_core.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA core logic
@@ -673,3 +675,5 @@ udp_payload_fifo (
 );
 
 endmodule
+
+`resetall

example/DE2-115/fpga/rtl/hex_display.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * 7 segment display hexadecimal encoding
@@ -68,3 +70,5 @@ end
 assign out = INVERT ? ~enc : enc;
 
 endmodule
+
+`resetall

example/DE2-115/fpga/rtl/sync_signal.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an asyncronous signal to a given clock by using a pipeline of
@@ -56,3 +58,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/DE5-Net/fpga/rtl/debounce_switch.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes switch and button inputs with a slow sampled shift register
@@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin
 end
 
 endmodule
+
+`resetall

example/DE5-Net/fpga/rtl/fpga.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA top-level module
@@ -468,3 +470,5 @@ core_inst (
 );
 
 endmodule
+
+`resetall

example/DE5-Net/fpga/rtl/fpga_core.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA core logic
@@ -612,3 +614,5 @@ udp_payload_fifo (
 );
 
 endmodule
+
+`resetall

example/DE5-Net/fpga/rtl/i2c_master.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * I2C master
@@ -893,3 +895,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/DE5-Net/fpga/rtl/si570_i2c_init.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * si570_i2c_init
@@ -453,3 +455,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/DE5-Net/fpga/rtl/sync_signal.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an asyncronous signal to a given clock by using a pipeline of
@@ -56,3 +58,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/ExaNIC_X10/fpga/rtl/eth_xcvr_phy_wrapper.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * Transceiver and PHY wrapper
@@ -301,3 +303,5 @@ phy_inst (
 );
 
 endmodule
+
+`resetall

example/ExaNIC_X10/fpga/rtl/fpga.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA top-level module
@@ -349,3 +351,5 @@ core_inst (
 );
 
 endmodule
+
+`resetall

example/ExaNIC_X10/fpga/rtl/fpga_core.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA core logic
@@ -592,3 +594,5 @@ udp_payload_fifo (
 );
 
 endmodule
+
+`resetall

example/ExaNIC_X10/fpga/rtl/sync_signal.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an asyncronous signal to a given clock by using a pipeline of
@@ -56,3 +58,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/ExaNIC_X25/fpga_10g/rtl/eth_xcvr_phy_wrapper.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * Transceiver and PHY wrapper
@@ -301,3 +303,5 @@ phy_inst (
 );
 
 endmodule
+
+`resetall

example/ExaNIC_X25/fpga_10g/rtl/fpga.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA top-level module
@@ -349,3 +351,5 @@ core_inst (
 );
 
 endmodule
+
+`resetall

example/ExaNIC_X25/fpga_10g/rtl/fpga_core.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA core logic
@@ -592,3 +594,5 @@ udp_payload_fifo (
 );
 
 endmodule
+
+`resetall

example/ExaNIC_X25/fpga_10g/rtl/sync_signal.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an asyncronous signal to a given clock by using a pipeline of
@@ -56,3 +58,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/HTG9200/fpga_10g/rtl/debounce_switch.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes switch and button inputs with a slow sampled shift register
@@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin
 end
 
 endmodule
+
+`resetall

example/HTG9200/fpga_10g/rtl/eth_xcvr_phy_wrapper.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * Transceiver and PHY wrapper
@@ -293,3 +295,5 @@ phy_inst (
 );
 
 endmodule
+
+`resetall

example/HTG9200/fpga_10g/rtl/fpga.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA top-level module
@@ -2845,3 +2847,5 @@ core_inst (
 );
 
 endmodule
+
+`resetall

example/HTG9200/fpga_10g/rtl/fpga_core.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA core logic
@@ -955,3 +957,5 @@ udp_payload_fifo (
 );
 
 endmodule
+
+`resetall

example/HTG9200/fpga_10g/rtl/i2c_master.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * I2C master
@@ -895,3 +897,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/HTG9200/fpga_10g/rtl/si5341_i2c_init.py

@@ -130,7 +130,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * {{name}}
@@ -581,6 +583,8 @@ end
 
 endmodule
 
+`resetall
+
 """)
 
     print(f"Writing file '{output}'...")

example/HTG9200/fpga_10g/rtl/si5341_i2c_init.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * si5341_i2c_init
@@ -1035,3 +1037,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/HTG9200/fpga_10g/rtl/sync_signal.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an asyncronous signal to a given clock by using a pipeline of
@@ -56,3 +58,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/HXT100G/fpga/rtl/debounce_switch.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes switch and button inputs with a slow sampled shift register
@@ -87,3 +89,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/HXT100G/fpga/rtl/eth_gth_phy_quad.v

@@ -22,6 +22,12 @@ THE SOFTWARE.
 
 */
 
+// Language: Verilog 2001
+
+`resetall
+`timescale 1 ns / 1 ps
+`default_nettype none
+
 module eth_gth_phy_quad (
     /*
      * Clock and reset
@@ -567,3 +573,5 @@ mgmt_arb_inst
 );
 
 endmodule
+
+`resetall

example/HXT100G/fpga/rtl/fpga.v

@@ -22,6 +22,12 @@ THE SOFTWARE.
 
 */
 
+// Language: Verilog 2001
+
+`resetall
+`timescale 1 ns / 1 ps
+`default_nettype none
+
 module fpga (
     /*
      * Clock: 50MHz
@@ -1129,3 +1135,5 @@ core_inst (
 );
 
 endmodule
+
+`resetall

example/HXT100G/fpga/rtl/fpga_core.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 module fpga_core
 (
@@ -756,3 +758,5 @@ udp_payload_fifo (
 );
 
 endmodule
+
+`resetall

example/HXT100G/fpga/rtl/gth_i2c_init.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * gth_i2c_init
@@ -506,3 +508,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/HXT100G/fpga/rtl/i2c_master.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * I2C master
@@ -893,3 +895,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/HXT100G/fpga/rtl/sync_signal.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an asyncronous signal to a given clock by using a pipeline of
@@ -56,3 +58,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/HXT100G/fpga_cxpt16/rtl/debounce_switch.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes switch and button inputs with a slow sampled shift register
@@ -87,3 +89,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/HXT100G/fpga_cxpt16/rtl/eth_gth_phy_quad.v

@@ -22,6 +22,12 @@ THE SOFTWARE.
 
 */
 
+// Language: Verilog 2001
+
+`resetall
+`timescale 1 ns / 1 ps
+`default_nettype none
+
 module eth_gth_phy_quad (
     /*
      * Clock and reset
@@ -567,3 +573,5 @@ mgmt_arb_inst
 );
 
 endmodule
+
+`resetall

example/HXT100G/fpga_cxpt16/rtl/fpga.v

@@ -22,6 +22,12 @@ THE SOFTWARE.
 
 */
 
+// Language: Verilog 2001
+
+`resetall
+`timescale 1 ns / 1 ps
+`default_nettype none
+
 module fpga (
     /*
      * Clock: 50MHz
@@ -1129,3 +1135,5 @@ core_inst (
 );
 
 endmodule
+
+`resetall

example/HXT100G/fpga_cxpt16/rtl/fpga_core.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 module fpga_core
 (
@@ -459,3 +461,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/HXT100G/fpga_cxpt16/rtl/gth_i2c_init.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * gth_i2c_init
@@ -506,3 +508,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/HXT100G/fpga_cxpt16/rtl/i2c_master.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * I2C master
@@ -893,3 +895,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/HXT100G/fpga_cxpt16/rtl/sync_signal.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an asyncronous signal to a given clock by using a pipeline of
@@ -56,3 +58,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/KC705/fpga_gmii/rtl/debounce_switch.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes switch and button inputs with a slow sampled shift register
@@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin
 end
 
 endmodule
+
+`resetall

example/KC705/fpga_gmii/rtl/fpga.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA top-level module
@@ -253,3 +255,5 @@ core_inst (
 );
 
 endmodule
+
+`resetall

example/KC705/fpga_gmii/rtl/fpga_core.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA core logic
@@ -585,3 +587,5 @@ udp_payload_fifo (
 );
 
 endmodule
+
+`resetall

example/KC705/fpga_gmii/rtl/sync_signal.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an asyncronous signal to a given clock by using a pipeline of
@@ -56,3 +58,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/KC705/fpga_rgmii/rtl/debounce_switch.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes switch and button inputs with a slow sampled shift register
@@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin
 end
 
 endmodule
+
+`resetall

example/KC705/fpga_rgmii/rtl/fpga.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA top-level module
@@ -369,3 +371,5 @@ core_inst (
 );
 
 endmodule
+
+`resetall

example/KC705/fpga_rgmii/rtl/fpga_core.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA core logic
@@ -582,3 +584,5 @@ udp_payload_fifo (
 );
 
 endmodule
+
+`resetall

example/KC705/fpga_rgmii/rtl/sync_signal.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an asyncronous signal to a given clock by using a pipeline of
@@ -56,3 +58,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/KC705/fpga_sgmii/rtl/debounce_switch.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes switch and button inputs with a slow sampled shift register
@@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin
 end
 
 endmodule
+
+`resetall

example/KC705/fpga_sgmii/rtl/fpga.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA top-level module
@@ -363,3 +365,5 @@ core_inst (
 );
 
 endmodule
+
+`resetall

example/KC705/fpga_sgmii/rtl/fpga_core.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA core logic
@@ -582,3 +584,5 @@ udp_payload_fifo (
 );
 
 endmodule
+
+`resetall

example/KC705/fpga_sgmii/rtl/sync_signal.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an asyncronous signal to a given clock by using a pipeline of
@@ -56,3 +58,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/ML605/fpga_gmii/rtl/debounce_switch.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes switch and button inputs with a slow sampled shift register
@@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin
 end
 
 endmodule
+
+`resetall

example/ML605/fpga_gmii/rtl/fpga.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA top-level module
@@ -279,3 +281,5 @@ core_inst (
 );
 
 endmodule
+
+`resetall

example/ML605/fpga_gmii/rtl/fpga_core.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA core logic
@@ -594,3 +596,5 @@ udp_payload_fifo (
 );
 
 endmodule
+
+`resetall

example/ML605/fpga_gmii/rtl/sync_signal.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes an asyncronous signal to a given clock by using a pipeline of
@@ -56,3 +58,5 @@ always @(posedge clk) begin
 end
 
 endmodule
+
+`resetall

example/ML605/fpga_rgmii/rtl/debounce_switch.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog-2001
 
+`resetall
 `timescale 1 ns / 1 ps
+`default_nettype none
 
 /*
  * Synchronizes switch and button inputs with a slow sampled shift register
@@ -87,3 +89,5 @@ always @(posedge clk or posedge rst) begin
 end
 
 endmodule
+
+`resetall

example/ML605/fpga_rgmii/rtl/fpga.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA top-level module
@@ -282,3 +284,5 @@ core_inst (
 );
 
 endmodule
+
+`resetall

example/ML605/fpga_rgmii/rtl/fpga_core.v

@@ -24,7 +24,9 @@ THE SOFTWARE.
 
 // Language: Verilog 2001
 
+`resetall
 `timescale 1ns / 1ps
+`default_nettype none
 
 /*
  * FPGA core logic
@@ -591,3 +593,5 @@ udp_payload_fifo (
 );
 
 endmodule
+
+`resetall