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Assert header ready earlier if possible

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This commit is contained in:
Alex Forencich 2018-11-07 23:10:07 -08:00
parent b223c94adb
commit 6b1b36ded6
12 changed files with 49 additions and 49 deletions
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6
rtl/arp_eth_rx.v
View File

@ -227,7 +227,7 @@ always @* begin
STATE_IDLE: begin
// idle state - wait for data
frame_ptr_next = 8'd0;
s_eth_hdr_ready_next = !m_frame_valid_reg;
s_eth_hdr_ready_next = !m_frame_valid_next;
if (s_eth_hdr_ready && s_eth_hdr_valid) begin
s_eth_hdr_ready_next = 1'b0;
@ -291,7 +291,7 @@ always @* begin
// otherwise, transfer tuser
m_frame_valid_next = !s_eth_payload_axis_tuser;
end
s_eth_hdr_ready_next = !m_frame_valid_reg;
s_eth_hdr_ready_next = !m_frame_valid_next;
s_eth_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end
@ -312,7 +312,7 @@ always @* begin
// otherwise, transfer tuser
m_frame_valid_next = !s_eth_payload_axis_tuser;
end
s_eth_hdr_ready_next = !m_frame_valid_reg;
s_eth_hdr_ready_next = !m_frame_valid_next;
s_eth_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin

6
rtl/arp_eth_rx_64.v
View File

@ -180,7 +180,7 @@ always @* begin
STATE_IDLE: begin
// idle state - wait for data
frame_ptr_next = 8'd0;
s_eth_hdr_ready_next = !m_frame_valid_reg;
s_eth_hdr_ready_next = !m_frame_valid_next;
if (s_eth_hdr_ready && s_eth_hdr_valid) begin
s_eth_hdr_ready_next = 1'b0;
@ -216,7 +216,7 @@ always @* begin
end else begin
m_frame_valid_next = !s_eth_payload_axis_tuser;
end
s_eth_hdr_ready_next = !m_frame_valid_reg;
s_eth_hdr_ready_next = !m_frame_valid_next;
s_eth_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end
@ -237,7 +237,7 @@ always @* begin
// otherwise, transfer tuser
m_frame_valid_next = !s_eth_payload_axis_tuser;
end
s_eth_hdr_ready_next = !m_frame_valid_reg;
s_eth_hdr_ready_next = !m_frame_valid_next;
s_eth_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin

4
rtl/arp_eth_tx.v
View File

@ -158,7 +158,7 @@ always @* begin
STATE_IDLE: begin
// idle state - wait for data
frame_ptr_next = 8'd0;
s_frame_ready_next = !m_eth_hdr_valid_reg;
s_frame_ready_next = !m_eth_hdr_valid_next;
if (s_frame_ready && s_frame_valid) begin
store_frame = 1'b1;
@ -212,7 +212,7 @@ always @* begin
8'h1B: begin
m_eth_payload_axis_tdata_int = arp_tpa_reg[ 7: 0];
m_eth_payload_axis_tlast_int = 1'b1;
s_frame_ready_next = !m_eth_hdr_valid_reg;
s_frame_ready_next = !m_eth_hdr_valid_next;
state_next = STATE_IDLE;
end
endcase

4
rtl/arp_eth_tx_64.v
View File

@ -161,7 +161,7 @@ always @* begin
STATE_IDLE: begin
// idle state - wait for data
frame_ptr_next = 8'd0;
s_frame_ready_next = !m_eth_hdr_valid_reg;
s_frame_ready_next = !m_eth_hdr_valid_next;
if (s_frame_ready && s_frame_valid) begin
store_frame = 1'b1;
@ -237,7 +237,7 @@ always @* begin
m_eth_payload_axis_tdata_int[63:56] = 0;
m_eth_payload_axis_tkeep_int = 8'h0f;
m_eth_payload_axis_tlast_int = 1'b1;
s_frame_ready_next = !m_eth_hdr_valid_reg;
s_frame_ready_next = !m_eth_hdr_valid_next;
state_next = STATE_IDLE;
end
endcase

10
rtl/ip_eth_rx.v
View File

@ -277,7 +277,7 @@ always @* begin
// idle state - wait for header
frame_ptr_next = 16'd0;
hdr_sum_next = 16'd0;
s_eth_hdr_ready_next = !m_ip_hdr_valid_reg;
s_eth_hdr_ready_next = !m_ip_hdr_valid_next;
if (s_eth_hdr_ready && s_eth_hdr_valid) begin
s_eth_hdr_ready_next = 1'b0;
@ -342,7 +342,7 @@ always @* begin
if (s_eth_payload_axis_tlast) begin
error_header_early_termination_next = 1'b1;
m_ip_hdr_valid_next = 1'b0;
s_eth_hdr_ready_next = !m_ip_hdr_valid_reg;
s_eth_hdr_ready_next = !m_ip_hdr_valid_next;
s_eth_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end
@ -369,7 +369,7 @@ always @* begin
m_ip_payload_axis_tuser_int = 1'b1;
error_payload_early_termination_next = 1'b1;
end
s_eth_hdr_ready_next = !m_ip_hdr_valid_reg;
s_eth_hdr_ready_next = !m_ip_hdr_valid_next;
s_eth_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin
@ -396,7 +396,7 @@ always @* begin
if (s_eth_payload_axis_tready && s_eth_payload_axis_tvalid) begin
if (s_eth_payload_axis_tlast) begin
s_eth_hdr_ready_next = !m_ip_hdr_valid_reg;
s_eth_hdr_ready_next = !m_ip_hdr_valid_next;
s_eth_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin
@ -412,7 +412,7 @@ always @* begin
if (s_eth_payload_axis_tready && s_eth_payload_axis_tvalid) begin
if (s_eth_payload_axis_tlast) begin
s_eth_hdr_ready_next = !m_ip_hdr_valid_reg;
s_eth_hdr_ready_next = !m_ip_hdr_valid_next;
s_eth_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin

8
rtl/ip_eth_rx_64.v
View File

@ -315,7 +315,7 @@ always @* begin
frame_ptr_next = 16'd0;
hdr_sum_next = 32'd0;
flush_save = 1'b1;
s_eth_hdr_ready_next = !m_ip_hdr_valid_reg;
s_eth_hdr_ready_next = !m_ip_hdr_valid_next;
if (s_eth_hdr_ready && s_eth_hdr_valid) begin
s_eth_hdr_ready_next = 1'b0;
@ -378,7 +378,7 @@ always @* begin
error_invalid_header_next = 1'b0;
error_invalid_checksum_next = 1'b0;
m_ip_hdr_valid_next = 1'b0;
s_eth_hdr_ready_next = !m_ip_hdr_valid_reg;
s_eth_hdr_ready_next = !m_ip_hdr_valid_next;
s_eth_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end
@ -472,7 +472,7 @@ always @* begin
if (shift_eth_payload_axis_tlast) begin
s_eth_payload_axis_tready_next = 1'b0;
flush_save = 1'b1;
s_eth_hdr_ready_next = 1'b1;
s_eth_hdr_ready_next = !m_ip_hdr_valid_next;
state_next = STATE_IDLE;
end else begin
state_next = STATE_READ_PAYLOAD_LAST;
@ -490,7 +490,7 @@ always @* begin
if (shift_eth_payload_axis_tlast) begin
s_eth_payload_axis_tready_next = 1'b0;
flush_save = 1'b1;
s_eth_hdr_ready_next = 1'b1;
s_eth_hdr_ready_next = !m_ip_hdr_valid_next;
state_next = STATE_IDLE;
end else begin
state_next = STATE_WAIT_LAST;

8
rtl/ip_eth_tx.v
View File

@ -206,7 +206,7 @@ always @* begin
STATE_IDLE: begin
// idle state - wait for data
frame_ptr_next = 16'd0;
s_ip_hdr_ready_next = !m_eth_hdr_valid_reg;
s_ip_hdr_ready_next = !m_eth_hdr_valid_next;
if (s_ip_hdr_ready && s_ip_hdr_valid) begin
store_ip_hdr = 1'b1;
@ -305,7 +305,7 @@ always @* begin
m_eth_payload_axis_tuser_int = 1'b1;
error_payload_early_termination_next = 1'b1;
end
s_ip_hdr_ready_next = !m_eth_hdr_valid_reg;
s_ip_hdr_ready_next = !m_eth_hdr_valid_next;
s_ip_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin
@ -332,7 +332,7 @@ always @* begin
if (s_ip_payload_axis_tready && s_ip_payload_axis_tvalid) begin
if (s_ip_payload_axis_tlast) begin
s_ip_hdr_ready_next = !m_eth_hdr_valid_reg;
s_ip_hdr_ready_next = !m_eth_hdr_valid_next;
s_ip_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin
@ -348,7 +348,7 @@ always @* begin
if (s_ip_payload_axis_tready && s_ip_payload_axis_tvalid) begin
if (s_ip_payload_axis_tlast) begin
s_ip_hdr_ready_next = !m_eth_hdr_valid_reg;
s_ip_hdr_ready_next = !m_eth_hdr_valid_next;
s_ip_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin

12
rtl/ip_eth_tx_64.v
View File

@ -277,7 +277,7 @@ always @* begin
// idle state - wait for data
frame_ptr_next = 16'd0;
flush_save = 1'b1;
s_ip_hdr_ready_next = !m_eth_hdr_valid_reg;
s_ip_hdr_ready_next = !m_eth_hdr_valid_next;
if (s_ip_hdr_ready && s_ip_hdr_valid) begin
store_ip_hdr = 1'b1;
@ -374,7 +374,7 @@ always @* begin
frame_ptr_next = ip_length_reg;
m_eth_payload_axis_tkeep_int = count2keep(ip_length_reg - frame_ptr_reg);
if (shift_ip_payload_axis_tlast) begin
s_ip_hdr_ready_next = !m_eth_hdr_valid_reg;
s_ip_hdr_ready_next = !m_eth_hdr_valid_next;
s_ip_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin
@ -419,7 +419,7 @@ always @* begin
if (shift_ip_payload_axis_tlast) begin
s_ip_payload_axis_tready_next = 1'b0;
flush_save = 1'b1;
s_ip_hdr_ready_next = !m_eth_hdr_valid_reg;
s_ip_hdr_ready_next = !m_eth_hdr_valid_next;
state_next = STATE_IDLE;
end else begin
store_last_word = 1'b1;
@ -433,7 +433,7 @@ always @* begin
m_eth_payload_axis_tuser_int = 1'b1;
s_ip_payload_axis_tready_next = 1'b0;
flush_save = 1'b1;
s_ip_hdr_ready_next = !m_eth_hdr_valid_reg;
s_ip_hdr_ready_next = !m_eth_hdr_valid_next;
state_next = STATE_IDLE;
end else begin
state_next = STATE_WRITE_PAYLOAD;
@ -456,7 +456,7 @@ always @* begin
if (m_eth_payload_axis_tready_int_reg && shift_ip_payload_axis_tvalid) begin
transfer_in_save = 1'b1;
if (shift_ip_payload_axis_tlast) begin
s_ip_hdr_ready_next = !m_eth_hdr_valid_reg;
s_ip_hdr_ready_next = !m_eth_hdr_valid_next;
s_ip_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin
@ -473,7 +473,7 @@ always @* begin
if (shift_ip_payload_axis_tvalid) begin
transfer_in_save = 1'b1;
if (shift_ip_payload_axis_tlast) begin
s_ip_hdr_ready_next = !m_eth_hdr_valid_reg;
s_ip_hdr_ready_next = !m_eth_hdr_valid_next;
s_ip_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin

10
rtl/udp_ip_rx.v
View File

@ -262,7 +262,7 @@ always @* begin
STATE_IDLE: begin
// idle state - wait for header
frame_ptr_next = 16'd0;
s_ip_hdr_ready_next = !m_udp_hdr_valid_reg;
s_ip_hdr_ready_next = !m_udp_hdr_valid_next;
if (s_ip_hdr_ready && s_ip_hdr_valid) begin
s_ip_hdr_ready_next = 1'b0;
@ -301,7 +301,7 @@ always @* begin
if (s_ip_payload_axis_tlast) begin
error_header_early_termination_next = 1'b1;
m_udp_hdr_valid_next = 1'b0;
s_ip_hdr_ready_next = !m_udp_hdr_valid_reg;
s_ip_hdr_ready_next = !m_udp_hdr_valid_next;
s_ip_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end
@ -328,7 +328,7 @@ always @* begin
m_udp_payload_axis_tuser_int = 1'b1;
error_payload_early_termination_next = 1'b1;
end
s_ip_hdr_ready_next = !m_udp_hdr_valid_reg;
s_ip_hdr_ready_next = !m_udp_hdr_valid_next;
s_ip_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin
@ -355,7 +355,7 @@ always @* begin
if (s_ip_payload_axis_tready && s_ip_payload_axis_tvalid) begin
if (s_ip_payload_axis_tlast) begin
s_ip_hdr_ready_next = !m_udp_hdr_valid_reg;
s_ip_hdr_ready_next = !m_udp_hdr_valid_next;
s_ip_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin
@ -371,7 +371,7 @@ always @* begin
if (s_ip_payload_axis_tready && s_ip_payload_axis_tvalid) begin
if (s_ip_payload_axis_tlast) begin
s_ip_hdr_ready_next = !m_udp_hdr_valid_reg;
s_ip_hdr_ready_next = !m_udp_hdr_valid_next;
s_ip_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin

12
rtl/udp_ip_rx_64.v
View File

@ -283,7 +283,7 @@ always @* begin
STATE_IDLE: begin
// idle state - wait for header
frame_ptr_next = 16'd0;
s_ip_hdr_ready_next = !m_udp_hdr_valid_reg;
s_ip_hdr_ready_next = !m_udp_hdr_valid_next;
if (s_ip_hdr_ready && s_ip_hdr_valid) begin
s_ip_hdr_ready_next = 1'b0;
@ -315,7 +315,7 @@ always @* begin
if (s_ip_payload_axis_tlast) begin
error_header_early_termination_next = 1'b1;
m_udp_hdr_valid_next = 1'b0;
s_ip_hdr_ready_next = !m_udp_hdr_valid_reg;
s_ip_hdr_ready_next = !m_udp_hdr_valid_next;
s_ip_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end
@ -343,7 +343,7 @@ always @* begin
m_udp_payload_axis_tkeep_int = s_ip_payload_axis_tkeep & count2keep(m_udp_length_reg - frame_ptr_reg);
if (s_ip_payload_axis_tlast) begin
s_ip_payload_axis_tready_next = 1'b0;
s_ip_hdr_ready_next = !m_udp_hdr_valid_reg;
s_ip_hdr_ready_next = !m_udp_hdr_valid_next;
state_next = STATE_IDLE;
end else begin
store_last_word = 1'b1;
@ -356,7 +356,7 @@ always @* begin
error_payload_early_termination_next = 1'b1;
m_udp_payload_axis_tuser_int = 1'b1;
s_ip_payload_axis_tready_next = 1'b0;
s_ip_hdr_ready_next = !m_udp_hdr_valid_reg;
s_ip_hdr_ready_next = !m_udp_hdr_valid_next;
state_next = STATE_IDLE;
end else begin
state_next = STATE_READ_PAYLOAD;
@ -378,7 +378,7 @@ always @* begin
if (s_ip_payload_axis_tready && s_ip_payload_axis_tvalid) begin
if (s_ip_payload_axis_tlast) begin
s_ip_hdr_ready_next = !m_udp_hdr_valid_reg;
s_ip_hdr_ready_next = !m_udp_hdr_valid_next;
s_ip_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin
@ -394,7 +394,7 @@ always @* begin
if (s_ip_payload_axis_tready && s_ip_payload_axis_tvalid) begin
if (s_ip_payload_axis_tlast) begin
s_ip_hdr_ready_next = !m_udp_hdr_valid_reg;
s_ip_hdr_ready_next = !m_udp_hdr_valid_next;
s_ip_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin

8
rtl/udp_ip_tx.v
View File

@ -237,7 +237,7 @@ always @* begin
STATE_IDLE: begin
// idle state - wait for data
frame_ptr_next = 16'd0;
s_udp_hdr_ready_next = !m_ip_hdr_valid_reg;
s_udp_hdr_ready_next = !m_ip_hdr_valid_next;
if (s_udp_hdr_ready && s_udp_hdr_valid) begin
store_udp_hdr = 1'b1;
@ -296,7 +296,7 @@ always @* begin
m_ip_payload_axis_tuser_int = 1'b1;
error_payload_early_termination_next = 1'b1;
end
s_udp_hdr_ready_next = !m_ip_hdr_valid_reg;
s_udp_hdr_ready_next = !m_ip_hdr_valid_next;
s_udp_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin
@ -323,7 +323,7 @@ always @* begin
if (s_udp_payload_axis_tready && s_udp_payload_axis_tvalid) begin
if (s_udp_payload_axis_tlast) begin
s_udp_hdr_ready_next = !m_ip_hdr_valid_reg;
s_udp_hdr_ready_next = !m_ip_hdr_valid_next;
s_udp_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin
@ -339,7 +339,7 @@ always @* begin
if (s_udp_payload_axis_tvalid) begin
if (s_udp_payload_axis_tlast) begin
s_udp_hdr_ready_next = !m_ip_hdr_valid_reg;
s_udp_hdr_ready_next = !m_ip_hdr_valid_next;
s_udp_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin

10
rtl/udp_ip_tx_64.v
View File

@ -272,7 +272,7 @@ always @* begin
STATE_IDLE: begin
// idle state - wait for data
frame_ptr_next = 16'd0;
s_udp_hdr_ready_next = !m_ip_hdr_valid_reg;
s_udp_hdr_ready_next = !m_ip_hdr_valid_next;
if (s_udp_hdr_ready && s_udp_hdr_valid) begin
store_udp_hdr = 1'b1;
@ -343,7 +343,7 @@ always @* begin
m_ip_payload_axis_tkeep_int = count2keep(udp_length_reg - frame_ptr_reg);
if (s_udp_payload_axis_tlast) begin
s_udp_payload_axis_tready_next = 1'b0;
s_udp_hdr_ready_next = !m_ip_hdr_valid_reg;
s_udp_hdr_ready_next = !m_ip_hdr_valid_next;
state_next = STATE_IDLE;
end else begin
store_last_word = 1'b1;
@ -356,7 +356,7 @@ always @* begin
error_payload_early_termination_next = 1'b1;
m_ip_payload_axis_tuser_int = 1'b1;
s_udp_payload_axis_tready_next = 1'b0;
s_udp_hdr_ready_next = !m_ip_hdr_valid_reg;
s_udp_hdr_ready_next = !m_ip_hdr_valid_next;
state_next = STATE_IDLE;
end else begin
state_next = STATE_WRITE_PAYLOAD;
@ -378,7 +378,7 @@ always @* begin
if (s_udp_payload_axis_tready && s_udp_payload_axis_tvalid) begin
if (s_udp_payload_axis_tlast) begin
s_udp_hdr_ready_next = !m_ip_hdr_valid_reg;
s_udp_hdr_ready_next = !m_ip_hdr_valid_next;
s_udp_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin
@ -394,7 +394,7 @@ always @* begin
if (s_udp_payload_axis_tvalid) begin
if (s_udp_payload_axis_tlast) begin
s_udp_hdr_ready_next = !m_ip_hdr_valid_reg;
s_udp_hdr_ready_next = !m_ip_hdr_valid_next;
s_udp_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin