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Add VCU118 + HTG 6x QSFP28 example design
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
parent
31901754a6
commit
6bf727d3ef
30
example/VCU118/fpga_fmc_htg_6qsfp_25g/README.md
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example/VCU118/fpga_fmc_htg_6qsfp_25g/README.md
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# Verilog Ethernet VCU118 + HTG 6x QSFP28 FMC+ Example Design
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## Introduction
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This example design targets the Xilinx VCU118 FPGA board with the HiTech Global HTG-FMC-X6QSFP28 FMC+ board installed on J22.
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The design by default listens to UDP port 1234 at IP address 192.168.1.128 and will echo back any packets received. The design will also respond correctly to ARP requests. The design also enables the gigabit Ethernet interface for testing with a QSFP loopback adapter.
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The design is configured to run all 8 QSFP28 modules synchronous to the QSFP Si570 (U38) on the VCU118. This is done by forwarding the MGT reference clock for QSFP1 through the FPGA to the SYNC_C2M pins on the FMC+, which is connected as a reference input to the Si5341 PLL (U7) on the FMC+.
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* FPGA: xcvu9p-flga2104-2L-e
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* PHY: 25G BASE-R PHY IP core and internal GTY transceiver
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## How to build
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Run make to build. Ensure that the Xilinx Vivado toolchain components are in PATH.
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## How to test
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Run make program to program the VCU118 board with Vivado. Then run
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netcat -u 192.168.1.128 1234
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to open a UDP connection to port 1234. Any text entered into netcat will be echoed back after pressing enter.
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It is also possible to use hping to test the design by running
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hping 192.168.1.128 -2 -p 1234 -d 1024
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Note that the gigabit PHY is also enabled for debugging. The gigabit port can be inserted into the 25G data path between the 25G MAC and 25G PHY so that the 25G interface can be tested with a QSFP loopback adapter. Turn on SW12.1 to insert the gigabit port into the 25G data path, or off to bypass the gigabit port. Turn on SW12.2 to place the port in the TX path or off to place the port in the RX path.
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137
example/VCU118/fpga_fmc_htg_6qsfp_25g/common/vivado.mk
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example/VCU118/fpga_fmc_htg_6qsfp_25g/common/vivado.mk
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###################################################################
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#
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# Xilinx Vivado FPGA Makefile
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#
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# Copyright (c) 2016 Alex Forencich
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#
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###################################################################
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#
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# Parameters:
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# FPGA_TOP - Top module name
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# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
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# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
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# SYN_FILES - space-separated list of source files
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# INC_FILES - space-separated list of include files
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# XDC_FILES - space-separated list of timing constraint files
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# XCI_FILES - space-separated list of IP XCI files
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#
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# Example:
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#
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# FPGA_TOP = fpga
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# FPGA_FAMILY = VirtexUltrascale
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# FPGA_DEVICE = xcvu095-ffva2104-2-e
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# SYN_FILES = rtl/fpga.v
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# XDC_FILES = fpga.xdc
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# XCI_FILES = ip/pcspma.xci
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# include ../common/vivado.mk
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#
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###################################################################
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# phony targets
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.PHONY: fpga vivado tmpclean clean distclean
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# prevent make from deleting intermediate files and reports
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.PRECIOUS: %.xpr %.bit %.mcs %.prm
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.SECONDARY:
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CONFIG ?= config.mk
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-include ../$(CONFIG)
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FPGA_TOP ?= fpga
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PROJECT ?= $(FPGA_TOP)
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SYN_FILES_REL = $(foreach p,$(SYN_FILES),$(if $(filter /% ./%,$p),$p,../$p))
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INC_FILES_REL = $(foreach p,$(INC_FILES),$(if $(filter /% ./%,$p),$p,../$p))
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XCI_FILES_REL = $(foreach p,$(XCI_FILES),$(if $(filter /% ./%,$p),$p,../$p))
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IP_TCL_FILES_REL = $(foreach p,$(IP_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p))
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CONFIG_TCL_FILES_REL = $(foreach p,$(CONFIG_TCL_FILES),$(if $(filter /% ./%,$p),$p,../$p))
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ifdef XDC_FILES
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XDC_FILES_REL = $(foreach p,$(XDC_FILES),$(if $(filter /% ./%,$p),$p,../$p))
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else
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XDC_FILES_REL = $(PROJECT).xdc
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endif
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###################################################################
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# Main Targets
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#
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# all: build everything
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# clean: remove output files and project files
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###################################################################
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all: fpga
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fpga: $(PROJECT).bit
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vivado: $(PROJECT).xpr
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vivado $(PROJECT).xpr
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tmpclean::
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-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
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-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
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clean:: tmpclean
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-rm -rf *.bit *.ltx program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
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-rm -rf *_utilization.rpt *_utilization_hierarchical.rpt
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distclean:: clean
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-rm -rf rev
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###################################################################
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# Target implementations
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###################################################################
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# Vivado project file
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create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL)
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rm -rf defines.v
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touch defines.v
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for x in $(DEFS); do echo '`define' $$x >> defines.v; done
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echo "create_project -force -part $(FPGA_PART) $(PROJECT)" > $@
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echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@
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echo "set_property top $(FPGA_TOP) [current_fileset]" >> $@
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echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@
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for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done
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for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done
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for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done
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update_config.tcl: $(CONFIG_TCL_FILES_REL) $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL)
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echo "open_project -quiet $(PROJECT).xpr" > $@
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for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done
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$(PROJECT).xpr: create_project.tcl update_config.tcl
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vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
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# synthesis run
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$(PROJECT).runs/synth_1/$(PROJECT).dcp: create_project.tcl update_config.tcl $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) | $(PROJECT).xpr
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echo "open_project $(PROJECT).xpr" > run_synth.tcl
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echo "reset_run synth_1" >> run_synth.tcl
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echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
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echo "wait_on_run synth_1" >> run_synth.tcl
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vivado -nojournal -nolog -mode batch -source run_synth.tcl
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# implementation run
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$(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp: $(PROJECT).runs/synth_1/$(PROJECT).dcp
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echo "open_project $(PROJECT).xpr" > run_impl.tcl
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echo "reset_run impl_1" >> run_impl.tcl
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echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
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echo "wait_on_run impl_1" >> run_impl.tcl
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echo "open_run impl_1" >> run_impl.tcl
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echo "report_utilization -file $(PROJECT)_utilization.rpt" >> run_impl.tcl
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echo "report_utilization -hierarchical -file $(PROJECT)_utilization_hierarchical.rpt" >> run_impl.tcl
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vivado -nojournal -nolog -mode batch -source run_impl.tcl
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# bit file
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$(PROJECT).bit $(PROJECT).ltx: $(PROJECT).runs/impl_1/$(PROJECT)_routed.dcp
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echo "open_project $(PROJECT).xpr" > generate_bit.tcl
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echo "open_run impl_1" >> generate_bit.tcl
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echo "write_bitstream -force $(PROJECT).runs/impl_1/$(PROJECT).bit" >> generate_bit.tcl
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echo "write_debug_probes -force $(PROJECT).runs/impl_1/$(PROJECT).ltx" >> generate_bit.tcl
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vivado -nojournal -nolog -mode batch -source generate_bit.tcl
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ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).bit .
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if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then ln -f -s $(PROJECT).runs/impl_1/$(PROJECT).ltx .; fi
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mkdir -p rev
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COUNT=100; \
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while [ -e rev/$(PROJECT)_rev$$COUNT.bit ]; \
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do COUNT=$$((COUNT+1)); done; \
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cp -pv $(PROJECT).runs/impl_1/$(PROJECT).bit rev/$(PROJECT)_rev$$COUNT.bit; \
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if [ -e $(PROJECT).runs/impl_1/$(PROJECT).ltx ]; then cp -pv $(PROJECT).runs/impl_1/$(PROJECT).ltx rev/$(PROJECT)_rev$$COUNT.ltx; fi
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963
example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga.xdc
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example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga.xdc
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# XDC constraints for the Xilinx VCU118 board
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# part: xcvu9p-flga2104-2L-e
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# General configuration
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set_property CFGBVS GND [current_design]
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set_property CONFIG_VOLTAGE 1.8 [current_design]
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set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
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set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN {DIV-1} [current_design]
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set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
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set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 8 [current_design]
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set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES [current_design]
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# System clocks
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# 300 MHz
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#set_property -dict {LOC G31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_p]
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#set_property -dict {LOC F31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_n]
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#create_clock -period 3.333 -name clk_300mhz [get_ports clk_300mhz_p]
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# 250 MHz
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#set_property -dict {LOC E12 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_1_p]
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#set_property -dict {LOC D12 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_1_n]
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#create_clock -period 4 -name clk_250mhz_1 [get_ports clk_250mhz_1_p]
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#set_property -dict {LOC AW26 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_2_p]
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#set_property -dict {LOC AW27 IOSTANDARD DIFF_SSTL12} [get_ports clk_250mhz_2_n]
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#create_clock -period 4 -name clk_250mhz_2 [get_ports clk_250mhz_2_p]
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# 125 MHz
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set_property -dict {LOC AY24 IOSTANDARD LVDS} [get_ports clk_125mhz_p]
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set_property -dict {LOC AY23 IOSTANDARD LVDS} [get_ports clk_125mhz_n]
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create_clock -period 8.000 -name clk_125mhz [get_ports clk_125mhz_p]
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# 90 MHz
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#set_property -dict {LOC AL20 IOSTANDARD LVCMOS18} [get_ports clk_90mhz]
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#create_clock -period 11.111 -name clk_90mhz [get_ports clk_90mhz]
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# LEDs
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set_property -dict {LOC AT32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}]
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set_property -dict {LOC AV34 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[1]}]
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set_property -dict {LOC AY30 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[2]}]
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set_property -dict {LOC BB32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[3]}]
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set_property -dict {LOC BF32 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[4]}]
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set_property -dict {LOC AU37 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[5]}]
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set_property -dict {LOC AV36 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[6]}]
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set_property -dict {LOC BA37 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[7]}]
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set_false_path -to [get_ports {led[*]}]
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set_output_delay 0 [get_ports {led[*]}]
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# Reset button
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set_property -dict {LOC L19 IOSTANDARD LVCMOS12} [get_ports reset]
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set_false_path -from [get_ports {reset}]
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set_input_delay 0 [get_ports {reset}]
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# Push buttons
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set_property -dict {LOC BB24 IOSTANDARD LVCMOS18} [get_ports btnu]
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set_property -dict {LOC BF22 IOSTANDARD LVCMOS18} [get_ports btnl]
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set_property -dict {LOC BE22 IOSTANDARD LVCMOS18} [get_ports btnd]
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set_property -dict {LOC BE23 IOSTANDARD LVCMOS18} [get_ports btnr]
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set_property -dict {LOC BD23 IOSTANDARD LVCMOS18} [get_ports btnc]
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set_false_path -from [get_ports {btnu btnl btnd btnr btnc}]
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set_input_delay 0 [get_ports {btnu btnl btnd btnr btnc}]
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# DIP switches
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set_property -dict {LOC B17 IOSTANDARD LVCMOS12} [get_ports {sw[0]}]
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set_property -dict {LOC G16 IOSTANDARD LVCMOS12} [get_ports {sw[1]}]
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set_property -dict {LOC J16 IOSTANDARD LVCMOS12} [get_ports {sw[2]}]
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set_property -dict {LOC D21 IOSTANDARD LVCMOS12} [get_ports {sw[3]}]
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set_false_path -from [get_ports {sw[*]}]
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set_input_delay 0 [get_ports {sw[*]}]
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# PMOD0
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#set_property -dict {LOC AY14 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[0]}]
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#set_property -dict {LOC AY15 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[1]}]
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#set_property -dict {LOC AW15 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[2]}]
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#set_property -dict {LOC AV15 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[3]}]
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#set_property -dict {LOC AV16 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[4]}]
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#set_property -dict {LOC AU16 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[5]}]
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#set_property -dict {LOC AT15 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[6]}]
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#set_property -dict {LOC AT16 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports {pmod0[7]}]
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#set_false_path -to [get_ports {pmod0[*]}]
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#set_output_delay 0 [get_ports {pmod0[*]}]
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# PMOD1
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#set_property -dict {LOC N28 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[0]}]
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#set_property -dict {LOC M30 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[1]}]
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#set_property -dict {LOC N30 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[2]}]
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#set_property -dict {LOC P30 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[3]}]
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#set_property -dict {LOC P29 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[4]}]
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#set_property -dict {LOC L31 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[5]}]
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#set_property -dict {LOC M31 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[6]}]
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#set_property -dict {LOC R29 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {pmod1[7]}]
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#set_false_path -to [get_ports {pmod1[*]}]
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#set_output_delay 0 [get_ports {pmod1[*]}]
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# UART
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set_property -dict {LOC BB21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_txd]
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set_property -dict {LOC AW25 IOSTANDARD LVCMOS18} [get_ports uart_rxd]
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set_property -dict {LOC BB22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports uart_rts]
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set_property -dict {LOC AY25 IOSTANDARD LVCMOS18} [get_ports uart_cts]
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set_false_path -to [get_ports {uart_txd uart_rts}]
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set_output_delay 0 [get_ports {uart_txd uart_rts}]
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set_false_path -from [get_ports {uart_rxd uart_cts}]
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set_input_delay 0 [get_ports {uart_rxd uart_cts}]
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# Gigabit Ethernet SGMII PHY
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set_property -dict {LOC AU24 IOSTANDARD LVDS} [get_ports phy_sgmii_rx_p]
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set_property -dict {LOC AV24 IOSTANDARD LVDS} [get_ports phy_sgmii_rx_n]
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set_property -dict {LOC AU21 IOSTANDARD LVDS} [get_ports phy_sgmii_tx_p]
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set_property -dict {LOC AV21 IOSTANDARD LVDS} [get_ports phy_sgmii_tx_n]
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set_property -dict {LOC AT22 IOSTANDARD LVDS} [get_ports phy_sgmii_clk_p]
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set_property -dict {LOC AU22 IOSTANDARD LVDS} [get_ports phy_sgmii_clk_n]
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set_property -dict {LOC BA21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports phy_reset_n]
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set_property -dict {LOC AR24 IOSTANDARD LVCMOS18} [get_ports phy_int_n]
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set_property -dict {LOC AR23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports phy_mdio]
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set_property -dict {LOC AV23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports phy_mdc]
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# 625 MHz ref clock from SGMII PHY
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#create_clock -period 1.600 -name phy_sgmii_clk [get_ports phy_sgmii_clk_p]
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set_false_path -to [get_ports {phy_reset_n phy_mdio phy_mdc}]
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set_output_delay 0 [get_ports {phy_reset_n phy_mdio phy_mdc}]
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set_false_path -from [get_ports {phy_int_n phy_mdio}]
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set_input_delay 0 [get_ports {phy_int_n phy_mdio}]
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# QSFP28 Interfaces
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set_property -dict {LOC Y2 } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
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set_property -dict {LOC Y1 } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
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set_property -dict {LOC V7 } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
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set_property -dict {LOC V6 } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y48 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC W4 } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC W3 } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC T7 } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC T6 } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y49 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC V2 } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC V1 } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC P7 } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC P6 } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y50 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC U4 } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC U3 } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M7 } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC M6 } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y51 / GTYE4_COMMON_X1Y12
|
||||
set_property -dict {LOC W9 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_231 from U38.4
|
||||
set_property -dict {LOC W8 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_231 from U38.5
|
||||
#set_property -dict {LOC U9 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_231 from U57.28
|
||||
#set_property -dict {LOC U8 } [get_ports qsfp1_mgt_refclk_1_n] ;# MGTREFCLK1N_231 from U57.29
|
||||
#set_property -dict {LOC AM23 IOSTANDARD LVDS} [get_ports qsfp1_recclk_p] ;# to U57.16
|
||||
#set_property -dict {LOC AM22 IOSTANDARD LVDS} [get_ports qsfp1_recclk_n] ;# to U57.17
|
||||
set_property -dict {LOC AM21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp1_modsell]
|
||||
set_property -dict {LOC BA22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp1_resetl]
|
||||
set_property -dict {LOC AL21 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp1_modprsl]
|
||||
set_property -dict {LOC AP21 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp1_intl]
|
||||
set_property -dict {LOC AN21 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp1_lpmode]
|
||||
|
||||
# 156.25 MHz MGT reference clock
|
||||
create_clock -period 6.400 -name qsfp1_mgt_refclk_0 [get_ports qsfp1_mgt_refclk_0_p]
|
||||
|
||||
set_false_path -to [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode}]
|
||||
set_output_delay 0 [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode}]
|
||||
set_false_path -from [get_ports {qsfp1_modprsl qsfp1_intl}]
|
||||
set_input_delay 0 [get_ports {qsfp1_modprsl qsfp1_intl}]
|
||||
|
||||
set_property -dict {LOC T2 } [get_ports qsfp2_rx1_p] ;# MGTYRXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC T1 } [get_ports qsfp2_rx1_n] ;# MGTYRXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC L5 } [get_ports qsfp2_tx1_p] ;# MGTYTXP0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC L4 } [get_ports qsfp2_tx1_n] ;# MGTYTXN0_232 GTYE4_CHANNEL_X1Y52 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC R4 } [get_ports qsfp2_rx2_p] ;# MGTYRXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC R3 } [get_ports qsfp2_rx2_n] ;# MGTYRXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC K7 } [get_ports qsfp2_tx2_p] ;# MGTYTXP1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC K6 } [get_ports qsfp2_tx2_n] ;# MGTYTXN1_232 GTYE4_CHANNEL_X1Y53 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC P2 } [get_ports qsfp2_rx3_p] ;# MGTYRXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC P1 } [get_ports qsfp2_rx3_n] ;# MGTYRXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC J5 } [get_ports qsfp2_tx3_p] ;# MGTYTXP2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC J4 } [get_ports qsfp2_tx3_n] ;# MGTYTXN2_232 GTYE4_CHANNEL_X1Y54 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC M2 } [get_ports qsfp2_rx4_p] ;# MGTYRXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC M1 } [get_ports qsfp2_rx4_n] ;# MGTYRXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC H7 } [get_ports qsfp2_tx4_p] ;# MGTYTXP3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13
|
||||
set_property -dict {LOC H6 } [get_ports qsfp2_tx4_n] ;# MGTYTXN3_232 GTYE4_CHANNEL_X1Y55 / GTYE4_COMMON_X1Y13
|
||||
#set_property -dict {LOC R9 } [get_ports qsfp2_mgt_refclk_0_p] ;# MGTREFCLK0P_232 from U104.13
|
||||
#set_property -dict {LOC R8 } [get_ports qsfp2_mgt_refclk_0_n] ;# MGTREFCLK0N_232 from U104.14
|
||||
#set_property -dict {LOC N9 } [get_ports qsfp2_mgt_refclk_1_p] ;# MGTREFCLK1P_232 from U57.35
|
||||
#set_property -dict {LOC N8 } [get_ports qsfp2_mgt_refclk_1_n] ;# MGTREFCLK1N_232 from U57.34
|
||||
#set_property -dict {LOC AP23 IOSTANDARD LVDS} [get_ports qsfp2_recclk_p] ;# to U57.12
|
||||
#set_property -dict {LOC AP22 IOSTANDARD LVDS} [get_ports qsfp2_recclk_n] ;# to U57.13
|
||||
set_property -dict {LOC AN23 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp2_modsell]
|
||||
set_property -dict {LOC AY22 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp2_resetl]
|
||||
set_property -dict {LOC AN24 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp2_modprsl]
|
||||
set_property -dict {LOC AT21 IOSTANDARD LVCMOS18 PULLUP true} [get_ports qsfp2_intl]
|
||||
set_property -dict {LOC AT24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports qsfp2_lpmode]
|
||||
|
||||
# 156.25 MHz MGT reference clock
|
||||
#create_clock -period 6.400 -name qsfp2_mgt_refclk_0 [get_ports qsfp2_mgt_refclk_0_p]
|
||||
|
||||
set_false_path -to [get_ports {qsfp2_modsell qsfp2_resetl qsfp2_lpmode}]
|
||||
set_output_delay 0 [get_ports {qsfp2_modsell qsfp2_resetl qsfp2_lpmode}]
|
||||
set_false_path -from [get_ports {qsfp2_modprsl qsfp2_intl}]
|
||||
set_input_delay 0 [get_ports {qsfp2_modprsl qsfp2_intl}]
|
||||
|
||||
# I2C interface
|
||||
set_property -dict {LOC AM24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_scl]
|
||||
set_property -dict {LOC AL24 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 8} [get_ports i2c_sda]
|
||||
|
||||
set_false_path -to [get_ports {i2c_sda i2c_scl}]
|
||||
set_output_delay 0 [get_ports {i2c_sda i2c_scl}]
|
||||
set_false_path -from [get_ports {i2c_sda i2c_scl}]
|
||||
set_input_delay 0 [get_ports {i2c_sda i2c_scl}]
|
||||
|
||||
# PCIe Interface
|
||||
#set_property -dict {LOC AA4 } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AA3 } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC Y7 } [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC Y6 } [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y35 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AB2 } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AB1 } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AB7 } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AB6 } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y34 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AC4 } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AC3 } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AD7 } [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AD6 } [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y33 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AD2 } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AD1 } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AF7 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AF6 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y32 / GTYE4_COMMON_X1Y8
|
||||
#set_property -dict {LOC AE4 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AE3 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AH7 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AH6 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AK7 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AK6 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AG4 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AG3 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AM7 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AM6 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AH2 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AH1 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AN5 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AN4 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7
|
||||
#set_property -dict {LOC AJ4 } [get_ports {pcie_rx_p[8]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AJ3 } [get_ports {pcie_rx_n[8]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AP7 } [get_ports {pcie_tx_p[8]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AP6 } [get_ports {pcie_tx_n[8]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AK2 } [get_ports {pcie_rx_p[9]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AK1 } [get_ports {pcie_rx_n[9]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AR5 } [get_ports {pcie_tx_p[9]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AR4 } [get_ports {pcie_tx_n[9]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AM2 } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AM1 } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AT7 } [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AT6 } [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AP2 } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AP1 } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AU5 } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AU4 } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6
|
||||
#set_property -dict {LOC AT2 } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC AT1 } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC AW5 } [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC AW4 } [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC AV2 } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC AV1 } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC BA5 } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC BA4 } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC AY2 } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC AY1 } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC BC5 } [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC BC4 } [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC BB2 } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC BB1 } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC BE5 } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC BE4 } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5
|
||||
#set_property -dict {LOC AC9 } [get_ports pcie_refclk_1_p] ;# MGTREFCLK0P_227
|
||||
#set_property -dict {LOC AC8 } [get_ports pcie_refclk_1_n] ;# MGTREFCLK0N_227
|
||||
#set_property -dict {LOC AL9 } [get_ports pcie_refclk_2_p] ;# MGTREFCLK0P_225
|
||||
#set_property -dict {LOC AL8 } [get_ports pcie_refclk_2_n] ;# MGTREFCLK0N_225
|
||||
#set_property -dict {LOC AM17 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_reset_n]
|
||||
|
||||
# 100 MHz MGT reference clock
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_1_p]
|
||||
#create_clock -period 10 -name pcie_mgt_refclk_2 [get_ports pcie_refclk_2_p]
|
||||
|
||||
#set_false_path -from [get_ports {pcie_reset_n}]
|
||||
#set_input_delay 0 [get_ports {pcie_reset_n}]
|
||||
|
||||
# FMC+ J22
|
||||
set_property -dict {LOC AL35 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp1_lpmode] ;# J22.G9 LA00_P_CC
|
||||
set_property -dict {LOC AL36 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp6_resetl] ;# J22.G10 LA00_N_CC
|
||||
set_property -dict {LOC AL30 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp1_modprsl] ;# J22.D8 LA01_P_CC
|
||||
set_property -dict {LOC AL31 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp1_intl] ;# J22.D9 LA01_N_CC
|
||||
set_property -dict {LOC AJ32 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp6_modsell] ;# J22.H7 LA02_P
|
||||
set_property -dict {LOC AK32 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp6_modprsl] ;# J22.H8 LA02_N
|
||||
set_property -dict {LOC AT39 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp6_intl] ;# J22.G12 LA03_P
|
||||
set_property -dict {LOC AT40 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp5_modsell] ;# J22.G13 LA03_N
|
||||
set_property -dict {LOC AR37 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp6_lpmode] ;# J22.H10 LA04_P
|
||||
set_property -dict {LOC AT37 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp5_resetl] ;# J22.H11 LA04_N
|
||||
set_property -dict {LOC AP38 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp1_modsell] ;# J22.D11 LA05_P
|
||||
set_property -dict {LOC AR38 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp2_intl] ;# J22.D12 LA05_N
|
||||
set_property -dict {LOC AT35 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp1_resetl] ;# J22.C10 LA06_P
|
||||
set_property -dict {LOC AT36 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp2_lpmode] ;# J22.C11 LA06_N
|
||||
set_property -dict {LOC AP36 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp4_modprsl] ;# J22.H13 LA07_P
|
||||
set_property -dict {LOC AP37 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp4_modsell] ;# J22.H14 LA07_N
|
||||
set_property -dict {LOC AK29 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp4_lpmode] ;# J22.G12 LA08_P
|
||||
set_property -dict {LOC AK30 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp4_intl] ;# J22.G13 LA08_N
|
||||
set_property -dict {LOC AJ33 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp2_modprsl] ;# J22.D14 LA09_P
|
||||
set_property -dict {LOC AK33 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp2_modsell] ;# J22.D15 LA09_N
|
||||
set_property -dict {LOC AP35 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp2_resetl] ;# J22.C14 LA10_P
|
||||
set_property -dict {LOC AR35 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp3_lpmode] ;# J22.C15 LA10_N
|
||||
set_property -dict {LOC AJ30 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp5_intl] ;# J22.H16 LA11_P
|
||||
set_property -dict {LOC AJ31 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp5_modprsl] ;# J22.H17 LA11_N
|
||||
set_property -dict {LOC AH33 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp4_resetl] ;# J22.G15 LA12_P
|
||||
set_property -dict {LOC AH34 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp5_lpmode] ;# J22.G16 LA12_N
|
||||
set_property -dict {LOC AJ35 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp3_intl] ;# J22.D17 LA13_P
|
||||
set_property -dict {LOC AJ36 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp3_modprsl] ;# J22.D18 LA13_N
|
||||
set_property -dict {LOC AG31 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp3_modsell] ;# J22.C18 LA14_P
|
||||
set_property -dict {LOC AH31 IOSTANDARD LVCMOS18} [get_ports fmcp_qsfp3_resetl] ;# J22.C19 LA14_N
|
||||
set_property -dict {LOC AG32 IOSTANDARD LVCMOS18} [get_ports fmcp_clk_finc] ;# J22.H19 LA15_P
|
||||
set_property -dict {LOC AG33 IOSTANDARD LVCMOS18} [get_ports fmcp_clk_fdec] ;# J22.H20 LA15_N
|
||||
set_property -dict {LOC AG34 IOSTANDARD LVCMOS18} [get_ports fmcp_clk_rst_n] ;# J22.G18 LA16_P
|
||||
set_property -dict {LOC AH35 IOSTANDARD LVCMOS18} [get_ports fmcp_clk_lol_n] ;# J22.G19 LA16_N
|
||||
set_property -dict {LOC R34 IOSTANDARD LVCMOS18} [get_ports fmcp_clk_sync_n] ;# J22.D20 LA17_P_CC
|
||||
set_property -dict {LOC P34 IOSTANDARD LVCMOS18} [get_ports fmcp_clk_intr_n] ;# J22.D21 LA17_N_CC
|
||||
#set_property -dict {LOC R31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[18]}] ;# J22.C22 LA18_P_CC
|
||||
#set_property -dict {LOC P31 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[18]}] ;# J22.C23 LA18_N_CC
|
||||
#set_property -dict {LOC N33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[19]}] ;# J22.H22 LA19_P
|
||||
#set_property -dict {LOC M33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[19]}] ;# J22.H23 LA19_N
|
||||
#set_property -dict {LOC N32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[20]}] ;# J22.G21 LA20_P
|
||||
#set_property -dict {LOC M32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[20]}] ;# J22.G22 LA20_N
|
||||
#set_property -dict {LOC M35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[21]}] ;# J22.H25 LA21_P
|
||||
#set_property -dict {LOC L35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[21]}] ;# J22.H26 LA21_N
|
||||
#set_property -dict {LOC N34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[22]}] ;# J22.G24 LA22_P
|
||||
#set_property -dict {LOC N35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[22]}] ;# J22.G25 LA22_N
|
||||
#set_property -dict {LOC Y32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[23]}] ;# J22.D23 LA23_P
|
||||
#set_property -dict {LOC W32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[23]}] ;# J22.D24 LA23_N
|
||||
#set_property -dict {LOC T34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[24]}] ;# J22.H28 LA24_P
|
||||
#set_property -dict {LOC T35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[24]}] ;# J22.H29 LA24_N
|
||||
#set_property -dict {LOC Y34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[25]}] ;# J22.G27 LA25_P
|
||||
#set_property -dict {LOC W34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[25]}] ;# J22.G28 LA25_N
|
||||
#set_property -dict {LOC V32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[26]}] ;# J22.D26 LA26_P
|
||||
#set_property -dict {LOC U33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[26]}] ;# J22.D27 LA26_N
|
||||
#set_property -dict {LOC V33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[27]}] ;# J22.C26 LA27_P
|
||||
#set_property -dict {LOC V34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[27]}] ;# J22.C27 LA27_N
|
||||
#set_property -dict {LOC M36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[28]}] ;# J22.H31 LA28_P
|
||||
#set_property -dict {LOC L36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[28]}] ;# J22.H32 LA28_N
|
||||
#set_property -dict {LOC U35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[29]}] ;# J22.G30 LA29_P
|
||||
#set_property -dict {LOC T36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[29]}] ;# J22.G31 LA29_N
|
||||
#set_property -dict {LOC N38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[30]}] ;# J22.H34 LA30_P
|
||||
#set_property -dict {LOC M38 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[30]}] ;# J22.H35 LA30_N
|
||||
#set_property -dict {LOC P37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[31]}] ;# J22.G33 LA31_P
|
||||
#set_property -dict {LOC N37 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[31]}] ;# J22.G34 LA31_N
|
||||
#set_property -dict {LOC L33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[32]}] ;# J22.H37 LA32_P
|
||||
#set_property -dict {LOC K33 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[32]}] ;# J22.H38 LA32_N
|
||||
#set_property -dict {LOC L34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_p[33]}] ;# J22.G36 LA33_P
|
||||
#set_property -dict {LOC K34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_la_n[33]}] ;# J22.G37 LA33_N
|
||||
|
||||
#set_property -dict {LOC N14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[0]}] ;# J22.F4 HA00_P_CC
|
||||
#set_property -dict {LOC N13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[0]}] ;# J22.F5 HA00_N_CC
|
||||
#set_property -dict {LOC V15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[1]}] ;# J22.E2 HA01_P_CC
|
||||
#set_property -dict {LOC U15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[1]}] ;# J22.E3 HA01_N_CC
|
||||
#set_property -dict {LOC AA12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[2]}] ;# J22.K7 HA02_P
|
||||
#set_property -dict {LOC Y12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[2]}] ;# J22.K8 HA02_N
|
||||
#set_property -dict {LOC W12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[3]}] ;# J22.J6 HA03_P
|
||||
#set_property -dict {LOC V12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[3]}] ;# J22.J7 HA03_N
|
||||
#set_property -dict {LOC AA13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[4]}] ;# J22.F7 HA04_P
|
||||
#set_property -dict {LOC Y13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[4]}] ;# J22.F8 HA04_N
|
||||
#set_property -dict {LOC R14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[5]}] ;# J22.E6 HA05_P
|
||||
#set_property -dict {LOC P14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[5]}] ;# J22.E7 HA05_N
|
||||
#set_property -dict {LOC U13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[6]}] ;# J22.K10 HA06_P
|
||||
#set_property -dict {LOC T13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[6]}] ;# J22.K11 HA06_N
|
||||
#set_property -dict {LOC AA14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[7]}] ;# J22.J9 HA07_P
|
||||
#set_property -dict {LOC Y14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[7]}] ;# J22.J10 HA07_N
|
||||
#set_property -dict {LOC U11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[8]}] ;# J22.F10 HA08_P
|
||||
#set_property -dict {LOC T11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[8]}] ;# J22.F11 HA08_N
|
||||
#set_property -dict {LOC W14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[9]}] ;# J22.E9 HA09_P
|
||||
#set_property -dict {LOC V14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[9]}] ;# J22.E10 HA09_N
|
||||
#set_property -dict {LOC V16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[10]}] ;# J22.K13 HA10_P
|
||||
#set_property -dict {LOC U16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[10]}] ;# J22.K14 HA10_N
|
||||
#set_property -dict {LOC R12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[11]}] ;# J22.J12 HA11_P
|
||||
#set_property -dict {LOC P12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[11]}] ;# J22.J13 HA11_N
|
||||
#set_property -dict {LOC T16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[12]}] ;# J22.F13 HA12_P
|
||||
#set_property -dict {LOC T15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[12]}] ;# J22.F14 HA12_N
|
||||
#set_property -dict {LOC V13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[13]}] ;# J22.E12 HA13_P
|
||||
#set_property -dict {LOC U12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[13]}] ;# J22.E13 HA13_N
|
||||
#set_property -dict {LOC M11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[14]}] ;# J22.J15 HA14_P
|
||||
#set_property -dict {LOC L11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[14]}] ;# J22.J16 HA14_N
|
||||
#set_property -dict {LOC M13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[15]}] ;# J22.F14 HA15_P
|
||||
#set_property -dict {LOC M12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[15]}] ;# J22.F16 HA15_N
|
||||
#set_property -dict {LOC T14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[16]}] ;# J22.E15 HA16_P
|
||||
#set_property -dict {LOC R13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[16]}] ;# J22.E16 HA16_N
|
||||
#set_property -dict {LOC R11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[17]}] ;# J22.K16 HA17_P_CC
|
||||
#set_property -dict {LOC P11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[17]}] ;# J22.K17 HA17_N_CC
|
||||
#set_property -dict {LOC P15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[18]}] ;# J22.J18 HA18_P_CC
|
||||
#set_property -dict {LOC N15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[18]}] ;# J22.J19 HA18_N_CC
|
||||
#set_property -dict {LOC L14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[19]}] ;# J22.F19 HA19_P
|
||||
#set_property -dict {LOC L13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[19]}] ;# J22.F20 HA19_N
|
||||
#set_property -dict {LOC M15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[20]}] ;# J22.E18 HA20_P
|
||||
#set_property -dict {LOC L15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[20]}] ;# J22.E19 HA20_N
|
||||
#set_property -dict {LOC K14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[21]}] ;# J22.K19 HA21_P
|
||||
#set_property -dict {LOC K13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[21]}] ;# J22.K20 HA21_N
|
||||
#set_property -dict {LOC K12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[22]}] ;# J22.J21 HA22_P
|
||||
#set_property -dict {LOC J12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[22]}] ;# J22.J22 HA22_N
|
||||
#set_property -dict {LOC K11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_p[23]}] ;# J22.K22 HA23_P
|
||||
#set_property -dict {LOC J11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_ha_n[23]}] ;# J22.K23 HA23_N
|
||||
|
||||
#set_property -dict {LOC AL32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_clk0_m2c_p}] ;# J22.H4 CLK0_M2C_P
|
||||
#set_property -dict {LOC AM32 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_clk0_m2c_n}] ;# J22.H5 CLK0_M2C_N
|
||||
#set_property -dict {LOC P35 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_clk1_m2c_p}] ;# J22.G2 CLK1_M2C_P
|
||||
#set_property -dict {LOC P36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_clk1_m2c_n}] ;# J22.G3 CLK1_M2C_N
|
||||
|
||||
#set_property -dict {LOC AN33 IOSTANDARD LVDS } [get_ports {fmcp_hspc_refclk_c2m_p}] ;# J22.L20 REFCLK_C2M_P
|
||||
#set_property -dict {LOC AP33 IOSTANDARD LVDS } [get_ports {fmcp_hspc_refclk_c2m_n}] ;# J22.L21 REFCLK_C2M_N
|
||||
#set_property -dict {LOC AK34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_refclk_m2c_p}] ;# J22.L24 REFCLK_M2C_P
|
||||
#set_property -dict {LOC AL34 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_refclk_m2c_n}] ;# J22.L25 REFCLK_M2C_N
|
||||
set_property -dict {LOC AN34 IOSTANDARD LVDS } [get_ports {fmcp_hspc_sync_c2m_p}] ;# J22.L16 SYNC_C2M_P
|
||||
set_property -dict {LOC AN35 IOSTANDARD LVDS } [get_ports {fmcp_hspc_sync_c2m_n}] ;# J22.L17 SYNC_C2M_N
|
||||
#set_property -dict {LOC AM36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_sync_m2c_p}] ;# J22.L28 SYNC_M2C_P
|
||||
#set_property -dict {LOC AN36 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmcp_hspc_sync_m2c_n}] ;# J22.L29 SYNC_M2C_N
|
||||
|
||||
#set_property -dict {LOC AL36 IOSTANDARD LVCMOS18} [get_ports {fmcp_hspc_pg_m2c}] ;# J22.F1 PG_M2C
|
||||
#set_property -dict {LOC AM33 IOSTANDARD LVCMOS18} [get_ports {fmcp_hspc_h_prsnt_m2c_l}] ;# J22.H2 PRSNT_M2C_L
|
||||
#set_property -dict {LOC AM29 IOSTANDARD LVCMOS18} [get_ports {fmcp_hspc_z_prsnt_m2c_l}] ;# J22.Z1 HSPC_PRSNT_M2C_L
|
||||
|
||||
set_property -dict {LOC AT42} [get_ports {fmcp_qsfp1_tx_p[0]}] ;# MGTYTXP0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 from J22.C2 DP0_C2M_P
|
||||
set_property -dict {LOC AT43} [get_ports {fmcp_qsfp1_tx_n[0]}] ;# MGTYTXN0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 from J22.C3 DP0_C2M_N
|
||||
set_property -dict {LOC AR45} [get_ports {fmcp_qsfp1_rx_p[0]}] ;# MGTYRXP0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 from J22.C6 DP0_M2C_P
|
||||
set_property -dict {LOC AR46} [get_ports {fmcp_qsfp1_rx_n[0]}] ;# MGTYRXN0_121 GTYE4_CHANNEL_X0Y8 / GTYE4_COMMON_X0Y2 from J22.C7 DP0_M2C_N
|
||||
set_property -dict {LOC AP42} [get_ports {fmcp_qsfp1_tx_p[2]}] ;# MGTYTXP1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 from J22.A22 DP1_C2M_P
|
||||
set_property -dict {LOC AP43} [get_ports {fmcp_qsfp1_tx_n[2]}] ;# MGTYTXN1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 from J22.A23 DP1_C2M_N
|
||||
set_property -dict {LOC AN45} [get_ports {fmcp_qsfp1_rx_p[2]}] ;# MGTYRXP1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 from J22.A2 DP1_M2C_P
|
||||
set_property -dict {LOC AN46} [get_ports {fmcp_qsfp1_rx_n[2]}] ;# MGTYRXN1_121 GTYE4_CHANNEL_X0Y9 / GTYE4_COMMON_X0Y2 from J22.A3 DP1_M2C_N
|
||||
set_property -dict {LOC AM42} [get_ports {fmcp_qsfp1_tx_p[1]}] ;# MGTYTXP2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 from J22.A26 DP2_C2M_P
|
||||
set_property -dict {LOC AM43} [get_ports {fmcp_qsfp1_tx_n[1]}] ;# MGTYTXN2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 from J22.A27 DP2_C2M_N
|
||||
set_property -dict {LOC AL45} [get_ports {fmcp_qsfp1_rx_p[1]}] ;# MGTYRXP2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 from J22.A6 DP2_M2C_P
|
||||
set_property -dict {LOC AL46} [get_ports {fmcp_qsfp1_rx_n[1]}] ;# MGTYRXN2_121 GTYE4_CHANNEL_X0Y10 / GTYE4_COMMON_X0Y2 from J22.A7 DP2_M2C_N
|
||||
set_property -dict {LOC AL40} [get_ports {fmcp_qsfp1_tx_p[3]}] ;# MGTYTXP3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 from J22.A30 DP3_C2M_P
|
||||
set_property -dict {LOC AL41} [get_ports {fmcp_qsfp1_tx_n[3]}] ;# MGTYTXN3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 from J22.A31 DP3_C2M_N
|
||||
set_property -dict {LOC AJ45} [get_ports {fmcp_qsfp1_rx_p[3]}] ;# MGTYRXP3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 from J22.A10 DP3_M2C_P
|
||||
set_property -dict {LOC AJ46} [get_ports {fmcp_qsfp1_rx_n[3]}] ;# MGTYRXN3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2 from J22.A11 DP3_M2C_N
|
||||
set_property -dict {LOC AK38} [get_ports fmcp_qsfp1_mgt_refclk_p] ;# MGTREFCLK0P_121 from U40.1 Q0 from J22.D4 GBTCLK0_M2C_P
|
||||
set_property -dict {LOC AK39} [get_ports fmcp_qsfp1_mgt_refclk_n] ;# MGTREFCLK0N_121 from U40.2 NQ0 from J22.D5 GBTCLK0_M2C_N
|
||||
#set_property -dict {LOC AH38} [get_ports fmcp_hspc_mgt_refclk_0_1_p] ;# MGTREFCLK1P_121 from U39.5 Q0_P from J22.B20 GBTCLK1_M2C_P
|
||||
#set_property -dict {LOC AH39} [get_ports fmcp_hspc_mgt_refclk_0_1_n] ;# MGTREFCLK1N_121 from U39.6 Q0_N from J22.B21 GBTCLK1_M2C_N
|
||||
|
||||
# reference clock
|
||||
create_clock -period 6.400 -name fmcp_qsfp1_mgt_refclk [get_ports fmcp_qsfp1_mgt_refclk_p]
|
||||
#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_0_1 [get_ports fmcp_hspc_mgt_refclk_0_1_p]
|
||||
|
||||
set_property -dict {LOC T42 } [get_ports {fmcp_qsfp6_tx_p[1]}] ;# MGTYTXP0_126 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 from J22.A34 DP4_C2M_P
|
||||
set_property -dict {LOC T43 } [get_ports {fmcp_qsfp6_tx_n[1]}] ;# MGTYTXN0_126 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 from J22.A35 DP4_C2M_N
|
||||
set_property -dict {LOC W45 } [get_ports {fmcp_qsfp6_rx_p[1]}] ;# MGTYRXP0_126 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 from J22.A14 DP4_M2C_P
|
||||
set_property -dict {LOC W46 } [get_ports {fmcp_qsfp6_rx_n[1]}] ;# MGTYRXN0_126 GTYE4_CHANNEL_X0Y28 / GTYE4_COMMON_X0Y7 from J22.A15 DP4_M2C_N
|
||||
set_property -dict {LOC P42 } [get_ports {fmcp_qsfp6_tx_p[0]}] ;# MGTYTXP1_126 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 from J22.A38 DP5_C2M_P
|
||||
set_property -dict {LOC P43 } [get_ports {fmcp_qsfp6_tx_n[0]}] ;# MGTYTXN1_126 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 from J22.A39 DP5_C2M_N
|
||||
set_property -dict {LOC U45 } [get_ports {fmcp_qsfp6_rx_p[0]}] ;# MGTYRXP1_126 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 from J22.A18 DP5_M2C_P
|
||||
set_property -dict {LOC U46 } [get_ports {fmcp_qsfp6_rx_n[0]}] ;# MGTYRXN1_126 GTYE4_CHANNEL_X0Y29 / GTYE4_COMMON_X0Y7 from J22.A19 DP5_M2C_N
|
||||
set_property -dict {LOC M42 } [get_ports {fmcp_qsfp6_tx_p[2]}] ;# MGTYTXP2_126 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 from J22.B36 DP6_C2M_P
|
||||
set_property -dict {LOC M43 } [get_ports {fmcp_qsfp6_tx_n[2]}] ;# MGTYTXN2_126 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 from J22.B37 DP6_C2M_N
|
||||
set_property -dict {LOC R45 } [get_ports {fmcp_qsfp6_rx_p[2]}] ;# MGTYRXP2_126 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 from J22.B16 DP6_M2C_P
|
||||
set_property -dict {LOC R46 } [get_ports {fmcp_qsfp6_rx_n[2]}] ;# MGTYRXN2_126 GTYE4_CHANNEL_X0Y30 / GTYE4_COMMON_X0Y7 from J22.B17 DP6_M2C_N
|
||||
set_property -dict {LOC K42 } [get_ports {fmcp_qsfp6_tx_p[3]}] ;# MGTYTXP3_126 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 from J22.B32 DP7_C2M_P
|
||||
set_property -dict {LOC K43 } [get_ports {fmcp_qsfp6_tx_n[3]}] ;# MGTYTXN3_126 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 from J22.B33 DP7_C2M_N
|
||||
set_property -dict {LOC N45 } [get_ports {fmcp_qsfp6_rx_p[3]}] ;# MGTYRXP3_126 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 from J22.B12 DP7_M2C_P
|
||||
set_property -dict {LOC N46 } [get_ports {fmcp_qsfp6_rx_n[3]}] ;# MGTYRXN3_126 GTYE4_CHANNEL_X0Y31 / GTYE4_COMMON_X0Y7 from J22.B13 DP7_M2C_N
|
||||
set_property -dict {LOC V38 } [get_ports fmcp_qsfp6_mgt_refclk_p] ;# MGTREFCLK0P_126 from U40.3 Q1 from J22.D4 GBTCLK0_M2C_P
|
||||
set_property -dict {LOC V39 } [get_ports fmcp_qsfp6_mgt_refclk_n] ;# MGTREFCLK0N_126 from U40.4 NQ1 from J22.D5 GBTCLK0_M2C_N
|
||||
#set_property -dict {LOC T38 } [get_ports fmcp_hspc_mgt_refclk_1_1_p] ;# MGTREFCLK1P_126 from U39.8 Q1_P from J22.B20 GBTCLK1_M2C_P
|
||||
#set_property -dict {LOC T39 } [get_ports fmcp_hspc_mgt_refclk_1_1_n] ;# MGTREFCLK1N_126 from U39.9 Q1_N from J22.B21 GBTCLK1_M2C_N
|
||||
|
||||
# reference clock
|
||||
create_clock -period 6.400 -name fmcp_qsfp6_mgt_refclk [get_ports fmcp_qsfp6_mgt_refclk_p]
|
||||
#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_1_1 [get_ports fmcp_hspc_mgt_refclk_1_1_p]
|
||||
|
||||
set_property -dict {LOC AK42} [get_ports {fmcp_qsfp4_tx_p[3]}] ;# MGTYTXP0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 from J22.B28 DP8_C2M_P
|
||||
set_property -dict {LOC AK43} [get_ports {fmcp_qsfp4_tx_n[3]}] ;# MGTYTXN0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 from J22.B29 DP8_C2M_N
|
||||
set_property -dict {LOC AG45} [get_ports {fmcp_qsfp4_rx_p[3]}] ;# MGTYRXP0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 from J22.B8 DP8_M2C_P
|
||||
set_property -dict {LOC AG46} [get_ports {fmcp_qsfp4_rx_n[3]}] ;# MGTYRXN0_122 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3 from J22.B9 DP8_M2C_N
|
||||
set_property -dict {LOC AJ40} [get_ports {fmcp_qsfp4_tx_p[2]}] ;# MGTYTXP1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 from J22.B24 DP9_C2M_P
|
||||
set_property -dict {LOC AJ41} [get_ports {fmcp_qsfp4_tx_n[2]}] ;# MGTYTXN1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 from J22.B25 DP9_C2M_N
|
||||
set_property -dict {LOC AF43} [get_ports {fmcp_qsfp4_rx_p[2]}] ;# MGTYRXP1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 from J22.B4 DP9_M2C_P
|
||||
set_property -dict {LOC AF44} [get_ports {fmcp_qsfp4_rx_n[2]}] ;# MGTYRXN1_122 GTYE4_CHANNEL_X0Y13 / GTYE4_COMMON_X0Y3 from J22.B5 DP9_M2C_N
|
||||
set_property -dict {LOC AG40} [get_ports {fmcp_qsfp4_tx_p[1]}] ;# MGTYTXP2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 from J22.Z24 DP10_C2M_P
|
||||
set_property -dict {LOC AG41} [get_ports {fmcp_qsfp4_tx_n[1]}] ;# MGTYTXN2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 from J22.Z25 DP10_C2M_N
|
||||
set_property -dict {LOC AE45} [get_ports {fmcp_qsfp4_rx_p[1]}] ;# MGTYRXP2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 from J22.Y10 DP10_M2C_P
|
||||
set_property -dict {LOC AE46} [get_ports {fmcp_qsfp4_rx_n[1]}] ;# MGTYRXN2_122 GTYE4_CHANNEL_X0Y14 / GTYE4_COMMON_X0Y3 from J22.Y11 DP10_M2C_N
|
||||
set_property -dict {LOC AE40} [get_ports {fmcp_qsfp4_tx_p[0]}] ;# MGTYTXP3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 from J22.Y26 DP11_C2M_P
|
||||
set_property -dict {LOC AE41} [get_ports {fmcp_qsfp4_tx_n[0]}] ;# MGTYTXN3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 from J22.Y27 DP11_C2M_N
|
||||
set_property -dict {LOC AD43} [get_ports {fmcp_qsfp4_rx_p[0]}] ;# MGTYRXP3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 from J22.Z12 DP11_M2C_P
|
||||
set_property -dict {LOC AD44} [get_ports {fmcp_qsfp4_rx_n[0]}] ;# MGTYRXN3_122 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3 from J22.Z13 DP11_M2C_N
|
||||
set_property -dict {LOC AF38} [get_ports fmcp_qsfp4_mgt_refclk_p] ;# MGTREFCLK0P_122 from J22.L12 GBTCLK2_M2C_P
|
||||
set_property -dict {LOC AF39} [get_ports fmcp_qsfp4_mgt_refclk_n] ;# MGTREFCLK0N_122 from J22.L13 GBTCLK2_M2C_N
|
||||
#set_property -dict {LOC AD38} [get_ports fmcp_hspc_mgt_refclk_2_1_p] ;# MGTREFCLK1P_122 from U39.11 Q2_P from J22.B20 GBTCLK1_M2C_P
|
||||
#set_property -dict {LOC AD39} [get_ports fmcp_hspc_mgt_refclk_2_1_n] ;# MGTREFCLK1N_122 from U39.12 Q2_N from J22.B21 GBTCLK1_M2C_N
|
||||
|
||||
# reference clock
|
||||
create_clock -period 6.400 -name fmcp_qsfp4_mgt_refclk [get_ports fmcp_qsfp4_mgt_refclk_p]
|
||||
#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_2_1 [get_ports fmcp_hspc_mgt_refclk_2_1_p]
|
||||
|
||||
set_property -dict {LOC AC40} [get_ports {fmcp_qsfp3_tx_p[2]}] ;# MGTYTXP0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 from J22.Z28 DP12_C2M_P
|
||||
set_property -dict {LOC AC41} [get_ports {fmcp_qsfp3_tx_n[2]}] ;# MGTYTXN0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 from J22.Z29 DP12_C2M_N
|
||||
set_property -dict {LOC AC45} [get_ports {fmcp_qsfp3_rx_p[2]}] ;# MGTYRXP0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 from J22.Y14 DP12_M2C_P
|
||||
set_property -dict {LOC AC46} [get_ports {fmcp_qsfp3_rx_n[2]}] ;# MGTYRXN0_125 GTYE4_CHANNEL_X0Y24 / GTYE4_COMMON_X0Y6 from J22.Y15 DP12_M2C_N
|
||||
set_property -dict {LOC AA40} [get_ports {fmcp_qsfp3_tx_p[3]}] ;# MGTYTXP1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 from J22.Y30 DP13_C2M_P
|
||||
set_property -dict {LOC AA41} [get_ports {fmcp_qsfp3_tx_n[3]}] ;# MGTYTXN1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 from J22.Y31 DP13_C2M_N
|
||||
set_property -dict {LOC AB43} [get_ports {fmcp_qsfp3_rx_p[3]}] ;# MGTYRXP1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 from J22.Z16 DP13_M2C_P
|
||||
set_property -dict {LOC AB44} [get_ports {fmcp_qsfp3_rx_n[3]}] ;# MGTYRXN1_125 GTYE4_CHANNEL_X0Y25 / GTYE4_COMMON_X0Y6 from J22.Z17 DP13_M2C_N
|
||||
set_property -dict {LOC W40 } [get_ports {fmcp_qsfp3_tx_p[1]}] ;# MGTYTXP2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 from J22.M18 DP14_C2M_P
|
||||
set_property -dict {LOC W41 } [get_ports {fmcp_qsfp3_tx_n[1]}] ;# MGTYTXN2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 from J22.M19 DP14_C2M_N
|
||||
set_property -dict {LOC AA45} [get_ports {fmcp_qsfp3_rx_p[1]}] ;# MGTYRXP2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 from J22.Y18 DP14_M2C_P
|
||||
set_property -dict {LOC AA46} [get_ports {fmcp_qsfp3_rx_n[1]}] ;# MGTYRXN2_125 GTYE4_CHANNEL_X0Y26 / GTYE4_COMMON_X0Y6 from J22.Y19 DP14_M2C_N
|
||||
set_property -dict {LOC U40 } [get_ports {fmcp_qsfp3_tx_p[0]}] ;# MGTYTXP3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 from J22.M22 DP15_C2M_P
|
||||
set_property -dict {LOC U41 } [get_ports {fmcp_qsfp3_tx_n[0]}] ;# MGTYTXN3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 from J22.M23 DP15_C2M_N
|
||||
set_property -dict {LOC Y43 } [get_ports {fmcp_qsfp3_rx_p[0]}] ;# MGTYRXP3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 from J22.Y22 DP15_M2C_P
|
||||
set_property -dict {LOC Y44 } [get_ports {fmcp_qsfp3_rx_n[0]}] ;# MGTYRXN3_125 GTYE4_CHANNEL_X0Y27 / GTYE4_COMMON_X0Y6 from J22.Y23 DP15_M2C_N
|
||||
set_property -dict {LOC AB38} [get_ports fmcp_qsfp3_mgt_refclk_p] ;# MGTREFCLK0P_125 from J22.L8 GBTCLK3_M2C_P
|
||||
set_property -dict {LOC AB39} [get_ports fmcp_qsfp3_mgt_refclk_n] ;# MGTREFCLK0N_125 from J22.L9 GBTCLK3_M2C_N
|
||||
#set_property -dict {LOC Y38 } [get_ports fmcp_hspc_mgt_refclk_3_1_p] ;# MGTREFCLK1P_125 from U39.13 Q3_P from J22.B20 GBTCLK1_M2C_P
|
||||
#set_property -dict {LOC Y39 } [get_ports fmcp_hspc_mgt_refclk_3_1_n] ;# MGTREFCLK1N_125 from U39.14 Q3_N from J22.B21 GBTCLK1_M2C_N
|
||||
|
||||
# reference clock
|
||||
create_clock -period 6.400 -name fmcp_qsfp3_mgt_refclk [get_ports fmcp_qsfp3_mgt_refclk_p]
|
||||
#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_3_1 [get_ports fmcp_hspc_mgt_refclk_3_1_p]
|
||||
|
||||
set_property -dict {LOC H42 } [get_ports {fmcp_qsfp5_tx_p[3]}] ;# MGTYTXP0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 from J22.M26 DP16_C2M_P
|
||||
set_property -dict {LOC H43 } [get_ports {fmcp_qsfp5_tx_n[3]}] ;# MGTYTXN0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 from J22.M27 DP16_C2M_N
|
||||
set_property -dict {LOC L45 } [get_ports {fmcp_qsfp5_rx_p[3]}] ;# MGTYRXP0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 from J22.Z32 DP16_M2C_P
|
||||
set_property -dict {LOC L46 } [get_ports {fmcp_qsfp5_rx_n[3]}] ;# MGTYRXN0_127 GTYE4_CHANNEL_X0Y32 / GTYE4_COMMON_X0Y8 from J22.Z33 DP16_M2C_N
|
||||
set_property -dict {LOC F42 } [get_ports {fmcp_qsfp5_tx_p[1]}] ;# MGTYTXP1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 from J22.M30 DP17_C2M_P
|
||||
set_property -dict {LOC F43 } [get_ports {fmcp_qsfp5_tx_n[1]}] ;# MGTYTXN1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 from J22.M31 DP17_C2M_N
|
||||
set_property -dict {LOC J45 } [get_ports {fmcp_qsfp5_rx_p[1]}] ;# MGTYRXP1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 from J22.Y34 DP17_M2C_P
|
||||
set_property -dict {LOC J46 } [get_ports {fmcp_qsfp5_rx_n[1]}] ;# MGTYRXN1_127 GTYE4_CHANNEL_X0Y33 / GTYE4_COMMON_X0Y8 from J22.Y35 DP17_M2C_N
|
||||
set_property -dict {LOC D42 } [get_ports {fmcp_qsfp5_tx_p[2]}] ;# MGTYTXP2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 from J22.M34 DP18_C2M_P
|
||||
set_property -dict {LOC D43 } [get_ports {fmcp_qsfp5_tx_n[2]}] ;# MGTYTXN2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 from J22.M35 DP18_C2M_N
|
||||
set_property -dict {LOC G45 } [get_ports {fmcp_qsfp5_rx_p[2]}] ;# MGTYRXP2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 from J22.Z36 DP18_M2C_P
|
||||
set_property -dict {LOC G46 } [get_ports {fmcp_qsfp5_rx_n[2]}] ;# MGTYRXN2_127 GTYE4_CHANNEL_X0Y34 / GTYE4_COMMON_X0Y8 from J22.Z37 DP18_M2C_N
|
||||
set_property -dict {LOC B42 } [get_ports {fmcp_qsfp5_tx_p[0]}] ;# MGTYTXP3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 from J22.M38 DP19_C2M_P
|
||||
set_property -dict {LOC B43 } [get_ports {fmcp_qsfp5_tx_n[0]}] ;# MGTYTXN3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 from J22.M39 DP19_C2M_N
|
||||
set_property -dict {LOC E45 } [get_ports {fmcp_qsfp5_rx_p[0]}] ;# MGTYRXP3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 from J22.Y38 DP19_M2C_P
|
||||
set_property -dict {LOC E46 } [get_ports {fmcp_qsfp5_rx_n[0]}] ;# MGTYRXN3_127 GTYE4_CHANNEL_X0Y35 / GTYE4_COMMON_X0Y8 from J22.Y39 DP19_M2C_N
|
||||
set_property -dict {LOC R40 } [get_ports fmcp_qsfp5_mgt_refclk_p] ;# MGTREFCLK0P_127 from J22.L4 GBTCLK4_M2C_P
|
||||
set_property -dict {LOC R41 } [get_ports fmcp_qsfp5_mgt_refclk_n] ;# MGTREFCLK0N_127 from J22.L5 GBTCLK4_M2C_N
|
||||
#set_property -dict {LOC N40 } [get_ports fmcp_hspc_mgt_refclk_4_1_p] ;# MGTREFCLK1P_127 from U39.16 Q4_P from J22.B20 GBTCLK1_M2C_P
|
||||
#set_property -dict {LOC N41 } [get_ports fmcp_hspc_mgt_refclk_4_1_n] ;# MGTREFCLK1N_127 from U39.17 Q4_N from J22.B21 GBTCLK1_M2C_N
|
||||
|
||||
# reference clock
|
||||
create_clock -period 6.400 -name fmcp_qsfp5_mgt_refclk [get_ports fmcp_qsfp5_mgt_refclk_p]
|
||||
#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_4_1 [get_ports fmcp_hspc_mgt_refclk_4_1_p]
|
||||
|
||||
set_property -dict {LOC BD42} [get_ports {fmcp_qsfp2_tx_p[3]}] ;# MGTYTXP0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 from J22.Z8 DP20_C2M_P
|
||||
set_property -dict {LOC BD43} [get_ports {fmcp_qsfp2_tx_n[3]}] ;# MGTYTXN0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 from J22.Z9 DP20_C2M_N
|
||||
set_property -dict {LOC BC45} [get_ports {fmcp_qsfp2_rx_p[3]}] ;# MGTYRXP0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 from J22.M14 DP20_M2C_P
|
||||
set_property -dict {LOC BC46} [get_ports {fmcp_qsfp2_rx_n[3]}] ;# MGTYRXN0_120 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1 from J22.M15 DP20_M2C_N
|
||||
set_property -dict {LOC BB42} [get_ports {fmcp_qsfp2_tx_p[2]}] ;# MGTYTXP1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 from J22.Y6 DP21_C2M_P
|
||||
set_property -dict {LOC BB43} [get_ports {fmcp_qsfp2_tx_n[2]}] ;# MGTYTXN1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 from J22.Y7 DP21_C2M_N
|
||||
set_property -dict {LOC BA45} [get_ports {fmcp_qsfp2_rx_p[2]}] ;# MGTYRXP1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 from J22.M10 DP21_M2C_P
|
||||
set_property -dict {LOC BA46} [get_ports {fmcp_qsfp2_rx_n[2]}] ;# MGTYRXN1_120 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1 from J22.M11 DP21_M2C_N
|
||||
set_property -dict {LOC AY42} [get_ports {fmcp_qsfp2_tx_p[0]}] ;# MGTYTXP2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 from J22.Z4 DP22_C2M_P
|
||||
set_property -dict {LOC AY43} [get_ports {fmcp_qsfp2_tx_n[0]}] ;# MGTYTXN2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 from J22.Z5 DP22_C2M_N
|
||||
set_property -dict {LOC AW45} [get_ports {fmcp_qsfp2_rx_p[0]}] ;# MGTYRXP2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 from J22.M6 DP22_M2C_P
|
||||
set_property -dict {LOC AW46} [get_ports {fmcp_qsfp2_rx_n[0]}] ;# MGTYRXN2_120 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1 from J22.M7 DP22_M2C_N
|
||||
set_property -dict {LOC AV42} [get_ports {fmcp_qsfp2_tx_p[1]}] ;# MGTYTXP3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 from J22.Y2 DP23_C2M_P
|
||||
set_property -dict {LOC AV43} [get_ports {fmcp_qsfp2_tx_n[1]}] ;# MGTYTXN3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 from J22.Y3 DP23_C2M_N
|
||||
set_property -dict {LOC AU45} [get_ports {fmcp_qsfp2_rx_p[1]}] ;# MGTYRXP3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 from J22.M2 DP23_M2C_P
|
||||
set_property -dict {LOC AU46} [get_ports {fmcp_qsfp2_rx_n[1]}] ;# MGTYRXN3_120 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1 from J22.M3 DP23_M2C_N
|
||||
set_property -dict {LOC AN40} [get_ports fmcp_qsfp2_mgt_refclk_p] ;# MGTREFCLK0P_120 from J22.Z20 GBTCLK5_M2C_P
|
||||
set_property -dict {LOC AN41} [get_ports fmcp_qsfp2_mgt_refclk_n] ;# MGTREFCLK0N_120 from J22.Z21 GBTCLK5_M2C_N
|
||||
#set_property -dict {LOC AM38} [get_ports fmcp_hspc_mgt_refclk_5_1_p] ;# MGTREFCLK1P_120 from U39.19 Q5_P from J22.B20 GBTCLK1_M2C_P
|
||||
#set_property -dict {LOC AM39} [get_ports fmcp_hspc_mgt_refclk_5_1_n] ;# MGTREFCLK1N_120 from U39.20 Q5_N from J22.B21 GBTCLK1_M2C_N
|
||||
|
||||
# reference clock
|
||||
create_clock -period 6.400 -name fmcp_qsfp2_mgt_refclk [get_ports fmcp_qsfp2_mgt_refclk_p]
|
||||
#create_clock -period 6.400 -name fmcp_hspc_mgt_refclk_5_1 [get_ports fmcp_hspc_mgt_refclk_5_1_p]
|
||||
|
||||
# FMC HPC1 J2
|
||||
#set_property -dict {LOC AY9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[0]}] ;# J2.G9 LA00_P_CC
|
||||
#set_property -dict {LOC BA9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[0]}] ;# J2.G10 LA00_N_CC
|
||||
#set_property -dict {LOC BF10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[1]}] ;# J2.D8 LA01_P_CC
|
||||
#set_property -dict {LOC BF9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[1]}] ;# J2.D9 LA01_N_CC
|
||||
#set_property -dict {LOC BC11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[2]}] ;# J2.H7 LA02_P
|
||||
#set_property -dict {LOC BD11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[2]}] ;# J2.H8 LA02_N
|
||||
#set_property -dict {LOC BD12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[3]}] ;# J2.G12 LA03_P
|
||||
#set_property -dict {LOC BE12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[3]}] ;# J2.G13 LA03_N
|
||||
#set_property -dict {LOC BD12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[4]}] ;# J2.H10 LA04_P
|
||||
#set_property -dict {LOC BF11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[4]}] ;# J2.H11 LA04_N
|
||||
#set_property -dict {LOC BE14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[5]}] ;# J2.D11 LA05_P
|
||||
#set_property -dict {LOC BF14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[5]}] ;# J2.D12 LA05_N
|
||||
#set_property -dict {LOC BD13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[6]}] ;# J2.C10 LA06_P
|
||||
#set_property -dict {LOC BE13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[6]}] ;# J2.C11 LA06_N
|
||||
#set_property -dict {LOC BC15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[7]}] ;# J2.H13 LA07_P
|
||||
#set_property -dict {LOC BD15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[7]}] ;# J2.H14 LA07_N
|
||||
#set_property -dict {LOC BE15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[8]}] ;# J2.G12 LA08_P
|
||||
#set_property -dict {LOC BF15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[8]}] ;# J2.G13 LA08_N
|
||||
#set_property -dict {LOC BA14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[9]}] ;# J2.D14 LA09_P
|
||||
#set_property -dict {LOC BB14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[9]}] ;# J2.D15 LA09_N
|
||||
#set_property -dict {LOC BB13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[10]}] ;# J2.C14 LA10_P
|
||||
#set_property -dict {LOC BB12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[10]}] ;# J2.C15 LA10_N
|
||||
#set_property -dict {LOC BA16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[11]}] ;# J2.H16 LA11_P
|
||||
#set_property -dict {LOC BA15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[11]}] ;# J2.H17 LA11_N
|
||||
#set_property -dict {LOC BC14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[12]}] ;# J2.G15 LA12_P
|
||||
#set_property -dict {LOC BC13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[12]}] ;# J2.G16 LA12_N
|
||||
#set_property -dict {LOC AY8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[13]}] ;# J2.D17 LA13_P
|
||||
#set_property -dict {LOC AY7 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[13]}] ;# J2.D18 LA13_N
|
||||
#set_property -dict {LOC AW8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[14]}] ;# J2.C18 LA14_P
|
||||
#set_property -dict {LOC AW7 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[14]}] ;# J2.C19 LA14_N
|
||||
#set_property -dict {LOC BB16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[15]}] ;# J2.H19 LA15_P
|
||||
#set_property -dict {LOC BC16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[15]}] ;# J2.H20 LA15_N
|
||||
#set_property -dict {LOC AV9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[16]}] ;# J2.G18 LA16_P
|
||||
#set_property -dict {LOC AB8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[16]}] ;# J2.G19 LA16_N
|
||||
#set_property -dict {LOC AR14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[17]}] ;# J2.D20 LA17_P_CC
|
||||
#set_property -dict {LOC AT14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[17]}] ;# J2.D21 LA17_N_CC
|
||||
#set_property -dict {LOC AP12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[18]}] ;# J2.C22 LA18_P_CC
|
||||
#set_property -dict {LOC AR12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[18]}] ;# J2.C23 LA18_N_CC
|
||||
#set_property -dict {LOC AW12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[19]}] ;# J2.H22 LA19_P
|
||||
#set_property -dict {LOC AY12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[19]}] ;# J2.H23 LA19_N
|
||||
#set_property -dict {LOC AW11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[20]}] ;# J2.G21 LA20_P
|
||||
#set_property -dict {LOC AY10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[20]}] ;# J2.G22 LA20_N
|
||||
#set_property -dict {LOC AU11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[21]}] ;# J2.H25 LA21_P
|
||||
#set_property -dict {LOC AV11 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[21]}] ;# J2.H26 LA21_N
|
||||
#set_property -dict {LOC AW13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[22]}] ;# J2.G24 LA22_P
|
||||
#set_property -dict {LOC AY13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[22]}] ;# J2.G25 LA22_N
|
||||
#set_property -dict {LOC AN16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[23]}] ;# J2.D23 LA23_P
|
||||
#set_property -dict {LOC AP16 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[23]}] ;# J2.D24 LA23_N
|
||||
#set_property -dict {LOC AP13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[24]}] ;# J2.H28 LA24_P
|
||||
#set_property -dict {LOC AR13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[24]}] ;# J2.H29 LA24_N
|
||||
#set_property -dict {LOC AT12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[25]}] ;# J2.G27 LA25_P
|
||||
#set_property -dict {LOC AU12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[25]}] ;# J2.G28 LA25_N
|
||||
#set_property -dict {LOC AK15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[26]}] ;# J2.D26 LA26_P
|
||||
#set_property -dict {LOC AL15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[26]}] ;# J2.D27 LA26_N
|
||||
#set_property -dict {LOC AL14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[27]}] ;# J2.C26 LA27_P
|
||||
#set_property -dict {LOC AM14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[27]}] ;# J2.C27 LA27_N
|
||||
#set_property -dict {LOC AV10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[28]}] ;# J2.H31 LA28_P
|
||||
#set_property -dict {LOC AW10 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[28]}] ;# J2.H32 LA28_N
|
||||
#set_property -dict {LOC AN15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[29]}] ;# J2.G30 LA29_P
|
||||
#set_property -dict {LOC AP15 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[29]}] ;# J2.G31 LA29_N
|
||||
#set_property -dict {LOC AK12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[30]}] ;# J2.H34 LA30_P
|
||||
#set_property -dict {LOC AL12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[30]}] ;# J2.H35 LA30_N
|
||||
#set_property -dict {LOC AM13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[31]}] ;# J2.G33 LA31_P
|
||||
#set_property -dict {LOC AM12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[31]}] ;# J2.G34 LA31_N
|
||||
#set_property -dict {LOC AJ13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[32]}] ;# J2.H37 LA32_P
|
||||
#set_property -dict {LOC AJ12 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[32]}] ;# J2.H38 LA32_N
|
||||
#set_property -dict {LOC AK14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_p[33]}] ;# J2.G36 LA33_P
|
||||
#set_property -dict {LOC AK13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_la_n[33]}] ;# J2.G37 LA33_N
|
||||
|
||||
#set_property -dict {LOC BC9 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_clk0_m2c_p}] ;# J2.H4 CLK0_M2C_P
|
||||
#set_property -dict {LOC BC8 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_clk0_m2c_n}] ;# J2.H5 CLK0_M2C_N
|
||||
#set_property -dict {LOC AV14 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_clk1_m2c_p}] ;# J2.G2 CLK1_M2C_P
|
||||
#set_property -dict {LOC AV13 IOSTANDARD LVDS DIFF_TERM TRUE} [get_ports {fmc_hpc1_clk1_m2c_n}] ;# J2.G3 CLK1_M2C_N
|
||||
|
||||
#set_property -dict {LOC BA7 IOSTANDARD LVCMOS18} [get_ports {fmc_hpc1_pg_m2c}] ;# J2.F1 PG_M2C
|
||||
#set_property -dict {LOC BB7 IOSTANDARD LVCMOS18} [get_ports {fmc_hpc1_prsnt_m2c_l}] ;# J2.H2 PRSNT_M2C_L
|
||||
|
||||
# DDR4 C1
|
||||
# 5x MT40A256M16GE-075E
|
||||
#set_property -dict {LOC D14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[0]}]
|
||||
#set_property -dict {LOC B15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[1]}]
|
||||
#set_property -dict {LOC B16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[2]}]
|
||||
#set_property -dict {LOC C14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[3]}]
|
||||
#set_property -dict {LOC C15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[4]}]
|
||||
#set_property -dict {LOC A13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[5]}]
|
||||
#set_property -dict {LOC A14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[6]}]
|
||||
#set_property -dict {LOC A15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[7]}]
|
||||
#set_property -dict {LOC A16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[8]}]
|
||||
#set_property -dict {LOC B12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[9]}]
|
||||
#set_property -dict {LOC C12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[10]}]
|
||||
#set_property -dict {LOC B13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[11]}]
|
||||
#set_property -dict {LOC C13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[12]}]
|
||||
#set_property -dict {LOC D15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[13]}]
|
||||
#set_property -dict {LOC H14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[14]}]
|
||||
#set_property -dict {LOC H15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[15]}]
|
||||
#set_property -dict {LOC F15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_adr[16]}]
|
||||
#set_property -dict {LOC G15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[0]}]
|
||||
#set_property -dict {LOC G13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_ba[1]}]
|
||||
#set_property -dict {LOC H13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_bg[0]}]
|
||||
#set_property -dict {LOC F14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_t}]
|
||||
#set_property -dict {LOC E14 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c1_ck_c}]
|
||||
#set_property -dict {LOC A10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cke}]
|
||||
#set_property -dict {LOC F13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_cs_n}]
|
||||
#set_property -dict {LOC E13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_act_n}]
|
||||
#set_property -dict {LOC C8 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_odt}]
|
||||
#set_property -dict {LOC G10 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c1_par}]
|
||||
#set_property -dict {LOC N20 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_reset_n}]
|
||||
#set_property -dict {LOC R17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_alert_n}]
|
||||
#set_property -dict {LOC A20 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c1_ten}]
|
||||
|
||||
#set_property -dict {LOC F11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[0]}] ;# U60.G2 DQL0
|
||||
#set_property -dict {LOC E11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[1]}] ;# U60.F7 DQL1
|
||||
#set_property -dict {LOC F10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[2]}] ;# U60.H3 DQL2
|
||||
#set_property -dict {LOC F9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[3]}] ;# U60.H7 DQL3
|
||||
#set_property -dict {LOC H12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[4]}] ;# U60.H2 DQL4
|
||||
#set_property -dict {LOC G12 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[5]}] ;# U60.H8 DQL5
|
||||
#set_property -dict {LOC E9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[6]}] ;# U60.J3 DQL6
|
||||
#set_property -dict {LOC D9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[7]}] ;# U60.J7 DQL7
|
||||
#set_property -dict {LOC R19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[8]}] ;# U60.A3 DQU0
|
||||
#set_property -dict {LOC P19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[9]}] ;# U60.B8 DQU1
|
||||
#set_property -dict {LOC M18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[10]}] ;# U60.C3 DQU2
|
||||
#set_property -dict {LOC M17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[11]}] ;# U60.C7 DQU3
|
||||
#set_property -dict {LOC N19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[12]}] ;# U60.C2 DQU4
|
||||
#set_property -dict {LOC N18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[13]}] ;# U60.C8 DQU5
|
||||
#set_property -dict {LOC N17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[14]}] ;# U60.D3 DQU6
|
||||
#set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[15]}] ;# U60.D7 DQU7
|
||||
#set_property -dict {LOC D11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[0]}] ;# U60.G3 DQSL_T
|
||||
#set_property -dict {LOC D10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[0]}] ;# U60.F3 DQSL_C
|
||||
#set_property -dict {LOC P17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[1]}] ;# U60.B7 DQSU_T
|
||||
#set_property -dict {LOC P16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[1]}] ;# U60.A7 DQSU_C
|
||||
#set_property -dict {LOC G11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[0]}] ;# U60.E7 DML_B/DBIL_B
|
||||
#set_property -dict {LOC R18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[1]}] ;# U60.E2 DMU_B/DBIU_B
|
||||
|
||||
#set_property -dict {LOC L16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[16]}] ;# U61.G2 DQL0
|
||||
#set_property -dict {LOC K16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[17]}] ;# U61.F7 DQL1
|
||||
#set_property -dict {LOC L18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[18]}] ;# U61.H3 DQL2
|
||||
#set_property -dict {LOC K18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[19]}] ;# U61.H7 DQL3
|
||||
#set_property -dict {LOC J17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[20]}] ;# U61.H2 DQL4
|
||||
#set_property -dict {LOC H17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[21]}] ;# U61.H8 DQL5
|
||||
#set_property -dict {LOC H19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[22]}] ;# U61.J3 DQL6
|
||||
#set_property -dict {LOC H18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[23]}] ;# U61.J7 DQL7
|
||||
#set_property -dict {LOC F19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[24]}] ;# U61.A3 DQU0
|
||||
#set_property -dict {LOC F18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[25]}] ;# U61.B8 DQU1
|
||||
#set_property -dict {LOC E19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[26]}] ;# U61.C3 DQU2
|
||||
#set_property -dict {LOC E18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[27]}] ;# U61.C7 DQU3
|
||||
#set_property -dict {LOC G20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[28]}] ;# U61.C2 DQU4
|
||||
#set_property -dict {LOC F20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[29]}] ;# U61.C8 DQU5
|
||||
#set_property -dict {LOC E17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[30]}] ;# U61.D3 DQU6
|
||||
#set_property -dict {LOC D16 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[31]}] ;# U61.D7 DQU7
|
||||
#set_property -dict {LOC K19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[2]}] ;# U61.G3 DQSL_T
|
||||
#set_property -dict {LOC J19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[2]}] ;# U61.F3 DQSL_C
|
||||
#set_property -dict {LOC F16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[3]}] ;# U61.B7 DQSU_T
|
||||
#set_property -dict {LOC E16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[3]}] ;# U61.A7 DQSU_C
|
||||
#set_property -dict {LOC K17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[2]}] ;# U61.E7 DML_B/DBIL_B
|
||||
#set_property -dict {LOC G18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[3]}] ;# U61.E2 DMU_B/DBIU_B
|
||||
|
||||
#set_property -dict {LOC D17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[32]}] ;# U62.G2 DQL0
|
||||
#set_property -dict {LOC C17 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[33]}] ;# U62.F7 DQL1
|
||||
#set_property -dict {LOC C19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[34]}] ;# U62.H3 DQL2
|
||||
#set_property -dict {LOC C18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[35]}] ;# U62.H7 DQL3
|
||||
#set_property -dict {LOC D20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[36]}] ;# U62.H2 DQL4
|
||||
#set_property -dict {LOC D19 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[37]}] ;# U62.H8 DQL5
|
||||
#set_property -dict {LOC C20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[38]}] ;# U62.J3 DQL6
|
||||
#set_property -dict {LOC B20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[39]}] ;# U62.J7 DQL7
|
||||
#set_property -dict {LOC N23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[40]}] ;# U62.A3 DQU0
|
||||
#set_property -dict {LOC M23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[41]}] ;# U62.B8 DQU1
|
||||
#set_property -dict {LOC R21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[42]}] ;# U62.C3 DQU2
|
||||
#set_property -dict {LOC P21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[43]}] ;# U62.C7 DQU3
|
||||
#set_property -dict {LOC R22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[44]}] ;# U62.C2 DQU4
|
||||
#set_property -dict {LOC P22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[45]}] ;# U62.C8 DQU5
|
||||
#set_property -dict {LOC T23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[46]}] ;# U62.D3 DQU6
|
||||
#set_property -dict {LOC R23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[47]}] ;# U62.D7 DQU7
|
||||
#set_property -dict {LOC A19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[4]}] ;# U62.G3 DQSL_T
|
||||
#set_property -dict {LOC A18 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[4]}] ;# U62.F3 DQSL_C
|
||||
#set_property -dict {LOC N22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[5]}] ;# U62.B7 DQSU_T
|
||||
#set_property -dict {LOC M22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[5]}] ;# U62.A7 DQSU_C
|
||||
#set_property -dict {LOC B18 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[4]}] ;# U62.E7 DML_B/DBIL_B
|
||||
#set_property -dict {LOC P20 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[5]}] ;# U62.E2 DMU_B/DBIU_B
|
||||
|
||||
#set_property -dict {LOC K24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[48]}] ;# U63.G2 DQL0
|
||||
#set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[49]}] ;# U63.F7 DQL1
|
||||
#set_property -dict {LOC M21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[50]}] ;# U63.H3 DQL2
|
||||
#set_property -dict {LOC L21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[51]}] ;# U63.H7 DQL3
|
||||
#set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[52]}] ;# U63.H2 DQL4
|
||||
#set_property -dict {LOC J21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[53]}] ;# U63.H8 DQL5
|
||||
#set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[54]}] ;# U63.J3 DQL6
|
||||
#set_property -dict {LOC J22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[55]}] ;# U63.J7 DQL7
|
||||
#set_property -dict {LOC H23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[56]}] ;# U63.A3 DQU0
|
||||
#set_property -dict {LOC H22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[57]}] ;# U63.B8 DQU1
|
||||
#set_property -dict {LOC E23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[58]}] ;# U63.C3 DQU2
|
||||
#set_property -dict {LOC E22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[59]}] ;# U63.C7 DQU3
|
||||
#set_property -dict {LOC F21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[60]}] ;# U63.C2 DQU4
|
||||
#set_property -dict {LOC E21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[61]}] ;# U63.C8 DQU5
|
||||
#set_property -dict {LOC F24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[62]}] ;# U63.D3 DQU6
|
||||
#set_property -dict {LOC F23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[63]}] ;# U63.D7 DQU7
|
||||
#set_property -dict {LOC M20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[6]}] ;# U63.G3 DQSL_T
|
||||
#set_property -dict {LOC L20 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[6]}] ;# U63.F3 DQSL_C
|
||||
#set_property -dict {LOC H24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[7]}] ;# U63.B7 DQSU_T
|
||||
#set_property -dict {LOC G23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[7]}] ;# U63.A7 DQSU_C
|
||||
#set_property -dict {LOC L23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[6]}] ;# U63.E7 DML_B/DBIL_B
|
||||
#set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[7]}] ;# U63.E2 DMU_B/DBIU_B
|
||||
|
||||
#set_property -dict {LOC A24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[64]}] ;# U64.G2 DQL0
|
||||
#set_property -dict {LOC A23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[65]}] ;# U64.F7 DQL1
|
||||
#set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[66]}] ;# U64.H3 DQL2
|
||||
#set_property -dict {LOC C23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[67]}] ;# U64.H7 DQL3
|
||||
#set_property -dict {LOC B23 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[68]}] ;# U64.H2 DQL4
|
||||
#set_property -dict {LOC B22 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[69]}] ;# U64.H8 DQL5
|
||||
#set_property -dict {LOC B21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[70]}] ;# U64.J3 DQL6
|
||||
#set_property -dict {LOC A21 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[71]}] ;# U64.J7 DQL7
|
||||
#set_property -dict {LOC D7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[72]}] ;# U64.A3 DQU0
|
||||
#set_property -dict {LOC C7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[73]}] ;# U64.B8 DQU1
|
||||
#set_property -dict {LOC B8 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[74]}] ;# U64.C3 DQU2
|
||||
#set_property -dict {LOC B7 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[75]}] ;# U64.C7 DQU3
|
||||
#set_property -dict {LOC C10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[76]}] ;# U64.C2 DQU4
|
||||
#set_property -dict {LOC B10 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[77]}] ;# U64.C8 DQU5
|
||||
#set_property -dict {LOC B11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[78]}] ;# U64.D3 DQU6
|
||||
#set_property -dict {LOC A11 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dq[79]}] ;# U64.D7 DQU7
|
||||
#set_property -dict {LOC D22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[8]}] ;# U64.G3 DQSL_T
|
||||
#set_property -dict {LOC C22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[8]}] ;# U64.F3 DQSL_C
|
||||
#set_property -dict {LOC A9 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_t[9]}] ;# U64.B7 DQSU_T
|
||||
#set_property -dict {LOC A8 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c1_dqs_c[9]}] ;# U64.A7 DQSU_C
|
||||
#set_property -dict {LOC E24 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[8]}] ;# U64.E7 DML_B/DBIL_B
|
||||
#set_property -dict {LOC C9 IOSTANDARD POD12_DCI } [get_ports {ddr4_c1_dm_dbi_n[9]}] ;# U64.E2 DMU_B/DBIU_B
|
||||
|
||||
# DDR4 C2
|
||||
# 5x MT40A256M16GE-075E
|
||||
#set_property -dict {LOC AM27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[0]}]
|
||||
#set_property -dict {LOC AL27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[1]}]
|
||||
#set_property -dict {LOC AP26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[2]}]
|
||||
#set_property -dict {LOC AP25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[3]}]
|
||||
#set_property -dict {LOC AN28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[4]}]
|
||||
#set_property -dict {LOC AM28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[5]}]
|
||||
#set_property -dict {LOC AP28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[6]}]
|
||||
#set_property -dict {LOC AP27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[7]}]
|
||||
#set_property -dict {LOC AN26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[8]}]
|
||||
#set_property -dict {LOC AM26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[9]}]
|
||||
#set_property -dict {LOC AR28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[10]}]
|
||||
#set_property -dict {LOC AR27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[11]}]
|
||||
#set_property -dict {LOC AV25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[12]}]
|
||||
#set_property -dict {LOC AT25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[13]}]
|
||||
#set_property -dict {LOC AV28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[14]}]
|
||||
#set_property -dict {LOC AU26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[15]}]
|
||||
#set_property -dict {LOC AV26 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_adr[16]}]
|
||||
#set_property -dict {LOC AR25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[0]}]
|
||||
#set_property -dict {LOC AU28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_ba[1]}]
|
||||
#set_property -dict {LOC AU27 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_bg[0]}]
|
||||
#set_property -dict {LOC AT26 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_t}]
|
||||
#set_property -dict {LOC AT27 IOSTANDARD DIFF_SSTL12_DCI} [get_ports {ddr4_c2_ck_c}]
|
||||
#set_property -dict {LOC AW28 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cke}]
|
||||
#set_property -dict {LOC AY29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_cs_n}]
|
||||
#set_property -dict {LOC AN25 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_act_n}]
|
||||
#set_property -dict {LOC BB29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_odt}]
|
||||
#set_property -dict {LOC BF29 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_c2_par}]
|
||||
#set_property -dict {LOC BD35 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_reset_n}]
|
||||
#set_property -dict {LOC AR29 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_alert_n}]
|
||||
#set_property -dict {LOC AY35 IOSTANDARD LVCMOS12 } [get_ports {ddr4_c2_ten}]
|
||||
|
||||
#set_property -dict {LOC BD30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[0]}] ;# U135.G2 DQL0
|
||||
#set_property -dict {LOC BE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[1]}] ;# U135.F7 DQL1
|
||||
#set_property -dict {LOC BD32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[2]}] ;# U135.H3 DQL2
|
||||
#set_property -dict {LOC BE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[3]}] ;# U135.H7 DQL3
|
||||
#set_property -dict {LOC BC33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[4]}] ;# U135.H2 DQL4
|
||||
#set_property -dict {LOC BD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[5]}] ;# U135.H8 DQL5
|
||||
#set_property -dict {LOC BC31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[6]}] ;# U135.J3 DQL6
|
||||
#set_property -dict {LOC BD31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[7]}] ;# U135.J7 DQL7
|
||||
#set_property -dict {LOC BA32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[8]}] ;# U135.A3 DQU0
|
||||
#set_property -dict {LOC BB33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[9]}] ;# U135.B8 DQU1
|
||||
#set_property -dict {LOC BA30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[10]}] ;# U135.C3 DQU2
|
||||
#set_property -dict {LOC BA31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[11]}] ;# U135.C7 DQU3
|
||||
#set_property -dict {LOC AW31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[12]}] ;# U135.C2 DQU4
|
||||
#set_property -dict {LOC AW32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[13]}] ;# U135.C8 DQU5
|
||||
#set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[14]}] ;# U135.D3 DQU6
|
||||
#set_property -dict {LOC AY33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[15]}] ;# U135.D7 DQU7
|
||||
#set_property -dict {LOC BF30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[0]}] ;# U135.G3 DQSL_T
|
||||
#set_property -dict {LOC BF31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[0]}] ;# U135.F3 DQSL_C
|
||||
#set_property -dict {LOC AY34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[1]}] ;# U135.B7 DQSU_T
|
||||
#set_property -dict {LOC BA34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[1]}] ;# U135.A7 DQSU_C
|
||||
#set_property -dict {LOC BE32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[0]}] ;# U135.E7 DML_B/DBIL_B
|
||||
#set_property -dict {LOC BB31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[1]}] ;# U135.E2 DMU_B/DBIU_B
|
||||
|
||||
#set_property -dict {LOC AV30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[16]}] ;# U136.G2 DQL0
|
||||
#set_property -dict {LOC AW30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[17]}] ;# U136.F7 DQL1
|
||||
#set_property -dict {LOC AU33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[18]}] ;# U136.H3 DQL2
|
||||
#set_property -dict {LOC AU34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[19]}] ;# U136.H7 DQL3
|
||||
#set_property -dict {LOC AT31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[20]}] ;# U136.H2 DQL4
|
||||
#set_property -dict {LOC AU32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[21]}] ;# U136.H8 DQL5
|
||||
#set_property -dict {LOC AU31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[22]}] ;# U136.J3 DQL6
|
||||
#set_property -dict {LOC AV31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[23]}] ;# U136.J7 DQL7
|
||||
#set_property -dict {LOC AR33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[24]}] ;# U136.A3 DQU0
|
||||
#set_property -dict {LOC AT34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[25]}] ;# U136.B8 DQU1
|
||||
#set_property -dict {LOC AT29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[26]}] ;# U136.C3 DQU2
|
||||
#set_property -dict {LOC AT30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[27]}] ;# U136.C7 DQU3
|
||||
#set_property -dict {LOC AP30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[28]}] ;# U136.C2 DQU4
|
||||
#set_property -dict {LOC AR30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[29]}] ;# U136.C8 DQU5
|
||||
#set_property -dict {LOC AN30 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[30]}] ;# U136.D3 DQU6
|
||||
#set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[31]}] ;# U136.D7 DQU7
|
||||
#set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[2]}] ;# U136.G3 DQSL_T
|
||||
#set_property -dict {LOC AV29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[2]}] ;# U136.F3 DQSL_C
|
||||
#set_property -dict {LOC AP31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[3]}] ;# U136.B7 DQSU_T
|
||||
#set_property -dict {LOC AP32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[3]}] ;# U136.A7 DQSU_C
|
||||
#set_property -dict {LOC AV33 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[2]}] ;# U136.E7 DML_B/DBIL_B
|
||||
#set_property -dict {LOC AR32 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[3]}] ;# U136.E2 DMU_B/DBIU_B
|
||||
|
||||
#set_property -dict {LOC BE34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[32]}] ;# U137.G2 DQL0
|
||||
#set_property -dict {LOC BF34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[33]}] ;# U137.F7 DQL1
|
||||
#set_property -dict {LOC BC35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[34]}] ;# U137.H3 DQL2
|
||||
#set_property -dict {LOC BC36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[35]}] ;# U137.H7 DQL3
|
||||
#set_property -dict {LOC BD36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[36]}] ;# U137.H2 DQL4
|
||||
#set_property -dict {LOC BE37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[37]}] ;# U137.H8 DQL5
|
||||
#set_property -dict {LOC BF36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[38]}] ;# U137.J3 DQL6
|
||||
#set_property -dict {LOC BF37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[39]}] ;# U137.J7 DQL7
|
||||
#set_property -dict {LOC BD37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[40]}] ;# U137.A3 DQU0
|
||||
#set_property -dict {LOC BE38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[41]}] ;# U137.B8 DQU1
|
||||
#set_property -dict {LOC BC39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[42]}] ;# U137.C3 DQU2
|
||||
#set_property -dict {LOC BD40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[43]}] ;# U137.C7 DQU3
|
||||
#set_property -dict {LOC BB38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[44]}] ;# U137.C2 DQU4
|
||||
#set_property -dict {LOC BB39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[45]}] ;# U137.C8 DQU5
|
||||
#set_property -dict {LOC BC38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[46]}] ;# U137.D3 DQU6
|
||||
#set_property -dict {LOC BD38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[47]}] ;# U137.D7 DQU7
|
||||
#set_property -dict {LOC BE35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[4]}] ;# U137.G3 DQSL_T
|
||||
#set_property -dict {LOC BF35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[4]}] ;# U137.F3 DQSL_C
|
||||
#set_property -dict {LOC BE39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[5]}] ;# U137.B7 DQSU_T
|
||||
#set_property -dict {LOC BF39 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[5]}] ;# U137.A7 DQSU_C
|
||||
#set_property -dict {LOC BC34 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[4]}] ;# U137.E7 DML_B/DBIL_B
|
||||
#set_property -dict {LOC BE40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[5]}] ;# U137.E2 DMU_B/DBIU_B
|
||||
|
||||
#set_property -dict {LOC BB36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[48]}] ;# U138.G2 DQL0
|
||||
#set_property -dict {LOC BB37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[49]}] ;# U138.F7 DQL1
|
||||
#set_property -dict {LOC BA39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[50]}] ;# U138.H3 DQL2
|
||||
#set_property -dict {LOC BA40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[51]}] ;# U138.H7 DQL3
|
||||
#set_property -dict {LOC AW40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[52]}] ;# U138.H2 DQL4
|
||||
#set_property -dict {LOC AY40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[53]}] ;# U138.H8 DQL5
|
||||
#set_property -dict {LOC AY38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[54]}] ;# U138.J3 DQL6
|
||||
#set_property -dict {LOC AY39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[55]}] ;# U138.J7 DQL7
|
||||
#set_property -dict {LOC AW35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[56]}] ;# U138.A3 DQU0
|
||||
#set_property -dict {LOC AW36 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[57]}] ;# U138.B8 DQU1
|
||||
#set_property -dict {LOC AU40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[58]}] ;# U138.C3 DQU2
|
||||
#set_property -dict {LOC AV40 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[59]}] ;# U138.C7 DQU3
|
||||
#set_property -dict {LOC AU38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[60]}] ;# U138.C2 DQU4
|
||||
#set_property -dict {LOC AU39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[61]}] ;# U138.C8 DQU5
|
||||
#set_property -dict {LOC AV38 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[62]}] ;# U138.D3 DQU6
|
||||
#set_property -dict {LOC AV39 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[63]}] ;# U138.D7 DQU7
|
||||
#set_property -dict {LOC BA35 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[6]}] ;# U138.G3 DQSL_T
|
||||
#set_property -dict {LOC BA36 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[6]}] ;# U138.F3 DQSL_C
|
||||
#set_property -dict {LOC AW37 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[7]}] ;# U138.B7 DQSU_T
|
||||
#set_property -dict {LOC AW38 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[7]}] ;# U138.A7 DQSU_C
|
||||
#set_property -dict {LOC AY37 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[6]}] ;# U138.E7 DML_B/DBIL_B
|
||||
#set_property -dict {LOC AV35 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[7]}] ;# U138.E2 DMU_B/DBIU_B
|
||||
|
||||
#set_property -dict {LOC BF26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[64]}] ;# U139.G2 DQL0
|
||||
#set_property -dict {LOC BF27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[65]}] ;# U139.F7 DQL1
|
||||
#set_property -dict {LOC BD28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[66]}] ;# U139.H3 DQL2
|
||||
#set_property -dict {LOC BE28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[67]}] ;# U139.H7 DQL3
|
||||
#set_property -dict {LOC BD27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[68]}] ;# U139.H2 DQL4
|
||||
#set_property -dict {LOC BE27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[69]}] ;# U139.H8 DQL5
|
||||
#set_property -dict {LOC BD25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[70]}] ;# U139.J3 DQL6
|
||||
#set_property -dict {LOC BD26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[71]}] ;# U139.J7 DQL7
|
||||
#set_property -dict {LOC BC25 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[72]}] ;# U139.A3 DQU0
|
||||
#set_property -dict {LOC BC26 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[73]}] ;# U139.B8 DQU1
|
||||
#set_property -dict {LOC BB28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[74]}] ;# U139.C3 DQU2
|
||||
#set_property -dict {LOC BC28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[75]}] ;# U139.C7 DQU3
|
||||
#set_property -dict {LOC AY27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[76]}] ;# U139.C2 DQU4
|
||||
#set_property -dict {LOC AY28 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[77]}] ;# U139.C8 DQU5
|
||||
#set_property -dict {LOC BA27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[78]}] ;# U139.D3 DQU6
|
||||
#set_property -dict {LOC BB27 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dq[79]}] ;# U139.D7 DQU7
|
||||
#set_property -dict {LOC BE25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[8]}] ;# U139.G3 DQSL_T
|
||||
#set_property -dict {LOC BF25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[8]}] ;# U139.F3 DQSL_C
|
||||
#set_property -dict {LOC BA26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_t[9]}] ;# U139.B7 DQSU_T
|
||||
#set_property -dict {LOC BB26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_c2_dqs_c[9]}] ;# U139.A7 DQSU_C
|
||||
#set_property -dict {LOC BE29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[8]}] ;# U139.E7 DML_B/DBIL_B
|
||||
#set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_c2_dm_dbi_n[9]}] ;# U139.E2 DMU_B/DBIU_B
|
||||
|
||||
# QSPI flash
|
||||
#set_property -dict {LOC AM19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[0]}]
|
||||
#set_property -dict {LOC AM18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[1]}]
|
||||
#set_property -dict {LOC AN20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[2]}]
|
||||
#set_property -dict {LOC AP20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_dq[3]}]
|
||||
#set_property -dict {LOC BF16 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {qspi_1_cs}]
|
||||
|
||||
#set_false_path -to [get_ports {qspi_1_dq[*] qspi_1_cs}]
|
||||
#set_output_delay 0 [get_ports {qspi_1_dq[*] qspi_1_cs}]
|
||||
#set_false_path -from [get_ports {qspi_1_dq}]
|
||||
#set_input_delay 0 [get_ports {qspi_1_dq}]
|
||||
124
example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga/Makefile
Normal file
124
example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga/Makefile
Normal file
@ -0,0 +1,124 @@
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcvu9p-flga2104-2L-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = virtexuplus
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = rtl/fpga.v
|
||||
SYN_FILES += rtl/fpga_core.v
|
||||
SYN_FILES += rtl/eth_xcvr_phy_wrapper.v
|
||||
SYN_FILES += rtl/debounce_switch.v
|
||||
SYN_FILES += rtl/sync_signal.v
|
||||
SYN_FILES += rtl/mdio_master.v
|
||||
SYN_FILES += rtl/i2c_master.v
|
||||
SYN_FILES += pll/si5341_i2c_init.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_1g_fifo.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_1g.v
|
||||
SYN_FILES += lib/eth/rtl/axis_gmii_rx.v
|
||||
SYN_FILES += lib/eth/rtl/axis_gmii_tx.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
|
||||
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
|
||||
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
|
||||
SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
|
||||
SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
|
||||
SYN_FILES += lib/eth/rtl/lfsr.v
|
||||
SYN_FILES += lib/eth/rtl/eth_axis_rx.v
|
||||
SYN_FILES += lib/eth/rtl/eth_axis_tx.v
|
||||
SYN_FILES += lib/eth/rtl/udp_complete_64.v
|
||||
SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v
|
||||
SYN_FILES += lib/eth/rtl/udp_64.v
|
||||
SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v
|
||||
SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v
|
||||
SYN_FILES += lib/eth/rtl/ip_complete_64.v
|
||||
SYN_FILES += lib/eth/rtl/ip_64.v
|
||||
SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v
|
||||
SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v
|
||||
SYN_FILES += lib/eth/rtl/ip_arb_mux.v
|
||||
SYN_FILES += lib/eth/rtl/arp.v
|
||||
SYN_FILES += lib/eth/rtl/arp_cache.v
|
||||
SYN_FILES += lib/eth/rtl/arp_eth_rx.v
|
||||
SYN_FILES += lib/eth/rtl/arp_eth_tx.v
|
||||
SYN_FILES += lib/eth/rtl/eth_arb_mux.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/axis_adapter.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/axis_switch.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/axis_register.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = fpga.xdc
|
||||
XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
|
||||
XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
|
||||
XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = ip/gig_ethernet_pcs_pma_0.tcl
|
||||
IP_TCL_FILES += ip/eth_xcvr_gt.tcl
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(FPGA_TOP).bit
|
||||
echo "open_hw" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
%_primary.mcs %_secondary.mcs %_primary.prm %_secondary.prm: %.bit
|
||||
echo "write_cfgmem -force -format mcs -size 256 -interface SPIx8 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in _primary.mcs _secondary.mcs _primary.prm _secondary.prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(FPGA_TOP)_primary.mcs $(FPGA_TOP)_secondary.mcs $(FPGA_TOP)_primary.prm $(FPGA_TOP)_secondary.prm
|
||||
echo "open_hw" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4_x8}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)_primary.mcs\" \"$(FPGA_TOP)_secondary.mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)_primary.prm\" \"$(FPGA_TOP)_secondary.prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
|
||||
50
example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga/config.tcl
Normal file
50
example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga/config.tcl
Normal file
@ -0,0 +1,50 @@
|
||||
# Copyright (c) 2023 Alex Forencich
|
||||
#
|
||||
# Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
# of this software and associated documentation files (the "Software"), to deal
|
||||
# in the Software without restriction, including without limitation the rights
|
||||
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
# copies of the Software, and to permit persons to whom the Software is
|
||||
# furnished to do so, subject to the following conditions:
|
||||
#
|
||||
# The above copyright notice and this permission notice shall be included in
|
||||
# all copies or substantial portions of the Software.
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
# THE SOFTWARE.
|
||||
|
||||
# Transceiver configuration
|
||||
set eth_xcvr_freerun_freq {125}
|
||||
set eth_xcvr_line_rate {25.78125}
|
||||
set eth_xcvr_sec_line_rate {0}
|
||||
set eth_xcvr_refclk_freq {156.25}
|
||||
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
|
||||
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
|
||||
set eth_xcvr_rx_eq_mode {DFE}
|
||||
|
||||
set xcvr_config [dict create]
|
||||
|
||||
dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate
|
||||
dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn
|
||||
dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
|
||||
dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate
|
||||
dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn
|
||||
dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
|
||||
dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode
|
||||
if {$eth_xcvr_sec_line_rate != 0} {
|
||||
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
|
||||
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
|
||||
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
|
||||
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
|
||||
} else {
|
||||
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
|
||||
}
|
||||
dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq
|
||||
|
||||
set_property -dict $xcvr_config [get_ips eth_xcvr_gt_full]
|
||||
set_property -dict $xcvr_config [get_ips eth_xcvr_gt_channel]
|
||||
124
example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga_10g/Makefile
Normal file
124
example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga_10g/Makefile
Normal file
@ -0,0 +1,124 @@
|
||||
|
||||
# FPGA settings
|
||||
FPGA_PART = xcvu9p-flga2104-2L-e
|
||||
FPGA_TOP = fpga
|
||||
FPGA_ARCH = virtexuplus
|
||||
|
||||
# Files for synthesis
|
||||
SYN_FILES = rtl/fpga.v
|
||||
SYN_FILES += rtl/fpga_core.v
|
||||
SYN_FILES += rtl/eth_xcvr_phy_wrapper.v
|
||||
SYN_FILES += rtl/debounce_switch.v
|
||||
SYN_FILES += rtl/sync_signal.v
|
||||
SYN_FILES += rtl/mdio_master.v
|
||||
SYN_FILES += rtl/i2c_master.v
|
||||
SYN_FILES += pll/si5341_i2c_init.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_1g_fifo.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_1g.v
|
||||
SYN_FILES += lib/eth/rtl/axis_gmii_rx.v
|
||||
SYN_FILES += lib/eth/rtl/axis_gmii_tx.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g_fifo.v
|
||||
SYN_FILES += lib/eth/rtl/eth_mac_10g.v
|
||||
SYN_FILES += lib/eth/rtl/axis_xgmii_rx_64.v
|
||||
SYN_FILES += lib/eth/rtl/axis_xgmii_tx_64.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_if.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_frame_sync.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_ber_mon.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_rx_watchdog.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_tx.v
|
||||
SYN_FILES += lib/eth/rtl/eth_phy_10g_tx_if.v
|
||||
SYN_FILES += lib/eth/rtl/xgmii_baser_dec_64.v
|
||||
SYN_FILES += lib/eth/rtl/xgmii_baser_enc_64.v
|
||||
SYN_FILES += lib/eth/rtl/lfsr.v
|
||||
SYN_FILES += lib/eth/rtl/eth_axis_rx.v
|
||||
SYN_FILES += lib/eth/rtl/eth_axis_tx.v
|
||||
SYN_FILES += lib/eth/rtl/udp_complete_64.v
|
||||
SYN_FILES += lib/eth/rtl/udp_checksum_gen_64.v
|
||||
SYN_FILES += lib/eth/rtl/udp_64.v
|
||||
SYN_FILES += lib/eth/rtl/udp_ip_rx_64.v
|
||||
SYN_FILES += lib/eth/rtl/udp_ip_tx_64.v
|
||||
SYN_FILES += lib/eth/rtl/ip_complete_64.v
|
||||
SYN_FILES += lib/eth/rtl/ip_64.v
|
||||
SYN_FILES += lib/eth/rtl/ip_eth_rx_64.v
|
||||
SYN_FILES += lib/eth/rtl/ip_eth_tx_64.v
|
||||
SYN_FILES += lib/eth/rtl/ip_arb_mux.v
|
||||
SYN_FILES += lib/eth/rtl/arp.v
|
||||
SYN_FILES += lib/eth/rtl/arp_cache.v
|
||||
SYN_FILES += lib/eth/rtl/arp_eth_rx.v
|
||||
SYN_FILES += lib/eth/rtl/arp_eth_tx.v
|
||||
SYN_FILES += lib/eth/rtl/eth_arb_mux.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/arbiter.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/priority_encoder.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/axis_adapter.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/axis_fifo.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/axis_switch.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/axis_register.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
|
||||
SYN_FILES += lib/eth/lib/axis/rtl/sync_reset.v
|
||||
|
||||
# XDC files
|
||||
XDC_FILES = fpga.xdc
|
||||
XDC_FILES += lib/eth/syn/vivado/eth_mac_fifo.tcl
|
||||
XDC_FILES += lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
|
||||
XDC_FILES += lib/eth/lib/axis/syn/vivado/sync_reset.tcl
|
||||
|
||||
# IP
|
||||
IP_TCL_FILES = ip/gig_ethernet_pcs_pma_0.tcl
|
||||
IP_TCL_FILES += ip/eth_xcvr_gt.tcl
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
include ../common/vivado.mk
|
||||
|
||||
program: $(FPGA_TOP).bit
|
||||
echo "open_hw" > program.tcl
|
||||
echo "connect_hw_server" >> program.tcl
|
||||
echo "open_hw_target" >> program.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
|
||||
echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> program.tcl
|
||||
echo "exit" >> program.tcl
|
||||
vivado -nojournal -nolog -mode batch -source program.tcl
|
||||
|
||||
%_primary.mcs %_secondary.mcs %_primary.prm %_secondary.prm: %.bit
|
||||
echo "write_cfgmem -force -format mcs -size 256 -interface SPIx8 -loadbit {up 0x0000000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
|
||||
echo "exit" >> generate_mcs.tcl
|
||||
vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
|
||||
mkdir -p rev
|
||||
COUNT=100; \
|
||||
while [ -e rev/$*_rev$$COUNT.bit ]; \
|
||||
do COUNT=$$((COUNT+1)); done; \
|
||||
COUNT=$$((COUNT-1)); \
|
||||
for x in _primary.mcs _secondary.mcs _primary.prm _secondary.prm; \
|
||||
do cp $*$$x rev/$*_rev$$COUNT$$x; \
|
||||
echo "Output: rev/$*_rev$$COUNT$$x"; done;
|
||||
|
||||
flash: $(FPGA_TOP)_primary.mcs $(FPGA_TOP)_secondary.mcs $(FPGA_TOP)_primary.prm $(FPGA_TOP)_secondary.prm
|
||||
echo "open_hw" > flash.tcl
|
||||
echo "connect_hw_server" >> flash.tcl
|
||||
echo "open_hw_target" >> flash.tcl
|
||||
echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
|
||||
echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
|
||||
echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4_x8}] 0]" >> flash.tcl
|
||||
echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
|
||||
echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP)_primary.mcs\" \"$(FPGA_TOP)_secondary.mcs\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP)_primary.prm\" \"$(FPGA_TOP)_secondary.prm\"] [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
|
||||
echo "program_hw_devices [current_hw_device]" >> flash.tcl
|
||||
echo "refresh_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
|
||||
echo "boot_hw_device [current_hw_device]" >> flash.tcl
|
||||
echo "exit" >> flash.tcl
|
||||
vivado -nojournal -nolog -mode batch -source flash.tcl
|
||||
|
||||
50
example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga_10g/config.tcl
Normal file
50
example/VCU118/fpga_fmc_htg_6qsfp_25g/fpga_10g/config.tcl
Normal file
@ -0,0 +1,50 @@
|
||||
# Copyright (c) 2023 Alex Forencich
|
||||
#
|
||||
# Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
# of this software and associated documentation files (the "Software"), to deal
|
||||
# in the Software without restriction, including without limitation the rights
|
||||
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
# copies of the Software, and to permit persons to whom the Software is
|
||||
# furnished to do so, subject to the following conditions:
|
||||
#
|
||||
# The above copyright notice and this permission notice shall be included in
|
||||
# all copies or substantial portions of the Software.
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
# THE SOFTWARE.
|
||||
|
||||
# Transceiver configuration
|
||||
set eth_xcvr_freerun_freq {125}
|
||||
set eth_xcvr_line_rate {10.3125}
|
||||
set eth_xcvr_sec_line_rate {0}
|
||||
set eth_xcvr_refclk_freq {156.25}
|
||||
set eth_xcvr_qpll_fracn [expr {int(fmod($eth_xcvr_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
|
||||
set eth_xcvr_sec_qpll_fracn [expr {int(fmod($eth_xcvr_sec_line_rate*1000/2 / $eth_xcvr_refclk_freq, 1)*pow(2, 24))}]
|
||||
set eth_xcvr_rx_eq_mode {DFE}
|
||||
|
||||
set xcvr_config [dict create]
|
||||
|
||||
dict set xcvr_config CONFIG.TX_LINE_RATE $eth_xcvr_line_rate
|
||||
dict set xcvr_config CONFIG.TX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn
|
||||
dict set xcvr_config CONFIG.TX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
|
||||
dict set xcvr_config CONFIG.RX_LINE_RATE $eth_xcvr_line_rate
|
||||
dict set xcvr_config CONFIG.RX_QPLL_FRACN_NUMERATOR $eth_xcvr_qpll_fracn
|
||||
dict set xcvr_config CONFIG.RX_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
|
||||
dict set xcvr_config CONFIG.RX_EQ_MODE $eth_xcvr_rx_eq_mode
|
||||
if {$eth_xcvr_sec_line_rate != 0} {
|
||||
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE true
|
||||
dict set xcvr_config CONFIG.SECONDARY_QPLL_FRACN_NUMERATOR $eth_xcvr_sec_qpll_fracn
|
||||
dict set xcvr_config CONFIG.SECONDARY_QPLL_LINE_RATE $eth_xcvr_sec_line_rate
|
||||
dict set xcvr_config CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY $eth_xcvr_refclk_freq
|
||||
} else {
|
||||
dict set xcvr_config CONFIG.SECONDARY_QPLL_ENABLE false
|
||||
}
|
||||
dict set xcvr_config CONFIG.FREERUN_FREQUENCY $eth_xcvr_freerun_freq
|
||||
|
||||
set_property -dict $xcvr_config [get_ips eth_xcvr_gt_full]
|
||||
set_property -dict $xcvr_config [get_ips eth_xcvr_gt_channel]
|
||||
76
example/VCU118/fpga_fmc_htg_6qsfp_25g/ip/eth_xcvr_gt.tcl
Normal file
76
example/VCU118/fpga_fmc_htg_6qsfp_25g/ip/eth_xcvr_gt.tcl
Normal file
@ -0,0 +1,76 @@
|
||||
# Copyright (c) 2021 Alex Forencich
|
||||
#
|
||||
# Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
# of this software and associated documentation files (the "Software"), to deal
|
||||
# in the Software without restriction, including without limitation the rights
|
||||
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
# copies of the Software, and to permit persons to whom the Software is
|
||||
# furnished to do so, subject to the following conditions:
|
||||
#
|
||||
# The above copyright notice and this permission notice shall be included in
|
||||
# all copies or substantial portions of the Software.
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
# THE SOFTWARE.
|
||||
|
||||
set base_name {eth_xcvr_gt}
|
||||
|
||||
set preset {GTY-10GBASE-R}
|
||||
|
||||
set freerun_freq {125}
|
||||
set line_rate {25.78125}
|
||||
set refclk_freq {156.25}
|
||||
set qpll_fracn [expr {int(fmod($line_rate*1000/2 / $refclk_freq, 1)*pow(2, 24))}]
|
||||
set user_data_width {64}
|
||||
set int_data_width $user_data_width
|
||||
set extra_ports [list]
|
||||
set extra_pll_ports [list {qpll0lock_out}]
|
||||
|
||||
set config [dict create]
|
||||
|
||||
dict set config TX_LINE_RATE $line_rate
|
||||
dict set config TX_REFCLK_FREQUENCY $refclk_freq
|
||||
dict set config TX_QPLL_FRACN_NUMERATOR $qpll_fracn
|
||||
dict set config TX_USER_DATA_WIDTH $user_data_width
|
||||
dict set config TX_INT_DATA_WIDTH $int_data_width
|
||||
dict set config RX_LINE_RATE $line_rate
|
||||
dict set config RX_REFCLK_FREQUENCY $refclk_freq
|
||||
dict set config RX_QPLL_FRACN_NUMERATOR $qpll_fracn
|
||||
dict set config RX_USER_DATA_WIDTH $user_data_width
|
||||
dict set config RX_INT_DATA_WIDTH $int_data_width
|
||||
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
|
||||
dict set config LOCATE_COMMON {CORE}
|
||||
dict set config LOCATE_RESET_CONTROLLER {CORE}
|
||||
dict set config LOCATE_TX_USER_CLOCKING {CORE}
|
||||
dict set config LOCATE_RX_USER_CLOCKING {CORE}
|
||||
dict set config LOCATE_USER_DATA_WIDTH_SIZING {CORE}
|
||||
dict set config FREERUN_FREQUENCY $freerun_freq
|
||||
dict set config DISABLE_LOC_XDC {1}
|
||||
|
||||
proc create_gtwizard_ip {name preset config} {
|
||||
create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -module_name $name
|
||||
set ip [get_ips $name]
|
||||
set_property CONFIG.preset $preset $ip
|
||||
set config_list {}
|
||||
dict for {name value} $config {
|
||||
lappend config_list "CONFIG.${name}" $value
|
||||
}
|
||||
set_property -dict $config_list $ip
|
||||
}
|
||||
|
||||
# variant with channel and common
|
||||
dict set config ENABLE_OPTIONAL_PORTS [concat $extra_pll_ports $extra_ports]
|
||||
dict set config LOCATE_COMMON {CORE}
|
||||
|
||||
create_gtwizard_ip "${base_name}_full" $preset $config
|
||||
|
||||
# variant with channel only
|
||||
dict set config ENABLE_OPTIONAL_PORTS $extra_ports
|
||||
dict set config LOCATE_COMMON {EXAMPLE_DESIGN}
|
||||
|
||||
create_gtwizard_ip "${base_name}_channel" $preset $config
|
||||
@ -0,0 +1,13 @@
|
||||
|
||||
create_ip -name gig_ethernet_pcs_pma -vendor xilinx.com -library ip -module_name gig_ethernet_pcs_pma_0
|
||||
|
||||
set_property -dict [list \
|
||||
CONFIG.Standard {SGMII} \
|
||||
CONFIG.Physical_Interface {LVDS} \
|
||||
CONFIG.Management_Interface {false} \
|
||||
CONFIG.SupportLevel {Include_Shared_Logic_in_Core} \
|
||||
CONFIG.LvdsRefClk {625} \
|
||||
CONFIG.TxLane0_Placement {DIFF_PAIR_2} \
|
||||
CONFIG.RxLane0_Placement {DIFF_PAIR_0} \
|
||||
CONFIG.Tx_In_Upper_Nibble {0} \
|
||||
] [get_ips gig_ethernet_pcs_pma_0]
|
||||
1
example/VCU118/fpga_fmc_htg_6qsfp_25g/lib/eth
Symbolic link
1
example/VCU118/fpga_fmc_htg_6qsfp_25g/lib/eth
Symbolic link
@ -0,0 +1 @@
|
||||
../../../../
|
||||
@ -0,0 +1,412 @@
|
||||
# Si534x/7x/8x/9x Registers Script
|
||||
#
|
||||
# Part: Si5341
|
||||
# Project File: X:\Projects\verilog-ethernet\example\VCU118\fpga_fmc_htg_6qsfp_25g\pll\VCU118_HTG_FMC_6QSFP_156-HTG6Q156.slabtimeproj
|
||||
# Design ID: HTG6Q156
|
||||
# Includes Pre/Post Download Control Register Writes: Yes
|
||||
# Die Revision: B1
|
||||
# Creator: ClockBuilder Pro v4.1 [2021-09-22]
|
||||
# Created On: 2023-07-19 01:56:40 GMT-07:00
|
||||
Address,Data
|
||||
#
|
||||
# Start configuration preamble
|
||||
0x0B24,0xC0
|
||||
0x0B25,0x00
|
||||
# Rev D stuck divider fix
|
||||
0x0502,0x01
|
||||
0x0505,0x03
|
||||
0x0957,0x17
|
||||
0x0B4E,0x1A
|
||||
# End configuration preamble
|
||||
#
|
||||
# Delay 300 msec
|
||||
# Delay is worst case time for device to complete any calibration
|
||||
# that is running due to device state change previous to this script
|
||||
# being processed.
|
||||
#
|
||||
# Start configuration registers
|
||||
0x0006,0x00
|
||||
0x0007,0x00
|
||||
0x0008,0x00
|
||||
0x000B,0x74
|
||||
0x0017,0xD0
|
||||
0x0018,0xFF
|
||||
0x0021,0x0D
|
||||
0x0022,0x00
|
||||
0x002B,0x02
|
||||
0x002C,0x34
|
||||
0x002D,0x10
|
||||
0x002E,0x00
|
||||
0x002F,0x00
|
||||
0x0030,0x00
|
||||
0x0031,0x00
|
||||
0x0032,0xB1
|
||||
0x0033,0x00
|
||||
0x0034,0x00
|
||||
0x0035,0x00
|
||||
0x0036,0x00
|
||||
0x0037,0x00
|
||||
0x0038,0x00
|
||||
0x0039,0x00
|
||||
0x003A,0xB1
|
||||
0x003B,0x00
|
||||
0x003C,0x00
|
||||
0x003D,0x00
|
||||
0x0041,0x00
|
||||
0x0042,0x00
|
||||
0x0043,0x07
|
||||
0x0044,0x00
|
||||
0x009E,0x00
|
||||
0x0102,0x01
|
||||
0x0108,0x06
|
||||
0x0109,0x09
|
||||
0x010A,0x33
|
||||
0x010B,0x08
|
||||
0x010D,0x06
|
||||
0x010E,0x09
|
||||
0x010F,0x33
|
||||
0x0110,0x08
|
||||
0x0112,0x06
|
||||
0x0113,0x09
|
||||
0x0114,0x33
|
||||
0x0115,0x08
|
||||
0x0117,0x06
|
||||
0x0118,0x09
|
||||
0x0119,0x33
|
||||
0x011A,0x08
|
||||
0x011C,0x06
|
||||
0x011D,0x09
|
||||
0x011E,0x33
|
||||
0x011F,0x08
|
||||
0x0121,0x06
|
||||
0x0122,0x09
|
||||
0x0123,0x33
|
||||
0x0124,0x08
|
||||
0x0126,0x06
|
||||
0x0127,0x09
|
||||
0x0128,0x33
|
||||
0x0129,0x08
|
||||
0x012B,0x06
|
||||
0x012C,0x09
|
||||
0x012D,0x33
|
||||
0x012E,0x08
|
||||
0x0130,0x06
|
||||
0x0131,0x09
|
||||
0x0132,0x33
|
||||
0x0133,0x08
|
||||
0x013A,0x01
|
||||
0x013B,0x09
|
||||
0x013C,0x3B
|
||||
0x013D,0x28
|
||||
0x013F,0x00
|
||||
0x0140,0x00
|
||||
0x0141,0x40
|
||||
0x0206,0x00
|
||||
0x0208,0x00
|
||||
0x0209,0x00
|
||||
0x020A,0x00
|
||||
0x020B,0x00
|
||||
0x020C,0x00
|
||||
0x020D,0x00
|
||||
0x020E,0x00
|
||||
0x020F,0x00
|
||||
0x0210,0x00
|
||||
0x0211,0x00
|
||||
0x0212,0x00
|
||||
0x0213,0x00
|
||||
0x0214,0x00
|
||||
0x0215,0x00
|
||||
0x0216,0x00
|
||||
0x0217,0x00
|
||||
0x0218,0x00
|
||||
0x0219,0x00
|
||||
0x021A,0x00
|
||||
0x021B,0x00
|
||||
0x021C,0x02
|
||||
0x021D,0x00
|
||||
0x021E,0x00
|
||||
0x021F,0x00
|
||||
0x0220,0x00
|
||||
0x0221,0x00
|
||||
0x0222,0x01
|
||||
0x0223,0x00
|
||||
0x0224,0x00
|
||||
0x0225,0x00
|
||||
0x0226,0x00
|
||||
0x0227,0x00
|
||||
0x0228,0x00
|
||||
0x0229,0x00
|
||||
0x022A,0x00
|
||||
0x022B,0x00
|
||||
0x022C,0x00
|
||||
0x022D,0x00
|
||||
0x022E,0x00
|
||||
0x022F,0x00
|
||||
0x0235,0x00
|
||||
0x0236,0x00
|
||||
0x0237,0x00
|
||||
0x0238,0x00
|
||||
0x0239,0x56
|
||||
0x023A,0x00
|
||||
0x023B,0x00
|
||||
0x023C,0x00
|
||||
0x023D,0x00
|
||||
0x023E,0x80
|
||||
0x024A,0x00
|
||||
0x024B,0x00
|
||||
0x024C,0x00
|
||||
0x024D,0x00
|
||||
0x024E,0x00
|
||||
0x024F,0x00
|
||||
0x0250,0x00
|
||||
0x0251,0x00
|
||||
0x0252,0x00
|
||||
0x0253,0x00
|
||||
0x0254,0x00
|
||||
0x0255,0x00
|
||||
0x0256,0x00
|
||||
0x0257,0x00
|
||||
0x0258,0x00
|
||||
0x0259,0x00
|
||||
0x025A,0x00
|
||||
0x025B,0x00
|
||||
0x025C,0x00
|
||||
0x025D,0x00
|
||||
0x025E,0x00
|
||||
0x025F,0x00
|
||||
0x0260,0x00
|
||||
0x0261,0x00
|
||||
0x0262,0x00
|
||||
0x0263,0x00
|
||||
0x0264,0x00
|
||||
0x0268,0x00
|
||||
0x0269,0x00
|
||||
0x026A,0x00
|
||||
0x026B,0x48
|
||||
0x026C,0x54
|
||||
0x026D,0x47
|
||||
0x026E,0x36
|
||||
0x026F,0x51
|
||||
0x0270,0x31
|
||||
0x0271,0x35
|
||||
0x0272,0x36
|
||||
0x0302,0x00
|
||||
0x0303,0x00
|
||||
0x0304,0x00
|
||||
0x0305,0x80
|
||||
0x0306,0x15
|
||||
0x0307,0x00
|
||||
0x0308,0x00
|
||||
0x0309,0x00
|
||||
0x030A,0x00
|
||||
0x030B,0x80
|
||||
0x030C,0x00
|
||||
0x030D,0x00
|
||||
0x030E,0x00
|
||||
0x030F,0x00
|
||||
0x0310,0x00
|
||||
0x0311,0x00
|
||||
0x0312,0x00
|
||||
0x0313,0x00
|
||||
0x0314,0x00
|
||||
0x0315,0x00
|
||||
0x0316,0x00
|
||||
0x0317,0x00
|
||||
0x0318,0x00
|
||||
0x0319,0x00
|
||||
0x031A,0x00
|
||||
0x031B,0x00
|
||||
0x031C,0x00
|
||||
0x031D,0x00
|
||||
0x031E,0x00
|
||||
0x031F,0x00
|
||||
0x0320,0x00
|
||||
0x0321,0x00
|
||||
0x0322,0x00
|
||||
0x0323,0x00
|
||||
0x0324,0x00
|
||||
0x0325,0x00
|
||||
0x0326,0x00
|
||||
0x0327,0x00
|
||||
0x0328,0x00
|
||||
0x0329,0x00
|
||||
0x032A,0x00
|
||||
0x032B,0x00
|
||||
0x032C,0x00
|
||||
0x032D,0x00
|
||||
0x032E,0x00
|
||||
0x032F,0x00
|
||||
0x0330,0x00
|
||||
0x0331,0x00
|
||||
0x0332,0x00
|
||||
0x0333,0x00
|
||||
0x0334,0x00
|
||||
0x0335,0x00
|
||||
0x0336,0x00
|
||||
0x0337,0x00
|
||||
0x0338,0x00
|
||||
0x0339,0x1F
|
||||
0x033B,0x00
|
||||
0x033C,0x00
|
||||
0x033D,0x00
|
||||
0x033E,0x00
|
||||
0x033F,0x00
|
||||
0x0340,0x00
|
||||
0x0341,0x00
|
||||
0x0342,0x00
|
||||
0x0343,0x00
|
||||
0x0344,0x00
|
||||
0x0345,0x00
|
||||
0x0346,0x00
|
||||
0x0347,0x00
|
||||
0x0348,0x00
|
||||
0x0349,0x00
|
||||
0x034A,0x00
|
||||
0x034B,0x00
|
||||
0x034C,0x00
|
||||
0x034D,0x00
|
||||
0x034E,0x00
|
||||
0x034F,0x00
|
||||
0x0350,0x00
|
||||
0x0351,0x00
|
||||
0x0352,0x00
|
||||
0x0353,0x00
|
||||
0x0354,0x00
|
||||
0x0355,0x00
|
||||
0x0356,0x00
|
||||
0x0357,0x00
|
||||
0x0358,0x00
|
||||
0x0359,0x00
|
||||
0x035A,0x00
|
||||
0x035B,0x00
|
||||
0x035C,0x00
|
||||
0x035D,0x00
|
||||
0x035E,0x00
|
||||
0x035F,0x00
|
||||
0x0360,0x00
|
||||
0x0361,0x00
|
||||
0x0362,0x00
|
||||
0x0802,0x00
|
||||
0x0803,0x00
|
||||
0x0804,0x00
|
||||
0x0805,0x00
|
||||
0x0806,0x00
|
||||
0x0807,0x00
|
||||
0x0808,0x00
|
||||
0x0809,0x00
|
||||
0x080A,0x00
|
||||
0x080B,0x00
|
||||
0x080C,0x00
|
||||
0x080D,0x00
|
||||
0x080E,0x00
|
||||
0x080F,0x00
|
||||
0x0810,0x00
|
||||
0x0811,0x00
|
||||
0x0812,0x00
|
||||
0x0813,0x00
|
||||
0x0814,0x00
|
||||
0x0815,0x00
|
||||
0x0816,0x00
|
||||
0x0817,0x00
|
||||
0x0818,0x00
|
||||
0x0819,0x00
|
||||
0x081A,0x00
|
||||
0x081B,0x00
|
||||
0x081C,0x00
|
||||
0x081D,0x00
|
||||
0x081E,0x00
|
||||
0x081F,0x00
|
||||
0x0820,0x00
|
||||
0x0821,0x00
|
||||
0x0822,0x00
|
||||
0x0823,0x00
|
||||
0x0824,0x00
|
||||
0x0825,0x00
|
||||
0x0826,0x00
|
||||
0x0827,0x00
|
||||
0x0828,0x00
|
||||
0x0829,0x00
|
||||
0x082A,0x00
|
||||
0x082B,0x00
|
||||
0x082C,0x00
|
||||
0x082D,0x00
|
||||
0x082E,0x00
|
||||
0x082F,0x00
|
||||
0x0830,0x00
|
||||
0x0831,0x00
|
||||
0x0832,0x00
|
||||
0x0833,0x00
|
||||
0x0834,0x00
|
||||
0x0835,0x00
|
||||
0x0836,0x00
|
||||
0x0837,0x00
|
||||
0x0838,0x00
|
||||
0x0839,0x00
|
||||
0x083A,0x00
|
||||
0x083B,0x00
|
||||
0x083C,0x00
|
||||
0x083D,0x00
|
||||
0x083E,0x00
|
||||
0x083F,0x00
|
||||
0x0840,0x00
|
||||
0x0841,0x00
|
||||
0x0842,0x00
|
||||
0x0843,0x00
|
||||
0x0844,0x00
|
||||
0x0845,0x00
|
||||
0x0846,0x00
|
||||
0x0847,0x00
|
||||
0x0848,0x00
|
||||
0x0849,0x00
|
||||
0x084A,0x00
|
||||
0x084B,0x00
|
||||
0x084C,0x00
|
||||
0x084D,0x00
|
||||
0x084E,0x00
|
||||
0x084F,0x00
|
||||
0x0850,0x00
|
||||
0x0851,0x00
|
||||
0x0852,0x00
|
||||
0x0853,0x00
|
||||
0x0854,0x00
|
||||
0x0855,0x00
|
||||
0x0856,0x00
|
||||
0x0857,0x00
|
||||
0x0858,0x00
|
||||
0x0859,0x00
|
||||
0x085A,0x00
|
||||
0x085B,0x00
|
||||
0x085C,0x00
|
||||
0x085D,0x00
|
||||
0x085E,0x00
|
||||
0x085F,0x00
|
||||
0x0860,0x00
|
||||
0x0861,0x00
|
||||
0x090E,0x00
|
||||
0x091C,0x04
|
||||
0x0943,0x00
|
||||
0x0949,0x04
|
||||
0x094A,0x40
|
||||
0x094E,0x49
|
||||
0x094F,0x02
|
||||
0x095E,0x00
|
||||
0x0A02,0x00
|
||||
0x0A03,0x01
|
||||
0x0A04,0x01
|
||||
0x0A05,0x01
|
||||
0x0A14,0x00
|
||||
0x0A1A,0x00
|
||||
0x0A20,0x00
|
||||
0x0A26,0x00
|
||||
0x0A2C,0x00
|
||||
0x0B44,0x0F
|
||||
0x0B4A,0x1E
|
||||
0x0B57,0xA5
|
||||
0x0B58,0x00
|
||||
# End configuration registers
|
||||
#
|
||||
# Start configuration postamble
|
||||
0x001C,0x01
|
||||
0x0B24,0xC3
|
||||
0x0B25,0x02
|
||||
# End configuration postamble
|
||||
Binary file not shown.
599
example/VCU118/fpga_fmc_htg_6qsfp_25g/pll/si5341_i2c_init.py
Executable file
599
example/VCU118/fpga_fmc_htg_6qsfp_25g/pll/si5341_i2c_init.py
Executable file
@ -0,0 +1,599 @@
|
||||
#!/usr/bin/env python
|
||||
"""
|
||||
Generates an I2C init module for multiple chips
|
||||
"""
|
||||
|
||||
from jinja2 import Template
|
||||
|
||||
|
||||
def si5341_cmds(regs, dev_addr=0x77):
|
||||
cur_page = None
|
||||
cur_addr = None
|
||||
|
||||
cmds = []
|
||||
|
||||
print(f"Reading register list file '{regs}'...")
|
||||
|
||||
with open(regs, "r") as f:
|
||||
for line in f:
|
||||
line = line.strip()
|
||||
if not line or line == "Address,Data":
|
||||
continue
|
||||
if line[0] == '#':
|
||||
cmds.append(f"// {line[1:].strip()}")
|
||||
|
||||
if line.startswith("# Delay"):
|
||||
cmds.append("9'b000011010; // delay 300 ms")
|
||||
cur_addr = None
|
||||
|
||||
continue
|
||||
|
||||
d = line.split(",")
|
||||
addr = int(d[0], 0)
|
||||
page = (addr >> 8) & 0xff
|
||||
data = int(d[1], 0)
|
||||
|
||||
if page != cur_page:
|
||||
cmds.append(f"{{2'b01, 7'h{dev_addr:02x}}};")
|
||||
cmds.append("{1'b1, 8'h01};")
|
||||
cmds.append(f"{{1'b1, 8'h{page:02x}}}; // set page {page:#04x}")
|
||||
cur_page = page
|
||||
cur_addr = None
|
||||
|
||||
if addr != cur_addr:
|
||||
cmds.append(f"{{2'b01, 7'h{dev_addr:02x}}};")
|
||||
cmds.append(f"{{1'b1, 8'h{addr & 0xff:02x}}};")
|
||||
cur_addr = addr
|
||||
|
||||
cmds.append(f"{{1'b1, 8'h{data:02x}}}; // write {data:#04x} to {addr:#06x}")
|
||||
cur_addr += 1
|
||||
|
||||
return cmds
|
||||
|
||||
|
||||
def mux_cmds(val, dev_addr):
|
||||
cmds = []
|
||||
cmds.append(f"{{2'b01, 7'h{dev_addr:02x}}};")
|
||||
cmds.append(f"{{1'b1, 8'h{val:02x}}};")
|
||||
cmds.append("9'b001000001; // I2C stop")
|
||||
return cmds
|
||||
|
||||
|
||||
def main():
|
||||
cmds = []
|
||||
|
||||
cmds.append("// Initial delay")
|
||||
cmds.append("9'b000010110; // delay 30 ms")
|
||||
|
||||
# Si5341 on FMC+
|
||||
cmds.append("// Set muxes to select U7 Si5341 on HTG-FMC-x6-QSFP28")
|
||||
cmds.extend(mux_cmds(0x00, 0x74))
|
||||
cmds.extend(mux_cmds(0x02, 0x75))
|
||||
|
||||
cmds.extend(si5341_cmds("VCU118_HTG_FMC_6QSFP_156-HTG6Q156-Registers.txt", 0x77))
|
||||
|
||||
generate(cmds)
|
||||
|
||||
|
||||
def generate(cmds=None, name=None, output=None):
|
||||
if cmds is None:
|
||||
raise Exception("Command list is required")
|
||||
|
||||
if name is None:
|
||||
name = "si5341_i2c_init"
|
||||
|
||||
if output is None:
|
||||
output = name + ".v"
|
||||
|
||||
print(f"Generating Si5341 I2C init module {name}...")
|
||||
|
||||
cmds.append("9'd0; // end")
|
||||
|
||||
cmd_str = ""
|
||||
cmd_count = 0
|
||||
|
||||
for cmd in cmds:
|
||||
if cmd.startswith('//'):
|
||||
cmd_str += f" {cmd}\n"
|
||||
else:
|
||||
cmd_str += f" init_data[{cmd_count}] = {cmd}\n"
|
||||
cmd_count += 1
|
||||
|
||||
t = Template(u"""/*
|
||||
|
||||
Copyright (c) 2015-2021 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* {{name}}
|
||||
*/
|
||||
module {{name}} (
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
/*
|
||||
* I2C master interface
|
||||
*/
|
||||
output wire [6:0] m_axis_cmd_address,
|
||||
output wire m_axis_cmd_start,
|
||||
output wire m_axis_cmd_read,
|
||||
output wire m_axis_cmd_write,
|
||||
output wire m_axis_cmd_write_multiple,
|
||||
output wire m_axis_cmd_stop,
|
||||
output wire m_axis_cmd_valid,
|
||||
input wire m_axis_cmd_ready,
|
||||
|
||||
output wire [7:0] m_axis_data_tdata,
|
||||
output wire m_axis_data_tvalid,
|
||||
input wire m_axis_data_tready,
|
||||
output wire m_axis_data_tlast,
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
output wire busy,
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
input wire start
|
||||
);
|
||||
|
||||
/*
|
||||
|
||||
Generic module for I2C bus initialization. Good for use when multiple devices
|
||||
on an I2C bus must be initialized on system start without intervention of a
|
||||
general-purpose processor.
|
||||
|
||||
Copy this file and change init_data and INIT_DATA_LEN as needed.
|
||||
|
||||
This module can be used in two modes: simple device initialization, or multiple
|
||||
device initialization. In multiple device mode, the same initialization sequence
|
||||
can be performed on multiple different device addresses.
|
||||
|
||||
To use single device mode, only use the start write to address and write data commands.
|
||||
The module will generate the I2C commands in sequential order. Terminate the list
|
||||
with a 0 entry.
|
||||
|
||||
To use the multiple device mode, use the start data and start address block commands
|
||||
to set up lists of initialization data and device addresses. The module enters
|
||||
multiple device mode upon seeing a start data block command. The module stores the
|
||||
offset of the start of the data block and then skips ahead until it reaches a start
|
||||
address block command. The module will store the offset to the address block and
|
||||
read the first address in the block. Then it will jump back to the data block
|
||||
and execute it, substituting the stored address for each current address write
|
||||
command. Upon reaching the start address block command, the module will read out the
|
||||
next address and start again at the top of the data block. If the module encounters
|
||||
a start data block command while looking for an address, then it will store a new data
|
||||
offset and then look for a start address block command. Terminate the list with a 0
|
||||
entry. Normal address commands will operate normally inside a data block.
|
||||
|
||||
Commands:
|
||||
|
||||
00 0000000 : stop
|
||||
00 0000001 : exit multiple device mode
|
||||
00 0000011 : start write to current address
|
||||
00 0001000 : start address block
|
||||
00 0001001 : start data block
|
||||
00 001dddd : delay 2**(16+d) cycles
|
||||
00 1000001 : send I2C stop
|
||||
01 aaaaaaa : start write to address
|
||||
1 dddddddd : write 8-bit data
|
||||
|
||||
Examples
|
||||
|
||||
write 0x11223344 to register 0x0004 on device at 0x50
|
||||
|
||||
01 1010000 start write to 0x50
|
||||
1 00000000 write address 0x0004
|
||||
1 00000100
|
||||
1 00010001 write data 0x11223344
|
||||
1 00100010
|
||||
1 00110011
|
||||
1 01000100
|
||||
0 00000000 stop
|
||||
|
||||
write 0x11223344 to register 0x0004 on devices at 0x50, 0x51, 0x52, and 0x53
|
||||
|
||||
00 0001001 start data block
|
||||
00 0000011 start write to current address
|
||||
1 00000000 write address 0x0004
|
||||
1 00000100
|
||||
1 00010001 write data 0x11223344
|
||||
1 00100010
|
||||
1 00110011
|
||||
1 01000100
|
||||
00 0001000 start address block
|
||||
01 1010000 address 0x50
|
||||
01 1010001 address 0x51
|
||||
01 1010010 address 0x52
|
||||
01 1010011 address 0x53
|
||||
00 0000000 stop
|
||||
|
||||
*/
|
||||
|
||||
// init_data ROM
|
||||
localparam INIT_DATA_LEN = {{cmd_count}};
|
||||
|
||||
reg [8:0] init_data [INIT_DATA_LEN-1:0];
|
||||
|
||||
initial begin
|
||||
{{cmd_str-}}
|
||||
end
|
||||
|
||||
localparam [3:0]
|
||||
STATE_IDLE = 3'd0,
|
||||
STATE_RUN = 3'd1,
|
||||
STATE_TABLE_1 = 3'd2,
|
||||
STATE_TABLE_2 = 3'd3,
|
||||
STATE_TABLE_3 = 3'd4;
|
||||
|
||||
reg [4:0] state_reg = STATE_IDLE, state_next;
|
||||
|
||||
parameter AW = $clog2(INIT_DATA_LEN);
|
||||
|
||||
reg [8:0] init_data_reg = 9'd0;
|
||||
|
||||
reg [AW-1:0] address_reg = {AW{1'b0}}, address_next;
|
||||
reg [AW-1:0] address_ptr_reg = {AW{1'b0}}, address_ptr_next;
|
||||
reg [AW-1:0] data_ptr_reg = {AW{1'b0}}, data_ptr_next;
|
||||
|
||||
reg [6:0] cur_address_reg = 7'd0, cur_address_next;
|
||||
|
||||
reg [31:0] delay_counter_reg = 32'd0, delay_counter_next;
|
||||
|
||||
reg [6:0] m_axis_cmd_address_reg = 7'd0, m_axis_cmd_address_next;
|
||||
reg m_axis_cmd_start_reg = 1'b0, m_axis_cmd_start_next;
|
||||
reg m_axis_cmd_write_reg = 1'b0, m_axis_cmd_write_next;
|
||||
reg m_axis_cmd_stop_reg = 1'b0, m_axis_cmd_stop_next;
|
||||
reg m_axis_cmd_valid_reg = 1'b0, m_axis_cmd_valid_next;
|
||||
|
||||
reg [7:0] m_axis_data_tdata_reg = 8'd0, m_axis_data_tdata_next;
|
||||
reg m_axis_data_tvalid_reg = 1'b0, m_axis_data_tvalid_next;
|
||||
|
||||
reg start_flag_reg = 1'b0, start_flag_next;
|
||||
|
||||
reg busy_reg = 1'b0;
|
||||
|
||||
assign m_axis_cmd_address = m_axis_cmd_address_reg;
|
||||
assign m_axis_cmd_start = m_axis_cmd_start_reg;
|
||||
assign m_axis_cmd_read = 1'b0;
|
||||
assign m_axis_cmd_write = m_axis_cmd_write_reg;
|
||||
assign m_axis_cmd_write_multiple = 1'b0;
|
||||
assign m_axis_cmd_stop = m_axis_cmd_stop_reg;
|
||||
assign m_axis_cmd_valid = m_axis_cmd_valid_reg;
|
||||
|
||||
assign m_axis_data_tdata = m_axis_data_tdata_reg;
|
||||
assign m_axis_data_tvalid = m_axis_data_tvalid_reg;
|
||||
assign m_axis_data_tlast = 1'b1;
|
||||
|
||||
assign busy = busy_reg;
|
||||
|
||||
always @* begin
|
||||
state_next = STATE_IDLE;
|
||||
|
||||
address_next = address_reg;
|
||||
address_ptr_next = address_ptr_reg;
|
||||
data_ptr_next = data_ptr_reg;
|
||||
|
||||
cur_address_next = cur_address_reg;
|
||||
|
||||
delay_counter_next = delay_counter_reg;
|
||||
|
||||
m_axis_cmd_address_next = m_axis_cmd_address_reg;
|
||||
m_axis_cmd_start_next = m_axis_cmd_start_reg & ~(m_axis_cmd_valid & m_axis_cmd_ready);
|
||||
m_axis_cmd_write_next = m_axis_cmd_write_reg & ~(m_axis_cmd_valid & m_axis_cmd_ready);
|
||||
m_axis_cmd_stop_next = m_axis_cmd_stop_reg & ~(m_axis_cmd_valid & m_axis_cmd_ready);
|
||||
m_axis_cmd_valid_next = m_axis_cmd_valid_reg & ~m_axis_cmd_ready;
|
||||
|
||||
m_axis_data_tdata_next = m_axis_data_tdata_reg;
|
||||
m_axis_data_tvalid_next = m_axis_data_tvalid_reg & ~m_axis_data_tready;
|
||||
|
||||
start_flag_next = start_flag_reg;
|
||||
|
||||
if (m_axis_cmd_valid | m_axis_data_tvalid) begin
|
||||
// wait for output registers to clear
|
||||
state_next = state_reg;
|
||||
end else if (delay_counter_reg != 0) begin
|
||||
// delay
|
||||
delay_counter_next = delay_counter_reg - 1;
|
||||
state_next = state_reg;
|
||||
end else begin
|
||||
case (state_reg)
|
||||
STATE_IDLE: begin
|
||||
// wait for start signal
|
||||
if (~start_flag_reg & start) begin
|
||||
address_next = {AW{1'b0}};
|
||||
start_flag_next = 1'b1;
|
||||
state_next = STATE_RUN;
|
||||
end else begin
|
||||
state_next = STATE_IDLE;
|
||||
end
|
||||
end
|
||||
STATE_RUN: begin
|
||||
// process commands
|
||||
if (init_data_reg[8] == 1'b1) begin
|
||||
// write data
|
||||
m_axis_cmd_write_next = 1'b1;
|
||||
m_axis_cmd_stop_next = 1'b0;
|
||||
m_axis_cmd_valid_next = 1'b1;
|
||||
|
||||
m_axis_data_tdata_next = init_data_reg[7:0];
|
||||
m_axis_data_tvalid_next = 1'b1;
|
||||
|
||||
address_next = address_reg + 1;
|
||||
|
||||
state_next = STATE_RUN;
|
||||
end else if (init_data_reg[8:7] == 2'b01) begin
|
||||
// write address
|
||||
m_axis_cmd_address_next = init_data_reg[6:0];
|
||||
m_axis_cmd_start_next = 1'b1;
|
||||
|
||||
address_next = address_reg + 1;
|
||||
|
||||
state_next = STATE_RUN;
|
||||
end else if (init_data_reg[8:4] == 5'b00001) begin
|
||||
// delay
|
||||
delay_counter_next = 32'd1 << (init_data_reg[3:0]+16);
|
||||
|
||||
address_next = address_reg + 1;
|
||||
|
||||
state_next = STATE_RUN;
|
||||
end else if (init_data_reg == 9'b001000001) begin
|
||||
// send stop
|
||||
m_axis_cmd_write_next = 1'b0;
|
||||
m_axis_cmd_start_next = 1'b0;
|
||||
m_axis_cmd_stop_next = 1'b1;
|
||||
m_axis_cmd_valid_next = 1'b1;
|
||||
|
||||
address_next = address_reg + 1;
|
||||
|
||||
state_next = STATE_RUN;
|
||||
end else if (init_data_reg == 9'b000001001) begin
|
||||
// data table start
|
||||
data_ptr_next = address_reg + 1;
|
||||
address_next = address_reg + 1;
|
||||
state_next = STATE_TABLE_1;
|
||||
end else if (init_data_reg == 9'd0) begin
|
||||
// stop
|
||||
m_axis_cmd_start_next = 1'b0;
|
||||
m_axis_cmd_write_next = 1'b0;
|
||||
m_axis_cmd_stop_next = 1'b1;
|
||||
m_axis_cmd_valid_next = 1'b1;
|
||||
|
||||
state_next = STATE_IDLE;
|
||||
end else begin
|
||||
// invalid command, skip
|
||||
address_next = address_reg + 1;
|
||||
state_next = STATE_RUN;
|
||||
end
|
||||
end
|
||||
STATE_TABLE_1: begin
|
||||
// find address table start
|
||||
if (init_data_reg == 9'b000001000) begin
|
||||
// address table start
|
||||
address_ptr_next = address_reg + 1;
|
||||
address_next = address_reg + 1;
|
||||
state_next = STATE_TABLE_2;
|
||||
end else if (init_data_reg == 9'b000001001) begin
|
||||
// data table start
|
||||
data_ptr_next = address_reg + 1;
|
||||
address_next = address_reg + 1;
|
||||
state_next = STATE_TABLE_1;
|
||||
end else if (init_data_reg == 1) begin
|
||||
// exit mode
|
||||
address_next = address_reg + 1;
|
||||
state_next = STATE_RUN;
|
||||
end else if (init_data_reg == 9'd0) begin
|
||||
// stop
|
||||
m_axis_cmd_start_next = 1'b0;
|
||||
m_axis_cmd_write_next = 1'b0;
|
||||
m_axis_cmd_stop_next = 1'b1;
|
||||
m_axis_cmd_valid_next = 1'b1;
|
||||
|
||||
state_next = STATE_IDLE;
|
||||
end else begin
|
||||
// invalid command, skip
|
||||
address_next = address_reg + 1;
|
||||
state_next = STATE_TABLE_1;
|
||||
end
|
||||
end
|
||||
STATE_TABLE_2: begin
|
||||
// find next address
|
||||
if (init_data_reg[8:7] == 2'b01) begin
|
||||
// write address command
|
||||
// store address and move to data table
|
||||
cur_address_next = init_data_reg[6:0];
|
||||
address_ptr_next = address_reg + 1;
|
||||
address_next = data_ptr_reg;
|
||||
state_next = STATE_TABLE_3;
|
||||
end else if (init_data_reg == 9'b000001001) begin
|
||||
// data table start
|
||||
data_ptr_next = address_reg + 1;
|
||||
address_next = address_reg + 1;
|
||||
state_next = STATE_TABLE_1;
|
||||
end else if (init_data_reg == 9'd1) begin
|
||||
// exit mode
|
||||
address_next = address_reg + 1;
|
||||
state_next = STATE_RUN;
|
||||
end else if (init_data_reg == 9'd0) begin
|
||||
// stop
|
||||
m_axis_cmd_start_next = 1'b0;
|
||||
m_axis_cmd_write_next = 1'b0;
|
||||
m_axis_cmd_stop_next = 1'b1;
|
||||
m_axis_cmd_valid_next = 1'b1;
|
||||
|
||||
state_next = STATE_IDLE;
|
||||
end else begin
|
||||
// invalid command, skip
|
||||
address_next = address_reg + 1;
|
||||
state_next = STATE_TABLE_2;
|
||||
end
|
||||
end
|
||||
STATE_TABLE_3: begin
|
||||
// process data table with selected address
|
||||
if (init_data_reg[8] == 1'b1) begin
|
||||
// write data
|
||||
m_axis_cmd_write_next = 1'b1;
|
||||
m_axis_cmd_stop_next = 1'b0;
|
||||
m_axis_cmd_valid_next = 1'b1;
|
||||
|
||||
m_axis_data_tdata_next = init_data_reg[7:0];
|
||||
m_axis_data_tvalid_next = 1'b1;
|
||||
|
||||
address_next = address_reg + 1;
|
||||
|
||||
state_next = STATE_TABLE_3;
|
||||
end else if (init_data_reg[8:7] == 2'b01) begin
|
||||
// write address
|
||||
m_axis_cmd_address_next = init_data_reg[6:0];
|
||||
m_axis_cmd_start_next = 1'b1;
|
||||
|
||||
address_next = address_reg + 1;
|
||||
|
||||
state_next = STATE_TABLE_3;
|
||||
end else if (init_data_reg == 9'b000000011) begin
|
||||
// write current address
|
||||
m_axis_cmd_address_next = cur_address_reg;
|
||||
m_axis_cmd_start_next = 1'b1;
|
||||
|
||||
address_next = address_reg + 1;
|
||||
|
||||
state_next = STATE_TABLE_3;
|
||||
end else if (init_data_reg == 9'b001000001) begin
|
||||
// send stop
|
||||
m_axis_cmd_write_next = 1'b0;
|
||||
m_axis_cmd_start_next = 1'b0;
|
||||
m_axis_cmd_stop_next = 1'b1;
|
||||
m_axis_cmd_valid_next = 1'b1;
|
||||
|
||||
address_next = address_reg + 1;
|
||||
|
||||
state_next = STATE_TABLE_3;
|
||||
end else if (init_data_reg == 9'b000001001) begin
|
||||
// data table start
|
||||
data_ptr_next = address_reg + 1;
|
||||
address_next = address_reg + 1;
|
||||
state_next = STATE_TABLE_1;
|
||||
end else if (init_data_reg == 9'b000001000) begin
|
||||
// address table start
|
||||
address_next = address_ptr_reg;
|
||||
state_next = STATE_TABLE_2;
|
||||
end else if (init_data_reg == 9'd1) begin
|
||||
// exit mode
|
||||
address_next = address_reg + 1;
|
||||
state_next = STATE_RUN;
|
||||
end else if (init_data_reg == 9'd0) begin
|
||||
// stop
|
||||
m_axis_cmd_start_next = 1'b0;
|
||||
m_axis_cmd_write_next = 1'b0;
|
||||
m_axis_cmd_stop_next = 1'b1;
|
||||
m_axis_cmd_valid_next = 1'b1;
|
||||
|
||||
state_next = STATE_IDLE;
|
||||
end else begin
|
||||
// invalid command, skip
|
||||
address_next = address_reg + 1;
|
||||
state_next = STATE_TABLE_3;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
state_reg <= state_next;
|
||||
|
||||
// read init_data ROM
|
||||
init_data_reg <= init_data[address_next];
|
||||
|
||||
address_reg <= address_next;
|
||||
address_ptr_reg <= address_ptr_next;
|
||||
data_ptr_reg <= data_ptr_next;
|
||||
|
||||
cur_address_reg <= cur_address_next;
|
||||
|
||||
delay_counter_reg <= delay_counter_next;
|
||||
|
||||
m_axis_cmd_address_reg <= m_axis_cmd_address_next;
|
||||
m_axis_cmd_start_reg <= m_axis_cmd_start_next;
|
||||
m_axis_cmd_write_reg <= m_axis_cmd_write_next;
|
||||
m_axis_cmd_stop_reg <= m_axis_cmd_stop_next;
|
||||
m_axis_cmd_valid_reg <= m_axis_cmd_valid_next;
|
||||
|
||||
m_axis_data_tdata_reg <= m_axis_data_tdata_next;
|
||||
m_axis_data_tvalid_reg <= m_axis_data_tvalid_next;
|
||||
|
||||
start_flag_reg <= start & start_flag_next;
|
||||
|
||||
busy_reg <= (state_reg != STATE_IDLE);
|
||||
|
||||
if (rst) begin
|
||||
state_reg <= STATE_IDLE;
|
||||
|
||||
init_data_reg <= 9'd0;
|
||||
|
||||
address_reg <= {AW{1'b0}};
|
||||
address_ptr_reg <= {AW{1'b0}};
|
||||
data_ptr_reg <= {AW{1'b0}};
|
||||
|
||||
cur_address_reg <= 7'd0;
|
||||
|
||||
delay_counter_reg <= 32'd0;
|
||||
|
||||
m_axis_cmd_valid_reg <= 1'b0;
|
||||
|
||||
m_axis_data_tvalid_reg <= 1'b0;
|
||||
|
||||
start_flag_reg <= 1'b0;
|
||||
|
||||
busy_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
|
||||
""")
|
||||
|
||||
print(f"Writing file '{output}'...")
|
||||
|
||||
with open(output, 'w') as f:
|
||||
f.write(t.render(
|
||||
cmd_str=cmd_str,
|
||||
cmd_count=cmd_count,
|
||||
name=name
|
||||
))
|
||||
f.flush()
|
||||
|
||||
print("Done")
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
1041
example/VCU118/fpga_fmc_htg_6qsfp_25g/pll/si5341_i2c_init.v
Normal file
1041
example/VCU118/fpga_fmc_htg_6qsfp_25g/pll/si5341_i2c_init.v
Normal file
File diff suppressed because it is too large
Load Diff
93
example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/debounce_switch.v
Normal file
93
example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/debounce_switch.v
Normal file
@ -0,0 +1,93 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog-2001
|
||||
|
||||
`resetall
|
||||
`timescale 1 ns / 1 ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* Synchronizes switch and button inputs with a slow sampled shift register
|
||||
*/
|
||||
module debounce_switch #(
|
||||
parameter WIDTH=1, // width of the input and output signals
|
||||
parameter N=3, // length of shift register
|
||||
parameter RATE=125000 // clock division factor
|
||||
)(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
input wire [WIDTH-1:0] in,
|
||||
output wire [WIDTH-1:0] out
|
||||
);
|
||||
|
||||
reg [23:0] cnt_reg = 24'd0;
|
||||
|
||||
reg [N-1:0] debounce_reg[WIDTH-1:0];
|
||||
|
||||
reg [WIDTH-1:0] state;
|
||||
|
||||
/*
|
||||
* The synchronized output is the state register
|
||||
*/
|
||||
assign out = state;
|
||||
|
||||
integer k;
|
||||
|
||||
always @(posedge clk or posedge rst) begin
|
||||
if (rst) begin
|
||||
cnt_reg <= 0;
|
||||
state <= 0;
|
||||
|
||||
for (k = 0; k < WIDTH; k = k + 1) begin
|
||||
debounce_reg[k] <= 0;
|
||||
end
|
||||
end else begin
|
||||
if (cnt_reg < RATE) begin
|
||||
cnt_reg <= cnt_reg + 24'd1;
|
||||
end else begin
|
||||
cnt_reg <= 24'd0;
|
||||
end
|
||||
|
||||
if (cnt_reg == 24'd0) begin
|
||||
for (k = 0; k < WIDTH; k = k + 1) begin
|
||||
debounce_reg[k] <= {debounce_reg[k][N-2:0], in[k]};
|
||||
end
|
||||
end
|
||||
|
||||
for (k = 0; k < WIDTH; k = k + 1) begin
|
||||
if (|debounce_reg[k] == 0) begin
|
||||
state[k] <= 0;
|
||||
end else if (&debounce_reg[k] == 1) begin
|
||||
state[k] <= 1;
|
||||
end else begin
|
||||
state[k] <= state[k];
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
299
example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_wrapper.v
Normal file
299
example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/eth_xcvr_phy_wrapper.v
Normal file
@ -0,0 +1,299 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2021 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* Transceiver and PHY wrapper
|
||||
*/
|
||||
module eth_xcvr_phy_wrapper #
|
||||
(
|
||||
parameter HAS_COMMON = 1,
|
||||
parameter DATA_WIDTH = 64,
|
||||
parameter CTRL_WIDTH = (DATA_WIDTH/8),
|
||||
parameter HDR_WIDTH = 2,
|
||||
parameter PRBS31_ENABLE = 0,
|
||||
parameter TX_SERDES_PIPELINE = 0,
|
||||
parameter RX_SERDES_PIPELINE = 0,
|
||||
parameter BITSLIP_HIGH_CYCLES = 1,
|
||||
parameter BITSLIP_LOW_CYCLES = 8,
|
||||
parameter COUNT_125US = 125000/6.4
|
||||
)
|
||||
(
|
||||
input wire xcvr_ctrl_clk,
|
||||
input wire xcvr_ctrl_rst,
|
||||
|
||||
/*
|
||||
* Common
|
||||
*/
|
||||
output wire xcvr_gtpowergood_out,
|
||||
|
||||
/*
|
||||
* PLL out
|
||||
*/
|
||||
input wire xcvr_gtrefclk00_in,
|
||||
output wire xcvr_qpll0lock_out,
|
||||
output wire xcvr_qpll0outclk_out,
|
||||
output wire xcvr_qpll0outrefclk_out,
|
||||
|
||||
/*
|
||||
* PLL in
|
||||
*/
|
||||
input wire xcvr_qpll0lock_in,
|
||||
output wire xcvr_qpll0reset_out,
|
||||
input wire xcvr_qpll0clk_in,
|
||||
input wire xcvr_qpll0refclk_in,
|
||||
|
||||
/*
|
||||
* Serial data
|
||||
*/
|
||||
output wire xcvr_txp,
|
||||
output wire xcvr_txn,
|
||||
input wire xcvr_rxp,
|
||||
input wire xcvr_rxn,
|
||||
|
||||
/*
|
||||
* PHY connections
|
||||
*/
|
||||
output wire phy_tx_clk,
|
||||
output wire phy_tx_rst,
|
||||
input wire [DATA_WIDTH-1:0] phy_xgmii_txd,
|
||||
input wire [CTRL_WIDTH-1:0] phy_xgmii_txc,
|
||||
output wire phy_rx_clk,
|
||||
output wire phy_rx_rst,
|
||||
output wire [DATA_WIDTH-1:0] phy_xgmii_rxd,
|
||||
output wire [CTRL_WIDTH-1:0] phy_xgmii_rxc,
|
||||
output wire phy_tx_bad_block,
|
||||
output wire [6:0] phy_rx_error_count,
|
||||
output wire phy_rx_bad_block,
|
||||
output wire phy_rx_sequence_error,
|
||||
output wire phy_rx_block_lock,
|
||||
output wire phy_rx_high_ber,
|
||||
input wire phy_tx_prbs31_enable,
|
||||
input wire phy_rx_prbs31_enable
|
||||
);
|
||||
|
||||
wire phy_rx_reset_req;
|
||||
|
||||
wire gt_reset_tx_datapath = 1'b0;
|
||||
wire gt_reset_rx_datapath = phy_rx_reset_req;
|
||||
|
||||
wire gt_reset_tx_done;
|
||||
wire gt_reset_rx_done;
|
||||
|
||||
wire [5:0] gt_txheader;
|
||||
wire [63:0] gt_txdata;
|
||||
wire gt_rxgearboxslip;
|
||||
wire [5:0] gt_rxheader;
|
||||
wire [1:0] gt_rxheadervalid;
|
||||
wire [63:0] gt_rxdata;
|
||||
wire [1:0] gt_rxdatavalid;
|
||||
|
||||
generate
|
||||
|
||||
if (HAS_COMMON) begin : xcvr
|
||||
|
||||
eth_xcvr_gt_full
|
||||
eth_xcvr_gt_full_inst (
|
||||
// Common
|
||||
.gtwiz_reset_clk_freerun_in(xcvr_ctrl_clk),
|
||||
.gtwiz_reset_all_in(xcvr_ctrl_rst),
|
||||
.gtpowergood_out(xcvr_gtpowergood_out),
|
||||
|
||||
// PLL
|
||||
.gtrefclk00_in(xcvr_gtrefclk00_in),
|
||||
.qpll0lock_out(xcvr_qpll0lock_out),
|
||||
.qpll0outclk_out(xcvr_qpll0outclk_out),
|
||||
.qpll0outrefclk_out(xcvr_qpll0outrefclk_out),
|
||||
|
||||
// Serial data
|
||||
.gtytxp_out(xcvr_txp),
|
||||
.gtytxn_out(xcvr_txn),
|
||||
.gtyrxp_in(xcvr_rxp),
|
||||
.gtyrxn_in(xcvr_rxn),
|
||||
|
||||
// Transmit
|
||||
.gtwiz_userclk_tx_reset_in(1'b0),
|
||||
.gtwiz_userclk_tx_srcclk_out(),
|
||||
.gtwiz_userclk_tx_usrclk_out(),
|
||||
.gtwiz_userclk_tx_usrclk2_out(phy_tx_clk),
|
||||
.gtwiz_userclk_tx_active_out(),
|
||||
.gtwiz_reset_tx_pll_and_datapath_in(1'b0),
|
||||
.gtwiz_reset_tx_datapath_in(gt_reset_tx_datapath),
|
||||
.gtwiz_reset_tx_done_out(gt_reset_tx_done),
|
||||
.txpmaresetdone_out(),
|
||||
.txprgdivresetdone_out(),
|
||||
|
||||
.gtwiz_userdata_tx_in(gt_txdata),
|
||||
.txheader_in(gt_txheader),
|
||||
.txsequence_in(7'b0),
|
||||
|
||||
// Receive
|
||||
.gtwiz_userclk_rx_reset_in(1'b0),
|
||||
.gtwiz_userclk_rx_srcclk_out(),
|
||||
.gtwiz_userclk_rx_usrclk_out(),
|
||||
.gtwiz_userclk_rx_usrclk2_out(phy_rx_clk),
|
||||
.gtwiz_userclk_rx_active_out(),
|
||||
.gtwiz_reset_rx_pll_and_datapath_in(1'b0),
|
||||
.gtwiz_reset_rx_datapath_in(gt_reset_rx_datapath),
|
||||
.gtwiz_reset_rx_cdr_stable_out(),
|
||||
.gtwiz_reset_rx_done_out(gt_reset_rx_done),
|
||||
.rxpmaresetdone_out(),
|
||||
.rxprgdivresetdone_out(),
|
||||
|
||||
.rxgearboxslip_in(gt_rxgearboxslip),
|
||||
.gtwiz_userdata_rx_out(gt_rxdata),
|
||||
.rxdatavalid_out(gt_rxdatavalid),
|
||||
.rxheader_out(gt_rxheader),
|
||||
.rxheadervalid_out(gt_rxheadervalid),
|
||||
.rxstartofseq_out()
|
||||
);
|
||||
|
||||
end else begin : xcvr
|
||||
|
||||
eth_xcvr_gt_channel
|
||||
eth_xcvr_gt_channel_inst (
|
||||
// Common
|
||||
.gtwiz_reset_clk_freerun_in(xcvr_ctrl_clk),
|
||||
.gtwiz_reset_all_in(xcvr_ctrl_rst),
|
||||
.gtpowergood_out(xcvr_gtpowergood_out),
|
||||
|
||||
// PLL
|
||||
.gtwiz_reset_qpll0lock_in(xcvr_qpll0lock_in),
|
||||
.gtwiz_reset_qpll0reset_out(xcvr_qpll0reset_out),
|
||||
.qpll0clk_in(xcvr_qpll0clk_in),
|
||||
.qpll0refclk_in(xcvr_qpll0refclk_in),
|
||||
.qpll1clk_in(1'b0),
|
||||
.qpll1refclk_in(1'b0),
|
||||
|
||||
// Serial data
|
||||
.gtytxp_out(xcvr_txp),
|
||||
.gtytxn_out(xcvr_txn),
|
||||
.gtyrxp_in(xcvr_rxp),
|
||||
.gtyrxn_in(xcvr_rxn),
|
||||
|
||||
// Transmit
|
||||
.gtwiz_userclk_tx_reset_in(1'b0),
|
||||
.gtwiz_userclk_tx_srcclk_out(),
|
||||
.gtwiz_userclk_tx_usrclk_out(),
|
||||
.gtwiz_userclk_tx_usrclk2_out(phy_tx_clk),
|
||||
.gtwiz_userclk_tx_active_out(),
|
||||
.gtwiz_reset_tx_pll_and_datapath_in(1'b0),
|
||||
.gtwiz_reset_tx_datapath_in(gt_reset_tx_datapath),
|
||||
.gtwiz_reset_tx_done_out(gt_reset_tx_done),
|
||||
.txpmaresetdone_out(),
|
||||
.txprgdivresetdone_out(),
|
||||
|
||||
.gtwiz_userdata_tx_in(gt_txdata),
|
||||
.txheader_in(gt_txheader),
|
||||
.txsequence_in(7'b0),
|
||||
|
||||
// Receive
|
||||
.gtwiz_userclk_rx_reset_in(1'b0),
|
||||
.gtwiz_userclk_rx_srcclk_out(),
|
||||
.gtwiz_userclk_rx_usrclk_out(),
|
||||
.gtwiz_userclk_rx_usrclk2_out(phy_rx_clk),
|
||||
.gtwiz_userclk_rx_active_out(),
|
||||
.gtwiz_reset_rx_pll_and_datapath_in(1'b0),
|
||||
.gtwiz_reset_rx_datapath_in(gt_reset_rx_datapath),
|
||||
.gtwiz_reset_rx_cdr_stable_out(),
|
||||
.gtwiz_reset_rx_done_out(gt_reset_rx_done),
|
||||
.rxpmaresetdone_out(),
|
||||
.rxprgdivresetdone_out(),
|
||||
|
||||
.rxgearboxslip_in(gt_rxgearboxslip),
|
||||
.gtwiz_userdata_rx_out(gt_rxdata),
|
||||
.rxdatavalid_out(gt_rxdatavalid),
|
||||
.rxheader_out(gt_rxheader),
|
||||
.rxheadervalid_out(gt_rxheadervalid),
|
||||
.rxstartofseq_out()
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
tx_reset_sync_inst (
|
||||
.clk(phy_tx_clk),
|
||||
.rst(!gt_reset_tx_done),
|
||||
.out(phy_tx_rst)
|
||||
);
|
||||
|
||||
sync_reset #(
|
||||
.N(4)
|
||||
)
|
||||
rx_reset_sync_inst (
|
||||
.clk(phy_rx_clk),
|
||||
.rst(!gt_reset_rx_done),
|
||||
.out(phy_rx_rst)
|
||||
);
|
||||
|
||||
eth_phy_10g #(
|
||||
.DATA_WIDTH(DATA_WIDTH),
|
||||
.CTRL_WIDTH(CTRL_WIDTH),
|
||||
.HDR_WIDTH(HDR_WIDTH),
|
||||
.BIT_REVERSE(1),
|
||||
.SCRAMBLER_DISABLE(0),
|
||||
.PRBS31_ENABLE(PRBS31_ENABLE),
|
||||
.TX_SERDES_PIPELINE(TX_SERDES_PIPELINE),
|
||||
.RX_SERDES_PIPELINE(RX_SERDES_PIPELINE),
|
||||
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
|
||||
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
|
||||
.COUNT_125US(COUNT_125US)
|
||||
)
|
||||
phy_inst (
|
||||
.tx_clk(phy_tx_clk),
|
||||
.tx_rst(phy_tx_rst),
|
||||
.rx_clk(phy_rx_clk),
|
||||
.rx_rst(phy_rx_rst),
|
||||
.xgmii_txd(phy_xgmii_txd),
|
||||
.xgmii_txc(phy_xgmii_txc),
|
||||
.xgmii_rxd(phy_xgmii_rxd),
|
||||
.xgmii_rxc(phy_xgmii_rxc),
|
||||
.serdes_tx_data(gt_txdata),
|
||||
.serdes_tx_hdr(gt_txheader),
|
||||
.serdes_rx_data(gt_rxdata),
|
||||
.serdes_rx_hdr(gt_rxheader),
|
||||
.serdes_rx_bitslip(gt_rxgearboxslip),
|
||||
.serdes_rx_reset_req(phy_rx_reset_req),
|
||||
.tx_bad_block(phy_tx_bad_block),
|
||||
.rx_error_count(phy_rx_error_count),
|
||||
.rx_bad_block(phy_rx_bad_block),
|
||||
.rx_sequence_error(phy_rx_sequence_error),
|
||||
.rx_block_lock(phy_rx_block_lock),
|
||||
.rx_high_ber(phy_rx_high_ber),
|
||||
.tx_prbs31_enable(phy_tx_prbs31_enable),
|
||||
.rx_prbs31_enable(phy_rx_prbs31_enable)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
3083
example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v
Normal file
3083
example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga.v
Normal file
File diff suppressed because it is too large
Load Diff
1166
example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v
Normal file
1166
example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/fpga_core.v
Normal file
File diff suppressed because it is too large
Load Diff
901
example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/i2c_master.v
Normal file
901
example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/i2c_master.v
Normal file
@ -0,0 +1,901 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2015-2017 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* I2C master
|
||||
*/
|
||||
module i2c_master (
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
/*
|
||||
* Host interface
|
||||
*/
|
||||
input wire [6:0] s_axis_cmd_address,
|
||||
input wire s_axis_cmd_start,
|
||||
input wire s_axis_cmd_read,
|
||||
input wire s_axis_cmd_write,
|
||||
input wire s_axis_cmd_write_multiple,
|
||||
input wire s_axis_cmd_stop,
|
||||
input wire s_axis_cmd_valid,
|
||||
output wire s_axis_cmd_ready,
|
||||
|
||||
input wire [7:0] s_axis_data_tdata,
|
||||
input wire s_axis_data_tvalid,
|
||||
output wire s_axis_data_tready,
|
||||
input wire s_axis_data_tlast,
|
||||
|
||||
output wire [7:0] m_axis_data_tdata,
|
||||
output wire m_axis_data_tvalid,
|
||||
input wire m_axis_data_tready,
|
||||
output wire m_axis_data_tlast,
|
||||
|
||||
/*
|
||||
* I2C interface
|
||||
*/
|
||||
input wire scl_i,
|
||||
output wire scl_o,
|
||||
output wire scl_t,
|
||||
input wire sda_i,
|
||||
output wire sda_o,
|
||||
output wire sda_t,
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
output wire busy,
|
||||
output wire bus_control,
|
||||
output wire bus_active,
|
||||
output wire missed_ack,
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
input wire [15:0] prescale,
|
||||
input wire stop_on_idle
|
||||
);
|
||||
|
||||
/*
|
||||
|
||||
I2C
|
||||
|
||||
Read
|
||||
__ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ __
|
||||
sda \__/_6_X_5_X_4_X_3_X_2_X_1_X_0_\_R___A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\_A____/
|
||||
____ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____
|
||||
scl ST \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ SP
|
||||
|
||||
Write
|
||||
__ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ __
|
||||
sda \__/_6_X_5_X_4_X_3_X_2_X_1_X_0_/ W \_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_\_A_/_7_X_6_X_5_X_4_X_3_X_2_X_1_X_0_/ N \__/
|
||||
____ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____
|
||||
scl ST \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ SP
|
||||
|
||||
Commands:
|
||||
|
||||
read
|
||||
read data byte
|
||||
set start to force generation of a start condition
|
||||
start is implied when bus is inactive or active with write or different address
|
||||
set stop to issue a stop condition after reading current byte
|
||||
if stop is set with read command, then m_axis_data_tlast will be set
|
||||
|
||||
write
|
||||
write data byte
|
||||
set start to force generation of a start condition
|
||||
start is implied when bus is inactive or active with read or different address
|
||||
set stop to issue a stop condition after writing current byte
|
||||
|
||||
write multiple
|
||||
write multiple data bytes (until s_axis_data_tlast)
|
||||
set start to force generation of a start condition
|
||||
start is implied when bus is inactive or active with read or different address
|
||||
set stop to issue a stop condition after writing block
|
||||
|
||||
stop
|
||||
issue stop condition if bus is active
|
||||
|
||||
Status:
|
||||
|
||||
busy
|
||||
module is communicating over the bus
|
||||
|
||||
bus_control
|
||||
module has control of bus in active state
|
||||
|
||||
bus_active
|
||||
bus is active, not necessarily controlled by this module
|
||||
|
||||
missed_ack
|
||||
strobed when a slave ack is missed
|
||||
|
||||
Parameters:
|
||||
|
||||
prescale
|
||||
set prescale to 1/4 of the minimum clock period in units
|
||||
of input clk cycles (prescale = Fclk / (FI2Cclk * 4))
|
||||
|
||||
stop_on_idle
|
||||
automatically issue stop when command input is not valid
|
||||
|
||||
Example of interfacing with tristate pins:
|
||||
(this will work for any tristate bus)
|
||||
|
||||
assign scl_i = scl_pin;
|
||||
assign scl_pin = scl_t ? 1'bz : scl_o;
|
||||
assign sda_i = sda_pin;
|
||||
assign sda_pin = sda_t ? 1'bz : sda_o;
|
||||
|
||||
Equivalent code that does not use *_t connections:
|
||||
(we can get away with this because I2C is open-drain)
|
||||
|
||||
assign scl_i = scl_pin;
|
||||
assign scl_pin = scl_o ? 1'bz : 1'b0;
|
||||
assign sda_i = sda_pin;
|
||||
assign sda_pin = sda_o ? 1'bz : 1'b0;
|
||||
|
||||
Example of two interconnected I2C devices:
|
||||
|
||||
assign scl_1_i = scl_1_o & scl_2_o;
|
||||
assign scl_2_i = scl_1_o & scl_2_o;
|
||||
assign sda_1_i = sda_1_o & sda_2_o;
|
||||
assign sda_2_i = sda_1_o & sda_2_o;
|
||||
|
||||
Example of two I2C devices sharing the same pins:
|
||||
|
||||
assign scl_1_i = scl_pin;
|
||||
assign scl_2_i = scl_pin;
|
||||
assign scl_pin = (scl_1_o & scl_2_o) ? 1'bz : 1'b0;
|
||||
assign sda_1_i = sda_pin;
|
||||
assign sda_2_i = sda_pin;
|
||||
assign sda_pin = (sda_1_o & sda_2_o) ? 1'bz : 1'b0;
|
||||
|
||||
Notes:
|
||||
|
||||
scl_o should not be connected directly to scl_i, only via AND logic or a tristate
|
||||
I/O pin. This would prevent devices from stretching the clock period.
|
||||
|
||||
*/
|
||||
|
||||
localparam [4:0]
|
||||
STATE_IDLE = 4'd0,
|
||||
STATE_ACTIVE_WRITE = 4'd1,
|
||||
STATE_ACTIVE_READ = 4'd2,
|
||||
STATE_START_WAIT = 4'd3,
|
||||
STATE_START = 4'd4,
|
||||
STATE_ADDRESS_1 = 4'd5,
|
||||
STATE_ADDRESS_2 = 4'd6,
|
||||
STATE_WRITE_1 = 4'd7,
|
||||
STATE_WRITE_2 = 4'd8,
|
||||
STATE_WRITE_3 = 4'd9,
|
||||
STATE_READ = 4'd10,
|
||||
STATE_STOP = 4'd11;
|
||||
|
||||
reg [4:0] state_reg = STATE_IDLE, state_next;
|
||||
|
||||
localparam [4:0]
|
||||
PHY_STATE_IDLE = 5'd0,
|
||||
PHY_STATE_ACTIVE = 5'd1,
|
||||
PHY_STATE_REPEATED_START_1 = 5'd2,
|
||||
PHY_STATE_REPEATED_START_2 = 5'd3,
|
||||
PHY_STATE_START_1 = 5'd4,
|
||||
PHY_STATE_START_2 = 5'd5,
|
||||
PHY_STATE_WRITE_BIT_1 = 5'd6,
|
||||
PHY_STATE_WRITE_BIT_2 = 5'd7,
|
||||
PHY_STATE_WRITE_BIT_3 = 5'd8,
|
||||
PHY_STATE_READ_BIT_1 = 5'd9,
|
||||
PHY_STATE_READ_BIT_2 = 5'd10,
|
||||
PHY_STATE_READ_BIT_3 = 5'd11,
|
||||
PHY_STATE_READ_BIT_4 = 5'd12,
|
||||
PHY_STATE_STOP_1 = 5'd13,
|
||||
PHY_STATE_STOP_2 = 5'd14,
|
||||
PHY_STATE_STOP_3 = 5'd15;
|
||||
|
||||
reg [4:0] phy_state_reg = STATE_IDLE, phy_state_next;
|
||||
|
||||
reg phy_start_bit;
|
||||
reg phy_stop_bit;
|
||||
reg phy_write_bit;
|
||||
reg phy_read_bit;
|
||||
reg phy_release_bus;
|
||||
|
||||
reg phy_tx_data;
|
||||
|
||||
reg phy_rx_data_reg = 1'b0, phy_rx_data_next;
|
||||
|
||||
reg [6:0] addr_reg = 7'd0, addr_next;
|
||||
reg [7:0] data_reg = 8'd0, data_next;
|
||||
reg last_reg = 1'b0, last_next;
|
||||
|
||||
reg mode_read_reg = 1'b0, mode_read_next;
|
||||
reg mode_write_multiple_reg = 1'b0, mode_write_multiple_next;
|
||||
reg mode_stop_reg = 1'b0, mode_stop_next;
|
||||
|
||||
reg [16:0] delay_reg = 16'd0, delay_next;
|
||||
reg delay_scl_reg = 1'b0, delay_scl_next;
|
||||
reg delay_sda_reg = 1'b0, delay_sda_next;
|
||||
|
||||
reg [3:0] bit_count_reg = 4'd0, bit_count_next;
|
||||
|
||||
reg s_axis_cmd_ready_reg = 1'b0, s_axis_cmd_ready_next;
|
||||
|
||||
reg s_axis_data_tready_reg = 1'b0, s_axis_data_tready_next;
|
||||
|
||||
reg [7:0] m_axis_data_tdata_reg = 8'd0, m_axis_data_tdata_next;
|
||||
reg m_axis_data_tvalid_reg = 1'b0, m_axis_data_tvalid_next;
|
||||
reg m_axis_data_tlast_reg = 1'b0, m_axis_data_tlast_next;
|
||||
|
||||
reg scl_i_reg = 1'b1;
|
||||
reg sda_i_reg = 1'b1;
|
||||
|
||||
reg scl_o_reg = 1'b1, scl_o_next;
|
||||
reg sda_o_reg = 1'b1, sda_o_next;
|
||||
|
||||
reg last_scl_i_reg = 1'b1;
|
||||
reg last_sda_i_reg = 1'b1;
|
||||
|
||||
reg busy_reg = 1'b0;
|
||||
reg bus_active_reg = 1'b0;
|
||||
reg bus_control_reg = 1'b0, bus_control_next;
|
||||
reg missed_ack_reg = 1'b0, missed_ack_next;
|
||||
|
||||
assign s_axis_cmd_ready = s_axis_cmd_ready_reg;
|
||||
|
||||
assign s_axis_data_tready = s_axis_data_tready_reg;
|
||||
|
||||
assign m_axis_data_tdata = m_axis_data_tdata_reg;
|
||||
assign m_axis_data_tvalid = m_axis_data_tvalid_reg;
|
||||
assign m_axis_data_tlast = m_axis_data_tlast_reg;
|
||||
|
||||
assign scl_o = scl_o_reg;
|
||||
assign scl_t = scl_o_reg;
|
||||
assign sda_o = sda_o_reg;
|
||||
assign sda_t = sda_o_reg;
|
||||
|
||||
assign busy = busy_reg;
|
||||
assign bus_active = bus_active_reg;
|
||||
assign bus_control = bus_control_reg;
|
||||
assign missed_ack = missed_ack_reg;
|
||||
|
||||
wire scl_posedge = scl_i_reg & ~last_scl_i_reg;
|
||||
wire scl_negedge = ~scl_i_reg & last_scl_i_reg;
|
||||
wire sda_posedge = sda_i_reg & ~last_sda_i_reg;
|
||||
wire sda_negedge = ~sda_i_reg & last_sda_i_reg;
|
||||
|
||||
wire start_bit = sda_negedge & scl_i_reg;
|
||||
wire stop_bit = sda_posedge & scl_i_reg;
|
||||
|
||||
always @* begin
|
||||
state_next = STATE_IDLE;
|
||||
|
||||
phy_start_bit = 1'b0;
|
||||
phy_stop_bit = 1'b0;
|
||||
phy_write_bit = 1'b0;
|
||||
phy_read_bit = 1'b0;
|
||||
phy_tx_data = 1'b0;
|
||||
phy_release_bus = 1'b0;
|
||||
|
||||
addr_next = addr_reg;
|
||||
data_next = data_reg;
|
||||
last_next = last_reg;
|
||||
|
||||
mode_read_next = mode_read_reg;
|
||||
mode_write_multiple_next = mode_write_multiple_reg;
|
||||
mode_stop_next = mode_stop_reg;
|
||||
|
||||
bit_count_next = bit_count_reg;
|
||||
|
||||
s_axis_cmd_ready_next = 1'b0;
|
||||
|
||||
s_axis_data_tready_next = 1'b0;
|
||||
|
||||
m_axis_data_tdata_next = m_axis_data_tdata_reg;
|
||||
m_axis_data_tvalid_next = m_axis_data_tvalid_reg & ~m_axis_data_tready;
|
||||
m_axis_data_tlast_next = m_axis_data_tlast_reg;
|
||||
|
||||
missed_ack_next = 1'b0;
|
||||
|
||||
// generate delays
|
||||
if (phy_state_reg != PHY_STATE_IDLE && phy_state_reg != PHY_STATE_ACTIVE) begin
|
||||
// wait for phy operation
|
||||
state_next = state_reg;
|
||||
end else begin
|
||||
// process states
|
||||
case (state_reg)
|
||||
STATE_IDLE: begin
|
||||
// line idle
|
||||
s_axis_cmd_ready_next = 1'b1;
|
||||
|
||||
if (s_axis_cmd_ready & s_axis_cmd_valid) begin
|
||||
// command valid
|
||||
if (s_axis_cmd_read ^ (s_axis_cmd_write | s_axis_cmd_write_multiple)) begin
|
||||
// read or write command
|
||||
addr_next = s_axis_cmd_address;
|
||||
mode_read_next = s_axis_cmd_read;
|
||||
mode_write_multiple_next = s_axis_cmd_write_multiple;
|
||||
mode_stop_next = s_axis_cmd_stop;
|
||||
|
||||
s_axis_cmd_ready_next = 1'b0;
|
||||
|
||||
// start bit
|
||||
if (bus_active) begin
|
||||
state_next = STATE_START_WAIT;
|
||||
end else begin
|
||||
phy_start_bit = 1'b1;
|
||||
bit_count_next = 4'd8;
|
||||
state_next = STATE_ADDRESS_1;
|
||||
end
|
||||
end else begin
|
||||
// invalid or unspecified - ignore
|
||||
state_next = STATE_IDLE;
|
||||
end
|
||||
end else begin
|
||||
state_next = STATE_IDLE;
|
||||
end
|
||||
end
|
||||
STATE_ACTIVE_WRITE: begin
|
||||
// line active with current address and read/write mode
|
||||
s_axis_cmd_ready_next = 1'b1;
|
||||
|
||||
if (s_axis_cmd_ready & s_axis_cmd_valid) begin
|
||||
// command valid
|
||||
if (s_axis_cmd_read ^ (s_axis_cmd_write | s_axis_cmd_write_multiple)) begin
|
||||
// read or write command
|
||||
addr_next = s_axis_cmd_address;
|
||||
mode_read_next = s_axis_cmd_read;
|
||||
mode_write_multiple_next = s_axis_cmd_write_multiple;
|
||||
mode_stop_next = s_axis_cmd_stop;
|
||||
|
||||
s_axis_cmd_ready_next = 1'b0;
|
||||
|
||||
if (s_axis_cmd_start || s_axis_cmd_address != addr_reg || s_axis_cmd_read) begin
|
||||
// address or mode mismatch or forced start - repeated start
|
||||
|
||||
// repeated start bit
|
||||
phy_start_bit = 1'b1;
|
||||
bit_count_next = 4'd8;
|
||||
state_next = STATE_ADDRESS_1;
|
||||
end else begin
|
||||
// address and mode match
|
||||
|
||||
// start write
|
||||
s_axis_data_tready_next = 1'b1;
|
||||
state_next = STATE_WRITE_1;
|
||||
end
|
||||
end else if (s_axis_cmd_stop && !(s_axis_cmd_read || s_axis_cmd_write || s_axis_cmd_write_multiple)) begin
|
||||
// stop command
|
||||
phy_stop_bit = 1'b1;
|
||||
state_next = STATE_IDLE;
|
||||
end else begin
|
||||
// invalid or unspecified - ignore
|
||||
state_next = STATE_ACTIVE_WRITE;
|
||||
end
|
||||
end else begin
|
||||
if (stop_on_idle & s_axis_cmd_ready & ~s_axis_cmd_valid) begin
|
||||
// no waiting command and stop_on_idle selected, issue stop condition
|
||||
phy_stop_bit = 1'b1;
|
||||
state_next = STATE_IDLE;
|
||||
end else begin
|
||||
state_next = STATE_ACTIVE_WRITE;
|
||||
end
|
||||
end
|
||||
end
|
||||
STATE_ACTIVE_READ: begin
|
||||
// line active to current address
|
||||
s_axis_cmd_ready_next = ~m_axis_data_tvalid;
|
||||
|
||||
if (s_axis_cmd_ready & s_axis_cmd_valid) begin
|
||||
// command valid
|
||||
if (s_axis_cmd_read ^ (s_axis_cmd_write | s_axis_cmd_write_multiple)) begin
|
||||
// read or write command
|
||||
addr_next = s_axis_cmd_address;
|
||||
mode_read_next = s_axis_cmd_read;
|
||||
mode_write_multiple_next = s_axis_cmd_write_multiple;
|
||||
mode_stop_next = s_axis_cmd_stop;
|
||||
|
||||
s_axis_cmd_ready_next = 1'b0;
|
||||
|
||||
if (s_axis_cmd_start || s_axis_cmd_address != addr_reg || s_axis_cmd_write) begin
|
||||
// address or mode mismatch or forced start - repeated start
|
||||
|
||||
// write nack for previous read
|
||||
phy_write_bit = 1'b1;
|
||||
phy_tx_data = 1'b1;
|
||||
// repeated start bit
|
||||
state_next = STATE_START;
|
||||
end else begin
|
||||
// address and mode match
|
||||
|
||||
// write ack for previous read
|
||||
phy_write_bit = 1'b1;
|
||||
phy_tx_data = 1'b0;
|
||||
// start next read
|
||||
bit_count_next = 4'd8;
|
||||
data_next = 8'd0;
|
||||
state_next = STATE_READ;
|
||||
end
|
||||
end else if (s_axis_cmd_stop && !(s_axis_cmd_read || s_axis_cmd_write || s_axis_cmd_write_multiple)) begin
|
||||
// stop command
|
||||
// write nack for previous read
|
||||
phy_write_bit = 1'b1;
|
||||
phy_tx_data = 1'b1;
|
||||
// send stop bit
|
||||
state_next = STATE_STOP;
|
||||
end else begin
|
||||
// invalid or unspecified - ignore
|
||||
state_next = STATE_ACTIVE_READ;
|
||||
end
|
||||
end else begin
|
||||
if (stop_on_idle & s_axis_cmd_ready & ~s_axis_cmd_valid) begin
|
||||
// no waiting command and stop_on_idle selected, issue stop condition
|
||||
// write ack for previous read
|
||||
phy_write_bit = 1'b1;
|
||||
phy_tx_data = 1'b1;
|
||||
// send stop bit
|
||||
state_next = STATE_STOP;
|
||||
end else begin
|
||||
state_next = STATE_ACTIVE_READ;
|
||||
end
|
||||
end
|
||||
end
|
||||
STATE_START_WAIT: begin
|
||||
// wait for bus idle
|
||||
|
||||
if (bus_active) begin
|
||||
state_next = STATE_START_WAIT;
|
||||
end else begin
|
||||
// bus is idle, take control
|
||||
phy_start_bit = 1'b1;
|
||||
bit_count_next = 4'd8;
|
||||
state_next = STATE_ADDRESS_1;
|
||||
end
|
||||
end
|
||||
STATE_START: begin
|
||||
// send start bit
|
||||
|
||||
phy_start_bit = 1'b1;
|
||||
bit_count_next = 4'd8;
|
||||
state_next = STATE_ADDRESS_1;
|
||||
end
|
||||
STATE_ADDRESS_1: begin
|
||||
// send address
|
||||
bit_count_next = bit_count_reg - 1;
|
||||
if (bit_count_reg > 1) begin
|
||||
// send address
|
||||
phy_write_bit = 1'b1;
|
||||
phy_tx_data = addr_reg[bit_count_reg-2];
|
||||
state_next = STATE_ADDRESS_1;
|
||||
end else if (bit_count_reg > 0) begin
|
||||
// send read/write bit
|
||||
phy_write_bit = 1'b1;
|
||||
phy_tx_data = mode_read_reg;
|
||||
state_next = STATE_ADDRESS_1;
|
||||
end else begin
|
||||
// read ack bit
|
||||
phy_read_bit = 1'b1;
|
||||
state_next = STATE_ADDRESS_2;
|
||||
end
|
||||
end
|
||||
STATE_ADDRESS_2: begin
|
||||
// read ack bit
|
||||
missed_ack_next = phy_rx_data_reg;
|
||||
|
||||
if (mode_read_reg) begin
|
||||
// start read
|
||||
bit_count_next = 4'd8;
|
||||
data_next = 1'b0;
|
||||
state_next = STATE_READ;
|
||||
end else begin
|
||||
// start write
|
||||
s_axis_data_tready_next = 1'b1;
|
||||
state_next = STATE_WRITE_1;
|
||||
end
|
||||
end
|
||||
STATE_WRITE_1: begin
|
||||
s_axis_data_tready_next = 1'b1;
|
||||
|
||||
if (s_axis_data_tready & s_axis_data_tvalid) begin
|
||||
// got data, start write
|
||||
data_next = s_axis_data_tdata;
|
||||
last_next = s_axis_data_tlast;
|
||||
bit_count_next = 4'd8;
|
||||
s_axis_data_tready_next = 1'b0;
|
||||
state_next = STATE_WRITE_2;
|
||||
end else begin
|
||||
// wait for data
|
||||
state_next = STATE_WRITE_1;
|
||||
end
|
||||
end
|
||||
STATE_WRITE_2: begin
|
||||
// send data
|
||||
bit_count_next = bit_count_reg - 1;
|
||||
if (bit_count_reg > 0) begin
|
||||
// write data bit
|
||||
phy_write_bit = 1'b1;
|
||||
phy_tx_data = data_reg[bit_count_reg-1];
|
||||
state_next = STATE_WRITE_2;
|
||||
end else begin
|
||||
// read ack bit
|
||||
phy_read_bit = 1'b1;
|
||||
state_next = STATE_WRITE_3;
|
||||
end
|
||||
end
|
||||
STATE_WRITE_3: begin
|
||||
// read ack bit
|
||||
missed_ack_next = phy_rx_data_reg;
|
||||
|
||||
if (mode_write_multiple_reg && !last_reg) begin
|
||||
// more to write
|
||||
state_next = STATE_WRITE_1;
|
||||
end else if (mode_stop_reg) begin
|
||||
// last cycle and stop selected
|
||||
phy_stop_bit = 1'b1;
|
||||
state_next = STATE_IDLE;
|
||||
end else begin
|
||||
// otherwise, return to bus active state
|
||||
state_next = STATE_ACTIVE_WRITE;
|
||||
end
|
||||
end
|
||||
STATE_READ: begin
|
||||
// read data
|
||||
|
||||
bit_count_next = bit_count_reg - 1;
|
||||
data_next = {data_reg[6:0], phy_rx_data_reg};
|
||||
if (bit_count_reg > 0) begin
|
||||
// read next bit
|
||||
phy_read_bit = 1'b1;
|
||||
state_next = STATE_READ;
|
||||
end else begin
|
||||
// output data word
|
||||
m_axis_data_tdata_next = data_next;
|
||||
m_axis_data_tvalid_next = 1'b1;
|
||||
m_axis_data_tlast_next = 1'b0;
|
||||
if (mode_stop_reg) begin
|
||||
// send nack and stop
|
||||
m_axis_data_tlast_next = 1'b1;
|
||||
phy_write_bit = 1'b1;
|
||||
phy_tx_data = 1'b1;
|
||||
state_next = STATE_STOP;
|
||||
end else begin
|
||||
// return to bus active state
|
||||
state_next = STATE_ACTIVE_READ;
|
||||
end
|
||||
end
|
||||
end
|
||||
STATE_STOP: begin
|
||||
// send stop bit
|
||||
phy_stop_bit = 1'b1;
|
||||
state_next = STATE_IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always @* begin
|
||||
phy_state_next = PHY_STATE_IDLE;
|
||||
|
||||
phy_rx_data_next = phy_rx_data_reg;
|
||||
|
||||
delay_next = delay_reg;
|
||||
delay_scl_next = delay_scl_reg;
|
||||
delay_sda_next = delay_sda_reg;
|
||||
|
||||
scl_o_next = scl_o_reg;
|
||||
sda_o_next = sda_o_reg;
|
||||
|
||||
bus_control_next = bus_control_reg;
|
||||
|
||||
if (phy_release_bus) begin
|
||||
// release bus and return to idle state
|
||||
sda_o_next = 1'b1;
|
||||
scl_o_next = 1'b1;
|
||||
delay_scl_next = 1'b0;
|
||||
delay_sda_next = 1'b0;
|
||||
delay_next = 1'b0;
|
||||
phy_state_next = PHY_STATE_IDLE;
|
||||
end else if (delay_scl_reg) begin
|
||||
// wait for SCL to match command
|
||||
delay_scl_next = scl_o_reg & ~scl_i_reg;
|
||||
phy_state_next = phy_state_reg;
|
||||
end else if (delay_sda_reg) begin
|
||||
// wait for SDA to match command
|
||||
delay_sda_next = sda_o_reg & ~sda_i_reg;
|
||||
phy_state_next = phy_state_reg;
|
||||
end else if (delay_reg > 0) begin
|
||||
// time delay
|
||||
delay_next = delay_reg - 1;
|
||||
phy_state_next = phy_state_reg;
|
||||
end else begin
|
||||
case (phy_state_reg)
|
||||
PHY_STATE_IDLE: begin
|
||||
// bus idle - wait for start command
|
||||
sda_o_next = 1'b1;
|
||||
scl_o_next = 1'b1;
|
||||
if (phy_start_bit) begin
|
||||
sda_o_next = 1'b0;
|
||||
delay_next = prescale;
|
||||
phy_state_next = PHY_STATE_START_1;
|
||||
end else begin
|
||||
phy_state_next = PHY_STATE_IDLE;
|
||||
end
|
||||
end
|
||||
PHY_STATE_ACTIVE: begin
|
||||
// bus active
|
||||
if (phy_start_bit) begin
|
||||
sda_o_next = 1'b1;
|
||||
delay_next = prescale;
|
||||
phy_state_next = PHY_STATE_REPEATED_START_1;
|
||||
end else if (phy_write_bit) begin
|
||||
sda_o_next = phy_tx_data;
|
||||
delay_next = prescale;
|
||||
phy_state_next = PHY_STATE_WRITE_BIT_1;
|
||||
end else if (phy_read_bit) begin
|
||||
sda_o_next = 1'b1;
|
||||
delay_next = prescale;
|
||||
phy_state_next = PHY_STATE_READ_BIT_1;
|
||||
end else if (phy_stop_bit) begin
|
||||
sda_o_next = 1'b0;
|
||||
delay_next = prescale;
|
||||
phy_state_next = PHY_STATE_STOP_1;
|
||||
end else begin
|
||||
phy_state_next = PHY_STATE_ACTIVE;
|
||||
end
|
||||
end
|
||||
PHY_STATE_REPEATED_START_1: begin
|
||||
// generate repeated start bit
|
||||
// ______
|
||||
// sda XXX/ \_______
|
||||
// _______
|
||||
// scl ______/ \___
|
||||
//
|
||||
|
||||
scl_o_next = 1'b1;
|
||||
delay_scl_next = 1'b1;
|
||||
delay_next = prescale;
|
||||
phy_state_next = PHY_STATE_REPEATED_START_2;
|
||||
end
|
||||
PHY_STATE_REPEATED_START_2: begin
|
||||
// generate repeated start bit
|
||||
// ______
|
||||
// sda XXX/ \_______
|
||||
// _______
|
||||
// scl ______/ \___
|
||||
//
|
||||
|
||||
sda_o_next = 1'b0;
|
||||
delay_next = prescale;
|
||||
phy_state_next = PHY_STATE_START_1;
|
||||
end
|
||||
PHY_STATE_START_1: begin
|
||||
// generate start bit
|
||||
// ___
|
||||
// sda \_______
|
||||
// _______
|
||||
// scl \___
|
||||
//
|
||||
|
||||
scl_o_next = 1'b0;
|
||||
delay_next = prescale;
|
||||
phy_state_next = PHY_STATE_START_2;
|
||||
end
|
||||
PHY_STATE_START_2: begin
|
||||
// generate start bit
|
||||
// ___
|
||||
// sda \_______
|
||||
// _______
|
||||
// scl \___
|
||||
//
|
||||
|
||||
bus_control_next = 1'b1;
|
||||
phy_state_next = PHY_STATE_ACTIVE;
|
||||
end
|
||||
PHY_STATE_WRITE_BIT_1: begin
|
||||
// write bit
|
||||
// ________
|
||||
// sda X________X
|
||||
// ____
|
||||
// scl __/ \__
|
||||
|
||||
scl_o_next = 1'b1;
|
||||
delay_scl_next = 1'b1;
|
||||
delay_next = prescale << 1;
|
||||
phy_state_next = PHY_STATE_WRITE_BIT_2;
|
||||
end
|
||||
PHY_STATE_WRITE_BIT_2: begin
|
||||
// write bit
|
||||
// ________
|
||||
// sda X________X
|
||||
// ____
|
||||
// scl __/ \__
|
||||
|
||||
scl_o_next = 1'b0;
|
||||
delay_next = prescale;
|
||||
phy_state_next = PHY_STATE_WRITE_BIT_3;
|
||||
end
|
||||
PHY_STATE_WRITE_BIT_3: begin
|
||||
// write bit
|
||||
// ________
|
||||
// sda X________X
|
||||
// ____
|
||||
// scl __/ \__
|
||||
|
||||
phy_state_next = PHY_STATE_ACTIVE;
|
||||
end
|
||||
PHY_STATE_READ_BIT_1: begin
|
||||
// read bit
|
||||
// ________
|
||||
// sda X________X
|
||||
// ____
|
||||
// scl __/ \__
|
||||
|
||||
scl_o_next = 1'b1;
|
||||
delay_scl_next = 1'b1;
|
||||
delay_next = prescale;
|
||||
phy_state_next = PHY_STATE_READ_BIT_2;
|
||||
end
|
||||
PHY_STATE_READ_BIT_2: begin
|
||||
// read bit
|
||||
// ________
|
||||
// sda X________X
|
||||
// ____
|
||||
// scl __/ \__
|
||||
|
||||
phy_rx_data_next = sda_i_reg;
|
||||
delay_next = prescale;
|
||||
phy_state_next = PHY_STATE_READ_BIT_3;
|
||||
end
|
||||
PHY_STATE_READ_BIT_3: begin
|
||||
// read bit
|
||||
// ________
|
||||
// sda X________X
|
||||
// ____
|
||||
// scl __/ \__
|
||||
|
||||
scl_o_next = 1'b0;
|
||||
delay_next = prescale;
|
||||
phy_state_next = PHY_STATE_READ_BIT_4;
|
||||
end
|
||||
PHY_STATE_READ_BIT_4: begin
|
||||
// read bit
|
||||
// ________
|
||||
// sda X________X
|
||||
// ____
|
||||
// scl __/ \__
|
||||
|
||||
phy_state_next = PHY_STATE_ACTIVE;
|
||||
end
|
||||
PHY_STATE_STOP_1: begin
|
||||
// stop bit
|
||||
// ___
|
||||
// sda XXX\_______/
|
||||
// _______
|
||||
// scl _______/
|
||||
|
||||
scl_o_next = 1'b1;
|
||||
delay_scl_next = 1'b1;
|
||||
delay_next = prescale;
|
||||
phy_state_next = PHY_STATE_STOP_2;
|
||||
end
|
||||
PHY_STATE_STOP_2: begin
|
||||
// stop bit
|
||||
// ___
|
||||
// sda XXX\_______/
|
||||
// _______
|
||||
// scl _______/
|
||||
|
||||
sda_o_next = 1'b1;
|
||||
delay_next = prescale;
|
||||
phy_state_next = PHY_STATE_STOP_3;
|
||||
end
|
||||
PHY_STATE_STOP_3: begin
|
||||
// stop bit
|
||||
// ___
|
||||
// sda XXX\_______/
|
||||
// _______
|
||||
// scl _______/
|
||||
|
||||
bus_control_next = 1'b0;
|
||||
phy_state_next = PHY_STATE_IDLE;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
state_reg <= state_next;
|
||||
phy_state_reg <= phy_state_next;
|
||||
|
||||
phy_rx_data_reg <= phy_rx_data_next;
|
||||
|
||||
addr_reg <= addr_next;
|
||||
data_reg <= data_next;
|
||||
last_reg <= last_next;
|
||||
|
||||
mode_read_reg <= mode_read_next;
|
||||
mode_write_multiple_reg <= mode_write_multiple_next;
|
||||
mode_stop_reg <= mode_stop_next;
|
||||
|
||||
delay_reg <= delay_next;
|
||||
delay_scl_reg <= delay_scl_next;
|
||||
delay_sda_reg <= delay_sda_next;
|
||||
|
||||
bit_count_reg <= bit_count_next;
|
||||
|
||||
s_axis_cmd_ready_reg <= s_axis_cmd_ready_next;
|
||||
|
||||
s_axis_data_tready_reg <= s_axis_data_tready_next;
|
||||
|
||||
m_axis_data_tdata_reg <= m_axis_data_tdata_next;
|
||||
m_axis_data_tlast_reg <= m_axis_data_tlast_next;
|
||||
m_axis_data_tvalid_reg <= m_axis_data_tvalid_next;
|
||||
|
||||
scl_i_reg <= scl_i;
|
||||
sda_i_reg <= sda_i;
|
||||
|
||||
scl_o_reg <= scl_o_next;
|
||||
sda_o_reg <= sda_o_next;
|
||||
|
||||
last_scl_i_reg <= scl_i_reg;
|
||||
last_sda_i_reg <= sda_i_reg;
|
||||
|
||||
busy_reg <= !(state_reg == STATE_IDLE || state_reg == STATE_ACTIVE_WRITE || state_reg == STATE_ACTIVE_READ) || !(phy_state_reg == PHY_STATE_IDLE || phy_state_reg == PHY_STATE_ACTIVE);
|
||||
|
||||
if (start_bit) begin
|
||||
bus_active_reg <= 1'b1;
|
||||
end else if (stop_bit) begin
|
||||
bus_active_reg <= 1'b0;
|
||||
end else begin
|
||||
bus_active_reg <= bus_active_reg;
|
||||
end
|
||||
|
||||
bus_control_reg <= bus_control_next;
|
||||
missed_ack_reg <= missed_ack_next;
|
||||
|
||||
if (rst) begin
|
||||
state_reg <= STATE_IDLE;
|
||||
phy_state_reg <= PHY_STATE_IDLE;
|
||||
delay_reg <= 16'd0;
|
||||
delay_scl_reg <= 1'b0;
|
||||
delay_sda_reg <= 1'b0;
|
||||
s_axis_cmd_ready_reg <= 1'b0;
|
||||
s_axis_data_tready_reg <= 1'b0;
|
||||
m_axis_data_tvalid_reg <= 1'b0;
|
||||
scl_o_reg <= 1'b1;
|
||||
sda_o_reg <= 1'b1;
|
||||
busy_reg <= 1'b0;
|
||||
bus_active_reg <= 1'b0;
|
||||
bus_control_reg <= 1'b0;
|
||||
missed_ack_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
229
example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/mdio_master.v
Normal file
229
example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/mdio_master.v
Normal file
@ -0,0 +1,229 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2015-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* MDIO master
|
||||
*/
|
||||
module mdio_master (
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
/*
|
||||
* Host interface
|
||||
*/
|
||||
input wire [4:0] cmd_phy_addr,
|
||||
input wire [4:0] cmd_reg_addr,
|
||||
input wire [15:0] cmd_data,
|
||||
input wire [1:0] cmd_opcode,
|
||||
input wire cmd_valid,
|
||||
output wire cmd_ready,
|
||||
|
||||
output wire [15:0] data_out,
|
||||
output wire data_out_valid,
|
||||
input wire data_out_ready,
|
||||
|
||||
/*
|
||||
* MDIO to PHY
|
||||
*/
|
||||
output wire mdc_o,
|
||||
input wire mdio_i,
|
||||
output wire mdio_o,
|
||||
output wire mdio_t,
|
||||
|
||||
/*
|
||||
* Status
|
||||
*/
|
||||
output wire busy,
|
||||
|
||||
/*
|
||||
* Configuration
|
||||
*/
|
||||
input wire [7:0] prescale
|
||||
);
|
||||
|
||||
localparam [1:0]
|
||||
STATE_IDLE = 2'd0,
|
||||
STATE_PREAMBLE = 2'd1,
|
||||
STATE_TRANSFER = 2'd2;
|
||||
|
||||
reg [1:0] state_reg = STATE_IDLE, state_next;
|
||||
|
||||
reg [16:0] count_reg = 16'd0, count_next;
|
||||
reg [6:0] bit_count_reg = 6'd0, bit_count_next;
|
||||
reg cycle_reg = 1'b0, cycle_next;
|
||||
|
||||
reg [31:0] data_reg = 32'd0, data_next;
|
||||
|
||||
reg [1:0] op_reg = 2'b00, op_next;
|
||||
|
||||
reg cmd_ready_reg = 1'b0, cmd_ready_next;
|
||||
|
||||
reg [15:0] data_out_reg = 15'd0, data_out_next;
|
||||
reg data_out_valid_reg = 1'b0, data_out_valid_next;
|
||||
|
||||
reg mdio_i_reg = 1'b1;
|
||||
|
||||
reg mdc_o_reg = 1'b0, mdc_o_next;
|
||||
reg mdio_o_reg = 1'b0, mdio_o_next;
|
||||
reg mdio_t_reg = 1'b1, mdio_t_next;
|
||||
|
||||
reg busy_reg = 1'b0;
|
||||
|
||||
assign cmd_ready = cmd_ready_reg;
|
||||
|
||||
assign data_out = data_out_reg;
|
||||
assign data_out_valid = data_out_valid_reg;
|
||||
|
||||
assign mdc_o = mdc_o_reg;
|
||||
assign mdio_o = mdio_o_reg;
|
||||
assign mdio_t = mdio_t_reg;
|
||||
|
||||
assign busy = busy_reg;
|
||||
|
||||
always @* begin
|
||||
state_next = STATE_IDLE;
|
||||
|
||||
count_next = count_reg;
|
||||
bit_count_next = bit_count_reg;
|
||||
cycle_next = cycle_reg;
|
||||
|
||||
data_next = data_reg;
|
||||
|
||||
op_next = op_reg;
|
||||
|
||||
cmd_ready_next = 1'b0;
|
||||
|
||||
data_out_next = data_out_reg;
|
||||
data_out_valid_next = data_out_valid_reg & ~data_out_ready;
|
||||
|
||||
mdc_o_next = mdc_o_reg;
|
||||
mdio_o_next = mdio_o_reg;
|
||||
mdio_t_next = mdio_t_reg;
|
||||
|
||||
if (count_reg > 16'd0) begin
|
||||
count_next = count_reg - 16'd1;
|
||||
state_next = state_reg;
|
||||
end else if (cycle_reg) begin
|
||||
cycle_next = 1'b0;
|
||||
mdc_o_next = 1'b1;
|
||||
count_next = prescale;
|
||||
state_next = state_reg;
|
||||
end else begin
|
||||
mdc_o_next = 1'b0;
|
||||
case (state_reg)
|
||||
STATE_IDLE: begin
|
||||
// idle - accept new command
|
||||
cmd_ready_next = ~data_out_valid;
|
||||
|
||||
if (cmd_ready & cmd_valid) begin
|
||||
cmd_ready_next = 1'b0;
|
||||
data_next = {2'b01, cmd_opcode, cmd_phy_addr, cmd_reg_addr, 2'b10, cmd_data};
|
||||
op_next = cmd_opcode;
|
||||
mdio_t_next = 1'b0;
|
||||
mdio_o_next = 1'b1;
|
||||
bit_count_next = 6'd32;
|
||||
cycle_next = 1'b1;
|
||||
count_next = prescale;
|
||||
state_next = STATE_PREAMBLE;
|
||||
end else begin
|
||||
state_next = STATE_IDLE;
|
||||
end
|
||||
end
|
||||
STATE_PREAMBLE: begin
|
||||
cycle_next = 1'b1;
|
||||
count_next = prescale;
|
||||
if (bit_count_reg > 6'd1) begin
|
||||
bit_count_next = bit_count_reg - 6'd1;
|
||||
state_next = STATE_PREAMBLE;
|
||||
end else begin
|
||||
bit_count_next = 6'd32;
|
||||
{mdio_o_next, data_next} = {data_reg, mdio_i_reg};
|
||||
state_next = STATE_TRANSFER;
|
||||
end
|
||||
end
|
||||
STATE_TRANSFER: begin
|
||||
cycle_next = 1'b1;
|
||||
count_next = prescale;
|
||||
if ((op_reg == 2'b10 || op_reg == 2'b11) && bit_count_reg == 6'd19) begin
|
||||
mdio_t_next = 1'b1;
|
||||
end
|
||||
if (bit_count_reg > 6'd1) begin
|
||||
bit_count_next = bit_count_reg - 6'd1;
|
||||
{mdio_o_next, data_next} = {data_reg, mdio_i_reg};
|
||||
state_next = STATE_TRANSFER;
|
||||
end else begin
|
||||
if (op_reg == 2'b10 || op_reg == 2'b11) begin
|
||||
data_out_next = data_reg[15:0];
|
||||
data_out_valid_next = 1'b1;
|
||||
end
|
||||
mdio_t_next = 1'b1;
|
||||
state_next = STATE_IDLE;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (rst) begin
|
||||
state_reg <= STATE_IDLE;
|
||||
count_reg <= 16'd0;
|
||||
bit_count_reg <= 6'd0;
|
||||
cycle_reg <= 1'b0;
|
||||
cmd_ready_reg <= 1'b0;
|
||||
data_out_valid_reg <= 1'b0;
|
||||
mdc_o_reg <= 1'b0;
|
||||
mdio_o_reg <= 1'b0;
|
||||
mdio_t_reg <= 1'b1;
|
||||
busy_reg <= 1'b0;
|
||||
end else begin
|
||||
state_reg <= state_next;
|
||||
count_reg <= count_next;
|
||||
bit_count_reg <= bit_count_next;
|
||||
cycle_reg <= cycle_next;
|
||||
cmd_ready_reg <= cmd_ready_next;
|
||||
data_out_valid_reg <= data_out_valid_next;
|
||||
mdc_o_reg <= mdc_o_next;
|
||||
mdio_o_reg <= mdio_o_next;
|
||||
mdio_t_reg <= mdio_t_next;
|
||||
busy_reg <= (state_next != STATE_IDLE || count_reg != 0 || cycle_reg || mdc_o);
|
||||
end
|
||||
|
||||
data_reg <= data_next;
|
||||
op_reg <= op_next;
|
||||
|
||||
data_out_reg <= data_out_next;
|
||||
|
||||
mdio_i_reg <= mdio_i;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
62
example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/sync_signal.v
Normal file
62
example/VCU118/fpga_fmc_htg_6qsfp_25g/rtl/sync_signal.v
Normal file
@ -0,0 +1,62 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014-2018 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog-2001
|
||||
|
||||
`resetall
|
||||
`timescale 1 ns / 1 ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* Synchronizes an asyncronous signal to a given clock by using a pipeline of
|
||||
* two registers.
|
||||
*/
|
||||
module sync_signal #(
|
||||
parameter WIDTH=1, // width of the input and output signals
|
||||
parameter N=2 // depth of synchronizer
|
||||
)(
|
||||
input wire clk,
|
||||
input wire [WIDTH-1:0] in,
|
||||
output wire [WIDTH-1:0] out
|
||||
);
|
||||
|
||||
reg [WIDTH-1:0] sync_reg[N-1:0];
|
||||
|
||||
/*
|
||||
* The synchronized output is the last register in the pipeline.
|
||||
*/
|
||||
assign out = sync_reg[N-1];
|
||||
|
||||
integer k;
|
||||
|
||||
always @(posedge clk) begin
|
||||
sync_reg[0] <= in;
|
||||
for (k = 1; k < N; k = k + 1) begin
|
||||
sync_reg[k] <= sync_reg[k-1];
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
102
example/VCU118/fpga_fmc_htg_6qsfp_25g/tb/fpga_core/Makefile
Normal file
102
example/VCU118/fpga_fmc_htg_6qsfp_25g/tb/fpga_core/Makefile
Normal file
@ -0,0 +1,102 @@
|
||||
# Copyright (c) 2020 Alex Forencich
|
||||
#
|
||||
# Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
# of this software and associated documentation files (the "Software"), to deal
|
||||
# in the Software without restriction, including without limitation the rights
|
||||
# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
# copies of the Software, and to permit persons to whom the Software is
|
||||
# furnished to do so, subject to the following conditions:
|
||||
#
|
||||
# The above copyright notice and this permission notice shall be included in
|
||||
# all copies or substantial portions of the Software.
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
# THE SOFTWARE.
|
||||
|
||||
TOPLEVEL_LANG = verilog
|
||||
|
||||
SIM ?= icarus
|
||||
WAVES ?= 0
|
||||
|
||||
COCOTB_HDL_TIMEUNIT = 1ns
|
||||
COCOTB_HDL_TIMEPRECISION = 1ps
|
||||
|
||||
DUT = fpga_core
|
||||
TOPLEVEL = $(DUT)
|
||||
MODULE = test_$(DUT)
|
||||
VERILOG_SOURCES += ../../rtl/$(DUT).v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_1g_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_1g.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/axis_gmii_rx.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/axis_gmii_tx.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/eth_mac_10g.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_rx_64.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/axis_xgmii_tx_64.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/lfsr.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/eth_axis_rx.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/eth_axis_tx.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/udp_complete_64.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/udp_checksum_gen_64.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/udp_64.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/udp_ip_rx_64.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/udp_ip_tx_64.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/ip_complete_64.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/ip_64.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/ip_eth_rx_64.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/ip_eth_tx_64.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/ip_arb_mux.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/arp.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/arp_cache.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/arp_eth_rx.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/arp_eth_tx.v
|
||||
VERILOG_SOURCES += ../../lib/eth/rtl/eth_arb_mux.v
|
||||
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/arbiter.v
|
||||
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/priority_encoder.v
|
||||
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_adapter.v
|
||||
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_switch.v
|
||||
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_register.v
|
||||
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo.v
|
||||
VERILOG_SOURCES += ../../lib/eth/lib/axis/rtl/axis_async_fifo_adapter.v
|
||||
|
||||
# module parameters
|
||||
#export PARAM_A := value
|
||||
|
||||
ifeq ($(SIM), icarus)
|
||||
PLUSARGS += -fst
|
||||
|
||||
# COMPILE_ARGS += -P $(TOPLEVEL).A=$(PARAM_A)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
VERILOG_SOURCES += iverilog_dump.v
|
||||
COMPILE_ARGS += -s iverilog_dump
|
||||
endif
|
||||
else ifeq ($(SIM), verilator)
|
||||
COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
|
||||
|
||||
# COMPILE_ARGS += -GA=$(PARAM_A)
|
||||
|
||||
ifeq ($(WAVES), 1)
|
||||
COMPILE_ARGS += --trace-fst
|
||||
endif
|
||||
endif
|
||||
|
||||
include $(shell cocotb-config --makefiles)/Makefile.sim
|
||||
|
||||
iverilog_dump.v:
|
||||
echo 'module iverilog_dump();' > $@
|
||||
echo 'initial begin' >> $@
|
||||
echo ' $$dumpfile("$(TOPLEVEL).fst");' >> $@
|
||||
echo ' $$dumpvars(0, $(TOPLEVEL));' >> $@
|
||||
echo 'end' >> $@
|
||||
echo 'endmodule' >> $@
|
||||
|
||||
clean::
|
||||
@rm -rf iverilog_dump.v
|
||||
@rm -rf dump.fst $(TOPLEVEL).fst
|
||||
@ -0,0 +1,666 @@
|
||||
"""
|
||||
|
||||
Copyright (c) 2020 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
"""
|
||||
|
||||
import logging
|
||||
import os
|
||||
|
||||
from scapy.layers.l2 import Ether, ARP
|
||||
from scapy.layers.inet import IP, UDP
|
||||
|
||||
import cocotb_test.simulator
|
||||
|
||||
import cocotb
|
||||
from cocotb.log import SimLog
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import RisingEdge
|
||||
|
||||
from cocotbext.eth import GmiiFrame, GmiiSource, GmiiSink
|
||||
from cocotbext.eth import XgmiiFrame, XgmiiSource, XgmiiSink
|
||||
|
||||
|
||||
class TB:
|
||||
def __init__(self, dut):
|
||||
self.dut = dut
|
||||
|
||||
self.log = SimLog("cocotb.tb")
|
||||
self.log.setLevel(logging.DEBUG)
|
||||
|
||||
cocotb.start_soon(Clock(dut.clk, 2.56, units="ns").start())
|
||||
|
||||
# Ethernet
|
||||
cocotb.start_soon(Clock(dut.phy_gmii_clk, 8, units="ns").start())
|
||||
|
||||
self.gmii_source = GmiiSource(dut.phy_gmii_rxd, dut.phy_gmii_rx_er, dut.phy_gmii_rx_dv,
|
||||
dut.phy_gmii_clk, dut.phy_gmii_rst, dut.phy_gmii_clk_en)
|
||||
self.gmii_sink = GmiiSink(dut.phy_gmii_txd, dut.phy_gmii_tx_er, dut.phy_gmii_tx_en,
|
||||
dut.phy_gmii_clk, dut.phy_gmii_rst, dut.phy_gmii_clk_en)
|
||||
|
||||
dut.phy_gmii_clk_en.setimmediatevalue(1)
|
||||
|
||||
cocotb.start_soon(Clock(dut.qsfp1_rx_clk_1, 2.56, units="ns").start())
|
||||
self.qsfp1_1_source = XgmiiSource(dut.qsfp1_rxd_1, dut.qsfp1_rxc_1, dut.qsfp1_rx_clk_1, dut.qsfp1_rx_rst_1)
|
||||
cocotb.start_soon(Clock(dut.qsfp1_tx_clk_1, 2.56, units="ns").start())
|
||||
self.qsfp1_1_sink = XgmiiSink(dut.qsfp1_txd_1, dut.qsfp1_txc_1, dut.qsfp1_tx_clk_1, dut.qsfp1_tx_rst_1)
|
||||
|
||||
cocotb.start_soon(Clock(dut.qsfp1_rx_clk_2, 2.56, units="ns").start())
|
||||
self.qsfp1_2_source = XgmiiSource(dut.qsfp1_rxd_2, dut.qsfp1_rxc_2, dut.qsfp1_rx_clk_2, dut.qsfp1_rx_rst_2)
|
||||
cocotb.start_soon(Clock(dut.qsfp1_tx_clk_2, 2.56, units="ns").start())
|
||||
self.qsfp1_2_sink = XgmiiSink(dut.qsfp1_txd_2, dut.qsfp1_txc_2, dut.qsfp1_tx_clk_2, dut.qsfp1_tx_rst_2)
|
||||
|
||||
cocotb.start_soon(Clock(dut.qsfp1_rx_clk_3, 2.56, units="ns").start())
|
||||
self.qsfp1_3_source = XgmiiSource(dut.qsfp1_rxd_3, dut.qsfp1_rxc_3, dut.qsfp1_rx_clk_3, dut.qsfp1_rx_rst_3)
|
||||
cocotb.start_soon(Clock(dut.qsfp1_tx_clk_3, 2.56, units="ns").start())
|
||||
self.qsfp1_3_sink = XgmiiSink(dut.qsfp1_txd_3, dut.qsfp1_txc_3, dut.qsfp1_tx_clk_3, dut.qsfp1_tx_rst_3)
|
||||
|
||||
cocotb.start_soon(Clock(dut.qsfp1_rx_clk_4, 2.56, units="ns").start())
|
||||
self.qsfp1_4_source = XgmiiSource(dut.qsfp1_rxd_4, dut.qsfp1_rxc_4, dut.qsfp1_rx_clk_4, dut.qsfp1_rx_rst_4)
|
||||
cocotb.start_soon(Clock(dut.qsfp1_tx_clk_4, 2.56, units="ns").start())
|
||||
self.qsfp1_4_sink = XgmiiSink(dut.qsfp1_txd_4, dut.qsfp1_txc_4, dut.qsfp1_tx_clk_4, dut.qsfp1_tx_rst_4)
|
||||
|
||||
cocotb.start_soon(Clock(dut.qsfp2_rx_clk_1, 2.56, units="ns").start())
|
||||
self.qsfp2_1_source = XgmiiSource(dut.qsfp2_rxd_1, dut.qsfp2_rxc_1, dut.qsfp2_rx_clk_1, dut.qsfp2_rx_rst_1)
|
||||
cocotb.start_soon(Clock(dut.qsfp2_tx_clk_1, 2.56, units="ns").start())
|
||||
self.qsfp2_1_sink = XgmiiSink(dut.qsfp2_txd_1, dut.qsfp2_txc_1, dut.qsfp2_tx_clk_1, dut.qsfp2_tx_rst_1)
|
||||
|
||||
cocotb.start_soon(Clock(dut.qsfp2_rx_clk_2, 2.56, units="ns").start())
|
||||
self.qsfp2_2_source = XgmiiSource(dut.qsfp2_rxd_2, dut.qsfp2_rxc_2, dut.qsfp2_rx_clk_2, dut.qsfp2_rx_rst_2)
|
||||
cocotb.start_soon(Clock(dut.qsfp2_tx_clk_2, 2.56, units="ns").start())
|
||||
self.qsfp2_2_sink = XgmiiSink(dut.qsfp2_txd_2, dut.qsfp2_txc_2, dut.qsfp2_tx_clk_2, dut.qsfp2_tx_rst_2)
|
||||
|
||||
cocotb.start_soon(Clock(dut.qsfp2_rx_clk_3, 2.56, units="ns").start())
|
||||
self.qsfp2_3_source = XgmiiSource(dut.qsfp2_rxd_3, dut.qsfp2_rxc_3, dut.qsfp2_rx_clk_3, dut.qsfp2_rx_rst_3)
|
||||
cocotb.start_soon(Clock(dut.qsfp2_tx_clk_3, 2.56, units="ns").start())
|
||||
self.qsfp2_3_sink = XgmiiSink(dut.qsfp2_txd_3, dut.qsfp2_txc_3, dut.qsfp2_tx_clk_3, dut.qsfp2_tx_rst_3)
|
||||
|
||||
cocotb.start_soon(Clock(dut.qsfp2_rx_clk_4, 2.56, units="ns").start())
|
||||
self.qsfp2_4_source = XgmiiSource(dut.qsfp2_rxd_4, dut.qsfp2_rxc_4, dut.qsfp2_rx_clk_4, dut.qsfp2_rx_rst_4)
|
||||
cocotb.start_soon(Clock(dut.qsfp2_tx_clk_4, 2.56, units="ns").start())
|
||||
self.qsfp2_4_sink = XgmiiSink(dut.qsfp2_txd_4, dut.qsfp2_txc_4, dut.qsfp2_tx_clk_4, dut.qsfp2_tx_rst_4)
|
||||
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp1_rx_clk_1, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp1_1_source = XgmiiSource(dut.fmcp_qsfp1_rxd_1, dut.fmcp_qsfp1_rxc_1, dut.fmcp_qsfp1_rx_clk_1, dut.fmcp_qsfp1_rx_rst_1)
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp1_tx_clk_1, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp1_1_sink = XgmiiSink(dut.fmcp_qsfp1_txd_1, dut.fmcp_qsfp1_txc_1, dut.fmcp_qsfp1_tx_clk_1, dut.fmcp_qsfp1_tx_rst_1)
|
||||
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp1_rx_clk_2, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp1_2_source = XgmiiSource(dut.fmcp_qsfp1_rxd_2, dut.fmcp_qsfp1_rxc_2, dut.fmcp_qsfp1_rx_clk_2, dut.fmcp_qsfp1_rx_rst_2)
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp1_tx_clk_2, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp1_2_sink = XgmiiSink(dut.fmcp_qsfp1_txd_2, dut.fmcp_qsfp1_txc_2, dut.fmcp_qsfp1_tx_clk_2, dut.fmcp_qsfp1_tx_rst_2)
|
||||
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp1_rx_clk_3, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp1_3_source = XgmiiSource(dut.fmcp_qsfp1_rxd_3, dut.fmcp_qsfp1_rxc_3, dut.fmcp_qsfp1_rx_clk_3, dut.fmcp_qsfp1_rx_rst_3)
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp1_tx_clk_3, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp1_3_sink = XgmiiSink(dut.fmcp_qsfp1_txd_3, dut.fmcp_qsfp1_txc_3, dut.fmcp_qsfp1_tx_clk_3, dut.fmcp_qsfp1_tx_rst_3)
|
||||
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp1_rx_clk_4, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp1_4_source = XgmiiSource(dut.fmcp_qsfp1_rxd_4, dut.fmcp_qsfp1_rxc_4, dut.fmcp_qsfp1_rx_clk_4, dut.fmcp_qsfp1_rx_rst_4)
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp1_tx_clk_4, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp1_4_sink = XgmiiSink(dut.fmcp_qsfp1_txd_4, dut.fmcp_qsfp1_txc_4, dut.fmcp_qsfp1_tx_clk_4, dut.fmcp_qsfp1_tx_rst_4)
|
||||
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp2_rx_clk_1, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp2_1_source = XgmiiSource(dut.fmcp_qsfp2_rxd_1, dut.fmcp_qsfp2_rxc_1, dut.fmcp_qsfp2_rx_clk_1, dut.fmcp_qsfp2_rx_rst_1)
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp2_tx_clk_1, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp2_1_sink = XgmiiSink(dut.fmcp_qsfp2_txd_1, dut.fmcp_qsfp2_txc_1, dut.fmcp_qsfp2_tx_clk_1, dut.fmcp_qsfp2_tx_rst_1)
|
||||
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp2_rx_clk_2, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp2_2_source = XgmiiSource(dut.fmcp_qsfp2_rxd_2, dut.fmcp_qsfp2_rxc_2, dut.fmcp_qsfp2_rx_clk_2, dut.fmcp_qsfp2_rx_rst_2)
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp2_tx_clk_2, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp2_2_sink = XgmiiSink(dut.fmcp_qsfp2_txd_2, dut.fmcp_qsfp2_txc_2, dut.fmcp_qsfp2_tx_clk_2, dut.fmcp_qsfp2_tx_rst_2)
|
||||
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp2_rx_clk_3, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp2_3_source = XgmiiSource(dut.fmcp_qsfp2_rxd_3, dut.fmcp_qsfp2_rxc_3, dut.fmcp_qsfp2_rx_clk_3, dut.fmcp_qsfp2_rx_rst_3)
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp2_tx_clk_3, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp2_3_sink = XgmiiSink(dut.fmcp_qsfp2_txd_3, dut.fmcp_qsfp2_txc_3, dut.fmcp_qsfp2_tx_clk_3, dut.fmcp_qsfp2_tx_rst_3)
|
||||
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp2_rx_clk_4, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp2_4_source = XgmiiSource(dut.fmcp_qsfp2_rxd_4, dut.fmcp_qsfp2_rxc_4, dut.fmcp_qsfp2_rx_clk_4, dut.fmcp_qsfp2_rx_rst_4)
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp2_tx_clk_4, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp2_4_sink = XgmiiSink(dut.fmcp_qsfp2_txd_4, dut.fmcp_qsfp2_txc_4, dut.fmcp_qsfp2_tx_clk_4, dut.fmcp_qsfp2_tx_rst_4)
|
||||
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp3_rx_clk_1, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp3_1_source = XgmiiSource(dut.fmcp_qsfp3_rxd_1, dut.fmcp_qsfp3_rxc_1, dut.fmcp_qsfp3_rx_clk_1, dut.fmcp_qsfp3_rx_rst_1)
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp3_tx_clk_1, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp3_1_sink = XgmiiSink(dut.fmcp_qsfp3_txd_1, dut.fmcp_qsfp3_txc_1, dut.fmcp_qsfp3_tx_clk_1, dut.fmcp_qsfp3_tx_rst_1)
|
||||
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp3_rx_clk_2, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp3_2_source = XgmiiSource(dut.fmcp_qsfp3_rxd_2, dut.fmcp_qsfp3_rxc_2, dut.fmcp_qsfp3_rx_clk_2, dut.fmcp_qsfp3_rx_rst_2)
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp3_tx_clk_2, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp3_2_sink = XgmiiSink(dut.fmcp_qsfp3_txd_2, dut.fmcp_qsfp3_txc_2, dut.fmcp_qsfp3_tx_clk_2, dut.fmcp_qsfp3_tx_rst_2)
|
||||
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp3_rx_clk_3, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp3_3_source = XgmiiSource(dut.fmcp_qsfp3_rxd_3, dut.fmcp_qsfp3_rxc_3, dut.fmcp_qsfp3_rx_clk_3, dut.fmcp_qsfp3_rx_rst_3)
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp3_tx_clk_3, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp3_3_sink = XgmiiSink(dut.fmcp_qsfp3_txd_3, dut.fmcp_qsfp3_txc_3, dut.fmcp_qsfp3_tx_clk_3, dut.fmcp_qsfp3_tx_rst_3)
|
||||
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp3_rx_clk_4, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp3_4_source = XgmiiSource(dut.fmcp_qsfp3_rxd_4, dut.fmcp_qsfp3_rxc_4, dut.fmcp_qsfp3_rx_clk_4, dut.fmcp_qsfp3_rx_rst_4)
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp3_tx_clk_4, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp3_4_sink = XgmiiSink(dut.fmcp_qsfp3_txd_4, dut.fmcp_qsfp3_txc_4, dut.fmcp_qsfp3_tx_clk_4, dut.fmcp_qsfp3_tx_rst_4)
|
||||
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp4_rx_clk_1, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp4_1_source = XgmiiSource(dut.fmcp_qsfp4_rxd_1, dut.fmcp_qsfp4_rxc_1, dut.fmcp_qsfp4_rx_clk_1, dut.fmcp_qsfp4_rx_rst_1)
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp4_tx_clk_1, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp4_1_sink = XgmiiSink(dut.fmcp_qsfp4_txd_1, dut.fmcp_qsfp4_txc_1, dut.fmcp_qsfp4_tx_clk_1, dut.fmcp_qsfp4_tx_rst_1)
|
||||
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp4_rx_clk_2, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp4_2_source = XgmiiSource(dut.fmcp_qsfp4_rxd_2, dut.fmcp_qsfp4_rxc_2, dut.fmcp_qsfp4_rx_clk_2, dut.fmcp_qsfp4_rx_rst_2)
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp4_tx_clk_2, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp4_2_sink = XgmiiSink(dut.fmcp_qsfp4_txd_2, dut.fmcp_qsfp4_txc_2, dut.fmcp_qsfp4_tx_clk_2, dut.fmcp_qsfp4_tx_rst_2)
|
||||
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp4_rx_clk_3, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp4_3_source = XgmiiSource(dut.fmcp_qsfp4_rxd_3, dut.fmcp_qsfp4_rxc_3, dut.fmcp_qsfp4_rx_clk_3, dut.fmcp_qsfp4_rx_rst_3)
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp4_tx_clk_3, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp4_3_sink = XgmiiSink(dut.fmcp_qsfp4_txd_3, dut.fmcp_qsfp4_txc_3, dut.fmcp_qsfp4_tx_clk_3, dut.fmcp_qsfp4_tx_rst_3)
|
||||
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp4_rx_clk_4, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp4_4_source = XgmiiSource(dut.fmcp_qsfp4_rxd_4, dut.fmcp_qsfp4_rxc_4, dut.fmcp_qsfp4_rx_clk_4, dut.fmcp_qsfp4_rx_rst_4)
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp4_tx_clk_4, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp4_4_sink = XgmiiSink(dut.fmcp_qsfp4_txd_4, dut.fmcp_qsfp4_txc_4, dut.fmcp_qsfp4_tx_clk_4, dut.fmcp_qsfp4_tx_rst_4)
|
||||
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp5_rx_clk_1, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp5_1_source = XgmiiSource(dut.fmcp_qsfp5_rxd_1, dut.fmcp_qsfp5_rxc_1, dut.fmcp_qsfp5_rx_clk_1, dut.fmcp_qsfp5_rx_rst_1)
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp5_tx_clk_1, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp5_1_sink = XgmiiSink(dut.fmcp_qsfp5_txd_1, dut.fmcp_qsfp5_txc_1, dut.fmcp_qsfp5_tx_clk_1, dut.fmcp_qsfp5_tx_rst_1)
|
||||
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp5_rx_clk_2, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp5_2_source = XgmiiSource(dut.fmcp_qsfp5_rxd_2, dut.fmcp_qsfp5_rxc_2, dut.fmcp_qsfp5_rx_clk_2, dut.fmcp_qsfp5_rx_rst_2)
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp5_tx_clk_2, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp5_2_sink = XgmiiSink(dut.fmcp_qsfp5_txd_2, dut.fmcp_qsfp5_txc_2, dut.fmcp_qsfp5_tx_clk_2, dut.fmcp_qsfp5_tx_rst_2)
|
||||
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp5_rx_clk_3, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp5_3_source = XgmiiSource(dut.fmcp_qsfp5_rxd_3, dut.fmcp_qsfp5_rxc_3, dut.fmcp_qsfp5_rx_clk_3, dut.fmcp_qsfp5_rx_rst_3)
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp5_tx_clk_3, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp5_3_sink = XgmiiSink(dut.fmcp_qsfp5_txd_3, dut.fmcp_qsfp5_txc_3, dut.fmcp_qsfp5_tx_clk_3, dut.fmcp_qsfp5_tx_rst_3)
|
||||
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp5_rx_clk_4, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp5_4_source = XgmiiSource(dut.fmcp_qsfp5_rxd_4, dut.fmcp_qsfp5_rxc_4, dut.fmcp_qsfp5_rx_clk_4, dut.fmcp_qsfp5_rx_rst_4)
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp5_tx_clk_4, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp5_4_sink = XgmiiSink(dut.fmcp_qsfp5_txd_4, dut.fmcp_qsfp5_txc_4, dut.fmcp_qsfp5_tx_clk_4, dut.fmcp_qsfp5_tx_rst_4)
|
||||
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp6_rx_clk_1, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp6_1_source = XgmiiSource(dut.fmcp_qsfp6_rxd_1, dut.fmcp_qsfp6_rxc_1, dut.fmcp_qsfp6_rx_clk_1, dut.fmcp_qsfp6_rx_rst_1)
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp6_tx_clk_1, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp6_1_sink = XgmiiSink(dut.fmcp_qsfp6_txd_1, dut.fmcp_qsfp6_txc_1, dut.fmcp_qsfp6_tx_clk_1, dut.fmcp_qsfp6_tx_rst_1)
|
||||
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp6_rx_clk_2, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp6_2_source = XgmiiSource(dut.fmcp_qsfp6_rxd_2, dut.fmcp_qsfp6_rxc_2, dut.fmcp_qsfp6_rx_clk_2, dut.fmcp_qsfp6_rx_rst_2)
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp6_tx_clk_2, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp6_2_sink = XgmiiSink(dut.fmcp_qsfp6_txd_2, dut.fmcp_qsfp6_txc_2, dut.fmcp_qsfp6_tx_clk_2, dut.fmcp_qsfp6_tx_rst_2)
|
||||
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp6_rx_clk_3, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp6_3_source = XgmiiSource(dut.fmcp_qsfp6_rxd_3, dut.fmcp_qsfp6_rxc_3, dut.fmcp_qsfp6_rx_clk_3, dut.fmcp_qsfp6_rx_rst_3)
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp6_tx_clk_3, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp6_3_sink = XgmiiSink(dut.fmcp_qsfp6_txd_3, dut.fmcp_qsfp6_txc_3, dut.fmcp_qsfp6_tx_clk_3, dut.fmcp_qsfp6_tx_rst_3)
|
||||
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp6_rx_clk_4, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp6_4_source = XgmiiSource(dut.fmcp_qsfp6_rxd_4, dut.fmcp_qsfp6_rxc_4, dut.fmcp_qsfp6_rx_clk_4, dut.fmcp_qsfp6_rx_rst_4)
|
||||
cocotb.start_soon(Clock(dut.fmcp_qsfp6_tx_clk_4, 2.56, units="ns").start())
|
||||
self.fmcp_qsfp6_4_sink = XgmiiSink(dut.fmcp_qsfp6_txd_4, dut.fmcp_qsfp6_txc_4, dut.fmcp_qsfp6_tx_clk_4, dut.fmcp_qsfp6_tx_rst_4)
|
||||
|
||||
dut.btnu.setimmediatevalue(0)
|
||||
dut.btnl.setimmediatevalue(0)
|
||||
dut.btnd.setimmediatevalue(0)
|
||||
dut.btnr.setimmediatevalue(0)
|
||||
dut.btnc.setimmediatevalue(0)
|
||||
dut.sw.setimmediatevalue(0)
|
||||
dut.uart_rxd.setimmediatevalue(0)
|
||||
dut.uart_cts.setimmediatevalue(0)
|
||||
|
||||
async def init(self):
|
||||
|
||||
self.dut.rst.setimmediatevalue(0)
|
||||
self.dut.phy_gmii_rst.setimmediatevalue(0)
|
||||
self.dut.qsfp1_rx_rst_1.setimmediatevalue(0)
|
||||
self.dut.qsfp1_tx_rst_1.setimmediatevalue(0)
|
||||
self.dut.qsfp1_rx_rst_2.setimmediatevalue(0)
|
||||
self.dut.qsfp1_tx_rst_2.setimmediatevalue(0)
|
||||
self.dut.qsfp1_rx_rst_3.setimmediatevalue(0)
|
||||
self.dut.qsfp1_tx_rst_3.setimmediatevalue(0)
|
||||
self.dut.qsfp1_rx_rst_4.setimmediatevalue(0)
|
||||
self.dut.qsfp1_tx_rst_4.setimmediatevalue(0)
|
||||
self.dut.qsfp2_rx_rst_1.setimmediatevalue(0)
|
||||
self.dut.qsfp2_tx_rst_1.setimmediatevalue(0)
|
||||
self.dut.qsfp2_rx_rst_2.setimmediatevalue(0)
|
||||
self.dut.qsfp2_tx_rst_2.setimmediatevalue(0)
|
||||
self.dut.qsfp2_rx_rst_3.setimmediatevalue(0)
|
||||
self.dut.qsfp2_tx_rst_3.setimmediatevalue(0)
|
||||
self.dut.qsfp2_rx_rst_4.setimmediatevalue(0)
|
||||
self.dut.qsfp2_tx_rst_4.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp1_rx_rst_1.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp1_tx_rst_1.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp1_rx_rst_2.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp1_tx_rst_2.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp1_rx_rst_3.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp1_tx_rst_3.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp1_rx_rst_4.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp1_tx_rst_4.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp2_rx_rst_1.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp2_tx_rst_1.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp2_rx_rst_2.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp2_tx_rst_2.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp2_rx_rst_3.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp2_tx_rst_3.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp2_rx_rst_4.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp2_tx_rst_4.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp3_rx_rst_1.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp3_tx_rst_1.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp3_rx_rst_2.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp3_tx_rst_2.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp3_rx_rst_3.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp3_tx_rst_3.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp3_rx_rst_4.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp3_tx_rst_4.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp4_rx_rst_1.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp4_tx_rst_1.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp4_rx_rst_2.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp4_tx_rst_2.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp4_rx_rst_3.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp4_tx_rst_3.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp4_rx_rst_4.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp4_tx_rst_4.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp5_rx_rst_1.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp5_tx_rst_1.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp5_rx_rst_2.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp5_tx_rst_2.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp5_rx_rst_3.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp5_tx_rst_3.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp5_rx_rst_4.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp5_tx_rst_4.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp6_rx_rst_1.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp6_tx_rst_1.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp6_rx_rst_2.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp6_tx_rst_2.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp6_rx_rst_3.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp6_tx_rst_3.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp6_rx_rst_4.setimmediatevalue(0)
|
||||
self.dut.fmcp_qsfp6_tx_rst_4.setimmediatevalue(0)
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
self.dut.rst.value = 1
|
||||
self.dut.phy_gmii_rst.value = 1
|
||||
self.dut.qsfp1_rx_rst_1.value = 1
|
||||
self.dut.qsfp1_tx_rst_1.value = 1
|
||||
self.dut.qsfp1_rx_rst_2.value = 1
|
||||
self.dut.qsfp1_tx_rst_2.value = 1
|
||||
self.dut.qsfp1_rx_rst_3.value = 1
|
||||
self.dut.qsfp1_tx_rst_3.value = 1
|
||||
self.dut.qsfp1_rx_rst_4.value = 1
|
||||
self.dut.qsfp1_tx_rst_4.value = 1
|
||||
self.dut.qsfp2_rx_rst_1.value = 1
|
||||
self.dut.qsfp2_tx_rst_1.value = 1
|
||||
self.dut.qsfp2_rx_rst_2.value = 1
|
||||
self.dut.qsfp2_tx_rst_2.value = 1
|
||||
self.dut.qsfp2_rx_rst_3.value = 1
|
||||
self.dut.qsfp2_tx_rst_3.value = 1
|
||||
self.dut.qsfp2_rx_rst_4.value = 1
|
||||
self.dut.qsfp2_tx_rst_4.value = 1
|
||||
self.dut.fmcp_qsfp1_rx_rst_1.value = 1
|
||||
self.dut.fmcp_qsfp1_tx_rst_1.value = 1
|
||||
self.dut.fmcp_qsfp1_rx_rst_2.value = 1
|
||||
self.dut.fmcp_qsfp1_tx_rst_2.value = 1
|
||||
self.dut.fmcp_qsfp1_rx_rst_3.value = 1
|
||||
self.dut.fmcp_qsfp1_tx_rst_3.value = 1
|
||||
self.dut.fmcp_qsfp1_rx_rst_4.value = 1
|
||||
self.dut.fmcp_qsfp1_tx_rst_4.value = 1
|
||||
self.dut.fmcp_qsfp2_rx_rst_1.value = 1
|
||||
self.dut.fmcp_qsfp2_tx_rst_1.value = 1
|
||||
self.dut.fmcp_qsfp2_rx_rst_2.value = 1
|
||||
self.dut.fmcp_qsfp2_tx_rst_2.value = 1
|
||||
self.dut.fmcp_qsfp2_rx_rst_3.value = 1
|
||||
self.dut.fmcp_qsfp2_tx_rst_3.value = 1
|
||||
self.dut.fmcp_qsfp2_rx_rst_4.value = 1
|
||||
self.dut.fmcp_qsfp2_tx_rst_4.value = 1
|
||||
self.dut.fmcp_qsfp3_rx_rst_1.value = 1
|
||||
self.dut.fmcp_qsfp3_tx_rst_1.value = 1
|
||||
self.dut.fmcp_qsfp3_rx_rst_2.value = 1
|
||||
self.dut.fmcp_qsfp3_tx_rst_2.value = 1
|
||||
self.dut.fmcp_qsfp3_rx_rst_3.value = 1
|
||||
self.dut.fmcp_qsfp3_tx_rst_3.value = 1
|
||||
self.dut.fmcp_qsfp3_rx_rst_4.value = 1
|
||||
self.dut.fmcp_qsfp3_tx_rst_4.value = 1
|
||||
self.dut.fmcp_qsfp4_rx_rst_1.value = 1
|
||||
self.dut.fmcp_qsfp4_tx_rst_1.value = 1
|
||||
self.dut.fmcp_qsfp4_rx_rst_2.value = 1
|
||||
self.dut.fmcp_qsfp4_tx_rst_2.value = 1
|
||||
self.dut.fmcp_qsfp4_rx_rst_3.value = 1
|
||||
self.dut.fmcp_qsfp4_tx_rst_3.value = 1
|
||||
self.dut.fmcp_qsfp4_rx_rst_4.value = 1
|
||||
self.dut.fmcp_qsfp4_tx_rst_4.value = 1
|
||||
self.dut.fmcp_qsfp5_rx_rst_1.value = 1
|
||||
self.dut.fmcp_qsfp5_tx_rst_1.value = 1
|
||||
self.dut.fmcp_qsfp5_rx_rst_2.value = 1
|
||||
self.dut.fmcp_qsfp5_tx_rst_2.value = 1
|
||||
self.dut.fmcp_qsfp5_rx_rst_3.value = 1
|
||||
self.dut.fmcp_qsfp5_tx_rst_3.value = 1
|
||||
self.dut.fmcp_qsfp5_rx_rst_4.value = 1
|
||||
self.dut.fmcp_qsfp5_tx_rst_4.value = 1
|
||||
self.dut.fmcp_qsfp6_rx_rst_1.value = 1
|
||||
self.dut.fmcp_qsfp6_tx_rst_1.value = 1
|
||||
self.dut.fmcp_qsfp6_rx_rst_2.value = 1
|
||||
self.dut.fmcp_qsfp6_tx_rst_2.value = 1
|
||||
self.dut.fmcp_qsfp6_rx_rst_3.value = 1
|
||||
self.dut.fmcp_qsfp6_tx_rst_3.value = 1
|
||||
self.dut.fmcp_qsfp6_rx_rst_4.value = 1
|
||||
self.dut.fmcp_qsfp6_tx_rst_4.value = 1
|
||||
|
||||
for k in range(10):
|
||||
await RisingEdge(self.dut.clk)
|
||||
|
||||
self.dut.rst.value = 0
|
||||
self.dut.phy_gmii_rst.value = 0
|
||||
self.dut.qsfp1_rx_rst_1.value = 0
|
||||
self.dut.qsfp1_tx_rst_1.value = 0
|
||||
self.dut.qsfp1_rx_rst_2.value = 0
|
||||
self.dut.qsfp1_tx_rst_2.value = 0
|
||||
self.dut.qsfp1_rx_rst_3.value = 0
|
||||
self.dut.qsfp1_tx_rst_3.value = 0
|
||||
self.dut.qsfp1_rx_rst_4.value = 0
|
||||
self.dut.qsfp1_tx_rst_4.value = 0
|
||||
self.dut.qsfp2_rx_rst_1.value = 0
|
||||
self.dut.qsfp2_tx_rst_1.value = 0
|
||||
self.dut.qsfp2_rx_rst_2.value = 0
|
||||
self.dut.qsfp2_tx_rst_2.value = 0
|
||||
self.dut.qsfp2_rx_rst_3.value = 0
|
||||
self.dut.qsfp2_tx_rst_3.value = 0
|
||||
self.dut.qsfp2_rx_rst_4.value = 0
|
||||
self.dut.qsfp2_tx_rst_4.value = 0
|
||||
self.dut.fmcp_qsfp1_rx_rst_1.value = 0
|
||||
self.dut.fmcp_qsfp1_tx_rst_1.value = 0
|
||||
self.dut.fmcp_qsfp1_rx_rst_2.value = 0
|
||||
self.dut.fmcp_qsfp1_tx_rst_2.value = 0
|
||||
self.dut.fmcp_qsfp1_rx_rst_3.value = 0
|
||||
self.dut.fmcp_qsfp1_tx_rst_3.value = 0
|
||||
self.dut.fmcp_qsfp1_rx_rst_4.value = 0
|
||||
self.dut.fmcp_qsfp1_tx_rst_4.value = 0
|
||||
self.dut.fmcp_qsfp2_rx_rst_1.value = 0
|
||||
self.dut.fmcp_qsfp2_tx_rst_1.value = 0
|
||||
self.dut.fmcp_qsfp2_rx_rst_2.value = 0
|
||||
self.dut.fmcp_qsfp2_tx_rst_2.value = 0
|
||||
self.dut.fmcp_qsfp2_rx_rst_3.value = 0
|
||||
self.dut.fmcp_qsfp2_tx_rst_3.value = 0
|
||||
self.dut.fmcp_qsfp2_rx_rst_4.value = 0
|
||||
self.dut.fmcp_qsfp2_tx_rst_4.value = 0
|
||||
self.dut.fmcp_qsfp3_rx_rst_1.value = 0
|
||||
self.dut.fmcp_qsfp3_tx_rst_1.value = 0
|
||||
self.dut.fmcp_qsfp3_rx_rst_2.value = 0
|
||||
self.dut.fmcp_qsfp3_tx_rst_2.value = 0
|
||||
self.dut.fmcp_qsfp3_rx_rst_3.value = 0
|
||||
self.dut.fmcp_qsfp3_tx_rst_3.value = 0
|
||||
self.dut.fmcp_qsfp3_rx_rst_4.value = 0
|
||||
self.dut.fmcp_qsfp3_tx_rst_4.value = 0
|
||||
self.dut.fmcp_qsfp4_rx_rst_1.value = 0
|
||||
self.dut.fmcp_qsfp4_tx_rst_1.value = 0
|
||||
self.dut.fmcp_qsfp4_rx_rst_2.value = 0
|
||||
self.dut.fmcp_qsfp4_tx_rst_2.value = 0
|
||||
self.dut.fmcp_qsfp4_rx_rst_3.value = 0
|
||||
self.dut.fmcp_qsfp4_tx_rst_3.value = 0
|
||||
self.dut.fmcp_qsfp4_rx_rst_4.value = 0
|
||||
self.dut.fmcp_qsfp4_tx_rst_4.value = 0
|
||||
self.dut.fmcp_qsfp5_rx_rst_1.value = 0
|
||||
self.dut.fmcp_qsfp5_tx_rst_1.value = 0
|
||||
self.dut.fmcp_qsfp5_rx_rst_2.value = 0
|
||||
self.dut.fmcp_qsfp5_tx_rst_2.value = 0
|
||||
self.dut.fmcp_qsfp5_rx_rst_3.value = 0
|
||||
self.dut.fmcp_qsfp5_tx_rst_3.value = 0
|
||||
self.dut.fmcp_qsfp5_rx_rst_4.value = 0
|
||||
self.dut.fmcp_qsfp5_tx_rst_4.value = 0
|
||||
self.dut.fmcp_qsfp6_rx_rst_1.value = 0
|
||||
self.dut.fmcp_qsfp6_tx_rst_1.value = 0
|
||||
self.dut.fmcp_qsfp6_rx_rst_2.value = 0
|
||||
self.dut.fmcp_qsfp6_tx_rst_2.value = 0
|
||||
self.dut.fmcp_qsfp6_rx_rst_3.value = 0
|
||||
self.dut.fmcp_qsfp6_tx_rst_3.value = 0
|
||||
self.dut.fmcp_qsfp6_rx_rst_4.value = 0
|
||||
self.dut.fmcp_qsfp6_tx_rst_4.value = 0
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def run_test(dut):
|
||||
|
||||
tb = TB(dut)
|
||||
|
||||
await tb.init()
|
||||
|
||||
tb.log.info("test UDP RX packet")
|
||||
|
||||
payload = bytes([x % 256 for x in range(256)])
|
||||
eth = Ether(src='5a:51:52:53:54:55', dst='02:00:00:00:00:00')
|
||||
ip = IP(src='192.168.1.100', dst='192.168.1.128')
|
||||
udp = UDP(sport=5678, dport=1234)
|
||||
test_pkt = eth / ip / udp / payload
|
||||
|
||||
test_frame = XgmiiFrame.from_payload(test_pkt.build())
|
||||
|
||||
await tb.qsfp1_1_source.send(test_frame)
|
||||
|
||||
tb.log.info("receive ARP request")
|
||||
|
||||
rx_frame = await tb.qsfp1_1_sink.recv()
|
||||
|
||||
rx_pkt = Ether(bytes(rx_frame.get_payload()))
|
||||
|
||||
tb.log.info("RX packet: %s", repr(rx_pkt))
|
||||
|
||||
assert rx_pkt.dst == 'ff:ff:ff:ff:ff:ff'
|
||||
assert rx_pkt.src == test_pkt.dst
|
||||
assert rx_pkt[ARP].hwtype == 1
|
||||
assert rx_pkt[ARP].ptype == 0x0800
|
||||
assert rx_pkt[ARP].hwlen == 6
|
||||
assert rx_pkt[ARP].plen == 4
|
||||
assert rx_pkt[ARP].op == 1
|
||||
assert rx_pkt[ARP].hwsrc == test_pkt.dst
|
||||
assert rx_pkt[ARP].psrc == test_pkt[IP].dst
|
||||
assert rx_pkt[ARP].hwdst == '00:00:00:00:00:00'
|
||||
assert rx_pkt[ARP].pdst == test_pkt[IP].src
|
||||
|
||||
tb.log.info("send ARP response")
|
||||
|
||||
eth = Ether(src=test_pkt.src, dst=test_pkt.dst)
|
||||
arp = ARP(hwtype=1, ptype=0x0800, hwlen=6, plen=4, op=2,
|
||||
hwsrc=test_pkt.src, psrc=test_pkt[IP].src,
|
||||
hwdst=test_pkt.dst, pdst=test_pkt[IP].dst)
|
||||
resp_pkt = eth / arp
|
||||
|
||||
resp_frame = XgmiiFrame.from_payload(resp_pkt.build())
|
||||
|
||||
await tb.qsfp1_1_source.send(resp_frame)
|
||||
|
||||
tb.log.info("receive UDP packet")
|
||||
|
||||
rx_frame = await tb.qsfp1_1_sink.recv()
|
||||
|
||||
rx_pkt = Ether(bytes(rx_frame.get_payload()))
|
||||
|
||||
tb.log.info("RX packet: %s", repr(rx_pkt))
|
||||
|
||||
assert rx_pkt.dst == test_pkt.src
|
||||
assert rx_pkt.src == test_pkt.dst
|
||||
assert rx_pkt[IP].dst == test_pkt[IP].src
|
||||
assert rx_pkt[IP].src == test_pkt[IP].dst
|
||||
assert rx_pkt[UDP].dport == test_pkt[UDP].sport
|
||||
assert rx_pkt[UDP].sport == test_pkt[UDP].dport
|
||||
assert rx_pkt[UDP].payload == test_pkt[UDP].payload
|
||||
|
||||
tb.log.info("test gigabit tap, RX side")
|
||||
|
||||
# insert tap
|
||||
await RisingEdge(dut.clk)
|
||||
dut.sw.value = 0x8
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
payload = bytes([x % 256 for x in range(256)])
|
||||
eth = Ether(src='5a:51:52:53:54:55', dst='02:00:00:00:00:00')
|
||||
ip = IP(src='192.168.1.100', dst='192.168.1.128')
|
||||
udp = UDP(sport=5678, dport=1234)
|
||||
test_pkt = eth / ip / udp / payload
|
||||
|
||||
test_frame = GmiiFrame.from_payload(test_pkt.build())
|
||||
|
||||
await tb.gmii_source.send(test_frame)
|
||||
|
||||
tb.log.info("loop back packet on XGMII interface")
|
||||
|
||||
rx_frame = await tb.qsfp1_1_sink.recv()
|
||||
|
||||
rx_pkt = Ether(bytes(rx_frame.get_payload()))
|
||||
|
||||
tb.log.info("RX packet: %s", repr(rx_pkt))
|
||||
|
||||
await tb.qsfp1_1_source.send(rx_frame)
|
||||
|
||||
tb.log.info("receive UDP packet")
|
||||
|
||||
rx_frame = await tb.gmii_sink.recv()
|
||||
|
||||
rx_pkt = Ether(bytes(rx_frame.get_payload()))
|
||||
|
||||
tb.log.info("RX packet: %s", repr(rx_pkt))
|
||||
|
||||
assert rx_pkt.dst == test_pkt.src
|
||||
assert rx_pkt.src == test_pkt.dst
|
||||
assert rx_pkt[IP].dst == test_pkt[IP].src
|
||||
assert rx_pkt[IP].src == test_pkt[IP].dst
|
||||
assert rx_pkt[UDP].dport == test_pkt[UDP].sport
|
||||
assert rx_pkt[UDP].sport == test_pkt[UDP].dport
|
||||
assert rx_pkt[UDP].payload == test_pkt[UDP].payload
|
||||
|
||||
tb.log.info("test gigabit tap, TX side")
|
||||
|
||||
# insert tap
|
||||
await RisingEdge(dut.clk)
|
||||
dut.sw.value = 0xC
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
payload = bytes([x % 256 for x in range(256)])
|
||||
eth = Ether(src='5a:51:52:53:54:55', dst='02:00:00:00:00:00')
|
||||
ip = IP(src='192.168.1.100', dst='192.168.1.128')
|
||||
udp = UDP(sport=5678, dport=1234)
|
||||
test_pkt = eth / ip / udp / payload
|
||||
|
||||
test_frame = GmiiFrame.from_payload(test_pkt.build())
|
||||
|
||||
await tb.gmii_source.send(test_frame)
|
||||
|
||||
tb.log.info("loop back packet on XGMII interface")
|
||||
|
||||
rx_frame = await tb.qsfp1_1_sink.recv()
|
||||
|
||||
rx_pkt = Ether(bytes(rx_frame.get_payload()))
|
||||
|
||||
tb.log.info("RX packet: %s", repr(rx_pkt))
|
||||
|
||||
await tb.qsfp1_1_source.send(rx_frame)
|
||||
|
||||
tb.log.info("receive UDP packet")
|
||||
|
||||
rx_frame = await tb.gmii_sink.recv()
|
||||
|
||||
rx_pkt = Ether(bytes(rx_frame.get_payload()))
|
||||
|
||||
tb.log.info("RX packet: %s", repr(rx_pkt))
|
||||
|
||||
assert rx_pkt.dst == test_pkt.src
|
||||
assert rx_pkt.src == test_pkt.dst
|
||||
assert rx_pkt[IP].dst == test_pkt[IP].src
|
||||
assert rx_pkt[IP].src == test_pkt[IP].dst
|
||||
assert rx_pkt[UDP].dport == test_pkt[UDP].sport
|
||||
assert rx_pkt[UDP].sport == test_pkt[UDP].dport
|
||||
assert rx_pkt[UDP].payload == test_pkt[UDP].payload
|
||||
|
||||
await RisingEdge(dut.clk)
|
||||
await RisingEdge(dut.clk)
|
||||
|
||||
|
||||
# cocotb-test
|
||||
|
||||
tests_dir = os.path.abspath(os.path.dirname(__file__))
|
||||
rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
|
||||
lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib'))
|
||||
axis_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'lib', 'axis', 'rtl'))
|
||||
eth_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'eth', 'rtl'))
|
||||
|
||||
|
||||
def test_fpga_core(request):
|
||||
dut = "fpga_core"
|
||||
module = os.path.splitext(os.path.basename(__file__))[0]
|
||||
toplevel = dut
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(rtl_dir, f"{dut}.v"),
|
||||
os.path.join(eth_rtl_dir, "eth_mac_1g_fifo.v"),
|
||||
os.path.join(eth_rtl_dir, "eth_mac_1g.v"),
|
||||
os.path.join(eth_rtl_dir, "axis_gmii_rx.v"),
|
||||
os.path.join(eth_rtl_dir, "axis_gmii_tx.v"),
|
||||
os.path.join(eth_rtl_dir, "eth_mac_10g_fifo.v"),
|
||||
os.path.join(eth_rtl_dir, "eth_mac_10g.v"),
|
||||
os.path.join(eth_rtl_dir, "axis_xgmii_rx_64.v"),
|
||||
os.path.join(eth_rtl_dir, "axis_xgmii_tx_64.v"),
|
||||
os.path.join(eth_rtl_dir, "lfsr.v"),
|
||||
os.path.join(eth_rtl_dir, "eth_axis_rx.v"),
|
||||
os.path.join(eth_rtl_dir, "eth_axis_tx.v"),
|
||||
os.path.join(eth_rtl_dir, "udp_complete_64.v"),
|
||||
os.path.join(eth_rtl_dir, "udp_checksum_gen_64.v"),
|
||||
os.path.join(eth_rtl_dir, "udp_64.v"),
|
||||
os.path.join(eth_rtl_dir, "udp_ip_rx_64.v"),
|
||||
os.path.join(eth_rtl_dir, "udp_ip_tx_64.v"),
|
||||
os.path.join(eth_rtl_dir, "ip_complete_64.v"),
|
||||
os.path.join(eth_rtl_dir, "ip_64.v"),
|
||||
os.path.join(eth_rtl_dir, "ip_eth_rx_64.v"),
|
||||
os.path.join(eth_rtl_dir, "ip_eth_tx_64.v"),
|
||||
os.path.join(eth_rtl_dir, "ip_arb_mux.v"),
|
||||
os.path.join(eth_rtl_dir, "arp.v"),
|
||||
os.path.join(eth_rtl_dir, "arp_cache.v"),
|
||||
os.path.join(eth_rtl_dir, "arp_eth_rx.v"),
|
||||
os.path.join(eth_rtl_dir, "arp_eth_tx.v"),
|
||||
os.path.join(eth_rtl_dir, "eth_arb_mux.v"),
|
||||
os.path.join(axis_rtl_dir, "arbiter.v"),
|
||||
os.path.join(axis_rtl_dir, "priority_encoder.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_adapter.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_fifo.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_switch.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_register.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_async_fifo.v"),
|
||||
os.path.join(axis_rtl_dir, "axis_async_fifo_adapter.v"),
|
||||
]
|
||||
|
||||
parameters = {}
|
||||
|
||||
# parameters['A'] = val
|
||||
|
||||
extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
|
||||
|
||||
sim_build = os.path.join(tests_dir, "sim_build",
|
||||
request.node.name.replace('[', '-').replace(']', ''))
|
||||
|
||||
cocotb_test.simulator.run(
|
||||
python_search=[tests_dir],
|
||||
verilog_sources=verilog_sources,
|
||||
toplevel=toplevel,
|
||||
module=module,
|
||||
parameters=parameters,
|
||||
sim_build=sim_build,
|
||||
extra_env=extra_env,
|
||||
)
|
||||
Loading…
x
Reference in New Issue
Block a user