diff --git a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile index 8abf58b3c..b451fb066 100644 --- a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile +++ b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/Makefile @@ -41,6 +41,7 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/common/$(DUT).v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v +VERILOG_SOURCES += ../../rtl/common/mqnic_dram_if.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v diff --git a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py index 48b70b8f4..ccf3b399e 100644 --- a/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py +++ b/fpga/app/dma_bench/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py @@ -864,6 +864,7 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt os.path.join(rtl_dir, "common", f"{dut}.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), + os.path.join(rtl_dir, "common", "mqnic_dram_if.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), diff --git a/fpga/app/template/tb/mqnic_core_pcie_us/Makefile b/fpga/app/template/tb/mqnic_core_pcie_us/Makefile index fd1853f5b..7e7ebe2c2 100644 --- a/fpga/app/template/tb/mqnic_core_pcie_us/Makefile +++ b/fpga/app/template/tb/mqnic_core_pcie_us/Makefile @@ -41,6 +41,7 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/common/$(DUT).v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v +VERILOG_SOURCES += ../../rtl/common/mqnic_dram_if.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v diff --git a/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py index 1bed08207..ff6c8f0ca 100644 --- a/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py +++ b/fpga/app/template/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py @@ -699,8 +699,9 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt verilog_sources = [ os.path.join(rtl_dir, "common", f"{dut}.v"), - os.path.join(rtl_dir, "common", "mqnic_core.v"), os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), + os.path.join(rtl_dir, "common", "mqnic_core.v"), + os.path.join(rtl_dir, "common", "mqnic_dram_if.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), diff --git a/fpga/common/rtl/mqnic_core.v b/fpga/common/rtl/mqnic_core.v index 57c81321a..0d6bb493d 100644 --- a/fpga/common/rtl/mqnic_core.v +++ b/fpga/common/rtl/mqnic_core.v @@ -608,6 +608,8 @@ localparam CLK_CYCLES_PER_US = (1000*CLK_PERIOD_NS_DENOM)/CLK_PERIOD_NS_NUM; localparam PHC_RB_BASE_ADDR = 32'h100; localparam CLK_RB_BASE_ADDR = PHC_RB_BASE_ADDR + 32'h100; +genvar m, n; + // check configuration initial begin if (RB_NEXT_PTR > 0 && RB_NEXT_PTR < 16'h200) begin @@ -882,7 +884,7 @@ mqnic_ptp_inst ( .ptp_perout_pulse(ptp_perout_pulse) ); -localparam CLK_CNT = PORT_COUNT*2; +localparam CLK_CNT = PORT_COUNT*2 + (DDR_ENABLE ? DDR_CH : 0) + (HBM_ENABLE ? HBM_CH : 0); wire [CLK_CNT-1:0] all_clocks; @@ -891,7 +893,7 @@ mqnic_rb_clk_info #( .CLK_PERIOD_NS_DENOM(CLK_PERIOD_NS_DENOM), .REF_CLK_PERIOD_NS_NUM(PTP_CLK_PERIOD_NS_NUM), .REF_CLK_PERIOD_NS_DENOM(PTP_CLK_PERIOD_NS_DENOM), - .CH_CNT(PORT_COUNT*2), + .CH_CNT(CLK_CNT), .REG_ADDR_WIDTH(AXIL_CTRL_ADDR_WIDTH), .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), @@ -2426,6 +2428,481 @@ end endgenerate +// RAM infrastructure +wire [DDR_CH-1:0] app_ddr_clk; +wire [DDR_CH-1:0] app_ddr_rst; + +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] app_m_axi_ddr_awid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] app_m_axi_ddr_awaddr; +wire [DDR_CH*8-1:0] app_m_axi_ddr_awlen; +wire [DDR_CH*3-1:0] app_m_axi_ddr_awsize; +wire [DDR_CH*2-1:0] app_m_axi_ddr_awburst; +wire [DDR_CH-1:0] app_m_axi_ddr_awlock; +wire [DDR_CH*4-1:0] app_m_axi_ddr_awcache; +wire [DDR_CH*3-1:0] app_m_axi_ddr_awprot; +wire [DDR_CH*4-1:0] app_m_axi_ddr_awqos; +wire [DDR_CH*AXI_DDR_AWUSER_WIDTH-1:0] app_m_axi_ddr_awuser; +wire [DDR_CH-1:0] app_m_axi_ddr_awvalid; +wire [DDR_CH-1:0] app_m_axi_ddr_awready; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] app_m_axi_ddr_wdata; +wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] app_m_axi_ddr_wstrb; +wire [DDR_CH-1:0] app_m_axi_ddr_wlast; +wire [DDR_CH*AXI_DDR_WUSER_WIDTH-1:0] app_m_axi_ddr_wuser; +wire [DDR_CH-1:0] app_m_axi_ddr_wvalid; +wire [DDR_CH-1:0] app_m_axi_ddr_wready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] app_m_axi_ddr_bid; +wire [DDR_CH*2-1:0] app_m_axi_ddr_bresp; +wire [DDR_CH*AXI_DDR_BUSER_WIDTH-1:0] app_m_axi_ddr_buser; +wire [DDR_CH-1:0] app_m_axi_ddr_bvalid; +wire [DDR_CH-1:0] app_m_axi_ddr_bready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] app_m_axi_ddr_arid; +wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] app_m_axi_ddr_araddr; +wire [DDR_CH*8-1:0] app_m_axi_ddr_arlen; +wire [DDR_CH*3-1:0] app_m_axi_ddr_arsize; +wire [DDR_CH*2-1:0] app_m_axi_ddr_arburst; +wire [DDR_CH-1:0] app_m_axi_ddr_arlock; +wire [DDR_CH*4-1:0] app_m_axi_ddr_arcache; +wire [DDR_CH*3-1:0] app_m_axi_ddr_arprot; +wire [DDR_CH*4-1:0] app_m_axi_ddr_arqos; +wire [DDR_CH*AXI_DDR_ARUSER_WIDTH-1:0] app_m_axi_ddr_aruser; +wire [DDR_CH-1:0] app_m_axi_ddr_arvalid; +wire [DDR_CH-1:0] app_m_axi_ddr_arready; +wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] app_m_axi_ddr_rid; +wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] app_m_axi_ddr_rdata; +wire [DDR_CH*2-1:0] app_m_axi_ddr_rresp; +wire [DDR_CH-1:0] app_m_axi_ddr_rlast; +wire [DDR_CH*AXI_DDR_RUSER_WIDTH-1:0] app_m_axi_ddr_ruser; +wire [DDR_CH-1:0] app_m_axi_ddr_rvalid; +wire [DDR_CH-1:0] app_m_axi_ddr_rready; + +wire [DDR_CH-1:0] app_ddr_status; + +wire [HBM_CH-1:0] app_hbm_clk; +wire [HBM_CH-1:0] app_hbm_rst; + +wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] app_m_axi_hbm_awid; +wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] app_m_axi_hbm_awaddr; +wire [HBM_CH*8-1:0] app_m_axi_hbm_awlen; +wire [HBM_CH*3-1:0] app_m_axi_hbm_awsize; +wire [HBM_CH*2-1:0] app_m_axi_hbm_awburst; +wire [HBM_CH-1:0] app_m_axi_hbm_awlock; +wire [HBM_CH*4-1:0] app_m_axi_hbm_awcache; +wire [HBM_CH*3-1:0] app_m_axi_hbm_awprot; +wire [HBM_CH*4-1:0] app_m_axi_hbm_awqos; +wire [HBM_CH*AXI_HBM_AWUSER_WIDTH-1:0] app_m_axi_hbm_awuser; +wire [HBM_CH-1:0] app_m_axi_hbm_awvalid; +wire [HBM_CH-1:0] app_m_axi_hbm_awready; +wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] app_m_axi_hbm_wdata; +wire [HBM_CH*AXI_HBM_STRB_WIDTH-1:0] app_m_axi_hbm_wstrb; +wire [HBM_CH-1:0] app_m_axi_hbm_wlast; +wire [HBM_CH*AXI_HBM_WUSER_WIDTH-1:0] app_m_axi_hbm_wuser; +wire [HBM_CH-1:0] app_m_axi_hbm_wvalid; +wire [HBM_CH-1:0] app_m_axi_hbm_wready; +wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] app_m_axi_hbm_bid; +wire [HBM_CH*2-1:0] app_m_axi_hbm_bresp; +wire [HBM_CH*AXI_HBM_BUSER_WIDTH-1:0] app_m_axi_hbm_buser; +wire [HBM_CH-1:0] app_m_axi_hbm_bvalid; +wire [HBM_CH-1:0] app_m_axi_hbm_bready; +wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] app_m_axi_hbm_arid; +wire [HBM_CH*AXI_HBM_ADDR_WIDTH-1:0] app_m_axi_hbm_araddr; +wire [HBM_CH*8-1:0] app_m_axi_hbm_arlen; +wire [HBM_CH*3-1:0] app_m_axi_hbm_arsize; +wire [HBM_CH*2-1:0] app_m_axi_hbm_arburst; +wire [HBM_CH-1:0] app_m_axi_hbm_arlock; +wire [HBM_CH*4-1:0] app_m_axi_hbm_arcache; +wire [HBM_CH*3-1:0] app_m_axi_hbm_arprot; +wire [HBM_CH*4-1:0] app_m_axi_hbm_arqos; +wire [HBM_CH*AXI_HBM_ARUSER_WIDTH-1:0] app_m_axi_hbm_aruser; +wire [HBM_CH-1:0] app_m_axi_hbm_arvalid; +wire [HBM_CH-1:0] app_m_axi_hbm_arready; +wire [HBM_CH*AXI_HBM_ID_WIDTH-1:0] app_m_axi_hbm_rid; +wire [HBM_CH*AXI_HBM_DATA_WIDTH-1:0] app_m_axi_hbm_rdata; +wire [HBM_CH*2-1:0] app_m_axi_hbm_rresp; +wire [HBM_CH-1:0] app_m_axi_hbm_rlast; +wire [HBM_CH*AXI_HBM_RUSER_WIDTH-1:0] app_m_axi_hbm_ruser; +wire [HBM_CH-1:0] app_m_axi_hbm_rvalid; +wire [HBM_CH-1:0] app_m_axi_hbm_rready; + +wire [HBM_CH-1:0] app_hbm_status; + +generate + +if (DDR_ENABLE) begin : ddr + + mqnic_dram_if #( + // RAM configuration + .CH(DDR_CH), + .GROUP_SIZE(DDR_GROUP_SIZE), + .AXI_DATA_WIDTH(AXI_DDR_DATA_WIDTH), + .AXI_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH), + .AXI_STRB_WIDTH(AXI_DDR_STRB_WIDTH), + .AXI_ID_WIDTH(AXI_DDR_ID_WIDTH), + .AXI_AWUSER_ENABLE(AXI_DDR_AWUSER_ENABLE), + .AXI_AWUSER_WIDTH(AXI_DDR_AWUSER_WIDTH), + .AXI_WUSER_ENABLE(AXI_DDR_WUSER_ENABLE), + .AXI_WUSER_WIDTH(AXI_DDR_WUSER_WIDTH), + .AXI_BUSER_ENABLE(AXI_DDR_BUSER_ENABLE), + .AXI_BUSER_WIDTH(AXI_DDR_BUSER_WIDTH), + .AXI_ARUSER_ENABLE(AXI_DDR_ARUSER_ENABLE), + .AXI_ARUSER_WIDTH(AXI_DDR_ARUSER_WIDTH), + .AXI_RUSER_ENABLE(AXI_DDR_RUSER_ENABLE), + .AXI_RUSER_WIDTH(AXI_DDR_RUSER_WIDTH), + .AXI_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN), + .AXI_NARROW_BURST(AXI_DDR_NARROW_BURST), + .AXI_FIXED_BURST(AXI_DDR_FIXED_BURST), + .AXI_WRAP_BURST(AXI_DDR_WRAP_BURST) + ) + dram_if_inst ( + .clk(clk), + .rst(rst), + + /* + * AXI to DRAM + */ + .m_axi_clk(ddr_clk), + .m_axi_rst(ddr_rst), + + .m_axi_awid(m_axi_ddr_awid), + .m_axi_awaddr(m_axi_ddr_awaddr), + .m_axi_awlen(m_axi_ddr_awlen), + .m_axi_awsize(m_axi_ddr_awsize), + .m_axi_awburst(m_axi_ddr_awburst), + .m_axi_awlock(m_axi_ddr_awlock), + .m_axi_awcache(m_axi_ddr_awcache), + .m_axi_awprot(m_axi_ddr_awprot), + .m_axi_awqos(m_axi_ddr_awqos), + .m_axi_awuser(m_axi_ddr_awuser), + .m_axi_awvalid(m_axi_ddr_awvalid), + .m_axi_awready(m_axi_ddr_awready), + .m_axi_wdata(m_axi_ddr_wdata), + .m_axi_wstrb(m_axi_ddr_wstrb), + .m_axi_wlast(m_axi_ddr_wlast), + .m_axi_wuser(m_axi_ddr_wuser), + .m_axi_wvalid(m_axi_ddr_wvalid), + .m_axi_wready(m_axi_ddr_wready), + .m_axi_bid(m_axi_ddr_bid), + .m_axi_bresp(m_axi_ddr_bresp), + .m_axi_buser(m_axi_ddr_buser), + .m_axi_bvalid(m_axi_ddr_bvalid), + .m_axi_bready(m_axi_ddr_bready), + .m_axi_arid(m_axi_ddr_arid), + .m_axi_araddr(m_axi_ddr_araddr), + .m_axi_arlen(m_axi_ddr_arlen), + .m_axi_arsize(m_axi_ddr_arsize), + .m_axi_arburst(m_axi_ddr_arburst), + .m_axi_arlock(m_axi_ddr_arlock), + .m_axi_arcache(m_axi_ddr_arcache), + .m_axi_arprot(m_axi_ddr_arprot), + .m_axi_arqos(m_axi_ddr_arqos), + .m_axi_aruser(m_axi_ddr_aruser), + .m_axi_arvalid(m_axi_ddr_arvalid), + .m_axi_arready(m_axi_ddr_arready), + .m_axi_rid(m_axi_ddr_rid), + .m_axi_rdata(m_axi_ddr_rdata), + .m_axi_rresp(m_axi_ddr_rresp), + .m_axi_rlast(m_axi_ddr_rlast), + .m_axi_ruser(m_axi_ddr_ruser), + .m_axi_rvalid(m_axi_ddr_rvalid), + .m_axi_rready(m_axi_ddr_rready), + + .status_in(ddr_status), + + /* + * AXI to application + */ + .s_axi_app_clk(app_ddr_clk), + .s_axi_app_rst(app_ddr_rst), + + .s_axi_app_awid(app_m_axi_ddr_awid), + .s_axi_app_awaddr(app_m_axi_ddr_awaddr), + .s_axi_app_awlen(app_m_axi_ddr_awlen), + .s_axi_app_awsize(app_m_axi_ddr_awsize), + .s_axi_app_awburst(app_m_axi_ddr_awburst), + .s_axi_app_awlock(app_m_axi_ddr_awlock), + .s_axi_app_awcache(app_m_axi_ddr_awcache), + .s_axi_app_awprot(app_m_axi_ddr_awprot), + .s_axi_app_awqos(app_m_axi_ddr_awqos), + .s_axi_app_awuser(app_m_axi_ddr_awuser), + .s_axi_app_awvalid(app_m_axi_ddr_awvalid), + .s_axi_app_awready(app_m_axi_ddr_awready), + .s_axi_app_wdata(app_m_axi_ddr_wdata), + .s_axi_app_wstrb(app_m_axi_ddr_wstrb), + .s_axi_app_wlast(app_m_axi_ddr_wlast), + .s_axi_app_wuser(app_m_axi_ddr_wuser), + .s_axi_app_wvalid(app_m_axi_ddr_wvalid), + .s_axi_app_wready(app_m_axi_ddr_wready), + .s_axi_app_bid(app_m_axi_ddr_bid), + .s_axi_app_bresp(app_m_axi_ddr_bresp), + .s_axi_app_buser(app_m_axi_ddr_buser), + .s_axi_app_bvalid(app_m_axi_ddr_bvalid), + .s_axi_app_bready(app_m_axi_ddr_bready), + .s_axi_app_arid(app_m_axi_ddr_arid), + .s_axi_app_araddr(app_m_axi_ddr_araddr), + .s_axi_app_arlen(app_m_axi_ddr_arlen), + .s_axi_app_arsize(app_m_axi_ddr_arsize), + .s_axi_app_arburst(app_m_axi_ddr_arburst), + .s_axi_app_arlock(app_m_axi_ddr_arlock), + .s_axi_app_arcache(app_m_axi_ddr_arcache), + .s_axi_app_arprot(app_m_axi_ddr_arprot), + .s_axi_app_arqos(app_m_axi_ddr_arqos), + .s_axi_app_aruser(app_m_axi_ddr_aruser), + .s_axi_app_arvalid(app_m_axi_ddr_arvalid), + .s_axi_app_arready(app_m_axi_ddr_arready), + .s_axi_app_rid(app_m_axi_ddr_rid), + .s_axi_app_rdata(app_m_axi_ddr_rdata), + .s_axi_app_rresp(app_m_axi_ddr_rresp), + .s_axi_app_rlast(app_m_axi_ddr_rlast), + .s_axi_app_ruser(app_m_axi_ddr_ruser), + .s_axi_app_rvalid(app_m_axi_ddr_rvalid), + .s_axi_app_rready(app_m_axi_ddr_rready), + + .app_status(app_ddr_status) + ); + + assign all_clocks[PORT_COUNT*2 +: DDR_CH] = ddr_clk; + +end else begin + + assign m_axi_ddr_awid = 0; + assign m_axi_ddr_awaddr = 0; + assign m_axi_ddr_awlen = 0; + assign m_axi_ddr_awsize = 0; + assign m_axi_ddr_awburst = 0; + assign m_axi_ddr_awlock = 0; + assign m_axi_ddr_awcache = 0; + assign m_axi_ddr_awprot = 0; + assign m_axi_ddr_awqos = 0; + assign m_axi_ddr_awuser = 0; + assign m_axi_ddr_awvalid = 0; + assign m_axi_ddr_wdata = 0; + assign m_axi_ddr_wstrb = 0; + assign m_axi_ddr_wlast = 0; + assign m_axi_ddr_wuser = 0; + assign m_axi_ddr_wvalid = 0; + assign m_axi_ddr_bready = 0; + assign m_axi_ddr_arid = 0; + assign m_axi_ddr_araddr = 0; + assign m_axi_ddr_arlen = 0; + assign m_axi_ddr_arsize = 0; + assign m_axi_ddr_arburst = 0; + assign m_axi_ddr_arlock = 0; + assign m_axi_ddr_arcache = 0; + assign m_axi_ddr_arprot = 0; + assign m_axi_ddr_arqos = 0; + assign m_axi_ddr_aruser = 0; + assign m_axi_ddr_arvalid = 0; + assign m_axi_ddr_rready = 0; + + assign app_ddr_clk = 0; + assign app_ddr_rst = 0; + + assign app_m_axi_ddr_awready = 0; + assign app_m_axi_ddr_wready = 0; + assign app_m_axi_ddr_bid = 0; + assign app_m_axi_ddr_bresp = 0; + assign app_m_axi_ddr_buser = 0; + assign app_m_axi_ddr_bvalid = 0; + assign app_m_axi_ddr_arready = 0; + assign app_m_axi_ddr_rid = 0; + assign app_m_axi_ddr_rdata = 0; + assign app_m_axi_ddr_rresp = 0; + assign app_m_axi_ddr_rlast = 0; + assign app_m_axi_ddr_ruser = 0; + assign app_m_axi_ddr_rvalid = 0; + + assign app_ddr_status = 0; + +end + +if (HBM_ENABLE) begin : hbm + + mqnic_dram_if #( + // RAM configuration + .CH(HBM_CH), + .GROUP_SIZE(HBM_GROUP_SIZE), + .AXI_DATA_WIDTH(AXI_HBM_DATA_WIDTH), + .AXI_ADDR_WIDTH(AXI_HBM_ADDR_WIDTH), + .AXI_STRB_WIDTH(AXI_HBM_STRB_WIDTH), + .AXI_ID_WIDTH(AXI_HBM_ID_WIDTH), + .AXI_AWUSER_ENABLE(AXI_HBM_AWUSER_ENABLE), + .AXI_AWUSER_WIDTH(AXI_HBM_AWUSER_WIDTH), + .AXI_WUSER_ENABLE(AXI_HBM_WUSER_ENABLE), + .AXI_WUSER_WIDTH(AXI_HBM_WUSER_WIDTH), + .AXI_BUSER_ENABLE(AXI_HBM_BUSER_ENABLE), + .AXI_BUSER_WIDTH(AXI_HBM_BUSER_WIDTH), + .AXI_ARUSER_ENABLE(AXI_HBM_ARUSER_ENABLE), + .AXI_ARUSER_WIDTH(AXI_HBM_ARUSER_WIDTH), + .AXI_RUSER_ENABLE(AXI_HBM_RUSER_ENABLE), + .AXI_RUSER_WIDTH(AXI_HBM_RUSER_WIDTH), + .AXI_MAX_BURST_LEN(AXI_HBM_MAX_BURST_LEN), + .AXI_NARROW_BURST(AXI_HBM_NARROW_BURST), + .AXI_FIXED_BURST(AXI_HBM_FIXED_BURST), + .AXI_WRAP_BURST(AXI_HBM_WRAP_BURST) + ) + dram_if_inst ( + .clk(clk), + .rst(rst), + + /* + * AXI to DRAM + */ + .m_axi_clk(hbm_clk), + .m_axi_rst(hbm_rst), + + .m_axi_awid(m_axi_hbm_awid), + .m_axi_awaddr(m_axi_hbm_awaddr), + .m_axi_awlen(m_axi_hbm_awlen), + .m_axi_awsize(m_axi_hbm_awsize), + .m_axi_awburst(m_axi_hbm_awburst), + .m_axi_awlock(m_axi_hbm_awlock), + .m_axi_awcache(m_axi_hbm_awcache), + .m_axi_awprot(m_axi_hbm_awprot), + .m_axi_awqos(m_axi_hbm_awqos), + .m_axi_awuser(m_axi_hbm_awuser), + .m_axi_awvalid(m_axi_hbm_awvalid), + .m_axi_awready(m_axi_hbm_awready), + .m_axi_wdata(m_axi_hbm_wdata), + .m_axi_wstrb(m_axi_hbm_wstrb), + .m_axi_wlast(m_axi_hbm_wlast), + .m_axi_wuser(m_axi_hbm_wuser), + .m_axi_wvalid(m_axi_hbm_wvalid), + .m_axi_wready(m_axi_hbm_wready), + .m_axi_bid(m_axi_hbm_bid), + .m_axi_bresp(m_axi_hbm_bresp), + .m_axi_buser(m_axi_hbm_buser), + .m_axi_bvalid(m_axi_hbm_bvalid), + .m_axi_bready(m_axi_hbm_bready), + .m_axi_arid(m_axi_hbm_arid), + .m_axi_araddr(m_axi_hbm_araddr), + .m_axi_arlen(m_axi_hbm_arlen), + .m_axi_arsize(m_axi_hbm_arsize), + .m_axi_arburst(m_axi_hbm_arburst), + .m_axi_arlock(m_axi_hbm_arlock), + .m_axi_arcache(m_axi_hbm_arcache), + .m_axi_arprot(m_axi_hbm_arprot), + .m_axi_arqos(m_axi_hbm_arqos), + .m_axi_aruser(m_axi_hbm_aruser), + .m_axi_arvalid(m_axi_hbm_arvalid), + .m_axi_arready(m_axi_hbm_arready), + .m_axi_rid(m_axi_hbm_rid), + .m_axi_rdata(m_axi_hbm_rdata), + .m_axi_rresp(m_axi_hbm_rresp), + .m_axi_rlast(m_axi_hbm_rlast), + .m_axi_ruser(m_axi_hbm_ruser), + .m_axi_rvalid(m_axi_hbm_rvalid), + .m_axi_rready(m_axi_hbm_rready), + + .status_in(hbm_status), + + /* + * AXI to application + */ + .s_axi_app_clk(app_hbm_clk), + .s_axi_app_rst(app_hbm_rst), + + .s_axi_app_awid(app_m_axi_hbm_awid), + .s_axi_app_awaddr(app_m_axi_hbm_awaddr), + .s_axi_app_awlen(app_m_axi_hbm_awlen), + .s_axi_app_awsize(app_m_axi_hbm_awsize), + .s_axi_app_awburst(app_m_axi_hbm_awburst), + .s_axi_app_awlock(app_m_axi_hbm_awlock), + .s_axi_app_awcache(app_m_axi_hbm_awcache), + .s_axi_app_awprot(app_m_axi_hbm_awprot), + .s_axi_app_awqos(app_m_axi_hbm_awqos), + .s_axi_app_awuser(app_m_axi_hbm_awuser), + .s_axi_app_awvalid(app_m_axi_hbm_awvalid), + .s_axi_app_awready(app_m_axi_hbm_awready), + .s_axi_app_wdata(app_m_axi_hbm_wdata), + .s_axi_app_wstrb(app_m_axi_hbm_wstrb), + .s_axi_app_wlast(app_m_axi_hbm_wlast), + .s_axi_app_wuser(app_m_axi_hbm_wuser), + .s_axi_app_wvalid(app_m_axi_hbm_wvalid), + .s_axi_app_wready(app_m_axi_hbm_wready), + .s_axi_app_bid(app_m_axi_hbm_bid), + .s_axi_app_bresp(app_m_axi_hbm_bresp), + .s_axi_app_buser(app_m_axi_hbm_buser), + .s_axi_app_bvalid(app_m_axi_hbm_bvalid), + .s_axi_app_bready(app_m_axi_hbm_bready), + .s_axi_app_arid(app_m_axi_hbm_arid), + .s_axi_app_araddr(app_m_axi_hbm_araddr), + .s_axi_app_arlen(app_m_axi_hbm_arlen), + .s_axi_app_arsize(app_m_axi_hbm_arsize), + .s_axi_app_arburst(app_m_axi_hbm_arburst), + .s_axi_app_arlock(app_m_axi_hbm_arlock), + .s_axi_app_arcache(app_m_axi_hbm_arcache), + .s_axi_app_arprot(app_m_axi_hbm_arprot), + .s_axi_app_arqos(app_m_axi_hbm_arqos), + .s_axi_app_aruser(app_m_axi_hbm_aruser), + .s_axi_app_arvalid(app_m_axi_hbm_arvalid), + .s_axi_app_arready(app_m_axi_hbm_arready), + .s_axi_app_rid(app_m_axi_hbm_rid), + .s_axi_app_rdata(app_m_axi_hbm_rdata), + .s_axi_app_rresp(app_m_axi_hbm_rresp), + .s_axi_app_rlast(app_m_axi_hbm_rlast), + .s_axi_app_ruser(app_m_axi_hbm_ruser), + .s_axi_app_rvalid(app_m_axi_hbm_rvalid), + .s_axi_app_rready(app_m_axi_hbm_rready), + + .app_status(app_hbm_status) + ); + + assign all_clocks[PORT_COUNT*2 + (DDR_ENABLE ? DDR_CH : 0) +: HBM_CH] = hbm_clk; + +end else begin + + assign m_axi_hbm_awid = 0; + assign m_axi_hbm_awaddr = 0; + assign m_axi_hbm_awlen = 0; + assign m_axi_hbm_awsize = 0; + assign m_axi_hbm_awburst = 0; + assign m_axi_hbm_awlock = 0; + assign m_axi_hbm_awcache = 0; + assign m_axi_hbm_awprot = 0; + assign m_axi_hbm_awqos = 0; + assign m_axi_hbm_awuser = 0; + assign m_axi_hbm_awvalid = 0; + assign m_axi_hbm_wdata = 0; + assign m_axi_hbm_wstrb = 0; + assign m_axi_hbm_wlast = 0; + assign m_axi_hbm_wuser = 0; + assign m_axi_hbm_wvalid = 0; + assign m_axi_hbm_bready = 0; + assign m_axi_hbm_arid = 0; + assign m_axi_hbm_araddr = 0; + assign m_axi_hbm_arlen = 0; + assign m_axi_hbm_arsize = 0; + assign m_axi_hbm_arburst = 0; + assign m_axi_hbm_arlock = 0; + assign m_axi_hbm_arcache = 0; + assign m_axi_hbm_arprot = 0; + assign m_axi_hbm_arqos = 0; + assign m_axi_hbm_aruser = 0; + assign m_axi_hbm_arvalid = 0; + assign m_axi_hbm_rready = 0; + + assign app_hbm_clk = 0; + assign app_hbm_rst = 0; + + assign app_m_axi_hbm_awready = 0; + assign app_m_axi_hbm_wready = 0; + assign app_m_axi_hbm_bid = 0; + assign app_m_axi_hbm_bresp = 0; + assign app_m_axi_hbm_buser = 0; + assign app_m_axi_hbm_bvalid = 0; + assign app_m_axi_hbm_arready = 0; + assign app_m_axi_hbm_rid = 0; + assign app_m_axi_hbm_rdata = 0; + assign app_m_axi_hbm_rresp = 0; + assign app_m_axi_hbm_rlast = 0; + assign app_m_axi_hbm_ruser = 0; + assign app_m_axi_hbm_rvalid = 0; + + assign app_hbm_status = 0; + +end + +endgenerate + // streaming connections to application wire [PORT_COUNT-1:0] app_direct_tx_clk; wire [PORT_COUNT-1:0] app_direct_tx_rst; @@ -2556,7 +3033,6 @@ wire [IF_COUNT*AXIS_IF_RX_DEST_WIDTH-1:0] app_m_axis_if_rx_tdest; wire [IF_COUNT*AXIS_IF_RX_USER_WIDTH-1:0] app_m_axis_if_rx_tuser; generate - genvar m, n; for (n = 0; n < IF_COUNT; n = n + 1) begin : iface @@ -3578,102 +4054,102 @@ if (APP_ENABLE) begin : app /* * DDR */ - .ddr_clk(ddr_clk), - .ddr_rst(ddr_rst), + .ddr_clk(app_ddr_clk), + .ddr_rst(app_ddr_rst), - .m_axi_ddr_awid(m_axi_ddr_awid), - .m_axi_ddr_awaddr(m_axi_ddr_awaddr), - .m_axi_ddr_awlen(m_axi_ddr_awlen), - .m_axi_ddr_awsize(m_axi_ddr_awsize), - .m_axi_ddr_awburst(m_axi_ddr_awburst), - .m_axi_ddr_awlock(m_axi_ddr_awlock), - .m_axi_ddr_awcache(m_axi_ddr_awcache), - .m_axi_ddr_awprot(m_axi_ddr_awprot), - .m_axi_ddr_awqos(m_axi_ddr_awqos), - .m_axi_ddr_awuser(m_axi_ddr_awuser), - .m_axi_ddr_awvalid(m_axi_ddr_awvalid), - .m_axi_ddr_awready(m_axi_ddr_awready), - .m_axi_ddr_wdata(m_axi_ddr_wdata), - .m_axi_ddr_wstrb(m_axi_ddr_wstrb), - .m_axi_ddr_wlast(m_axi_ddr_wlast), - .m_axi_ddr_wuser(m_axi_ddr_wuser), - .m_axi_ddr_wvalid(m_axi_ddr_wvalid), - .m_axi_ddr_wready(m_axi_ddr_wready), - .m_axi_ddr_bid(m_axi_ddr_bid), - .m_axi_ddr_bresp(m_axi_ddr_bresp), - .m_axi_ddr_buser(m_axi_ddr_buser), - .m_axi_ddr_bvalid(m_axi_ddr_bvalid), - .m_axi_ddr_bready(m_axi_ddr_bready), - .m_axi_ddr_arid(m_axi_ddr_arid), - .m_axi_ddr_araddr(m_axi_ddr_araddr), - .m_axi_ddr_arlen(m_axi_ddr_arlen), - .m_axi_ddr_arsize(m_axi_ddr_arsize), - .m_axi_ddr_arburst(m_axi_ddr_arburst), - .m_axi_ddr_arlock(m_axi_ddr_arlock), - .m_axi_ddr_arcache(m_axi_ddr_arcache), - .m_axi_ddr_arprot(m_axi_ddr_arprot), - .m_axi_ddr_arqos(m_axi_ddr_arqos), - .m_axi_ddr_aruser(m_axi_ddr_aruser), - .m_axi_ddr_arvalid(m_axi_ddr_arvalid), - .m_axi_ddr_arready(m_axi_ddr_arready), - .m_axi_ddr_rid(m_axi_ddr_rid), - .m_axi_ddr_rdata(m_axi_ddr_rdata), - .m_axi_ddr_rresp(m_axi_ddr_rresp), - .m_axi_ddr_rlast(m_axi_ddr_rlast), - .m_axi_ddr_ruser(m_axi_ddr_ruser), - .m_axi_ddr_rvalid(m_axi_ddr_rvalid), - .m_axi_ddr_rready(m_axi_ddr_rready), + .m_axi_ddr_awid(app_m_axi_ddr_awid), + .m_axi_ddr_awaddr(app_m_axi_ddr_awaddr), + .m_axi_ddr_awlen(app_m_axi_ddr_awlen), + .m_axi_ddr_awsize(app_m_axi_ddr_awsize), + .m_axi_ddr_awburst(app_m_axi_ddr_awburst), + .m_axi_ddr_awlock(app_m_axi_ddr_awlock), + .m_axi_ddr_awcache(app_m_axi_ddr_awcache), + .m_axi_ddr_awprot(app_m_axi_ddr_awprot), + .m_axi_ddr_awqos(app_m_axi_ddr_awqos), + .m_axi_ddr_awuser(app_m_axi_ddr_awuser), + .m_axi_ddr_awvalid(app_m_axi_ddr_awvalid), + .m_axi_ddr_awready(app_m_axi_ddr_awready), + .m_axi_ddr_wdata(app_m_axi_ddr_wdata), + .m_axi_ddr_wstrb(app_m_axi_ddr_wstrb), + .m_axi_ddr_wlast(app_m_axi_ddr_wlast), + .m_axi_ddr_wuser(app_m_axi_ddr_wuser), + .m_axi_ddr_wvalid(app_m_axi_ddr_wvalid), + .m_axi_ddr_wready(app_m_axi_ddr_wready), + .m_axi_ddr_bid(app_m_axi_ddr_bid), + .m_axi_ddr_bresp(app_m_axi_ddr_bresp), + .m_axi_ddr_buser(app_m_axi_ddr_buser), + .m_axi_ddr_bvalid(app_m_axi_ddr_bvalid), + .m_axi_ddr_bready(app_m_axi_ddr_bready), + .m_axi_ddr_arid(app_m_axi_ddr_arid), + .m_axi_ddr_araddr(app_m_axi_ddr_araddr), + .m_axi_ddr_arlen(app_m_axi_ddr_arlen), + .m_axi_ddr_arsize(app_m_axi_ddr_arsize), + .m_axi_ddr_arburst(app_m_axi_ddr_arburst), + .m_axi_ddr_arlock(app_m_axi_ddr_arlock), + .m_axi_ddr_arcache(app_m_axi_ddr_arcache), + .m_axi_ddr_arprot(app_m_axi_ddr_arprot), + .m_axi_ddr_arqos(app_m_axi_ddr_arqos), + .m_axi_ddr_aruser(app_m_axi_ddr_aruser), + .m_axi_ddr_arvalid(app_m_axi_ddr_arvalid), + .m_axi_ddr_arready(app_m_axi_ddr_arready), + .m_axi_ddr_rid(app_m_axi_ddr_rid), + .m_axi_ddr_rdata(app_m_axi_ddr_rdata), + .m_axi_ddr_rresp(app_m_axi_ddr_rresp), + .m_axi_ddr_rlast(app_m_axi_ddr_rlast), + .m_axi_ddr_ruser(app_m_axi_ddr_ruser), + .m_axi_ddr_rvalid(app_m_axi_ddr_rvalid), + .m_axi_ddr_rready(app_m_axi_ddr_rready), .ddr_status(ddr_status), /* * HBM */ - .hbm_clk(hbm_clk), - .hbm_rst(hbm_rst), + .hbm_clk(app_hbm_clk), + .hbm_rst(app_hbm_rst), - .m_axi_hbm_awid(m_axi_hbm_awid), - .m_axi_hbm_awaddr(m_axi_hbm_awaddr), - .m_axi_hbm_awlen(m_axi_hbm_awlen), - .m_axi_hbm_awsize(m_axi_hbm_awsize), - .m_axi_hbm_awburst(m_axi_hbm_awburst), - .m_axi_hbm_awlock(m_axi_hbm_awlock), - .m_axi_hbm_awcache(m_axi_hbm_awcache), - .m_axi_hbm_awprot(m_axi_hbm_awprot), - .m_axi_hbm_awqos(m_axi_hbm_awqos), - .m_axi_hbm_awuser(m_axi_hbm_awuser), - .m_axi_hbm_awvalid(m_axi_hbm_awvalid), - .m_axi_hbm_awready(m_axi_hbm_awready), - .m_axi_hbm_wdata(m_axi_hbm_wdata), - .m_axi_hbm_wstrb(m_axi_hbm_wstrb), - .m_axi_hbm_wlast(m_axi_hbm_wlast), - .m_axi_hbm_wuser(m_axi_hbm_wuser), - .m_axi_hbm_wvalid(m_axi_hbm_wvalid), - .m_axi_hbm_wready(m_axi_hbm_wready), - .m_axi_hbm_bid(m_axi_hbm_bid), - .m_axi_hbm_bresp(m_axi_hbm_bresp), - .m_axi_hbm_buser(m_axi_hbm_buser), - .m_axi_hbm_bvalid(m_axi_hbm_bvalid), - .m_axi_hbm_bready(m_axi_hbm_bready), - .m_axi_hbm_arid(m_axi_hbm_arid), - .m_axi_hbm_araddr(m_axi_hbm_araddr), - .m_axi_hbm_arlen(m_axi_hbm_arlen), - .m_axi_hbm_arsize(m_axi_hbm_arsize), - .m_axi_hbm_arburst(m_axi_hbm_arburst), - .m_axi_hbm_arlock(m_axi_hbm_arlock), - .m_axi_hbm_arcache(m_axi_hbm_arcache), - .m_axi_hbm_arprot(m_axi_hbm_arprot), - .m_axi_hbm_arqos(m_axi_hbm_arqos), - .m_axi_hbm_aruser(m_axi_hbm_aruser), - .m_axi_hbm_arvalid(m_axi_hbm_arvalid), - .m_axi_hbm_arready(m_axi_hbm_arready), - .m_axi_hbm_rid(m_axi_hbm_rid), - .m_axi_hbm_rdata(m_axi_hbm_rdata), - .m_axi_hbm_rresp(m_axi_hbm_rresp), - .m_axi_hbm_rlast(m_axi_hbm_rlast), - .m_axi_hbm_ruser(m_axi_hbm_ruser), - .m_axi_hbm_rvalid(m_axi_hbm_rvalid), - .m_axi_hbm_rready(m_axi_hbm_rready), + .m_axi_hbm_awid(app_m_axi_hbm_awid), + .m_axi_hbm_awaddr(app_m_axi_hbm_awaddr), + .m_axi_hbm_awlen(app_m_axi_hbm_awlen), + .m_axi_hbm_awsize(app_m_axi_hbm_awsize), + .m_axi_hbm_awburst(app_m_axi_hbm_awburst), + .m_axi_hbm_awlock(app_m_axi_hbm_awlock), + .m_axi_hbm_awcache(app_m_axi_hbm_awcache), + .m_axi_hbm_awprot(app_m_axi_hbm_awprot), + .m_axi_hbm_awqos(app_m_axi_hbm_awqos), + .m_axi_hbm_awuser(app_m_axi_hbm_awuser), + .m_axi_hbm_awvalid(app_m_axi_hbm_awvalid), + .m_axi_hbm_awready(app_m_axi_hbm_awready), + .m_axi_hbm_wdata(app_m_axi_hbm_wdata), + .m_axi_hbm_wstrb(app_m_axi_hbm_wstrb), + .m_axi_hbm_wlast(app_m_axi_hbm_wlast), + .m_axi_hbm_wuser(app_m_axi_hbm_wuser), + .m_axi_hbm_wvalid(app_m_axi_hbm_wvalid), + .m_axi_hbm_wready(app_m_axi_hbm_wready), + .m_axi_hbm_bid(app_m_axi_hbm_bid), + .m_axi_hbm_bresp(app_m_axi_hbm_bresp), + .m_axi_hbm_buser(app_m_axi_hbm_buser), + .m_axi_hbm_bvalid(app_m_axi_hbm_bvalid), + .m_axi_hbm_bready(app_m_axi_hbm_bready), + .m_axi_hbm_arid(app_m_axi_hbm_arid), + .m_axi_hbm_araddr(app_m_axi_hbm_araddr), + .m_axi_hbm_arlen(app_m_axi_hbm_arlen), + .m_axi_hbm_arsize(app_m_axi_hbm_arsize), + .m_axi_hbm_arburst(app_m_axi_hbm_arburst), + .m_axi_hbm_arlock(app_m_axi_hbm_arlock), + .m_axi_hbm_arcache(app_m_axi_hbm_arcache), + .m_axi_hbm_arprot(app_m_axi_hbm_arprot), + .m_axi_hbm_arqos(app_m_axi_hbm_arqos), + .m_axi_hbm_aruser(app_m_axi_hbm_aruser), + .m_axi_hbm_arvalid(app_m_axi_hbm_arvalid), + .m_axi_hbm_arready(app_m_axi_hbm_arready), + .m_axi_hbm_rid(app_m_axi_hbm_rid), + .m_axi_hbm_rdata(app_m_axi_hbm_rdata), + .m_axi_hbm_rresp(app_m_axi_hbm_rresp), + .m_axi_hbm_rlast(app_m_axi_hbm_rlast), + .m_axi_hbm_ruser(app_m_axi_hbm_ruser), + .m_axi_hbm_rvalid(app_m_axi_hbm_rvalid), + .m_axi_hbm_rready(app_m_axi_hbm_rready), .hbm_status(hbm_status), @@ -3837,65 +4313,65 @@ end else begin assign app_m_axis_if_rx_tdest = 0; assign app_m_axis_if_rx_tuser = 0; - assign m_axi_ddr_awid = 0; - assign m_axi_ddr_awaddr = 0; - assign m_axi_ddr_awlen = 0; - assign m_axi_ddr_awsize = 0; - assign m_axi_ddr_awburst = 0; - assign m_axi_ddr_awlock = 0; - assign m_axi_ddr_awcache = 0; - assign m_axi_ddr_awprot = 0; - assign m_axi_ddr_awqos = 0; - assign m_axi_ddr_awuser = 0; - assign m_axi_ddr_awvalid = 0; - assign m_axi_ddr_wdata = 0; - assign m_axi_ddr_wstrb = 0; - assign m_axi_ddr_wlast = 0; - assign m_axi_ddr_wuser = 0; - assign m_axi_ddr_wvalid = 0; - assign m_axi_ddr_bready = 0; - assign m_axi_ddr_arid = 0; - assign m_axi_ddr_araddr = 0; - assign m_axi_ddr_arlen = 0; - assign m_axi_ddr_arsize = 0; - assign m_axi_ddr_arburst = 0; - assign m_axi_ddr_arlock = 0; - assign m_axi_ddr_arcache = 0; - assign m_axi_ddr_arprot = 0; - assign m_axi_ddr_arqos = 0; - assign m_axi_ddr_aruser = 0; - assign m_axi_ddr_arvalid = 0; - assign m_axi_ddr_rready = 0; + assign app_m_axi_ddr_awid = 0; + assign app_m_axi_ddr_awaddr = 0; + assign app_m_axi_ddr_awlen = 0; + assign app_m_axi_ddr_awsize = 0; + assign app_m_axi_ddr_awburst = 0; + assign app_m_axi_ddr_awlock = 0; + assign app_m_axi_ddr_awcache = 0; + assign app_m_axi_ddr_awprot = 0; + assign app_m_axi_ddr_awqos = 0; + assign app_m_axi_ddr_awuser = 0; + assign app_m_axi_ddr_awvalid = 0; + assign app_m_axi_ddr_wdata = 0; + assign app_m_axi_ddr_wstrb = 0; + assign app_m_axi_ddr_wlast = 0; + assign app_m_axi_ddr_wuser = 0; + assign app_m_axi_ddr_wvalid = 0; + assign app_m_axi_ddr_bready = 0; + assign app_m_axi_ddr_arid = 0; + assign app_m_axi_ddr_araddr = 0; + assign app_m_axi_ddr_arlen = 0; + assign app_m_axi_ddr_arsize = 0; + assign app_m_axi_ddr_arburst = 0; + assign app_m_axi_ddr_arlock = 0; + assign app_m_axi_ddr_arcache = 0; + assign app_m_axi_ddr_arprot = 0; + assign app_m_axi_ddr_arqos = 0; + assign app_m_axi_ddr_aruser = 0; + assign app_m_axi_ddr_arvalid = 0; + assign app_m_axi_ddr_rready = 0; - assign m_axi_hbm_awid = 0; - assign m_axi_hbm_awaddr = 0; - assign m_axi_hbm_awlen = 0; - assign m_axi_hbm_awsize = 0; - assign m_axi_hbm_awburst = 0; - assign m_axi_hbm_awlock = 0; - assign m_axi_hbm_awcache = 0; - assign m_axi_hbm_awprot = 0; - assign m_axi_hbm_awqos = 0; - assign m_axi_hbm_awuser = 0; - assign m_axi_hbm_awvalid = 0; - assign m_axi_hbm_wdata = 0; - assign m_axi_hbm_wstrb = 0; - assign m_axi_hbm_wlast = 0; - assign m_axi_hbm_wuser = 0; - assign m_axi_hbm_wvalid = 0; - assign m_axi_hbm_bready = 0; - assign m_axi_hbm_arid = 0; - assign m_axi_hbm_araddr = 0; - assign m_axi_hbm_arlen = 0; - assign m_axi_hbm_arsize = 0; - assign m_axi_hbm_arburst = 0; - assign m_axi_hbm_arlock = 0; - assign m_axi_hbm_arcache = 0; - assign m_axi_hbm_arprot = 0; - assign m_axi_hbm_arqos = 0; - assign m_axi_hbm_aruser = 0; - assign m_axi_hbm_arvalid = 0; - assign m_axi_hbm_rready = 0; + assign app_m_axi_hbm_awid = 0; + assign app_m_axi_hbm_awaddr = 0; + assign app_m_axi_hbm_awlen = 0; + assign app_m_axi_hbm_awsize = 0; + assign app_m_axi_hbm_awburst = 0; + assign app_m_axi_hbm_awlock = 0; + assign app_m_axi_hbm_awcache = 0; + assign app_m_axi_hbm_awprot = 0; + assign app_m_axi_hbm_awqos = 0; + assign app_m_axi_hbm_awuser = 0; + assign app_m_axi_hbm_awvalid = 0; + assign app_m_axi_hbm_wdata = 0; + assign app_m_axi_hbm_wstrb = 0; + assign app_m_axi_hbm_wlast = 0; + assign app_m_axi_hbm_wuser = 0; + assign app_m_axi_hbm_wvalid = 0; + assign app_m_axi_hbm_bready = 0; + assign app_m_axi_hbm_arid = 0; + assign app_m_axi_hbm_araddr = 0; + assign app_m_axi_hbm_arlen = 0; + assign app_m_axi_hbm_arsize = 0; + assign app_m_axi_hbm_arburst = 0; + assign app_m_axi_hbm_arlock = 0; + assign app_m_axi_hbm_arcache = 0; + assign app_m_axi_hbm_arprot = 0; + assign app_m_axi_hbm_arqos = 0; + assign app_m_axi_hbm_aruser = 0; + assign app_m_axi_hbm_arvalid = 0; + assign app_m_axi_hbm_rready = 0; assign axis_app_stat_tdata = 0; assign axis_app_stat_tid = 0; diff --git a/fpga/common/rtl/mqnic_dram_if.v b/fpga/common/rtl/mqnic_dram_if.v new file mode 100644 index 000000000..392175cb7 --- /dev/null +++ b/fpga/common/rtl/mqnic_dram_if.v @@ -0,0 +1,325 @@ +/* + +Copyright 2022, The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + + 1. Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + + 2. Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ''AS +IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE REGENTS OF THE UNIVERSITY OF CALIFORNIA OR +CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT +OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING +IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. + +The views and conclusions contained in the software and documentation are those +of the authors and should not be interpreted as representing official policies, +either expressed or implied, of The Regents of the University of California. + +*/ + +// Language: Verilog 2001 + +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * mqnic DRAM interface + */ +module mqnic_dram_if # +( + // RAM configuration + parameter CH = 1, + parameter GROUP_SIZE = 1, + parameter AXI_DATA_WIDTH = 256, + parameter AXI_ADDR_WIDTH = 32, + parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8), + parameter AXI_ID_WIDTH = 8, + parameter AXI_AWUSER_ENABLE = 0, + parameter AXI_AWUSER_WIDTH = 1, + parameter AXI_WUSER_ENABLE = 0, + parameter AXI_WUSER_WIDTH = 1, + parameter AXI_BUSER_ENABLE = 0, + parameter AXI_BUSER_WIDTH = 1, + parameter AXI_ARUSER_ENABLE = 0, + parameter AXI_ARUSER_WIDTH = 1, + parameter AXI_RUSER_ENABLE = 0, + parameter AXI_RUSER_WIDTH = 1, + parameter AXI_MAX_BURST_LEN = 256, + parameter AXI_NARROW_BURST = 0, + parameter AXI_FIXED_BURST = 0, + parameter AXI_WRAP_BURST = 0 +) +( + input wire clk, + input wire rst, + + /* + * AXI to DRAM + */ + input wire [CH-1:0] m_axi_clk, + input wire [CH-1:0] m_axi_rst, + + output wire [CH*AXI_ID_WIDTH-1:0] m_axi_awid, + output wire [CH*AXI_ADDR_WIDTH-1:0] m_axi_awaddr, + output wire [CH*8-1:0] m_axi_awlen, + output wire [CH*3-1:0] m_axi_awsize, + output wire [CH*2-1:0] m_axi_awburst, + output wire [CH-1:0] m_axi_awlock, + output wire [CH*4-1:0] m_axi_awcache, + output wire [CH*3-1:0] m_axi_awprot, + output wire [CH*4-1:0] m_axi_awqos, + output wire [CH*AXI_AWUSER_WIDTH-1:0] m_axi_awuser, + output wire [CH-1:0] m_axi_awvalid, + input wire [CH-1:0] m_axi_awready, + output wire [CH*AXI_DATA_WIDTH-1:0] m_axi_wdata, + output wire [CH*AXI_STRB_WIDTH-1:0] m_axi_wstrb, + output wire [CH-1:0] m_axi_wlast, + output wire [CH*AXI_WUSER_WIDTH-1:0] m_axi_wuser, + output wire [CH-1:0] m_axi_wvalid, + input wire [CH-1:0] m_axi_wready, + input wire [CH*AXI_ID_WIDTH-1:0] m_axi_bid, + input wire [CH*2-1:0] m_axi_bresp, + input wire [CH*AXI_BUSER_WIDTH-1:0] m_axi_buser, + input wire [CH-1:0] m_axi_bvalid, + output wire [CH-1:0] m_axi_bready, + output wire [CH*AXI_ID_WIDTH-1:0] m_axi_arid, + output wire [CH*AXI_ADDR_WIDTH-1:0] m_axi_araddr, + output wire [CH*8-1:0] m_axi_arlen, + output wire [CH*3-1:0] m_axi_arsize, + output wire [CH*2-1:0] m_axi_arburst, + output wire [CH-1:0] m_axi_arlock, + output wire [CH*4-1:0] m_axi_arcache, + output wire [CH*3-1:0] m_axi_arprot, + output wire [CH*4-1:0] m_axi_arqos, + output wire [CH*AXI_ARUSER_WIDTH-1:0] m_axi_aruser, + output wire [CH-1:0] m_axi_arvalid, + input wire [CH-1:0] m_axi_arready, + input wire [CH*AXI_ID_WIDTH-1:0] m_axi_rid, + input wire [CH*AXI_DATA_WIDTH-1:0] m_axi_rdata, + input wire [CH*2-1:0] m_axi_rresp, + input wire [CH-1:0] m_axi_rlast, + input wire [CH*AXI_RUSER_WIDTH-1:0] m_axi_ruser, + input wire [CH-1:0] m_axi_rvalid, + output wire [CH-1:0] m_axi_rready, + + input wire [CH-1:0] status_in, + + /* + * AXI to application + */ + output wire [CH-1:0] s_axi_app_clk, + output wire [CH-1:0] s_axi_app_rst, + + input wire [CH*AXI_ID_WIDTH-1:0] s_axi_app_awid, + input wire [CH*AXI_ADDR_WIDTH-1:0] s_axi_app_awaddr, + input wire [CH*8-1:0] s_axi_app_awlen, + input wire [CH*3-1:0] s_axi_app_awsize, + input wire [CH*2-1:0] s_axi_app_awburst, + input wire [CH-1:0] s_axi_app_awlock, + input wire [CH*4-1:0] s_axi_app_awcache, + input wire [CH*3-1:0] s_axi_app_awprot, + input wire [CH*4-1:0] s_axi_app_awqos, + input wire [CH*AXI_AWUSER_WIDTH-1:0] s_axi_app_awuser, + input wire [CH-1:0] s_axi_app_awvalid, + output wire [CH-1:0] s_axi_app_awready, + input wire [CH*AXI_DATA_WIDTH-1:0] s_axi_app_wdata, + input wire [CH*AXI_STRB_WIDTH-1:0] s_axi_app_wstrb, + input wire [CH-1:0] s_axi_app_wlast, + input wire [CH*AXI_WUSER_WIDTH-1:0] s_axi_app_wuser, + input wire [CH-1:0] s_axi_app_wvalid, + output wire [CH-1:0] s_axi_app_wready, + output wire [CH*AXI_ID_WIDTH-1:0] s_axi_app_bid, + output wire [CH*2-1:0] s_axi_app_bresp, + output wire [CH*AXI_BUSER_WIDTH-1:0] s_axi_app_buser, + output wire [CH-1:0] s_axi_app_bvalid, + input wire [CH-1:0] s_axi_app_bready, + input wire [CH*AXI_ID_WIDTH-1:0] s_axi_app_arid, + input wire [CH*AXI_ADDR_WIDTH-1:0] s_axi_app_araddr, + input wire [CH*8-1:0] s_axi_app_arlen, + input wire [CH*3-1:0] s_axi_app_arsize, + input wire [CH*2-1:0] s_axi_app_arburst, + input wire [CH-1:0] s_axi_app_arlock, + input wire [CH*4-1:0] s_axi_app_arcache, + input wire [CH*3-1:0] s_axi_app_arprot, + input wire [CH*4-1:0] s_axi_app_arqos, + input wire [CH*AXI_ARUSER_WIDTH-1:0] s_axi_app_aruser, + input wire [CH-1:0] s_axi_app_arvalid, + output wire [CH-1:0] s_axi_app_arready, + output wire [CH*AXI_ID_WIDTH-1:0] s_axi_app_rid, + output wire [CH*AXI_DATA_WIDTH-1:0] s_axi_app_rdata, + output wire [CH*2-1:0] s_axi_app_rresp, + output wire [CH-1:0] s_axi_app_rlast, + output wire [CH*AXI_RUSER_WIDTH-1:0] s_axi_app_ruser, + output wire [CH-1:0] s_axi_app_rvalid, + input wire [CH-1:0] s_axi_app_rready, + + output wire [CH-1:0] app_status +); + +generate + +genvar n; + + for (n = 0; n < CH; n = n + 1) begin : ch + + wire ch_clk = m_axi_clk[n]; + wire ch_rst = m_axi_rst[n]; + + wire [AXI_ID_WIDTH-1:0] axi_ch_awid; + wire [AXI_ADDR_WIDTH-1:0] axi_ch_awaddr; + wire [7:0] axi_ch_awlen; + wire [2:0] axi_ch_awsize; + wire [1:0] axi_ch_awburst; + wire axi_ch_awlock; + wire [3:0] axi_ch_awcache; + wire [2:0] axi_ch_awprot; + wire [3:0] axi_ch_awqos; + wire [AXI_AWUSER_WIDTH-1:0] axi_ch_awuser; + wire axi_ch_awvalid; + wire axi_ch_awready; + wire [AXI_DATA_WIDTH-1:0] axi_ch_wdata; + wire [AXI_STRB_WIDTH-1:0] axi_ch_wstrb; + wire axi_ch_wlast; + wire [AXI_WUSER_WIDTH-1:0] axi_ch_wuser; + wire axi_ch_wvalid; + wire axi_ch_wready; + wire [AXI_ID_WIDTH-1:0] axi_ch_bid; + wire [1:0] axi_ch_bresp; + wire [AXI_BUSER_WIDTH-1:0] axi_ch_buser; + wire axi_ch_bvalid; + wire axi_ch_bready; + wire [AXI_ID_WIDTH-1:0] axi_ch_arid; + wire [AXI_ADDR_WIDTH-1:0] axi_ch_araddr; + wire [7:0] axi_ch_arlen; + wire [2:0] axi_ch_arsize; + wire [1:0] axi_ch_arburst; + wire axi_ch_arlock; + wire [3:0] axi_ch_arcache; + wire [2:0] axi_ch_arprot; + wire [3:0] axi_ch_arqos; + wire [AXI_ARUSER_WIDTH-1:0] axi_ch_aruser; + wire axi_ch_arvalid; + wire axi_ch_arready; + wire [AXI_ID_WIDTH-1:0] axi_ch_rid; + wire [AXI_DATA_WIDTH-1:0] axi_ch_rdata; + wire [1:0] axi_ch_rresp; + wire axi_ch_rlast; + wire [AXI_RUSER_WIDTH-1:0] axi_ch_ruser; + wire axi_ch_rvalid; + wire axi_ch_rready; + + wire ch_status = status_in[n]; + + assign m_axi_awid[n*AXI_ID_WIDTH +: AXI_ID_WIDTH] = axi_ch_awid; + assign m_axi_awaddr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH] = axi_ch_awaddr; + assign m_axi_awlen[n*8 +: 8] = axi_ch_awlen; + assign m_axi_awsize[n*3 +: 3] = axi_ch_awsize; + assign m_axi_awburst[n*2 +: 2] = axi_ch_awburst; + assign m_axi_awlock[n*1 +: 1] = axi_ch_awlock; + assign m_axi_awcache[n*4 +: 4] = axi_ch_awcache; + assign m_axi_awprot[n*3 +: 3] = axi_ch_awprot; + assign m_axi_awqos[n*4 +: 4] = axi_ch_awqos; + assign m_axi_awuser[n*AXI_AWUSER_WIDTH +: AXI_AWUSER_WIDTH] = axi_ch_awuser; + assign m_axi_awvalid[n*1 +: 1] = axi_ch_awvalid; + assign axi_ch_awready = m_axi_awready[n*1 +: 1]; + assign m_axi_wdata[n*AXI_DATA_WIDTH +: AXI_DATA_WIDTH] = axi_ch_wdata; + assign m_axi_wstrb[n*AXI_STRB_WIDTH +: AXI_STRB_WIDTH] = axi_ch_wstrb; + assign m_axi_wlast[n*1 +: 1] = axi_ch_wlast; + assign m_axi_wuser[n*AXI_WUSER_WIDTH +: AXI_WUSER_WIDTH] = axi_ch_wuser; + assign m_axi_wvalid[n*1 +: 1] = axi_ch_wvalid; + assign axi_ch_wready = m_axi_wready[n*1 +: 1]; + assign axi_ch_bid = m_axi_bid[n*AXI_ID_WIDTH +: AXI_ID_WIDTH]; + assign axi_ch_bresp = m_axi_bresp[n*2 +: 2]; + assign axi_ch_buser = m_axi_buser[n*AXI_BUSER_WIDTH +: AXI_BUSER_WIDTH]; + assign axi_ch_bvalid = m_axi_bvalid[n*1 +: 1]; + assign m_axi_bready[n*1 +: 1] = axi_ch_bready; + assign m_axi_arid[n*AXI_ID_WIDTH +: AXI_ID_WIDTH] = axi_ch_arid; + assign m_axi_araddr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH] = axi_ch_araddr; + assign m_axi_arlen[n*8 +: 8] = axi_ch_arlen; + assign m_axi_arsize[n*3 +: 3] = axi_ch_arsize; + assign m_axi_arburst[n*2 +: 2] = axi_ch_arburst; + assign m_axi_arlock[n*1 +: 1] = axi_ch_arlock; + assign m_axi_arcache[n*4 +: 4] = axi_ch_arcache; + assign m_axi_arprot[n*3 +: 3] = axi_ch_arprot; + assign m_axi_arqos[n*4 +: 4] = axi_ch_arqos; + assign m_axi_aruser[n*AXI_ARUSER_WIDTH +: AXI_ARUSER_WIDTH] = axi_ch_aruser; + assign m_axi_arvalid[n*1 +: 1] = axi_ch_arvalid; + assign axi_ch_arready = m_axi_arready[n*1 +: 1]; + assign axi_ch_rid = m_axi_rid[n*AXI_ID_WIDTH +: AXI_ID_WIDTH]; + assign axi_ch_rdata = m_axi_rdata[n*AXI_DATA_WIDTH +: AXI_DATA_WIDTH]; + assign axi_ch_rresp = m_axi_rresp[n*2 +: 2]; + assign axi_ch_rlast = m_axi_rlast[n*1 +: 1]; + assign axi_ch_ruser = m_axi_ruser[n*AXI_RUSER_WIDTH +: AXI_RUSER_WIDTH]; + assign axi_ch_rvalid = m_axi_rvalid[n*1 +: 1]; + assign m_axi_rready[n*1 +: 1] = axi_ch_rready; + + assign s_axi_app_clk[n] = ch_clk; + assign s_axi_app_rst[n] = ch_rst; + + assign axi_ch_awid = s_axi_app_awid[n*AXI_ID_WIDTH +: AXI_ID_WIDTH]; + assign axi_ch_awaddr = s_axi_app_awaddr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH]; + assign axi_ch_awlen = s_axi_app_awlen[n*8 +: 8]; + assign axi_ch_awsize = s_axi_app_awsize[n*3 +: 3]; + assign axi_ch_awburst = s_axi_app_awburst[n*2 +: 2]; + assign axi_ch_awlock = s_axi_app_awlock[n*1 +: 1]; + assign axi_ch_awcache = s_axi_app_awcache[n*4 +: 4]; + assign axi_ch_awprot = s_axi_app_awprot[n*3 +: 3]; + assign axi_ch_awqos = s_axi_app_awqos[n*4 +: 4]; + assign axi_ch_awuser = s_axi_app_awuser[n*AXI_AWUSER_WIDTH +: AXI_AWUSER_WIDTH]; + assign axi_ch_awvalid = s_axi_app_awvalid[n*1 +: 1]; + assign s_axi_app_awready[n*1 +: 1] = axi_ch_awready; + assign axi_ch_wdata = s_axi_app_wdata[n*AXI_DATA_WIDTH +: AXI_DATA_WIDTH]; + assign axi_ch_wstrb = s_axi_app_wstrb[n*AXI_STRB_WIDTH +: AXI_STRB_WIDTH]; + assign axi_ch_wlast = s_axi_app_wlast[n*1 +: 1]; + assign axi_ch_wuser = s_axi_app_wuser[n*AXI_WUSER_WIDTH +: AXI_WUSER_WIDTH]; + assign axi_ch_wvalid = s_axi_app_wvalid[n*1 +: 1]; + assign s_axi_app_wready[n*1 +: 1] = axi_ch_wready; + assign s_axi_app_bid[n*AXI_ID_WIDTH +: AXI_ID_WIDTH] = axi_ch_bid; + assign s_axi_app_bresp[n*2 +: 2] = axi_ch_bresp; + assign s_axi_app_buser[n*AXI_BUSER_WIDTH +: AXI_BUSER_WIDTH] = axi_ch_buser; + assign s_axi_app_bvalid[n*1 +: 1] = axi_ch_bvalid; + assign axi_ch_bready = s_axi_app_bready[n*1 +: 1]; + assign axi_ch_arid = s_axi_app_arid[n*AXI_ID_WIDTH +: AXI_ID_WIDTH]; + assign axi_ch_araddr = s_axi_app_araddr[n*AXI_ADDR_WIDTH +: AXI_ADDR_WIDTH]; + assign axi_ch_arlen = s_axi_app_arlen[n*8 +: 8]; + assign axi_ch_arsize = s_axi_app_arsize[n*3 +: 3]; + assign axi_ch_arburst = s_axi_app_arburst[n*2 +: 2]; + assign axi_ch_arlock = s_axi_app_arlock[n*1 +: 1]; + assign axi_ch_arcache = s_axi_app_arcache[n*4 +: 4]; + assign axi_ch_arprot = s_axi_app_arprot[n*3 +: 3]; + assign axi_ch_arqos = s_axi_app_arqos[n*4 +: 4]; + assign axi_ch_aruser = s_axi_app_aruser[n*AXI_ARUSER_WIDTH +: AXI_ARUSER_WIDTH]; + assign axi_ch_arvalid = s_axi_app_arvalid[n*1 +: 1]; + assign s_axi_app_arready[n*1 +: 1] = axi_ch_arready; + assign s_axi_app_rid[n*AXI_ID_WIDTH +: AXI_ID_WIDTH] = axi_ch_rid; + assign s_axi_app_rdata[n*AXI_DATA_WIDTH +: AXI_DATA_WIDTH] = axi_ch_rdata; + assign s_axi_app_rresp[n*2 +: 2] = axi_ch_rresp; + assign s_axi_app_rlast[n*1 +: 1] = axi_ch_rlast; + assign s_axi_app_ruser[n*AXI_RUSER_WIDTH +: AXI_RUSER_WIDTH] = axi_ch_ruser; + assign s_axi_app_rvalid[n*1 +: 1] = axi_ch_rvalid; + assign axi_ch_rready = s_axi_app_rready[n*1 +: 1]; + + assign app_status[n] = ch_status; + + end + +endgenerate + +endmodule + +`resetall diff --git a/fpga/common/tb/mqnic_core_axi/Makefile b/fpga/common/tb/mqnic_core_axi/Makefile index d2339b66f..ddbb49518 100644 --- a/fpga/common/tb/mqnic_core_axi/Makefile +++ b/fpga/common/tb/mqnic_core_axi/Makefile @@ -40,6 +40,7 @@ TOPLEVEL = $(DUT) MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/mqnic_core.v +VERILOG_SOURCES += ../../rtl/mqnic_dram_if.v VERILOG_SOURCES += ../../rtl/mqnic_interface.v VERILOG_SOURCES += ../../rtl/mqnic_interface_tx.v VERILOG_SOURCES += ../../rtl/mqnic_interface_rx.v diff --git a/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py b/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py index ef28c9c5e..32d23aba4 100644 --- a/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py +++ b/fpga/common/tb/mqnic_core_axi/test_mqnic_core_axi.py @@ -491,6 +491,7 @@ def test_mqnic_core_pcie_axi(request, if_count, ports_per_if, axi_data_width, verilog_sources = [ os.path.join(rtl_dir, f"{dut}.v"), os.path.join(rtl_dir, "mqnic_core.v"), + os.path.join(rtl_dir, "mqnic_dram_if.v"), os.path.join(rtl_dir, "mqnic_interface.v"), os.path.join(rtl_dir, "mqnic_interface_tx.v"), os.path.join(rtl_dir, "mqnic_interface_rx.v"), diff --git a/fpga/common/tb/mqnic_core_pcie_ptile/Makefile b/fpga/common/tb/mqnic_core_pcie_ptile/Makefile index d26d489c9..47a46d6b2 100644 --- a/fpga/common/tb/mqnic_core_pcie_ptile/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_ptile/Makefile @@ -41,6 +41,7 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/mqnic_core.v +VERILOG_SOURCES += ../../rtl/mqnic_dram_if.v VERILOG_SOURCES += ../../rtl/mqnic_interface.v VERILOG_SOURCES += ../../rtl/mqnic_interface_tx.v VERILOG_SOURCES += ../../rtl/mqnic_interface_rx.v diff --git a/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py b/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py index 8f5531c7f..902a02545 100644 --- a/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py +++ b/fpga/common/tb/mqnic_core_pcie_ptile/test_mqnic_core_pcie_ptile.py @@ -690,8 +690,9 @@ def test_mqnic_core_pcie_ptile(request, if_count, ports_per_if, pcie_data_width, verilog_sources = [ os.path.join(rtl_dir, f"{dut}.v"), - os.path.join(rtl_dir, "mqnic_core.v"), os.path.join(rtl_dir, "mqnic_core_pcie.v"), + os.path.join(rtl_dir, "mqnic_core.v"), + os.path.join(rtl_dir, "mqnic_dram_if.v"), os.path.join(rtl_dir, "mqnic_interface.v"), os.path.join(rtl_dir, "mqnic_interface_tx.v"), os.path.join(rtl_dir, "mqnic_interface_rx.v"), diff --git a/fpga/common/tb/mqnic_core_pcie_s10/Makefile b/fpga/common/tb/mqnic_core_pcie_s10/Makefile index 39d464502..0b130e50e 100644 --- a/fpga/common/tb/mqnic_core_pcie_s10/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_s10/Makefile @@ -41,6 +41,7 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/mqnic_core.v +VERILOG_SOURCES += ../../rtl/mqnic_dram_if.v VERILOG_SOURCES += ../../rtl/mqnic_interface.v VERILOG_SOURCES += ../../rtl/mqnic_interface_tx.v VERILOG_SOURCES += ../../rtl/mqnic_interface_rx.v diff --git a/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py b/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py index 0016641bf..7a50a4a78 100644 --- a/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py +++ b/fpga/common/tb/mqnic_core_pcie_s10/test_mqnic_core_pcie_s10.py @@ -638,8 +638,9 @@ def test_mqnic_core_pcie_s10(request, if_count, ports_per_if, pcie_data_width, verilog_sources = [ os.path.join(rtl_dir, f"{dut}.v"), - os.path.join(rtl_dir, "mqnic_core.v"), os.path.join(rtl_dir, "mqnic_core_pcie.v"), + os.path.join(rtl_dir, "mqnic_core.v"), + os.path.join(rtl_dir, "mqnic_dram_if.v"), os.path.join(rtl_dir, "mqnic_interface.v"), os.path.join(rtl_dir, "mqnic_interface_tx.v"), os.path.join(rtl_dir, "mqnic_interface_rx.v"), diff --git a/fpga/common/tb/mqnic_core_pcie_us/Makefile b/fpga/common/tb/mqnic_core_pcie_us/Makefile index b44aaeb47..db3a6d691 100644 --- a/fpga/common/tb/mqnic_core_pcie_us/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_us/Makefile @@ -41,6 +41,7 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/mqnic_core.v +VERILOG_SOURCES += ../../rtl/mqnic_dram_if.v VERILOG_SOURCES += ../../rtl/mqnic_interface.v VERILOG_SOURCES += ../../rtl/mqnic_interface_tx.v VERILOG_SOURCES += ../../rtl/mqnic_interface_rx.v diff --git a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py index 2a6eba7ef..0c6f3a03f 100644 --- a/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py +++ b/fpga/common/tb/mqnic_core_pcie_us/test_mqnic_core_pcie_us.py @@ -712,8 +712,9 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt verilog_sources = [ os.path.join(rtl_dir, f"{dut}.v"), - os.path.join(rtl_dir, "mqnic_core.v"), os.path.join(rtl_dir, "mqnic_core_pcie.v"), + os.path.join(rtl_dir, "mqnic_core.v"), + os.path.join(rtl_dir, "mqnic_dram_if.v"), os.path.join(rtl_dir, "mqnic_interface.v"), os.path.join(rtl_dir, "mqnic_interface_tx.v"), os.path.join(rtl_dir, "mqnic_interface_rx.v"), diff --git a/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile b/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile index 0234b6ca0..d0370c607 100644 --- a/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile +++ b/fpga/common/tb/mqnic_core_pcie_us_tdma/Makefile @@ -41,6 +41,7 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/mqnic_core.v +VERILOG_SOURCES += ../../rtl/mqnic_dram_if.v VERILOG_SOURCES += ../../rtl/mqnic_interface.v VERILOG_SOURCES += ../../rtl/mqnic_interface_tx.v VERILOG_SOURCES += ../../rtl/mqnic_interface_rx.v diff --git a/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py b/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py index ed0d0abb5..5e72fda79 100644 --- a/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py +++ b/fpga/common/tb/mqnic_core_pcie_us_tdma/test_mqnic_core_pcie_us.py @@ -765,8 +765,9 @@ def test_mqnic_core_pcie_us(request, if_count, ports_per_if, axis_pcie_data_widt verilog_sources = [ os.path.join(rtl_dir, f"{dut}.v"), - os.path.join(rtl_dir, "mqnic_core.v"), os.path.join(rtl_dir, "mqnic_core_pcie.v"), + os.path.join(rtl_dir, "mqnic_core.v"), + os.path.join(rtl_dir, "mqnic_dram_if.v"), os.path.join(rtl_dir, "mqnic_interface.v"), os.path.join(rtl_dir, "mqnic_interface_tx.v"), os.path.join(rtl_dir, "mqnic_interface_rx.v"), diff --git a/fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile b/fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile index 5312a4eb9..812615ae1 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/250_SoC/fpga_100g/fpga/Makefile @@ -11,6 +11,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/Makefile index 078aa4bdd..9673599d8 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/250_SoC/fpga_100g/fpga_app_dma_bench/Makefile @@ -11,6 +11,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile index 5332284c2..8fdd0d599 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/Makefile @@ -42,6 +42,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v +VERILOG_SOURCES += ../../rtl/common/mqnic_dram_if.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py index 393a26db7..f9f54614d 100644 --- a/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/250_SoC/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -631,6 +631,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"), os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), + os.path.join(rtl_dir, "common", "mqnic_dram_if.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), diff --git a/fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile b/fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile index f3394d995..a3b7aee1e 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/250_SoC/fpga_25g/fpga/Makefile @@ -11,6 +11,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile index f3394d995..a3b7aee1e 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/250_SoC/fpga_25g/fpga_10g/Makefile @@ -11,6 +11,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile index 573e6e3f9..fa16ef117 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/Makefile @@ -42,6 +42,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v +VERILOG_SOURCES += ../../rtl/common/mqnic_dram_if.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py index 2bdfc1a8f..2ff5c5f3c 100644 --- a/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/250_SoC/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -679,6 +679,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"), os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), + os.path.join(rtl_dir, "common", "mqnic_dram_if.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile index 6ebc8c405..cfad96dae 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga/Makefile @@ -12,6 +12,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/Makefile index 712e90251..47e426b5a 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_app_dma_bench/Makefile @@ -12,6 +12,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile index 6d90698cd..da8487941 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/fpga_tdma/Makefile @@ -12,6 +12,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile index 855d5ad2a..4674d8832 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/Makefile @@ -42,6 +42,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v +VERILOG_SOURCES += ../../rtl/common/mqnic_dram_if.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py index 9bb4e2315..7eeca56dd 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -631,6 +631,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"), os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), + os.path.join(rtl_dir, "common", "mqnic_dram_if.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile index cc62e1d3d..820cca85a 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga/Makefile @@ -12,6 +12,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile index cc62e1d3d..820cca85a 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_10g/Makefile @@ -12,6 +12,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile index d3d9872dc..1206fdcb0 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/fpga_tdma/Makefile @@ -12,6 +12,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile index bc81bf9ff..673fe79ba 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/Makefile @@ -42,6 +42,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v +VERILOG_SOURCES += ../../rtl/common/mqnic_dram_if.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py index df59e4d87..126a0b5d8 100644 --- a/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ADM_PCIE_9V3/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -679,6 +679,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"), os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), + os.path.join(rtl_dir, "common", "mqnic_dram_if.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), diff --git a/fpga/mqnic/AU200/fpga_100g/fpga/Makefile b/fpga/mqnic/AU200/fpga_100g/fpga/Makefile index db0508e28..5f6bc24cf 100644 --- a/fpga/mqnic/AU200/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/AU200/fpga_100g/fpga/Makefile @@ -12,6 +12,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/AU200/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/AU200/fpga_100g/fpga_app_dma_bench/Makefile index 8ad11ffb1..965536f6b 100644 --- a/fpga/mqnic/AU200/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/AU200/fpga_100g/fpga_app_dma_bench/Makefile @@ -12,6 +12,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile index edc3d6b92..5e2f6a2e1 100644 --- a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/Makefile @@ -42,6 +42,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v +VERILOG_SOURCES += ../../rtl/common/mqnic_dram_if.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py index e06f79375..4bbb9d955 100644 --- a/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU200/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -631,6 +631,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"), os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), + os.path.join(rtl_dir, "common", "mqnic_dram_if.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), diff --git a/fpga/mqnic/AU200/fpga_25g/fpga/Makefile b/fpga/mqnic/AU200/fpga_25g/fpga/Makefile index c0b0018c6..3f0da8c98 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/AU200/fpga_25g/fpga/Makefile @@ -12,6 +12,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile index c0b0018c6..3f0da8c98 100644 --- a/fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/AU200/fpga_25g/fpga_10g/Makefile @@ -12,6 +12,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile index 45d778c7a..53bd64077 100644 --- a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/Makefile @@ -42,6 +42,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v +VERILOG_SOURCES += ../../rtl/common/mqnic_dram_if.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py index 3d229c47f..c564391dd 100644 --- a/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU200/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -679,6 +679,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"), os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), + os.path.join(rtl_dir, "common", "mqnic_dram_if.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), diff --git a/fpga/mqnic/AU250/fpga_100g/fpga/Makefile b/fpga/mqnic/AU250/fpga_100g/fpga/Makefile index e5b4c8806..4b797c5ee 100644 --- a/fpga/mqnic/AU250/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/AU250/fpga_100g/fpga/Makefile @@ -12,6 +12,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/AU250/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/AU250/fpga_100g/fpga_app_dma_bench/Makefile index c1d7e580e..ffed238a0 100644 --- a/fpga/mqnic/AU250/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/AU250/fpga_100g/fpga_app_dma_bench/Makefile @@ -12,6 +12,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile index edc3d6b92..5e2f6a2e1 100644 --- a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/Makefile @@ -42,6 +42,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v +VERILOG_SOURCES += ../../rtl/common/mqnic_dram_if.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py index e06f79375..4bbb9d955 100644 --- a/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU250/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -631,6 +631,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"), os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), + os.path.join(rtl_dir, "common", "mqnic_dram_if.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), diff --git a/fpga/mqnic/AU250/fpga_25g/fpga/Makefile b/fpga/mqnic/AU250/fpga_25g/fpga/Makefile index 75b2b1d2f..94e602d74 100644 --- a/fpga/mqnic/AU250/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/AU250/fpga_25g/fpga/Makefile @@ -12,6 +12,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile index 75b2b1d2f..94e602d74 100644 --- a/fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/AU250/fpga_25g/fpga_10g/Makefile @@ -12,6 +12,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile index 45d778c7a..53bd64077 100644 --- a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/Makefile @@ -42,6 +42,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v +VERILOG_SOURCES += ../../rtl/common/mqnic_dram_if.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py index 3d229c47f..c564391dd 100644 --- a/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU250/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -679,6 +679,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"), os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), + os.path.join(rtl_dir, "common", "mqnic_dram_if.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), diff --git a/fpga/mqnic/AU280/fpga_100g/fpga/Makefile b/fpga/mqnic/AU280/fpga_100g/fpga/Makefile index c5ea87b19..90e8e7bb3 100644 --- a/fpga/mqnic/AU280/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/AU280/fpga_100g/fpga/Makefile @@ -11,6 +11,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/AU280/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/AU280/fpga_100g/fpga_app_dma_bench/Makefile index 626af390b..94bb6d7c2 100644 --- a/fpga/mqnic/AU280/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/AU280/fpga_100g/fpga_app_dma_bench/Makefile @@ -11,6 +11,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile index 569e0655f..35bf87365 100644 --- a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/Makefile @@ -42,6 +42,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v +VERILOG_SOURCES += ../../rtl/common/mqnic_dram_if.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py index 3309dfbdb..504b5fca5 100644 --- a/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU280/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -620,6 +620,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"), os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), + os.path.join(rtl_dir, "common", "mqnic_dram_if.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), diff --git a/fpga/mqnic/AU280/fpga_25g/fpga/Makefile b/fpga/mqnic/AU280/fpga_25g/fpga/Makefile index ce306c385..4a55c4945 100644 --- a/fpga/mqnic/AU280/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/AU280/fpga_25g/fpga/Makefile @@ -11,6 +11,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile index ce306c385..4a55c4945 100644 --- a/fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/AU280/fpga_25g/fpga_10g/Makefile @@ -11,6 +11,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile index e71acbfcf..708b32460 100644 --- a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/Makefile @@ -42,6 +42,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v +VERILOG_SOURCES += ../../rtl/common/mqnic_dram_if.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py index e528159cd..b1334e2ee 100644 --- a/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU280/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -668,6 +668,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"), os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), + os.path.join(rtl_dir, "common", "mqnic_dram_if.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), diff --git a/fpga/mqnic/AU50/fpga_100g/fpga/Makefile b/fpga/mqnic/AU50/fpga_100g/fpga/Makefile index 8f7e6f74f..4b04491cb 100644 --- a/fpga/mqnic/AU50/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/AU50/fpga_100g/fpga/Makefile @@ -11,6 +11,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/Makefile index 73aed7cce..61b688549 100644 --- a/fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/AU50/fpga_100g/fpga_app_dma_bench/Makefile @@ -11,6 +11,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile index a2d121a05..b12e06512 100644 --- a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/Makefile @@ -42,6 +42,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v +VERILOG_SOURCES += ../../rtl/common/mqnic_dram_if.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py index 54cff4e59..ee64b3ad3 100644 --- a/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU50/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -574,6 +574,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"), os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), + os.path.join(rtl_dir, "common", "mqnic_dram_if.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), diff --git a/fpga/mqnic/AU50/fpga_25g/fpga/Makefile b/fpga/mqnic/AU50/fpga_25g/fpga/Makefile index 3c5855964..90ea776c6 100644 --- a/fpga/mqnic/AU50/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/AU50/fpga_25g/fpga/Makefile @@ -11,6 +11,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile index 3c5855964..90ea776c6 100644 --- a/fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/AU50/fpga_25g/fpga_10g/Makefile @@ -11,6 +11,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile index 914eda364..457bd74f5 100644 --- a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/Makefile @@ -42,6 +42,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v +VERILOG_SOURCES += ../../rtl/common/mqnic_dram_if.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py index 1d9e17d25..3ea93b233 100644 --- a/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/AU50/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -588,6 +588,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"), os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), + os.path.join(rtl_dir, "common", "mqnic_dram_if.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku040/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku040/Makefile index be3f856e3..ec5e34ec3 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku040/Makefile +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku040/Makefile @@ -11,6 +11,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku060/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku060/Makefile index 879bf9c72..38fd0ed23 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku060/Makefile +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_app_dma_bench_ku060/Makefile @@ -11,6 +11,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile index 1d2914bc9..acba68ea2 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku040/Makefile @@ -11,6 +11,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile index 1980895cc..2acccfa88 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/fpga_ku060/Makefile @@ -11,6 +11,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile index 63de11717..a02464465 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/Makefile @@ -42,6 +42,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v +VERILOG_SOURCES += ../../rtl/common/mqnic_dram_if.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py index 21b23839e..699300301 100644 --- a/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/DNPCIe_40G_KU_LL_2QSFP/fpga/tb/fpga_core/test_fpga_core.py @@ -643,6 +643,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"), os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), + os.path.join(rtl_dir, "common", "mqnic_dram_if.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile index e0afd9fb9..9fa82d72a 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga/Makefile @@ -11,6 +11,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile index e0afd9fb9..9fa82d72a 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_10g/Makefile @@ -11,6 +11,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/Makefile b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/Makefile index 0cec24662..c708876d4 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/fpga_app_dma_bench/Makefile @@ -11,6 +11,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile index 66281cee6..8cc33b4ed 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/Makefile @@ -42,6 +42,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v +VERILOG_SOURCES += ../../rtl/common/mqnic_dram_if.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py index 5c93931d0..23000b8e4 100644 --- a/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/Nexus_K3P_Q/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -683,6 +683,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"), os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), + os.path.join(rtl_dir, "common", "mqnic_dram_if.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/Makefile b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/Makefile index dbd6a9b8d..3099a7449 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga/Makefile @@ -11,6 +11,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/Makefile index dbd6a9b8d..3099a7449 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_10g/Makefile @@ -11,6 +11,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_app_dma_bench/Makefile b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_app_dma_bench/Makefile index 47ed20eff..85f70a285 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/fpga_app_dma_bench/Makefile @@ -11,6 +11,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile index 66281cee6..8cc33b4ed 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/Makefile @@ -42,6 +42,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v +VERILOG_SOURCES += ../../rtl/common/mqnic_dram_if.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py index 2395507aa..7debed726 100644 --- a/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/Nexus_K3P_S/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -583,6 +583,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"), os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), + os.path.join(rtl_dir, "common", "mqnic_dram_if.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga/Makefile b/fpga/mqnic/VCU108/fpga_25g/fpga/Makefile index dc4a597de..a69ba5c7b 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/VCU108/fpga_25g/fpga/Makefile @@ -12,6 +12,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/VCU108/fpga_25g/fpga_10g/Makefile index dc4a597de..a69ba5c7b 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/VCU108/fpga_25g/fpga_10g/Makefile @@ -12,6 +12,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/Makefile b/fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/Makefile index 62b82a392..58920f678 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/VCU108/fpga_25g/fpga_app_dma_bench/Makefile @@ -12,6 +12,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile index a2a5b859b..c401b04e6 100644 --- a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/Makefile @@ -42,6 +42,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v +VERILOG_SOURCES += ../../rtl/common/mqnic_dram_if.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py index d9b416852..0cf362735 100644 --- a/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU108/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -575,6 +575,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"), os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), + os.path.join(rtl_dir, "common", "mqnic_dram_if.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), diff --git a/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile b/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile index e204f6dd5..5e03e55a8 100644 --- a/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/VCU118/fpga_100g/fpga/Makefile @@ -12,6 +12,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/VCU118/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/VCU118/fpga_100g/fpga_app_dma_bench/Makefile index ee2866d6b..fc8e1ba05 100644 --- a/fpga/mqnic/VCU118/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/VCU118/fpga_100g/fpga_app_dma_bench/Makefile @@ -12,6 +12,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile index 7adfe634e..c09b020ed 100644 --- a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/Makefile @@ -42,6 +42,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v +VERILOG_SOURCES += ../../rtl/common/mqnic_dram_if.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py index 350895e1a..8286652b2 100644 --- a/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU118/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -635,6 +635,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"), os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), + os.path.join(rtl_dir, "common", "mqnic_dram_if.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile b/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile index 980d43781..b14df3f0a 100644 --- a/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/VCU118/fpga_25g/fpga/Makefile @@ -12,6 +12,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile index 980d43781..b14df3f0a 100644 --- a/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/VCU118/fpga_25g/fpga_10g/Makefile @@ -12,6 +12,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile index c82531d25..ca54ce532 100644 --- a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/Makefile @@ -42,6 +42,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v +VERILOG_SOURCES += ../../rtl/common/mqnic_dram_if.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py index 5a12c0ffe..ec4db5639 100644 --- a/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU118/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -683,6 +683,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"), os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), + os.path.join(rtl_dir, "common", "mqnic_dram_if.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), diff --git a/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile b/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile index 95a428c86..1aa375796 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/VCU1525/fpga_100g/fpga/Makefile @@ -12,6 +12,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/VCU1525/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/VCU1525/fpga_100g/fpga_app_dma_bench/Makefile index f3b91e404..aaa739263 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/VCU1525/fpga_100g/fpga_app_dma_bench/Makefile @@ -12,6 +12,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile index edc3d6b92..5e2f6a2e1 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/Makefile @@ -42,6 +42,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v +VERILOG_SOURCES += ../../rtl/common/mqnic_dram_if.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py index 8b3fefa1c..0acd7218d 100644 --- a/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU1525/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -629,6 +629,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"), os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), + os.path.join(rtl_dir, "common", "mqnic_dram_if.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile b/fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile index 8e4c7a88d..6a003ddd7 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/VCU1525/fpga_25g/fpga/Makefile @@ -12,6 +12,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile index 8e4c7a88d..6a003ddd7 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/VCU1525/fpga_25g/fpga_10g/Makefile @@ -12,6 +12,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile index 45d778c7a..53bd64077 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/Makefile @@ -42,6 +42,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v +VERILOG_SOURCES += ../../rtl/common/mqnic_dram_if.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py index 08a78e029..f31385422 100644 --- a/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/VCU1525/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -677,6 +677,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"), os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), + os.path.join(rtl_dir, "common", "mqnic_dram_if.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), diff --git a/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile b/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile index 5abf7e8d0..5d136bef0 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_100g/fpga/Makefile @@ -11,6 +11,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/Makefile index 23d6d858a..3eba8b091 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_100g/fpga_app_dma_bench/Makefile @@ -11,6 +11,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile index 534899c1e..fa4266040 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/Makefile @@ -42,6 +42,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v +VERILOG_SOURCES += ../../rtl/common/mqnic_dram_if.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py index a376a6843..01d1d1e0d 100644 --- a/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/XUPP3R/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -711,6 +711,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"), os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), + os.path.join(rtl_dir, "common", "mqnic_dram_if.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile index 0a12528b3..662445043 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga/Makefile @@ -11,6 +11,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile index 0a12528b3..662445043 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_25g/fpga_10g/Makefile @@ -11,6 +11,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile index b95f4843a..8dc256bcc 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/Makefile @@ -42,6 +42,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v +VERILOG_SOURCES += ../../rtl/common/mqnic_dram_if.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py index 0a380da26..fe032466c 100644 --- a/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/XUPP3R/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -827,6 +827,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"), os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), + os.path.join(rtl_dir, "common", "mqnic_dram_if.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), diff --git a/fpga/mqnic/ZCU102/fpga/fpga/Makefile b/fpga/mqnic/ZCU102/fpga/fpga/Makefile index b78410ace..a834163cb 100644 --- a/fpga/mqnic/ZCU102/fpga/fpga/Makefile +++ b/fpga/mqnic/ZCU102/fpga/fpga/Makefile @@ -10,6 +10,7 @@ SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/common/mqnic_core_axi.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/ZCU102/fpga/fpga_app_dma_bench/Makefile b/fpga/mqnic/ZCU102/fpga/fpga_app_dma_bench/Makefile index aa66a5298..3a899c053 100644 --- a/fpga/mqnic/ZCU102/fpga/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/ZCU102/fpga/fpga_app_dma_bench/Makefile @@ -10,6 +10,7 @@ SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/common/mqnic_core_axi.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile index bbd5f083d..fc8577791 100644 --- a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile +++ b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/Makefile @@ -41,6 +41,7 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/common/mqnic_core_axi.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v +VERILOG_SOURCES += ../../rtl/common/mqnic_dram_if.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py index 8ce9e128f..b65336b70 100644 --- a/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ZCU102/fpga/tb/fpga_core/test_fpga_core.py @@ -383,6 +383,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, f"{dut}.v"), os.path.join(rtl_dir, "common", "mqnic_core_axi.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), + os.path.join(rtl_dir, "common", "mqnic_dram_if.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), diff --git a/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile b/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile index 365221d55..c80c935a4 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile +++ b/fpga/mqnic/ZCU106/fpga_pcie/fpga/Makefile @@ -12,6 +12,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/ZCU106/fpga_pcie/fpga_app_dma_bench/Makefile b/fpga/mqnic/ZCU106/fpga_pcie/fpga_app_dma_bench/Makefile index b0aa15573..48c35c9d2 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/ZCU106/fpga_pcie/fpga_app_dma_bench/Makefile @@ -12,6 +12,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile index 4af112e62..e0b926b18 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile +++ b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/Makefile @@ -42,6 +42,7 @@ VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v +VERILOG_SOURCES += ../../rtl/common/mqnic_dram_if.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py index b0baa48ac..3e8c7f53e 100644 --- a/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ZCU106/fpga_pcie/tb/fpga_core/test_fpga_core.py @@ -577,6 +577,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"), os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), + os.path.join(rtl_dir, "common", "mqnic_dram_if.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile index 312d205b3..a2584c1b1 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga/Makefile @@ -10,6 +10,7 @@ SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/common/mqnic_core_axi.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga_app_dma_bench/Makefile b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga_app_dma_bench/Makefile index 2532d8904..d9438ce7c 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/fpga_app_dma_bench/Makefile @@ -10,6 +10,7 @@ SYN_FILES += rtl/fpga_core.v SYN_FILES += rtl/debounce_switch.v SYN_FILES += rtl/common/mqnic_core_axi.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile index bbd5f083d..fc8577791 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/Makefile @@ -41,6 +41,7 @@ MODULE = test_$(DUT) VERILOG_SOURCES += ../../rtl/$(DUT).v VERILOG_SOURCES += ../../rtl/common/mqnic_core_axi.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v +VERILOG_SOURCES += ../../rtl/common/mqnic_dram_if.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py index 9c3c61c61..aade157c5 100644 --- a/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/ZCU106/fpga_zynqmp/tb/fpga_core/test_fpga_core.py @@ -353,6 +353,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, f"{dut}.v"), os.path.join(rtl_dir, "common", "mqnic_core_axi.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), + os.path.join(rtl_dir, "common", "mqnic_dram_if.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile index f2aea2f9e..64a351a3c 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga/Makefile @@ -13,6 +13,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile index 8ae182cfa..9e48be492 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_dma_bench/Makefile @@ -13,6 +13,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile index bad6fb5e6..8551e1b80 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_app_template/Makefile @@ -13,6 +13,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile index 78df115fc..da3d649f5 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga_tdma/Makefile @@ -13,6 +13,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile index eaeefaefd..f4ac0d8c2 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile +++ b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/Makefile @@ -43,6 +43,7 @@ VERILOG_SOURCES += ../../rtl/bmc_spi.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v +VERILOG_SOURCES += ../../rtl/common/mqnic_dram_if.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py index a665ad129..5b6ddb1ca 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/fb2CG/fpga_100g/tb/fpga_core/test_fpga_core.py @@ -633,6 +633,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"), os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), + os.path.join(rtl_dir, "common", "mqnic_dram_if.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"), diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile index a2e7f63ac..2354807f7 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga/Makefile @@ -13,6 +13,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile index a2e7f63ac..2354807f7 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_10g/Makefile @@ -13,6 +13,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile index b03cfd59d..7ef4e865b 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga_tdma/Makefile @@ -13,6 +13,7 @@ SYN_FILES += rtl/sync_signal.v SYN_FILES += rtl/common/mqnic_core_pcie_us.v SYN_FILES += rtl/common/mqnic_core_pcie.v SYN_FILES += rtl/common/mqnic_core.v +SYN_FILES += rtl/common/mqnic_dram_if.v SYN_FILES += rtl/common/mqnic_interface.v SYN_FILES += rtl/common/mqnic_interface_tx.v SYN_FILES += rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile index cae664edd..379b00cec 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile +++ b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/Makefile @@ -43,6 +43,7 @@ VERILOG_SOURCES += ../../rtl/bmc_spi.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v VERILOG_SOURCES += ../../rtl/common/mqnic_core.v +VERILOG_SOURCES += ../../rtl/common/mqnic_dram_if.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_tx.v VERILOG_SOURCES += ../../rtl/common/mqnic_interface_rx.v diff --git a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py index 5a893499a..8491693a7 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py +++ b/fpga/mqnic/fb2CG/fpga_25g/tb/fpga_core/test_fpga_core.py @@ -682,6 +682,7 @@ def test_fpga_core(request): os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"), os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"), os.path.join(rtl_dir, "common", "mqnic_core.v"), + os.path.join(rtl_dir, "common", "mqnic_dram_if.v"), os.path.join(rtl_dir, "common", "mqnic_interface.v"), os.path.join(rtl_dir, "common", "mqnic_interface_tx.v"), os.path.join(rtl_dir, "common", "mqnic_interface_rx.v"),