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fpga/mqnic: Add RAM inference directive to Intel designs

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Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich 2022-08-05 16:27:29 -07:00
parent f3bf63a775
commit 6c6648f114
4 changed files with 8 additions and 0 deletions
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2
fpga/mqnic/DE10_Agilex/fpga_100g/fpga.qsf
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@ -17,6 +17,8 @@ set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHZ
set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON
set_global_assignment -name verilog_allow_ram_inferred_in_generate_loop on
# Clock and reset
set_location_assignment PIN_CU50 -to clk_100_b2a
set_location_assignment PIN_CU24 -to clk_30m72

2
fpga/mqnic/DE10_Agilex/fpga_25g/fpga.qsf
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@ -17,6 +17,8 @@ set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHZ
set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON
set_global_assignment -name verilog_allow_ram_inferred_in_generate_loop on
# Clock and reset
set_location_assignment PIN_CU50 -to clk_100_b2a
set_location_assignment PIN_CU24 -to clk_30m72

2
fpga/mqnic/S10DX_DK/fpga_25g/fpga.qsf
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@ -34,6 +34,8 @@ set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON
set_global_assignment -name verilog_allow_ram_inferred_in_generate_loop on
# Clock and reset
set_location_assignment PIN_E21 -to clk_133m_ddr4_0_p
set_location_assignment PIN_F21 -to clk_133m_ddr4_0_n

2
fpga/mqnic/S10MX_DK/fpga_25g/fpga.qsf
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@ -41,6 +41,8 @@ set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-ST
set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON
set_global_assignment -name verilog_allow_ram_inferred_in_generate_loop on
# Clock and reset
set_location_assignment PIN_BE17 -to "clk_sys_50m_p"
set_location_assignment PIN_BD17 -to "clk_sys_50m_n"