diff --git a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga.qsf b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga.qsf index dbee88f79..a40ab675f 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_100g/fpga.qsf +++ b/fpga/mqnic/DE10_Agilex/fpga_100g/fpga.qsf @@ -17,6 +17,8 @@ set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHZ set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON +set_global_assignment -name verilog_allow_ram_inferred_in_generate_loop on + # Clock and reset set_location_assignment PIN_CU50 -to clk_100_b2a set_location_assignment PIN_CU24 -to clk_30m72 diff --git a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga.qsf b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga.qsf index dbee88f79..a40ab675f 100644 --- a/fpga/mqnic/DE10_Agilex/fpga_25g/fpga.qsf +++ b/fpga/mqnic/DE10_Agilex/fpga_25g/fpga.qsf @@ -17,6 +17,8 @@ set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_125MHZ set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON +set_global_assignment -name verilog_allow_ram_inferred_in_generate_loop on + # Clock and reset set_location_assignment PIN_CU50 -to clk_100_b2a set_location_assignment PIN_CU24 -to clk_30m72 diff --git a/fpga/mqnic/S10DX_DK/fpga_25g/fpga.qsf b/fpga/mqnic/S10DX_DK/fpga_25g/fpga.qsf index d7739ab39..dcc208712 100644 --- a/fpga/mqnic/S10DX_DK/fpga_25g/fpga.qsf +++ b/fpga/mqnic/S10DX_DK/fpga_25g/fpga.qsf @@ -34,6 +34,8 @@ set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON +set_global_assignment -name verilog_allow_ram_inferred_in_generate_loop on + # Clock and reset set_location_assignment PIN_E21 -to clk_133m_ddr4_0_p set_location_assignment PIN_F21 -to clk_133m_ddr4_0_n diff --git a/fpga/mqnic/S10MX_DK/fpga_25g/fpga.qsf b/fpga/mqnic/S10MX_DK/fpga_25g/fpga.qsf index 8e607ebec..0c99b0b87 100644 --- a/fpga/mqnic/S10MX_DK/fpga_25g/fpga.qsf +++ b/fpga/mqnic/S10MX_DK/fpga_25g/fpga.qsf @@ -41,6 +41,8 @@ set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-ST set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON +set_global_assignment -name verilog_allow_ram_inferred_in_generate_loop on + # Clock and reset set_location_assignment PIN_BE17 -to "clk_sys_50m_p" set_location_assignment PIN_BD17 -to "clk_sys_50m_n"