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Add MTU registers to driver
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4e958096b2
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@ -309,6 +309,10 @@ int mqnic_activate_port(struct mqnic_port *port);
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void mqnic_deactivate_port(struct mqnic_port *port);
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u32 mqnic_port_get_rss_mask(struct mqnic_port *port);
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void mqnic_port_set_rss_mask(struct mqnic_port *port, u32 rss_mask);
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u32 mqnic_port_get_tx_mtu(struct mqnic_port *port);
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void mqnic_port_set_tx_mtu(struct mqnic_port *port, u32 mtu);
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u32 mqnic_port_get_rx_mtu(struct mqnic_port *port);
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void mqnic_port_set_rx_mtu(struct mqnic_port *port, u32 mtu);
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// mqnic_ptp.c
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void mqnic_register_phc(struct mqnic_dev *mdev);
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@ -93,6 +93,14 @@ static int mqnic_start_port(struct net_device *ndev)
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priv->tx_ring[k]->tx_queue = netdev_get_tx_queue(ndev, k);
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}
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// configure ports
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for (k = 0; k < priv->port_count; k++)
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{
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// set port MTU
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mqnic_port_set_tx_mtu(priv->ports[k], ndev->mtu+ETH_HLEN);
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mqnic_port_set_rx_mtu(priv->ports[k], ndev->mtu+ETH_HLEN);
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}
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// enable first port
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mqnic_activate_port(priv->ports[0]);
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@ -120,3 +120,22 @@ void mqnic_port_set_rss_mask(struct mqnic_port *port, u32 rss_mask)
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iowrite32(rss_mask, port->hw_addr+MQNIC_PORT_REG_RSS_MASK);
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}
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u32 mqnic_port_get_tx_mtu(struct mqnic_port *port)
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{
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return ioread32(port->hw_addr+MQNIC_PORT_REG_TX_MTU);
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}
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void mqnic_port_set_tx_mtu(struct mqnic_port *port, u32 mtu)
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{
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iowrite32(mtu, port->hw_addr+MQNIC_PORT_REG_TX_MTU);
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}
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u32 mqnic_port_get_rx_mtu(struct mqnic_port *port)
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{
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return ioread32(port->hw_addr+MQNIC_PORT_REG_RX_MTU);
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}
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void mqnic_port_set_rx_mtu(struct mqnic_port *port, u32 mtu)
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{
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iowrite32(mtu, port->hw_addr+MQNIC_PORT_REG_RX_MTU);
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}
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