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Add gigabit MAC module

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Alex Forencich 2015-02-26 19:16:08 -08:00
parent bb31d57921
commit 6dee616834
9 changed files with 1950 additions and 0 deletions
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/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* 1G Ethernet MAC
*/
module eth_mac_1g #
(
parameter ENABLE_PADDING = 1,
parameter MIN_FRAME_LENGTH = 64
)
(
input wire rx_clk,
input wire rx_rst,
input wire tx_clk,
input wire tx_rst,
/*
* AXI input
*/
input wire [7:0] tx_axis_tdata,
input wire tx_axis_tvalid,
output wire tx_axis_tready,
input wire tx_axis_tlast,
input wire tx_axis_tuser,
/*
* AXI output
*/
output wire [7:0] rx_axis_tdata,
output wire rx_axis_tvalid,
output wire rx_axis_tlast,
output wire rx_axis_tuser,
/*
* GMII interface
*/
input wire [7:0] gmii_rxd,
input wire gmii_rx_dv,
input wire gmii_rx_er,
output wire [7:0] gmii_txd,
output wire gmii_tx_en,
output wire gmii_tx_er,
/*
* Status
*/
output wire rx_error_bad_frame,
output wire rx_error_bad_fcs,
/*
* Configuration
*/
input wire [7:0] ifg_delay
);
eth_mac_1g_rx
eth_mac_1g_rx_inst (
.clk(rx_clk),
.rst(rx_rst),
.gmii_rxd(gmii_rxd),
.gmii_rx_dv(gmii_rx_dv),
.gmii_rx_er(gmii_rx_er),
.output_axis_tdata(rx_axis_tdata),
.output_axis_tvalid(rx_axis_tvalid),
.output_axis_tlast(rx_axis_tlast),
.output_axis_tuser(rx_axis_tuser),
.error_bad_frame(rx_error_bad_frame),
.error_bad_fcs(rx_error_bad_fcs)
);
eth_mac_1g_tx #(
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
)
eth_mac_1g_tx_inst (
.clk(tx_clk),
.rst(tx_rst),
.input_axis_tdata(tx_axis_tdata),
.input_axis_tvalid(tx_axis_tvalid),
.input_axis_tready(tx_axis_tready),
.input_axis_tlast(tx_axis_tlast),
.input_axis_tuser(tx_axis_tuser),
.gmii_txd(gmii_txd),
.gmii_tx_en(gmii_tx_en),
.gmii_tx_er(gmii_tx_er),
.ifg_delay(ifg_delay)
);
endmodule

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/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* 1G Ethernet MAC
*/
module eth_mac_1g_rx
(
input wire clk,
input wire rst,
/*
* GMII input
*/
input wire [7:0] gmii_rxd,
input wire gmii_rx_dv,
input wire gmii_rx_er,
/*
* AXI output
*/
output wire [7:0] output_axis_tdata,
output wire output_axis_tvalid,
output wire output_axis_tlast,
output wire output_axis_tuser,
/*
* Status
*/
output wire error_bad_frame,
output wire error_bad_fcs
);
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_PAYLOAD = 3'd1;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg reset_crc;
reg update_crc;
reg [7:0] frame_ptr_reg = 0, frame_ptr_next;
reg [7:0] gmii_rxd_d0 = 0;
reg [7:0] gmii_rxd_d1 = 0;
reg [7:0] gmii_rxd_d2 = 0;
reg [7:0] gmii_rxd_d3 = 0;
reg [7:0] gmii_rxd_d4 = 0;
reg gmii_rx_dv_d0 = 0;
reg gmii_rx_dv_d1 = 0;
reg gmii_rx_dv_d2 = 0;
reg gmii_rx_dv_d3 = 0;
reg gmii_rx_dv_d4 = 0;
reg gmii_rx_er_d0 = 0;
reg gmii_rx_er_d1 = 0;
reg gmii_rx_er_d2 = 0;
reg gmii_rx_er_d3 = 0;
reg gmii_rx_er_d4 = 0;
reg [7:0] output_axis_tdata_reg = 0, output_axis_tdata_next;
reg output_axis_tvalid_reg = 0, output_axis_tvalid_next;
reg output_axis_tlast_reg = 0, output_axis_tlast_next;
reg output_axis_tuser_reg = 0, output_axis_tuser_next;
reg error_bad_frame_reg = 0, error_bad_frame_next;
reg error_bad_fcs_reg = 0, error_bad_fcs_next;
reg [31:0] crc_state = 32'hFFFFFFFF;
wire [31:0] crc_next;
assign output_axis_tdata = output_axis_tdata_reg;
assign output_axis_tvalid = output_axis_tvalid_reg;
assign output_axis_tlast = output_axis_tlast_reg;
assign output_axis_tuser = output_axis_tuser_reg;
assign error_bad_frame = error_bad_frame_reg;
assign error_bad_fcs = error_bad_fcs_reg;
eth_crc_8
eth_crc_8_inst (
.data_in(gmii_rxd_d4),
.crc_state(crc_state),
.crc_next(crc_next)
);
always @* begin
state_next = STATE_IDLE;
reset_crc = 0;
update_crc = 0;
frame_ptr_next = frame_ptr_reg;
output_axis_tdata_next = 0;
output_axis_tvalid_next = 0;
output_axis_tlast_next = 0;
output_axis_tuser_next = 0;
error_bad_frame_next = 0;
error_bad_fcs_next = 0;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for packet
reset_crc = 1;
if (gmii_rx_dv_d4 && ~gmii_rx_er_d4 && gmii_rxd_d4 == 8'hD5) begin
state_next = STATE_PAYLOAD;
end else begin
state_next = STATE_IDLE;
end
end
STATE_PAYLOAD: begin
// read payload
update_crc = 1;
output_axis_tdata_next = gmii_rxd_d4;
output_axis_tvalid_next = 1;
if (gmii_rx_er) begin
// error
output_axis_tlast_next = 1;
output_axis_tuser_next = 1;
error_bad_frame_next = 1;
state_next = STATE_IDLE;
end if (~gmii_rx_dv) begin
// end of packet
output_axis_tlast_next = 1;
if ({gmii_rxd_d0, gmii_rxd_d1, gmii_rxd_d2, gmii_rxd_d3} == ~crc_next) begin
// FCS good
output_axis_tuser_next = 0;
end else begin
// FCS bad
output_axis_tuser_next = 1;
error_bad_frame_next = 1;
error_bad_fcs_next = 1;
end
state_next = STATE_IDLE;
end else begin
state_next = STATE_PAYLOAD;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
frame_ptr_reg <= 0;
output_axis_tdata_reg <= 0;
output_axis_tvalid_reg <= 0;
output_axis_tlast_reg <= 0;
output_axis_tuser_reg <= 0;
error_bad_frame_reg <= 0;
error_bad_fcs_reg <= 0;
crc_state <= 32'hFFFFFFFF;
end else begin
state_reg <= state_next;
frame_ptr_reg <= frame_ptr_next;
output_axis_tdata_reg <= output_axis_tdata_next;
output_axis_tvalid_reg <= output_axis_tvalid_next;
output_axis_tlast_reg <= output_axis_tlast_next;
output_axis_tuser_reg <= output_axis_tuser_next;
error_bad_frame_reg <= error_bad_frame_next;
error_bad_fcs_reg <= error_bad_fcs_next;
// datapath
if (reset_crc) begin
crc_state <= 32'hFFFFFFFF;
end else if (update_crc) begin
crc_state <= crc_next;
end
end
// delay input
gmii_rxd_d0 <= gmii_rxd;
gmii_rxd_d1 <= gmii_rxd_d0;
gmii_rxd_d2 <= gmii_rxd_d1;
gmii_rxd_d3 <= gmii_rxd_d2;
gmii_rxd_d4 <= gmii_rxd_d3;
gmii_rx_dv_d0 <= gmii_rx_dv;
gmii_rx_dv_d1 <= gmii_rx_dv_d0;
gmii_rx_dv_d2 <= gmii_rx_dv_d1;
gmii_rx_dv_d3 <= gmii_rx_dv_d2;
gmii_rx_dv_d4 <= gmii_rx_dv_d3;
gmii_rx_er_d0 <= gmii_rx_er;
gmii_rx_er_d1 <= gmii_rx_er_d0;
gmii_rx_er_d2 <= gmii_rx_er_d1;
gmii_rx_er_d3 <= gmii_rx_er_d2;
gmii_rx_er_d4 <= gmii_rx_er_d3;
end
endmodule

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/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* 1G Ethernet MAC
*/
module eth_mac_1g_tx #
(
parameter ENABLE_PADDING = 1,
parameter MIN_FRAME_LENGTH = 64
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [7:0] input_axis_tdata,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* GMII output
*/
output wire [7:0] gmii_txd,
output wire gmii_tx_en,
output wire gmii_tx_er,
/*
* Configuration
*/
input wire [7:0] ifg_delay
);
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_PREAMBLE = 3'd1,
STATE_PAYLOAD = 3'd2,
STATE_PAD = 3'd3,
STATE_FCS = 3'd4,
STATE_IFG = 3'd5;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg reset_crc;
reg update_crc;
reg [7:0] frame_ptr_reg = 0, frame_ptr_next;
reg [7:0] gmii_txd_reg = 0, gmii_txd_next;
reg gmii_tx_en_reg = 0, gmii_tx_en_next;
reg gmii_tx_er_reg = 0, gmii_tx_er_next;
reg input_axis_tready_reg = 0, input_axis_tready_next;
reg [31:0] crc_state = 32'hFFFFFFFF;
wire [31:0] crc_next;
assign input_axis_tready = input_axis_tready_reg;
assign gmii_txd = gmii_txd_reg;
assign gmii_tx_en = gmii_tx_en_reg;
assign gmii_tx_er = gmii_tx_er_reg;
eth_crc_8
eth_crc_8_inst (
.data_in(gmii_txd_next),
.crc_state(crc_state),
.crc_next(crc_next)
);
always @* begin
state_next = STATE_IDLE;
reset_crc = 0;
update_crc = 0;
frame_ptr_next = frame_ptr_reg;
input_axis_tready_next = 0;
gmii_txd_next = 0;
gmii_tx_en_next = 0;
gmii_tx_er_next = 0;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for packet
reset_crc = 1;
if (input_axis_tvalid) begin
frame_ptr_next = 1;
gmii_txd_next = 8'h55; // Preamble
gmii_tx_en_next = 1;
state_next = STATE_PREAMBLE;
end else begin
state_next = STATE_IDLE;
end
end
STATE_PREAMBLE: begin
// send preamble
reset_crc = 1;
frame_ptr_next = frame_ptr_reg + 1;
gmii_txd_next = 8'h55; // Preamble
gmii_tx_en_next = 1;
if (frame_ptr_reg == 7) begin
// end of preamble; start payload
frame_ptr_next = 0;
input_axis_tready_next = 1;
gmii_txd_next = 8'hD5; // SFD
state_next = STATE_PAYLOAD;
end else begin
state_next = STATE_PREAMBLE;
end
end
STATE_PAYLOAD: begin
// send payload
update_crc = 1;
input_axis_tready_next = 1;
frame_ptr_next = frame_ptr_reg + 1;
gmii_txd_next = input_axis_tdata;
gmii_tx_en_next = 1;
if (input_axis_tvalid) begin
if (input_axis_tlast) begin
input_axis_tready_next = 0;
if (input_axis_tuser) begin
gmii_tx_er_next = 1;
frame_ptr_next = 0;
state_next = STATE_IFG;
end else begin
if (ENABLE_PADDING && frame_ptr_reg < MIN_FRAME_LENGTH-5) begin
state_next = STATE_PAD;
end else begin
frame_ptr_next = 0;
state_next = STATE_FCS;
end
end
end else begin
state_next = STATE_PAYLOAD;
end
end else begin
gmii_tx_er_next = 1;
frame_ptr_next = 0;
state_next = STATE_IFG;
end
end
STATE_PAD: begin
// send padding
update_crc = 1;
frame_ptr_next = frame_ptr_reg + 1;
gmii_txd_next = 0;
gmii_tx_en_next = 1;
if (frame_ptr_reg < MIN_FRAME_LENGTH-5) begin
state_next = STATE_PAD;
end else begin
frame_ptr_next = 0;
state_next = STATE_FCS;
end
end
STATE_FCS: begin
// send FCS
frame_ptr_next = frame_ptr_reg + 1;
case (frame_ptr_reg)
2'd0: gmii_txd_next = ~crc_state[7:0];
2'd1: gmii_txd_next = ~crc_state[15:8];
2'd2: gmii_txd_next = ~crc_state[23:16];
2'd3: gmii_txd_next = ~crc_state[31:24];
endcase
gmii_tx_en_next = 1;
if (frame_ptr_reg < 3) begin
state_next = STATE_FCS;
end else begin
frame_ptr_next = 0;
state_next = STATE_IFG;
end
end
STATE_IFG: begin
// send IFG
frame_ptr_next = frame_ptr_reg + 1;
reset_crc = 1;
if (frame_ptr_reg < ifg_delay-1) begin
state_next = STATE_IFG;
end else begin
state_next = STATE_IDLE;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
frame_ptr_reg <= 0;
input_axis_tready_reg <= 0;
gmii_txd_reg <= 0;
gmii_tx_en_reg <= 0;
gmii_tx_er_reg <= 0;
crc_state <= 32'hFFFFFFFF;
end else begin
state_reg <= state_next;
frame_ptr_reg <= frame_ptr_next;
input_axis_tready_reg <= input_axis_tready_next;
gmii_txd_reg <= gmii_txd_next;
gmii_tx_en_reg <= gmii_tx_en_next;
gmii_tx_er_reg <= gmii_tx_er_next;
// datapath
if (reset_crc) begin
crc_state <= 32'hFFFFFFFF;
end else if (update_crc) begin
crc_state <= crc_next;
end
end
end
endmodule

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#!/usr/bin/env python2
"""
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
"""
from myhdl import *
import os
from Queue import Queue
import axis_ep
import eth_ep
import gmii_ep
module = 'eth_mac_1g'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/eth_crc_8.v")
srcs.append("../rtl/eth_mac_1g_rx.v")
srcs.append("../rtl/eth_mac_1g_tx.v")
srcs.append("test_%s.v" % module)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_eth_mac_1g(clk,
rst,
current_test,
rx_clk,
rx_rst,
tx_clk,
tx_rst,
tx_axis_tdata,
tx_axis_tvalid,
tx_axis_tready,
tx_axis_tlast,
tx_axis_tuser,
rx_axis_tdata,
rx_axis_tvalid,
rx_axis_tlast,
rx_axis_tuser,
gmii_rxd,
gmii_rx_dv,
gmii_rx_er,
gmii_txd,
gmii_tx_en,
gmii_tx_er,
rx_error_bad_frame,
rx_error_bad_fcs,
ifg_delay):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
rx_clk=rx_clk,
rx_rst=rx_rst,
tx_clk=tx_clk,
tx_rst=tx_rst,
tx_axis_tdata=tx_axis_tdata,
tx_axis_tvalid=tx_axis_tvalid,
tx_axis_tready=tx_axis_tready,
tx_axis_tlast=tx_axis_tlast,
tx_axis_tuser=tx_axis_tuser,
rx_axis_tdata=rx_axis_tdata,
rx_axis_tvalid=rx_axis_tvalid,
rx_axis_tlast=rx_axis_tlast,
rx_axis_tuser=rx_axis_tuser,
gmii_rxd=gmii_rxd,
gmii_rx_dv=gmii_rx_dv,
gmii_rx_er=gmii_rx_er,
gmii_txd=gmii_txd,
gmii_tx_en=gmii_tx_en,
gmii_tx_er=gmii_tx_er,
rx_error_bad_frame=rx_error_bad_frame,
rx_error_bad_fcs=rx_error_bad_fcs,
ifg_delay=ifg_delay)
def bench():
# Parameters
ENABLE_PADDING = 1
MIN_FRAME_LENGTH = 64
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
rx_clk = Signal(bool(0))
rx_rst = Signal(bool(0))
tx_clk = Signal(bool(0))
tx_rst = Signal(bool(0))
tx_axis_tdata = Signal(intbv(0)[8:])
tx_axis_tvalid = Signal(bool(0))
tx_axis_tlast = Signal(bool(0))
tx_axis_tuser = Signal(bool(0))
gmii_rxd = Signal(intbv(0)[8:])
gmii_rx_dv = Signal(bool(0))
gmii_rx_er = Signal(bool(0))
ifg_delay = Signal(intbv(0)[8:])
# Outputs
tx_axis_tready = Signal(bool(0))
rx_axis_tdata = Signal(intbv(0)[8:])
rx_axis_tvalid = Signal(bool(0))
rx_axis_tlast = Signal(bool(0))
rx_axis_tuser = Signal(bool(0))
gmii_txd = Signal(intbv(0)[8:])
gmii_tx_en = Signal(bool(0))
gmii_tx_er = Signal(bool(0))
rx_error_bad_frame = Signal(bool(0))
rx_error_bad_fcs = Signal(bool(0))
# sources and sinks
gmii_source_queue = Queue()
gmii_sink_queue = Queue()
axis_source_queue = Queue()
axis_source_pause = Signal(bool(0))
axis_sink_queue = Queue()
gmii_source = gmii_ep.GMIISource(rx_clk,
rx_rst,
txd=gmii_rxd,
tx_en=gmii_rx_dv,
tx_er=gmii_rx_er,
fifo=gmii_source_queue,
name='gmii_source')
gmii_sink = gmii_ep.GMIISink(tx_clk,
tx_rst,
rxd=gmii_txd,
rx_dv=gmii_tx_en,
rx_er=gmii_tx_er,
fifo=gmii_sink_queue,
name='gmii_sink')
axis_source = axis_ep.AXIStreamSource(tx_clk,
tx_rst,
tdata=tx_axis_tdata,
tvalid=tx_axis_tvalid,
tready=tx_axis_tready,
tlast=tx_axis_tlast,
tuser=tx_axis_tuser,
fifo=axis_source_queue,
pause=axis_source_pause,
name='axis_source')
axis_sink = axis_ep.AXIStreamSink(rx_clk,
rx_rst,
tdata=rx_axis_tdata,
tvalid=rx_axis_tvalid,
tlast=rx_axis_tlast,
tuser=rx_axis_tuser,
fifo=axis_sink_queue,
name='axis_sink')
# DUT
dut = dut_eth_mac_1g(clk,
rst,
current_test,
rx_clk,
rx_rst,
tx_clk,
tx_rst,
tx_axis_tdata,
tx_axis_tvalid,
tx_axis_tready,
tx_axis_tlast,
tx_axis_tuser,
rx_axis_tdata,
rx_axis_tvalid,
rx_axis_tlast,
rx_axis_tuser,
gmii_rxd,
gmii_rx_dv,
gmii_rx_er,
gmii_txd,
gmii_tx_en,
gmii_tx_er,
rx_error_bad_frame,
rx_error_bad_fcs,
ifg_delay)
@always(delay(4))
def clkgen():
clk.next = not clk
tx_clk.next = not tx_clk
rx_clk.next = not rx_clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
tx_rst.next = 1
rx_rst.next = 1
yield clk.posedge
rst.next = 0
tx_rst.next = 0
rx_rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
ifg_delay.next = 12
# testbench stimulus
yield clk.posedge
print("test 1: test rx packet")
current_test.next = 1
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(32))
test_frame.update_fcs()
axis_frame = test_frame.build_axis_fcs()
gmii_source_queue.put(axis_frame)
yield clk.posedge
yield clk.posedge
while gmii_rx_dv or rx_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not axis_sink_queue.empty():
rx_frame = axis_sink_queue.get()
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis(rx_frame)
eth_frame.update_fcs()
assert eth_frame == test_frame
yield delay(100)
yield clk.posedge
print("test 2: test tx packet")
current_test.next = 2
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(32))
test_frame.update_fcs()
axis_frame = test_frame.build_axis()
axis_source_queue.put(axis_frame)
yield clk.posedge
yield clk.posedge
while gmii_tx_en or tx_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not gmii_sink_queue.empty():
rx_frame = gmii_sink_queue.get()
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis_fcs(bytearray(rx_frame))
print(hex(eth_frame.eth_fcs))
print(hex(eth_frame.calc_fcs()))
assert eth_frame.eth_fcs == eth_frame.calc_fcs()
assert eth_frame.eth_dest_mac == test_frame.eth_dest_mac
assert eth_frame.eth_src_mac == test_frame.eth_src_mac
assert eth_frame.eth_type == test_frame.eth_type
assert eth_frame.payload.data.index(test_frame.payload.data) == 0
yield delay(100)
raise StopSimulation
return dut, axis_source, axis_sink, gmii_source, gmii_sink, clkgen, check
def test_bench():
sim = Simulation(bench())
sim.run()
if __name__ == '__main__':
print("Running test...")
test_bench()

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/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for eth_mac_1g
*/
module test_eth_mac_1g;
// Parameters
parameter ENABLE_PADDING = 1;
parameter MIN_FRAME_LENGTH = 64;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg rx_clk = 0;
reg rx_rst = 0;
reg tx_clk = 0;
reg tx_rst = 0;
reg [7:0] tx_axis_tdata = 0;
reg tx_axis_tvalid = 0;
reg tx_axis_tlast = 0;
reg tx_axis_tuser = 0;
reg [7:0] gmii_rxd = 0;
reg gmii_rx_dv = 0;
reg gmii_rx_er = 0;
reg [7:0] ifg_delay = 0;
// Outputs
wire tx_axis_tready;
wire [7:0] rx_axis_tdata;
wire rx_axis_tvalid;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [7:0] gmii_txd;
wire gmii_tx_en;
wire gmii_tx_er;
wire rx_error_bad_frame;
wire rx_error_bad_fcs;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
rx_clk,
rx_rst,
tx_clk,
tx_rst,
tx_axis_tdata,
tx_axis_tvalid,
tx_axis_tlast,
tx_axis_tuser,
gmii_rxd,
gmii_rx_dv,
gmii_rx_er,
ifg_delay);
$to_myhdl(tx_axis_tready,
rx_axis_tdata,
rx_axis_tvalid,
rx_axis_tlast,
rx_axis_tuser,
gmii_txd,
gmii_tx_en,
gmii_tx_er,
rx_error_bad_frame,
rx_error_bad_fcs);
// dump file
$dumpfile("test_eth_mac_1g.lxt");
$dumpvars(0, test_eth_mac_1g);
end
eth_mac_1g #(
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
)
UUT (
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.gmii_rxd(gmii_rxd),
.gmii_rx_dv(gmii_rx_dv),
.gmii_rx_er(gmii_rx_er),
.gmii_txd(gmii_txd),
.gmii_tx_en(gmii_tx_en),
.gmii_tx_er(gmii_tx_er),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.ifg_delay(ifg_delay)
);
endmodule

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#!/usr/bin/env python2
"""
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
"""
from myhdl import *
import os
from Queue import Queue
import axis_ep
import eth_ep
import gmii_ep
module = 'eth_mac_1g_rx'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/eth_crc_8.v")
srcs.append("test_%s.v" % module)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_eth_mac_1g_rx(clk,
rst,
current_test,
gmii_rxd,
gmii_rx_dv,
gmii_rx_er,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser,
error_bad_frame,
error_bad_fcs):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
gmii_rxd=gmii_rxd,
gmii_rx_dv=gmii_rx_dv,
gmii_rx_er=gmii_rx_er,
output_axis_tdata=output_axis_tdata,
output_axis_tvalid=output_axis_tvalid,
output_axis_tlast=output_axis_tlast,
output_axis_tuser=output_axis_tuser,
error_bad_frame=error_bad_frame,
error_bad_fcs=error_bad_fcs)
def bench():
# Parameters
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
gmii_rxd = Signal(intbv(0)[8:])
gmii_rx_dv = Signal(bool(0))
gmii_rx_er = Signal(bool(0))
# Outputs
output_axis_tdata = Signal(intbv(0)[8:])
output_axis_tvalid = Signal(bool(0))
output_axis_tlast = Signal(bool(0))
output_axis_tuser = Signal(bool(0))
error_bad_frame = Signal(bool(0))
error_bad_fcs = Signal(bool(0))
# sources and sinks
source_queue = Queue()
sink_queue = Queue()
source = gmii_ep.GMIISource(clk,
rst,
txd=gmii_rxd,
tx_en=gmii_rx_dv,
tx_er=gmii_rx_er,
fifo=source_queue,
name='source')
sink = axis_ep.AXIStreamSink(clk,
rst,
tdata=output_axis_tdata,
tvalid=output_axis_tvalid,
tlast=output_axis_tlast,
tuser=output_axis_tuser,
fifo=sink_queue,
name='sink')
# DUT
dut = dut_eth_mac_1g_rx(clk,
rst,
current_test,
gmii_rxd,
gmii_rx_dv,
gmii_rx_er,
output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser,
error_bad_frame,
error_bad_fcs)
@always(delay(4))
def clkgen():
clk.next = not clk
error_bad_frame_asserted = Signal(bool(0))
error_bad_fcs_asserted = Signal(bool(0))
@always(clk.posedge)
def monitor():
if (error_bad_frame):
error_bad_frame_asserted.next = 1
if (error_bad_fcs):
error_bad_fcs_asserted.next = 1
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
# testbench stimulus
for payload_len in list(range(1,18))+list(range(64,82)):
yield clk.posedge
print("test 1: test packet, length %d" % payload_len)
current_test.next = 1
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(payload_len))
test_frame.update_fcs()
axis_frame = test_frame.build_axis_fcs()
source_queue.put(axis_frame)
yield clk.posedge
yield clk.posedge
while gmii_rx_dv or output_axis_tvalid or not source_queue.empty():
yield clk.posedge
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis(rx_frame)
eth_frame.update_fcs()
assert eth_frame == test_frame
assert sink_queue.empty()
yield delay(100)
yield clk.posedge
print("test 2: back-to-back packets, length %d" % payload_len)
current_test.next = 2
test_frame1 = eth_ep.EthFrame()
test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x8000
test_frame1.payload = bytearray(range(payload_len))
test_frame1.update_fcs()
test_frame2 = eth_ep.EthFrame()
test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x8000
test_frame2.payload = bytearray(range(payload_len))
test_frame2.update_fcs()
axis_frame1 = test_frame1.build_axis_fcs()
axis_frame2 = test_frame2.build_axis_fcs()
source_queue.put(axis_frame1)
source_queue.put(axis_frame2)
yield clk.posedge
yield clk.posedge
while gmii_rx_dv or output_axis_tvalid or not source_queue.empty():
yield clk.posedge
yield clk.posedge
while gmii_rx_dv or output_axis_tvalid or not source_queue.empty():
yield clk.posedge
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis(rx_frame)
eth_frame.update_fcs()
assert eth_frame == test_frame1
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis(rx_frame)
eth_frame.update_fcs()
assert eth_frame == test_frame2
assert sink_queue.empty()
yield delay(100)
yield clk.posedge
print("test 3: truncated frame, length %d" % payload_len)
current_test.next = 3
test_frame1 = eth_ep.EthFrame()
test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x8000
test_frame1.payload = bytearray(range(payload_len))
test_frame1.update_fcs()
test_frame2 = eth_ep.EthFrame()
test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x8000
test_frame2.payload = bytearray(range(payload_len))
test_frame2.update_fcs()
axis_frame1 = test_frame1.build_axis_fcs()
axis_frame2 = test_frame2.build_axis_fcs()
axis_frame1.data = axis_frame1.data[:-1]
error_bad_frame_asserted.next = 0
error_bad_fcs_asserted.next = 0
source_queue.put(axis_frame1)
source_queue.put(axis_frame2)
yield clk.posedge
yield clk.posedge
while gmii_rx_dv or output_axis_tvalid or not source_queue.empty():
yield clk.posedge
yield clk.posedge
while gmii_rx_dv or output_axis_tvalid or not source_queue.empty():
yield clk.posedge
yield clk.posedge
yield clk.posedge
yield clk.posedge
assert error_bad_frame_asserted
assert error_bad_fcs_asserted
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
assert rx_frame.user[-1]
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis(rx_frame)
eth_frame.update_fcs()
assert eth_frame == test_frame2
assert sink_queue.empty()
yield delay(100)
raise StopSimulation
return dut, monitor, source, sink, clkgen, check
def test_bench():
sim = Simulation(bench())
sim.run()
if __name__ == '__main__':
print("Running test...")
test_bench()

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/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for eth_mac_1g_rx
*/
module test_eth_mac_1g_rx;
// Parameters
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] gmii_rxd = 0;
reg gmii_rx_dv = 0;
reg gmii_rx_er = 0;
// Outputs
wire [7:0] output_axis_tdata;
wire output_axis_tvalid;
wire output_axis_tlast;
wire output_axis_tuser;
wire error_bad_frame;
wire error_bad_fcs;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
gmii_rxd,
gmii_rx_dv,
gmii_rx_er);
$to_myhdl(output_axis_tdata,
output_axis_tvalid,
output_axis_tlast,
output_axis_tuser,
error_bad_frame,
error_bad_fcs);
// dump file
$dumpfile("test_eth_mac_1g_rx.lxt");
$dumpvars(0, test_eth_mac_1g_rx);
end
eth_mac_1g_rx
UUT (
.clk(clk),
.rst(rst),
.gmii_rxd(gmii_rxd),
.gmii_rx_dv(gmii_rx_dv),
.gmii_rx_er(gmii_rx_er),
.output_axis_tdata(output_axis_tdata),
.output_axis_tvalid(output_axis_tvalid),
.output_axis_tlast(output_axis_tlast),
.output_axis_tuser(output_axis_tuser),
.error_bad_frame(error_bad_frame),
.error_bad_fcs(error_bad_fcs)
);
endmodule

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#!/usr/bin/env python2
"""
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
"""
from myhdl import *
import os
from Queue import Queue
import axis_ep
import eth_ep
import gmii_ep
module = 'eth_mac_1g_tx'
srcs = []
srcs.append("../rtl/%s.v" % module)
srcs.append("../rtl/eth_crc_8.v")
srcs.append("test_%s.v" % module)
src = ' '.join(srcs)
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
def dut_eth_mac_1g_tx(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
gmii_txd,
gmii_tx_en,
gmii_tx_er,
ifg_delay):
if os.system(build_cmd):
raise Exception("Error running build command")
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
clk=clk,
rst=rst,
current_test=current_test,
input_axis_tdata=input_axis_tdata,
input_axis_tvalid=input_axis_tvalid,
input_axis_tready=input_axis_tready,
input_axis_tlast=input_axis_tlast,
input_axis_tuser=input_axis_tuser,
gmii_txd=gmii_txd,
gmii_tx_en=gmii_tx_en,
gmii_tx_er=gmii_tx_er,
ifg_delay=ifg_delay)
def bench():
# Parameters
ENABLE_PADDING = 1
MIN_FRAME_LENGTH = 64
# Inputs
clk = Signal(bool(0))
rst = Signal(bool(0))
current_test = Signal(intbv(0)[8:])
input_axis_tdata = Signal(intbv(0)[8:])
input_axis_tvalid = Signal(bool(0))
input_axis_tlast = Signal(bool(0))
input_axis_tuser = Signal(bool(0))
ifg_delay = Signal(intbv(0)[8:])
# Outputs
input_axis_tready = Signal(bool(0))
gmii_txd = Signal(intbv(0)[8:])
gmii_tx_en = Signal(bool(0))
gmii_tx_er = Signal(bool(0))
# sources and sinks
source_queue = Queue()
source_pause = Signal(bool(0))
sink_queue = Queue()
source = axis_ep.AXIStreamSource(clk,
rst,
tdata=input_axis_tdata,
tvalid=input_axis_tvalid,
tready=input_axis_tready,
tlast=input_axis_tlast,
tuser=input_axis_tuser,
fifo=source_queue,
pause=source_pause,
name='source')
sink = gmii_ep.GMIISink(clk,
rst,
rxd=gmii_txd,
rx_dv=gmii_tx_en,
rx_er=gmii_tx_er,
fifo=sink_queue,
name='sink')
# DUT
dut = dut_eth_mac_1g_tx(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tready,
input_axis_tlast,
input_axis_tuser,
gmii_txd,
gmii_tx_en,
gmii_tx_er,
ifg_delay)
@always(delay(4))
def clkgen():
clk.next = not clk
@instance
def check():
yield delay(100)
yield clk.posedge
rst.next = 1
yield clk.posedge
rst.next = 0
yield clk.posedge
yield delay(100)
yield clk.posedge
ifg_delay.next = 12
# testbench stimulus
for payload_len in list(range(1,18))+list(range(64,82)):
yield clk.posedge
print("test 1: test packet, length %d" % payload_len)
current_test.next = 1
test_frame = eth_ep.EthFrame()
test_frame.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame.eth_src_mac = 0x5A5152535455
test_frame.eth_type = 0x8000
test_frame.payload = bytearray(range(payload_len))
test_frame.update_fcs()
axis_frame = test_frame.build_axis()
source_queue.put(axis_frame)
yield clk.posedge
yield clk.posedge
while gmii_tx_en or input_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis_fcs(bytearray(rx_frame))
print(hex(eth_frame.eth_fcs))
print(hex(eth_frame.calc_fcs()))
assert eth_frame.eth_fcs == eth_frame.calc_fcs()
assert eth_frame.eth_dest_mac == test_frame.eth_dest_mac
assert eth_frame.eth_src_mac == test_frame.eth_src_mac
assert eth_frame.eth_type == test_frame.eth_type
assert eth_frame.payload.data.index(test_frame.payload.data) == 0
assert sink_queue.empty()
yield delay(100)
yield clk.posedge
print("test 2: back-to-back packets, length %d" % payload_len)
current_test.next = 2
test_frame1 = eth_ep.EthFrame()
test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x8000
test_frame1.payload = bytearray(range(payload_len))
test_frame1.update_fcs()
test_frame2 = eth_ep.EthFrame()
test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x8000
test_frame2.payload = bytearray(range(payload_len))
test_frame2.update_fcs()
axis_frame1 = test_frame1.build_axis()
axis_frame2 = test_frame2.build_axis()
source_queue.put(axis_frame1)
source_queue.put(axis_frame2)
yield clk.posedge
yield clk.posedge
while gmii_tx_en or input_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis_fcs(bytearray(rx_frame))
print(hex(eth_frame.eth_fcs))
print(hex(eth_frame.calc_fcs()))
assert eth_frame.eth_fcs == eth_frame.calc_fcs()
assert eth_frame.eth_dest_mac == test_frame1.eth_dest_mac
assert eth_frame.eth_src_mac == test_frame1.eth_src_mac
assert eth_frame.eth_type == test_frame1.eth_type
assert eth_frame.payload.data.index(test_frame1.payload.data) == 0
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis_fcs(bytearray(rx_frame))
print(hex(eth_frame.eth_fcs))
print(hex(eth_frame.calc_fcs()))
assert eth_frame.eth_fcs == eth_frame.calc_fcs()
assert eth_frame.eth_dest_mac == test_frame2.eth_dest_mac
assert eth_frame.eth_src_mac == test_frame2.eth_src_mac
assert eth_frame.eth_type == test_frame2.eth_type
assert eth_frame.payload.data.index(test_frame2.payload.data) == 0
assert sink_queue.empty()
yield delay(100)
yield clk.posedge
print("test 3: tuser assert, length %d" % payload_len)
current_test.next = 3
test_frame1 = eth_ep.EthFrame()
test_frame1.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame1.eth_src_mac = 0x5A5152535455
test_frame1.eth_type = 0x8000
test_frame1.payload = bytearray(range(payload_len))
test_frame1.update_fcs()
test_frame2 = eth_ep.EthFrame()
test_frame2.eth_dest_mac = 0xDAD1D2D3D4D5
test_frame2.eth_src_mac = 0x5A5152535455
test_frame2.eth_type = 0x8000
test_frame2.payload = bytearray(range(payload_len))
test_frame2.update_fcs()
axis_frame1 = test_frame1.build_axis()
axis_frame2 = test_frame2.build_axis()
axis_frame1.user = 1
source_queue.put(axis_frame1)
source_queue.put(axis_frame2)
yield clk.posedge
yield clk.posedge
while gmii_tx_en or input_axis_tvalid:
yield clk.posedge
yield clk.posedge
yield clk.posedge
yield clk.posedge
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
# bad packet
rx_frame = None
if not sink_queue.empty():
rx_frame = sink_queue.get()
eth_frame = eth_ep.EthFrame()
eth_frame.parse_axis_fcs(bytearray(rx_frame))
print(hex(eth_frame.eth_fcs))
print(hex(eth_frame.calc_fcs()))
assert eth_frame.eth_fcs == eth_frame.calc_fcs()
assert eth_frame.eth_dest_mac == test_frame2.eth_dest_mac
assert eth_frame.eth_src_mac == test_frame2.eth_src_mac
assert eth_frame.eth_type == test_frame2.eth_type
assert eth_frame.payload.data.index(test_frame2.payload.data) == 0
assert sink_queue.empty()
yield delay(100)
raise StopSimulation
return dut, source, sink, clkgen, check
def test_bench():
sim = Simulation(bench())
sim.run()
if __name__ == '__main__':
print("Running test...")
test_bench()

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tb/test_eth_mac_1g_tx.v Normal file
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/*
Copyright (c) 2015 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for eth_mac_1g_tx
*/
module test_eth_mac_1g_tx;
// Parameters
parameter ENABLE_PADDING = 1;
parameter MIN_FRAME_LENGTH = 64;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [7:0] input_axis_tdata = 0;
reg input_axis_tvalid = 0;
reg input_axis_tlast = 0;
reg input_axis_tuser = 0;
reg [7:0] ifg_delay = 0;
// Outputs
wire input_axis_tready;
wire [7:0] gmii_txd;
wire gmii_tx_en;
wire gmii_tx_er;
initial begin
// myhdl integration
$from_myhdl(clk,
rst,
current_test,
input_axis_tdata,
input_axis_tvalid,
input_axis_tlast,
input_axis_tuser,
ifg_delay);
$to_myhdl(input_axis_tready,
gmii_txd,
gmii_tx_en,
gmii_tx_er);
// dump file
$dumpfile("test_eth_mac_1g_tx.lxt");
$dumpvars(0, test_eth_mac_1g_tx);
end
eth_mac_1g_tx #(
.ENABLE_PADDING(ENABLE_PADDING),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)
)
UUT (
.clk(clk),
.rst(rst),
.input_axis_tdata(input_axis_tdata),
.input_axis_tvalid(input_axis_tvalid),
.input_axis_tready(input_axis_tready),
.input_axis_tlast(input_axis_tlast),
.input_axis_tuser(input_axis_tuser),
.gmii_txd(gmii_txd),
.gmii_tx_en(gmii_tx_en),
.gmii_tx_er(gmii_tx_er),
.ifg_delay(ifg_delay)
);
endmodule