mirror of
https://github.com/corundum/corundum.git
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fpga/mqnic/fb4CGg3: Add DRAM support on fb4CGg3
Signed-off-by: Alex Forencich <alex@alexforencich.com>
This commit is contained in:
Alex Forencich
parent
f1884b98bf
commit
6e67bd652e
4
fpga/mqnic/fb4CGg3/fpga_100g/boot.xdc
Normal file
4
fpga/mqnic/fb4CGg3/fpga_100g/boot.xdc
Normal file
@ -0,0 +1,4 @@
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# Timing constraints for FPGA boot logic
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set_property ASYNC_REG TRUE [get_cells "fpga_boot_sync_reg_0_reg fpga_boot_sync_reg_1_reg"]
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set_false_path -to [get_pins "fpga_boot_sync_reg_0_reg/D"]
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@ -13,24 +13,24 @@ set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
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set_property -dict {LOC AV26 IOSTANDARD LVCMOS18} [get_ports init_clk]
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create_clock -period 20.000 -name init_clk [get_ports init_clk]
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# DDR4 refclk1
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#set_property -dict {LOC BA34 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk1_p]
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#set_property -dict {LOC BB34 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk1_n]
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#create_clock -period 3.750 -name clk_ddr4_refclk1 [get_ports clk_ddr4_refclk1_p]
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# DDR4 A refclk
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set_property -dict {LOC BA34 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr4_a_refclk_p]
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set_property -dict {LOC BB34 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr4_a_refclk_n]
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#create_clock -period 3.750 -name clk_ddr4_a_refclk [get_ports clk_ddr4_a_refclk_p]
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# DDR4 refclk2
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#set_property -dict {LOC C36 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk2_p]
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#set_property -dict {LOC C37 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk2_n]
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#create_clock -period 3.750 -name clk_ddr4_refclk2 [get_ports clk_ddr4_refclk2_p]
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# DDR4 B refclk
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set_property -dict {LOC C36 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr4_b_refclk_p]
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set_property -dict {LOC C37 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr4_b_refclk_n]
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#create_clock -period 3.750 -name clk_ddr4_b_refclk [get_ports clk_ddr4_b_refclk_p]
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# SODIMM A refclk
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#set_property -dict {LOC AV27 IOSTANDARD DIFF_SSTL12} [get_ports clk_sodimm_a_refclk_p]
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#set_property -dict {LOC AV28 IOSTANDARD DIFF_SSTL12} [get_ports clk_sodimm_a_refclk_n]
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set_property -dict {LOC AV27 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports clk_sodimm_a_refclk_p]
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set_property -dict {LOC AV28 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports clk_sodimm_a_refclk_n]
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#create_clock -period 3.750 -name clk_sodimm_a_refclk [get_ports clk_sodimm_a_refclk_p]
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# SODIMM B refclk
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#set_property -dict {LOC H19 IOSTANDARD DIFF_SSTL12} [get_ports clk_sodimm_b_refclk_p]
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#set_property -dict {LOC H18 IOSTANDARD DIFF_SSTL12} [get_ports clk_sodimm_b_refclk_n]
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set_property -dict {LOC H19 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_sodimm_b_refclk_p]
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set_property -dict {LOC H18 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_sodimm_b_refclk_n]
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#create_clock -period 3.750 -name clk_sodimm_b_refclk [get_ports clk_sodimm_b_refclk_p]
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# LEDs
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@ -55,6 +55,17 @@ set_output_delay 0 [get_ports {pps_out}]
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set_false_path -from [get_ports {pps_in}]
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set_input_delay 0 [get_ports {pps_in}]
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# BMC interface
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set_property -dict {LOC AW28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports bmc_clk]
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set_property -dict {LOC AY27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports bmc_nss]
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set_property -dict {LOC AY28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports bmc_mosi]
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set_property -dict {LOC AY26 IOSTANDARD LVCMOS18} [get_ports bmc_miso]
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set_false_path -to [get_ports {bmc_clk bmc_nss bmc_mosi}]
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set_output_delay 0 [get_ports {bmc_clk bmc_nss bmc_mosi}]
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set_false_path -from [get_ports {bmc_miso}]
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set_input_delay 0 [get_ports {bmc_miso}]
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# QSFP28 Interfaces
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set_property -dict {LOC AP43} [get_ports qsfp_0_rx_0_p] ;# MGTYRXP3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2
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set_property -dict {LOC AP44} [get_ports qsfp_0_rx_0_n] ;# MGTYRXN3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2
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@ -285,3 +296,505 @@ create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_refclk_0_p]
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set_false_path -from [get_ports {pcie_rst_n}]
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set_input_delay 0 [get_ports {pcie_rst_n}]
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# DDR4 A (U100, U101, U102, U103)
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# 4x MT40A512M16JY-083E
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set_property -dict {LOC BD34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[0]}]
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set_property -dict {LOC AV33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[1]}]
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set_property -dict {LOC AM32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[2]}]
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set_property -dict {LOC AL34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[3]}]
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set_property -dict {LOC BE35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[4]}]
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set_property -dict {LOC AY33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[5]}]
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set_property -dict {LOC AY35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[6]}]
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set_property -dict {LOC AW33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[7]}]
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set_property -dict {LOC AW34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[8]}]
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set_property -dict {LOC AU34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[9]}]
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set_property -dict {LOC AN34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[10]}]
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set_property -dict {LOC BC34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[11]}]
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set_property -dict {LOC BE36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[12]}]
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set_property -dict {LOC AL32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[13]}]
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set_property -dict {LOC BB37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[14]}]
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set_property -dict {LOC AM34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[15]}]
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set_property -dict {LOC AP33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[16]}]
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set_property -dict {LOC AY36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_ba[0]}]
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set_property -dict {LOC BA33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_ba[1]}]
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set_property -dict {LOC AW36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_bg[0]}]
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set_property -dict {LOC AR33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_bg[1]}]
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set_property -dict {LOC AN32 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_a_ck_t[0]}]
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set_property -dict {LOC AN33 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_a_ck_c[0]}]
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set_property -dict {LOC AV34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_cke[0]}]
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set_property -dict {LOC AP34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_cs_n[0]}]
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set_property -dict {LOC AL33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_act_n}]
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set_property -dict {LOC BD35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_odt[0]}]
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set_property -dict {LOC AW35 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_a_reset_n}]
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set_property -dict {LOC BD36 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_a_ten}]
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set_property -dict {LOC Y33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[0]}]
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set_property -dict {LOC W34 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[1]}]
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set_property -dict {LOC AA34 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[2]}]
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set_property -dict {LOC Y32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[3]}]
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set_property -dict {LOC W33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[4]}]
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set_property -dict {LOC W30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[5]}]
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set_property -dict {LOC AB34 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[6]}]
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set_property -dict {LOC Y30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[7]}]
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set_property -dict {LOC AD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[8]}]
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set_property -dict {LOC AC34 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[9]}]
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set_property -dict {LOC AE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[10]}]
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set_property -dict {LOC AC33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[11]}]
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set_property -dict {LOC AF30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[12]}]
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set_property -dict {LOC AC32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[13]}]
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set_property -dict {LOC AE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[14]}]
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set_property -dict {LOC AD34 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[15]}]
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set_property -dict {LOC AF34 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[16]}]
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set_property -dict {LOC AJ33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[17]}]
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set_property -dict {LOC AG34 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[18]}]
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set_property -dict {LOC AG32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[19]}]
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set_property -dict {LOC AF33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[20]}]
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set_property -dict {LOC AG31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[21]}]
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set_property -dict {LOC AF32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[22]}]
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set_property -dict {LOC AH33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[23]}]
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set_property -dict {LOC AK31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[24]}]
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set_property -dict {LOC AK28 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[25]}]
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set_property -dict {LOC AJ31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[26]}]
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set_property -dict {LOC AJ29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[27]}]
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set_property -dict {LOC AG29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[28]}]
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set_property -dict {LOC AJ28 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[29]}]
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set_property -dict {LOC AG30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[30]}]
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set_property -dict {LOC AJ30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[31]}]
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set_property -dict {LOC AP29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[32]}]
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set_property -dict {LOC AM31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[33]}]
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set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[34]}]
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set_property -dict {LOC AL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[35]}]
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set_property -dict {LOC AP30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[36]}]
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set_property -dict {LOC AL29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[37]}]
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set_property -dict {LOC AR30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[38]}]
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set_property -dict {LOC AN29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[39]}]
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set_property -dict {LOC AW31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[40]}]
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set_property -dict {LOC AV32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[41]}]
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set_property -dict {LOC AV31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[42]}]
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set_property -dict {LOC AU31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[43]}]
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set_property -dict {LOC AU30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[44]}]
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set_property -dict {LOC AU32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[45]}]
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set_property -dict {LOC AT29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[46]}]
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set_property -dict {LOC AT30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[47]}]
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set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[48]}]
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set_property -dict {LOC BB29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[49]}]
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set_property -dict {LOC AY30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[50]}]
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set_property -dict {LOC BB31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[51]}]
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set_property -dict {LOC BA30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[52]}]
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set_property -dict {LOC BB30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[53]}]
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set_property -dict {LOC AY31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[54]}]
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set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[55]}]
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set_property -dict {LOC BC29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[56]}]
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set_property -dict {LOC BF30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[57]}]
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set_property -dict {LOC BD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[58]}]
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set_property -dict {LOC BE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[59]}]
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set_property -dict {LOC BD29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[60]}]
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set_property -dict {LOC BE31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[61]}]
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set_property -dict {LOC BE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[62]}]
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set_property -dict {LOC BE32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[63]}]
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set_property -dict {LOC W31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_t[0]}]
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set_property -dict {LOC Y31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_c[0]}]
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set_property -dict {LOC AC31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_t[1]}]
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set_property -dict {LOC AD31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_c[1]}]
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set_property -dict {LOC AH31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_t[2]}]
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set_property -dict {LOC AH32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_c[2]}]
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set_property -dict {LOC AH28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_t[3]}]
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set_property -dict {LOC AH29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_c[3]}]
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set_property -dict {LOC AM29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_t[4]}]
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set_property -dict {LOC AM30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_c[4]}]
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set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_t[5]}]
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set_property -dict {LOC AV29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_c[5]}]
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set_property -dict {LOC BA32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_t[6]}]
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set_property -dict {LOC BB32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_c[6]}]
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set_property -dict {LOC BD30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_t[7]}]
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set_property -dict {LOC BD31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_c[7]}]
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set_property -dict {LOC AA32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dm_dbi_n[0]}]
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set_property -dict {LOC AE31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dm_dbi_n[1]}]
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set_property -dict {LOC AH34 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dm_dbi_n[2]}]
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set_property -dict {LOC AJ27 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dm_dbi_n[3]}]
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set_property -dict {LOC AP31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dm_dbi_n[4]}]
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set_property -dict {LOC AW29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dm_dbi_n[5]}]
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set_property -dict {LOC BC31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dm_dbi_n[6]}]
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set_property -dict {LOC BF32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dm_dbi_n[7]}]
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# DDR4 B (U200, U201, U202, U203)
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# 4x MT40A512M16JY-083E
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set_property -dict {LOC E37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[0]}]
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set_property -dict {LOC D36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[1]}]
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set_property -dict {LOC E36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[2]}]
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set_property -dict {LOC B35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[3]}]
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set_property -dict {LOC D35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[4]}]
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set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[5]}]
|
||||
set_property -dict {LOC D39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[6]}]
|
||||
set_property -dict {LOC D33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[7]}]
|
||||
set_property -dict {LOC E40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[8]}]
|
||||
set_property -dict {LOC E35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[9]}]
|
||||
set_property -dict {LOC A38 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[10]}]
|
||||
set_property -dict {LOC E39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[11]}]
|
||||
set_property -dict {LOC B37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[12]}]
|
||||
set_property -dict {LOC D31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[13]}]
|
||||
set_property -dict {LOC B39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[14]}]
|
||||
set_property -dict {LOC C31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[15]}]
|
||||
set_property -dict {LOC B31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[16]}]
|
||||
set_property -dict {LOC D40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_ba[0]}]
|
||||
set_property -dict {LOC B32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_ba[1]}]
|
||||
set_property -dict {LOC B40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_bg[0]}]
|
||||
set_property -dict {LOC B36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_bg[1]}]
|
||||
set_property -dict {LOC A32 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_b_ck_t[0]}]
|
||||
set_property -dict {LOC A33 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_b_ck_c[0]}]
|
||||
set_property -dict {LOC C33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_cke[0]}]
|
||||
set_property -dict {LOC A37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_cs_n[0]}]
|
||||
set_property -dict {LOC A40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_act_n}]
|
||||
set_property -dict {LOC C34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_odt[0]}]
|
||||
set_property -dict {LOC D34 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_b_reset_n}]
|
||||
set_property -dict {LOC A35 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_b_ten}]
|
||||
|
||||
set_property -dict {LOC B30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[0]}]
|
||||
set_property -dict {LOC C29 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[1]}]
|
||||
set_property -dict {LOC B29 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[2]}]
|
||||
set_property -dict {LOC A29 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[3]}]
|
||||
set_property -dict {LOC A30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[4]}]
|
||||
set_property -dict {LOC D29 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[5]}]
|
||||
set_property -dict {LOC E30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[6]}]
|
||||
set_property -dict {LOC D30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[7]}]
|
||||
set_property -dict {LOC H29 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[8]}]
|
||||
set_property -dict {LOC E28 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[9]}]
|
||||
set_property -dict {LOC G29 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[10]}]
|
||||
set_property -dict {LOC G27 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[11]}]
|
||||
set_property -dict {LOC E27 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[12]}]
|
||||
set_property -dict {LOC D28 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[13]}]
|
||||
set_property -dict {LOC G26 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[14]}]
|
||||
set_property -dict {LOC F27 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[15]}]
|
||||
set_property -dict {LOC J28 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[16]}]
|
||||
set_property -dict {LOC L28 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[17]}]
|
||||
set_property -dict {LOC J29 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[18]}]
|
||||
set_property -dict {LOC L27 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[19]}]
|
||||
set_property -dict {LOC H28 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[20]}]
|
||||
set_property -dict {LOC M27 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[21]}]
|
||||
set_property -dict {LOC H27 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[22]}]
|
||||
set_property -dict {LOC K28 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[23]}]
|
||||
set_property -dict {LOC N28 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[24]}]
|
||||
set_property -dict {LOC R27 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[25]}]
|
||||
set_property -dict {LOC P28 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[26]}]
|
||||
set_property -dict {LOC T27 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[27]}]
|
||||
set_property -dict {LOC P26 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[28]}]
|
||||
set_property -dict {LOC R26 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[29]}]
|
||||
set_property -dict {LOC N26 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[30]}]
|
||||
set_property -dict {LOC T26 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[31]}]
|
||||
set_property -dict {LOC F33 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[32]}]
|
||||
set_property -dict {LOC G32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[33]}]
|
||||
set_property -dict {LOC H32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[34]}]
|
||||
set_property -dict {LOC E32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[35]}]
|
||||
set_property -dict {LOC F32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[36]}]
|
||||
set_property -dict {LOC G31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[37]}]
|
||||
set_property -dict {LOC E33 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[38]}]
|
||||
set_property -dict {LOC H31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[39]}]
|
||||
set_property -dict {LOC L33 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[40]}]
|
||||
set_property -dict {LOC J31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[41]}]
|
||||
set_property -dict {LOC L32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[42]}]
|
||||
set_property -dict {LOC K33 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[43]}]
|
||||
set_property -dict {LOC M30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[44]}]
|
||||
set_property -dict {LOC K32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[45]}]
|
||||
set_property -dict {LOC L30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[46]}]
|
||||
set_property -dict {LOC K31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[47]}]
|
||||
set_property -dict {LOC N33 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[48]}]
|
||||
set_property -dict {LOC R31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[49]}]
|
||||
set_property -dict {LOC N34 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[50]}]
|
||||
set_property -dict {LOC P34 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[51]}]
|
||||
set_property -dict {LOC N32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[52]}]
|
||||
set_property -dict {LOC R32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[53]}]
|
||||
set_property -dict {LOC N31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[54]}]
|
||||
set_property -dict {LOC P31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[55]}]
|
||||
set_property -dict {LOC U31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[56]}]
|
||||
set_property -dict {LOC U30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[57]}]
|
||||
set_property -dict {LOC T32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[58]}]
|
||||
set_property -dict {LOC V31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[59]}]
|
||||
set_property -dict {LOC T30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[60]}]
|
||||
set_property -dict {LOC T33 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[61]}]
|
||||
set_property -dict {LOC R33 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[62]}]
|
||||
set_property -dict {LOC U32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[63]}]
|
||||
set_property -dict {LOC A27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_t[0]}]
|
||||
set_property -dict {LOC A28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_c[0]}]
|
||||
set_property -dict {LOC F28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_t[1]}]
|
||||
set_property -dict {LOC F29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_c[1]}]
|
||||
set_property -dict {LOC K26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_t[2]}]
|
||||
set_property -dict {LOC K27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_c[2]}]
|
||||
set_property -dict {LOC P29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_t[3]}]
|
||||
set_property -dict {LOC N29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_c[3]}]
|
||||
set_property -dict {LOC J33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_t[4]}]
|
||||
set_property -dict {LOC H33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_c[4]}]
|
||||
set_property -dict {LOC K30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_t[5]}]
|
||||
set_property -dict {LOC J30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_c[5]}]
|
||||
set_property -dict {LOC M34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_t[6]}]
|
||||
set_property -dict {LOC L34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_c[6]}]
|
||||
set_property -dict {LOC V32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_t[7]}]
|
||||
set_property -dict {LOC V33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_c[7]}]
|
||||
set_property -dict {LOC C27 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dm_dbi_n[0]}]
|
||||
set_property -dict {LOC J26 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dm_dbi_n[1]}]
|
||||
set_property -dict {LOC M29 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dm_dbi_n[2]}]
|
||||
set_property -dict {LOC T28 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dm_dbi_n[3]}]
|
||||
set_property -dict {LOC G30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dm_dbi_n[4]}]
|
||||
set_property -dict {LOC M31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dm_dbi_n[5]}]
|
||||
set_property -dict {LOC R30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dm_dbi_n[6]}]
|
||||
set_property -dict {LOC U34 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dm_dbi_n[7]}]
|
||||
|
||||
# DDR4 SODIMM A
|
||||
set_property -dict {LOC BE15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_adr[0]}]
|
||||
set_property -dict {LOC BF15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_adr[1]}]
|
||||
set_property -dict {LOC BD16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_adr[2]}]
|
||||
set_property -dict {LOC BD15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_adr[3]}]
|
||||
set_property -dict {LOC BE16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_adr[4]}]
|
||||
set_property -dict {LOC BD14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_adr[5]}]
|
||||
set_property -dict {LOC BC14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_adr[6]}]
|
||||
set_property -dict {LOC BC13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_adr[7]}]
|
||||
set_property -dict {LOC AT14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_adr[8]}]
|
||||
set_property -dict {LOC AR16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_adr[9]}]
|
||||
set_property -dict {LOC AR15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_adr[10]}]
|
||||
set_property -dict {LOC AP15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_adr[11]}]
|
||||
set_property -dict {LOC AP14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_adr[12]}]
|
||||
set_property -dict {LOC AM15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_adr[13]}]
|
||||
set_property -dict {LOC AN13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_adr[14]}]
|
||||
set_property -dict {LOC AP13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_adr[15]}]
|
||||
set_property -dict {LOC AR13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_adr[16]}]
|
||||
set_property -dict {LOC AL15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_ba[0]}]
|
||||
set_property -dict {LOC AN14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_ba[1]}]
|
||||
set_property -dict {LOC AL14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_bg[0]}]
|
||||
set_property -dict {LOC AM14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_bg[1]}]
|
||||
set_property -dict {LOC BD13 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_sodimm_a_ck_t[0]}]
|
||||
set_property -dict {LOC BE13 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_sodimm_a_ck_c[0]}]
|
||||
set_property -dict {LOC AT13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_cke[0]}]
|
||||
set_property -dict {LOC BB12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_cs_n[0]}]
|
||||
#set_property -dict {LOC BA17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_cs_n[2]}]
|
||||
#set_property -dict {LOC AU21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_cs_n[3]}]
|
||||
set_property -dict {LOC BF14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_act_n}]
|
||||
set_property -dict {LOC BF13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_odt[0]}]
|
||||
set_property -dict {LOC BC11 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_sodimm_a_reset_n}]
|
||||
set_property -dict {LOC AU19 IOSTANDARD LVCMOS12 } [get_ports {ddr4_sodimm_a_alert_n}]
|
||||
set_property -dict {LOC AV17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_sodimm_a_event_n}]
|
||||
|
||||
set_property -dict {LOC BE8 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[0]}]
|
||||
set_property -dict {LOC BE12 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[1]}]
|
||||
set_property -dict {LOC BF10 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[2]}]
|
||||
set_property -dict {LOC BD8 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[3]}]
|
||||
set_property -dict {LOC BD9 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[4]}]
|
||||
set_property -dict {LOC BF12 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[5]}]
|
||||
set_property -dict {LOC BF8 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[6]}]
|
||||
set_property -dict {LOC BF9 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[7]}]
|
||||
set_property -dict {LOC BB11 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[8]}]
|
||||
set_property -dict {LOC BA9 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[9]}]
|
||||
set_property -dict {LOC BC8 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[10]}]
|
||||
set_property -dict {LOC BC9 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[11]}]
|
||||
set_property -dict {LOC BB10 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[12]}]
|
||||
set_property -dict {LOC BA8 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[13]}]
|
||||
set_property -dict {LOC BB9 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[14]}]
|
||||
set_property -dict {LOC BC7 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[15]}]
|
||||
set_property -dict {LOC AY11 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[16]}]
|
||||
set_property -dict {LOC BA15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[17]}]
|
||||
set_property -dict {LOC BA14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[18]}]
|
||||
set_property -dict {LOC AY13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[19]}]
|
||||
set_property -dict {LOC AY12 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[20]}]
|
||||
set_property -dict {LOC BA13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[21]}]
|
||||
set_property -dict {LOC AY16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[22]}]
|
||||
set_property -dict {LOC AY15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[23]}]
|
||||
set_property -dict {LOC AW15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[24]}]
|
||||
set_property -dict {LOC AW16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[25]}]
|
||||
set_property -dict {LOC AU16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[26]}]
|
||||
set_property -dict {LOC AV13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[27]}]
|
||||
set_property -dict {LOC AU13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[28]}]
|
||||
set_property -dict {LOC AT15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[29]}]
|
||||
set_property -dict {LOC AV16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[30]}]
|
||||
set_property -dict {LOC AU15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[31]}]
|
||||
set_property -dict {LOC AN16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[32]}]
|
||||
set_property -dict {LOC AM20 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[33]}]
|
||||
set_property -dict {LOC AM19 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[34]}]
|
||||
set_property -dict {LOC AN19 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[35]}]
|
||||
set_property -dict {LOC AM16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[36]}]
|
||||
set_property -dict {LOC AL20 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[37]}]
|
||||
set_property -dict {LOC AL19 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[38]}]
|
||||
set_property -dict {LOC AP19 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[39]}]
|
||||
set_property -dict {LOC AP20 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[40]}]
|
||||
set_property -dict {LOC AR18 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[41]}]
|
||||
set_property -dict {LOC AP18 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[42]}]
|
||||
set_property -dict {LOC AT20 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[43]}]
|
||||
set_property -dict {LOC AU20 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[44]}]
|
||||
set_property -dict {LOC AU17 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[45]}]
|
||||
set_property -dict {LOC AR20 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[46]}]
|
||||
set_property -dict {LOC AT18 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[47]}]
|
||||
set_property -dict {LOC AW20 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[48]}]
|
||||
set_property -dict {LOC AW19 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[49]}]
|
||||
set_property -dict {LOC AW18 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[50]}]
|
||||
set_property -dict {LOC AV19 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[51]}]
|
||||
set_property -dict {LOC AY18 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[52]}]
|
||||
set_property -dict {LOC AY20 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[53]}]
|
||||
set_property -dict {LOC AV18 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[54]}]
|
||||
set_property -dict {LOC BA18 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[55]}]
|
||||
set_property -dict {LOC BE18 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[56]}]
|
||||
set_property -dict {LOC BB17 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[57]}]
|
||||
set_property -dict {LOC BC18 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[58]}]
|
||||
set_property -dict {LOC BD18 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[59]}]
|
||||
set_property -dict {LOC BC17 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[60]}]
|
||||
set_property -dict {LOC BF19 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[61]}]
|
||||
set_property -dict {LOC BB19 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[62]}]
|
||||
set_property -dict {LOC BF18 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[63]}]
|
||||
#set_property -dict {LOC AP16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[64]}]
|
||||
#set_property -dict {LOC BF17 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[65]}]
|
||||
#set_property -dict {LOC BB16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[66]}]
|
||||
#set_property -dict {LOC AW13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[67]}]
|
||||
#set_property -dict {LOC BF7 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[68]}]
|
||||
#set_property -dict {LOC BD11 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[69]}]
|
||||
#set_property -dict {LOC AN17 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[70]}]
|
||||
set_property -dict {LOC BE11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_a_dqs_t[0]}]
|
||||
set_property -dict {LOC BE10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_a_dqs_c[0]}]
|
||||
set_property -dict {LOC BA7 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_a_dqs_t[1]}]
|
||||
set_property -dict {LOC BB7 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_a_dqs_c[1]}]
|
||||
set_property -dict {LOC BB15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_a_dqs_t[2]}]
|
||||
set_property -dict {LOC BB14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_a_dqs_c[2]}]
|
||||
set_property -dict {LOC AU14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_a_dqs_t[3]}]
|
||||
set_property -dict {LOC AV14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_a_dqs_c[3]}]
|
||||
set_property -dict {LOC AL17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_a_dqs_t[4]}]
|
||||
set_property -dict {LOC AM17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_a_dqs_c[4]}]
|
||||
set_property -dict {LOC AR17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_a_dqs_t[5]}]
|
||||
set_property -dict {LOC AT17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_a_dqs_c[5]}]
|
||||
set_property -dict {LOC AV21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_a_dqs_t[6]}]
|
||||
set_property -dict {LOC AW21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_a_dqs_c[6]}]
|
||||
set_property -dict {LOC BC19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_a_dqs_t[7]}]
|
||||
set_property -dict {LOC BD19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_a_dqs_c[7]}]
|
||||
set_property -dict {LOC BE7 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dm_dbi_n[0]}]
|
||||
set_property -dict {LOC BC12 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dm_dbi_n[1]}]
|
||||
set_property -dict {LOC BA12 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dm_dbi_n[2]}]
|
||||
set_property -dict {LOC AW14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dm_dbi_n[3]}]
|
||||
set_property -dict {LOC AN18 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dm_dbi_n[4]}]
|
||||
set_property -dict {LOC AT19 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dm_dbi_n[5]}]
|
||||
set_property -dict {LOC AY17 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dm_dbi_n[6]}]
|
||||
set_property -dict {LOC BE17 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dm_dbi_n[7]}]
|
||||
|
||||
# DDR4 SODIMM B
|
||||
set_property -dict {LOC G20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_adr[0]}]
|
||||
set_property -dict {LOC G19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_adr[1]}]
|
||||
set_property -dict {LOC F20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_adr[2]}]
|
||||
set_property -dict {LOC E21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_adr[3]}]
|
||||
set_property -dict {LOC F19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_adr[4]}]
|
||||
set_property -dict {LOC E20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_adr[5]}]
|
||||
set_property -dict {LOC F18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_adr[6]}]
|
||||
set_property -dict {LOC F17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_adr[7]}]
|
||||
set_property -dict {LOC G21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_adr[8]}]
|
||||
set_property -dict {LOC D19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_adr[9]}]
|
||||
set_property -dict {LOC C19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_adr[10]}]
|
||||
set_property -dict {LOC D21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_adr[11]}]
|
||||
set_property -dict {LOC D20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_adr[12]}]
|
||||
set_property -dict {LOC A19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_adr[13]}]
|
||||
set_property -dict {LOC B21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_adr[14]}]
|
||||
set_property -dict {LOC D18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_adr[15]}]
|
||||
set_property -dict {LOC C18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_adr[16]}]
|
||||
set_property -dict {LOC B19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_ba[0]}]
|
||||
set_property -dict {LOC C21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_ba[1]}]
|
||||
set_property -dict {LOC B20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_bg[0]}]
|
||||
set_property -dict {LOC A20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_bg[1]}]
|
||||
set_property -dict {LOC E18 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_sodimm_b_ck_t[0]}]
|
||||
set_property -dict {LOC E17 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_sodimm_b_ck_c[0]}]
|
||||
set_property -dict {LOC A18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_cke[0]}]
|
||||
set_property -dict {LOC H21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_cs_n[0]}]
|
||||
#set_property -dict {LOC K13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_cs_n[2]}]
|
||||
#set_property -dict {LOC D14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_cs_n[3]}]
|
||||
set_property -dict {LOC L18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_act_n}]
|
||||
set_property -dict {LOC L19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_odt[0]}]
|
||||
set_property -dict {LOC L20 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_sodimm_b_reset_n}]
|
||||
set_property -dict {LOC C17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_sodimm_b_alert_n}]
|
||||
set_property -dict {LOC F14 IOSTANDARD LVCMOS12 } [get_ports {ddr4_sodimm_b_event_n}]
|
||||
|
||||
set_property -dict {LOC N22 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[0]}]
|
||||
set_property -dict {LOC M25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[1]}]
|
||||
set_property -dict {LOC P23 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[2]}]
|
||||
set_property -dict {LOC P25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[3]}]
|
||||
set_property -dict {LOC R25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[4]}]
|
||||
set_property -dict {LOC M24 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[5]}]
|
||||
set_property -dict {LOC M22 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[6]}]
|
||||
set_property -dict {LOC N23 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[7]}]
|
||||
set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[8]}]
|
||||
set_property -dict {LOC B25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[9]}]
|
||||
set_property -dict {LOC C26 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[10]}]
|
||||
set_property -dict {LOC A24 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[11]}]
|
||||
set_property -dict {LOC C23 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[12]}]
|
||||
set_property -dict {LOC A25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[13]}]
|
||||
set_property -dict {LOC B24 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[14]}]
|
||||
set_property -dict {LOC B26 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[15]}]
|
||||
set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[16]}]
|
||||
set_property -dict {LOC J23 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[17]}]
|
||||
set_property -dict {LOC H23 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[18]}]
|
||||
set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[19]}]
|
||||
set_property -dict {LOC L22 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[20]}]
|
||||
set_property -dict {LOC H24 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[21]}]
|
||||
set_property -dict {LOC L23 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[22]}]
|
||||
set_property -dict {LOC K23 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[23]}]
|
||||
set_property -dict {LOC F23 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[24]}]
|
||||
set_property -dict {LOC F24 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[25]}]
|
||||
set_property -dict {LOC E25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[26]}]
|
||||
set_property -dict {LOC F22 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[27]}]
|
||||
set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[28]}]
|
||||
set_property -dict {LOC D24 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[29]}]
|
||||
set_property -dict {LOC D25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[30]}]
|
||||
set_property -dict {LOC D23 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[31]}]
|
||||
set_property -dict {LOC A13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[32]}]
|
||||
set_property -dict {LOC A17 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[33]}]
|
||||
set_property -dict {LOC B16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[34]}]
|
||||
set_property -dict {LOC C14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[35]}]
|
||||
set_property -dict {LOC A14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[36]}]
|
||||
set_property -dict {LOC B17 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[37]}]
|
||||
set_property -dict {LOC C16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[38]}]
|
||||
set_property -dict {LOC B14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[39]}]
|
||||
set_property -dict {LOC E16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[40]}]
|
||||
set_property -dict {LOC D15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[41]}]
|
||||
set_property -dict {LOC E15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[42]}]
|
||||
set_property -dict {LOC G15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[43]}]
|
||||
set_property -dict {LOC F15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[44]}]
|
||||
set_property -dict {LOC E13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[45]}]
|
||||
set_property -dict {LOC D16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[46]}]
|
||||
set_property -dict {LOC F13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[47]}]
|
||||
set_property -dict {LOC J13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[48]}]
|
||||
set_property -dict {LOC J15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[49]}]
|
||||
set_property -dict {LOC H14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[50]}]
|
||||
set_property -dict {LOC J16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[51]}]
|
||||
set_property -dict {LOC K16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[52]}]
|
||||
set_property -dict {LOC H13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[53]}]
|
||||
set_property -dict {LOC J14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[54]}]
|
||||
set_property -dict {LOC K15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[55]}]
|
||||
set_property -dict {LOC P15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[56]}]
|
||||
set_property -dict {LOC M14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[57]}]
|
||||
set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[58]}]
|
||||
set_property -dict {LOC R15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[59]}]
|
||||
set_property -dict {LOC L14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[60]}]
|
||||
set_property -dict {LOC P14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[61]}]
|
||||
set_property -dict {LOC N16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[62]}]
|
||||
set_property -dict {LOC N14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[63]}]
|
||||
#set_property -dict {LOC J19 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[64]}]
|
||||
#set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[65]}]
|
||||
#set_property -dict {LOC H22 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[66]}]
|
||||
#set_property -dict {LOC G24 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[67]}]
|
||||
#set_property -dict {LOC P21 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[68]}]
|
||||
#set_property -dict {LOC D26 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[69]}]
|
||||
#set_property -dict {LOC C13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[70]}]
|
||||
set_property -dict {LOC P24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_b_dqs_t[0]}]
|
||||
set_property -dict {LOC N24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_b_dqs_c[0]}]
|
||||
set_property -dict {LOC A23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_b_dqs_t[1]}]
|
||||
set_property -dict {LOC A22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_b_dqs_c[1]}]
|
||||
set_property -dict {LOC K25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_b_dqs_t[2]}]
|
||||
set_property -dict {LOC J25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_b_dqs_c[2]}]
|
||||
set_property -dict {LOC E23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_b_dqs_t[3]}]
|
||||
set_property -dict {LOC E22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_b_dqs_c[3]}]
|
||||
set_property -dict {LOC B15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_b_dqs_t[4]}]
|
||||
set_property -dict {LOC A15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_b_dqs_c[4]}]
|
||||
set_property -dict {LOC G17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_b_dqs_t[5]}]
|
||||
set_property -dict {LOC G16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_b_dqs_c[5]}]
|
||||
set_property -dict {LOC H17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_b_dqs_t[6]}]
|
||||
set_property -dict {LOC H16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_b_dqs_c[6]}]
|
||||
set_property -dict {LOC R16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_b_dqs_t[7]}]
|
||||
set_property -dict {LOC P16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_b_dqs_c[7]}]
|
||||
set_property -dict {LOC R21 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dm_dbi_n[0]}]
|
||||
set_property -dict {LOC C22 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dm_dbi_n[1]}]
|
||||
set_property -dict {LOC L25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dm_dbi_n[2]}]
|
||||
set_property -dict {LOC G25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dm_dbi_n[3]}]
|
||||
set_property -dict {LOC D13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dm_dbi_n[4]}]
|
||||
set_property -dict {LOC G14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dm_dbi_n[5]}]
|
||||
set_property -dict {LOC L13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dm_dbi_n[6]}]
|
||||
set_property -dict {LOC P13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dm_dbi_n[7]}]
|
||||
|
||||
@ -9,6 +9,7 @@ FPGA_ARCH = virtexuplus
|
||||
# Files for synthesis
|
||||
SYN_FILES = rtl/fpga.v
|
||||
SYN_FILES += rtl/fpga_core.v
|
||||
SYN_FILES += rtl/bmc_spi.v
|
||||
SYN_FILES += rtl/sync_signal.v
|
||||
SYN_FILES += rtl/common/mqnic_core_pcie_us.v
|
||||
SYN_FILES += rtl/common/mqnic_core_pcie.v
|
||||
@ -114,6 +115,7 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
|
||||
# XDC files
|
||||
XDC_FILES = fpga.xdc
|
||||
XDC_FILES += placement.xdc
|
||||
XDC_FILES += boot.xdc
|
||||
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
|
||||
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
|
||||
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
|
||||
@ -129,6 +131,8 @@ XDC_FILES += ../../../common/syn/vivado/led_sreg_driver.tcl
|
||||
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
|
||||
IP_TCL_FILES += ip/cmac_usplus.tcl
|
||||
IP_TCL_FILES += ip/cmac_gty.tcl
|
||||
#IP_TCL_FILES += ip/ddr4_0.tcl
|
||||
#IP_TCL_FILES += ip/ddr4_sodimm_0.tcl
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
@ -108,6 +108,12 @@ dict set params MAX_RX_SIZE "9214"
|
||||
dict set params TX_RAM_SIZE "131072"
|
||||
dict set params RX_RAM_SIZE "131072"
|
||||
|
||||
# RAM configuration
|
||||
dict set params DDR_CH "4"
|
||||
dict set params DDR_ENABLE "0"
|
||||
dict set params AXI_DDR_ID_WIDTH "8"
|
||||
dict set params AXI_DDR_MAX_BURST_LEN "256"
|
||||
|
||||
# Application block configuration
|
||||
dict set params APP_ID "32'h00000000"
|
||||
dict set params APP_ENABLE "0"
|
||||
@ -151,6 +157,43 @@ dict set params STAT_PCIE_ENABLE "1"
|
||||
dict set params STAT_INC_WIDTH "24"
|
||||
dict set params STAT_ID_WIDTH "12"
|
||||
|
||||
# DDR4 MIG settings
|
||||
if {[dict get $params DDR_ENABLE]} {
|
||||
# components (DDR4 A, DDR4 B)
|
||||
set ddr4 [get_ips ddr4_0]
|
||||
|
||||
# performance-related configuration
|
||||
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
|
||||
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
|
||||
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
|
||||
|
||||
# set AXI ID width
|
||||
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
|
||||
|
||||
# extract AXI configuration
|
||||
dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4]
|
||||
dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4]
|
||||
dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1]
|
||||
|
||||
if {[dict get $params DDR_CH] > 2} {
|
||||
# SO-DIMMs (DDR4 SODMM A, DDR4 SODIMM B)
|
||||
set ddr4 [get_ips ddr4_sodimm_0]
|
||||
|
||||
# performance-related configuration
|
||||
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
|
||||
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
|
||||
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
|
||||
|
||||
# set AXI ID width
|
||||
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
|
||||
|
||||
# extract AXI configuration
|
||||
dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4]
|
||||
dict set params AXI_DDR_ADDR_WIDTH [expr max([get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4], [dict get $params AXI_DDR_ADDR_WIDTH])]
|
||||
dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && [dict get $params AXI_DDR_NARROW_BURST]]
|
||||
}
|
||||
}
|
||||
|
||||
# PCIe IP core settings
|
||||
set pcie [get_ips pcie4_uscale_plus_0]
|
||||
|
||||
|
||||
@ -9,6 +9,7 @@ FPGA_ARCH = virtexuplus
|
||||
# Files for synthesis
|
||||
SYN_FILES = rtl/fpga.v
|
||||
SYN_FILES += rtl/fpga_core.v
|
||||
SYN_FILES += rtl/bmc_spi.v
|
||||
SYN_FILES += rtl/sync_signal.v
|
||||
SYN_FILES += rtl/common/mqnic_core_pcie_us.v
|
||||
SYN_FILES += rtl/common/mqnic_core_pcie.v
|
||||
@ -121,6 +122,7 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
|
||||
# XDC files
|
||||
XDC_FILES = fpga.xdc
|
||||
XDC_FILES += placement.xdc
|
||||
XDC_FILES += boot.xdc
|
||||
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw.tcl
|
||||
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_wr.tcl
|
||||
XDC_FILES += lib/axi/syn/vivado/axi_vfifo_raw_rd.tcl
|
||||
@ -140,6 +142,8 @@ XDC_FILES += app/dma_bench/syn/vivado/dram_test_ch.tcl
|
||||
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
|
||||
IP_TCL_FILES += ip/cmac_usplus.tcl
|
||||
IP_TCL_FILES += ip/cmac_gty.tcl
|
||||
IP_TCL_FILES += ip/ddr4_0.tcl
|
||||
IP_TCL_FILES += ip/ddr4_sodimm_0.tcl
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
@ -108,6 +108,12 @@ dict set params MAX_RX_SIZE "9214"
|
||||
dict set params TX_RAM_SIZE "131072"
|
||||
dict set params RX_RAM_SIZE "131072"
|
||||
|
||||
# RAM configuration
|
||||
dict set params DDR_CH "4"
|
||||
dict set params DDR_ENABLE "1"
|
||||
dict set params AXI_DDR_ID_WIDTH "8"
|
||||
dict set params AXI_DDR_MAX_BURST_LEN "256"
|
||||
|
||||
# Application block configuration
|
||||
dict set params APP_ID "32'h12348001"
|
||||
dict set params APP_ENABLE "1"
|
||||
@ -151,6 +157,43 @@ dict set params STAT_PCIE_ENABLE "1"
|
||||
dict set params STAT_INC_WIDTH "24"
|
||||
dict set params STAT_ID_WIDTH "12"
|
||||
|
||||
# DDR4 MIG settings
|
||||
if {[dict get $params DDR_ENABLE]} {
|
||||
# components (DDR4 A, DDR4 B)
|
||||
set ddr4 [get_ips ddr4_0]
|
||||
|
||||
# performance-related configuration
|
||||
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
|
||||
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
|
||||
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
|
||||
|
||||
# set AXI ID width
|
||||
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
|
||||
|
||||
# extract AXI configuration
|
||||
dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4]
|
||||
dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4]
|
||||
dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1]
|
||||
|
||||
if {[dict get $params DDR_CH] > 2} {
|
||||
# SO-DIMMs (DDR4 SODMM A, DDR4 SODIMM B)
|
||||
set ddr4 [get_ips ddr4_sodimm_0]
|
||||
|
||||
# performance-related configuration
|
||||
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
|
||||
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
|
||||
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
|
||||
|
||||
# set AXI ID width
|
||||
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
|
||||
|
||||
# extract AXI configuration
|
||||
dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4]
|
||||
dict set params AXI_DDR_ADDR_WIDTH [expr max([get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4], [dict get $params AXI_DDR_ADDR_WIDTH])]
|
||||
dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && [dict get $params AXI_DDR_NARROW_BURST]]
|
||||
}
|
||||
}
|
||||
|
||||
# PCIe IP core settings
|
||||
set pcie [get_ips pcie4_uscale_plus_0]
|
||||
|
||||
|
||||
18
fpga/mqnic/fb4CGg3/fpga_100g/ip/ddr4_0.tcl
Normal file
18
fpga/mqnic/fb4CGg3/fpga_100g/ip/ddr4_0.tcl
Normal file
@ -0,0 +1,18 @@
|
||||
|
||||
create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0
|
||||
|
||||
set_property -dict [list \
|
||||
CONFIG.C0.DDR4_AxiSelection {true} \
|
||||
CONFIG.C0.DDR4_AxiDataWidth {512} \
|
||||
CONFIG.C0.DDR4_AxiIDWidth {8} \
|
||||
CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \
|
||||
CONFIG.C0.DDR4_TimePeriod {833} \
|
||||
CONFIG.C0.DDR4_InputClockPeriod {3750} \
|
||||
CONFIG.C0.DDR4_MemoryType {Components} \
|
||||
CONFIG.C0.DDR4_MemoryPart {MT40A512M16HA-083E} \
|
||||
CONFIG.C0.DDR4_DataWidth {64} \
|
||||
CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \
|
||||
CONFIG.C0.DDR4_CasLatency {16} \
|
||||
CONFIG.C0.DDR4_CasWriteLatency {12} \
|
||||
CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV}
|
||||
] [get_ips ddr4_0]
|
||||
18
fpga/mqnic/fb4CGg3/fpga_100g/ip/ddr4_sodimm_0.tcl
Normal file
18
fpga/mqnic/fb4CGg3/fpga_100g/ip/ddr4_sodimm_0.tcl
Normal file
@ -0,0 +1,18 @@
|
||||
|
||||
create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_sodimm_0
|
||||
|
||||
set_property -dict [list \
|
||||
CONFIG.C0.DDR4_AxiSelection {true} \
|
||||
CONFIG.C0.DDR4_AxiDataWidth {512} \
|
||||
CONFIG.C0.DDR4_AxiIDWidth {8} \
|
||||
CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \
|
||||
CONFIG.C0.DDR4_TimePeriod {833} \
|
||||
CONFIG.C0.DDR4_InputClockPeriod {3750} \
|
||||
CONFIG.C0.DDR4_MemoryType {SODIMMs} \
|
||||
CONFIG.C0.DDR4_MemoryPart {MTA8ATF1G64HZ-2G3} \
|
||||
CONFIG.C0.DDR4_DataWidth {64} \
|
||||
CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \
|
||||
CONFIG.C0.DDR4_CasLatency {17} \
|
||||
CONFIG.C0.DDR4_CasWriteLatency {12} \
|
||||
CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV}
|
||||
] [get_ips ddr4_sodimm_0]
|
||||
262
fpga/mqnic/fb4CGg3/fpga_100g/rtl/bmc_spi.v
Normal file
262
fpga/mqnic/fb4CGg3/fpga_100g/rtl/bmc_spi.v
Normal file
@ -0,0 +1,262 @@
|
||||
// SPDX-License-Identifier: BSD-2-Clause-Views
|
||||
/*
|
||||
* Copyright (c) 2021-2023 The Regents of the University of California
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* Board management controller interface
|
||||
*/
|
||||
module bmc_spi #(
|
||||
// clock prescale (SPI clock half period in cycles of clk)
|
||||
parameter PRESCALE = 125,
|
||||
// byte wait time (SPI clock cycles)
|
||||
parameter BYTE_WAIT = 32,
|
||||
// timeout (SPI clock cycles)
|
||||
parameter TIMEOUT = 5000
|
||||
)
|
||||
(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
input wire [15:0] ctrl_cmd,
|
||||
input wire [31:0] ctrl_data,
|
||||
input wire ctrl_valid,
|
||||
|
||||
output wire [15:0] read_data,
|
||||
|
||||
output wire status_idle,
|
||||
output wire status_done,
|
||||
output wire status_timeout,
|
||||
|
||||
output wire bmc_clk,
|
||||
output wire bmc_nss,
|
||||
output wire bmc_mosi,
|
||||
input wire bmc_miso,
|
||||
input wire bmc_int
|
||||
);
|
||||
|
||||
localparam CL_PRESCALE = $clog2(PRESCALE+1);
|
||||
localparam CL_DELAY = $clog2((BYTE_WAIT > TIMEOUT ? BYTE_WAIT : TIMEOUT)+1);
|
||||
|
||||
/*
|
||||
|
||||
SPI protocol:
|
||||
|
||||
8 byte transfer, MSB first
|
||||
|
||||
2 byte command
|
||||
4 byte data
|
||||
wait for int
|
||||
2 byte read data
|
||||
|
||||
nss deasserted between each byte
|
||||
wait 32 SPI cycle times between bytes
|
||||
wait up to 5 ms for int assert from bmc
|
||||
|
||||
*/
|
||||
|
||||
localparam [2:0]
|
||||
STATE_IDLE = 3'd0,
|
||||
STATE_SHIFT = 3'd1,
|
||||
STATE_WAIT_BYTE = 3'd2,
|
||||
STATE_WAIT_INT = 3'd3;
|
||||
|
||||
reg [2:0] state_reg = STATE_IDLE, state_next;
|
||||
|
||||
reg [15:0] read_data_reg = 15'd0, read_data_next;
|
||||
|
||||
reg status_idle_reg = 1'b0;
|
||||
reg status_done_reg = 1'b0, status_done_next;
|
||||
reg status_timeout_reg = 1'b0, status_timeout_next;
|
||||
|
||||
reg bmc_clk_reg = 1'b1, bmc_clk_next;
|
||||
reg bmc_nss_reg = 1'b1, bmc_nss_next;
|
||||
reg bmc_mosi_reg = 1'b1, bmc_mosi_next;
|
||||
reg bmc_miso_reg = 1'b1;
|
||||
reg bmc_int_reg = 1'b0;
|
||||
|
||||
reg [CL_PRESCALE+1-1:0] prescale_count_reg = 0, prescale_count_next;
|
||||
reg [CL_DELAY-1:0] delay_count_reg = 0, delay_count_next;
|
||||
reg [3:0] bit_count_reg = 0, bit_count_next;
|
||||
reg [3:0] byte_count_reg = 0, byte_count_next;
|
||||
reg [47:0] data_out_reg = 0, data_out_next;
|
||||
reg [15:0] data_in_reg = 0, data_in_next;
|
||||
reg int_reg = 0, int_next;
|
||||
|
||||
assign read_data = read_data_reg;
|
||||
|
||||
assign status_idle = status_idle_reg;
|
||||
assign status_done = status_done_reg;
|
||||
assign status_timeout = status_timeout_reg;
|
||||
|
||||
assign bmc_clk = bmc_clk_reg;
|
||||
assign bmc_nss = bmc_nss_reg;
|
||||
assign bmc_mosi = bmc_mosi_reg;
|
||||
|
||||
always @* begin
|
||||
state_next = state_reg;
|
||||
|
||||
read_data_next = read_data_reg;
|
||||
|
||||
status_done_next = status_done_reg;
|
||||
status_timeout_next = status_timeout_reg;
|
||||
|
||||
bmc_clk_next = bmc_clk_reg;
|
||||
bmc_nss_next = bmc_nss_reg;
|
||||
bmc_mosi_next = bmc_mosi_reg;
|
||||
|
||||
prescale_count_next = prescale_count_reg;
|
||||
delay_count_next = delay_count_reg;
|
||||
bit_count_next = bit_count_reg;
|
||||
byte_count_next = byte_count_reg;
|
||||
data_out_next = data_out_reg;
|
||||
data_in_next = data_in_reg;
|
||||
int_next = int_reg;
|
||||
|
||||
if (prescale_count_reg != 0) begin
|
||||
prescale_count_next = prescale_count_reg - 1;
|
||||
end else if (bmc_clk_reg == 1'b0) begin
|
||||
bmc_clk_next = 1'b1;
|
||||
prescale_count_next = PRESCALE;
|
||||
end else if (delay_count_reg != 0) begin
|
||||
delay_count_next = delay_count_reg - 1;
|
||||
prescale_count_next = PRESCALE*2;
|
||||
end
|
||||
|
||||
if (bmc_int_reg) begin
|
||||
int_next = 1'b1;
|
||||
end
|
||||
|
||||
case (state_reg)
|
||||
STATE_IDLE: begin
|
||||
bmc_clk_next = 1'b1;
|
||||
bmc_nss_next = 1'b1;
|
||||
|
||||
prescale_count_next = 0;
|
||||
delay_count_next = 0;
|
||||
bit_count_next = 8;
|
||||
byte_count_next = 8;
|
||||
data_out_next = {ctrl_cmd, ctrl_data};
|
||||
int_next = 1'b0;
|
||||
|
||||
if (ctrl_valid) begin
|
||||
status_done_next = 1'b0;
|
||||
status_timeout_next = 1'b0;
|
||||
bmc_nss_next = 1'b0;
|
||||
prescale_count_next = PRESCALE*2;
|
||||
state_next = STATE_SHIFT;
|
||||
end
|
||||
end
|
||||
STATE_SHIFT: begin
|
||||
if (prescale_count_reg == 0 && bmc_clk_reg) begin
|
||||
if (bit_count_reg != 8) begin
|
||||
// shift in bit
|
||||
data_in_next = {data_in_reg, bmc_miso_reg};
|
||||
end
|
||||
|
||||
if (bit_count_reg != 0) begin
|
||||
// more bits to send; send the next bit
|
||||
bmc_clk_next = 1'b0;
|
||||
prescale_count_next = PRESCALE;
|
||||
bit_count_next = bit_count_reg - 1;
|
||||
{bmc_mosi_next, data_out_next} = {data_out_reg, 1'b0};
|
||||
state_next = STATE_SHIFT;
|
||||
end else begin
|
||||
// at the end of the byte; small delay
|
||||
bmc_nss_next = 1'b1;
|
||||
delay_count_next = BYTE_WAIT;
|
||||
bit_count_next = 8;
|
||||
byte_count_next = byte_count_reg - 1;
|
||||
state_next = STATE_WAIT_BYTE;
|
||||
end
|
||||
end else begin
|
||||
state_next = STATE_SHIFT;
|
||||
end
|
||||
end
|
||||
STATE_WAIT_BYTE: begin
|
||||
// byte wait state; wait for delay timer
|
||||
if (delay_count_reg == 0) begin
|
||||
if (byte_count_reg == 2) begin
|
||||
// command sent; wait for int from BMC
|
||||
delay_count_next = TIMEOUT;
|
||||
state_next = STATE_WAIT_INT;
|
||||
end else if (byte_count_reg == 0) begin
|
||||
// done with operation; return to idle
|
||||
read_data_next = data_in_reg;
|
||||
status_done_next = 1'b1;
|
||||
state_next = STATE_IDLE;
|
||||
end else begin
|
||||
// not at end of command; send next byte
|
||||
bmc_nss_next = 1'b0;
|
||||
prescale_count_next = PRESCALE*2;
|
||||
state_next = STATE_SHIFT;
|
||||
end
|
||||
end else begin
|
||||
state_next = STATE_WAIT_BYTE;
|
||||
end
|
||||
end
|
||||
STATE_WAIT_INT: begin
|
||||
// wait for int from BMC
|
||||
if (int_reg) begin
|
||||
// got int, go back to shift state
|
||||
bmc_nss_next = 1'b0;
|
||||
prescale_count_next = PRESCALE*2;
|
||||
state_next = STATE_SHIFT;
|
||||
end else if (delay_count_reg == 0) begin
|
||||
// timed out waiting for BMC
|
||||
status_timeout_next = 1'b1;
|
||||
bmc_nss_next = 1'b0;
|
||||
prescale_count_next = PRESCALE*2;
|
||||
state_next = STATE_SHIFT;
|
||||
end else begin
|
||||
state_next = STATE_WAIT_INT;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
state_reg <= state_next;
|
||||
|
||||
read_data_reg <= read_data_next;
|
||||
|
||||
status_idle_reg <= state_next == STATE_IDLE;
|
||||
status_done_reg <= status_done_next;
|
||||
status_timeout_reg <= status_timeout_next;
|
||||
|
||||
bmc_clk_reg <= bmc_clk_next;
|
||||
bmc_nss_reg <= bmc_nss_next;
|
||||
bmc_mosi_reg <= bmc_mosi_next;
|
||||
bmc_miso_reg <= bmc_miso;
|
||||
bmc_int_reg <= bmc_int;
|
||||
|
||||
prescale_count_reg <= prescale_count_next;
|
||||
delay_count_reg <= delay_count_next;
|
||||
bit_count_reg <= bit_count_next;
|
||||
byte_count_reg <= byte_count_next;
|
||||
data_out_reg <= data_out_next;
|
||||
data_in_reg <= data_in_next;
|
||||
int_reg <= int_next;
|
||||
|
||||
if (rst) begin
|
||||
state_reg <= STATE_IDLE;
|
||||
|
||||
status_idle_reg <= 1'b0;
|
||||
status_done_reg <= 1'b0;
|
||||
status_timeout_reg <= 1'b0;
|
||||
|
||||
bmc_clk_reg <= 1'b1;
|
||||
bmc_nss_reg <= 1'b1;
|
||||
bmc_mosi_reg <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
@ -140,6 +140,14 @@ module fpga #
|
||||
* Clock: 100MHz
|
||||
*/
|
||||
input wire init_clk,
|
||||
input wire clk_ddr4_a_refclk_p,
|
||||
input wire clk_ddr4_a_refclk_n,
|
||||
input wire clk_ddr4_b_refclk_p,
|
||||
input wire clk_ddr4_b_refclk_n,
|
||||
input wire clk_sodimm_a_refclk_p,
|
||||
input wire clk_sodimm_a_refclk_n,
|
||||
input wire clk_sodimm_b_refclk_p,
|
||||
input wire clk_sodimm_b_refclk_n,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
@ -153,6 +161,14 @@ module fpga #
|
||||
input wire pps_in,
|
||||
output wire pps_out,
|
||||
|
||||
/*
|
||||
* BMC interface
|
||||
*/
|
||||
output wire bmc_clk,
|
||||
output wire bmc_nss,
|
||||
output wire bmc_mosi,
|
||||
input wire bmc_miso,
|
||||
|
||||
/*
|
||||
* PCI express
|
||||
*/
|
||||
@ -265,7 +281,76 @@ module fpga #
|
||||
output wire qsfp_3_lp_mode,
|
||||
input wire qsfp_3_intr_n,
|
||||
inout wire qsfp_3_i2c_scl,
|
||||
inout wire qsfp_3_i2c_sda
|
||||
inout wire qsfp_3_i2c_sda,
|
||||
|
||||
/*
|
||||
* DDR4
|
||||
*/
|
||||
output wire [16:0] ddr4_a_adr,
|
||||
output wire [1:0] ddr4_a_ba,
|
||||
output wire [1:0] ddr4_a_bg,
|
||||
output wire [0:0] ddr4_a_ck_t,
|
||||
output wire [0:0] ddr4_a_ck_c,
|
||||
output wire [0:0] ddr4_a_cke,
|
||||
output wire [0:0] ddr4_a_cs_n,
|
||||
output wire ddr4_a_act_n,
|
||||
output wire [0:0] ddr4_a_odt,
|
||||
output wire ddr4_a_reset_n,
|
||||
output wire ddr4_a_ten,
|
||||
inout wire [63:0] ddr4_a_dq,
|
||||
inout wire [7:0] ddr4_a_dqs_t,
|
||||
inout wire [7:0] ddr4_a_dqs_c,
|
||||
inout wire [7:0] ddr4_a_dm_dbi_n,
|
||||
|
||||
output wire [16:0] ddr4_b_adr,
|
||||
output wire [1:0] ddr4_b_ba,
|
||||
output wire [1:0] ddr4_b_bg,
|
||||
output wire [0:0] ddr4_b_ck_t,
|
||||
output wire [0:0] ddr4_b_ck_c,
|
||||
output wire [0:0] ddr4_b_cke,
|
||||
output wire [0:0] ddr4_b_cs_n,
|
||||
output wire ddr4_b_act_n,
|
||||
output wire [0:0] ddr4_b_odt,
|
||||
output wire ddr4_b_reset_n,
|
||||
output wire ddr4_b_ten,
|
||||
inout wire [63:0] ddr4_b_dq,
|
||||
inout wire [7:0] ddr4_b_dqs_t,
|
||||
inout wire [7:0] ddr4_b_dqs_c,
|
||||
inout wire [7:0] ddr4_b_dm_dbi_n,
|
||||
|
||||
output wire [16:0] ddr4_sodimm_a_adr,
|
||||
output wire [1:0] ddr4_sodimm_a_ba,
|
||||
output wire [1:0] ddr4_sodimm_a_bg,
|
||||
output wire [0:0] ddr4_sodimm_a_ck_t,
|
||||
output wire [0:0] ddr4_sodimm_a_ck_c,
|
||||
output wire [0:0] ddr4_sodimm_a_cke,
|
||||
output wire [0:0] ddr4_sodimm_a_cs_n,
|
||||
output wire ddr4_sodimm_a_act_n,
|
||||
output wire [0:0] ddr4_sodimm_a_odt,
|
||||
output wire ddr4_sodimm_a_reset_n,
|
||||
input wire ddr4_sodimm_a_alert_n,
|
||||
input wire ddr4_sodimm_a_event_n,
|
||||
inout wire [63:0] ddr4_sodimm_a_dq,
|
||||
inout wire [7:0] ddr4_sodimm_a_dqs_t,
|
||||
inout wire [7:0] ddr4_sodimm_a_dqs_c,
|
||||
inout wire [7:0] ddr4_sodimm_a_dm_dbi_n,
|
||||
|
||||
output wire [16:0] ddr4_sodimm_b_adr,
|
||||
output wire [1:0] ddr4_sodimm_b_ba,
|
||||
output wire [1:0] ddr4_sodimm_b_bg,
|
||||
output wire [0:0] ddr4_sodimm_b_ck_t,
|
||||
output wire [0:0] ddr4_sodimm_b_ck_c,
|
||||
output wire [0:0] ddr4_sodimm_b_cke,
|
||||
output wire [0:0] ddr4_sodimm_b_cs_n,
|
||||
output wire ddr4_sodimm_b_act_n,
|
||||
output wire [0:0] ddr4_sodimm_b_odt,
|
||||
output wire ddr4_sodimm_b_reset_n,
|
||||
input wire ddr4_sodimm_b_alert_n,
|
||||
input wire ddr4_sodimm_b_event_n,
|
||||
inout wire [63:0] ddr4_sodimm_b_dq,
|
||||
inout wire [7:0] ddr4_sodimm_b_dqs_t,
|
||||
inout wire [7:0] ddr4_sodimm_b_dqs_c,
|
||||
inout wire [7:0] ddr4_sodimm_b_dm_dbi_n
|
||||
);
|
||||
|
||||
// PTP configuration
|
||||
@ -278,6 +363,9 @@ parameter PTP_SEPARATE_RX_CLOCK = 1;
|
||||
// Interface configuration
|
||||
parameter TX_TAG_WIDTH = 16;
|
||||
|
||||
// RAM configuration
|
||||
parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8);
|
||||
|
||||
// PCIe interface configuration
|
||||
parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32);
|
||||
parameter AXIS_PCIE_RC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 75 : 161;
|
||||
@ -509,6 +597,121 @@ led_sreg_driver_inst (
|
||||
.sreg_clk(led_sreg_clk)
|
||||
);
|
||||
|
||||
// FPGA boot
|
||||
wire fpga_boot;
|
||||
|
||||
reg fpga_boot_sync_reg_0 = 1'b0;
|
||||
reg fpga_boot_sync_reg_1 = 1'b0;
|
||||
reg fpga_boot_sync_reg_2 = 1'b0;
|
||||
|
||||
wire icap_avail;
|
||||
reg [2:0] icap_state = 0;
|
||||
reg icap_csib_reg = 1'b1;
|
||||
reg icap_rdwrb_reg = 1'b0;
|
||||
reg [31:0] icap_di_reg = 32'hffffffff;
|
||||
|
||||
wire [31:0] icap_di_rev;
|
||||
|
||||
assign icap_di_rev[ 7] = icap_di_reg[ 0];
|
||||
assign icap_di_rev[ 6] = icap_di_reg[ 1];
|
||||
assign icap_di_rev[ 5] = icap_di_reg[ 2];
|
||||
assign icap_di_rev[ 4] = icap_di_reg[ 3];
|
||||
assign icap_di_rev[ 3] = icap_di_reg[ 4];
|
||||
assign icap_di_rev[ 2] = icap_di_reg[ 5];
|
||||
assign icap_di_rev[ 1] = icap_di_reg[ 6];
|
||||
assign icap_di_rev[ 0] = icap_di_reg[ 7];
|
||||
|
||||
assign icap_di_rev[15] = icap_di_reg[ 8];
|
||||
assign icap_di_rev[14] = icap_di_reg[ 9];
|
||||
assign icap_di_rev[13] = icap_di_reg[10];
|
||||
assign icap_di_rev[12] = icap_di_reg[11];
|
||||
assign icap_di_rev[11] = icap_di_reg[12];
|
||||
assign icap_di_rev[10] = icap_di_reg[13];
|
||||
assign icap_di_rev[ 9] = icap_di_reg[14];
|
||||
assign icap_di_rev[ 8] = icap_di_reg[15];
|
||||
|
||||
assign icap_di_rev[23] = icap_di_reg[16];
|
||||
assign icap_di_rev[22] = icap_di_reg[17];
|
||||
assign icap_di_rev[21] = icap_di_reg[18];
|
||||
assign icap_di_rev[20] = icap_di_reg[19];
|
||||
assign icap_di_rev[19] = icap_di_reg[20];
|
||||
assign icap_di_rev[18] = icap_di_reg[21];
|
||||
assign icap_di_rev[17] = icap_di_reg[22];
|
||||
assign icap_di_rev[16] = icap_di_reg[23];
|
||||
|
||||
assign icap_di_rev[31] = icap_di_reg[24];
|
||||
assign icap_di_rev[30] = icap_di_reg[25];
|
||||
assign icap_di_rev[29] = icap_di_reg[26];
|
||||
assign icap_di_rev[28] = icap_di_reg[27];
|
||||
assign icap_di_rev[27] = icap_di_reg[28];
|
||||
assign icap_di_rev[26] = icap_di_reg[29];
|
||||
assign icap_di_rev[25] = icap_di_reg[30];
|
||||
assign icap_di_rev[24] = icap_di_reg[31];
|
||||
|
||||
always @(posedge clk_125mhz_int) begin
|
||||
case (icap_state)
|
||||
0: begin
|
||||
icap_state <= 0;
|
||||
icap_csib_reg <= 1'b1;
|
||||
icap_rdwrb_reg <= 1'b0;
|
||||
icap_di_reg <= 32'hffffffff; // dummy word
|
||||
|
||||
if (fpga_boot_sync_reg_2 && icap_avail) begin
|
||||
icap_state <= 1;
|
||||
icap_csib_reg <= 1'b0;
|
||||
icap_rdwrb_reg <= 1'b0;
|
||||
icap_di_reg <= 32'hffffffff; // dummy word
|
||||
end
|
||||
end
|
||||
1: begin
|
||||
icap_state <= 2;
|
||||
icap_csib_reg <= 1'b0;
|
||||
icap_rdwrb_reg <= 1'b0;
|
||||
icap_di_reg <= 32'hAA995566; // sync word
|
||||
end
|
||||
2: begin
|
||||
icap_state <= 3;
|
||||
icap_csib_reg <= 1'b0;
|
||||
icap_rdwrb_reg <= 1'b0;
|
||||
icap_di_reg <= 32'h20000000; // type 1 noop
|
||||
end
|
||||
3: begin
|
||||
icap_state <= 4;
|
||||
icap_csib_reg <= 1'b0;
|
||||
icap_rdwrb_reg <= 1'b0;
|
||||
icap_di_reg <= 32'h30008001; // write 1 word to CMD
|
||||
end
|
||||
4: begin
|
||||
icap_state <= 5;
|
||||
icap_csib_reg <= 1'b0;
|
||||
icap_rdwrb_reg <= 1'b0;
|
||||
icap_di_reg <= 32'h0000000F; // IPROG
|
||||
end
|
||||
5: begin
|
||||
icap_state <= 0;
|
||||
icap_csib_reg <= 1'b0;
|
||||
icap_rdwrb_reg <= 1'b0;
|
||||
icap_di_reg <= 32'h20000000; // type 1 noop
|
||||
end
|
||||
endcase
|
||||
|
||||
fpga_boot_sync_reg_0 <= fpga_boot;
|
||||
fpga_boot_sync_reg_1 <= fpga_boot_sync_reg_0;
|
||||
fpga_boot_sync_reg_2 <= fpga_boot_sync_reg_1;
|
||||
end
|
||||
|
||||
ICAPE3
|
||||
icape3_inst (
|
||||
.AVAIL(icap_avail),
|
||||
.CLK(clk_125mhz_int),
|
||||
.CSIB(icap_csib_reg),
|
||||
.I(icap_di_rev),
|
||||
.O(),
|
||||
.PRDONE(),
|
||||
.PRERROR(),
|
||||
.RDWRB(icap_rdwrb_reg)
|
||||
);
|
||||
|
||||
// PCIe
|
||||
wire pcie_sys_clk;
|
||||
wire pcie_sys_clk_gt;
|
||||
@ -1411,6 +1614,491 @@ assign led_green[11:9] = 0;
|
||||
assign led_green[12] = qsfp_3_rx_status;
|
||||
assign led_green[15:13] = 0;
|
||||
|
||||
// DDR4
|
||||
wire [DDR_CH-1:0] ddr_clk;
|
||||
wire [DDR_CH-1:0] ddr_rst;
|
||||
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid;
|
||||
wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr;
|
||||
wire [DDR_CH*8-1:0] m_axi_ddr_awlen;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_awsize;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_awburst;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_awlock;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_awcache;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_awprot;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_awqos;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_awvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_awready;
|
||||
wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata;
|
||||
wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_wlast;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_wvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_wready;
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_bresp;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_bvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_bready;
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid;
|
||||
wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr;
|
||||
wire [DDR_CH*8-1:0] m_axi_ddr_arlen;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_arsize;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_arburst;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_arlock;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_arcache;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_arprot;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_arqos;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_arvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_arready;
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid;
|
||||
wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_rresp;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_rlast;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_rvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_rready;
|
||||
|
||||
wire [DDR_CH-1:0] ddr_status;
|
||||
|
||||
generate
|
||||
|
||||
if (DDR_ENABLE && DDR_CH > 0) begin
|
||||
|
||||
reg ddr4_rst_reg = 1'b1;
|
||||
|
||||
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
|
||||
if (pcie_user_reset) begin
|
||||
ddr4_rst_reg <= 1'b1;
|
||||
end else begin
|
||||
ddr4_rst_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
ddr4_0 ddr4_a_inst (
|
||||
.c0_sys_clk_p(clk_ddr4_a_refclk_p),
|
||||
.c0_sys_clk_n(clk_ddr4_a_refclk_n),
|
||||
.sys_rst(ddr4_rst_reg),
|
||||
|
||||
.c0_init_calib_complete(ddr_status[0 +: 1]),
|
||||
.dbg_clk(),
|
||||
.dbg_bus(),
|
||||
|
||||
.c0_ddr4_adr(ddr4_a_adr),
|
||||
.c0_ddr4_ba(ddr4_a_ba),
|
||||
.c0_ddr4_cke(ddr4_a_cke),
|
||||
.c0_ddr4_cs_n(ddr4_a_cs_n),
|
||||
.c0_ddr4_dq(ddr4_a_dq),
|
||||
.c0_ddr4_dqs_t(ddr4_a_dqs_t),
|
||||
.c0_ddr4_dqs_c(ddr4_a_dqs_c),
|
||||
.c0_ddr4_dm_dbi_n(ddr4_a_dm_dbi_n),
|
||||
.c0_ddr4_odt(ddr4_a_odt),
|
||||
.c0_ddr4_bg(ddr4_a_bg),
|
||||
.c0_ddr4_reset_n(ddr4_a_reset_n),
|
||||
.c0_ddr4_act_n(ddr4_a_act_n),
|
||||
.c0_ddr4_ck_t(ddr4_a_ck_t),
|
||||
.c0_ddr4_ck_c(ddr4_a_ck_c),
|
||||
|
||||
.c0_ddr4_ui_clk(ddr_clk[0 +: 1]),
|
||||
.c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]),
|
||||
|
||||
.c0_ddr4_aresetn(!ddr_rst[0 +: 1]),
|
||||
|
||||
.c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]),
|
||||
.c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]),
|
||||
.c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]),
|
||||
.c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]),
|
||||
.c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]),
|
||||
.c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]),
|
||||
.c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]),
|
||||
.c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH])
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign ddr4_a_adr = {17{1'bz}};
|
||||
assign ddr4_a_ba = {2{1'bz}};
|
||||
assign ddr4_a_bg = {2{1'bz}};
|
||||
assign ddr4_a_cke = 1'bz;
|
||||
assign ddr4_a_cs_n = 1'bz;
|
||||
assign ddr4_a_act_n = 1'bz;
|
||||
assign ddr4_a_odt = 1'bz;
|
||||
assign ddr4_a_reset_n = 1'b0;
|
||||
assign ddr4_a_dq = {64{1'bz}};
|
||||
assign ddr4_a_dqs_t = {8{1'bz}};
|
||||
assign ddr4_a_dqs_c = {8{1'bz}};
|
||||
assign ddr4_a_dm_dbi_n = {8{1'bz}};
|
||||
|
||||
OBUFTDS ddr4_a_ck_obuftds_inst (
|
||||
.I(1'b0),
|
||||
.T(1'b1),
|
||||
.O(ddr4_a_ck_t),
|
||||
.OB(ddr4_a_ck_c)
|
||||
);
|
||||
|
||||
assign ddr_clk = 0;
|
||||
assign ddr_rst = 0;
|
||||
|
||||
assign m_axi_ddr_awready = 0;
|
||||
assign m_axi_ddr_wready = 0;
|
||||
assign m_axi_ddr_bid = 0;
|
||||
assign m_axi_ddr_bresp = 0;
|
||||
assign m_axi_ddr_bvalid = 0;
|
||||
assign m_axi_ddr_arready = 0;
|
||||
assign m_axi_ddr_rid = 0;
|
||||
assign m_axi_ddr_rdata = 0;
|
||||
assign m_axi_ddr_rresp = 0;
|
||||
assign m_axi_ddr_rlast = 0;
|
||||
assign m_axi_ddr_rvalid = 0;
|
||||
|
||||
assign ddr_status = 0;
|
||||
|
||||
end
|
||||
|
||||
assign ddr4_a_ten = 1'b0;
|
||||
|
||||
if (DDR_ENABLE && DDR_CH > 1) begin
|
||||
|
||||
reg ddr4_rst_reg = 1'b1;
|
||||
|
||||
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
|
||||
if (pcie_user_reset) begin
|
||||
ddr4_rst_reg <= 1'b1;
|
||||
end else begin
|
||||
ddr4_rst_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
ddr4_0 ddr4_b_inst (
|
||||
.c0_sys_clk_p(clk_ddr4_b_refclk_p),
|
||||
.c0_sys_clk_n(clk_ddr4_b_refclk_n),
|
||||
.sys_rst(ddr4_rst_reg),
|
||||
|
||||
.c0_init_calib_complete(ddr_status[1 +: 1]),
|
||||
.dbg_clk(),
|
||||
.dbg_bus(),
|
||||
|
||||
.c0_ddr4_adr(ddr4_b_adr),
|
||||
.c0_ddr4_ba(ddr4_b_ba),
|
||||
.c0_ddr4_cke(ddr4_b_cke),
|
||||
.c0_ddr4_cs_n(ddr4_b_cs_n),
|
||||
.c0_ddr4_dq(ddr4_b_dq),
|
||||
.c0_ddr4_dqs_t(ddr4_b_dqs_t),
|
||||
.c0_ddr4_dqs_c(ddr4_b_dqs_c),
|
||||
.c0_ddr4_dm_dbi_n(ddr4_b_dm_dbi_n),
|
||||
.c0_ddr4_odt(ddr4_b_odt),
|
||||
.c0_ddr4_bg(ddr4_b_bg),
|
||||
.c0_ddr4_reset_n(ddr4_b_reset_n),
|
||||
.c0_ddr4_act_n(ddr4_b_act_n),
|
||||
.c0_ddr4_ck_t(ddr4_b_ck_t),
|
||||
.c0_ddr4_ck_c(ddr4_b_ck_c),
|
||||
|
||||
.c0_ddr4_ui_clk(ddr_clk[1 +: 1]),
|
||||
.c0_ddr4_ui_clk_sync_rst(ddr_rst[1 +: 1]),
|
||||
|
||||
.c0_ddr4_aresetn(!ddr_rst[1 +: 1]),
|
||||
|
||||
.c0_ddr4_s_axi_awid(m_axi_ddr_awid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[1*8 +: 8]),
|
||||
.c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[1*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[1*2 +: 2]),
|
||||
.c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[1 +: 1]),
|
||||
.c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[1*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[1*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[1*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_awready(m_axi_ddr_awready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]),
|
||||
.c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[1*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]),
|
||||
.c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[1 +: 1]),
|
||||
.c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_wready(m_axi_ddr_wready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_bready(m_axi_ddr_bready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_bid(m_axi_ddr_bid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[1*2 +: 2]),
|
||||
.c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_arid(m_axi_ddr_arid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[1*8 +: 8]),
|
||||
.c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[1*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[1*2 +: 2]),
|
||||
.c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[1 +: 1]),
|
||||
.c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[1*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[1*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[1*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_arready(m_axi_ddr_arready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_rready(m_axi_ddr_rready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[1 +: 1]),
|
||||
.c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[1*2 +: 2]),
|
||||
.c0_ddr4_s_axi_rid(m_axi_ddr_rid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH])
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign ddr4_b_adr = {17{1'bz}};
|
||||
assign ddr4_b_ba = {2{1'bz}};
|
||||
assign ddr4_b_bg = {2{1'bz}};
|
||||
assign ddr4_b_cke = 1'bz;
|
||||
assign ddr4_b_cs_n = 1'bz;
|
||||
assign ddr4_b_act_n = 1'bz;
|
||||
assign ddr4_b_odt = 1'bz;
|
||||
assign ddr4_b_reset_n = 1'b0;
|
||||
assign ddr4_b_dq = {64{1'bz}};
|
||||
assign ddr4_b_dqs_t = {8{1'bz}};
|
||||
assign ddr4_b_dqs_c = {8{1'bz}};
|
||||
assign ddr4_b_dm_dbi_n = {8{1'bz}};
|
||||
|
||||
OBUFTDS ddr4_b_ck_obuftds_inst (
|
||||
.I(1'b0),
|
||||
.T(1'b1),
|
||||
.O(ddr4_b_ck_t),
|
||||
.OB(ddr4_b_ck_c)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
assign ddr4_b_ten = 1'b0;
|
||||
|
||||
if (DDR_ENABLE && DDR_CH > 2) begin
|
||||
|
||||
reg ddr4_rst_reg = 1'b1;
|
||||
|
||||
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
|
||||
if (pcie_user_reset) begin
|
||||
ddr4_rst_reg <= 1'b1;
|
||||
end else begin
|
||||
ddr4_rst_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
ddr4_sodimm_0 ddr4_sodimm_a_inst (
|
||||
.c0_sys_clk_p(clk_sodimm_a_refclk_p),
|
||||
.c0_sys_clk_n(clk_sodimm_a_refclk_n),
|
||||
.sys_rst(ddr4_rst_reg),
|
||||
|
||||
.c0_init_calib_complete(ddr_status[2 +: 1]),
|
||||
.dbg_clk(),
|
||||
.dbg_bus(),
|
||||
|
||||
.c0_ddr4_adr(ddr4_sodimm_a_adr),
|
||||
.c0_ddr4_ba(ddr4_sodimm_a_ba),
|
||||
.c0_ddr4_cke(ddr4_sodimm_a_cke),
|
||||
.c0_ddr4_cs_n(ddr4_sodimm_a_cs_n),
|
||||
.c0_ddr4_dq(ddr4_sodimm_a_dq),
|
||||
.c0_ddr4_dqs_t(ddr4_sodimm_a_dqs_t),
|
||||
.c0_ddr4_dqs_c(ddr4_sodimm_a_dqs_c),
|
||||
.c0_ddr4_dm_dbi_n(ddr4_sodimm_a_dm_dbi_n),
|
||||
.c0_ddr4_odt(ddr4_sodimm_a_odt),
|
||||
.c0_ddr4_bg(ddr4_sodimm_a_bg),
|
||||
.c0_ddr4_reset_n(ddr4_sodimm_a_reset_n),
|
||||
.c0_ddr4_act_n(ddr4_sodimm_a_act_n),
|
||||
.c0_ddr4_ck_t(ddr4_sodimm_a_ck_t),
|
||||
.c0_ddr4_ck_c(ddr4_sodimm_a_ck_c),
|
||||
|
||||
.c0_ddr4_ui_clk(ddr_clk[2 +: 1]),
|
||||
.c0_ddr4_ui_clk_sync_rst(ddr_rst[2 +: 1]),
|
||||
|
||||
.c0_ddr4_aresetn(!ddr_rst[2 +: 1]),
|
||||
|
||||
.c0_ddr4_s_axi_awid(m_axi_ddr_awid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[2*8 +: 8]),
|
||||
.c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[2*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[2*2 +: 2]),
|
||||
.c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[2 +: 1]),
|
||||
.c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[2*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[2*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[2*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[2 +: 1]),
|
||||
.c0_ddr4_s_axi_awready(m_axi_ddr_awready[2 +: 1]),
|
||||
.c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]),
|
||||
.c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[2*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]),
|
||||
.c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[2 +: 1]),
|
||||
.c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[2 +: 1]),
|
||||
.c0_ddr4_s_axi_wready(m_axi_ddr_wready[2 +: 1]),
|
||||
.c0_ddr4_s_axi_bready(m_axi_ddr_bready[2 +: 1]),
|
||||
.c0_ddr4_s_axi_bid(m_axi_ddr_bid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[2*2 +: 2]),
|
||||
.c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[2 +: 1]),
|
||||
.c0_ddr4_s_axi_arid(m_axi_ddr_arid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[2*8 +: 8]),
|
||||
.c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[2*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[2*2 +: 2]),
|
||||
.c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[2 +: 1]),
|
||||
.c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[2*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[2*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[2*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[2 +: 1]),
|
||||
.c0_ddr4_s_axi_arready(m_axi_ddr_arready[2 +: 1]),
|
||||
.c0_ddr4_s_axi_rready(m_axi_ddr_rready[2 +: 1]),
|
||||
.c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[2 +: 1]),
|
||||
.c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[2 +: 1]),
|
||||
.c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[2*2 +: 2]),
|
||||
.c0_ddr4_s_axi_rid(m_axi_ddr_rid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH])
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign ddr4_sodimm_a_adr = {17{1'bz}};
|
||||
assign ddr4_sodimm_a_ba = {2{1'bz}};
|
||||
assign ddr4_sodimm_a_bg = {2{1'bz}};
|
||||
assign ddr4_sodimm_a_cke = 1'bz;
|
||||
assign ddr4_sodimm_a_cs_n = 1'bz;
|
||||
assign ddr4_sodimm_a_act_n = 1'bz;
|
||||
assign ddr4_sodimm_a_odt = 1'bz;
|
||||
assign ddr4_sodimm_a_reset_n = 1'b0;
|
||||
assign ddr4_sodimm_a_dq = {64{1'bz}};
|
||||
assign ddr4_sodimm_a_dqs_t = {8{1'bz}};
|
||||
assign ddr4_sodimm_a_dqs_c = {8{1'bz}};
|
||||
assign ddr4_sodimm_a_dm_dbi_n = {8{1'bz}};
|
||||
|
||||
OBUFTDS ddr4_sodimm_a_ck_obuftds_inst (
|
||||
.I(1'b0),
|
||||
.T(1'b1),
|
||||
.O(ddr4_sodimm_a_ck_t),
|
||||
.OB(ddr4_sodimm_a_ck_c)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
if (DDR_ENABLE && DDR_CH > 3) begin
|
||||
|
||||
reg ddr4_rst_reg = 1'b1;
|
||||
|
||||
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
|
||||
if (pcie_user_reset) begin
|
||||
ddr4_rst_reg <= 1'b1;
|
||||
end else begin
|
||||
ddr4_rst_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
ddr4_sodimm_0 ddr4_sodimm_b_inst (
|
||||
.c0_sys_clk_p(clk_sodimm_b_refclk_p),
|
||||
.c0_sys_clk_n(clk_sodimm_b_refclk_n),
|
||||
.sys_rst(ddr4_rst_reg),
|
||||
|
||||
.c0_init_calib_complete(ddr_status[3 +: 1]),
|
||||
.dbg_clk(),
|
||||
.dbg_bus(),
|
||||
|
||||
.c0_ddr4_adr(ddr4_sodimm_b_adr),
|
||||
.c0_ddr4_ba(ddr4_sodimm_b_ba),
|
||||
.c0_ddr4_cke(ddr4_sodimm_b_cke),
|
||||
.c0_ddr4_cs_n(ddr4_sodimm_b_cs_n),
|
||||
.c0_ddr4_dq(ddr4_sodimm_b_dq),
|
||||
.c0_ddr4_dqs_t(ddr4_sodimm_b_dqs_t),
|
||||
.c0_ddr4_dqs_c(ddr4_sodimm_b_dqs_c),
|
||||
.c0_ddr4_dm_dbi_n(ddr4_sodimm_b_dm_dbi_n),
|
||||
.c0_ddr4_odt(ddr4_sodimm_b_odt),
|
||||
.c0_ddr4_bg(ddr4_sodimm_b_bg),
|
||||
.c0_ddr4_reset_n(ddr4_sodimm_b_reset_n),
|
||||
.c0_ddr4_act_n(ddr4_sodimm_b_act_n),
|
||||
.c0_ddr4_ck_t(ddr4_sodimm_b_ck_t),
|
||||
.c0_ddr4_ck_c(ddr4_sodimm_b_ck_c),
|
||||
|
||||
.c0_ddr4_ui_clk(ddr_clk[3 +: 1]),
|
||||
.c0_ddr4_ui_clk_sync_rst(ddr_rst[3 +: 1]),
|
||||
|
||||
.c0_ddr4_aresetn(!ddr_rst[3 +: 1]),
|
||||
|
||||
.c0_ddr4_s_axi_awid(m_axi_ddr_awid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[3*8 +: 8]),
|
||||
.c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[3*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[3*2 +: 2]),
|
||||
.c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[3 +: 1]),
|
||||
.c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[3*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[3*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[3*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[3 +: 1]),
|
||||
.c0_ddr4_s_axi_awready(m_axi_ddr_awready[3 +: 1]),
|
||||
.c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]),
|
||||
.c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[3*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]),
|
||||
.c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[3 +: 1]),
|
||||
.c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[3 +: 1]),
|
||||
.c0_ddr4_s_axi_wready(m_axi_ddr_wready[3 +: 1]),
|
||||
.c0_ddr4_s_axi_bready(m_axi_ddr_bready[3 +: 1]),
|
||||
.c0_ddr4_s_axi_bid(m_axi_ddr_bid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[3*2 +: 2]),
|
||||
.c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[3 +: 1]),
|
||||
.c0_ddr4_s_axi_arid(m_axi_ddr_arid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[3*8 +: 8]),
|
||||
.c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[3*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[3*2 +: 2]),
|
||||
.c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[3 +: 1]),
|
||||
.c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[3*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[3*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[3*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[3 +: 1]),
|
||||
.c0_ddr4_s_axi_arready(m_axi_ddr_arready[3 +: 1]),
|
||||
.c0_ddr4_s_axi_rready(m_axi_ddr_rready[3 +: 1]),
|
||||
.c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[3 +: 1]),
|
||||
.c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[3 +: 1]),
|
||||
.c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[3*2 +: 2]),
|
||||
.c0_ddr4_s_axi_rid(m_axi_ddr_rid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH])
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign ddr4_sodimm_b_adr = {17{1'bz}};
|
||||
assign ddr4_sodimm_b_ba = {2{1'bz}};
|
||||
assign ddr4_sodimm_b_bg = {2{1'bz}};
|
||||
assign ddr4_sodimm_b_cke = 1'bz;
|
||||
assign ddr4_sodimm_b_cs_n = 1'bz;
|
||||
assign ddr4_sodimm_b_act_n = 1'bz;
|
||||
assign ddr4_sodimm_b_odt = 1'bz;
|
||||
assign ddr4_sodimm_b_reset_n = 1'b0;
|
||||
assign ddr4_sodimm_b_dq = {64{1'bz}};
|
||||
assign ddr4_sodimm_b_dqs_t = {8{1'bz}};
|
||||
assign ddr4_sodimm_b_dqs_c = {8{1'bz}};
|
||||
assign ddr4_sodimm_b_dm_dbi_n = {8{1'bz}};
|
||||
|
||||
OBUFTDS ddr4_sodimm_b_ck_obuftds_inst (
|
||||
.I(1'b0),
|
||||
.T(1'b1),
|
||||
.O(ddr4_sodimm_b_ck_t),
|
||||
.OB(ddr4_sodimm_b_ck_c)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
fpga_core #(
|
||||
// FW and board IDs
|
||||
.FPGA_ID(FPGA_ID),
|
||||
@ -1482,6 +2170,16 @@ fpga_core #(
|
||||
.TX_RAM_SIZE(TX_RAM_SIZE),
|
||||
.RX_RAM_SIZE(RX_RAM_SIZE),
|
||||
|
||||
// RAM configuration
|
||||
.DDR_CH(DDR_CH),
|
||||
.DDR_ENABLE(DDR_ENABLE),
|
||||
.AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH),
|
||||
.AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH),
|
||||
.AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH),
|
||||
.AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH),
|
||||
.AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN),
|
||||
.AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST),
|
||||
|
||||
// Application block configuration
|
||||
.APP_ID(APP_ID),
|
||||
.APP_ENABLE(APP_ENABLE),
|
||||
@ -1572,6 +2270,14 @@ core_inst (
|
||||
.pps_in(pps_in),
|
||||
.pps_out(pps_out),
|
||||
|
||||
/*
|
||||
* BMC interface
|
||||
*/
|
||||
.bmc_clk(bmc_clk),
|
||||
.bmc_nss(bmc_nss),
|
||||
.bmc_mosi(bmc_mosi),
|
||||
.bmc_miso(bmc_miso),
|
||||
|
||||
/*
|
||||
* PCIe
|
||||
*/
|
||||
@ -1837,7 +2543,58 @@ core_inst (
|
||||
.qsfp_3_i2c_scl_t(qsfp_3_i2c_scl_t),
|
||||
.qsfp_3_i2c_sda_i(qsfp_3_i2c_sda_i),
|
||||
.qsfp_3_i2c_sda_o(qsfp_3_i2c_sda_o),
|
||||
.qsfp_3_i2c_sda_t(qsfp_3_i2c_sda_t)
|
||||
.qsfp_3_i2c_sda_t(qsfp_3_i2c_sda_t),
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
.ddr_clk(ddr_clk),
|
||||
.ddr_rst(ddr_rst),
|
||||
|
||||
.m_axi_ddr_awid(m_axi_ddr_awid),
|
||||
.m_axi_ddr_awaddr(m_axi_ddr_awaddr),
|
||||
.m_axi_ddr_awlen(m_axi_ddr_awlen),
|
||||
.m_axi_ddr_awsize(m_axi_ddr_awsize),
|
||||
.m_axi_ddr_awburst(m_axi_ddr_awburst),
|
||||
.m_axi_ddr_awlock(m_axi_ddr_awlock),
|
||||
.m_axi_ddr_awcache(m_axi_ddr_awcache),
|
||||
.m_axi_ddr_awprot(m_axi_ddr_awprot),
|
||||
.m_axi_ddr_awqos(m_axi_ddr_awqos),
|
||||
.m_axi_ddr_awvalid(m_axi_ddr_awvalid),
|
||||
.m_axi_ddr_awready(m_axi_ddr_awready),
|
||||
.m_axi_ddr_wdata(m_axi_ddr_wdata),
|
||||
.m_axi_ddr_wstrb(m_axi_ddr_wstrb),
|
||||
.m_axi_ddr_wlast(m_axi_ddr_wlast),
|
||||
.m_axi_ddr_wvalid(m_axi_ddr_wvalid),
|
||||
.m_axi_ddr_wready(m_axi_ddr_wready),
|
||||
.m_axi_ddr_bid(m_axi_ddr_bid),
|
||||
.m_axi_ddr_bresp(m_axi_ddr_bresp),
|
||||
.m_axi_ddr_bvalid(m_axi_ddr_bvalid),
|
||||
.m_axi_ddr_bready(m_axi_ddr_bready),
|
||||
.m_axi_ddr_arid(m_axi_ddr_arid),
|
||||
.m_axi_ddr_araddr(m_axi_ddr_araddr),
|
||||
.m_axi_ddr_arlen(m_axi_ddr_arlen),
|
||||
.m_axi_ddr_arsize(m_axi_ddr_arsize),
|
||||
.m_axi_ddr_arburst(m_axi_ddr_arburst),
|
||||
.m_axi_ddr_arlock(m_axi_ddr_arlock),
|
||||
.m_axi_ddr_arcache(m_axi_ddr_arcache),
|
||||
.m_axi_ddr_arprot(m_axi_ddr_arprot),
|
||||
.m_axi_ddr_arqos(m_axi_ddr_arqos),
|
||||
.m_axi_ddr_arvalid(m_axi_ddr_arvalid),
|
||||
.m_axi_ddr_arready(m_axi_ddr_arready),
|
||||
.m_axi_ddr_rid(m_axi_ddr_rid),
|
||||
.m_axi_ddr_rdata(m_axi_ddr_rdata),
|
||||
.m_axi_ddr_rresp(m_axi_ddr_rresp),
|
||||
.m_axi_ddr_rlast(m_axi_ddr_rlast),
|
||||
.m_axi_ddr_rvalid(m_axi_ddr_rvalid),
|
||||
.m_axi_ddr_rready(m_axi_ddr_rready),
|
||||
|
||||
.ddr_status(ddr_status),
|
||||
|
||||
/*
|
||||
* Reboot trigger
|
||||
*/
|
||||
.fpga_boot(fpga_boot)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
@ -84,6 +84,16 @@ module fpga_core #
|
||||
parameter TX_RAM_SIZE = 131072,
|
||||
parameter RX_RAM_SIZE = 131072,
|
||||
|
||||
// RAM configuration
|
||||
parameter DDR_CH = 4,
|
||||
parameter DDR_ENABLE = 0,
|
||||
parameter AXI_DDR_DATA_WIDTH = 512,
|
||||
parameter AXI_DDR_ADDR_WIDTH = 32,
|
||||
parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8),
|
||||
parameter AXI_DDR_ID_WIDTH = 8,
|
||||
parameter AXI_DDR_MAX_BURST_LEN = 256,
|
||||
parameter AXI_DDR_NARROW_BURST = 0,
|
||||
|
||||
// Application block configuration
|
||||
parameter APP_ID = 32'h00000000,
|
||||
parameter APP_ENABLE = 0,
|
||||
@ -174,6 +184,14 @@ module fpga_core #
|
||||
input wire pps_in,
|
||||
output wire pps_out,
|
||||
|
||||
/*
|
||||
* BMC interface
|
||||
*/
|
||||
output wire bmc_clk,
|
||||
output wire bmc_nss,
|
||||
output wire bmc_mosi,
|
||||
input wire bmc_miso,
|
||||
|
||||
/*
|
||||
* PCIe
|
||||
*/
|
||||
@ -451,7 +469,58 @@ module fpga_core #
|
||||
output wire qsfp_3_i2c_scl_t,
|
||||
input wire qsfp_3_i2c_sda_i,
|
||||
output wire qsfp_3_i2c_sda_o,
|
||||
output wire qsfp_3_i2c_sda_t
|
||||
output wire qsfp_3_i2c_sda_t,
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
input wire [DDR_CH-1:0] ddr_clk,
|
||||
input wire [DDR_CH-1:0] ddr_rst,
|
||||
|
||||
output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid,
|
||||
output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr,
|
||||
output wire [DDR_CH*8-1:0] m_axi_ddr_awlen,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_awsize,
|
||||
output wire [DDR_CH*2-1:0] m_axi_ddr_awburst,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_awlock,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_awcache,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_awprot,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_awqos,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_awvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_awready,
|
||||
output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata,
|
||||
output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_wlast,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_wvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_wready,
|
||||
input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid,
|
||||
input wire [DDR_CH*2-1:0] m_axi_ddr_bresp,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_bvalid,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_bready,
|
||||
output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid,
|
||||
output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr,
|
||||
output wire [DDR_CH*8-1:0] m_axi_ddr_arlen,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_arsize,
|
||||
output wire [DDR_CH*2-1:0] m_axi_ddr_arburst,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_arlock,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_arcache,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_arprot,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_arqos,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_arvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_arready,
|
||||
input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid,
|
||||
input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata,
|
||||
input wire [DDR_CH*2-1:0] m_axi_ddr_rresp,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_rlast,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_rvalid,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_rready,
|
||||
|
||||
input wire [DDR_CH-1:0] ddr_status,
|
||||
|
||||
/*
|
||||
* Reboot trigger
|
||||
*/
|
||||
output wire fpga_boot
|
||||
);
|
||||
|
||||
parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF;
|
||||
@ -465,7 +534,7 @@ parameter AXIL_CSR_ADDR_WIDTH = AXIL_IF_CTRL_ADDR_WIDTH-5-$clog2((PORTS_PER_IF+3
|
||||
localparam RB_BASE_ADDR = 16'h1000;
|
||||
localparam RBB = RB_BASE_ADDR & {AXIL_CTRL_ADDR_WIDTH{1'b1}};
|
||||
|
||||
localparam RB_DRP_QSFP_0_BASE = RB_BASE_ADDR + 16'h50;
|
||||
localparam RB_DRP_QSFP_0_BASE = RB_BASE_ADDR + 16'h70;
|
||||
localparam RB_DRP_QSFP_1_BASE = RB_DRP_QSFP_0_BASE + 16'h20;
|
||||
localparam RB_DRP_QSFP_2_BASE = RB_DRP_QSFP_1_BASE + 16'h20;
|
||||
localparam RB_DRP_QSFP_3_BASE = RB_DRP_QSFP_2_BASE + 16'h20;
|
||||
@ -551,6 +620,17 @@ reg qsfp_3_lp_mode_reg = 1'b0;
|
||||
reg qsfp_3_i2c_scl_o_reg = 1'b1;
|
||||
reg qsfp_3_i2c_sda_o_reg = 1'b1;
|
||||
|
||||
reg fpga_boot_reg = 1'b0;
|
||||
|
||||
reg [15:0] bmc_ctrl_cmd_reg = 16'd0;
|
||||
reg [31:0] bmc_ctrl_data_reg = 32'd0;
|
||||
reg bmc_ctrl_valid_reg = 1'b0;
|
||||
|
||||
wire [15:0] bmc_read_data;
|
||||
wire bmc_status_idle;
|
||||
wire bmc_status_done;
|
||||
wire bmc_status_timeout;
|
||||
|
||||
assign ctrl_reg_wr_wait = qsfp_0_drp_reg_wr_wait | qsfp_1_drp_reg_wr_wait | qsfp_2_drp_reg_wr_wait | qsfp_3_drp_reg_wr_wait;
|
||||
assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg | qsfp_0_drp_reg_wr_ack | qsfp_1_drp_reg_wr_ack | qsfp_2_drp_reg_wr_ack | qsfp_3_drp_reg_wr_ack;
|
||||
assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg | qsfp_0_drp_reg_rd_data | qsfp_1_drp_reg_rd_data | qsfp_2_drp_reg_rd_data | qsfp_3_drp_reg_rd_data;
|
||||
@ -585,15 +665,24 @@ assign qsfp_3_i2c_scl_t = qsfp_3_i2c_scl_o_reg;
|
||||
assign qsfp_3_i2c_sda_o = qsfp_3_i2c_sda_o_reg;
|
||||
assign qsfp_3_i2c_sda_t = qsfp_3_i2c_sda_o_reg;
|
||||
|
||||
assign fpga_boot = fpga_boot_reg;
|
||||
|
||||
always @(posedge clk_250mhz) begin
|
||||
ctrl_reg_wr_ack_reg <= 1'b0;
|
||||
ctrl_reg_rd_data_reg <= {AXIL_CTRL_DATA_WIDTH{1'b0}};
|
||||
ctrl_reg_rd_ack_reg <= 1'b0;
|
||||
|
||||
bmc_ctrl_valid_reg <= 1'b0;
|
||||
|
||||
if (ctrl_reg_wr_en && !ctrl_reg_wr_ack_reg) begin
|
||||
// write operation
|
||||
ctrl_reg_wr_ack_reg <= 1'b0;
|
||||
case ({ctrl_reg_wr_addr >> 2, 2'b00})
|
||||
// FW ID
|
||||
8'h0C: begin
|
||||
// FW ID: FPGA JTAG ID
|
||||
fpga_boot_reg <= ctrl_reg_wr_data == 32'hFEE1DEAD;
|
||||
end
|
||||
// I2C 0
|
||||
RBB+8'h0C: begin
|
||||
// I2C ctrl: control
|
||||
@ -654,6 +743,13 @@ always @(posedge clk_250mhz) begin
|
||||
qsfp_3_lp_mode_reg <= ctrl_reg_wr_data[29];
|
||||
end
|
||||
end
|
||||
// SF2 BMC
|
||||
RBB+8'h60: bmc_ctrl_data_reg <= ctrl_reg_wr_data; // BMC ctrl: data
|
||||
RBB+8'h64: begin
|
||||
// BMC ctrl: cmd
|
||||
bmc_ctrl_cmd_reg <= ctrl_reg_wr_data[31:16];
|
||||
bmc_ctrl_valid_reg <= 1'b1;
|
||||
end
|
||||
default: ctrl_reg_wr_ack_reg <= 1'b0;
|
||||
endcase
|
||||
end
|
||||
@ -709,7 +805,7 @@ always @(posedge clk_250mhz) begin
|
||||
// XCVR GPIO
|
||||
RBB+8'h40: ctrl_reg_rd_data_reg <= 32'h0000C101; // XCVR GPIO: Type
|
||||
RBB+8'h44: ctrl_reg_rd_data_reg <= 32'h00000100; // XCVR GPIO: Version
|
||||
RBB+8'h48: ctrl_reg_rd_data_reg <= RB_DRP_QSFP_0_BASE; // XCVR GPIO: Next header
|
||||
RBB+8'h48: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h50; // XCVR GPIO: Next header
|
||||
RBB+8'h4C: begin
|
||||
// XCVR GPIO: control 0123
|
||||
ctrl_reg_rd_data_reg[0] <= !qsfp_0_mod_prsnt_n;
|
||||
@ -729,6 +825,19 @@ always @(posedge clk_250mhz) begin
|
||||
ctrl_reg_rd_data_reg[28] <= qsfp_3_reset_reg;
|
||||
ctrl_reg_rd_data_reg[29] <= qsfp_3_lp_mode_reg;
|
||||
end
|
||||
// SF2 BMC
|
||||
RBB+8'h50: ctrl_reg_rd_data_reg <= 32'h0000C141; // BMC ctrl: Type
|
||||
RBB+8'h54: ctrl_reg_rd_data_reg <= 32'h00000100; // BMC ctrl: Version
|
||||
RBB+8'h58: ctrl_reg_rd_data_reg <= RB_DRP_QSFP_0_BASE; // BMC ctrl: Next header
|
||||
RBB+8'h5C: begin
|
||||
// BMC ctrl: status
|
||||
ctrl_reg_rd_data_reg[15:0] <= bmc_read_data;
|
||||
ctrl_reg_rd_data_reg[16] <= bmc_status_done;
|
||||
ctrl_reg_rd_data_reg[18] <= bmc_status_timeout;
|
||||
ctrl_reg_rd_data_reg[19] <= bmc_status_idle;
|
||||
end
|
||||
RBB+8'h60: ctrl_reg_rd_data_reg <= bmc_ctrl_data_reg; // BMC ctrl: data
|
||||
RBB+8'h64: ctrl_reg_rd_data_reg[31:16] <= bmc_ctrl_cmd_reg; // BMC ctrl: cmd
|
||||
default: ctrl_reg_rd_ack_reg <= 1'b0;
|
||||
endcase
|
||||
end
|
||||
@ -756,9 +865,37 @@ always @(posedge clk_250mhz) begin
|
||||
qsfp_3_lp_mode_reg <= 1'b0;
|
||||
qsfp_3_i2c_scl_o_reg <= 1'b1;
|
||||
qsfp_3_i2c_sda_o_reg <= 1'b1;
|
||||
|
||||
fpga_boot_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
bmc_spi #(
|
||||
.PRESCALE(125),
|
||||
.BYTE_WAIT(32),
|
||||
.TIMEOUT(5000)
|
||||
)
|
||||
bmc_spi_inst (
|
||||
.clk(clk_250mhz),
|
||||
.rst(rst_250mhz),
|
||||
|
||||
.ctrl_cmd(bmc_ctrl_cmd_reg),
|
||||
.ctrl_data(bmc_ctrl_data_reg),
|
||||
.ctrl_valid(bmc_ctrl_valid_reg),
|
||||
|
||||
.read_data(bmc_read_data),
|
||||
|
||||
.status_idle(bmc_status_idle),
|
||||
.status_done(bmc_status_done),
|
||||
.status_timeout(bmc_status_timeout),
|
||||
|
||||
.bmc_clk(bmc_clk),
|
||||
.bmc_nss(bmc_nss),
|
||||
.bmc_mosi(bmc_mosi),
|
||||
.bmc_miso(bmc_miso),
|
||||
.bmc_int(1'b0)
|
||||
);
|
||||
|
||||
rb_drp #(
|
||||
.DRP_ADDR_WIDTH(24),
|
||||
.DRP_DATA_WIDTH(16),
|
||||
@ -1167,7 +1304,22 @@ mqnic_core_pcie_us #(
|
||||
.RX_RAM_SIZE(RX_RAM_SIZE),
|
||||
|
||||
// RAM configuration
|
||||
.DDR_ENABLE(0),
|
||||
.DDR_CH(DDR_CH),
|
||||
.DDR_ENABLE(DDR_ENABLE),
|
||||
.DDR_GROUP_SIZE(1),
|
||||
.AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH),
|
||||
.AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH),
|
||||
.AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH),
|
||||
.AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH),
|
||||
.AXI_DDR_AWUSER_ENABLE(0),
|
||||
.AXI_DDR_WUSER_ENABLE(0),
|
||||
.AXI_DDR_BUSER_ENABLE(0),
|
||||
.AXI_DDR_ARUSER_ENABLE(0),
|
||||
.AXI_DDR_RUSER_ENABLE(0),
|
||||
.AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN),
|
||||
.AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST),
|
||||
.AXI_DDR_FIXED_BURST(0),
|
||||
.AXI_DDR_WRAP_BURST(1),
|
||||
.HBM_ENABLE(0),
|
||||
|
||||
// Application block configuration
|
||||
@ -1447,53 +1599,53 @@ core_inst (
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
.ddr_clk(0),
|
||||
.ddr_rst(0),
|
||||
.ddr_clk(ddr_clk),
|
||||
.ddr_rst(ddr_rst),
|
||||
|
||||
.m_axi_ddr_awid(),
|
||||
.m_axi_ddr_awaddr(),
|
||||
.m_axi_ddr_awlen(),
|
||||
.m_axi_ddr_awsize(),
|
||||
.m_axi_ddr_awburst(),
|
||||
.m_axi_ddr_awlock(),
|
||||
.m_axi_ddr_awcache(),
|
||||
.m_axi_ddr_awprot(),
|
||||
.m_axi_ddr_awqos(),
|
||||
.m_axi_ddr_awid(m_axi_ddr_awid),
|
||||
.m_axi_ddr_awaddr(m_axi_ddr_awaddr),
|
||||
.m_axi_ddr_awlen(m_axi_ddr_awlen),
|
||||
.m_axi_ddr_awsize(m_axi_ddr_awsize),
|
||||
.m_axi_ddr_awburst(m_axi_ddr_awburst),
|
||||
.m_axi_ddr_awlock(m_axi_ddr_awlock),
|
||||
.m_axi_ddr_awcache(m_axi_ddr_awcache),
|
||||
.m_axi_ddr_awprot(m_axi_ddr_awprot),
|
||||
.m_axi_ddr_awqos(m_axi_ddr_awqos),
|
||||
.m_axi_ddr_awuser(),
|
||||
.m_axi_ddr_awvalid(),
|
||||
.m_axi_ddr_awready(0),
|
||||
.m_axi_ddr_wdata(),
|
||||
.m_axi_ddr_wstrb(),
|
||||
.m_axi_ddr_wlast(),
|
||||
.m_axi_ddr_awvalid(m_axi_ddr_awvalid),
|
||||
.m_axi_ddr_awready(m_axi_ddr_awready),
|
||||
.m_axi_ddr_wdata(m_axi_ddr_wdata),
|
||||
.m_axi_ddr_wstrb(m_axi_ddr_wstrb),
|
||||
.m_axi_ddr_wlast(m_axi_ddr_wlast),
|
||||
.m_axi_ddr_wuser(),
|
||||
.m_axi_ddr_wvalid(),
|
||||
.m_axi_ddr_wready(0),
|
||||
.m_axi_ddr_bid(0),
|
||||
.m_axi_ddr_bresp(0),
|
||||
.m_axi_ddr_wvalid(m_axi_ddr_wvalid),
|
||||
.m_axi_ddr_wready(m_axi_ddr_wready),
|
||||
.m_axi_ddr_bid(m_axi_ddr_bid),
|
||||
.m_axi_ddr_bresp(m_axi_ddr_bresp),
|
||||
.m_axi_ddr_buser(0),
|
||||
.m_axi_ddr_bvalid(0),
|
||||
.m_axi_ddr_bready(),
|
||||
.m_axi_ddr_arid(),
|
||||
.m_axi_ddr_araddr(),
|
||||
.m_axi_ddr_arlen(),
|
||||
.m_axi_ddr_arsize(),
|
||||
.m_axi_ddr_arburst(),
|
||||
.m_axi_ddr_arlock(),
|
||||
.m_axi_ddr_arcache(),
|
||||
.m_axi_ddr_arprot(),
|
||||
.m_axi_ddr_arqos(),
|
||||
.m_axi_ddr_bvalid(m_axi_ddr_bvalid),
|
||||
.m_axi_ddr_bready(m_axi_ddr_bready),
|
||||
.m_axi_ddr_arid(m_axi_ddr_arid),
|
||||
.m_axi_ddr_araddr(m_axi_ddr_araddr),
|
||||
.m_axi_ddr_arlen(m_axi_ddr_arlen),
|
||||
.m_axi_ddr_arsize(m_axi_ddr_arsize),
|
||||
.m_axi_ddr_arburst(m_axi_ddr_arburst),
|
||||
.m_axi_ddr_arlock(m_axi_ddr_arlock),
|
||||
.m_axi_ddr_arcache(m_axi_ddr_arcache),
|
||||
.m_axi_ddr_arprot(m_axi_ddr_arprot),
|
||||
.m_axi_ddr_arqos(m_axi_ddr_arqos),
|
||||
.m_axi_ddr_aruser(),
|
||||
.m_axi_ddr_arvalid(),
|
||||
.m_axi_ddr_arready(0),
|
||||
.m_axi_ddr_rid(0),
|
||||
.m_axi_ddr_rdata(0),
|
||||
.m_axi_ddr_rresp(0),
|
||||
.m_axi_ddr_rlast(0),
|
||||
.m_axi_ddr_arvalid(m_axi_ddr_arvalid),
|
||||
.m_axi_ddr_arready(m_axi_ddr_arready),
|
||||
.m_axi_ddr_rid(m_axi_ddr_rid),
|
||||
.m_axi_ddr_rdata(m_axi_ddr_rdata),
|
||||
.m_axi_ddr_rresp(m_axi_ddr_rresp),
|
||||
.m_axi_ddr_rlast(m_axi_ddr_rlast),
|
||||
.m_axi_ddr_ruser(0),
|
||||
.m_axi_ddr_rvalid(0),
|
||||
.m_axi_ddr_rready(),
|
||||
.m_axi_ddr_rvalid(m_axi_ddr_rvalid),
|
||||
.m_axi_ddr_rready(m_axi_ddr_rready),
|
||||
|
||||
.ddr_status(0),
|
||||
.ddr_status(ddr_status),
|
||||
|
||||
/*
|
||||
* HBM
|
||||
|
||||
@ -13,6 +13,7 @@ DUT = fpga_core
|
||||
TOPLEVEL = $(DUT)
|
||||
MODULE = test_$(DUT)
|
||||
VERILOG_SOURCES += ../../rtl/$(DUT).v
|
||||
VERILOG_SOURCES += ../../rtl/bmc_spi.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
|
||||
|
||||
@ -313,6 +313,8 @@ class TB(object):
|
||||
|
||||
dut.pps_in.setimmediatevalue(0)
|
||||
|
||||
dut.bmc_miso.setimmediatevalue(0)
|
||||
|
||||
self.loopback_enable = False
|
||||
cocotb.start_soon(self._run_loopback())
|
||||
|
||||
@ -569,6 +571,7 @@ def test_fpga_core(request):
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(rtl_dir, f"{dut}.v"),
|
||||
os.path.join(rtl_dir, "bmc_spi.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_core.v"),
|
||||
|
||||
4
fpga/mqnic/fb4CGg3/fpga_25g/boot.xdc
Normal file
4
fpga/mqnic/fb4CGg3/fpga_25g/boot.xdc
Normal file
@ -0,0 +1,4 @@
|
||||
# Timing constraints for FPGA boot logic
|
||||
|
||||
set_property ASYNC_REG TRUE [get_cells "fpga_boot_sync_reg_0_reg fpga_boot_sync_reg_1_reg"]
|
||||
set_false_path -to [get_pins "fpga_boot_sync_reg_0_reg/D"]
|
||||
@ -13,24 +13,24 @@ set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable [current_design]
|
||||
set_property -dict {LOC AV26 IOSTANDARD LVCMOS18} [get_ports init_clk]
|
||||
create_clock -period 20.000 -name init_clk [get_ports init_clk]
|
||||
|
||||
# DDR4 refclk1
|
||||
#set_property -dict {LOC BA34 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk1_p]
|
||||
#set_property -dict {LOC BB34 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk1_n]
|
||||
#create_clock -period 3.750 -name clk_ddr4_refclk1 [get_ports clk_ddr4_refclk1_p]
|
||||
# DDR4 A refclk
|
||||
set_property -dict {LOC BA34 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr4_a_refclk_p]
|
||||
set_property -dict {LOC BB34 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr4_a_refclk_n]
|
||||
#create_clock -period 3.750 -name clk_ddr4_a_refclk [get_ports clk_ddr4_a_refclk_p]
|
||||
|
||||
# DDR4 refclk2
|
||||
#set_property -dict {LOC C36 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk2_p]
|
||||
#set_property -dict {LOC C37 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk2_n]
|
||||
#create_clock -period 3.750 -name clk_ddr4_refclk2 [get_ports clk_ddr4_refclk2_p]
|
||||
# DDR4 B refclk
|
||||
set_property -dict {LOC C36 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr4_b_refclk_p]
|
||||
set_property -dict {LOC C37 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_ddr4_b_refclk_n]
|
||||
#create_clock -period 3.750 -name clk_ddr4_b_refclk [get_ports clk_ddr4_b_refclk_p]
|
||||
|
||||
# SODIMM A refclk
|
||||
#set_property -dict {LOC AV27 IOSTANDARD DIFF_SSTL12} [get_ports clk_sodimm_a_refclk_p]
|
||||
#set_property -dict {LOC AV28 IOSTANDARD DIFF_SSTL12} [get_ports clk_sodimm_a_refclk_n]
|
||||
set_property -dict {LOC AV27 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports clk_sodimm_a_refclk_p]
|
||||
set_property -dict {LOC AV28 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports clk_sodimm_a_refclk_n]
|
||||
#create_clock -period 3.750 -name clk_sodimm_a_refclk [get_ports clk_sodimm_a_refclk_p]
|
||||
|
||||
# SODIMM B refclk
|
||||
#set_property -dict {LOC H19 IOSTANDARD DIFF_SSTL12} [get_ports clk_sodimm_b_refclk_p]
|
||||
#set_property -dict {LOC H18 IOSTANDARD DIFF_SSTL12} [get_ports clk_sodimm_b_refclk_n]
|
||||
set_property -dict {LOC H19 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_sodimm_b_refclk_p]
|
||||
set_property -dict {LOC H18 IOSTANDARD DIFF_SSTL12_DCI ODT RTT_48} [get_ports clk_sodimm_b_refclk_n]
|
||||
#create_clock -period 3.750 -name clk_sodimm_b_refclk [get_ports clk_sodimm_b_refclk_p]
|
||||
|
||||
# LEDs
|
||||
@ -55,6 +55,17 @@ set_output_delay 0 [get_ports {pps_out}]
|
||||
set_false_path -from [get_ports {pps_in}]
|
||||
set_input_delay 0 [get_ports {pps_in}]
|
||||
|
||||
# BMC interface
|
||||
set_property -dict {LOC AW28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports bmc_clk]
|
||||
set_property -dict {LOC AY27 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports bmc_nss]
|
||||
set_property -dict {LOC AY28 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 4} [get_ports bmc_mosi]
|
||||
set_property -dict {LOC AY26 IOSTANDARD LVCMOS18} [get_ports bmc_miso]
|
||||
|
||||
set_false_path -to [get_ports {bmc_clk bmc_nss bmc_mosi}]
|
||||
set_output_delay 0 [get_ports {bmc_clk bmc_nss bmc_mosi}]
|
||||
set_false_path -from [get_ports {bmc_miso}]
|
||||
set_input_delay 0 [get_ports {bmc_miso}]
|
||||
|
||||
# QSFP28 Interfaces
|
||||
set_property -dict {LOC AP43} [get_ports qsfp_0_rx_0_p] ;# MGTYRXP3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2
|
||||
set_property -dict {LOC AP44} [get_ports qsfp_0_rx_0_n] ;# MGTYRXN3_121 GTYE4_CHANNEL_X0Y11 / GTYE4_COMMON_X0Y2
|
||||
@ -285,3 +296,505 @@ create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_refclk_0_p]
|
||||
|
||||
set_false_path -from [get_ports {pcie_rst_n}]
|
||||
set_input_delay 0 [get_ports {pcie_rst_n}]
|
||||
|
||||
# DDR4 A (U100, U101, U102, U103)
|
||||
# 4x MT40A512M16JY-083E
|
||||
set_property -dict {LOC BD34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[0]}]
|
||||
set_property -dict {LOC AV33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[1]}]
|
||||
set_property -dict {LOC AM32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[2]}]
|
||||
set_property -dict {LOC AL34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[3]}]
|
||||
set_property -dict {LOC BE35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[4]}]
|
||||
set_property -dict {LOC AY33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[5]}]
|
||||
set_property -dict {LOC AY35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[6]}]
|
||||
set_property -dict {LOC AW33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[7]}]
|
||||
set_property -dict {LOC AW34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[8]}]
|
||||
set_property -dict {LOC AU34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[9]}]
|
||||
set_property -dict {LOC AN34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[10]}]
|
||||
set_property -dict {LOC BC34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[11]}]
|
||||
set_property -dict {LOC BE36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[12]}]
|
||||
set_property -dict {LOC AL32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[13]}]
|
||||
set_property -dict {LOC BB37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[14]}]
|
||||
set_property -dict {LOC AM34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[15]}]
|
||||
set_property -dict {LOC AP33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_adr[16]}]
|
||||
set_property -dict {LOC AY36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_ba[0]}]
|
||||
set_property -dict {LOC BA33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_ba[1]}]
|
||||
set_property -dict {LOC AW36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_bg[0]}]
|
||||
set_property -dict {LOC AR33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_bg[1]}]
|
||||
set_property -dict {LOC AN32 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_a_ck_t[0]}]
|
||||
set_property -dict {LOC AN33 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_a_ck_c[0]}]
|
||||
set_property -dict {LOC AV34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_cke[0]}]
|
||||
set_property -dict {LOC AP34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_cs_n[0]}]
|
||||
set_property -dict {LOC AL33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_act_n}]
|
||||
set_property -dict {LOC BD35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_a_odt[0]}]
|
||||
set_property -dict {LOC AW35 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_a_reset_n}]
|
||||
set_property -dict {LOC BD36 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_a_ten}]
|
||||
|
||||
set_property -dict {LOC Y33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[0]}]
|
||||
set_property -dict {LOC W34 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[1]}]
|
||||
set_property -dict {LOC AA34 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[2]}]
|
||||
set_property -dict {LOC Y32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[3]}]
|
||||
set_property -dict {LOC W33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[4]}]
|
||||
set_property -dict {LOC W30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[5]}]
|
||||
set_property -dict {LOC AB34 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[6]}]
|
||||
set_property -dict {LOC Y30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[7]}]
|
||||
set_property -dict {LOC AD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[8]}]
|
||||
set_property -dict {LOC AC34 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[9]}]
|
||||
set_property -dict {LOC AE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[10]}]
|
||||
set_property -dict {LOC AC33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[11]}]
|
||||
set_property -dict {LOC AF30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[12]}]
|
||||
set_property -dict {LOC AC32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[13]}]
|
||||
set_property -dict {LOC AE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[14]}]
|
||||
set_property -dict {LOC AD34 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[15]}]
|
||||
set_property -dict {LOC AF34 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[16]}]
|
||||
set_property -dict {LOC AJ33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[17]}]
|
||||
set_property -dict {LOC AG34 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[18]}]
|
||||
set_property -dict {LOC AG32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[19]}]
|
||||
set_property -dict {LOC AF33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[20]}]
|
||||
set_property -dict {LOC AG31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[21]}]
|
||||
set_property -dict {LOC AF32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[22]}]
|
||||
set_property -dict {LOC AH33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[23]}]
|
||||
set_property -dict {LOC AK31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[24]}]
|
||||
set_property -dict {LOC AK28 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[25]}]
|
||||
set_property -dict {LOC AJ31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[26]}]
|
||||
set_property -dict {LOC AJ29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[27]}]
|
||||
set_property -dict {LOC AG29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[28]}]
|
||||
set_property -dict {LOC AJ28 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[29]}]
|
||||
set_property -dict {LOC AG30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[30]}]
|
||||
set_property -dict {LOC AJ30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[31]}]
|
||||
set_property -dict {LOC AP29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[32]}]
|
||||
set_property -dict {LOC AM31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[33]}]
|
||||
set_property -dict {LOC AN31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[34]}]
|
||||
set_property -dict {LOC AL30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[35]}]
|
||||
set_property -dict {LOC AP30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[36]}]
|
||||
set_property -dict {LOC AL29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[37]}]
|
||||
set_property -dict {LOC AR30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[38]}]
|
||||
set_property -dict {LOC AN29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[39]}]
|
||||
set_property -dict {LOC AW31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[40]}]
|
||||
set_property -dict {LOC AV32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[41]}]
|
||||
set_property -dict {LOC AV31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[42]}]
|
||||
set_property -dict {LOC AU31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[43]}]
|
||||
set_property -dict {LOC AU30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[44]}]
|
||||
set_property -dict {LOC AU32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[45]}]
|
||||
set_property -dict {LOC AT29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[46]}]
|
||||
set_property -dict {LOC AT30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[47]}]
|
||||
set_property -dict {LOC AY32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[48]}]
|
||||
set_property -dict {LOC BB29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[49]}]
|
||||
set_property -dict {LOC AY30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[50]}]
|
||||
set_property -dict {LOC BB31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[51]}]
|
||||
set_property -dict {LOC BA30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[52]}]
|
||||
set_property -dict {LOC BB30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[53]}]
|
||||
set_property -dict {LOC AY31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[54]}]
|
||||
set_property -dict {LOC BA29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[55]}]
|
||||
set_property -dict {LOC BC29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[56]}]
|
||||
set_property -dict {LOC BF30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[57]}]
|
||||
set_property -dict {LOC BD33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[58]}]
|
||||
set_property -dict {LOC BE30 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[59]}]
|
||||
set_property -dict {LOC BD29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[60]}]
|
||||
set_property -dict {LOC BE31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[61]}]
|
||||
set_property -dict {LOC BE33 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[62]}]
|
||||
set_property -dict {LOC BE32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dq[63]}]
|
||||
set_property -dict {LOC W31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_t[0]}]
|
||||
set_property -dict {LOC Y31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_c[0]}]
|
||||
set_property -dict {LOC AC31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_t[1]}]
|
||||
set_property -dict {LOC AD31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_c[1]}]
|
||||
set_property -dict {LOC AH31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_t[2]}]
|
||||
set_property -dict {LOC AH32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_c[2]}]
|
||||
set_property -dict {LOC AH28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_t[3]}]
|
||||
set_property -dict {LOC AH29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_c[3]}]
|
||||
set_property -dict {LOC AM29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_t[4]}]
|
||||
set_property -dict {LOC AM30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_c[4]}]
|
||||
set_property -dict {LOC AU29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_t[5]}]
|
||||
set_property -dict {LOC AV29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_c[5]}]
|
||||
set_property -dict {LOC BA32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_t[6]}]
|
||||
set_property -dict {LOC BB32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_c[6]}]
|
||||
set_property -dict {LOC BD30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_t[7]}]
|
||||
set_property -dict {LOC BD31 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_a_dqs_c[7]}]
|
||||
set_property -dict {LOC AA32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dm_dbi_n[0]}]
|
||||
set_property -dict {LOC AE31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dm_dbi_n[1]}]
|
||||
set_property -dict {LOC AH34 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dm_dbi_n[2]}]
|
||||
set_property -dict {LOC AJ27 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dm_dbi_n[3]}]
|
||||
set_property -dict {LOC AP31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dm_dbi_n[4]}]
|
||||
set_property -dict {LOC AW29 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dm_dbi_n[5]}]
|
||||
set_property -dict {LOC BC31 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dm_dbi_n[6]}]
|
||||
set_property -dict {LOC BF32 IOSTANDARD POD12_DCI } [get_ports {ddr4_a_dm_dbi_n[7]}]
|
||||
|
||||
# DDR4 B (U200, U201, U202, U203)
|
||||
# 4x MT40A512M16JY-083E
|
||||
set_property -dict {LOC E37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[0]}]
|
||||
set_property -dict {LOC D36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[1]}]
|
||||
set_property -dict {LOC E36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[2]}]
|
||||
set_property -dict {LOC B35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[3]}]
|
||||
set_property -dict {LOC D35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[4]}]
|
||||
set_property -dict {LOC C32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[5]}]
|
||||
set_property -dict {LOC D39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[6]}]
|
||||
set_property -dict {LOC D33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[7]}]
|
||||
set_property -dict {LOC E40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[8]}]
|
||||
set_property -dict {LOC E35 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[9]}]
|
||||
set_property -dict {LOC A38 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[10]}]
|
||||
set_property -dict {LOC E39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[11]}]
|
||||
set_property -dict {LOC B37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[12]}]
|
||||
set_property -dict {LOC D31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[13]}]
|
||||
set_property -dict {LOC B39 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[14]}]
|
||||
set_property -dict {LOC C31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[15]}]
|
||||
set_property -dict {LOC B31 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_adr[16]}]
|
||||
set_property -dict {LOC D40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_ba[0]}]
|
||||
set_property -dict {LOC B32 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_ba[1]}]
|
||||
set_property -dict {LOC B40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_bg[0]}]
|
||||
set_property -dict {LOC B36 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_bg[1]}]
|
||||
set_property -dict {LOC A32 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_b_ck_t[0]}]
|
||||
set_property -dict {LOC A33 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_b_ck_c[0]}]
|
||||
set_property -dict {LOC C33 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_cke[0]}]
|
||||
set_property -dict {LOC A37 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_cs_n[0]}]
|
||||
set_property -dict {LOC A40 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_act_n}]
|
||||
set_property -dict {LOC C34 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_b_odt[0]}]
|
||||
set_property -dict {LOC D34 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_b_reset_n}]
|
||||
set_property -dict {LOC A35 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_b_ten}]
|
||||
|
||||
set_property -dict {LOC B30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[0]}]
|
||||
set_property -dict {LOC C29 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[1]}]
|
||||
set_property -dict {LOC B29 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[2]}]
|
||||
set_property -dict {LOC A29 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[3]}]
|
||||
set_property -dict {LOC A30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[4]}]
|
||||
set_property -dict {LOC D29 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[5]}]
|
||||
set_property -dict {LOC E30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[6]}]
|
||||
set_property -dict {LOC D30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[7]}]
|
||||
set_property -dict {LOC H29 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[8]}]
|
||||
set_property -dict {LOC E28 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[9]}]
|
||||
set_property -dict {LOC G29 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[10]}]
|
||||
set_property -dict {LOC G27 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[11]}]
|
||||
set_property -dict {LOC E27 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[12]}]
|
||||
set_property -dict {LOC D28 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[13]}]
|
||||
set_property -dict {LOC G26 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[14]}]
|
||||
set_property -dict {LOC F27 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[15]}]
|
||||
set_property -dict {LOC J28 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[16]}]
|
||||
set_property -dict {LOC L28 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[17]}]
|
||||
set_property -dict {LOC J29 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[18]}]
|
||||
set_property -dict {LOC L27 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[19]}]
|
||||
set_property -dict {LOC H28 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[20]}]
|
||||
set_property -dict {LOC M27 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[21]}]
|
||||
set_property -dict {LOC H27 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[22]}]
|
||||
set_property -dict {LOC K28 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[23]}]
|
||||
set_property -dict {LOC N28 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[24]}]
|
||||
set_property -dict {LOC R27 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[25]}]
|
||||
set_property -dict {LOC P28 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[26]}]
|
||||
set_property -dict {LOC T27 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[27]}]
|
||||
set_property -dict {LOC P26 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[28]}]
|
||||
set_property -dict {LOC R26 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[29]}]
|
||||
set_property -dict {LOC N26 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[30]}]
|
||||
set_property -dict {LOC T26 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[31]}]
|
||||
set_property -dict {LOC F33 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[32]}]
|
||||
set_property -dict {LOC G32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[33]}]
|
||||
set_property -dict {LOC H32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[34]}]
|
||||
set_property -dict {LOC E32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[35]}]
|
||||
set_property -dict {LOC F32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[36]}]
|
||||
set_property -dict {LOC G31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[37]}]
|
||||
set_property -dict {LOC E33 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[38]}]
|
||||
set_property -dict {LOC H31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[39]}]
|
||||
set_property -dict {LOC L33 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[40]}]
|
||||
set_property -dict {LOC J31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[41]}]
|
||||
set_property -dict {LOC L32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[42]}]
|
||||
set_property -dict {LOC K33 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[43]}]
|
||||
set_property -dict {LOC M30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[44]}]
|
||||
set_property -dict {LOC K32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[45]}]
|
||||
set_property -dict {LOC L30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[46]}]
|
||||
set_property -dict {LOC K31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[47]}]
|
||||
set_property -dict {LOC N33 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[48]}]
|
||||
set_property -dict {LOC R31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[49]}]
|
||||
set_property -dict {LOC N34 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[50]}]
|
||||
set_property -dict {LOC P34 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[51]}]
|
||||
set_property -dict {LOC N32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[52]}]
|
||||
set_property -dict {LOC R32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[53]}]
|
||||
set_property -dict {LOC N31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[54]}]
|
||||
set_property -dict {LOC P31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[55]}]
|
||||
set_property -dict {LOC U31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[56]}]
|
||||
set_property -dict {LOC U30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[57]}]
|
||||
set_property -dict {LOC T32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[58]}]
|
||||
set_property -dict {LOC V31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[59]}]
|
||||
set_property -dict {LOC T30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[60]}]
|
||||
set_property -dict {LOC T33 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[61]}]
|
||||
set_property -dict {LOC R33 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[62]}]
|
||||
set_property -dict {LOC U32 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dq[63]}]
|
||||
set_property -dict {LOC A27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_t[0]}]
|
||||
set_property -dict {LOC A28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_c[0]}]
|
||||
set_property -dict {LOC F28 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_t[1]}]
|
||||
set_property -dict {LOC F29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_c[1]}]
|
||||
set_property -dict {LOC K26 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_t[2]}]
|
||||
set_property -dict {LOC K27 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_c[2]}]
|
||||
set_property -dict {LOC P29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_t[3]}]
|
||||
set_property -dict {LOC N29 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_c[3]}]
|
||||
set_property -dict {LOC J33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_t[4]}]
|
||||
set_property -dict {LOC H33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_c[4]}]
|
||||
set_property -dict {LOC K30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_t[5]}]
|
||||
set_property -dict {LOC J30 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_c[5]}]
|
||||
set_property -dict {LOC M34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_t[6]}]
|
||||
set_property -dict {LOC L34 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_c[6]}]
|
||||
set_property -dict {LOC V32 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_t[7]}]
|
||||
set_property -dict {LOC V33 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_b_dqs_c[7]}]
|
||||
set_property -dict {LOC C27 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dm_dbi_n[0]}]
|
||||
set_property -dict {LOC J26 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dm_dbi_n[1]}]
|
||||
set_property -dict {LOC M29 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dm_dbi_n[2]}]
|
||||
set_property -dict {LOC T28 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dm_dbi_n[3]}]
|
||||
set_property -dict {LOC G30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dm_dbi_n[4]}]
|
||||
set_property -dict {LOC M31 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dm_dbi_n[5]}]
|
||||
set_property -dict {LOC R30 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dm_dbi_n[6]}]
|
||||
set_property -dict {LOC U34 IOSTANDARD POD12_DCI } [get_ports {ddr4_b_dm_dbi_n[7]}]
|
||||
|
||||
# DDR4 SODIMM A
|
||||
set_property -dict {LOC BE15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_adr[0]}]
|
||||
set_property -dict {LOC BF15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_adr[1]}]
|
||||
set_property -dict {LOC BD16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_adr[2]}]
|
||||
set_property -dict {LOC BD15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_adr[3]}]
|
||||
set_property -dict {LOC BE16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_adr[4]}]
|
||||
set_property -dict {LOC BD14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_adr[5]}]
|
||||
set_property -dict {LOC BC14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_adr[6]}]
|
||||
set_property -dict {LOC BC13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_adr[7]}]
|
||||
set_property -dict {LOC AT14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_adr[8]}]
|
||||
set_property -dict {LOC AR16 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_adr[9]}]
|
||||
set_property -dict {LOC AR15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_adr[10]}]
|
||||
set_property -dict {LOC AP15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_adr[11]}]
|
||||
set_property -dict {LOC AP14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_adr[12]}]
|
||||
set_property -dict {LOC AM15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_adr[13]}]
|
||||
set_property -dict {LOC AN13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_adr[14]}]
|
||||
set_property -dict {LOC AP13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_adr[15]}]
|
||||
set_property -dict {LOC AR13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_adr[16]}]
|
||||
set_property -dict {LOC AL15 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_ba[0]}]
|
||||
set_property -dict {LOC AN14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_ba[1]}]
|
||||
set_property -dict {LOC AL14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_bg[0]}]
|
||||
set_property -dict {LOC AM14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_bg[1]}]
|
||||
set_property -dict {LOC BD13 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_sodimm_a_ck_t[0]}]
|
||||
set_property -dict {LOC BE13 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_sodimm_a_ck_c[0]}]
|
||||
set_property -dict {LOC AT13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_cke[0]}]
|
||||
set_property -dict {LOC BB12 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_cs_n[0]}]
|
||||
#set_property -dict {LOC BA17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_cs_n[2]}]
|
||||
#set_property -dict {LOC AU21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_cs_n[3]}]
|
||||
set_property -dict {LOC BF14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_act_n}]
|
||||
set_property -dict {LOC BF13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_a_odt[0]}]
|
||||
set_property -dict {LOC BC11 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_sodimm_a_reset_n}]
|
||||
set_property -dict {LOC AU19 IOSTANDARD LVCMOS12 } [get_ports {ddr4_sodimm_a_alert_n}]
|
||||
set_property -dict {LOC AV17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_sodimm_a_event_n}]
|
||||
|
||||
set_property -dict {LOC BE8 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[0]}]
|
||||
set_property -dict {LOC BE12 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[1]}]
|
||||
set_property -dict {LOC BF10 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[2]}]
|
||||
set_property -dict {LOC BD8 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[3]}]
|
||||
set_property -dict {LOC BD9 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[4]}]
|
||||
set_property -dict {LOC BF12 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[5]}]
|
||||
set_property -dict {LOC BF8 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[6]}]
|
||||
set_property -dict {LOC BF9 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[7]}]
|
||||
set_property -dict {LOC BB11 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[8]}]
|
||||
set_property -dict {LOC BA9 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[9]}]
|
||||
set_property -dict {LOC BC8 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[10]}]
|
||||
set_property -dict {LOC BC9 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[11]}]
|
||||
set_property -dict {LOC BB10 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[12]}]
|
||||
set_property -dict {LOC BA8 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[13]}]
|
||||
set_property -dict {LOC BB9 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[14]}]
|
||||
set_property -dict {LOC BC7 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[15]}]
|
||||
set_property -dict {LOC AY11 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[16]}]
|
||||
set_property -dict {LOC BA15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[17]}]
|
||||
set_property -dict {LOC BA14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[18]}]
|
||||
set_property -dict {LOC AY13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[19]}]
|
||||
set_property -dict {LOC AY12 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[20]}]
|
||||
set_property -dict {LOC BA13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[21]}]
|
||||
set_property -dict {LOC AY16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[22]}]
|
||||
set_property -dict {LOC AY15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[23]}]
|
||||
set_property -dict {LOC AW15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[24]}]
|
||||
set_property -dict {LOC AW16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[25]}]
|
||||
set_property -dict {LOC AU16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[26]}]
|
||||
set_property -dict {LOC AV13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[27]}]
|
||||
set_property -dict {LOC AU13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[28]}]
|
||||
set_property -dict {LOC AT15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[29]}]
|
||||
set_property -dict {LOC AV16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[30]}]
|
||||
set_property -dict {LOC AU15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[31]}]
|
||||
set_property -dict {LOC AN16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[32]}]
|
||||
set_property -dict {LOC AM20 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[33]}]
|
||||
set_property -dict {LOC AM19 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[34]}]
|
||||
set_property -dict {LOC AN19 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[35]}]
|
||||
set_property -dict {LOC AM16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[36]}]
|
||||
set_property -dict {LOC AL20 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[37]}]
|
||||
set_property -dict {LOC AL19 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[38]}]
|
||||
set_property -dict {LOC AP19 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[39]}]
|
||||
set_property -dict {LOC AP20 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[40]}]
|
||||
set_property -dict {LOC AR18 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[41]}]
|
||||
set_property -dict {LOC AP18 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[42]}]
|
||||
set_property -dict {LOC AT20 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[43]}]
|
||||
set_property -dict {LOC AU20 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[44]}]
|
||||
set_property -dict {LOC AU17 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[45]}]
|
||||
set_property -dict {LOC AR20 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[46]}]
|
||||
set_property -dict {LOC AT18 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[47]}]
|
||||
set_property -dict {LOC AW20 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[48]}]
|
||||
set_property -dict {LOC AW19 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[49]}]
|
||||
set_property -dict {LOC AW18 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[50]}]
|
||||
set_property -dict {LOC AV19 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[51]}]
|
||||
set_property -dict {LOC AY18 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[52]}]
|
||||
set_property -dict {LOC AY20 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[53]}]
|
||||
set_property -dict {LOC AV18 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[54]}]
|
||||
set_property -dict {LOC BA18 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[55]}]
|
||||
set_property -dict {LOC BE18 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[56]}]
|
||||
set_property -dict {LOC BB17 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[57]}]
|
||||
set_property -dict {LOC BC18 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[58]}]
|
||||
set_property -dict {LOC BD18 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[59]}]
|
||||
set_property -dict {LOC BC17 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[60]}]
|
||||
set_property -dict {LOC BF19 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[61]}]
|
||||
set_property -dict {LOC BB19 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[62]}]
|
||||
set_property -dict {LOC BF18 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[63]}]
|
||||
#set_property -dict {LOC AP16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[64]}]
|
||||
#set_property -dict {LOC BF17 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[65]}]
|
||||
#set_property -dict {LOC BB16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[66]}]
|
||||
#set_property -dict {LOC AW13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[67]}]
|
||||
#set_property -dict {LOC BF7 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[68]}]
|
||||
#set_property -dict {LOC BD11 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[69]}]
|
||||
#set_property -dict {LOC AN17 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dq[70]}]
|
||||
set_property -dict {LOC BE11 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_a_dqs_t[0]}]
|
||||
set_property -dict {LOC BE10 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_a_dqs_c[0]}]
|
||||
set_property -dict {LOC BA7 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_a_dqs_t[1]}]
|
||||
set_property -dict {LOC BB7 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_a_dqs_c[1]}]
|
||||
set_property -dict {LOC BB15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_a_dqs_t[2]}]
|
||||
set_property -dict {LOC BB14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_a_dqs_c[2]}]
|
||||
set_property -dict {LOC AU14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_a_dqs_t[3]}]
|
||||
set_property -dict {LOC AV14 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_a_dqs_c[3]}]
|
||||
set_property -dict {LOC AL17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_a_dqs_t[4]}]
|
||||
set_property -dict {LOC AM17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_a_dqs_c[4]}]
|
||||
set_property -dict {LOC AR17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_a_dqs_t[5]}]
|
||||
set_property -dict {LOC AT17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_a_dqs_c[5]}]
|
||||
set_property -dict {LOC AV21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_a_dqs_t[6]}]
|
||||
set_property -dict {LOC AW21 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_a_dqs_c[6]}]
|
||||
set_property -dict {LOC BC19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_a_dqs_t[7]}]
|
||||
set_property -dict {LOC BD19 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_a_dqs_c[7]}]
|
||||
set_property -dict {LOC BE7 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dm_dbi_n[0]}]
|
||||
set_property -dict {LOC BC12 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dm_dbi_n[1]}]
|
||||
set_property -dict {LOC BA12 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dm_dbi_n[2]}]
|
||||
set_property -dict {LOC AW14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dm_dbi_n[3]}]
|
||||
set_property -dict {LOC AN18 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dm_dbi_n[4]}]
|
||||
set_property -dict {LOC AT19 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dm_dbi_n[5]}]
|
||||
set_property -dict {LOC AY17 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dm_dbi_n[6]}]
|
||||
set_property -dict {LOC BE17 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_a_dm_dbi_n[7]}]
|
||||
|
||||
# DDR4 SODIMM B
|
||||
set_property -dict {LOC G20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_adr[0]}]
|
||||
set_property -dict {LOC G19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_adr[1]}]
|
||||
set_property -dict {LOC F20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_adr[2]}]
|
||||
set_property -dict {LOC E21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_adr[3]}]
|
||||
set_property -dict {LOC F19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_adr[4]}]
|
||||
set_property -dict {LOC E20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_adr[5]}]
|
||||
set_property -dict {LOC F18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_adr[6]}]
|
||||
set_property -dict {LOC F17 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_adr[7]}]
|
||||
set_property -dict {LOC G21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_adr[8]}]
|
||||
set_property -dict {LOC D19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_adr[9]}]
|
||||
set_property -dict {LOC C19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_adr[10]}]
|
||||
set_property -dict {LOC D21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_adr[11]}]
|
||||
set_property -dict {LOC D20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_adr[12]}]
|
||||
set_property -dict {LOC A19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_adr[13]}]
|
||||
set_property -dict {LOC B21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_adr[14]}]
|
||||
set_property -dict {LOC D18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_adr[15]}]
|
||||
set_property -dict {LOC C18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_adr[16]}]
|
||||
set_property -dict {LOC B19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_ba[0]}]
|
||||
set_property -dict {LOC C21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_ba[1]}]
|
||||
set_property -dict {LOC B20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_bg[0]}]
|
||||
set_property -dict {LOC A20 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_bg[1]}]
|
||||
set_property -dict {LOC E18 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_sodimm_b_ck_t[0]}]
|
||||
set_property -dict {LOC E17 IOSTANDARD DIFF_SSTL12_DCI } [get_ports {ddr4_sodimm_b_ck_c[0]}]
|
||||
set_property -dict {LOC A18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_cke[0]}]
|
||||
set_property -dict {LOC H21 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_cs_n[0]}]
|
||||
#set_property -dict {LOC K13 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_cs_n[2]}]
|
||||
#set_property -dict {LOC D14 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_cs_n[3]}]
|
||||
set_property -dict {LOC L18 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_act_n}]
|
||||
set_property -dict {LOC L19 IOSTANDARD SSTL12_DCI } [get_ports {ddr4_sodimm_b_odt[0]}]
|
||||
set_property -dict {LOC L20 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports {ddr4_sodimm_b_reset_n}]
|
||||
set_property -dict {LOC C17 IOSTANDARD LVCMOS12 } [get_ports {ddr4_sodimm_b_alert_n}]
|
||||
set_property -dict {LOC F14 IOSTANDARD LVCMOS12 } [get_ports {ddr4_sodimm_b_event_n}]
|
||||
|
||||
set_property -dict {LOC N22 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[0]}]
|
||||
set_property -dict {LOC M25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[1]}]
|
||||
set_property -dict {LOC P23 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[2]}]
|
||||
set_property -dict {LOC P25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[3]}]
|
||||
set_property -dict {LOC R25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[4]}]
|
||||
set_property -dict {LOC M24 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[5]}]
|
||||
set_property -dict {LOC M22 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[6]}]
|
||||
set_property -dict {LOC N23 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[7]}]
|
||||
set_property -dict {LOC C24 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[8]}]
|
||||
set_property -dict {LOC B25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[9]}]
|
||||
set_property -dict {LOC C26 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[10]}]
|
||||
set_property -dict {LOC A24 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[11]}]
|
||||
set_property -dict {LOC C23 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[12]}]
|
||||
set_property -dict {LOC A25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[13]}]
|
||||
set_property -dict {LOC B24 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[14]}]
|
||||
set_property -dict {LOC B26 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[15]}]
|
||||
set_property -dict {LOC K22 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[16]}]
|
||||
set_property -dict {LOC J23 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[17]}]
|
||||
set_property -dict {LOC H23 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[18]}]
|
||||
set_property -dict {LOC J24 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[19]}]
|
||||
set_property -dict {LOC L22 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[20]}]
|
||||
set_property -dict {LOC H24 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[21]}]
|
||||
set_property -dict {LOC L23 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[22]}]
|
||||
set_property -dict {LOC K23 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[23]}]
|
||||
set_property -dict {LOC F23 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[24]}]
|
||||
set_property -dict {LOC F24 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[25]}]
|
||||
set_property -dict {LOC E25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[26]}]
|
||||
set_property -dict {LOC F22 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[27]}]
|
||||
set_property -dict {LOC G22 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[28]}]
|
||||
set_property -dict {LOC D24 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[29]}]
|
||||
set_property -dict {LOC D25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[30]}]
|
||||
set_property -dict {LOC D23 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[31]}]
|
||||
set_property -dict {LOC A13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[32]}]
|
||||
set_property -dict {LOC A17 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[33]}]
|
||||
set_property -dict {LOC B16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[34]}]
|
||||
set_property -dict {LOC C14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[35]}]
|
||||
set_property -dict {LOC A14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[36]}]
|
||||
set_property -dict {LOC B17 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[37]}]
|
||||
set_property -dict {LOC C16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[38]}]
|
||||
set_property -dict {LOC B14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[39]}]
|
||||
set_property -dict {LOC E16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[40]}]
|
||||
set_property -dict {LOC D15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[41]}]
|
||||
set_property -dict {LOC E15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[42]}]
|
||||
set_property -dict {LOC G15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[43]}]
|
||||
set_property -dict {LOC F15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[44]}]
|
||||
set_property -dict {LOC E13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[45]}]
|
||||
set_property -dict {LOC D16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[46]}]
|
||||
set_property -dict {LOC F13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[47]}]
|
||||
set_property -dict {LOC J13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[48]}]
|
||||
set_property -dict {LOC J15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[49]}]
|
||||
set_property -dict {LOC H14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[50]}]
|
||||
set_property -dict {LOC J16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[51]}]
|
||||
set_property -dict {LOC K16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[52]}]
|
||||
set_property -dict {LOC H13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[53]}]
|
||||
set_property -dict {LOC J14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[54]}]
|
||||
set_property -dict {LOC K15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[55]}]
|
||||
set_property -dict {LOC P15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[56]}]
|
||||
set_property -dict {LOC M14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[57]}]
|
||||
set_property -dict {LOC M16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[58]}]
|
||||
set_property -dict {LOC R15 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[59]}]
|
||||
set_property -dict {LOC L14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[60]}]
|
||||
set_property -dict {LOC P14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[61]}]
|
||||
set_property -dict {LOC N16 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[62]}]
|
||||
set_property -dict {LOC N14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[63]}]
|
||||
#set_property -dict {LOC J19 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[64]}]
|
||||
#set_property -dict {LOC K21 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[65]}]
|
||||
#set_property -dict {LOC H22 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[66]}]
|
||||
#set_property -dict {LOC G24 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[67]}]
|
||||
#set_property -dict {LOC P21 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[68]}]
|
||||
#set_property -dict {LOC D26 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[69]}]
|
||||
#set_property -dict {LOC C13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dq[70]}]
|
||||
set_property -dict {LOC P24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_b_dqs_t[0]}]
|
||||
set_property -dict {LOC N24 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_b_dqs_c[0]}]
|
||||
set_property -dict {LOC A23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_b_dqs_t[1]}]
|
||||
set_property -dict {LOC A22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_b_dqs_c[1]}]
|
||||
set_property -dict {LOC K25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_b_dqs_t[2]}]
|
||||
set_property -dict {LOC J25 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_b_dqs_c[2]}]
|
||||
set_property -dict {LOC E23 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_b_dqs_t[3]}]
|
||||
set_property -dict {LOC E22 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_b_dqs_c[3]}]
|
||||
set_property -dict {LOC B15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_b_dqs_t[4]}]
|
||||
set_property -dict {LOC A15 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_b_dqs_c[4]}]
|
||||
set_property -dict {LOC G17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_b_dqs_t[5]}]
|
||||
set_property -dict {LOC G16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_b_dqs_c[5]}]
|
||||
set_property -dict {LOC H17 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_b_dqs_t[6]}]
|
||||
set_property -dict {LOC H16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_b_dqs_c[6]}]
|
||||
set_property -dict {LOC R16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_b_dqs_t[7]}]
|
||||
set_property -dict {LOC P16 IOSTANDARD DIFF_POD12_DCI } [get_ports {ddr4_sodimm_b_dqs_c[7]}]
|
||||
set_property -dict {LOC R21 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dm_dbi_n[0]}]
|
||||
set_property -dict {LOC C22 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dm_dbi_n[1]}]
|
||||
set_property -dict {LOC L25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dm_dbi_n[2]}]
|
||||
set_property -dict {LOC G25 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dm_dbi_n[3]}]
|
||||
set_property -dict {LOC D13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dm_dbi_n[4]}]
|
||||
set_property -dict {LOC G14 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dm_dbi_n[5]}]
|
||||
set_property -dict {LOC L13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dm_dbi_n[6]}]
|
||||
set_property -dict {LOC P13 IOSTANDARD POD12_DCI } [get_ports {ddr4_sodimm_b_dm_dbi_n[7]}]
|
||||
|
||||
@ -9,6 +9,7 @@ FPGA_ARCH = virtexuplus
|
||||
# Files for synthesis
|
||||
SYN_FILES = rtl/fpga.v
|
||||
SYN_FILES += rtl/fpga_core.v
|
||||
SYN_FILES += rtl/bmc_spi.v
|
||||
SYN_FILES += rtl/sync_signal.v
|
||||
SYN_FILES += rtl/common/mqnic_core_pcie_us.v
|
||||
SYN_FILES += rtl/common/mqnic_core_pcie.v
|
||||
@ -129,6 +130,7 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
|
||||
# XDC files
|
||||
XDC_FILES = fpga.xdc
|
||||
XDC_FILES += placement.xdc
|
||||
XDC_FILES += boot.xdc
|
||||
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
|
||||
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
|
||||
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
|
||||
@ -143,6 +145,8 @@ XDC_FILES += ../../../common/syn/vivado/led_sreg_driver.tcl
|
||||
# IP
|
||||
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
|
||||
IP_TCL_FILES += ip/eth_xcvr_gty.tcl
|
||||
#IP_TCL_FILES += ip/ddr4_0.tcl
|
||||
#IP_TCL_FILES += ip/ddr4_sodimm_0.tcl
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
@ -120,6 +120,12 @@ dict set params MAX_RX_SIZE "9214"
|
||||
dict set params TX_RAM_SIZE "32768"
|
||||
dict set params RX_RAM_SIZE "131072"
|
||||
|
||||
# RAM configuration
|
||||
dict set params DDR_CH "4"
|
||||
dict set params DDR_ENABLE "0"
|
||||
dict set params AXI_DDR_ID_WIDTH "8"
|
||||
dict set params AXI_DDR_MAX_BURST_LEN "256"
|
||||
|
||||
# Application block configuration
|
||||
dict set params APP_ID "32'h00000000"
|
||||
dict set params APP_ENABLE "0"
|
||||
@ -164,6 +170,43 @@ dict set params STAT_PCIE_ENABLE "1"
|
||||
dict set params STAT_INC_WIDTH "24"
|
||||
dict set params STAT_ID_WIDTH "12"
|
||||
|
||||
# DDR4 MIG settings
|
||||
if {[dict get $params DDR_ENABLE]} {
|
||||
# components (DDR4 A, DDR4 B)
|
||||
set ddr4 [get_ips ddr4_0]
|
||||
|
||||
# performance-related configuration
|
||||
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
|
||||
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
|
||||
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
|
||||
|
||||
# set AXI ID width
|
||||
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
|
||||
|
||||
# extract AXI configuration
|
||||
dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4]
|
||||
dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4]
|
||||
dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1]
|
||||
|
||||
if {[dict get $params DDR_CH] > 2} {
|
||||
# SO-DIMMs (DDR4 SODMM A, DDR4 SODIMM B)
|
||||
set ddr4 [get_ips ddr4_sodimm_0]
|
||||
|
||||
# performance-related configuration
|
||||
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
|
||||
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
|
||||
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
|
||||
|
||||
# set AXI ID width
|
||||
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
|
||||
|
||||
# extract AXI configuration
|
||||
dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4]
|
||||
dict set params AXI_DDR_ADDR_WIDTH [expr max([get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4], [dict get $params AXI_DDR_ADDR_WIDTH])]
|
||||
dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && [dict get $params AXI_DDR_NARROW_BURST]]
|
||||
}
|
||||
}
|
||||
|
||||
# PCIe IP core settings
|
||||
set pcie [get_ips pcie4_uscale_plus_0]
|
||||
|
||||
|
||||
@ -9,6 +9,7 @@ FPGA_ARCH = virtexuplus
|
||||
# Files for synthesis
|
||||
SYN_FILES = rtl/fpga.v
|
||||
SYN_FILES += rtl/fpga_core.v
|
||||
SYN_FILES += rtl/bmc_spi.v
|
||||
SYN_FILES += rtl/sync_signal.v
|
||||
SYN_FILES += rtl/common/mqnic_core_pcie_us.v
|
||||
SYN_FILES += rtl/common/mqnic_core_pcie.v
|
||||
@ -129,6 +130,7 @@ SYN_FILES += lib/pcie/rtl/pulse_merge.v
|
||||
# XDC files
|
||||
XDC_FILES = fpga.xdc
|
||||
XDC_FILES += placement.xdc
|
||||
XDC_FILES += boot.xdc
|
||||
XDC_FILES += lib/axis/syn/vivado/axis_async_fifo.tcl
|
||||
XDC_FILES += lib/axis/syn/vivado/sync_reset.tcl
|
||||
XDC_FILES += lib/eth/syn/vivado/ptp_clock_cdc.tcl
|
||||
@ -143,6 +145,8 @@ XDC_FILES += ../../../common/syn/vivado/led_sreg_driver.tcl
|
||||
# IP
|
||||
IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
|
||||
IP_TCL_FILES += ip/eth_xcvr_gty.tcl
|
||||
#IP_TCL_FILES += ip/ddr4_0.tcl
|
||||
#IP_TCL_FILES += ip/ddr4_sodimm_0.tcl
|
||||
|
||||
# Configuration
|
||||
CONFIG_TCL_FILES = ./config.tcl
|
||||
|
||||
@ -120,6 +120,12 @@ dict set params MAX_RX_SIZE "9214"
|
||||
dict set params TX_RAM_SIZE "32768"
|
||||
dict set params RX_RAM_SIZE "32768"
|
||||
|
||||
# RAM configuration
|
||||
dict set params DDR_CH "4"
|
||||
dict set params DDR_ENABLE "0"
|
||||
dict set params AXI_DDR_ID_WIDTH "8"
|
||||
dict set params AXI_DDR_MAX_BURST_LEN "256"
|
||||
|
||||
# Application block configuration
|
||||
dict set params APP_ID "32'h00000000"
|
||||
dict set params APP_ENABLE "0"
|
||||
@ -164,6 +170,43 @@ dict set params STAT_PCIE_ENABLE "1"
|
||||
dict set params STAT_INC_WIDTH "24"
|
||||
dict set params STAT_ID_WIDTH "12"
|
||||
|
||||
# DDR4 MIG settings
|
||||
if {[dict get $params DDR_ENABLE]} {
|
||||
# components (DDR4 A, DDR4 B)
|
||||
set ddr4 [get_ips ddr4_0]
|
||||
|
||||
# performance-related configuration
|
||||
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
|
||||
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
|
||||
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
|
||||
|
||||
# set AXI ID width
|
||||
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
|
||||
|
||||
# extract AXI configuration
|
||||
dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4]
|
||||
dict set params AXI_DDR_ADDR_WIDTH [get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4]
|
||||
dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && 1]
|
||||
|
||||
if {[dict get $params DDR_CH] > 2} {
|
||||
# SO-DIMMs (DDR4 SODMM A, DDR4 SODIMM B)
|
||||
set ddr4 [get_ips ddr4_sodimm_0]
|
||||
|
||||
# performance-related configuration
|
||||
set_property CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} $ddr4
|
||||
set_property CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} $ddr4
|
||||
set_property CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV} $ddr4
|
||||
|
||||
# set AXI ID width
|
||||
set_property CONFIG.C0.DDR4_AxiIDWidth [dict get $params AXI_DDR_ID_WIDTH] $ddr4
|
||||
|
||||
# extract AXI configuration
|
||||
dict set params AXI_DDR_DATA_WIDTH [get_property CONFIG.C0.DDR4_AxiDataWidth $ddr4]
|
||||
dict set params AXI_DDR_ADDR_WIDTH [expr max([get_property CONFIG.C0.DDR4_AxiAddressWidth $ddr4], [dict get $params AXI_DDR_ADDR_WIDTH])]
|
||||
dict set params AXI_DDR_NARROW_BURST [expr [get_property CONFIG.C0.DDR4_AxiNarrowBurst $ddr4] && [dict get $params AXI_DDR_NARROW_BURST]]
|
||||
}
|
||||
}
|
||||
|
||||
# PCIe IP core settings
|
||||
set pcie [get_ips pcie4_uscale_plus_0]
|
||||
|
||||
|
||||
18
fpga/mqnic/fb4CGg3/fpga_25g/ip/ddr4_0.tcl
Normal file
18
fpga/mqnic/fb4CGg3/fpga_25g/ip/ddr4_0.tcl
Normal file
@ -0,0 +1,18 @@
|
||||
|
||||
create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_0
|
||||
|
||||
set_property -dict [list \
|
||||
CONFIG.C0.DDR4_AxiSelection {true} \
|
||||
CONFIG.C0.DDR4_AxiDataWidth {512} \
|
||||
CONFIG.C0.DDR4_AxiIDWidth {8} \
|
||||
CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \
|
||||
CONFIG.C0.DDR4_TimePeriod {833} \
|
||||
CONFIG.C0.DDR4_InputClockPeriod {3750} \
|
||||
CONFIG.C0.DDR4_MemoryType {Components} \
|
||||
CONFIG.C0.DDR4_MemoryPart {MT40A512M16HA-083E} \
|
||||
CONFIG.C0.DDR4_DataWidth {64} \
|
||||
CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \
|
||||
CONFIG.C0.DDR4_CasLatency {16} \
|
||||
CONFIG.C0.DDR4_CasWriteLatency {12} \
|
||||
CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV}
|
||||
] [get_ips ddr4_0]
|
||||
18
fpga/mqnic/fb4CGg3/fpga_25g/ip/ddr4_sodimm_0.tcl
Normal file
18
fpga/mqnic/fb4CGg3/fpga_25g/ip/ddr4_sodimm_0.tcl
Normal file
@ -0,0 +1,18 @@
|
||||
|
||||
create_ip -name ddr4 -vendor xilinx.com -library ip -module_name ddr4_sodimm_0
|
||||
|
||||
set_property -dict [list \
|
||||
CONFIG.C0.DDR4_AxiSelection {true} \
|
||||
CONFIG.C0.DDR4_AxiDataWidth {512} \
|
||||
CONFIG.C0.DDR4_AxiIDWidth {8} \
|
||||
CONFIG.C0.DDR4_AxiArbitrationScheme {RD_PRI_REG} \
|
||||
CONFIG.C0.DDR4_TimePeriod {833} \
|
||||
CONFIG.C0.DDR4_InputClockPeriod {3750} \
|
||||
CONFIG.C0.DDR4_MemoryType {SODIMMs} \
|
||||
CONFIG.C0.DDR4_MemoryPart {MTA8ATF1G64HZ-2G3} \
|
||||
CONFIG.C0.DDR4_DataWidth {64} \
|
||||
CONFIG.C0.DDR4_AUTO_AP_COL_A3 {true} \
|
||||
CONFIG.C0.DDR4_CasLatency {17} \
|
||||
CONFIG.C0.DDR4_CasWriteLatency {12} \
|
||||
CONFIG.C0.DDR4_Mem_Add_Map {ROW_COLUMN_BANK_INTLV}
|
||||
] [get_ips ddr4_sodimm_0]
|
||||
262
fpga/mqnic/fb4CGg3/fpga_25g/rtl/bmc_spi.v
Normal file
262
fpga/mqnic/fb4CGg3/fpga_25g/rtl/bmc_spi.v
Normal file
@ -0,0 +1,262 @@
|
||||
// SPDX-License-Identifier: BSD-2-Clause-Views
|
||||
/*
|
||||
* Copyright (c) 2021-2023 The Regents of the University of California
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`resetall
|
||||
`timescale 1ns / 1ps
|
||||
`default_nettype none
|
||||
|
||||
/*
|
||||
* Board management controller interface
|
||||
*/
|
||||
module bmc_spi #(
|
||||
// clock prescale (SPI clock half period in cycles of clk)
|
||||
parameter PRESCALE = 125,
|
||||
// byte wait time (SPI clock cycles)
|
||||
parameter BYTE_WAIT = 32,
|
||||
// timeout (SPI clock cycles)
|
||||
parameter TIMEOUT = 5000
|
||||
)
|
||||
(
|
||||
input wire clk,
|
||||
input wire rst,
|
||||
|
||||
input wire [15:0] ctrl_cmd,
|
||||
input wire [31:0] ctrl_data,
|
||||
input wire ctrl_valid,
|
||||
|
||||
output wire [15:0] read_data,
|
||||
|
||||
output wire status_idle,
|
||||
output wire status_done,
|
||||
output wire status_timeout,
|
||||
|
||||
output wire bmc_clk,
|
||||
output wire bmc_nss,
|
||||
output wire bmc_mosi,
|
||||
input wire bmc_miso,
|
||||
input wire bmc_int
|
||||
);
|
||||
|
||||
localparam CL_PRESCALE = $clog2(PRESCALE+1);
|
||||
localparam CL_DELAY = $clog2((BYTE_WAIT > TIMEOUT ? BYTE_WAIT : TIMEOUT)+1);
|
||||
|
||||
/*
|
||||
|
||||
SPI protocol:
|
||||
|
||||
8 byte transfer, MSB first
|
||||
|
||||
2 byte command
|
||||
4 byte data
|
||||
wait for int
|
||||
2 byte read data
|
||||
|
||||
nss deasserted between each byte
|
||||
wait 32 SPI cycle times between bytes
|
||||
wait up to 5 ms for int assert from bmc
|
||||
|
||||
*/
|
||||
|
||||
localparam [2:0]
|
||||
STATE_IDLE = 3'd0,
|
||||
STATE_SHIFT = 3'd1,
|
||||
STATE_WAIT_BYTE = 3'd2,
|
||||
STATE_WAIT_INT = 3'd3;
|
||||
|
||||
reg [2:0] state_reg = STATE_IDLE, state_next;
|
||||
|
||||
reg [15:0] read_data_reg = 15'd0, read_data_next;
|
||||
|
||||
reg status_idle_reg = 1'b0;
|
||||
reg status_done_reg = 1'b0, status_done_next;
|
||||
reg status_timeout_reg = 1'b0, status_timeout_next;
|
||||
|
||||
reg bmc_clk_reg = 1'b1, bmc_clk_next;
|
||||
reg bmc_nss_reg = 1'b1, bmc_nss_next;
|
||||
reg bmc_mosi_reg = 1'b1, bmc_mosi_next;
|
||||
reg bmc_miso_reg = 1'b1;
|
||||
reg bmc_int_reg = 1'b0;
|
||||
|
||||
reg [CL_PRESCALE+1-1:0] prescale_count_reg = 0, prescale_count_next;
|
||||
reg [CL_DELAY-1:0] delay_count_reg = 0, delay_count_next;
|
||||
reg [3:0] bit_count_reg = 0, bit_count_next;
|
||||
reg [3:0] byte_count_reg = 0, byte_count_next;
|
||||
reg [47:0] data_out_reg = 0, data_out_next;
|
||||
reg [15:0] data_in_reg = 0, data_in_next;
|
||||
reg int_reg = 0, int_next;
|
||||
|
||||
assign read_data = read_data_reg;
|
||||
|
||||
assign status_idle = status_idle_reg;
|
||||
assign status_done = status_done_reg;
|
||||
assign status_timeout = status_timeout_reg;
|
||||
|
||||
assign bmc_clk = bmc_clk_reg;
|
||||
assign bmc_nss = bmc_nss_reg;
|
||||
assign bmc_mosi = bmc_mosi_reg;
|
||||
|
||||
always @* begin
|
||||
state_next = state_reg;
|
||||
|
||||
read_data_next = read_data_reg;
|
||||
|
||||
status_done_next = status_done_reg;
|
||||
status_timeout_next = status_timeout_reg;
|
||||
|
||||
bmc_clk_next = bmc_clk_reg;
|
||||
bmc_nss_next = bmc_nss_reg;
|
||||
bmc_mosi_next = bmc_mosi_reg;
|
||||
|
||||
prescale_count_next = prescale_count_reg;
|
||||
delay_count_next = delay_count_reg;
|
||||
bit_count_next = bit_count_reg;
|
||||
byte_count_next = byte_count_reg;
|
||||
data_out_next = data_out_reg;
|
||||
data_in_next = data_in_reg;
|
||||
int_next = int_reg;
|
||||
|
||||
if (prescale_count_reg != 0) begin
|
||||
prescale_count_next = prescale_count_reg - 1;
|
||||
end else if (bmc_clk_reg == 1'b0) begin
|
||||
bmc_clk_next = 1'b1;
|
||||
prescale_count_next = PRESCALE;
|
||||
end else if (delay_count_reg != 0) begin
|
||||
delay_count_next = delay_count_reg - 1;
|
||||
prescale_count_next = PRESCALE*2;
|
||||
end
|
||||
|
||||
if (bmc_int_reg) begin
|
||||
int_next = 1'b1;
|
||||
end
|
||||
|
||||
case (state_reg)
|
||||
STATE_IDLE: begin
|
||||
bmc_clk_next = 1'b1;
|
||||
bmc_nss_next = 1'b1;
|
||||
|
||||
prescale_count_next = 0;
|
||||
delay_count_next = 0;
|
||||
bit_count_next = 8;
|
||||
byte_count_next = 8;
|
||||
data_out_next = {ctrl_cmd, ctrl_data};
|
||||
int_next = 1'b0;
|
||||
|
||||
if (ctrl_valid) begin
|
||||
status_done_next = 1'b0;
|
||||
status_timeout_next = 1'b0;
|
||||
bmc_nss_next = 1'b0;
|
||||
prescale_count_next = PRESCALE*2;
|
||||
state_next = STATE_SHIFT;
|
||||
end
|
||||
end
|
||||
STATE_SHIFT: begin
|
||||
if (prescale_count_reg == 0 && bmc_clk_reg) begin
|
||||
if (bit_count_reg != 8) begin
|
||||
// shift in bit
|
||||
data_in_next = {data_in_reg, bmc_miso_reg};
|
||||
end
|
||||
|
||||
if (bit_count_reg != 0) begin
|
||||
// more bits to send; send the next bit
|
||||
bmc_clk_next = 1'b0;
|
||||
prescale_count_next = PRESCALE;
|
||||
bit_count_next = bit_count_reg - 1;
|
||||
{bmc_mosi_next, data_out_next} = {data_out_reg, 1'b0};
|
||||
state_next = STATE_SHIFT;
|
||||
end else begin
|
||||
// at the end of the byte; small delay
|
||||
bmc_nss_next = 1'b1;
|
||||
delay_count_next = BYTE_WAIT;
|
||||
bit_count_next = 8;
|
||||
byte_count_next = byte_count_reg - 1;
|
||||
state_next = STATE_WAIT_BYTE;
|
||||
end
|
||||
end else begin
|
||||
state_next = STATE_SHIFT;
|
||||
end
|
||||
end
|
||||
STATE_WAIT_BYTE: begin
|
||||
// byte wait state; wait for delay timer
|
||||
if (delay_count_reg == 0) begin
|
||||
if (byte_count_reg == 2) begin
|
||||
// command sent; wait for int from BMC
|
||||
delay_count_next = TIMEOUT;
|
||||
state_next = STATE_WAIT_INT;
|
||||
end else if (byte_count_reg == 0) begin
|
||||
// done with operation; return to idle
|
||||
read_data_next = data_in_reg;
|
||||
status_done_next = 1'b1;
|
||||
state_next = STATE_IDLE;
|
||||
end else begin
|
||||
// not at end of command; send next byte
|
||||
bmc_nss_next = 1'b0;
|
||||
prescale_count_next = PRESCALE*2;
|
||||
state_next = STATE_SHIFT;
|
||||
end
|
||||
end else begin
|
||||
state_next = STATE_WAIT_BYTE;
|
||||
end
|
||||
end
|
||||
STATE_WAIT_INT: begin
|
||||
// wait for int from BMC
|
||||
if (int_reg) begin
|
||||
// got int, go back to shift state
|
||||
bmc_nss_next = 1'b0;
|
||||
prescale_count_next = PRESCALE*2;
|
||||
state_next = STATE_SHIFT;
|
||||
end else if (delay_count_reg == 0) begin
|
||||
// timed out waiting for BMC
|
||||
status_timeout_next = 1'b1;
|
||||
bmc_nss_next = 1'b0;
|
||||
prescale_count_next = PRESCALE*2;
|
||||
state_next = STATE_SHIFT;
|
||||
end else begin
|
||||
state_next = STATE_WAIT_INT;
|
||||
end
|
||||
end
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge clk) begin
|
||||
state_reg <= state_next;
|
||||
|
||||
read_data_reg <= read_data_next;
|
||||
|
||||
status_idle_reg <= state_next == STATE_IDLE;
|
||||
status_done_reg <= status_done_next;
|
||||
status_timeout_reg <= status_timeout_next;
|
||||
|
||||
bmc_clk_reg <= bmc_clk_next;
|
||||
bmc_nss_reg <= bmc_nss_next;
|
||||
bmc_mosi_reg <= bmc_mosi_next;
|
||||
bmc_miso_reg <= bmc_miso;
|
||||
bmc_int_reg <= bmc_int;
|
||||
|
||||
prescale_count_reg <= prescale_count_next;
|
||||
delay_count_reg <= delay_count_next;
|
||||
bit_count_reg <= bit_count_next;
|
||||
byte_count_reg <= byte_count_next;
|
||||
data_out_reg <= data_out_next;
|
||||
data_in_reg <= data_in_next;
|
||||
int_reg <= int_next;
|
||||
|
||||
if (rst) begin
|
||||
state_reg <= STATE_IDLE;
|
||||
|
||||
status_idle_reg <= 1'b0;
|
||||
status_done_reg <= 1'b0;
|
||||
status_timeout_reg <= 1'b0;
|
||||
|
||||
bmc_clk_reg <= 1'b1;
|
||||
bmc_nss_reg <= 1'b1;
|
||||
bmc_mosi_reg <= 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
`resetall
|
||||
@ -81,6 +81,15 @@ module fpga #
|
||||
parameter TX_RAM_SIZE = 32768,
|
||||
parameter RX_RAM_SIZE = 32768,
|
||||
|
||||
// RAM configuration
|
||||
parameter DDR_CH = 4,
|
||||
parameter DDR_ENABLE = 0,
|
||||
parameter AXI_DDR_DATA_WIDTH = 512,
|
||||
parameter AXI_DDR_ADDR_WIDTH = 32,
|
||||
parameter AXI_DDR_ID_WIDTH = 8,
|
||||
parameter AXI_DDR_MAX_BURST_LEN = 256,
|
||||
parameter AXI_DDR_NARROW_BURST = 0,
|
||||
|
||||
// Application block configuration
|
||||
parameter APP_ID = 32'h00000000,
|
||||
parameter APP_ENABLE = 0,
|
||||
@ -135,6 +144,14 @@ module fpga #
|
||||
* Clock: 100MHz
|
||||
*/
|
||||
input wire init_clk,
|
||||
input wire clk_ddr4_a_refclk_p,
|
||||
input wire clk_ddr4_a_refclk_n,
|
||||
input wire clk_ddr4_b_refclk_p,
|
||||
input wire clk_ddr4_b_refclk_n,
|
||||
input wire clk_sodimm_a_refclk_p,
|
||||
input wire clk_sodimm_a_refclk_n,
|
||||
input wire clk_sodimm_b_refclk_p,
|
||||
input wire clk_sodimm_b_refclk_n,
|
||||
|
||||
/*
|
||||
* GPIO
|
||||
@ -148,6 +165,14 @@ module fpga #
|
||||
input wire pps_in,
|
||||
output wire pps_out,
|
||||
|
||||
/*
|
||||
* BMC interface
|
||||
*/
|
||||
output wire bmc_clk,
|
||||
output wire bmc_nss,
|
||||
output wire bmc_mosi,
|
||||
input wire bmc_miso,
|
||||
|
||||
/*
|
||||
* PCI express
|
||||
*/
|
||||
@ -261,7 +286,76 @@ module fpga #
|
||||
output wire qsfp_3_lp_mode,
|
||||
input wire qsfp_3_intr_n,
|
||||
inout wire qsfp_3_i2c_scl,
|
||||
inout wire qsfp_3_i2c_sda
|
||||
inout wire qsfp_3_i2c_sda,
|
||||
|
||||
/*
|
||||
* DDR4
|
||||
*/
|
||||
output wire [16:0] ddr4_a_adr,
|
||||
output wire [1:0] ddr4_a_ba,
|
||||
output wire [1:0] ddr4_a_bg,
|
||||
output wire [0:0] ddr4_a_ck_t,
|
||||
output wire [0:0] ddr4_a_ck_c,
|
||||
output wire [0:0] ddr4_a_cke,
|
||||
output wire [0:0] ddr4_a_cs_n,
|
||||
output wire ddr4_a_act_n,
|
||||
output wire [0:0] ddr4_a_odt,
|
||||
output wire ddr4_a_reset_n,
|
||||
output wire ddr4_a_ten,
|
||||
inout wire [63:0] ddr4_a_dq,
|
||||
inout wire [7:0] ddr4_a_dqs_t,
|
||||
inout wire [7:0] ddr4_a_dqs_c,
|
||||
inout wire [7:0] ddr4_a_dm_dbi_n,
|
||||
|
||||
output wire [16:0] ddr4_b_adr,
|
||||
output wire [1:0] ddr4_b_ba,
|
||||
output wire [1:0] ddr4_b_bg,
|
||||
output wire [0:0] ddr4_b_ck_t,
|
||||
output wire [0:0] ddr4_b_ck_c,
|
||||
output wire [0:0] ddr4_b_cke,
|
||||
output wire [0:0] ddr4_b_cs_n,
|
||||
output wire ddr4_b_act_n,
|
||||
output wire [0:0] ddr4_b_odt,
|
||||
output wire ddr4_b_reset_n,
|
||||
output wire ddr4_b_ten,
|
||||
inout wire [63:0] ddr4_b_dq,
|
||||
inout wire [7:0] ddr4_b_dqs_t,
|
||||
inout wire [7:0] ddr4_b_dqs_c,
|
||||
inout wire [7:0] ddr4_b_dm_dbi_n,
|
||||
|
||||
output wire [16:0] ddr4_sodimm_a_adr,
|
||||
output wire [1:0] ddr4_sodimm_a_ba,
|
||||
output wire [1:0] ddr4_sodimm_a_bg,
|
||||
output wire [0:0] ddr4_sodimm_a_ck_t,
|
||||
output wire [0:0] ddr4_sodimm_a_ck_c,
|
||||
output wire [0:0] ddr4_sodimm_a_cke,
|
||||
output wire [0:0] ddr4_sodimm_a_cs_n,
|
||||
output wire ddr4_sodimm_a_act_n,
|
||||
output wire [0:0] ddr4_sodimm_a_odt,
|
||||
output wire ddr4_sodimm_a_reset_n,
|
||||
input wire ddr4_sodimm_a_alert_n,
|
||||
input wire ddr4_sodimm_a_event_n,
|
||||
inout wire [63:0] ddr4_sodimm_a_dq,
|
||||
inout wire [7:0] ddr4_sodimm_a_dqs_t,
|
||||
inout wire [7:0] ddr4_sodimm_a_dqs_c,
|
||||
inout wire [7:0] ddr4_sodimm_a_dm_dbi_n,
|
||||
|
||||
output wire [16:0] ddr4_sodimm_b_adr,
|
||||
output wire [1:0] ddr4_sodimm_b_ba,
|
||||
output wire [1:0] ddr4_sodimm_b_bg,
|
||||
output wire [0:0] ddr4_sodimm_b_ck_t,
|
||||
output wire [0:0] ddr4_sodimm_b_ck_c,
|
||||
output wire [0:0] ddr4_sodimm_b_cke,
|
||||
output wire [0:0] ddr4_sodimm_b_cs_n,
|
||||
output wire ddr4_sodimm_b_act_n,
|
||||
output wire [0:0] ddr4_sodimm_b_odt,
|
||||
output wire ddr4_sodimm_b_reset_n,
|
||||
input wire ddr4_sodimm_b_alert_n,
|
||||
input wire ddr4_sodimm_b_event_n,
|
||||
inout wire [63:0] ddr4_sodimm_b_dq,
|
||||
inout wire [7:0] ddr4_sodimm_b_dqs_t,
|
||||
inout wire [7:0] ddr4_sodimm_b_dqs_c,
|
||||
inout wire [7:0] ddr4_sodimm_b_dm_dbi_n
|
||||
);
|
||||
|
||||
// PTP configuration
|
||||
@ -275,6 +369,9 @@ parameter IF_PTP_PERIOD_FNS = 16'h8F5C;
|
||||
// Interface configuration
|
||||
parameter TX_TAG_WIDTH = 16;
|
||||
|
||||
// RAM configuration
|
||||
parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8);
|
||||
|
||||
// PCIe interface configuration
|
||||
parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32);
|
||||
parameter AXIS_PCIE_RC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 75 : 161;
|
||||
@ -508,6 +605,121 @@ led_sreg_driver_inst (
|
||||
.sreg_clk(led_sreg_clk)
|
||||
);
|
||||
|
||||
// FPGA boot
|
||||
wire fpga_boot;
|
||||
|
||||
reg fpga_boot_sync_reg_0 = 1'b0;
|
||||
reg fpga_boot_sync_reg_1 = 1'b0;
|
||||
reg fpga_boot_sync_reg_2 = 1'b0;
|
||||
|
||||
wire icap_avail;
|
||||
reg [2:0] icap_state = 0;
|
||||
reg icap_csib_reg = 1'b1;
|
||||
reg icap_rdwrb_reg = 1'b0;
|
||||
reg [31:0] icap_di_reg = 32'hffffffff;
|
||||
|
||||
wire [31:0] icap_di_rev;
|
||||
|
||||
assign icap_di_rev[ 7] = icap_di_reg[ 0];
|
||||
assign icap_di_rev[ 6] = icap_di_reg[ 1];
|
||||
assign icap_di_rev[ 5] = icap_di_reg[ 2];
|
||||
assign icap_di_rev[ 4] = icap_di_reg[ 3];
|
||||
assign icap_di_rev[ 3] = icap_di_reg[ 4];
|
||||
assign icap_di_rev[ 2] = icap_di_reg[ 5];
|
||||
assign icap_di_rev[ 1] = icap_di_reg[ 6];
|
||||
assign icap_di_rev[ 0] = icap_di_reg[ 7];
|
||||
|
||||
assign icap_di_rev[15] = icap_di_reg[ 8];
|
||||
assign icap_di_rev[14] = icap_di_reg[ 9];
|
||||
assign icap_di_rev[13] = icap_di_reg[10];
|
||||
assign icap_di_rev[12] = icap_di_reg[11];
|
||||
assign icap_di_rev[11] = icap_di_reg[12];
|
||||
assign icap_di_rev[10] = icap_di_reg[13];
|
||||
assign icap_di_rev[ 9] = icap_di_reg[14];
|
||||
assign icap_di_rev[ 8] = icap_di_reg[15];
|
||||
|
||||
assign icap_di_rev[23] = icap_di_reg[16];
|
||||
assign icap_di_rev[22] = icap_di_reg[17];
|
||||
assign icap_di_rev[21] = icap_di_reg[18];
|
||||
assign icap_di_rev[20] = icap_di_reg[19];
|
||||
assign icap_di_rev[19] = icap_di_reg[20];
|
||||
assign icap_di_rev[18] = icap_di_reg[21];
|
||||
assign icap_di_rev[17] = icap_di_reg[22];
|
||||
assign icap_di_rev[16] = icap_di_reg[23];
|
||||
|
||||
assign icap_di_rev[31] = icap_di_reg[24];
|
||||
assign icap_di_rev[30] = icap_di_reg[25];
|
||||
assign icap_di_rev[29] = icap_di_reg[26];
|
||||
assign icap_di_rev[28] = icap_di_reg[27];
|
||||
assign icap_di_rev[27] = icap_di_reg[28];
|
||||
assign icap_di_rev[26] = icap_di_reg[29];
|
||||
assign icap_di_rev[25] = icap_di_reg[30];
|
||||
assign icap_di_rev[24] = icap_di_reg[31];
|
||||
|
||||
always @(posedge clk_125mhz_int) begin
|
||||
case (icap_state)
|
||||
0: begin
|
||||
icap_state <= 0;
|
||||
icap_csib_reg <= 1'b1;
|
||||
icap_rdwrb_reg <= 1'b0;
|
||||
icap_di_reg <= 32'hffffffff; // dummy word
|
||||
|
||||
if (fpga_boot_sync_reg_2 && icap_avail) begin
|
||||
icap_state <= 1;
|
||||
icap_csib_reg <= 1'b0;
|
||||
icap_rdwrb_reg <= 1'b0;
|
||||
icap_di_reg <= 32'hffffffff; // dummy word
|
||||
end
|
||||
end
|
||||
1: begin
|
||||
icap_state <= 2;
|
||||
icap_csib_reg <= 1'b0;
|
||||
icap_rdwrb_reg <= 1'b0;
|
||||
icap_di_reg <= 32'hAA995566; // sync word
|
||||
end
|
||||
2: begin
|
||||
icap_state <= 3;
|
||||
icap_csib_reg <= 1'b0;
|
||||
icap_rdwrb_reg <= 1'b0;
|
||||
icap_di_reg <= 32'h20000000; // type 1 noop
|
||||
end
|
||||
3: begin
|
||||
icap_state <= 4;
|
||||
icap_csib_reg <= 1'b0;
|
||||
icap_rdwrb_reg <= 1'b0;
|
||||
icap_di_reg <= 32'h30008001; // write 1 word to CMD
|
||||
end
|
||||
4: begin
|
||||
icap_state <= 5;
|
||||
icap_csib_reg <= 1'b0;
|
||||
icap_rdwrb_reg <= 1'b0;
|
||||
icap_di_reg <= 32'h0000000F; // IPROG
|
||||
end
|
||||
5: begin
|
||||
icap_state <= 0;
|
||||
icap_csib_reg <= 1'b0;
|
||||
icap_rdwrb_reg <= 1'b0;
|
||||
icap_di_reg <= 32'h20000000; // type 1 noop
|
||||
end
|
||||
endcase
|
||||
|
||||
fpga_boot_sync_reg_0 <= fpga_boot;
|
||||
fpga_boot_sync_reg_1 <= fpga_boot_sync_reg_0;
|
||||
fpga_boot_sync_reg_2 <= fpga_boot_sync_reg_1;
|
||||
end
|
||||
|
||||
ICAPE3
|
||||
icape3_inst (
|
||||
.AVAIL(icap_avail),
|
||||
.CLK(clk_125mhz_int),
|
||||
.CSIB(icap_csib_reg),
|
||||
.I(icap_di_rev),
|
||||
.O(),
|
||||
.PRDONE(),
|
||||
.PRERROR(),
|
||||
.RDWRB(icap_rdwrb_reg)
|
||||
);
|
||||
|
||||
// PCIe
|
||||
wire pcie_sys_clk;
|
||||
wire pcie_sys_clk_gt;
|
||||
@ -1676,6 +1888,491 @@ assign led_green[13] = qsfp_3_rx_status_1;
|
||||
assign led_green[14] = qsfp_3_rx_status_2;
|
||||
assign led_green[15] = qsfp_3_rx_status_3;
|
||||
|
||||
// DDR4
|
||||
wire [DDR_CH-1:0] ddr_clk;
|
||||
wire [DDR_CH-1:0] ddr_rst;
|
||||
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid;
|
||||
wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr;
|
||||
wire [DDR_CH*8-1:0] m_axi_ddr_awlen;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_awsize;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_awburst;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_awlock;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_awcache;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_awprot;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_awqos;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_awvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_awready;
|
||||
wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata;
|
||||
wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_wlast;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_wvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_wready;
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_bresp;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_bvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_bready;
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid;
|
||||
wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr;
|
||||
wire [DDR_CH*8-1:0] m_axi_ddr_arlen;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_arsize;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_arburst;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_arlock;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_arcache;
|
||||
wire [DDR_CH*3-1:0] m_axi_ddr_arprot;
|
||||
wire [DDR_CH*4-1:0] m_axi_ddr_arqos;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_arvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_arready;
|
||||
wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid;
|
||||
wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata;
|
||||
wire [DDR_CH*2-1:0] m_axi_ddr_rresp;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_rlast;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_rvalid;
|
||||
wire [DDR_CH-1:0] m_axi_ddr_rready;
|
||||
|
||||
wire [DDR_CH-1:0] ddr_status;
|
||||
|
||||
generate
|
||||
|
||||
if (DDR_ENABLE && DDR_CH > 0) begin
|
||||
|
||||
reg ddr4_rst_reg = 1'b1;
|
||||
|
||||
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
|
||||
if (pcie_user_reset) begin
|
||||
ddr4_rst_reg <= 1'b1;
|
||||
end else begin
|
||||
ddr4_rst_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
ddr4_0 ddr4_a_inst (
|
||||
.c0_sys_clk_p(clk_ddr4_a_refclk_p),
|
||||
.c0_sys_clk_n(clk_ddr4_a_refclk_n),
|
||||
.sys_rst(ddr4_rst_reg),
|
||||
|
||||
.c0_init_calib_complete(ddr_status[0 +: 1]),
|
||||
.dbg_clk(),
|
||||
.dbg_bus(),
|
||||
|
||||
.c0_ddr4_adr(ddr4_a_adr),
|
||||
.c0_ddr4_ba(ddr4_a_ba),
|
||||
.c0_ddr4_cke(ddr4_a_cke),
|
||||
.c0_ddr4_cs_n(ddr4_a_cs_n),
|
||||
.c0_ddr4_dq(ddr4_a_dq),
|
||||
.c0_ddr4_dqs_t(ddr4_a_dqs_t),
|
||||
.c0_ddr4_dqs_c(ddr4_a_dqs_c),
|
||||
.c0_ddr4_dm_dbi_n(ddr4_a_dm_dbi_n),
|
||||
.c0_ddr4_odt(ddr4_a_odt),
|
||||
.c0_ddr4_bg(ddr4_a_bg),
|
||||
.c0_ddr4_reset_n(ddr4_a_reset_n),
|
||||
.c0_ddr4_act_n(ddr4_a_act_n),
|
||||
.c0_ddr4_ck_t(ddr4_a_ck_t),
|
||||
.c0_ddr4_ck_c(ddr4_a_ck_c),
|
||||
|
||||
.c0_ddr4_ui_clk(ddr_clk[0 +: 1]),
|
||||
.c0_ddr4_ui_clk_sync_rst(ddr_rst[0 +: 1]),
|
||||
|
||||
.c0_ddr4_aresetn(!ddr_rst[0 +: 1]),
|
||||
|
||||
.c0_ddr4_s_axi_awid(m_axi_ddr_awid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[0*8 +: 8]),
|
||||
.c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[0 +: 1]),
|
||||
.c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_awready(m_axi_ddr_awready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]),
|
||||
.c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[0*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]),
|
||||
.c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[0 +: 1]),
|
||||
.c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_wready(m_axi_ddr_wready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_bready(m_axi_ddr_bready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_bid(m_axi_ddr_bid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_arid(m_axi_ddr_arid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[0*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[0*8 +: 8]),
|
||||
.c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[0 +: 1]),
|
||||
.c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[0*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[0*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_arready(m_axi_ddr_arready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rready(m_axi_ddr_rready[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[0 +: 1]),
|
||||
.c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[0*2 +: 2]),
|
||||
.c0_ddr4_s_axi_rid(m_axi_ddr_rid[0*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[0*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH])
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign ddr4_a_adr = {17{1'bz}};
|
||||
assign ddr4_a_ba = {2{1'bz}};
|
||||
assign ddr4_a_bg = {2{1'bz}};
|
||||
assign ddr4_a_cke = 1'bz;
|
||||
assign ddr4_a_cs_n = 1'bz;
|
||||
assign ddr4_a_act_n = 1'bz;
|
||||
assign ddr4_a_odt = 1'bz;
|
||||
assign ddr4_a_reset_n = 1'b0;
|
||||
assign ddr4_a_dq = {64{1'bz}};
|
||||
assign ddr4_a_dqs_t = {8{1'bz}};
|
||||
assign ddr4_a_dqs_c = {8{1'bz}};
|
||||
assign ddr4_a_dm_dbi_n = {8{1'bz}};
|
||||
|
||||
OBUFTDS ddr4_a_ck_obuftds_inst (
|
||||
.I(1'b0),
|
||||
.T(1'b1),
|
||||
.O(ddr4_a_ck_t),
|
||||
.OB(ddr4_a_ck_c)
|
||||
);
|
||||
|
||||
assign ddr_clk = 0;
|
||||
assign ddr_rst = 0;
|
||||
|
||||
assign m_axi_ddr_awready = 0;
|
||||
assign m_axi_ddr_wready = 0;
|
||||
assign m_axi_ddr_bid = 0;
|
||||
assign m_axi_ddr_bresp = 0;
|
||||
assign m_axi_ddr_bvalid = 0;
|
||||
assign m_axi_ddr_arready = 0;
|
||||
assign m_axi_ddr_rid = 0;
|
||||
assign m_axi_ddr_rdata = 0;
|
||||
assign m_axi_ddr_rresp = 0;
|
||||
assign m_axi_ddr_rlast = 0;
|
||||
assign m_axi_ddr_rvalid = 0;
|
||||
|
||||
assign ddr_status = 0;
|
||||
|
||||
end
|
||||
|
||||
assign ddr4_a_ten = 1'b0;
|
||||
|
||||
if (DDR_ENABLE && DDR_CH > 1) begin
|
||||
|
||||
reg ddr4_rst_reg = 1'b1;
|
||||
|
||||
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
|
||||
if (pcie_user_reset) begin
|
||||
ddr4_rst_reg <= 1'b1;
|
||||
end else begin
|
||||
ddr4_rst_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
ddr4_0 ddr4_b_inst (
|
||||
.c0_sys_clk_p(clk_ddr4_b_refclk_p),
|
||||
.c0_sys_clk_n(clk_ddr4_b_refclk_n),
|
||||
.sys_rst(ddr4_rst_reg),
|
||||
|
||||
.c0_init_calib_complete(ddr_status[1 +: 1]),
|
||||
.dbg_clk(),
|
||||
.dbg_bus(),
|
||||
|
||||
.c0_ddr4_adr(ddr4_b_adr),
|
||||
.c0_ddr4_ba(ddr4_b_ba),
|
||||
.c0_ddr4_cke(ddr4_b_cke),
|
||||
.c0_ddr4_cs_n(ddr4_b_cs_n),
|
||||
.c0_ddr4_dq(ddr4_b_dq),
|
||||
.c0_ddr4_dqs_t(ddr4_b_dqs_t),
|
||||
.c0_ddr4_dqs_c(ddr4_b_dqs_c),
|
||||
.c0_ddr4_dm_dbi_n(ddr4_b_dm_dbi_n),
|
||||
.c0_ddr4_odt(ddr4_b_odt),
|
||||
.c0_ddr4_bg(ddr4_b_bg),
|
||||
.c0_ddr4_reset_n(ddr4_b_reset_n),
|
||||
.c0_ddr4_act_n(ddr4_b_act_n),
|
||||
.c0_ddr4_ck_t(ddr4_b_ck_t),
|
||||
.c0_ddr4_ck_c(ddr4_b_ck_c),
|
||||
|
||||
.c0_ddr4_ui_clk(ddr_clk[1 +: 1]),
|
||||
.c0_ddr4_ui_clk_sync_rst(ddr_rst[1 +: 1]),
|
||||
|
||||
.c0_ddr4_aresetn(!ddr_rst[1 +: 1]),
|
||||
|
||||
.c0_ddr4_s_axi_awid(m_axi_ddr_awid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[1*8 +: 8]),
|
||||
.c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[1*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[1*2 +: 2]),
|
||||
.c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[1 +: 1]),
|
||||
.c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[1*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[1*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[1*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_awready(m_axi_ddr_awready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]),
|
||||
.c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[1*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]),
|
||||
.c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[1 +: 1]),
|
||||
.c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_wready(m_axi_ddr_wready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_bready(m_axi_ddr_bready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_bid(m_axi_ddr_bid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[1*2 +: 2]),
|
||||
.c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_arid(m_axi_ddr_arid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[1*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[1*8 +: 8]),
|
||||
.c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[1*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[1*2 +: 2]),
|
||||
.c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[1 +: 1]),
|
||||
.c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[1*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[1*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[1*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_arready(m_axi_ddr_arready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_rready(m_axi_ddr_rready[1 +: 1]),
|
||||
.c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[1 +: 1]),
|
||||
.c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[1 +: 1]),
|
||||
.c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[1*2 +: 2]),
|
||||
.c0_ddr4_s_axi_rid(m_axi_ddr_rid[1*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[1*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH])
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign ddr4_b_adr = {17{1'bz}};
|
||||
assign ddr4_b_ba = {2{1'bz}};
|
||||
assign ddr4_b_bg = {2{1'bz}};
|
||||
assign ddr4_b_cke = 1'bz;
|
||||
assign ddr4_b_cs_n = 1'bz;
|
||||
assign ddr4_b_act_n = 1'bz;
|
||||
assign ddr4_b_odt = 1'bz;
|
||||
assign ddr4_b_reset_n = 1'b0;
|
||||
assign ddr4_b_dq = {64{1'bz}};
|
||||
assign ddr4_b_dqs_t = {8{1'bz}};
|
||||
assign ddr4_b_dqs_c = {8{1'bz}};
|
||||
assign ddr4_b_dm_dbi_n = {8{1'bz}};
|
||||
|
||||
OBUFTDS ddr4_b_ck_obuftds_inst (
|
||||
.I(1'b0),
|
||||
.T(1'b1),
|
||||
.O(ddr4_b_ck_t),
|
||||
.OB(ddr4_b_ck_c)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
assign ddr4_b_ten = 1'b0;
|
||||
|
||||
if (DDR_ENABLE && DDR_CH > 2) begin
|
||||
|
||||
reg ddr4_rst_reg = 1'b1;
|
||||
|
||||
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
|
||||
if (pcie_user_reset) begin
|
||||
ddr4_rst_reg <= 1'b1;
|
||||
end else begin
|
||||
ddr4_rst_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
ddr4_sodimm_0 ddr4_sodimm_a_inst (
|
||||
.c0_sys_clk_p(clk_sodimm_a_refclk_p),
|
||||
.c0_sys_clk_n(clk_sodimm_a_refclk_n),
|
||||
.sys_rst(ddr4_rst_reg),
|
||||
|
||||
.c0_init_calib_complete(ddr_status[2 +: 1]),
|
||||
.dbg_clk(),
|
||||
.dbg_bus(),
|
||||
|
||||
.c0_ddr4_adr(ddr4_sodimm_a_adr),
|
||||
.c0_ddr4_ba(ddr4_sodimm_a_ba),
|
||||
.c0_ddr4_cke(ddr4_sodimm_a_cke),
|
||||
.c0_ddr4_cs_n(ddr4_sodimm_a_cs_n),
|
||||
.c0_ddr4_dq(ddr4_sodimm_a_dq),
|
||||
.c0_ddr4_dqs_t(ddr4_sodimm_a_dqs_t),
|
||||
.c0_ddr4_dqs_c(ddr4_sodimm_a_dqs_c),
|
||||
.c0_ddr4_dm_dbi_n(ddr4_sodimm_a_dm_dbi_n),
|
||||
.c0_ddr4_odt(ddr4_sodimm_a_odt),
|
||||
.c0_ddr4_bg(ddr4_sodimm_a_bg),
|
||||
.c0_ddr4_reset_n(ddr4_sodimm_a_reset_n),
|
||||
.c0_ddr4_act_n(ddr4_sodimm_a_act_n),
|
||||
.c0_ddr4_ck_t(ddr4_sodimm_a_ck_t),
|
||||
.c0_ddr4_ck_c(ddr4_sodimm_a_ck_c),
|
||||
|
||||
.c0_ddr4_ui_clk(ddr_clk[2 +: 1]),
|
||||
.c0_ddr4_ui_clk_sync_rst(ddr_rst[2 +: 1]),
|
||||
|
||||
.c0_ddr4_aresetn(!ddr_rst[2 +: 1]),
|
||||
|
||||
.c0_ddr4_s_axi_awid(m_axi_ddr_awid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[2*8 +: 8]),
|
||||
.c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[2*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[2*2 +: 2]),
|
||||
.c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[2 +: 1]),
|
||||
.c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[2*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[2*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[2*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[2 +: 1]),
|
||||
.c0_ddr4_s_axi_awready(m_axi_ddr_awready[2 +: 1]),
|
||||
.c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]),
|
||||
.c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[2*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]),
|
||||
.c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[2 +: 1]),
|
||||
.c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[2 +: 1]),
|
||||
.c0_ddr4_s_axi_wready(m_axi_ddr_wready[2 +: 1]),
|
||||
.c0_ddr4_s_axi_bready(m_axi_ddr_bready[2 +: 1]),
|
||||
.c0_ddr4_s_axi_bid(m_axi_ddr_bid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[2*2 +: 2]),
|
||||
.c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[2 +: 1]),
|
||||
.c0_ddr4_s_axi_arid(m_axi_ddr_arid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[2*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[2*8 +: 8]),
|
||||
.c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[2*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[2*2 +: 2]),
|
||||
.c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[2 +: 1]),
|
||||
.c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[2*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[2*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[2*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[2 +: 1]),
|
||||
.c0_ddr4_s_axi_arready(m_axi_ddr_arready[2 +: 1]),
|
||||
.c0_ddr4_s_axi_rready(m_axi_ddr_rready[2 +: 1]),
|
||||
.c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[2 +: 1]),
|
||||
.c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[2 +: 1]),
|
||||
.c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[2*2 +: 2]),
|
||||
.c0_ddr4_s_axi_rid(m_axi_ddr_rid[2*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[2*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH])
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign ddr4_sodimm_a_adr = {17{1'bz}};
|
||||
assign ddr4_sodimm_a_ba = {2{1'bz}};
|
||||
assign ddr4_sodimm_a_bg = {2{1'bz}};
|
||||
assign ddr4_sodimm_a_cke = 1'bz;
|
||||
assign ddr4_sodimm_a_cs_n = 1'bz;
|
||||
assign ddr4_sodimm_a_act_n = 1'bz;
|
||||
assign ddr4_sodimm_a_odt = 1'bz;
|
||||
assign ddr4_sodimm_a_reset_n = 1'b0;
|
||||
assign ddr4_sodimm_a_dq = {64{1'bz}};
|
||||
assign ddr4_sodimm_a_dqs_t = {8{1'bz}};
|
||||
assign ddr4_sodimm_a_dqs_c = {8{1'bz}};
|
||||
assign ddr4_sodimm_a_dm_dbi_n = {8{1'bz}};
|
||||
|
||||
OBUFTDS ddr4_sodimm_a_ck_obuftds_inst (
|
||||
.I(1'b0),
|
||||
.T(1'b1),
|
||||
.O(ddr4_sodimm_a_ck_t),
|
||||
.OB(ddr4_sodimm_a_ck_c)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
if (DDR_ENABLE && DDR_CH > 3) begin
|
||||
|
||||
reg ddr4_rst_reg = 1'b1;
|
||||
|
||||
always @(posedge pcie_user_clk or posedge pcie_user_reset) begin
|
||||
if (pcie_user_reset) begin
|
||||
ddr4_rst_reg <= 1'b1;
|
||||
end else begin
|
||||
ddr4_rst_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
ddr4_sodimm_0 ddr4_sodimm_b_inst (
|
||||
.c0_sys_clk_p(clk_sodimm_b_refclk_p),
|
||||
.c0_sys_clk_n(clk_sodimm_b_refclk_n),
|
||||
.sys_rst(ddr4_rst_reg),
|
||||
|
||||
.c0_init_calib_complete(ddr_status[3 +: 1]),
|
||||
.dbg_clk(),
|
||||
.dbg_bus(),
|
||||
|
||||
.c0_ddr4_adr(ddr4_sodimm_b_adr),
|
||||
.c0_ddr4_ba(ddr4_sodimm_b_ba),
|
||||
.c0_ddr4_cke(ddr4_sodimm_b_cke),
|
||||
.c0_ddr4_cs_n(ddr4_sodimm_b_cs_n),
|
||||
.c0_ddr4_dq(ddr4_sodimm_b_dq),
|
||||
.c0_ddr4_dqs_t(ddr4_sodimm_b_dqs_t),
|
||||
.c0_ddr4_dqs_c(ddr4_sodimm_b_dqs_c),
|
||||
.c0_ddr4_dm_dbi_n(ddr4_sodimm_b_dm_dbi_n),
|
||||
.c0_ddr4_odt(ddr4_sodimm_b_odt),
|
||||
.c0_ddr4_bg(ddr4_sodimm_b_bg),
|
||||
.c0_ddr4_reset_n(ddr4_sodimm_b_reset_n),
|
||||
.c0_ddr4_act_n(ddr4_sodimm_b_act_n),
|
||||
.c0_ddr4_ck_t(ddr4_sodimm_b_ck_t),
|
||||
.c0_ddr4_ck_c(ddr4_sodimm_b_ck_c),
|
||||
|
||||
.c0_ddr4_ui_clk(ddr_clk[3 +: 1]),
|
||||
.c0_ddr4_ui_clk_sync_rst(ddr_rst[3 +: 1]),
|
||||
|
||||
.c0_ddr4_aresetn(!ddr_rst[3 +: 1]),
|
||||
|
||||
.c0_ddr4_s_axi_awid(m_axi_ddr_awid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_awaddr(m_axi_ddr_awaddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_awlen(m_axi_ddr_awlen[3*8 +: 8]),
|
||||
.c0_ddr4_s_axi_awsize(m_axi_ddr_awsize[3*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awburst(m_axi_ddr_awburst[3*2 +: 2]),
|
||||
.c0_ddr4_s_axi_awlock(m_axi_ddr_awlock[3 +: 1]),
|
||||
.c0_ddr4_s_axi_awcache(m_axi_ddr_awcache[3*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awprot(m_axi_ddr_awprot[3*3 +: 3]),
|
||||
.c0_ddr4_s_axi_awqos(m_axi_ddr_awqos[3*4 +: 4]),
|
||||
.c0_ddr4_s_axi_awvalid(m_axi_ddr_awvalid[3 +: 1]),
|
||||
.c0_ddr4_s_axi_awready(m_axi_ddr_awready[3 +: 1]),
|
||||
.c0_ddr4_s_axi_wdata(m_axi_ddr_wdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH]),
|
||||
.c0_ddr4_s_axi_wstrb(m_axi_ddr_wstrb[3*AXI_DDR_STRB_WIDTH +: AXI_DDR_STRB_WIDTH]),
|
||||
.c0_ddr4_s_axi_wlast(m_axi_ddr_wlast[3 +: 1]),
|
||||
.c0_ddr4_s_axi_wvalid(m_axi_ddr_wvalid[3 +: 1]),
|
||||
.c0_ddr4_s_axi_wready(m_axi_ddr_wready[3 +: 1]),
|
||||
.c0_ddr4_s_axi_bready(m_axi_ddr_bready[3 +: 1]),
|
||||
.c0_ddr4_s_axi_bid(m_axi_ddr_bid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_bresp(m_axi_ddr_bresp[3*2 +: 2]),
|
||||
.c0_ddr4_s_axi_bvalid(m_axi_ddr_bvalid[3 +: 1]),
|
||||
.c0_ddr4_s_axi_arid(m_axi_ddr_arid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_araddr(m_axi_ddr_araddr[3*AXI_DDR_ADDR_WIDTH +: AXI_DDR_ADDR_WIDTH]),
|
||||
.c0_ddr4_s_axi_arlen(m_axi_ddr_arlen[3*8 +: 8]),
|
||||
.c0_ddr4_s_axi_arsize(m_axi_ddr_arsize[3*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arburst(m_axi_ddr_arburst[3*2 +: 2]),
|
||||
.c0_ddr4_s_axi_arlock(m_axi_ddr_arlock[3 +: 1]),
|
||||
.c0_ddr4_s_axi_arcache(m_axi_ddr_arcache[3*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arprot(m_axi_ddr_arprot[3*3 +: 3]),
|
||||
.c0_ddr4_s_axi_arqos(m_axi_ddr_arqos[3*4 +: 4]),
|
||||
.c0_ddr4_s_axi_arvalid(m_axi_ddr_arvalid[3 +: 1]),
|
||||
.c0_ddr4_s_axi_arready(m_axi_ddr_arready[3 +: 1]),
|
||||
.c0_ddr4_s_axi_rready(m_axi_ddr_rready[3 +: 1]),
|
||||
.c0_ddr4_s_axi_rlast(m_axi_ddr_rlast[3 +: 1]),
|
||||
.c0_ddr4_s_axi_rvalid(m_axi_ddr_rvalid[3 +: 1]),
|
||||
.c0_ddr4_s_axi_rresp(m_axi_ddr_rresp[3*2 +: 2]),
|
||||
.c0_ddr4_s_axi_rid(m_axi_ddr_rid[3*AXI_DDR_ID_WIDTH +: AXI_DDR_ID_WIDTH]),
|
||||
.c0_ddr4_s_axi_rdata(m_axi_ddr_rdata[3*AXI_DDR_DATA_WIDTH +: AXI_DDR_DATA_WIDTH])
|
||||
);
|
||||
|
||||
end else begin
|
||||
|
||||
assign ddr4_sodimm_b_adr = {17{1'bz}};
|
||||
assign ddr4_sodimm_b_ba = {2{1'bz}};
|
||||
assign ddr4_sodimm_b_bg = {2{1'bz}};
|
||||
assign ddr4_sodimm_b_cke = 1'bz;
|
||||
assign ddr4_sodimm_b_cs_n = 1'bz;
|
||||
assign ddr4_sodimm_b_act_n = 1'bz;
|
||||
assign ddr4_sodimm_b_odt = 1'bz;
|
||||
assign ddr4_sodimm_b_reset_n = 1'b0;
|
||||
assign ddr4_sodimm_b_dq = {64{1'bz}};
|
||||
assign ddr4_sodimm_b_dqs_t = {8{1'bz}};
|
||||
assign ddr4_sodimm_b_dqs_c = {8{1'bz}};
|
||||
assign ddr4_sodimm_b_dm_dbi_n = {8{1'bz}};
|
||||
|
||||
OBUFTDS ddr4_sodimm_b_ck_obuftds_inst (
|
||||
.I(1'b0),
|
||||
.T(1'b1),
|
||||
.O(ddr4_sodimm_b_ck_t),
|
||||
.OB(ddr4_sodimm_b_ck_c)
|
||||
);
|
||||
|
||||
end
|
||||
|
||||
endgenerate
|
||||
|
||||
fpga_core #(
|
||||
// FW and board IDs
|
||||
.FPGA_ID(FPGA_ID),
|
||||
@ -1751,6 +2448,16 @@ fpga_core #(
|
||||
.TX_RAM_SIZE(TX_RAM_SIZE),
|
||||
.RX_RAM_SIZE(RX_RAM_SIZE),
|
||||
|
||||
// RAM configuration
|
||||
.DDR_CH(DDR_CH),
|
||||
.DDR_ENABLE(DDR_ENABLE),
|
||||
.AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH),
|
||||
.AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH),
|
||||
.AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH),
|
||||
.AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH),
|
||||
.AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN),
|
||||
.AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST),
|
||||
|
||||
// Application block configuration
|
||||
.APP_ID(APP_ID),
|
||||
.APP_ENABLE(APP_ENABLE),
|
||||
@ -1843,6 +2550,14 @@ core_inst (
|
||||
.pps_in(pps_in),
|
||||
.pps_out(pps_out),
|
||||
|
||||
/*
|
||||
* BMC interface
|
||||
*/
|
||||
.bmc_clk(bmc_clk),
|
||||
.bmc_nss(bmc_nss),
|
||||
.bmc_mosi(bmc_mosi),
|
||||
.bmc_miso(bmc_miso),
|
||||
|
||||
/*
|
||||
* PCIe
|
||||
*/
|
||||
@ -2212,7 +2927,58 @@ core_inst (
|
||||
.qsfp_3_i2c_scl_t(qsfp_3_i2c_scl_t),
|
||||
.qsfp_3_i2c_sda_i(qsfp_3_i2c_sda_i),
|
||||
.qsfp_3_i2c_sda_o(qsfp_3_i2c_sda_o),
|
||||
.qsfp_3_i2c_sda_t(qsfp_3_i2c_sda_t)
|
||||
.qsfp_3_i2c_sda_t(qsfp_3_i2c_sda_t),
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
.ddr_clk(ddr_clk),
|
||||
.ddr_rst(ddr_rst),
|
||||
|
||||
.m_axi_ddr_awid(m_axi_ddr_awid),
|
||||
.m_axi_ddr_awaddr(m_axi_ddr_awaddr),
|
||||
.m_axi_ddr_awlen(m_axi_ddr_awlen),
|
||||
.m_axi_ddr_awsize(m_axi_ddr_awsize),
|
||||
.m_axi_ddr_awburst(m_axi_ddr_awburst),
|
||||
.m_axi_ddr_awlock(m_axi_ddr_awlock),
|
||||
.m_axi_ddr_awcache(m_axi_ddr_awcache),
|
||||
.m_axi_ddr_awprot(m_axi_ddr_awprot),
|
||||
.m_axi_ddr_awqos(m_axi_ddr_awqos),
|
||||
.m_axi_ddr_awvalid(m_axi_ddr_awvalid),
|
||||
.m_axi_ddr_awready(m_axi_ddr_awready),
|
||||
.m_axi_ddr_wdata(m_axi_ddr_wdata),
|
||||
.m_axi_ddr_wstrb(m_axi_ddr_wstrb),
|
||||
.m_axi_ddr_wlast(m_axi_ddr_wlast),
|
||||
.m_axi_ddr_wvalid(m_axi_ddr_wvalid),
|
||||
.m_axi_ddr_wready(m_axi_ddr_wready),
|
||||
.m_axi_ddr_bid(m_axi_ddr_bid),
|
||||
.m_axi_ddr_bresp(m_axi_ddr_bresp),
|
||||
.m_axi_ddr_bvalid(m_axi_ddr_bvalid),
|
||||
.m_axi_ddr_bready(m_axi_ddr_bready),
|
||||
.m_axi_ddr_arid(m_axi_ddr_arid),
|
||||
.m_axi_ddr_araddr(m_axi_ddr_araddr),
|
||||
.m_axi_ddr_arlen(m_axi_ddr_arlen),
|
||||
.m_axi_ddr_arsize(m_axi_ddr_arsize),
|
||||
.m_axi_ddr_arburst(m_axi_ddr_arburst),
|
||||
.m_axi_ddr_arlock(m_axi_ddr_arlock),
|
||||
.m_axi_ddr_arcache(m_axi_ddr_arcache),
|
||||
.m_axi_ddr_arprot(m_axi_ddr_arprot),
|
||||
.m_axi_ddr_arqos(m_axi_ddr_arqos),
|
||||
.m_axi_ddr_arvalid(m_axi_ddr_arvalid),
|
||||
.m_axi_ddr_arready(m_axi_ddr_arready),
|
||||
.m_axi_ddr_rid(m_axi_ddr_rid),
|
||||
.m_axi_ddr_rdata(m_axi_ddr_rdata),
|
||||
.m_axi_ddr_rresp(m_axi_ddr_rresp),
|
||||
.m_axi_ddr_rlast(m_axi_ddr_rlast),
|
||||
.m_axi_ddr_rvalid(m_axi_ddr_rvalid),
|
||||
.m_axi_ddr_rready(m_axi_ddr_rready),
|
||||
|
||||
.ddr_status(ddr_status),
|
||||
|
||||
/*
|
||||
* Reboot trigger
|
||||
*/
|
||||
.fpga_boot(fpga_boot)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
@ -91,6 +91,16 @@ module fpga_core #
|
||||
parameter TX_RAM_SIZE = 32768,
|
||||
parameter RX_RAM_SIZE = 32768,
|
||||
|
||||
// RAM configuration
|
||||
parameter DDR_CH = 4,
|
||||
parameter DDR_ENABLE = 0,
|
||||
parameter AXI_DDR_DATA_WIDTH = 512,
|
||||
parameter AXI_DDR_ADDR_WIDTH = 32,
|
||||
parameter AXI_DDR_STRB_WIDTH = (AXI_DDR_DATA_WIDTH/8),
|
||||
parameter AXI_DDR_ID_WIDTH = 8,
|
||||
parameter AXI_DDR_MAX_BURST_LEN = 256,
|
||||
parameter AXI_DDR_NARROW_BURST = 0,
|
||||
|
||||
// Application block configuration
|
||||
parameter APP_ID = 32'h00000000,
|
||||
parameter APP_ENABLE = 0,
|
||||
@ -183,6 +193,14 @@ module fpga_core #
|
||||
input wire pps_in,
|
||||
output wire pps_out,
|
||||
|
||||
/*
|
||||
* BMC interface
|
||||
*/
|
||||
output wire bmc_clk,
|
||||
output wire bmc_nss,
|
||||
output wire bmc_mosi,
|
||||
input wire bmc_miso,
|
||||
|
||||
/*
|
||||
* PCIe
|
||||
*/
|
||||
@ -552,7 +570,58 @@ module fpga_core #
|
||||
output wire qsfp_3_i2c_scl_t,
|
||||
input wire qsfp_3_i2c_sda_i,
|
||||
output wire qsfp_3_i2c_sda_o,
|
||||
output wire qsfp_3_i2c_sda_t
|
||||
output wire qsfp_3_i2c_sda_t,
|
||||
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
input wire [DDR_CH-1:0] ddr_clk,
|
||||
input wire [DDR_CH-1:0] ddr_rst,
|
||||
|
||||
output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_awid,
|
||||
output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_awaddr,
|
||||
output wire [DDR_CH*8-1:0] m_axi_ddr_awlen,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_awsize,
|
||||
output wire [DDR_CH*2-1:0] m_axi_ddr_awburst,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_awlock,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_awcache,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_awprot,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_awqos,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_awvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_awready,
|
||||
output wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_wdata,
|
||||
output wire [DDR_CH*AXI_DDR_STRB_WIDTH-1:0] m_axi_ddr_wstrb,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_wlast,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_wvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_wready,
|
||||
input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_bid,
|
||||
input wire [DDR_CH*2-1:0] m_axi_ddr_bresp,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_bvalid,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_bready,
|
||||
output wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_arid,
|
||||
output wire [DDR_CH*AXI_DDR_ADDR_WIDTH-1:0] m_axi_ddr_araddr,
|
||||
output wire [DDR_CH*8-1:0] m_axi_ddr_arlen,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_arsize,
|
||||
output wire [DDR_CH*2-1:0] m_axi_ddr_arburst,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_arlock,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_arcache,
|
||||
output wire [DDR_CH*3-1:0] m_axi_ddr_arprot,
|
||||
output wire [DDR_CH*4-1:0] m_axi_ddr_arqos,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_arvalid,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_arready,
|
||||
input wire [DDR_CH*AXI_DDR_ID_WIDTH-1:0] m_axi_ddr_rid,
|
||||
input wire [DDR_CH*AXI_DDR_DATA_WIDTH-1:0] m_axi_ddr_rdata,
|
||||
input wire [DDR_CH*2-1:0] m_axi_ddr_rresp,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_rlast,
|
||||
input wire [DDR_CH-1:0] m_axi_ddr_rvalid,
|
||||
output wire [DDR_CH-1:0] m_axi_ddr_rready,
|
||||
|
||||
input wire [DDR_CH-1:0] ddr_status,
|
||||
|
||||
/*
|
||||
* Reboot trigger
|
||||
*/
|
||||
output wire fpga_boot
|
||||
);
|
||||
|
||||
parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF;
|
||||
@ -566,7 +635,7 @@ parameter AXIL_CSR_ADDR_WIDTH = AXIL_IF_CTRL_ADDR_WIDTH-5-$clog2((PORTS_PER_IF+3
|
||||
localparam RB_BASE_ADDR = 16'h1000;
|
||||
localparam RBB = RB_BASE_ADDR & {AXIL_CTRL_ADDR_WIDTH{1'b1}};
|
||||
|
||||
localparam RB_DRP_QSFP_0_BASE = RB_BASE_ADDR + 16'h50;
|
||||
localparam RB_DRP_QSFP_0_BASE = RB_BASE_ADDR + 16'h70;
|
||||
localparam RB_DRP_QSFP_1_BASE = RB_DRP_QSFP_0_BASE + 16'h20;
|
||||
localparam RB_DRP_QSFP_2_BASE = RB_DRP_QSFP_1_BASE + 16'h20;
|
||||
localparam RB_DRP_QSFP_3_BASE = RB_DRP_QSFP_2_BASE + 16'h20;
|
||||
@ -673,6 +742,17 @@ reg qsfp_3_lp_mode_reg = 1'b0;
|
||||
reg qsfp_3_i2c_scl_o_reg = 1'b1;
|
||||
reg qsfp_3_i2c_sda_o_reg = 1'b1;
|
||||
|
||||
reg fpga_boot_reg = 1'b0;
|
||||
|
||||
reg [15:0] bmc_ctrl_cmd_reg = 16'd0;
|
||||
reg [31:0] bmc_ctrl_data_reg = 32'd0;
|
||||
reg bmc_ctrl_valid_reg = 1'b0;
|
||||
|
||||
wire [15:0] bmc_read_data;
|
||||
wire bmc_status_idle;
|
||||
wire bmc_status_done;
|
||||
wire bmc_status_timeout;
|
||||
|
||||
assign ctrl_reg_wr_wait = qsfp_0_drp_reg_wr_wait | qsfp_1_drp_reg_wr_wait | qsfp_2_drp_reg_wr_wait | qsfp_3_drp_reg_wr_wait;
|
||||
assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg | qsfp_0_drp_reg_wr_ack | qsfp_1_drp_reg_wr_ack | qsfp_2_drp_reg_wr_ack | qsfp_3_drp_reg_wr_ack;
|
||||
assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg | qsfp_0_drp_reg_rd_data | qsfp_1_drp_reg_rd_data | qsfp_2_drp_reg_rd_data | qsfp_3_drp_reg_rd_data;
|
||||
@ -707,15 +787,24 @@ assign qsfp_3_i2c_scl_t = qsfp_3_i2c_scl_o_reg;
|
||||
assign qsfp_3_i2c_sda_o = qsfp_3_i2c_sda_o_reg;
|
||||
assign qsfp_3_i2c_sda_t = qsfp_3_i2c_sda_o_reg;
|
||||
|
||||
assign fpga_boot = fpga_boot_reg;
|
||||
|
||||
always @(posedge clk_250mhz) begin
|
||||
ctrl_reg_wr_ack_reg <= 1'b0;
|
||||
ctrl_reg_rd_data_reg <= {AXIL_CTRL_DATA_WIDTH{1'b0}};
|
||||
ctrl_reg_rd_ack_reg <= 1'b0;
|
||||
|
||||
bmc_ctrl_valid_reg <= 1'b0;
|
||||
|
||||
if (ctrl_reg_wr_en && !ctrl_reg_wr_ack_reg) begin
|
||||
// write operation
|
||||
ctrl_reg_wr_ack_reg <= 1'b0;
|
||||
case ({ctrl_reg_wr_addr >> 2, 2'b00})
|
||||
// FW ID
|
||||
8'h0C: begin
|
||||
// FW ID: FPGA JTAG ID
|
||||
fpga_boot_reg <= ctrl_reg_wr_data == 32'hFEE1DEAD;
|
||||
end
|
||||
// I2C 0
|
||||
RBB+8'h0C: begin
|
||||
// I2C ctrl: control
|
||||
@ -776,6 +865,13 @@ always @(posedge clk_250mhz) begin
|
||||
qsfp_3_lp_mode_reg <= ctrl_reg_wr_data[29];
|
||||
end
|
||||
end
|
||||
// SF2 BMC
|
||||
RBB+8'h60: bmc_ctrl_data_reg <= ctrl_reg_wr_data; // BMC ctrl: data
|
||||
RBB+8'h64: begin
|
||||
// BMC ctrl: cmd
|
||||
bmc_ctrl_cmd_reg <= ctrl_reg_wr_data[31:16];
|
||||
bmc_ctrl_valid_reg <= 1'b1;
|
||||
end
|
||||
default: ctrl_reg_wr_ack_reg <= 1'b0;
|
||||
endcase
|
||||
end
|
||||
@ -831,7 +927,7 @@ always @(posedge clk_250mhz) begin
|
||||
// XCVR GPIO
|
||||
RBB+8'h40: ctrl_reg_rd_data_reg <= 32'h0000C101; // XCVR GPIO: Type
|
||||
RBB+8'h44: ctrl_reg_rd_data_reg <= 32'h00000100; // XCVR GPIO: Version
|
||||
RBB+8'h48: ctrl_reg_rd_data_reg <= RB_DRP_QSFP_0_BASE; // XCVR GPIO: Next header
|
||||
RBB+8'h48: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h50; // XCVR GPIO: Next header
|
||||
RBB+8'h4C: begin
|
||||
// XCVR GPIO: control 0123
|
||||
ctrl_reg_rd_data_reg[0] <= !qsfp_0_mod_prsnt_n;
|
||||
@ -851,6 +947,17 @@ always @(posedge clk_250mhz) begin
|
||||
ctrl_reg_rd_data_reg[28] <= qsfp_3_reset_reg;
|
||||
ctrl_reg_rd_data_reg[29] <= qsfp_3_lp_mode_reg;
|
||||
end
|
||||
// SF2 BMC
|
||||
RBB+8'h50: ctrl_reg_rd_data_reg <= 32'h0000C141; // BMC ctrl: Type
|
||||
RBB+8'h54: ctrl_reg_rd_data_reg <= 32'h00000100; // BMC ctrl: Version
|
||||
RBB+8'h58: ctrl_reg_rd_data_reg <= RB_DRP_QSFP_0_BASE; // BMC ctrl: Next header
|
||||
RBB+8'h5C: begin
|
||||
// BMC ctrl: status
|
||||
ctrl_reg_rd_data_reg[15:0] <= bmc_read_data;
|
||||
ctrl_reg_rd_data_reg[16] <= bmc_status_done;
|
||||
ctrl_reg_rd_data_reg[18] <= bmc_status_timeout;
|
||||
ctrl_reg_rd_data_reg[19] <= bmc_status_idle;
|
||||
end
|
||||
default: ctrl_reg_rd_ack_reg <= 1'b0;
|
||||
endcase
|
||||
end
|
||||
@ -878,9 +985,37 @@ always @(posedge clk_250mhz) begin
|
||||
qsfp_3_lp_mode_reg <= 1'b0;
|
||||
qsfp_3_i2c_scl_o_reg <= 1'b1;
|
||||
qsfp_3_i2c_sda_o_reg <= 1'b1;
|
||||
|
||||
fpga_boot_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
bmc_spi #(
|
||||
.PRESCALE(125),
|
||||
.BYTE_WAIT(32),
|
||||
.TIMEOUT(5000)
|
||||
)
|
||||
bmc_spi_inst (
|
||||
.clk(clk_250mhz),
|
||||
.rst(rst_250mhz),
|
||||
|
||||
.ctrl_cmd(bmc_ctrl_cmd_reg),
|
||||
.ctrl_data(bmc_ctrl_data_reg),
|
||||
.ctrl_valid(bmc_ctrl_valid_reg),
|
||||
|
||||
.read_data(bmc_read_data),
|
||||
|
||||
.status_idle(bmc_status_idle),
|
||||
.status_done(bmc_status_done),
|
||||
.status_timeout(bmc_status_timeout),
|
||||
|
||||
.bmc_clk(bmc_clk),
|
||||
.bmc_nss(bmc_nss),
|
||||
.bmc_mosi(bmc_mosi),
|
||||
.bmc_miso(bmc_miso),
|
||||
.bmc_int(1'b0)
|
||||
);
|
||||
|
||||
rb_drp #(
|
||||
.DRP_ADDR_WIDTH(24),
|
||||
.DRP_DATA_WIDTH(16),
|
||||
@ -1378,7 +1513,22 @@ mqnic_core_pcie_us #(
|
||||
.RX_RAM_SIZE(RX_RAM_SIZE),
|
||||
|
||||
// RAM configuration
|
||||
.DDR_ENABLE(0),
|
||||
.DDR_CH(DDR_CH),
|
||||
.DDR_ENABLE(DDR_ENABLE),
|
||||
.DDR_GROUP_SIZE(1),
|
||||
.AXI_DDR_DATA_WIDTH(AXI_DDR_DATA_WIDTH),
|
||||
.AXI_DDR_ADDR_WIDTH(AXI_DDR_ADDR_WIDTH),
|
||||
.AXI_DDR_STRB_WIDTH(AXI_DDR_STRB_WIDTH),
|
||||
.AXI_DDR_ID_WIDTH(AXI_DDR_ID_WIDTH),
|
||||
.AXI_DDR_AWUSER_ENABLE(0),
|
||||
.AXI_DDR_WUSER_ENABLE(0),
|
||||
.AXI_DDR_BUSER_ENABLE(0),
|
||||
.AXI_DDR_ARUSER_ENABLE(0),
|
||||
.AXI_DDR_RUSER_ENABLE(0),
|
||||
.AXI_DDR_MAX_BURST_LEN(AXI_DDR_MAX_BURST_LEN),
|
||||
.AXI_DDR_NARROW_BURST(AXI_DDR_NARROW_BURST),
|
||||
.AXI_DDR_FIXED_BURST(0),
|
||||
.AXI_DDR_WRAP_BURST(1),
|
||||
.HBM_ENABLE(0),
|
||||
|
||||
// Application block configuration
|
||||
@ -1658,53 +1808,53 @@ core_inst (
|
||||
/*
|
||||
* DDR
|
||||
*/
|
||||
.ddr_clk(0),
|
||||
.ddr_rst(0),
|
||||
.ddr_clk(ddr_clk),
|
||||
.ddr_rst(ddr_rst),
|
||||
|
||||
.m_axi_ddr_awid(),
|
||||
.m_axi_ddr_awaddr(),
|
||||
.m_axi_ddr_awlen(),
|
||||
.m_axi_ddr_awsize(),
|
||||
.m_axi_ddr_awburst(),
|
||||
.m_axi_ddr_awlock(),
|
||||
.m_axi_ddr_awcache(),
|
||||
.m_axi_ddr_awprot(),
|
||||
.m_axi_ddr_awqos(),
|
||||
.m_axi_ddr_awid(m_axi_ddr_awid),
|
||||
.m_axi_ddr_awaddr(m_axi_ddr_awaddr),
|
||||
.m_axi_ddr_awlen(m_axi_ddr_awlen),
|
||||
.m_axi_ddr_awsize(m_axi_ddr_awsize),
|
||||
.m_axi_ddr_awburst(m_axi_ddr_awburst),
|
||||
.m_axi_ddr_awlock(m_axi_ddr_awlock),
|
||||
.m_axi_ddr_awcache(m_axi_ddr_awcache),
|
||||
.m_axi_ddr_awprot(m_axi_ddr_awprot),
|
||||
.m_axi_ddr_awqos(m_axi_ddr_awqos),
|
||||
.m_axi_ddr_awuser(),
|
||||
.m_axi_ddr_awvalid(),
|
||||
.m_axi_ddr_awready(0),
|
||||
.m_axi_ddr_wdata(),
|
||||
.m_axi_ddr_wstrb(),
|
||||
.m_axi_ddr_wlast(),
|
||||
.m_axi_ddr_awvalid(m_axi_ddr_awvalid),
|
||||
.m_axi_ddr_awready(m_axi_ddr_awready),
|
||||
.m_axi_ddr_wdata(m_axi_ddr_wdata),
|
||||
.m_axi_ddr_wstrb(m_axi_ddr_wstrb),
|
||||
.m_axi_ddr_wlast(m_axi_ddr_wlast),
|
||||
.m_axi_ddr_wuser(),
|
||||
.m_axi_ddr_wvalid(),
|
||||
.m_axi_ddr_wready(0),
|
||||
.m_axi_ddr_bid(0),
|
||||
.m_axi_ddr_bresp(0),
|
||||
.m_axi_ddr_wvalid(m_axi_ddr_wvalid),
|
||||
.m_axi_ddr_wready(m_axi_ddr_wready),
|
||||
.m_axi_ddr_bid(m_axi_ddr_bid),
|
||||
.m_axi_ddr_bresp(m_axi_ddr_bresp),
|
||||
.m_axi_ddr_buser(0),
|
||||
.m_axi_ddr_bvalid(0),
|
||||
.m_axi_ddr_bready(),
|
||||
.m_axi_ddr_arid(),
|
||||
.m_axi_ddr_araddr(),
|
||||
.m_axi_ddr_arlen(),
|
||||
.m_axi_ddr_arsize(),
|
||||
.m_axi_ddr_arburst(),
|
||||
.m_axi_ddr_arlock(),
|
||||
.m_axi_ddr_arcache(),
|
||||
.m_axi_ddr_arprot(),
|
||||
.m_axi_ddr_arqos(),
|
||||
.m_axi_ddr_bvalid(m_axi_ddr_bvalid),
|
||||
.m_axi_ddr_bready(m_axi_ddr_bready),
|
||||
.m_axi_ddr_arid(m_axi_ddr_arid),
|
||||
.m_axi_ddr_araddr(m_axi_ddr_araddr),
|
||||
.m_axi_ddr_arlen(m_axi_ddr_arlen),
|
||||
.m_axi_ddr_arsize(m_axi_ddr_arsize),
|
||||
.m_axi_ddr_arburst(m_axi_ddr_arburst),
|
||||
.m_axi_ddr_arlock(m_axi_ddr_arlock),
|
||||
.m_axi_ddr_arcache(m_axi_ddr_arcache),
|
||||
.m_axi_ddr_arprot(m_axi_ddr_arprot),
|
||||
.m_axi_ddr_arqos(m_axi_ddr_arqos),
|
||||
.m_axi_ddr_aruser(),
|
||||
.m_axi_ddr_arvalid(),
|
||||
.m_axi_ddr_arready(0),
|
||||
.m_axi_ddr_rid(0),
|
||||
.m_axi_ddr_rdata(0),
|
||||
.m_axi_ddr_rresp(0),
|
||||
.m_axi_ddr_rlast(0),
|
||||
.m_axi_ddr_arvalid(m_axi_ddr_arvalid),
|
||||
.m_axi_ddr_arready(m_axi_ddr_arready),
|
||||
.m_axi_ddr_rid(m_axi_ddr_rid),
|
||||
.m_axi_ddr_rdata(m_axi_ddr_rdata),
|
||||
.m_axi_ddr_rresp(m_axi_ddr_rresp),
|
||||
.m_axi_ddr_rlast(m_axi_ddr_rlast),
|
||||
.m_axi_ddr_ruser(0),
|
||||
.m_axi_ddr_rvalid(0),
|
||||
.m_axi_ddr_rready(),
|
||||
.m_axi_ddr_rvalid(m_axi_ddr_rvalid),
|
||||
.m_axi_ddr_rready(m_axi_ddr_rready),
|
||||
|
||||
.ddr_status(0),
|
||||
.ddr_status(ddr_status),
|
||||
|
||||
/*
|
||||
* HBM
|
||||
|
||||
@ -13,6 +13,7 @@ DUT = fpga_core
|
||||
TOPLEVEL = $(DUT)
|
||||
MODULE = test_$(DUT)
|
||||
VERILOG_SOURCES += ../../rtl/$(DUT).v
|
||||
VERILOG_SOURCES += ../../rtl/bmc_spi.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie_us.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_core_pcie.v
|
||||
VERILOG_SOURCES += ../../rtl/common/mqnic_core.v
|
||||
|
||||
@ -306,6 +306,8 @@ class TB(object):
|
||||
|
||||
dut.pps_in.setimmediatevalue(0)
|
||||
|
||||
dut.bmc_miso.setimmediatevalue(0)
|
||||
|
||||
self.loopback_enable = False
|
||||
cocotb.start_soon(self._run_loopback())
|
||||
|
||||
@ -546,6 +548,7 @@ def test_fpga_core(request):
|
||||
|
||||
verilog_sources = [
|
||||
os.path.join(rtl_dir, f"{dut}.v"),
|
||||
os.path.join(rtl_dir, "bmc_spi.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_core_pcie_us.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_core_pcie.v"),
|
||||
os.path.join(rtl_dir, "common", "mqnic_core.v"),
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user