diff --git a/fpga/mqnic/VCU108/fpga_25g/fpga.xdc b/fpga/mqnic/VCU108/fpga_25g/fpga.xdc index 573376c51..cb03c292a 100644 --- a/fpga/mqnic/VCU108/fpga_25g/fpga.xdc +++ b/fpga/mqnic/VCU108/fpga_25g/fpga.xdc @@ -16,8 +16,8 @@ set_property -dict {LOC F31 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_1_n] create_clock -period 3.333 -name clk_300mhz_1 [get_ports clk_300mhz_1_p] # DDR ref clock sharing -set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {name =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1 && name =~*ddr4_c1_inst*}] -set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {name =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1 && name =~*ddr4_c2_inst*}] +set_property -quiet CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -quiet -hier -filter {name =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1 && name =~*ddr4_c1_inst*}] +set_property -quiet CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -quiet -hier -filter {name =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1 && name =~*ddr4_c2_inst*}] #set_property -dict {LOC G22 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_2_p] #set_property -dict {LOC G21 IOSTANDARD DIFF_SSTL12} [get_ports clk_300mhz_2_n] diff --git a/fpga/mqnic/fb2CG/fpga_100g/fpga.xdc b/fpga/mqnic/fb2CG/fpga_100g/fpga.xdc index 429977e4a..c042a311e 100644 --- a/fpga/mqnic/fb2CG/fpga_100g/fpga.xdc +++ b/fpga/mqnic/fb2CG/fpga_100g/fpga.xdc @@ -28,8 +28,8 @@ set_property -dict {LOC AU32 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk1 create_clock -period 3.750 -name clk_ddr4_refclk1 [get_ports clk_ddr4_refclk1_p] # DDR ref clock sharing -set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {name =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1 && name =~*ddr4_c0_inst*}] -set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {name =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1 && name =~*ddr4_c1_inst*}] +set_property -quiet CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -quiet -hier -filter {name =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1 && name =~*ddr4_c0_inst*}] +set_property -quiet CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -quiet -hier -filter {name =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1 && name =~*ddr4_c1_inst*}] # DDR4 refclk2 set_property -dict {LOC G28 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk2_p] @@ -37,8 +37,8 @@ set_property -dict {LOC G29 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk2 create_clock -period 3.750 -name clk_ddr4_refclk2 [get_ports clk_ddr4_refclk2_p] # DDR ref clock sharing -set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {name =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1 && name =~*ddr4_c2_inst*}] -set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {name =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1 && name =~*ddr4_c3_inst*}] +set_property -quiet CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -quiet -hier -filter {name =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1 && name =~*ddr4_c2_inst*}] +set_property -quiet CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -quiet -hier -filter {name =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1 && name =~*ddr4_c3_inst*}] # LEDs set_property -dict {LOC C4 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports led_sreg_d] diff --git a/fpga/mqnic/fb2CG/fpga_25g/fpga.xdc b/fpga/mqnic/fb2CG/fpga_25g/fpga.xdc index af9b8f811..41d3309e0 100644 --- a/fpga/mqnic/fb2CG/fpga_25g/fpga.xdc +++ b/fpga/mqnic/fb2CG/fpga_25g/fpga.xdc @@ -28,8 +28,8 @@ set_property -dict {LOC AU32 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk1 create_clock -period 3.750 -name clk_ddr4_refclk1 [get_ports clk_ddr4_refclk1_p] # DDR ref clock sharing -set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {name =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1 && name =~*ddr4_c0_inst*}] -set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {name =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1 && name =~*ddr4_c1_inst*}] +set_property -quiet CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -quiet -hier -filter {name =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1 && name =~*ddr4_c0_inst*}] +set_property -quiet CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -quiet -hier -filter {name =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1 && name =~*ddr4_c1_inst*}] # DDR4 refclk2 set_property -dict {LOC G28 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk2_p] @@ -37,8 +37,8 @@ set_property -dict {LOC G29 IOSTANDARD DIFF_SSTL12} [get_ports clk_ddr4_refclk2 create_clock -period 3.750 -name clk_ddr4_refclk2 [get_ports clk_ddr4_refclk2_p] # DDR ref clock sharing -set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {name =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1 && name =~*ddr4_c2_inst*}] -set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {name =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1 && name =~*ddr4_c3_inst*}] +set_property -quiet CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -quiet -hier -filter {name =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1 && name =~*ddr4_c2_inst*}] +set_property -quiet CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -quiet -hier -filter {name =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1 && name =~*ddr4_c3_inst*}] # LEDs set_property -dict {LOC C4 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4} [get_ports led_sreg_d]