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Add AXI frame fifo and testbench
This commit is contained in:
Alex Forencich
parent
b232a6459d
commit
6fa46b6c57
138
rtl/axis_frame_fifo.v
Normal file
138
rtl/axis_frame_fifo.v
Normal file
@ -0,0 +1,138 @@
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/*
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Copyright (c) 2014 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
|
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of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4-Stream frame FIFO
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*/
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module axis_frame_fifo #
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(
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parameter ADDR_WIDTH = 12,
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parameter DATA_WIDTH = 8
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI input
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*/
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input wire [DATA_WIDTH-1:0] input_axis_tdata,
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input wire input_axis_tvalid,
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output wire input_axis_tready,
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input wire input_axis_tlast,
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input wire input_axis_tuser,
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/*
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* AXI output
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*/
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output wire [DATA_WIDTH-1:0] output_axis_tdata,
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output wire output_axis_tvalid,
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input wire output_axis_tready,
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output wire output_axis_tlast
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);
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reg [ADDR_WIDTH:0] wr_ptr = {ADDR_WIDTH+1{1'b0}};
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reg [ADDR_WIDTH:0] wr_ptr_cur = {ADDR_WIDTH+1{1'b0}};
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reg [ADDR_WIDTH:0] rd_ptr = {ADDR_WIDTH+1{1'b0}};
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reg [DATA_WIDTH+2-1:0] data_out_reg = {1'b0, {DATA_WIDTH{1'b0}}};
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//(* RAM_STYLE="BLOCK" *)
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reg [DATA_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0];
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reg output_read = 1'b0;
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reg output_axis_tvalid_reg = 1'b0;
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wire [DATA_WIDTH+2-1:0] data_in = {input_axis_tlast, input_axis_tdata};
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// full when first MSB different but rest same
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wire full = ((wr_ptr[ADDR_WIDTH] != rd_ptr[ADDR_WIDTH]) &&
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(wr_ptr[ADDR_WIDTH-1:0] == rd_ptr[ADDR_WIDTH-1:0]));
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// empty when pointers match exactly
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wire empty = wr_ptr == rd_ptr;
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// overflow in single packet
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wire full_cur = ((wr_ptr[ADDR_WIDTH] != wr_ptr_cur[ADDR_WIDTH]) &&
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(wr_ptr[ADDR_WIDTH-1:0] == wr_ptr_cur[ADDR_WIDTH-1:0]));
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wire write = input_axis_tvalid & ~full;
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wire read = (output_axis_tready | ~output_axis_tvalid_reg) & ~empty;
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assign {output_axis_tlast, output_axis_tdata} = data_out_reg;
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assign input_axis_tready = ~full;
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assign output_axis_tvalid = output_axis_tvalid_reg;
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// write
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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wr_ptr <= 0;
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end else if (write) begin
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if (full_cur) begin
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// buffer full, hold current pointer, drop packet at end
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if (input_axis_tlast) begin
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wr_ptr_cur <= wr_ptr;
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end
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end else begin
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mem[wr_ptr_cur[ADDR_WIDTH-1:0]] <= data_in;
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wr_ptr_cur <= wr_ptr_cur + 1;
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if (input_axis_tlast) begin
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if (input_axis_tuser) begin
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// bad packet, reset write pointer
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wr_ptr_cur <= wr_ptr;
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end else begin
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// good packet, push new write pointer
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wr_ptr <= wr_ptr_cur + 1;
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end
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end
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end
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end
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end
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// read
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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rd_ptr <= 0;
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end else if (read) begin
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data_out_reg <= mem[rd_ptr[ADDR_WIDTH-1:0]];
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rd_ptr <= rd_ptr + 1;
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end
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end
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// source ready output
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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output_axis_tvalid_reg <= 1'b0;
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end else if (output_axis_tready | ~output_axis_tvalid_reg) begin
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output_axis_tvalid_reg <= ~empty;
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end else begin
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output_axis_tvalid_reg <= output_axis_tvalid_reg;
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end
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end
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endmodule
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141
rtl/axis_frame_fifo_64.v
Normal file
141
rtl/axis_frame_fifo_64.v
Normal file
@ -0,0 +1,141 @@
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/*
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Copyright (c) 2014 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`timescale 1ns / 1ps
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/*
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* AXI4-Stream frame FIFO (64 bit datapath)
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*/
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module axis_frame_fifo_64 #
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(
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parameter ADDR_WIDTH = 12,
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parameter DATA_WIDTH = 64,
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parameter KEEP_WIDTH = (DATA_WIDTH/8)
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI input
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*/
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input wire [DATA_WIDTH-1:0] input_axis_tdata,
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input wire [KEEP_WIDTH-1:0] input_axis_tkeep,
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input wire input_axis_tvalid,
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output wire input_axis_tready,
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input wire input_axis_tlast,
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input wire input_axis_tuser,
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/*
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* AXI output
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*/
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output wire [DATA_WIDTH-1:0] output_axis_tdata,
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output wire [KEEP_WIDTH-1:0] output_axis_tkeep,
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output wire output_axis_tvalid,
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input wire output_axis_tready,
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output wire output_axis_tlast
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);
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reg [ADDR_WIDTH:0] wr_ptr = {ADDR_WIDTH+1{1'b0}};
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reg [ADDR_WIDTH:0] wr_ptr_cur = {ADDR_WIDTH+1{1'b0}};
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reg [ADDR_WIDTH:0] rd_ptr = {ADDR_WIDTH+1{1'b0}};
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reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] data_out_reg = {1'b0, {KEEP_WIDTH{1'b0}}, {DATA_WIDTH{1'b0}}};
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//(* RAM_STYLE="BLOCK" *)
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reg [DATA_WIDTH+KEEP_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0];
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reg output_read = 1'b0;
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reg output_axis_tvalid_reg = 1'b0;
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wire [DATA_WIDTH+KEEP_WIDTH+2-1:0] data_in = {input_axis_tlast, input_axis_tkeep, input_axis_tdata};
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// full when first MSB different but rest same
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wire full = ((wr_ptr[ADDR_WIDTH] != rd_ptr[ADDR_WIDTH]) &&
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(wr_ptr[ADDR_WIDTH-1:0] == rd_ptr[ADDR_WIDTH-1:0]));
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// empty when pointers match exactly
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wire empty = wr_ptr == rd_ptr;
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// overflow in single packet
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wire full_cur = ((wr_ptr[ADDR_WIDTH] != wr_ptr_cur[ADDR_WIDTH]) &&
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(wr_ptr[ADDR_WIDTH-1:0] == wr_ptr_cur[ADDR_WIDTH-1:0]));
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wire write = input_axis_tvalid & ~full;
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wire read = (output_axis_tready | ~output_axis_tvalid_reg) & ~empty;
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assign {output_axis_tlast, output_axis_tkeep, output_axis_tdata} = data_out_reg;
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assign input_axis_tready = ~full;
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assign output_axis_tvalid = output_axis_tvalid_reg;
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// write
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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wr_ptr <= 0;
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end else if (write) begin
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if (full_cur) begin
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// buffer full, hold current pointer, drop packet at end
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if (input_axis_tlast) begin
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wr_ptr_cur <= wr_ptr;
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end
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end else begin
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mem[wr_ptr_cur[ADDR_WIDTH-1:0]] <= data_in;
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wr_ptr_cur <= wr_ptr_cur + 1;
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if (input_axis_tlast) begin
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if (input_axis_tuser) begin
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// bad packet, reset write pointer
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wr_ptr_cur <= wr_ptr;
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end else begin
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// good packet, push new write pointer
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wr_ptr <= wr_ptr_cur + 1;
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end
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end
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end
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end
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end
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// read
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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rd_ptr <= 0;
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end else if (read) begin
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data_out_reg <= mem[rd_ptr[ADDR_WIDTH-1:0]];
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rd_ptr <= rd_ptr + 1;
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end
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end
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// source ready output
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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output_axis_tvalid_reg <= 1'b0;
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end else if (output_axis_tready | ~output_axis_tvalid_reg) begin
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output_axis_tvalid_reg <= ~empty;
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end else begin
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output_axis_tvalid_reg <= output_axis_tvalid_reg;
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end
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end
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endmodule
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401
tb/test_axis_frame_fifo.py
Executable file
401
tb/test_axis_frame_fifo.py
Executable file
@ -0,0 +1,401 @@
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#!/usr/bin/env python2
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"""
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Copyright (c) 2014 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
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THE SOFTWARE.
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"""
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from myhdl import *
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import os
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from Queue import Queue
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import axis_ep
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module = 'axis_frame_fifo'
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srcs = []
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srcs.append("../rtl/%s.v" % module)
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srcs.append("test_%s.v" % module)
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src = ' '.join(srcs)
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build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
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def dut_axis_frame_fifo(clk,
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rst,
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current_test,
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input_axis_tdata,
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input_axis_tvalid,
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input_axis_tready,
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input_axis_tlast,
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input_axis_tuser,
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output_axis_tdata,
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output_axis_tvalid,
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output_axis_tready,
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output_axis_tlast):
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if os.system(build_cmd):
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raise Exception("Error running build command")
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return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
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clk=clk,
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rst=rst,
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current_test=current_test,
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input_axis_tdata=input_axis_tdata,
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input_axis_tvalid=input_axis_tvalid,
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input_axis_tready=input_axis_tready,
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input_axis_tlast=input_axis_tlast,
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input_axis_tuser=input_axis_tuser,
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output_axis_tdata=output_axis_tdata,
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output_axis_tvalid=output_axis_tvalid,
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output_axis_tready=output_axis_tready,
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output_axis_tlast=output_axis_tlast)
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def bench():
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# Inputs
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clk = Signal(bool(0))
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rst = Signal(bool(0))
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current_test = Signal(intbv(0)[8:])
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input_axis_tdata = Signal(intbv(0)[8:])
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input_axis_tvalid = Signal(bool(0))
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input_axis_tlast = Signal(bool(0))
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input_axis_tuser = Signal(bool(0))
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output_axis_tready = Signal(bool(0))
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# Outputs
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input_axis_tready = Signal(bool(0))
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output_axis_tdata = Signal(intbv(0)[8:])
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output_axis_tvalid = Signal(bool(0))
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output_axis_tlast = Signal(bool(0))
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# sources and sinks
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source_queue = Queue()
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source_pause = Signal(bool(0))
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sink_queue = Queue()
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sink_pause = Signal(bool(0))
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source = axis_ep.AXIStreamSource(clk,
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rst,
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tdata=input_axis_tdata,
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tvalid=input_axis_tvalid,
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tready=input_axis_tready,
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tlast=input_axis_tlast,
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tuser=input_axis_tuser,
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fifo=source_queue,
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pause=source_pause,
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name='source')
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sink = axis_ep.AXIStreamSink(clk,
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rst,
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tdata=output_axis_tdata,
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tvalid=output_axis_tvalid,
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tready=output_axis_tready,
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tlast=output_axis_tlast,
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fifo=sink_queue,
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pause=sink_pause,
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name='sink')
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# DUT
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dut = dut_axis_frame_fifo(clk,
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rst,
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current_test,
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input_axis_tdata,
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input_axis_tvalid,
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input_axis_tready,
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input_axis_tlast,
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input_axis_tuser,
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output_axis_tdata,
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output_axis_tvalid,
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output_axis_tready,
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output_axis_tlast)
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@always(delay(4))
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def clkgen():
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clk.next = not clk
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@instance
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def check():
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yield delay(100)
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yield clk.posedge
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rst.next = 1
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yield clk.posedge
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rst.next = 0
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yield clk.posedge
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yield delay(100)
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yield clk.posedge
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yield clk.posedge
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yield clk.posedge
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print("test 1: test packet")
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current_test.next = 1
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test_frame = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
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'\x5A\x51\x52\x53\x54\x55' +
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'\x80\x00' +
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'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
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source_queue.put(test_frame)
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yield clk.posedge
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yield output_axis_tlast.posedge
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yield clk.posedge
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yield clk.posedge
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rx_frame = None
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if not sink_queue.empty():
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rx_frame = sink_queue.get()
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assert rx_frame == test_frame
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yield delay(100)
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yield clk.posedge
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print("test 2: longer packet")
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current_test.next = 2
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test_frame = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
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'\x5A\x51\x52\x53\x54\x55' +
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'\x80\x00' +
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bytearray(range(256)))
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source_queue.put(test_frame)
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yield clk.posedge
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yield output_axis_tlast.posedge
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yield clk.posedge
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yield clk.posedge
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rx_frame = None
|
||||
if not sink_queue.empty():
|
||||
rx_frame = sink_queue.get()
|
||||
|
||||
assert rx_frame == test_frame
|
||||
|
||||
yield clk.posedge
|
||||
print("test 3: test packet with pauses")
|
||||
current_test.next = 3
|
||||
|
||||
test_frame = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
'\x5A\x51\x52\x53\x54\x55' +
|
||||
'\x80\x00' +
|
||||
'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
source_queue.put(test_frame)
|
||||
yield clk.posedge
|
||||
|
||||
yield delay(64)
|
||||
yield clk.posedge
|
||||
source_pause.next = True
|
||||
yield delay(32)
|
||||
yield clk.posedge
|
||||
source_pause.next = False
|
||||
|
||||
yield delay(64)
|
||||
yield clk.posedge
|
||||
sink_pause.next = True
|
||||
yield delay(32)
|
||||
yield clk.posedge
|
||||
sink_pause.next = False
|
||||
|
||||
yield output_axis_tlast.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
rx_frame = None
|
||||
if not sink_queue.empty():
|
||||
rx_frame = sink_queue.get()
|
||||
|
||||
assert rx_frame == test_frame
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 4: back-to-back packets")
|
||||
current_test.next = 4
|
||||
|
||||
test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
'\x5A\x51\x52\x53\x54\x55' +
|
||||
'\x80\x00' +
|
||||
'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
'\x5A\x51\x52\x53\x54\x55' +
|
||||
'\x80\x00' +
|
||||
'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
source_queue.put(test_frame1)
|
||||
source_queue.put(test_frame2)
|
||||
yield clk.posedge
|
||||
|
||||
yield output_axis_tlast.posedge
|
||||
yield clk.posedge
|
||||
yield output_axis_tlast.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
rx_frame = None
|
||||
if not sink_queue.empty():
|
||||
rx_frame = sink_queue.get()
|
||||
|
||||
assert rx_frame == test_frame1
|
||||
|
||||
rx_frame = None
|
||||
if not sink_queue.empty():
|
||||
rx_frame = sink_queue.get()
|
||||
|
||||
assert rx_frame == test_frame2
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 5: alternate pause source")
|
||||
current_test.next = 5
|
||||
|
||||
test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
'\x5A\x51\x52\x53\x54\x55' +
|
||||
'\x80\x00' +
|
||||
'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
'\x5A\x51\x52\x53\x54\x55' +
|
||||
'\x80\x00' +
|
||||
'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
source_queue.put(test_frame1)
|
||||
source_queue.put(test_frame2)
|
||||
yield clk.posedge
|
||||
|
||||
while input_axis_tvalid or output_axis_tvalid:
|
||||
source_pause.next = True
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
source_pause.next = False
|
||||
yield clk.posedge
|
||||
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
rx_frame = None
|
||||
if not sink_queue.empty():
|
||||
rx_frame = sink_queue.get()
|
||||
|
||||
assert rx_frame == test_frame1
|
||||
|
||||
rx_frame = None
|
||||
if not sink_queue.empty():
|
||||
rx_frame = sink_queue.get()
|
||||
|
||||
assert rx_frame == test_frame2
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 6: alternate pause sink")
|
||||
current_test.next = 6
|
||||
|
||||
test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
'\x5A\x51\x52\x53\x54\x55' +
|
||||
'\x80\x00' +
|
||||
'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
'\x5A\x51\x52\x53\x54\x55' +
|
||||
'\x80\x00' +
|
||||
'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
source_queue.put(test_frame1)
|
||||
source_queue.put(test_frame2)
|
||||
yield clk.posedge
|
||||
|
||||
while input_axis_tvalid or output_axis_tvalid:
|
||||
sink_pause.next = True
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
sink_pause.next = False
|
||||
yield clk.posedge
|
||||
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
rx_frame = None
|
||||
if not sink_queue.empty():
|
||||
rx_frame = sink_queue.get()
|
||||
|
||||
assert rx_frame == test_frame1
|
||||
|
||||
rx_frame = None
|
||||
if not sink_queue.empty():
|
||||
rx_frame = sink_queue.get()
|
||||
|
||||
assert rx_frame == test_frame2
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 7: tuser assert")
|
||||
current_test.next = 7
|
||||
|
||||
test_frame = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
'\x5A\x51\x52\x53\x54\x55' +
|
||||
'\x80\x00' +
|
||||
'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame.user = 1
|
||||
source_queue.put(test_frame)
|
||||
yield clk.posedge
|
||||
|
||||
yield delay(1000)
|
||||
|
||||
assert sink_queue.empty()
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 8: single packet overflow")
|
||||
current_test.next = 8
|
||||
|
||||
test_frame = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
'\x5A\x51\x52\x53\x54\x55' +
|
||||
'\x80\x00' +
|
||||
bytearray(range(256))*2)
|
||||
source_queue.put(test_frame)
|
||||
yield clk.posedge
|
||||
|
||||
yield delay(10000)
|
||||
|
||||
assert sink_queue.empty()
|
||||
|
||||
yield delay(100)
|
||||
|
||||
raise StopSimulation
|
||||
|
||||
return dut, source, sink, clkgen, check
|
||||
|
||||
def test_bench():
|
||||
os.chdir(os.path.dirname(os.path.abspath(__file__)))
|
||||
sim = Simulation(bench())
|
||||
sim.run()
|
||||
|
||||
if __name__ == '__main__':
|
||||
print("Running test...")
|
||||
test_bench()
|
||||
|
||||
88
tb/test_axis_frame_fifo.v
Normal file
88
tb/test_axis_frame_fifo.v
Normal file
@ -0,0 +1,88 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`timescale 1 ns / 1 ps
|
||||
|
||||
module test_axis_frame_fifo;
|
||||
|
||||
// Inputs
|
||||
reg clk = 0;
|
||||
reg rst = 0;
|
||||
reg [7:0] current_test = 0;
|
||||
|
||||
reg [7:0] input_axis_tdata = 0;
|
||||
reg input_axis_tvalid = 0;
|
||||
reg input_axis_tlast = 0;
|
||||
reg input_axis_tuser = 0;
|
||||
reg output_axis_tready = 0;
|
||||
|
||||
// Outputs
|
||||
wire input_axis_tready;
|
||||
wire [7:0] output_axis_tdata;
|
||||
wire output_axis_tvalid;
|
||||
wire output_axis_tlast;
|
||||
|
||||
initial begin
|
||||
// myhdl integration
|
||||
$from_myhdl(clk,
|
||||
rst,
|
||||
current_test,
|
||||
input_axis_tdata,
|
||||
input_axis_tvalid,
|
||||
input_axis_tlast,
|
||||
input_axis_tuser,
|
||||
output_axis_tready);
|
||||
$to_myhdl(input_axis_tready,
|
||||
output_axis_tdata,
|
||||
output_axis_tvalid,
|
||||
output_axis_tlast);
|
||||
|
||||
// dump file
|
||||
$dumpfile("test_axis_frame_fifo.lxt");
|
||||
$dumpvars(0, test_axis_frame_fifo);
|
||||
end
|
||||
|
||||
axis_frame_fifo #(
|
||||
.ADDR_WIDTH(9),
|
||||
.DATA_WIDTH(8)
|
||||
)
|
||||
UUT (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
// AXI input
|
||||
.input_axis_tdata(input_axis_tdata),
|
||||
.input_axis_tvalid(input_axis_tvalid),
|
||||
.input_axis_tready(input_axis_tready),
|
||||
.input_axis_tlast(input_axis_tlast),
|
||||
.input_axis_tuser(input_axis_tuser),
|
||||
// AXI output
|
||||
.output_axis_tdata(output_axis_tdata),
|
||||
.output_axis_tvalid(output_axis_tvalid),
|
||||
.output_axis_tready(output_axis_tready),
|
||||
.output_axis_tlast(output_axis_tlast)
|
||||
);
|
||||
|
||||
endmodule
|
||||
414
tb/test_axis_frame_fifo_64.py
Executable file
414
tb/test_axis_frame_fifo_64.py
Executable file
@ -0,0 +1,414 @@
|
||||
#!/usr/bin/env python2
|
||||
"""
|
||||
|
||||
Copyright (c) 2014 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
"""
|
||||
|
||||
from myhdl import *
|
||||
import os
|
||||
from Queue import Queue
|
||||
|
||||
import axis_ep
|
||||
|
||||
module = 'axis_frame_fifo_64'
|
||||
|
||||
srcs = []
|
||||
|
||||
srcs.append("../rtl/%s.v" % module)
|
||||
srcs.append("test_%s.v" % module)
|
||||
|
||||
src = ' '.join(srcs)
|
||||
|
||||
build_cmd = "iverilog -o test_%s.vvp %s" % (module, src)
|
||||
|
||||
def dut_axis_frame_fifo_64(clk,
|
||||
rst,
|
||||
current_test,
|
||||
|
||||
input_axis_tdata,
|
||||
input_axis_tkeep,
|
||||
input_axis_tvalid,
|
||||
input_axis_tready,
|
||||
input_axis_tlast,
|
||||
input_axis_tuser,
|
||||
|
||||
output_axis_tdata,
|
||||
output_axis_tkeep,
|
||||
output_axis_tvalid,
|
||||
output_axis_tready,
|
||||
output_axis_tlast,
|
||||
output_axis_tuser):
|
||||
|
||||
if os.system(build_cmd):
|
||||
raise Exception("Error running build command")
|
||||
return Cosimulation("vvp -m myhdl test_%s.vvp -lxt2" % module,
|
||||
clk=clk,
|
||||
rst=rst,
|
||||
current_test=current_test,
|
||||
|
||||
input_axis_tdata=input_axis_tdata,
|
||||
input_axis_tkeep=input_axis_tkeep,
|
||||
input_axis_tvalid=input_axis_tvalid,
|
||||
input_axis_tready=input_axis_tready,
|
||||
input_axis_tlast=input_axis_tlast,
|
||||
input_axis_tuser=input_axis_tuser,
|
||||
|
||||
output_axis_tdata=output_axis_tdata,
|
||||
output_axis_tkeep=output_axis_tkeep,
|
||||
output_axis_tvalid=output_axis_tvalid,
|
||||
output_axis_tready=output_axis_tready,
|
||||
output_axis_tlast=output_axis_tlast,
|
||||
output_axis_tuser=output_axis_tuser)
|
||||
|
||||
def bench():
|
||||
|
||||
# Inputs
|
||||
clk = Signal(bool(0))
|
||||
rst = Signal(bool(0))
|
||||
current_test = Signal(intbv(0)[8:])
|
||||
|
||||
input_axis_tdata = Signal(intbv(0)[64:])
|
||||
input_axis_tkeep = Signal(intbv(0)[8:])
|
||||
input_axis_tvalid = Signal(bool(0))
|
||||
input_axis_tlast = Signal(bool(0))
|
||||
input_axis_tuser = Signal(bool(0))
|
||||
output_axis_tready = Signal(bool(0))
|
||||
|
||||
# Outputs
|
||||
input_axis_tready = Signal(bool(0))
|
||||
output_axis_tdata = Signal(intbv(0)[64:])
|
||||
output_axis_tkeep = Signal(intbv(0)[8:])
|
||||
output_axis_tvalid = Signal(bool(0))
|
||||
output_axis_tlast = Signal(bool(0))
|
||||
output_axis_tuser = Signal(bool(0))
|
||||
|
||||
# sources and sinks
|
||||
source_queue = Queue()
|
||||
source_pause = Signal(bool(0))
|
||||
sink_queue = Queue()
|
||||
sink_pause = Signal(bool(0))
|
||||
|
||||
source = axis_ep.AXIStreamSource(clk,
|
||||
rst,
|
||||
tdata=input_axis_tdata,
|
||||
tkeep=input_axis_tkeep,
|
||||
tvalid=input_axis_tvalid,
|
||||
tready=input_axis_tready,
|
||||
tlast=input_axis_tlast,
|
||||
tuser=input_axis_tuser,
|
||||
fifo=source_queue,
|
||||
pause=source_pause,
|
||||
name='source')
|
||||
|
||||
sink = axis_ep.AXIStreamSink(clk,
|
||||
rst,
|
||||
tdata=output_axis_tdata,
|
||||
tkeep=output_axis_tkeep,
|
||||
tvalid=output_axis_tvalid,
|
||||
tready=output_axis_tready,
|
||||
tlast=output_axis_tlast,
|
||||
tuser=output_axis_tuser,
|
||||
fifo=sink_queue,
|
||||
pause=sink_pause,
|
||||
name='sink')
|
||||
|
||||
# DUT
|
||||
dut = dut_axis_frame_fifo_64(clk,
|
||||
rst,
|
||||
current_test,
|
||||
|
||||
input_axis_tdata,
|
||||
input_axis_tkeep,
|
||||
input_axis_tvalid,
|
||||
input_axis_tready,
|
||||
input_axis_tlast,
|
||||
input_axis_tuser,
|
||||
|
||||
output_axis_tdata,
|
||||
output_axis_tkeep,
|
||||
output_axis_tvalid,
|
||||
output_axis_tready,
|
||||
output_axis_tlast,
|
||||
output_axis_tuser)
|
||||
|
||||
@always(delay(4))
|
||||
def clkgen():
|
||||
clk.next = not clk
|
||||
|
||||
@instance
|
||||
def check():
|
||||
yield delay(100)
|
||||
yield clk.posedge
|
||||
rst.next = 1
|
||||
yield clk.posedge
|
||||
rst.next = 0
|
||||
yield clk.posedge
|
||||
yield delay(100)
|
||||
yield clk.posedge
|
||||
|
||||
yield clk.posedge
|
||||
|
||||
yield clk.posedge
|
||||
print("test 1: test packet")
|
||||
current_test.next = 1
|
||||
|
||||
test_frame = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
'\x5A\x51\x52\x53\x54\x55' +
|
||||
'\x80\x00' +
|
||||
'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
source_queue.put(test_frame)
|
||||
yield clk.posedge
|
||||
|
||||
yield output_axis_tlast.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
rx_frame = None
|
||||
if not sink_queue.empty():
|
||||
rx_frame = sink_queue.get()
|
||||
|
||||
assert rx_frame == test_frame
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 2: longer packet")
|
||||
current_test.next = 2
|
||||
|
||||
test_frame = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
'\x5A\x51\x52\x53\x54\x55' +
|
||||
'\x80\x00' +
|
||||
bytearray(range(256)))
|
||||
source_queue.put(test_frame)
|
||||
yield clk.posedge
|
||||
|
||||
yield output_axis_tlast.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
rx_frame = None
|
||||
if not sink_queue.empty():
|
||||
rx_frame = sink_queue.get()
|
||||
|
||||
assert rx_frame == test_frame
|
||||
|
||||
yield clk.posedge
|
||||
print("test 3: test packet with pauses")
|
||||
current_test.next = 3
|
||||
|
||||
test_frame = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
'\x5A\x51\x52\x53\x54\x55' +
|
||||
'\x80\x00' +
|
||||
bytearray(range(256)))
|
||||
source_queue.put(test_frame)
|
||||
yield clk.posedge
|
||||
|
||||
yield delay(64)
|
||||
yield clk.posedge
|
||||
source_pause.next = True
|
||||
yield delay(32)
|
||||
yield clk.posedge
|
||||
source_pause.next = False
|
||||
|
||||
yield delay(64)
|
||||
yield clk.posedge
|
||||
sink_pause.next = True
|
||||
yield delay(32)
|
||||
yield clk.posedge
|
||||
sink_pause.next = False
|
||||
|
||||
yield output_axis_tlast.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
rx_frame = None
|
||||
if not sink_queue.empty():
|
||||
rx_frame = sink_queue.get()
|
||||
|
||||
assert rx_frame == test_frame
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 4: back-to-back packets")
|
||||
current_test.next = 4
|
||||
|
||||
test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
'\x5A\x51\x52\x53\x54\x55' +
|
||||
'\x80\x00' +
|
||||
'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
'\x5A\x51\x52\x53\x54\x55' +
|
||||
'\x80\x00' +
|
||||
'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
source_queue.put(test_frame1)
|
||||
source_queue.put(test_frame2)
|
||||
yield clk.posedge
|
||||
|
||||
yield output_axis_tlast.posedge
|
||||
yield clk.posedge
|
||||
yield output_axis_tlast.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
rx_frame = None
|
||||
if not sink_queue.empty():
|
||||
rx_frame = sink_queue.get()
|
||||
|
||||
assert rx_frame == test_frame1
|
||||
|
||||
rx_frame = None
|
||||
if not sink_queue.empty():
|
||||
rx_frame = sink_queue.get()
|
||||
|
||||
assert rx_frame == test_frame2
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 5: alternate pause source")
|
||||
current_test.next = 5
|
||||
|
||||
test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
'\x5A\x51\x52\x53\x54\x55' +
|
||||
'\x80\x00' +
|
||||
'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
'\x5A\x51\x52\x53\x54\x55' +
|
||||
'\x80\x00' +
|
||||
'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
source_queue.put(test_frame1)
|
||||
source_queue.put(test_frame2)
|
||||
yield clk.posedge
|
||||
|
||||
while input_axis_tvalid or output_axis_tvalid:
|
||||
source_pause.next = True
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
source_pause.next = False
|
||||
yield clk.posedge
|
||||
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
rx_frame = None
|
||||
if not sink_queue.empty():
|
||||
rx_frame = sink_queue.get()
|
||||
|
||||
assert rx_frame == test_frame1
|
||||
|
||||
rx_frame = None
|
||||
if not sink_queue.empty():
|
||||
rx_frame = sink_queue.get()
|
||||
|
||||
assert rx_frame == test_frame2
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 6: alternate pause sink")
|
||||
current_test.next = 6
|
||||
|
||||
test_frame1 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
'\x5A\x51\x52\x53\x54\x55' +
|
||||
'\x80\x00' +
|
||||
'\x01\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame2 = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
'\x5A\x51\x52\x53\x54\x55' +
|
||||
'\x80\x00' +
|
||||
'\x02\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
source_queue.put(test_frame1)
|
||||
source_queue.put(test_frame2)
|
||||
yield clk.posedge
|
||||
|
||||
while input_axis_tvalid or output_axis_tvalid:
|
||||
sink_pause.next = True
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
sink_pause.next = False
|
||||
yield clk.posedge
|
||||
|
||||
yield clk.posedge
|
||||
yield clk.posedge
|
||||
|
||||
rx_frame = None
|
||||
if not sink_queue.empty():
|
||||
rx_frame = sink_queue.get()
|
||||
|
||||
assert rx_frame == test_frame1
|
||||
|
||||
rx_frame = None
|
||||
if not sink_queue.empty():
|
||||
rx_frame = sink_queue.get()
|
||||
|
||||
assert rx_frame == test_frame2
|
||||
|
||||
yield delay(100)
|
||||
|
||||
yield clk.posedge
|
||||
print("test 7: tuser assert")
|
||||
current_test.next = 7
|
||||
|
||||
test_frame = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
'\x5A\x51\x52\x53\x54\x55' +
|
||||
'\x80\x00' +
|
||||
'\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0a\x0b\x0c\x0d\x0e\x0f\x10')
|
||||
test_frame.user = 1
|
||||
source_queue.put(test_frame)
|
||||
yield clk.posedge
|
||||
|
||||
yield delay(1000)
|
||||
|
||||
assert sink_queue.empty()
|
||||
|
||||
yield clk.posedge
|
||||
print("test 8: single packet overflow")
|
||||
current_test.next = 8
|
||||
|
||||
test_frame = axis_ep.AXIStreamFrame('\xDA\xD1\xD2\xD3\xD4\xD5' +
|
||||
'\x5A\x51\x52\x53\x54\x55' +
|
||||
'\x80\x00' +
|
||||
bytearray(range(256))*2)
|
||||
source_queue.put(test_frame)
|
||||
yield clk.posedge
|
||||
|
||||
yield delay(10000)
|
||||
|
||||
assert sink_queue.empty()
|
||||
|
||||
yield delay(100)
|
||||
|
||||
raise StopSimulation
|
||||
|
||||
return dut, source, sink, clkgen, check
|
||||
|
||||
def test_bench():
|
||||
os.chdir(os.path.dirname(os.path.abspath(__file__)))
|
||||
sim = Simulation(bench())
|
||||
sim.run()
|
||||
|
||||
if __name__ == '__main__':
|
||||
print("Running test...")
|
||||
test_bench()
|
||||
|
||||
94
tb/test_axis_frame_fifo_64.v
Normal file
94
tb/test_axis_frame_fifo_64.v
Normal file
@ -0,0 +1,94 @@
|
||||
/*
|
||||
|
||||
Copyright (c) 2014 Alex Forencich
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
|
||||
*/
|
||||
|
||||
// Language: Verilog 2001
|
||||
|
||||
`timescale 1 ns / 1 ps
|
||||
|
||||
module test_axis_frame_fifo_64;
|
||||
|
||||
// Inputs
|
||||
reg clk = 0;
|
||||
reg rst = 0;
|
||||
reg [7:0] current_test = 0;
|
||||
|
||||
reg [63:0] input_axis_tdata = 0;
|
||||
reg [7:0] input_axis_tkeep = 0;
|
||||
reg input_axis_tvalid = 0;
|
||||
reg input_axis_tlast = 0;
|
||||
reg input_axis_tuser = 0;
|
||||
reg output_axis_tready = 0;
|
||||
|
||||
// Outputs
|
||||
wire input_axis_tready;
|
||||
wire [63:0] output_axis_tdata;
|
||||
wire [7:0] output_axis_tkeep;
|
||||
wire output_axis_tvalid;
|
||||
wire output_axis_tlast;
|
||||
|
||||
initial begin
|
||||
// myhdl integration
|
||||
$from_myhdl(clk,
|
||||
rst,
|
||||
current_test,
|
||||
input_axis_tdata,
|
||||
input_axis_tkeep,
|
||||
input_axis_tvalid,
|
||||
input_axis_tlast,
|
||||
input_axis_tuser,
|
||||
output_axis_tready);
|
||||
$to_myhdl(input_axis_tready,
|
||||
output_axis_tdata,
|
||||
output_axis_tkeep,
|
||||
output_axis_tvalid,
|
||||
output_axis_tlast);
|
||||
|
||||
// dump file
|
||||
$dumpfile("test_axis_frame_fifo_64.lxt");
|
||||
$dumpvars(0, test_axis_frame_fifo_64);
|
||||
end
|
||||
|
||||
axis_frame_fifo_64 #(
|
||||
.ADDR_WIDTH(6),
|
||||
.DATA_WIDTH(64)
|
||||
)
|
||||
UUT (
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
// AXI input
|
||||
.input_axis_tdata(input_axis_tdata),
|
||||
.input_axis_tkeep(input_axis_tkeep),
|
||||
.input_axis_tvalid(input_axis_tvalid),
|
||||
.input_axis_tready(input_axis_tready),
|
||||
.input_axis_tlast(input_axis_tlast),
|
||||
.input_axis_tuser(input_axis_tuser),
|
||||
// AXI output
|
||||
.output_axis_tdata(output_axis_tdata),
|
||||
.output_axis_tkeep(output_axis_tkeep),
|
||||
.output_axis_tvalid(output_axis_tvalid),
|
||||
.output_axis_tready(output_axis_tready),
|
||||
.output_axis_tlast(output_axis_tlast)
|
||||
);
|
||||
|
||||
endmodule
|
||||
Loading…
x
Reference in New Issue
Block a user